From: rtel Date: Thu, 23 Aug 2018 00:00:20 +0000 (+0000) Subject: FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, X-Git-Tag: V10.1.0 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=321fc5f860a6aa5763eae06e40cecae1bd1e9a33;p=freertos FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches applied to FreeRTOS+TCP. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2565 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/ReadMe.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/ReadMe.txt new file mode 100644 index 000000000..24bb5461e --- /dev/null +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/ReadMe.txt @@ -0,0 +1,4 @@ +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/Read_Me_Instructions.url b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/Read_Me_Instructions.url deleted file mode 100644 index 86d28f180..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/Read_Me_Instructions.url +++ /dev/null @@ -1,5 +0,0 @@ -[InternetShortcut] -URL=http://www.freertos.org/Atmel_SAM4E_RTOS_Demo.html -IDList= -[{000214A0-0000-0000-C000-000000000046}] -Prop3=19,2 diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject deleted file mode 100644 index b97ce71fc..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject +++ /dev/null @@ -1,233 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - <?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_2="LPC1850A_4350A_SPIFI.cfx" property_3="NXP" property_4="LPC1830" property_count="5" version="70200"/> -<infoList vendor="NXP"><info chip="LPC1830" match_id="0x0" name="LPC1830" resetscript="LPC18LPC43ExternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"><chip><name>LPC1830</name> -<family>LPC18xx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" edited="true" id="SPIFlash" location="0x14000000" size="0x400000"/> -<memoryInstance derived_from="RAM" edited="true" id="RamLoc96" location="0x10000000" size="0x18000"/> -<memoryInstance derived_from="RAM" edited="true" id="RamLoc40" location="0x10080000" size="0xa000"/> -<memoryInstance derived_from="RAM" edited="true" id="RamAHB32" location="0x20000000" size="0x8000"/> -<memoryInstance derived_from="RAM" edited="true" id="RamAHB16" location="0x20008000" size="0x4000"/> -<memoryInstance derived_from="RAM" edited="true" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/> -<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/> -<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/> -<peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/> -<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/> -<peripheralInstance derived_from="SPIFI" id="SPIFI" location="0x40003000"/> -<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/> -<peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/> -<peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/> -<peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/> -<peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x4000e000"/> -<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/> -<peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/> -<peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/> -<peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/> -<peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/> -<peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/> -<peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/> -<peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/> -<peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/> -<peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/> -<peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/> -<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/> -<peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/> -<peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/> -<peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/> -<peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/> -<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/> -<peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/> -<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/> -<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/> -<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/> -<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/> -<peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/> -<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/> -<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/> -<peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/> -<peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/> -<peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/> -<peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/> -<peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/> -<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/> -<peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/> -<peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/> -<peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/> -<peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/> -<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/> -<peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/> -<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/> -</chip> -<processor><name gcc_name="cortex-m3">Cortex-M3</name> -<family>Cortex-M</family> -</processor> -<link href="nxp_lpc18xx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig> - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project deleted file mode 100644 index aa42a5e72..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project +++ /dev/null @@ -1,26 +0,0 @@ - - - FreeRTOS_UDP_Demo - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.cdt.codan.core.prefs b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.cdt.codan.core.prefs deleted file mode 100644 index 733f315b0..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.cdt.codan.core.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -useParentScope=false diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.ltk.core.refactoring.prefs b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.ltk.core.refactoring.prefs deleted file mode 100644 index cfcd1d3c2..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.ltk.core.refactoring.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CLI-commands.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CLI-commands.c deleted file mode 100644 index 7df058825..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CLI-commands.c +++ /dev/null @@ -1,664 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - /****************************************************************************** - * - * See the following URL for information on the commands defined in this file: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml - * - ******************************************************************************/ - - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Standard includes. */ -#include -#include -#include - -/* FreeRTOS+CLI includes. */ -#include "FreeRTOS_CLI.h" - -/* FreeRTOS+UDP includes, just to make the stats available to the CLI -commands. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_Sockets.h" - -#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS - #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0 -#endif - - -/* - * Implements the run-time-stats command. - */ -static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); - -/* - * Implements the task-stats command. - */ -static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); - -/* - * Implements the echo-three-parameters command. - */ -static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); - -/* - * Implements the echo-parameters command. - */ -static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); - -/* - * Defines a command that prints out IP address information. - */ -static BaseType_t prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); - -/* - * Defines a command that prints out the gathered demo debug stats. - */ -static BaseType_t prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); - -/* - * Defines a command that sends an ICMP ping request to an IP address. - */ -static BaseType_t prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); - -/* - * Implements the "trace start" and "trace stop" commands; - */ -#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 - static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); -#endif - -/* Structure that defines the "ip-config" command line command. */ -static const CLI_Command_Definition_t xIPConfig = -{ - "ip-config", - "ip-config:\r\n Displays IP address configuration\r\n\r\n", - prvDisplayIPConfig, - 0 -}; - -#if configINCLUDE_DEMO_DEBUG_STATS != 0 - /* Structure that defines the "ip-debug-stats" command line command. */ - static const CLI_Command_Definition_t xIPDebugStats = - { - "ip-debug-stats", /* The command string to type. */ - "ip-debug-stats:\r\n Shows some IP stack stats useful for debug - an example only.\r\n\r\n", - prvDisplayIPDebugStats, /* The function to run. */ - 0 /* No parameters are expected. */ - }; -#endif /* configINCLUDE_DEMO_DEBUG_STATS */ - -/* Structure that defines the "run-time-stats" command line command. This -generates a table that shows how much run time each task has */ -static const CLI_Command_Definition_t xRunTimeStats = -{ - "run-time-stats", /* The command string to type. */ - "run-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n\r\n", - prvRunTimeStatsCommand, /* The function to run. */ - 0 /* No parameters are expected. */ -}; - -/* Structure that defines the "task-stats" command line command. This generates -a table that gives information on each task in the system. */ -static const CLI_Command_Definition_t xTaskStats = -{ - "task-stats", /* The command string to type. */ - "task-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n\r\n", - prvTaskStatsCommand, /* The function to run. */ - 0 /* No parameters are expected. */ -}; - -/* Structure that defines the "echo_3_parameters" command line command. This -takes exactly three parameters that the command simply echos back one at a -time. */ -static const CLI_Command_Definition_t xThreeParameterEcho = -{ - "echo-3-parameters", - "echo-3-parameters :\r\n Expects three parameters, echos each in turn\r\n\r\n", - prvThreeParameterEchoCommand, /* The function to run. */ - 3 /* Three parameters are expected, which can take any value. */ -}; - -/* Structure that defines the "echo_parameters" command line command. This -takes a variable number of parameters that the command simply echos back one at -a time. */ -static const CLI_Command_Definition_t xParameterEcho = -{ - "echo-parameters", - "echo-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n\r\n", - prvParameterEchoCommand, /* The function to run. */ - -1 /* The user can enter any number of commands. */ -}; - -#if ipconfigSUPPORT_OUTGOING_PINGS == 1 - - /* Structure that defines the "ping" command line command. This takes an IP - address or host name and (optionally) the number of bytes to ping as - parameters. */ - static const CLI_Command_Definition_t xPing = - { - "ping", - "ping :\r\n for example, ping 192.168.0.3 8, or ping www.example.com\r\n\r\n", - prvPingCommand, /* The function to run. */ - -1 /* Ping can take either one or two parameter, so the number of parameters has to be determined by the ping command implementation. */ - }; - -#endif /* ipconfigSUPPORT_OUTGOING_PINGS */ - -#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 - /* Structure that defines the "trace" command line command. This takes a single - parameter, which can be either "start" or "stop". */ - static const CLI_Command_Definition_t xStartStopTrace = - { - "trace", - "trace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n\r\n", - prvStartStopTraceCommand, /* The function to run. */ - 1 /* One parameter is expected. Valid values are "start" and "stop". */ - }; -#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */ - -/*-----------------------------------------------------------*/ - -void vRegisterCLICommands( void ) -{ - /* Register all the command line commands defined immediately above. */ - FreeRTOS_CLIRegisterCommand( &xTaskStats ); - FreeRTOS_CLIRegisterCommand( &xRunTimeStats ); - FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho ); - FreeRTOS_CLIRegisterCommand( &xParameterEcho ); - FreeRTOS_CLIRegisterCommand( &xIPDebugStats ); - FreeRTOS_CLIRegisterCommand( &xIPConfig ); - - #if ipconfigSUPPORT_OUTGOING_PINGS == 1 - { - FreeRTOS_CLIRegisterCommand( &xPing ); - } - #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ - - #if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 - FreeRTOS_CLIRegisterCommand( & xStartStopTrace ); - #endif -} -/*-----------------------------------------------------------*/ - -static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) -{ -const char *const pcHeader = " State\tPriority\tStack\t#\r\n************************************************\r\n"; -BaseType_t xSpacePadding; - - /* Remove compile time warnings about unused parameters, and check the - write buffer is not NULL. NOTE - for simplicity, this example assumes the - write buffer length is adequate, so does not check for buffer overflows. */ - ( void ) pcCommandString; - ( void ) xWriteBufferLen; - configASSERT( pcWriteBuffer ); - - /* Generate a table of task stats. */ - strcpy( pcWriteBuffer, "Task" ); - pcWriteBuffer += strlen( pcWriteBuffer ); - - /* Pad the string "task" with however many bytes necessary to make it the - length of a task name. Minus three for the null terminator and half the - number of characters in "Task" so the column lines up with the centre of - the heading. */ - for( xSpacePadding = strlen( "Task" ); xSpacePadding < ( configMAX_TASK_NAME_LEN - 3 ); xSpacePadding++ ) - { - /* Add a space to align columns after the task's name. */ - *pcWriteBuffer = ' '; - pcWriteBuffer++; - - /* Ensure always terminated. */ - *pcWriteBuffer = 0x00; - } - strcpy( pcWriteBuffer, pcHeader ); - vTaskList( pcWriteBuffer + strlen( pcHeader ) ); - - /* There is no more data to return after this single string, so return - pdFALSE. */ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) -{ -const char * const pcHeader = " Abs Time % Time\r\n****************************************\r\n"; -BaseType_t xSpacePadding; - - /* Remove compile time warnings about unused parameters, and check the - write buffer is not NULL. NOTE - for simplicity, this example assumes the - write buffer length is adequate, so does not check for buffer overflows. */ - ( void ) pcCommandString; - ( void ) xWriteBufferLen; - configASSERT( pcWriteBuffer ); - - /* Generate a table of task stats. */ - strcpy( pcWriteBuffer, "Task" ); - pcWriteBuffer += strlen( pcWriteBuffer ); - - /* Pad the string "task" with however many bytes necessary to make it the - length of a task name. Minus three for the null terminator and half the - number of characters in "Task" so the column lines up with the centre of - the heading. */ - for( xSpacePadding = strlen( "Task" ); xSpacePadding < ( configMAX_TASK_NAME_LEN - 3 ); xSpacePadding++ ) - { - /* Add a space to align columns after the task's name. */ - *pcWriteBuffer = ' '; - pcWriteBuffer++; - - /* Ensure always terminated. */ - *pcWriteBuffer = 0x00; - } - - strcpy( pcWriteBuffer, pcHeader ); - vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) ); - - /* There is no more data to return after this single string, so return - pdFALSE. */ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) -{ -const char *pcParameter; -BaseType_t xParameterStringLength, xReturn; -static BaseType_t lParameterNumber = 0; - - /* Remove compile time warnings about unused parameters, and check the - write buffer is not NULL. NOTE - for simplicity, this example assumes the - write buffer length is adequate, so does not check for buffer overflows. */ - ( void ) pcCommandString; - ( void ) xWriteBufferLen; - configASSERT( pcWriteBuffer ); - - if( lParameterNumber == 0 ) - { - /* The first time the function is called after the command has been - entered just a header string is returned. */ - sprintf( pcWriteBuffer, "The three parameters were:\r\n" ); - - /* Next time the function is called the first parameter will be echoed - back. */ - lParameterNumber = 1L; - - /* There is more data to be returned as no parameters have been echoed - back yet. */ - xReturn = pdPASS; - } - else - { - /* Obtain the parameter string. */ - pcParameter = FreeRTOS_CLIGetParameter - ( - pcCommandString, /* The command string itself. */ - lParameterNumber, /* Return the next parameter. */ - &xParameterStringLength /* Store the parameter string length. */ - ); - - /* Sanity check something was returned. */ - configASSERT( pcParameter ); - - /* Return the parameter string. */ - memset( pcWriteBuffer, 0x00, xWriteBufferLen ); - sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber ); - strncat( pcWriteBuffer, pcParameter, xParameterStringLength ); - strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); - - /* If this is the last of the three parameters then there are no more - strings to return after this one. */ - if( lParameterNumber == 3L ) - { - /* If this is the last of the three parameters then there are no more - strings to return after this one. */ - xReturn = pdFALSE; - lParameterNumber = 0L; - } - else - { - /* There are more parameters to return after this one. */ - xReturn = pdTRUE; - lParameterNumber++; - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) -{ -const char *pcParameter; -BaseType_t xParameterStringLength, xReturn; -static BaseType_t lParameterNumber = 0; - - /* Remove compile time warnings about unused parameters, and check the - write buffer is not NULL. NOTE - for simplicity, this example assumes the - write buffer length is adequate, so does not check for buffer overflows. */ - ( void ) pcCommandString; - ( void ) xWriteBufferLen; - configASSERT( pcWriteBuffer ); - - if( lParameterNumber == 0 ) - { - /* The first time the function is called after the command has been - entered just a header string is returned. */ - sprintf( pcWriteBuffer, "The parameters were:\r\n" ); - - /* Next time the function is called the first parameter will be echoed - back. */ - lParameterNumber = 1L; - - /* There is more data to be returned as no parameters have been echoed - back yet. */ - xReturn = pdPASS; - } - else - { - /* Obtain the parameter string. */ - pcParameter = FreeRTOS_CLIGetParameter - ( - pcCommandString, /* The command string itself. */ - lParameterNumber, /* Return the next parameter. */ - &xParameterStringLength /* Store the parameter string length. */ - ); - - if( pcParameter != NULL ) - { - /* Return the parameter string. */ - memset( pcWriteBuffer, 0x00, xWriteBufferLen ); - sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber ); - strncat( pcWriteBuffer, pcParameter, xParameterStringLength ); - strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); - - /* There might be more parameters to return after this one. */ - xReturn = pdTRUE; - lParameterNumber++; - } - else - { - /* No more parameters were found. Make sure the write buffer does - not contain a valid string. */ - pcWriteBuffer[ 0 ] = 0x00; - - /* No more data to return. */ - xReturn = pdFALSE; - - /* Start over the next time this command is executed. */ - lParameterNumber = 0; - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ipconfigSUPPORT_OUTGOING_PINGS == 1 - - static BaseType_t prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) - { - char * pcParameter; - BaseType_t lParameterStringLength, xReturn; - uint32_t ulIPAddress, ulBytesToPing; - const uint32_t ulDefaultBytesToPing = 8UL; - char cBuffer[ 16 ]; - - /* Remove compile time warnings about unused parameters, and check the - write buffer is not NULL. NOTE - for simplicity, this example assumes the - write buffer length is adequate, so does not check for buffer overflows. */ - ( void ) pcCommandString; - ( void ) xWriteBufferLen; - configASSERT( pcWriteBuffer ); - - /* Start with an empty string. */ - pcWriteBuffer[ 0 ] = 0x00; - - /* Obtain the number of bytes to ping. */ - pcParameter = ( char * ) FreeRTOS_CLIGetParameter - ( - pcCommandString, /* The command string itself. */ - 2, /* Return the second parameter. */ - &lParameterStringLength /* Store the parameter string length. */ - ); - - if( pcParameter == NULL ) - { - /* The number of bytes was not specified, so default it. */ - ulBytesToPing = ulDefaultBytesToPing; - } - else - { - ulBytesToPing = atol( pcParameter ); - } - - /* Obtain the IP address string. */ - pcParameter = ( char * ) FreeRTOS_CLIGetParameter - ( - pcCommandString, /* The command string itself. */ - 1, /* Return the first parameter. */ - &lParameterStringLength /* Store the parameter string length. */ - ); - - /* Sanity check something was returned. */ - configASSERT( pcParameter ); - - /* Attempt to obtain the IP address. If the first character is not a - digit, assume the host name has been passed in. */ - if( ( *pcParameter >= '0' ) && ( *pcParameter <= '9' ) ) - { - ulIPAddress = FreeRTOS_inet_addr( pcParameter ); - } - else - { - /* Terminate the host name. */ - pcParameter[ lParameterStringLength ] = 0x00; - - /* Attempt to resolve host. */ - ulIPAddress = FreeRTOS_gethostbyname( pcParameter ); - } - - /* Convert IP address, which may have come from a DNS lookup, to string. */ - FreeRTOS_inet_ntoa( ulIPAddress, cBuffer ); - - if( ulIPAddress != 0 ) - { - xReturn = FreeRTOS_SendPingRequest( ulIPAddress, ( uint16_t ) ulBytesToPing, portMAX_DELAY ); - } - else - { - xReturn = pdFALSE; - } - - if( xReturn == pdFALSE ) - { - sprintf( pcWriteBuffer, "%s", "Could not send ping request\r\n" ); - } - else - { - sprintf( pcWriteBuffer, "Ping sent to %s with identifier %d\r\n", cBuffer, xReturn ); - } - - return pdFALSE; - } - /*-----------------------------------------------------------*/ - -#endif /* ipconfigSUPPORT_OUTGOING_PINGS */ - -#if configINCLUDE_DEMO_DEBUG_STATS != 0 - - static BaseType_t prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) - { - static BaseType_t xIndex = -1; - extern xExampleDebugStatEntry_t xIPTraceValues[]; - BaseType_t xReturn; - - /* Remove compile time warnings about unused parameters, and check the - write buffer is not NULL. NOTE - for simplicity, this example assumes the - write buffer length is adequate, so does not check for buffer overflows. */ - ( void ) pcCommandString; - ( void ) xWriteBufferLen; - configASSERT( pcWriteBuffer ); - - xIndex++; - - if( xIndex < xExampleDebugStatEntries() ) - { - sprintf( pcWriteBuffer, "%s %d\r\n", xIPTraceValues[ xIndex ].pucDescription, ( int ) xIPTraceValues[ xIndex ].ulData ); - xReturn = pdPASS; - } - else - { - /* Reset the index for the next time it is called. */ - xIndex = -1; - - /* Ensure nothing remains in the write buffer. */ - pcWriteBuffer[ 0 ] = 0x00; - xReturn = pdFALSE; - } - - return xReturn; - } - /*-----------------------------------------------------------*/ - -#endif /* configINCLUDE_DEMO_DEBUG_STATS */ - -static BaseType_t prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) -{ -static BaseType_t xIndex = 0; -BaseType_t xReturn; -uint32_t ulAddress; - - /* Remove compile time warnings about unused parameters, and check the - write buffer is not NULL. NOTE - for simplicity, this example assumes the - write buffer length is adequate, so does not check for buffer overflows. */ - ( void ) pcCommandString; - ( void ) xWriteBufferLen; - configASSERT( pcWriteBuffer ); - - switch( xIndex ) - { - case 0 : - FreeRTOS_GetAddressConfiguration( &ulAddress, NULL, NULL, NULL ); - sprintf( pcWriteBuffer, "\r\nIP address " ); - xReturn = pdTRUE; - xIndex++; - break; - - case 1 : - FreeRTOS_GetAddressConfiguration( NULL, &ulAddress, NULL, NULL ); - sprintf( pcWriteBuffer, "\r\nNet mask " ); - xReturn = pdTRUE; - xIndex++; - break; - - case 2 : - FreeRTOS_GetAddressConfiguration( NULL, NULL, &ulAddress, NULL ); - sprintf( pcWriteBuffer, "\r\nGateway address " ); - xReturn = pdTRUE; - xIndex++; - break; - - case 3 : - FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulAddress ); - sprintf( pcWriteBuffer, "\r\nDNS server address " ); - xReturn = pdTRUE; - xIndex++; - break; - - default : - ulAddress = 0; - sprintf( pcWriteBuffer, "\r\n\r\n" ); - xReturn = pdFALSE; - xIndex = 0; - break; - } - - if( ulAddress != 0 ) - { - FreeRTOS_inet_ntoa( ulAddress, &( pcWriteBuffer[ strlen( pcWriteBuffer ) ] ) ); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 - - static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) - { - const char *pcParameter; - BaseType_t lParameterStringLength; - - /* Remove compile time warnings about unused parameters, and check the - write buffer is not NULL. NOTE - for simplicity, this example assumes the - write buffer length is adequate, so does not check for buffer overflows. */ - ( void ) pcCommandString; - ( void ) xWriteBufferLen; - configASSERT( pcWriteBuffer ); - - /* Obtain the parameter string. */ - pcParameter = FreeRTOS_CLIGetParameter - ( - pcCommandString, /* The command string itself. */ - 1, /* Return the first parameter. */ - &lParameterStringLength /* Store the parameter string length. */ - ); - - /* Sanity check something was returned. */ - configASSERT( pcParameter ); - - /* There are only two valid parameter values. */ - if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 ) - { - /* Start or restart the trace. */ - vTraceStop(); - vTraceClear(); - vTraceStart(); - - sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" ); - } - else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 ) - { - /* End the trace, if one is running. */ - vTraceStop(); - sprintf( pcWriteBuffer, "Stopping trace recording.\r\n" ); - } - else - { - sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" ); - } - - /* There is no more data to return after this single string, so return - pdFALSE. */ - return pdFALSE; - } - -#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat deleted file mode 100644 index e60a79eb8..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat +++ /dev/null @@ -1,80 +0,0 @@ -REM This file should be executed from the command line prior to the first -REM build. It will be necessary to refresh the Eclipse project once the -REM .bat file has been executed (normally just press F5 to refresh). - -REM Copies all the required files from their location within the standard -REM FreeRTOS directory structure to under the Eclipse project directory. -REM This permits the Eclipse project to be used in 'managed' mode and without -REM having to setup any linked resources. - -REM Standard paths -SET FREERTOS_SOURCE=..\..\..\FreeRTOS\Source -SET FREERTOS_UDP_SOURCE=..\..\Source\FreeRTOS-Plus-UDP -SET FREERTOS_CLI_SOURCE=..\..\Source\FreeRTOS-Plus-CLI -set FREERTOS_TRACE_RECORDER_SOURCE=..\..\Source\FreeRTOS-Plus-Trace - -REM Have the files already been copied? -IF EXIST FreeRTOS_Source Goto END - - REM Create the required directory structure. - MD FreeRTOS_Source - MD FreeRTOS_Source\include - MD FreeRTOS_Source\portable\ - MD FreeRTOS_Source\portable\GCC - MD FreeRTOS_Source\portable\GCC\ARM_CM3 - MD FreeRTOS_Source\portable\MemMang - MD FreeRTOS_Plus_UDP - MD FreeRTOS_Plus_UDP\include - MD FreeRTOS_Plus_UDP\portable - MD FreeRTOS_Plus_UDP\portable\Compiler - MD FreeRTOS_Plus_UDP\portable\Compiler\GCC - MD FreeRTOS_Plus_UDP\portable\BufferManagement - MD FreeRTOS_Plus_UDP\portable\NetworkInterface - MD FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx - MD FreeRTOS_Plus_CLI - MD Examples\Ethernet - - REM Copy the core kernel files into the SDK projects directory - copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source - copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source - copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source - copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source - - REM Copy the common header files into the SDK projects directory - copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include - - REM Copy the portable layer files into the projects directory - copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* FreeRTOS_Source\portable\GCC\ARM_CM3 - - REM Copy the memory allocation file into the project's directory - copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS_Source\portable\MemMang - - REM Copy the FreeRTOS+UDP core files - copy %FREERTOS_UDP_SOURCE%\*.c FreeRTOS_Plus_UDP - copy %FREERTOS_UDP_SOURCE%\readme.txt FreeRTOS_Plus_UDP - copy %FREERTOS_UDP_SOURCE%\include\*.* FreeRTOS_Plus_UDP\include - - REM Copy the FreeRTOS+UDP portable layer files - copy %FREERTOS_UDP_SOURCE%\portable\NetworkInterface\LPC18xx\Using_CMSISv2p10_LPC18xx_DriverLib\*.* FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx - copy %FREERTOS_UDP_SOURCE%\portable\BufferManagement\BufferAllocation_2.c FreeRTOS_Plus_UDP\portable\BufferManagement - copy %FREERTOS_UDP_SOURCE%\portable\Compiler\GCC\*.* FreeRTOS_Plus_UDP\portable\Compiler\GCC - - REM Copy the FreeRTOS+CLI files - copy %FREERTOS_CLI_SOURCE%\*.* FreeRTOS_Plus_CLI - - REM Copy the FreeRTOS+Trace recorder files - copy %FREERTOS_TRACE_RECORDER_SOURCE%\*.* ThirdParty\FreeRTOS_Plus_Trace_Recorder - copy %FREERTOS_TRACE_RECORDER_SOURCE%\include\*.* ThirdParty\FreeRTOS_Plus_Trace_Recorder\include - - REM Copy the echo client example implementation - copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.c Examples\Ethernet - copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.h Examples\include - - REM Copy the example IP trace macro implementation - copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.c Examples\Ethernet - copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.h Examples\include - - REM Copy the CLI commands implementation into the project directory. - copy ..\Common\FreeRTOS_Plus_UDP_Demos\CLICommands\CLI-commands.c . - -: END diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c deleted file mode 100644 index e39cd673f..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * NOTE: This file uses a third party USB CDC driver. - */ - -/* Standard includes. */ -#include "string.h" -#include "stdio.h" - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Driver includes. */ -#include "usbhw.h" -#include "cdcuser.h" -#include "usbcfg.h" -#include "usbuser.h" - -/* Example includes. */ -#include "FreeRTOS_CLI.h" -#include "CDCCommandConsole.h" - -/* Dimensions the buffer into which input characters are placed. */ -#define cmdMAX_INPUT_SIZE 50 - -/* The maximum time in ticks to wait for the CDC access mutex. */ -#define cmdMAX_MUTEX_WAIT ( 200 / portTICK_RATE_MS ) - -/*-----------------------------------------------------------*/ - -/* - * The task that implements the command console processing. - */ -static void prvCDCCommandConsoleTask( void *pvParameters ); - -/* - * Obtain a character from the CDC input. The calling task will be held in the - * Blocked state (so other tasks can execute) until a character is avilable. - */ -char cGetCDCChar( void ); - -/* - * Initialise the third party virtual comport files driver - */ -static void prvSetupUSBDrivers( void ); - -/*-----------------------------------------------------------*/ - -/* 'Given' by the CDC interrupt to unblock the receiving task when new data -is available. */ -static xSemaphoreHandle xNewDataSemaphore = NULL; - -/* Used to guard access to the CDC output, which is used by more than one -task. */ -static xSemaphoreHandle xCDCMutex = NULL; - -/* Const messages output by the command console. */ -static const char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>"; -static const char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>"; -static const char * const pcNewLine = "\r\n"; - -/*-----------------------------------------------------------*/ - -void vCDCCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ) -{ - /* Create the semaphores and mutexes used by the CDC to task interface. */ - xCDCMutex = xSemaphoreCreateMutex(); - vSemaphoreCreateBinary( xNewDataSemaphore ); - configASSERT( xCDCMutex ); - configASSERT( xNewDataSemaphore ); - - /* Add the semaphore and mutex to the queue registry for viewing in the - kernel aware state viewer. */ - vQueueAddToRegistry( xCDCMutex, "CDCMu" ); - vQueueAddToRegistry( xNewDataSemaphore, "CDCDat" ); - - /* Create that task that handles the console itself. */ - xTaskCreate( prvCDCCommandConsoleTask, /* The task that implements the command console. */ - "CDCCmd", /* Text name assigned to the task. This is just to assist debugging. The kernel does not use this name itself. */ - usStackSize, /* The size of the stack allocated to the task. */ - NULL, /* The parameter is not used, so NULL is passed. */ - uxPriority, /* The priority allocated to the task. */ - NULL ); /* A handle is not required, so just pass NULL. */ -} -/*-----------------------------------------------------------*/ - -static void prvCDCCommandConsoleTask( void *pvParameters ) -{ -char cRxedChar; -uint8_t ucInputIndex = 0; -char *pcOutputString; -static char cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ]; -BaseType_t xReturned; - - ( void ) pvParameters; - - /* Obtain the address of the output buffer. Note there is no mutual - exclusion on this buffer as it is assumed only one command console - interface will be used at any one time. */ - pcOutputString = FreeRTOS_CLIGetOutputBuffer(); - - /* Initialise the virtual com port (CDC) interface. */ - prvSetupUSBDrivers(); - - /* Send the welcome message. This probably won't be seen as the console - will not have been connected yet. */ - USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcWelcomeMessage, strlen( pcWelcomeMessage ) ); - - for( ;; ) - { - /* No characters received yet for the current input string. */ - cRxedChar = 0; - - /* Only interested in reading one character at a time. */ - cRxedChar = cGetCDCChar(); - - if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS ) - { - /* Echo the character back. */ - USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) &cRxedChar, sizeof( uint8_t ) ); - - /* Was it the end of the line? */ - if( cRxedChar == '\n' || cRxedChar == '\r' ) - { - /* Just to space the output from the input. */ - USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcNewLine, strlen( pcNewLine ) ); - - /* See if the command is empty, indicating that the last command is - to be executed again. */ - if( ucInputIndex == 0 ) - { - /* Copy the last command back into the input string. */ - strcpy( cInputString, cLastInputString ); - } - - /* Pass the received command to the command interpreter. The - command interpreter is called repeatedly until it returns pdFALSE - (indicating there is no more output) as it might generate more than - one string. */ - do - { - /* Get the next output string from the command interpreter. */ - xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE ); - - /* Write the generated string to the CDC. */ - USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcOutputString, strlen( pcOutputString ) ); - vTaskDelay( 1 ); - - } while( xReturned != pdFALSE ); - - /* All the strings generated by the input command have been sent. - Clear the input string ready to receive the next command. Remember - the command that was just processed first in case it is to be - processed again. */ - strcpy( cLastInputString, cInputString ); - ucInputIndex = 0; - memset( cInputString, 0x00, cmdMAX_INPUT_SIZE ); - - USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcEndOfOutputMessage, strlen( pcEndOfOutputMessage ) ); - } - else - { - if( cRxedChar == '\r' ) - { - /* Ignore the character. */ - } - else if( cRxedChar == '\b' ) - { - /* Backspace was pressed. Erase the last character in the - string - if any. */ - if( ucInputIndex > 0 ) - { - ucInputIndex--; - cInputString[ ucInputIndex ] = '\0'; - } - } - else - { - /* A character was entered. Add it to the string - entered so far. When a \n is entered the complete - string will be passed to the command interpreter. */ - if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) ) - { - if( ucInputIndex < cmdMAX_INPUT_SIZE ) - { - cInputString[ ucInputIndex ] = cRxedChar; - ucInputIndex++; - } - } - } - } - - /* Must ensure to give the mutex back. */ - xSemaphoreGive( xCDCMutex ); - } - } -} -/*-----------------------------------------------------------*/ - -void vOutputString( const char * const pcMessage ) -{ - if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS ) - { - USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcMessage, strlen( pcMessage ) ); - xSemaphoreGive( xCDCMutex ); - } -} -/*-----------------------------------------------------------*/ - -char cGetCDCChar( void ) -{ -int32_t lAvailableBytes, xBytes = 0; -char cInputChar; - - do - { - /* Are there any characters already available? */ - CDC_OutBufAvailChar( &lAvailableBytes ); - if( lAvailableBytes > 0 ) - { - if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS ) - { - /* Attempt to read one character. */ - xBytes = 1; - xBytes = CDC_RdOutBuf( &cInputChar, &xBytes ); - - xSemaphoreGive( xCDCMutex ); - } - } - - if( xBytes == 0 ) - { - /* A character was not available. Wait until signalled by the - CDC Rx callback function that new data has arrived. */ - xSemaphoreTake( xNewDataSemaphore, portMAX_DELAY ); - } - - } while( xBytes == 0 ); - - return cInputChar; -} -/*-----------------------------------------------------------*/ - -/* Callback function executed by the USB interrupt when new data arrives. */ -void vCDCNewDataNotify( void ) -{ -BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - configASSERT( xNewDataSemaphore ); - - /* 'Give' the semaphore that signals the arrival of new data to the command - console task. */ - xSemaphoreGiveFromISR( xNewDataSemaphore, &xHigherPriorityTaskWoken ); - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupUSBDrivers( void ) -{ -LPC_USBDRV_INIT_T xUSBCallback; - - /* Initialise the callback structure. */ - memset( ( void * ) &xUSBCallback, 0, sizeof( LPC_USBDRV_INIT_T ) ); - xUSBCallback.USB_Reset_Event = USB_Reset_Event; - xUSBCallback.USB_P_EP[ 0 ] = USB_EndPoint0; - xUSBCallback.USB_P_EP[ 1 ] = USB_EndPoint1; - xUSBCallback.USB_P_EP[ 2 ] = USB_EndPoint2; - xUSBCallback.ep0_maxp = USB_MAX_PACKET0; - - /* Initialise then connect the USB. */ - USB_Init( &xUSBCallback ); - USB_Connect( pdTRUE ); -} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h deleted file mode 100644 index a5af52c30..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef CDC_COMMAND_CONSOLE_H -#define CDC_COMMAND_CONSOLE_H - -/* - * Create the task that implements a command console using the USB virtual com - * port driver for intput and output. - */ -void vCDCCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); - -#endif /* CDC_COMMAND_CONSOLE_H */ - - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h deleted file mode 100644 index dca98ac20..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef TWO_ECHO_CLIENTS_H -#define TWO_ECHO_CLIENTS_H - -/* - * Create the two UDP echo client tasks. One task uses the standard interface - * to send to and receive from an echo server. The other task uses the zero - * copy interface to send to and receive from an echo server. - */ -void vStartEchoClientTasks( uint16_t usTaskStackSize, UBaseType_t uxTaskPriority ); - -#endif /* TWO_ECHO_CLIENTS_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Flash_map.xml b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Flash_map.xml deleted file mode 100644 index 1fb1cd384..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Flash_map.xml +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h deleted file mode 100644 index ec7fefa88..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include -extern uint32_t SystemCoreClock; - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * http://www.freertos.org/a00110.html - * - * The bottom of this file contains some constants specific to running the UDP - * stack in this demo. Constants specific to FreeRTOS+UDP itself (rather than - * the demo) are contained in FreeRTOSIPConfig.h. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#define configUSE_TICKLESS_IDLE 0 -#define configMAX_PRIORITIES ( 7 ) -#define configCPU_CLOCK_HZ ( SystemCoreClock ) -#define configTICK_RATE_HZ 100 -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 300 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) /* Has not effect in this demo as the heap is manually pointed to AHB RAM. */ -#define configMAX_TASK_NAME_LEN ( 9 ) -#define configIDLE_SHOULD_YIELD 0 -#define configQUEUE_REGISTRY_SIZE 10 -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configUSE_MUTEXES 1 -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_ALTERNATIVE_API 0 -#define configUSE_RECURSIVE_MUTEXES 1 - -/* Hook function related definitions. */ -#define configUSE_TICK_HOOK 0 -#define configUSE_IDLE_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configCHECK_FOR_STACK_OVERFLOW 2 - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -/* Run time stats gathering definitions. */ -void vMainConfigureTimerForRunTimeStats( void ); -uint32_t ulMainGetRunTimeCounterValue( void ); -#define configGENERATE_RUN_TIME_STATS 1 -#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vMainConfigureTimerForRunTimeStats() -#define portGET_RUN_TIME_COUNTER_VALUE() ulMainGetRunTimeCounterValue() - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_xTimerGetTimerTaskHandle 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xQueueGetMutexHolder 1 - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 - -/* Assert statement defined for debug builds. */ -#ifdef DEBUG - #define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } -#endif - -/* Interrupt priority configuration settings follow. -http://www.freertos.org/RTOS-Cortex-M3-M4.html */ - -/* Use the system definition for the number of interrupt priorities, if there -is one */ -#ifdef __NVIC_PRIO_BITS - #define configPRIO_BITS __NVIC_PRIO_BITS -#else - #define configPRIO_BITS 3 /* 8 priority levels */ -#endif - -/* The maximum priority an interrupt that uses an interrupt safe FreeRTOS API -function can have. Note that lower priority have numerically higher values. */ -#define configMAX_LIBRARY_INTERRUPT_PRIORITY ( 5 ) - -/* The minimum possible interrupt priority. */ -#define configMIN_LIBRARY_INTERRUPT_PRIORITY ( 7 ) - -/* The lowest priority. */ -#define configKERNEL_INTERRUPT_PRIORITY ( configMIN_LIBRARY_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - -/* Priority 5, or 248 as only the top five bits are implemented. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configMAX_LIBRARY_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - -/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS -standard names. */ -#define vPortSVCHandler SVC_Handler -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler - - -/* - * DEMO APPLICATION SPECIFIC DEFINITIONS FOLLOW FROM HERE - */ - -/* Set to 1 to include "trace start" and "trace stop" CLI commands. These -commands start and stop the FreeRTOS+Trace recording. */ -#define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0 - -/* Dimensions a buffer that can be used by the FreeRTOS+CLI command -interpreter. See the FreeRTOS+CLI documentation for more information: -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */ -#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1024 - -/* The priority used by the Ethernet MAC driver interrupt. */ -#define configMAC_INTERRUPT_PRIORITY ( configMAX_LIBRARY_INTERRUPT_PRIORITY ) - -/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace -macros are defined to gather some UDP stack statistics that can then be viewed -through the CLI interface. See -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml*/ -#define configINCLUDE_DEMO_DEBUG_STATS 1 - -/* The LPC1830 Ethernet peripheral uses a DMA to transmit and receive packets. -The DMA uses a chain of descriptors to reference Ethernet buffers, and provide -information on the state of each buffer (full/empty/error/etc.). -configNUM_RX_ETHERNET_DMA_DESCRIPTORS defines the total number of receive -descriptors (descriptors that point to buffers into which the DMA will write -packets received from the network). An Ethernet buffer is assigned to each -descriptor. Having too few descriptors will impact reliability because the DMA -will have to drop packets that are received when there are no receive -descriptors free. It is however only necessary to have a couple of free -descriptors at a time, and having more wastes the RAM used by the Ethernet -buffers that are surplus to requirements. */ -#define configNUM_RX_ETHERNET_DMA_DESCRIPTORS 4 - -/* The LPC1830 Ethernet peripheral uses a DMA to transmit and receive packets. -The DMA uses a chain of descriptors to reference Ethernet buffers that are -waiting to be sent onto the network. configNUM_TX_ETHERNET_DMA_DESCRIPTORS -defines the total number of transmit descriptors. An Ethernet buffer is -not assigned to a transmit descriptor until data is actually sent, but will -remain assigned to the descriptor until the descriptor is re-used. It is not -necessary to have many transmit descriptors as the IP stack task will be held -in the Blocked state (so other tasks can run) until a descriptor becomes -available if it attempts to transmit when all the descriptors are in use. See -the iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() IP trace macro. */ -#define configNUM_TX_ETHERNET_DMA_DESCRIPTORS 1 - -/* The address of an echo server that will be used by the two demo echo client -tasks. -http://FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */ -#define configECHO_SERVER_ADDR0 172 -#define configECHO_SERVER_ADDR1 25 -#define configECHO_SERVER_ADDR2 218 -#define configECHO_SERVER_ADDR3 103 - -/* MAC address configuration. In a deployed production system this would -probably be read from an EEPROM. In the demo it is just hard coded. Make sure -each node on the network has a unique MAC address. */ -#define configMAC_ADDR0 0x00 -#define configMAC_ADDR1 0x01 -#define configMAC_ADDR2 0x02 -#define configMAC_ADDR3 0x03 -#define configMAC_ADDR4 0x04 -#define configMAC_ADDR5 0x08 - -/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or -ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configIP_ADDR0 172 -#define configIP_ADDR1 25 -#define configIP_ADDR2 218 -#define configIP_ADDR3 200 - -/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to -0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configGATEWAY_ADDR0 172 -#define configGATEWAY_ADDR1 25 -#define configGATEWAY_ADDR2 218 -#define configGATEWAY_ADDR3 1 - -/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and -208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set -to 1 but a DNS server cannot be contacted.*/ -#define configDNS_SERVER_ADDR0 208 -#define configDNS_SERVER_ADDR1 67 -#define configDNS_SERVER_ADDR2 222 -#define configDNS_SERVER_ADDR3 222 - -/* Defalt netmask configuration. Used in ipconfigUSE_DNS is set to 0, or -ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configNET_MASK0 255 -#define configNET_MASK1 255 -#define configNET_MASK2 255 -#define configNET_MASK3 0 - -/* Only include the trace macro definitions required by FreeRTOS+Trace if -the trace start and trace stop CLI commands are included. */ -#include "trcRecorder.h" - -#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSIPConfig.h deleted file mode 100644 index d676800a0..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSIPConfig.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for configuration information. - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Configuration.shtml - * - *****************************************************************************/ - -#ifndef FREERTOS_IP_CONFIG_H -#define FREERTOS_IP_CONFIG_H - -/* The IP stack executes it its own task (although any application task can make -use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY -sets the priority of the task that executes the IP stack. The priority is a -standard FreeRTOS task priority so can take any value from 0 (the lowest -priority) to (configMAX_PRIORITIES - 1) (the highest priority). -configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in -FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to -the priority assigned to the task executing the IP stack relative to the -priority assigned to tasks that use the IP stack. */ -#define ipconfigUDP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) - -/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+UDP -task. This setting is less important when the FreeRTOS Win32 simulator is used -as the Win32 simulator only stores a fixed amount of information on the task -stack. FreeRTOS includes optional stack overflow detection, see: -http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigUDP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 3 ) - -/* ipconfigRAND32() is called by the IP stack to generate a random number that -is then used as a DHCP transaction number. Random number generation is performed -via this macro to allow applications to use their own random number generation -method. For example, it might be possible to generate a random number by -sampling noise on an analogue input. */ -#define ipconfigRAND32() 1 - -/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+UDP will call the -network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK -is not set to 1 then the network event hook will never be called. See -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml -*/ -#define ipconfigUSE_NETWORK_EVENT_HOOK 1 - -/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but -a network buffer cannot be obtained then the calling task is held in the Blocked -state (so other tasks can continue to executed) until either a network buffer -becomes available or the send block time expires. If the send block time expires -then the send operation is aborted. The maximum allowable send block time is -capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the -maximum allowable send block time prevents prevents a deadlock occurring when -all the network buffers are in use and the tasks that process (and subsequently -free) the network buffers are themselves blocked waiting for a network buffer. -ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in -milliseconds can be converted to a time in ticks by dividing the time in -milliseconds by portTICK_RATE_MS. */ -#define ipconfigMAX_SEND_BLOCK_TIME_TICKS ( 20 / portTICK_RATE_MS ) - -/* If ipconfigUSE_DHCP is 1 then FreeRTOS+UDP will attempt to retrieve an IP -address, netmask, DNS server address and gateway address from a DHCP server. If -ipconfigUSE_DHCP is 0 then FreeRTOS+UDP will use a static IP address. The -stack will revert to using the static IP address even when ipconfigUSE_DHCP is -set to 1 if a valid configuration cannot be obtained from a DHCP server for any -reason. The static configuration used is that passed into the stack by the -FreeRTOS_IPInit() function call. */ -#define ipconfigUSE_DHCP 1 - -/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at -increasing time intervals until either a reply is received from a DHCP server -and accepted, or the interval between transmissions reaches -ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the -static IP address passed as a parameter to FreeRTOS_IPInit() if the -re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without -a DHCP reply being received. */ -#ifdef _WINDOWS_ - /* The windows simulated time is not real time so the max delay is much - shorter. */ - #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 999 / portTICK_RATE_MS ) -#else - #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 120000 / portTICK_RATE_MS ) -#endif /* _WINDOWS_ */ - -/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP -stack can only send a UDP message to a remove IP address if it knowns the MAC -address associated with the IP address, or the MAC address of the router used to -contact the remote IP address. When a UDP message is received from a remote IP -address the MAC address and IP address are added to the ARP cache. When a UDP -message is sent to a remote IP address that does not already appear in the ARP -cache then the UDP message is replaced by a ARP message that solicits the -required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum -number of entries that can exist in the ARP table at any one time. */ -#define ipconfigARP_CACHE_ENTRIES 6 - -/* ARP requests that do not result in an ARP response will be re-transmitted a -maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is -aborted. */ -#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 ) - -/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP -table being created or refreshed and the entry being removed because it is stale. -New ARP requests are sent for ARP cache entries that are nearing their maximum -age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is -equal to 1500 seconds (or 25 minutes). */ -#define ipconfigMAX_ARP_AGE 150 - -/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling -routines, which are relatively large. To save code space the full -FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster -alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr() -takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter. -FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets -(for example, 192, 168, 0, 1) as its parameters. If -ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and -FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is -not set to 1 then only FreeRTOS_indet_addr_quick() is available. */ -#define ipconfigINCLUDE_FULL_INET_ADDR 1 - -/* ipconfigNUM_NETWORK_BUFFERS defines the total number of network buffer that -are available to the IP stack. The total number of network buffers is limited -to ensure the total amount of RAM that can be consumed by the IP stack is capped -to a pre-determinable value. */ -#define ipconfigNUM_NETWORK_BUFFERS 10 - -/* A FreeRTOS queue is used to send events from application tasks to the IP -stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can -be queued for processing at any one time. The event queue must be a minimum of -5 greater than the total number of network buffers. */ -#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFERS + 5 ) - -/* The address of a socket is the combination of its IP address and its port -number. FreeRTOS_bind() is used to manually allocate a port number to a socket -(to 'bind' the socket to a port), but manual binding is not normally necessary -for client sockets (those sockets that initiate outgoing connections rather than -wait for incoming connections on a known port number). If -ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling -FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP -stack automatically binding the socket to a port number from the range -socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If -ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto() -on a socket that has not yet been bound will result in the send operation being -aborted. */ -#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1 - -/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */ -#define updconfigIP_TIME_TO_LIVE 128 - -/* If ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 1 then UDP packets that -contain more data than will fit in a single network frame will be fragmented -across multiple IP packets. Also see the ipconfigNETWORK_MTU setting. If -ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must -be divisible by 8. Setting ipconfigCAN_FRAGMENT_OUTGOING_PACKETS to 1 will -increase both the code size and execution time. */ -#define ipconfigCAN_FRAGMENT_OUTGOING_PACKETS 0 - -/* The MTU is the maximum number of bytes the payload of a network frame can -contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a -lower value can save RAM, depending on the buffer management scheme used. If -ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must -be divisible by 8. */ -#define ipconfigNETWORK_MTU 586 - -/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used -through the FreeRTOS_gethostbyname() API function. */ -#define ipconfigUSE_DNS 1 - -/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will -generate replies to incoming ICMP echo (ping) requests. */ -#define ipconfigREPLY_TO_INCOMING_PINGS 1 - -/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the -FreeRTOS_SendPingRequest() API function is available. */ -#define ipconfigSUPPORT_OUTGOING_PINGS 1 - -/* Used for stack testing only, and must be implemented in the network -interface. */ -#define updconfigLOOPBACK_ETHERNET_PACKETS 0 - -/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames -that are not in Ethernet II format will be dropped. This option is included for -potential future IP stack developments. */ -#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1 - -/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the -responsibility of the Ethernet interface to filter out packets that are of no -interest. If the Ethernet interface does not implement this functionality, then -set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack -perform the filtering instead (it is much less efficient for the stack to do it -because the packet will already have been passed into the stack). If the -Ethernet driver does all the necessary filtering in hardware then software -filtering can be removed by using a value other than 1 or 0. */ -#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 2 - -/* The example IP trace macros are included here so the definitions are -available in all the FreeRTOS+UDP source files. */ -#include "DemoIPTrace.h" - -#endif /* FREERTOS_IP_CONFIG_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LEDs.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LEDs.c deleted file mode 100644 index 8dc893ab1..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LEDs.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Simple LED IO functions. LED 0 is toggled by a timer every half second. */ - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "timers.h" - -/* Library includes. */ -#include "lpc18xx_gpio.h" -#include "lpc18xx_scu.h" -#include "lpc18xx_cgu.h" - -#define ledTOGGLE_RATE ( 500 / portTICK_RATE_MS ) - -#define ledLED0_PORT 1 -#define ledLED0_BIT ( 1UL << 11UL ) - -#define ledLED1_PORT 2 -#define ledLED1_BIT ( 1UL << 12UL ) - -/* - * Toggles an LED just to show the application is running. - */ -static void prvLEDToggleTimerCallback( xTimerHandle xTimer ); - -/*-----------------------------------------------------------*/ - -void vLEDsInitialise( void ) -{ -static xTimerHandle xLEDToggleTimer = NULL; - - /* Set the LED pin-muxing and configure as output. */ - scu_pinmux( 0x2 , 11, MD_PUP, FUNC0 ); - scu_pinmux( 0x2 , 12, MD_PUP, FUNC0 ); - GPIO_SetDir( ledLED0_PORT, ledLED0_BIT, 1 ); - GPIO_SetDir( ledLED1_PORT, ledLED1_BIT, 1 ); - - /* Create the timer used to toggle LED0. */ - xLEDToggleTimer = xTimerCreate( "LEDTmr", /* Just a text name to associate with the timer, useful for debugging, but not used by the kernel. */ - ledTOGGLE_RATE, /* The period of the timer. */ - pdTRUE, /* This timer will autoreload, so uxAutoReload is set to pdTRUE. */ - NULL, /* The timer ID is not used, so can be set to NULL. */ - prvLEDToggleTimerCallback ); /* The callback function executed each time the timer expires. */ - - /* Sanity check that the timer was actually created. */ - configASSERT( xLEDToggleTimer ); - - /* Start the timer. If this is called before the scheduler is started then - the block time will automatically get changed to 0 (from portMAX_DELAY). */ - xTimerStart( xLEDToggleTimer, portMAX_DELAY ); -} -/*-----------------------------------------------------------*/ - -static void prvLEDToggleTimerCallback( xTimerHandle xTimer ) -{ -static uint8_t ucState = 0; - - /* Remove compiler warnings. */ - ( void ) xTimer; - - /* Just toggle an LED to show the program is running. */ - if( ucState == 0 ) - { - GPIO_SetValue( ledLED0_PORT, ledLED0_BIT ); - } - else - { - GPIO_ClearValue( ledLED0_PORT, ledLED0_BIT ); - } - - ucState = !ucState; -} - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/README_FIRST.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/README_FIRST.txt deleted file mode 100644 index 4311d8b34..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/README_FIRST.txt +++ /dev/null @@ -1,11 +0,0 @@ -This demo is documented on the following web page: -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_and_CLI_LPC1830_NGX.shtml - -The FreeRTOS+UDP API is documented on the following web page: -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.shtml - -Other information, including a FreeRTOS+UDP primer, a description of the -directory structure, and a glossary of networking terminology, can be found in -the FreeRTOS+UDP portal: -http://www.FreeRTOS.org/udp - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ReadMe.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ReadMe.txt new file mode 100644 index 000000000..24bb5461e --- /dev/null +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ReadMe.txt @@ -0,0 +1,4 @@ +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/RunTimeStatsTimer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/RunTimeStatsTimer.c deleted file mode 100644 index 7d7ee4b02..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/RunTimeStatsTimer.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" - -/* Utility functions to implement run time stats on Cortex-M CPUs. The collected -run time data can be viewed through the CLI interface. See the following URL for -more information on run time stats: -http://www.freertos.org/rtos-run-time-stats.html */ - -/* Addresses of registers in the Cortex-M debug hardware. */ -#define rtsDWT_CYCCNT ( *( ( unsigned long * ) 0xE0001004 ) ) -#define rtsDWT_CONTROL ( *( ( unsigned long * ) 0xE0001000 ) ) -#define rtsSCB_DEMCR ( *( ( unsigned long * ) 0xE000EDFC ) ) -#define rtsTRCENA_BIT ( 0x01000000UL ) -#define rtsCOUNTER_ENABLE_BIT ( 0x01UL ) - -/* Simple shift divide for scaling to avoid an overflow occurring too soon. The -number of bits to shift depends on the clock speed. */ -#define runtimeSLOWER_CLOCK_SPEEDS ( 70000000UL ) -#define runtimeSHIFT_13 13 -#define runtimeOVERFLOW_BIT_13 ( 1UL << ( 32UL - runtimeSHIFT_13 ) ) -#define runtimeSHIFT_14 14 -#define runtimeOVERFLOW_BIT_14 ( 1UL << ( 32UL - runtimeSHIFT_14 ) ) - -/*-----------------------------------------------------------*/ - -void vMainConfigureTimerForRunTimeStats( void ) -{ - /* Enable TRCENA. */ - rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT; - - /* Reset counter. */ - rtsDWT_CYCCNT = 0; - - /* Enable counter. */ - rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT; -} -/*-----------------------------------------------------------*/ - -uint32_t ulMainGetRunTimeCounterValue( void ) -{ -static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0; -unsigned long ulValueNow; - - ulValueNow = rtsDWT_CYCCNT; - - /* Has the value overflowed since it was last read. */ - if( ulValueNow < ulLastCounterValue ) - { - ulOverflows++; - } - ulLastCounterValue = ulValueNow; - - /* Cannot use configCPU_CLOCK_HZ directly as it may itself not be a constant - but instead map to a variable that holds the clock speed. */ - - /* There is no prescale on the counter, so simulate in software. */ - if( configCPU_CLOCK_HZ < runtimeSLOWER_CLOCK_SPEEDS ) - { - ulValueNow >>= runtimeSHIFT_13; - ulValueNow += ( runtimeOVERFLOW_BIT_13 * ulOverflows ); - } - else - { - ulValueNow >>= runtimeSHIFT_14; - ulValueNow += ( runtimeOVERFLOW_BIT_14 * ulOverflows ); - } - - return ulValueNow; -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/CMSIS END USER LICENCE AGREEMENT.pdf b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/CMSIS END USER LICENCE AGREEMENT.pdf deleted file mode 100644 index e04afaee6..000000000 Binary files a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/CMSIS END USER LICENCE AGREEMENT.pdf and /dev/null differ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/cmsis_readme.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/cmsis_readme.txt deleted file mode 100644 index 316499c01..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/cmsis_readme.txt +++ /dev/null @@ -1,44 +0,0 @@ -CMSIS : Cortex Microcontroller Software Interface Standard -========================================================== - -Introduction -~~~~~~~~~~~~ -CMSIS defines for a Cortex-M Microcontroller System: - - * A common way to access peripheral registers and a - common way to define exception vectors. - * The register names of the Core Peripherals and the - names of the Core Exception Vectors. - * An device independent interface for RTOS Kernels - including a debug channel. - -By using CMSIS compliant software components, the user can -easier re-use template code. CMSIS is intended to enable the -combination of software components from multiple middleware -vendors. - -This project contains appropriate files for this MCU family -taken from CMSIS. A full copy of the CMSIS files, together -with additional information on CMSIS can be found at: - - http://www.onarm.com/ - http://www.arm.com/ - -Documentation -~~~~~~~~~~~~~ -The standard CMSIS documentation can be found within the -Code Red IDE help system, via: - -Help -> Help Contents -> Code Red Product Documentation -> CMSIS - -More information on the use of CMSIS within the Code Red IDE -can be found in the Support area of the Code Red website at - - http://www.code-red-tech.com/ - -At the time of writing, the CMSIS FAQ can be found directly -at: - - http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt deleted file mode 100644 index b91c5ee76..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt +++ /dev/null @@ -1,325 +0,0 @@ -RELEASE CMSIS for REV A 20111209 -1/ New LPC18xx.h header file. Changes GPIO structure. -2/ Addition of lpc18xx_emc.c and lpc18xx_emc.h to configure memory on Hitex board. -3/ Addition of spifi_rom_api.h, spifi_drv_M3.lib and SPIFI_ROM_support.doc SPIFI driver package -4/ Updated SPIFI programming driver for Keil MDK which uses the SPIFI lib -5/ New BOOTFAST example shows how to boot from external flash or QSPI and ramp to 180 MHz - -RELEASE CMSIS for REV A 20111130 -1./ lpc18xx_lcd.h LCD_CFG_type add member pcd, lpc18xx_lcd.c add init pcd in LCD_Init function -2./ protect MAX and MIN macro in lpc_types.h -3./ Add getPC function to ARM,GNU, IAR startup_lpc18xx.s -4./ Add VTOR init in SystemInit function -5./ Change All ADC examples to use ADC port 0 -6./ These example: CortexM3_Mpu, Pwr_DeepPowerDown, Timer_FreqMeasure, SCT_SimpleMatch and all USBDEV_ROM examples Keil project was adjusted -7./ SDRAM example and LCD example was changed not to use uint64_t in NS2CLK function -8./ Nvic_VectorTableRelocation.c -removed: -#if __RAM_MODE__//Run in RAM mode - memcpy((void *)VTOR_OFFSET, (const void *)0x10000000, 256*4); -#else - memcpy((void *)VTOR_OFFSET, (const void *)0x1C000000, 256*4); -#endif - -added: -memcpy((void *)VTOR_OFFSET, (const void *)(getPC()& 0xFF000000), 256*4); -9./ Pwr_PowerDown change method for testing this feature - - -RELEASE CMSIS for REV A 20111028 -1./ Add GNU support -2./ Addition of new Keil flash drivers for eFlash and SPIFI -3./ Change of Keil projects to support eFlash and SPIFI operation - -PRE-RELEASE CMSIS for REV A 20111011 -1/ PowerDown Example IAR issue fixed -2/ Upgraded CMSIS to version 2.10 -3/ Upgraded Core header to Rev A -4/ lpc18xx_can.h remove all bitrates from 8Mhz, add bitrates from 12Mhz - /** Bitrate: 100K */ - #define CAN_BITRATE100K12MHZ 0x00004509 - /** Bitrate: 125K */ - #define CAN_BITRATE125K12MHZ 0x00004507 - /** Bitrate: 250K */ - #define CAN_BITRATE250K12MHZ 0x00004503 - /** Bitrate: 500K */ - #define CAN_BITRATE500K12MHZ 0x00004501 - /** Bitrate: 1000K */ - #define CAN_BITRATE1000K12MHZ 0x00004500 -5./ lpc18xx_cgu.* add PLL audio clock, modify alloc connect table and CGU_Entity_ControlReg_Offset -6./ lpc18xx_evrt.h - add EVRT_SRC_SDIO -7./ lpc18xx_i2s.h separate LPC_I2S0 and LPC_I2S1 -8./ lpc18xx_scu.h - redefine, add pin modes and add pin functions 4->7 -9./ debug_frmwrk.c - changed pin mode for UART RXD0 and UART RXD1 -10./ lpc_can.c replace LPC_CAN by LPC_CAN0 -11./ lpc18xx_i2c.* replace i2c pin configurations -12./ lpc18xx_ssp.c down default clock speed to 100kHz -13./ Examples\CCAN\CCan_SimpleTxRx\CCan_SimpleTxRx.c change RD pin mode to enable input buffer -14./ Examples\EMAC\Emac_EasyWeb\emac.c - replace MII and RMII pin setting by source from CodeBundle -15./ Examples\EMC\Emc_Sdram\SDRAM_Init.c and Examples\EMC\Emc_NorFlash\SST39VF320.c - replace EMC pin setting to be compatible with Rev A -16./ Examples\I2S\I2s_Audio\I2s_Audio.c - replace I2S pin setting to be compatible with Rev A - replace I2S to I2S0 -17./ Examples\LCD\Lcd_Demo\IS42S16400D.c - replace EMC pin setting to be compatible with Rev A -18./ Examples\SSP\All SSP examples: replace SSP pin setting to be compatible with Rev A -19./ Timer_Capture and Timer_FreqMeasure: replace Capture input pin setting to be compatible with Rev A -20./ Examples\UART\All UART examples: replace UART pin setting to be compatible with Rev A -21./ Examples\USBDEV\USB_*\usbhw.c - replace USB pin setting to be compatible with Rev A - correct clock in Init function - -RELEASE: LPC1800CMSIS_20110829 -1./ Add GNU Support -modify pasting in can.c to be compatible with GCC - -RELEASE: LPC1800CMSIS_20110729 -1./ IAR flash support is moved to Tools folder -2./ ADC.h fixed macro ADC_CR_BITACC -3./ I2S.h fixed comment - from #endif /* LPC17XX_SSP_H_ */ - to #endif /* LPC18XX_I2S_H_ */ -4./ ADC.c fix ADC_Init Clock by rounding clk div value -5./ i2s.c fixed some comment -6./ EMC Nor Flash renamed file flash programing function -7./ SDRAM can run at MAX EMC Speed -8./ Removed flash programing support for LHF00L28 - -RELEASE: LPC1800CMSIS_20110627 -1./ Fix abstract -2./ Fix I2S FreqConfig mistake -3./ Add DFU Driver and App - - -RELEASE: LPC1800CMSIS_20110613 -1./ Add DSP Document -2./ Speed Up External FLash Mode -3./ Add IAR Flash Support -4./ Fix GPDMA Flash transfer issue in IAR -5./ Set default taget is EXFLASH(Keil only) - -************************************************************************************************************************************************ -RELEASE: LPC1800CMSIS_20110603 -1./ Add DSP_lib into Core folder -2./ Update core_cmFunc.h and core_cmInstr.h for solving conflict with IAR EWARM version 6.20 or later -3./ add IAR startup file and IAR support files in Core\DeviceSupport\NXP\LPC18xx -4./ Modify SystemInit function to support RAM mode - #if (__RAM_MODE__) - SCB->VTOR = 0x10000000; - #endif -5./ Modify CCU1 and CCU2 struct in LPC18xx.h -6./ Fix bug in uart_set_divisors function -7./ Change UART clock source from XTAL to PLL1 in uart driver -8./ Fix RTC bugs -9./ Modify lpc18xx_GPDMA.c to support IAR compiler -10./ Modify lpc18xx_cgu.c to support IAR compiler -11./ Update lpc_types.h to support IAR compiler -12./ Fix bugs in I2S driver -13./ Remove Warnings -14./ Change new header, add more comments -15./ Standalize example, project, output names -16./ Support IAR EWARM (RAM mode) -17./ SUpport Hitex Board as default -18./ Modify hardware configuration in abstract files -19./ Set default Target to RAM mode - -************************************************************************************************************************************************ -RELEASE: LPC1800CMSIS_20110514 -1./ Change all Keil example projects from device Cortex M3 to LPC1850 -2./ change all examples to support Hitex board only -3./ Verify all project option -4./ separated CGU and PWR into 2 independent drivers - -************************************************************************************************************************************************ -RELEASE: LPC1800CMSIS_20110421 -1./ Add CAN driver: - Drivers/include/lpc18xx_can.h - Drivers/source/lpc18xx_can.c - -2./ Add CAN example for simple Transceiver - Examples\C_CAN\simpleTxRx - -3./ Add 4 USB Rom examples: - USB_DFU - USB_HID - USB_MassStorage - USB_Composite - -4./ Enable _printf function - debug_frmwrk.h: - uncomment _printf function declaration - debug_frmwrk.c: - uncomment _printf function - -************************************************************************************************************************************************ -RELEASE: LPC1800CMSIS_20110401 - -1./ Change all Keil example proiects from device NXP LPC1768 to ARM Cortex-M3 - -2./ Fix bug in I2C driver (customer feedback) - Problem description: - I2C_MasterTransferData() is not able to - (1) Send, - (2) doing a repeated Start and - (3) starting to receive with one function call. - Problem is that the repeated start is not generated, but a retransmission of the - last word is startet. - Solve: change - I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; - I2Cx->I2CONSET = I2C_I2CONSET_STA; - to - I2Cx->I2CONSET = I2C_I2CONSET_STA; - I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; - in function I2C_Start () - -3./ lpc18xx_timer.c: - Function TIM_ClearIntPending(): - Change TIMx->IR |= TIM_IR_CLR(IntFlag); - To TIMx->IR = TIM_IR_CLR(IntFlag); - Function TIM_ClearIntCapturePending(): - Change TIMx->IR |= (1<<(4+IntFlag)); - To TIMx->IR = (1<<(4+IntFlag)); - Function TIM_GetCaptureValue(): - Add return 0; - -4./ EMC - Nor Flash: remove example build target for FLASH mode as it only can run in RAM mode. - -5./ SCT: update Fizzim tool to version 1.1 - -6./ Tools: - Update Flash burning for LHF00L28 and SST39X320X - -************************************************************************************************************************************************ - -RELEASE: LPC1800CMSIS_20110324 - -1./ Current support hardwares: - - NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA' - - Hitex LPC1800 Board through definition 'BOARD_HITEX_LPC1800' - Some examples can run on LPC1800 Evaluation board, some can run on Hitex board...Please refer to abstract.txt - -2./ Addin new flash support under Tools/Flash/SST39X320X - -3./ lpc18xx_evrt.c: - Change EVRTx->SET_EN |= (1<<(uint8_t)EVRT_Src); - To EVRTx->SET_EN = (1<<(uint8_t)EVRT_Src); - Purpose: prevent clearing other set bits as writing '0' has no effect - -4./ Fix ATIMER_WIC example: - - Configure 32KHZ osc in lpc18xx_atimer.c - - Call the configuration function in atimer_wic.c - -5./ Fix RTC_Alarm example: - - Configure 32KHZ osc in lpc18xx_rtc.c - - Update Rtc_Alarm.c - -6./ Add in PWR_PowerDown example - -7./ Add in PWR_DeepPowerDown example - -8./ All example in PWR are modified to wait for '1' sent from PC's COM port to start - -9./ Fix LCD Logic4.3 example to run on Hitex LPC1800 Board - -10./ Add in GPDMA Flash_2_Ram_Test example - -11./ EMC EXT_SDRAM example: join IS42S16400D.c and MT48LC4M32B2.c into SDRAM_Init.c - -12./ lpc18xx_i2s.c: update I2S_FreqConfig() function - -************************************************************************************************************************************************ - -RELEASE: LPC1800CMSIS_20110311 - -1./ This package is compliant to CMSIS 2.0 - -2./ Add in 'Tools' folder which contains neccessary material for building project, examples like flash burning,.. - -3./ Examples are given in Keil uVision 4 project - -4./ Current support hardwares: - - NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA' - -5./ Examples can run: - - RAM (debug) mode - - ROM (Flash, stand alone) mode - + External Nor Flash. Flash Part supporting: - 1) LHF00L28 - -6./ Each example folder has an 'abstract.txt' file, this is where user can start - -7./ Below is list of drivers and examples: - - ADC (lpc18xx_adc): - + ADC_Interrupt - + ADC_Polling - + ADC_Burst - + ADC_Dma - - ATIMER (lpc18xx_atimer): - + ATIMER_interrupt - - PWR (lpc18xx_clkpwr): - + CLKPWR_Sleep - + CLKPWR_DeepSleep - - DAC (lpc18xx_dac): - + DAC_WaveGenerator - + DAC_Dma - - EMAC (lpc18xx_emac): - + EMAC_EasyWeb - - EMC (no driver): - + EXT_SDRAM - + NOR_FLASH - - GPDMA (lpc18xx_gpdma): - + GPDMA_Ram2Ram - + GPDMA_LinkList - - GPIO (lpc18xx_gpio): - + GPIO_LedBlinky - - I2C (lpc18xx_i2c): - + I2C_Master - - I2S (lpc18xx_i2s): - + I2S_Audio - - LCD (lpc18xx_lcd) - - MCPWM (lpc18xx_mcpwm): - + MCPWM_Simple - - SCU (lpc18xx_scu) - - QEI (lpc18xx_qei): - + QEI_Velo - - RIT (lpc18xx_rit): - + RIT_Interrupt - - RTC (lpc18xx_rtc): - + RTC_Calib - + RTC_Alarm - - SSP (lpc18xx_ssp): - + SSP_SPI - + SSP_Microwire - + SSP_TI - - TIMER (lpc18xx_timer): - + TIMER_Capture - + TIMER_MatchInterrupt - + TIMER_FreqMeasure - - UART (lpc18xx_uart): - + UART_Autobaud - + UART_Dma - + UART_Interrupt - + UART_Polling - + UART_RS485 - - SCT(LPC18xx_SCT): - + SCT_Capture - + SCT_Match - - WWDT (lpc18xx_wwdt): - + WWDT_Interrupt - - CORTEXM3 (no driver): - + CORTEXM3_BitBanding - + CORTEXM3_MPU - + CORTEXM3_PriviledgeMode - - USBDEV (no driver): - + USBDEV_VirtualCOM - + USBDEV_MassStorage - - NVIC (no driver): - + NVIC_Priority - + NVIC_VecRelocation - - EVRT (lpc18xx_evrt) - \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/readme.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/readme.txt deleted file mode 100644 index cc002c2cb..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/readme.txt +++ /dev/null @@ -1,9 +0,0 @@ -NXP's documentation for their peripheral driver library can be found -as a Microsoft Compiled HTML Help file (.chm) within the LPC18xx -CMSIS Standard Peripheral Driver Library download on NXP's website. - -At the time of writing, this can be found at the following link: - -http://lpcware.com/file_filter/nxp?term_node_tid_depth=All&term_node_tid_depth_1=103 - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/LPC18xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/LPC18xx.h deleted file mode 100644 index 32fbff3b5..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/LPC18xx.h +++ /dev/null @@ -1,32280 +0,0 @@ - -/****************************************************************************************************//** - * @file LPC18xx.h - * - * @status EXPERIMENTAL - * - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * default LPC18xx Device Series - * - * @version V18 - * @date 1. December 2011 - * - * @note Generated with SVDConv V2.6 Build 6c on Thursday, 01.12.2011 08:48:39 - * - * from CMSIS SVD File 'LPC18xxv18.xml' Version 18, - * created on Tuesday, 22.11.2011 18:06:23, last modified on Tuesday, 22.11.2011 18:38:38 - * - *******************************************************************************************************/ - - - -/** @addtogroup (null) - * @{ - */ - -/** @addtogroup LPC18xx - * @{ - */ - -#ifndef __LPC18XX_H__ -#define __LPC18XX_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - - -/******************************************** -** Start of section using anonymous unions ** -*********************************************/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma push - #pragma language=extended -#else - #error Not supported compiler type -#endif - - - /* Interrupt Number Definition */ - -typedef enum { -// ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -// --------------------------- LPC18xx Specific Interrupt Numbers ------------------------------- - DAC_IRQn = 0, /*!< 0 DAC */ - RESERVED0_IRQn = 1, /*!< 1 M0a */ - DMA_IRQn = 2, /*!< 2 DMA */ - RESERVED1_IRQn = 3, /*!< 3 EZH/EDM */ - RESERVED2_IRQn = 4, - ETHERNET_IRQn = 5, /*!< 5 ETHERNET */ - SDIO_IRQn = 6, /*!< 6 SDIO */ - LCD_IRQn = 7, /*!< 7 LCD */ - USB0_IRQn = 8, /*!< 8 USB0 */ - USB1_IRQn = 9, /*!< 9 USB1 */ - SCT_IRQn = 10, /*!< 10 SCT */ - RITIMER_IRQn = 11, /*!< 11 RITIMER */ - TIMER0_IRQn = 12, /*!< 12 TIMER0 */ - TIMER1_IRQn = 13, /*!< 13 TIMER1 */ - TIMER2_IRQn = 14, /*!< 14 TIMER2 */ - TIMER3_IRQn = 15, /*!< 15 TIMER3 */ - MCPWM_IRQn = 16, /*!< 16 MCPWM */ - ADC0_IRQn = 17, /*!< 17 ADC0 */ - I2C0_IRQn = 18, /*!< 18 I2C0 */ - I2C1_IRQn = 19, /*!< 19 I2C1 */ - RESERVED3_IRQn = 20, - ADC1_IRQn = 21, /*!< 21 ADC1 */ - SSP0_IRQn = 22, /*!< 22 SSP0 */ - SSP1_IRQn = 23, /*!< 23 SSP1 */ - USART0_IRQn = 24, /*!< 24 USART0 */ - UART1_IRQn = 25, /*!< 25 UART1 */ - USART2_IRQn = 26, /*!< 26 USART2 */ - USART3_IRQn = 27, /*!< 27 USART3 */ - I2S0_IRQn = 28, /*!< 28 I2S0 */ - I2S1_IRQn = 29, /*!< 29 I2S1 */ - RESERVED4_IRQn = 30, - RESERVED5_IRQn = 31, - PIN_INT0_IRQn = 32, /*!< 32 PIN_INT0 */ - PIN_INT1_IRQn = 33, /*!< 33 PIN_INT1 */ - PIN_INT2_IRQn = 34, /*!< 34 PIN_INT2 */ - PIN_INT3_IRQn = 35, /*!< 35 PIN_INT3 */ - PIN_INT4_IRQn = 36, /*!< 36 PIN_INT4 */ - PIN_INT5_IRQn = 37, /*!< 37 PIN_INT5 */ - PIN_INT6_IRQn = 38, /*!< 38 PIN_INT6 */ - PIN_INT7_IRQn = 39, /*!< 39 PIN_INT7 */ - GINT0_IRQn = 40, /*!< 40 GINT0 */ - GINT1_IRQn = 41, /*!< 41 GINT1 */ - EVENTROUTER_IRQn = 42, /*!< 42 EVENTROUTER */ - C_CAN1_IRQn = 43, /*!< 43 C_CAN1 */ - RESERVED6_IRQn = 44, - RESERVED7_IRQn = 45, /*!< 45 VADC */ - ATIMER_IRQn = 46, /*!< 46 ATIMER */ - RTC_IRQn = 47, /*!< 47 RTC */ - RESERVED8_IRQn = 48, - WWDT_IRQn = 49, /*!< 49 WWDT */ - RESERVED9_IRQn = 50, - C_CAN0_IRQn = 51, /*!< 51 C_CAN0 */ - QEI_IRQn = 52, /*!< 52 QEI */ -} IRQn_Type; - - /* Event Router Input (ERI) Number Definitions */ -typedef enum { - WAKEUP0_ERIn = 0, - WAKEUP1_ERIn = 1, - WAKEUP2_ERIn = 2, - WAKEUP3_ERIn = 3, - ATIMER_ERIn = 4, - RTC_ERIn = 5, - BOD1_ERIn = 6, /* Bod trip 1 */ - WWDT_ERIn = 7, - ETH_ERIn = 8, - USB0_ERIn = 9, - USB1_ERIn = 10, - SDIO_ERIn = 11, - CAN_ERIn = 12, /* CAN0/1 or'ed */ - TIM2_ERIn = 13, - TIM6_ERIn = 14, - QEI_ERIn = 15, - TIM14_ERIn = 16, - RESERVED0_ERIn = 17, /* M0s */ - RESERVED1_ERIn = 18, /* M3/M4 */ - RESET_ERIn = 19 -}ERIn_Type; - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* Processor and Core Peripheral Section */ /* Configuration of the Template Processor and Core Peripherals */ - -#define __CM3_REV 0x0101 /*!< Cortex-M3 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */ -//#include /*!< Cortex-M3 processor and core peripherals */ - -#include "system_LPC18xx.h" /*!< LPC18xx System */ - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SCT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT) - */ - -#define CONFIG_SCT_nEV (16) /* Number of events */ -#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */ -#define CONFIG_SCT_nOU (16) /* Number of outputs */ - -typedef struct -{ - __IO uint32_t CONFIG; /* 0x000 Configuration Register */ - union { - __IO uint32_t CTRL_U; /* 0x004 Control Register */ - struct { - __IO uint16_t CTRL_L; /* 0x004 low control register */ - __IO uint16_t CTRL_H; /* 0x006 high control register */ - }; - }; - __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */ - __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */ - __IO uint16_t HALT_L; /* 0x00C halt register for counter L */ - __IO uint16_t HALT_H; /* 0x00E halt register for counter H */ - __IO uint16_t STOP_L; /* 0x010 stop register for counter L */ - __IO uint16_t STOP_H; /* 0x012 stop register for counter H */ - __IO uint16_t START_L; /* 0x014 start register for counter L */ - __IO uint16_t START_H; /* 0x016 start register for counter H */ - uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */ - union { - __IO uint32_t COUNT_U; /* 0x040 counter register */ - struct { - __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */ - __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */ - }; - }; - __IO uint16_t STATE_L; /* 0x044 state register for counter L */ - __IO uint16_t STATE_H; /* 0x046 state register for counter H */ - __I uint32_t INPUT; /* 0x048 input register */ - __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */ - __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */ - __IO uint32_t OUTPUT; /* 0x050 output register */ - __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */ - __IO uint32_t RES; /* 0x058 conflict resolution register */ - __IO uint32_t DMA0REQUEST; /* 0x05C DMA0 Request Register */ - __IO uint32_t DMA1REQUEST; /* 0x060 DMA1 Request Register */ - uint32_t RESERVED2[35]; /* 0x064-0x0EC reserved */ - __IO uint32_t EVEN; /* 0x0F0 event enable register */ - __IO uint32_t EVFLAG; /* 0x0F4 event flag register */ - __IO uint32_t CONEN; /* 0x0F8 conflict enable register */ - __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */ - - union { - __IO union { /* 0x100-... Match / Capture value */ - uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCH[i].L Access to L value */ - uint16_t H; /* SCTMATCH[i].H Access to H value */ - }; - } MATCH[CONFIG_SCT_nRG]; - __I union { - uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAP[i].L Access to H value */ - uint16_t H; /* SCTCAP[i].H Access to H value */ - }; - } CAP[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ - - union { - __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ - __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ - }; - uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ - union { - __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ - __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ - }; - uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ - - union { - __IO union { /* 0x200-... Match Reload / Capture Control value */ - uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCHREL[i].L Access to L value */ - uint16_t H; /* SCTMATCHREL[i].H Access to H value */ - }; - } MATCHREL[CONFIG_SCT_nRG]; - __IO union { - uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ - uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ - }; - } CAPCTRL[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ - - union { - __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ - __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ - }; - uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ - union { - __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ - __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ - }; - uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ - - __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ - uint32_t STATE; /* Event State Register */ - uint32_t CTRL; /* Event Control Register */ - } EVENT[CONFIG_SCT_nEV]; - - uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ - - __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ - uint32_t SET; /* Output n Set Register */ - uint32_t CLR; /* Output n Clear Register */ - } OUT[CONFIG_SCT_nOU]; - - uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ - - __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ - -} LPC_SCT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPDMA ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (GPDMA) - */ - -typedef struct { /*!< (@ 0x40002000) GPDMA Structure */ - __I uint32_t INTSTAT; /*!< (@ 0x40002000) DMA Interrupt Status Register */ - __I uint32_t INTTCSTAT; /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */ - __O uint32_t INTTCCLEAR; /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */ - __I uint32_t INTERRSTAT; /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */ - __O uint32_t INTERRCLR; /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */ - __I uint32_t RAWINTTCSTAT; /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */ - __I uint32_t RAWINTERRSTAT; /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */ - __I uint32_t ENBLDCHNS; /*!< (@ 0x4000201C) DMA Enabled Channel Register */ - __IO uint32_t SOFTBREQ; /*!< (@ 0x40002020) DMA Software Burst Request Register */ - __IO uint32_t SOFTSREQ; /*!< (@ 0x40002024) DMA Software Single Request Register */ - __IO uint32_t SOFTLBREQ; /*!< (@ 0x40002028) DMA Software Last Burst Request Register */ - __IO uint32_t SOFTLSREQ; /*!< (@ 0x4000202C) DMA Software Last Single Request Register */ - __IO uint32_t CONFIG; /*!< (@ 0x40002030) DMA Configuration Register */ - __IO uint32_t SYNC; /*!< (@ 0x40002034) DMA Synchronization Register */ - __I uint32_t RESERVED0[50]; - __IO uint32_t C0SRCADDR; /*!< (@ 0x40002100) DMA Channel Source Address Register */ - __IO uint32_t C0DESTADDR; /*!< (@ 0x40002104) DMA Channel Destination Address Register */ - __IO uint32_t C0LLI; /*!< (@ 0x40002108) DMA Channel Linked List Item Register */ - __IO uint32_t C0CONTROL; /*!< (@ 0x4000210C) DMA Channel Control Register */ - __IO uint32_t C0CONFIG; /*!< (@ 0x40002110) DMA Channel Configuration Register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t C1SRCADDR; /*!< (@ 0x40002120) DMA Channel Source Address Register */ - __IO uint32_t C1DESTADDR; /*!< (@ 0x40002124) DMA Channel Destination Address Register */ - __IO uint32_t C1LLI; /*!< (@ 0x40002128) DMA Channel Linked List Item Register */ - __IO uint32_t C1CONTROL; /*!< (@ 0x4000212C) DMA Channel Control Register */ - __IO uint32_t C1CONFIG; /*!< (@ 0x40002130) DMA Channel Configuration Register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t C2SRCADDR; /*!< (@ 0x40002140) DMA Channel Source Address Register */ - __IO uint32_t C2DESTADDR; /*!< (@ 0x40002144) DMA Channel Destination Address Register */ - __IO uint32_t C2LLI; /*!< (@ 0x40002148) DMA Channel Linked List Item Register */ - __IO uint32_t C2CONTROL; /*!< (@ 0x4000214C) DMA Channel Control Register */ - __IO uint32_t C2CONFIG; /*!< (@ 0x40002150) DMA Channel Configuration Register */ - __I uint32_t RESERVED3[3]; - __IO uint32_t C3SRCADDR; /*!< (@ 0x40002160) DMA Channel Source Address Register */ - __IO uint32_t C3DESTADDR; /*!< (@ 0x40002164) DMA Channel Destination Address Register */ - __IO uint32_t C3LLI; /*!< (@ 0x40002168) DMA Channel Linked List Item Register */ - __IO uint32_t C3CONTROL; /*!< (@ 0x4000216C) DMA Channel Control Register */ - __IO uint32_t C3CONFIG; /*!< (@ 0x40002170) DMA Channel Configuration Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t C4SRCADDR; /*!< (@ 0x40002180) DMA Channel Source Address Register */ - __IO uint32_t C4DESTADDR; /*!< (@ 0x40002184) DMA Channel Destination Address Register */ - __IO uint32_t C4LLI; /*!< (@ 0x40002188) DMA Channel Linked List Item Register */ - __IO uint32_t C4CONTROL; /*!< (@ 0x4000218C) DMA Channel Control Register */ - __IO uint32_t C4CONFIG; /*!< (@ 0x40002190) DMA Channel Configuration Register */ - __I uint32_t RESERVED5[3]; - __IO uint32_t C5SRCADDR; /*!< (@ 0x400021A0) DMA Channel Source Address Register */ - __IO uint32_t C5DESTADDR; /*!< (@ 0x400021A4) DMA Channel Destination Address Register */ - __IO uint32_t C5LLI; /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */ - __IO uint32_t C5CONTROL; /*!< (@ 0x400021AC) DMA Channel Control Register */ - __IO uint32_t C5CONFIG; /*!< (@ 0x400021B0) DMA Channel Configuration Register */ - __I uint32_t RESERVED6[3]; - __IO uint32_t C6SRCADDR; /*!< (@ 0x400021C0) DMA Channel Source Address Register */ - __IO uint32_t C6DESTADDR; /*!< (@ 0x400021C4) DMA Channel Destination Address Register */ - __IO uint32_t C6LLI; /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */ - __IO uint32_t C6CONTROL; /*!< (@ 0x400021CC) DMA Channel Control Register */ - __IO uint32_t C6CONFIG; /*!< (@ 0x400021D0) DMA Channel Configuration Register */ - __I uint32_t RESERVED7[3]; - __IO uint32_t C7SRCADDR; /*!< (@ 0x400021E0) DMA Channel Source Address Register */ - __IO uint32_t C7DESTADDR; /*!< (@ 0x400021E4) DMA Channel Destination Address Register */ - __IO uint32_t C7LLI; /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */ - __IO uint32_t C7CONTROL; /*!< (@ 0x400021EC) DMA Channel Control Register */ - __IO uint32_t C7CONFIG; /*!< (@ 0x400021F0) DMA Channel Configuration Register */ -} LPC_GPDMA_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SDMMC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a (SDMMC) - */ - -typedef struct { /*!< (@ 0x40004000) SDMMC Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40004000) Control Register */ - __IO uint32_t PWREN; /*!< (@ 0x40004004) Power Enable Register */ - __IO uint32_t CLKDIV; /*!< (@ 0x40004008) Clock Divider Register */ - __IO uint32_t CLKSRC; /*!< (@ 0x4000400C) SD Clock Source Register */ - __IO uint32_t CLKENA; /*!< (@ 0x40004010) Clock Enable Register */ - __IO uint32_t TMOUT; /*!< (@ 0x40004014) Timeout Register */ - __IO uint32_t CTYPE; /*!< (@ 0x40004018) Card Type Register */ - __IO uint32_t BLKSIZ; /*!< (@ 0x4000401C) Block Size Register */ - __IO uint32_t BYTCNT; /*!< (@ 0x40004020) Byte Count Register */ - __IO uint32_t INTMASK; /*!< (@ 0x40004024) Interrupt Mask Register */ - __IO uint32_t CMDARG; /*!< (@ 0x40004028) Command Argument Register */ - __IO uint32_t CMD; /*!< (@ 0x4000402C) Command Register */ - __I uint32_t RESP0; /*!< (@ 0x40004030) Response Register 0 */ - __I uint32_t RESP1; /*!< (@ 0x40004034) Response Register 1 */ - __I uint32_t RESP2; /*!< (@ 0x40004038) Response Register 2 */ - __I uint32_t RESP3; /*!< (@ 0x4000403C) Response Register 3 */ - __I uint32_t MINTSTS; /*!< (@ 0x40004040) Masked Interrupt Status Register */ - __IO uint32_t RINTSTS; /*!< (@ 0x40004044) Raw Interrupt Status Register */ - __I uint32_t STATUS; /*!< (@ 0x40004048) Status Register */ - __IO uint32_t FIFOTH; /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */ - __I uint32_t CDETECT; /*!< (@ 0x40004050) Card Detect Register */ - __I uint32_t WRTPRT; /*!< (@ 0x40004054) Write Protect Register */ - __IO uint32_t GPIO; /*!< (@ 0x40004058) General Purpose Input/Output Register */ - __I uint32_t TCBCNT; /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */ - __I uint32_t TBBCNT; /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */ - __IO uint32_t DEBNCE; /*!< (@ 0x40004064) Debounce Count Register */ - __IO uint32_t USRID; /*!< (@ 0x40004068) User ID Register */ - __I uint32_t VERID; /*!< (@ 0x4000406C) Version ID Register */ - __I uint32_t RESERVED0; - __IO uint32_t UHS_REG; /*!< (@ 0x40004074) UHS-1 Register */ - __IO uint32_t RST_N; /*!< (@ 0x40004078) Hardware Reset */ - __I uint32_t RESERVED1; - __IO uint32_t BMOD; /*!< (@ 0x40004080) Bus Mode Register */ - __O uint32_t PLDMND; /*!< (@ 0x40004084) Poll Demand Register */ - __IO uint32_t DBADDR; /*!< (@ 0x40004088) Descriptor List Base Address Register */ - __IO uint32_t IDSTS; /*!< (@ 0x4000408C) Internal DMAC Status Register */ - __IO uint32_t IDINTEN; /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */ - __I uint32_t DSCADDR; /*!< (@ 0x40004094) Current Host Descriptor Address Register */ - __I uint32_t BUFADDR; /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */ -} LPC_SDMMC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- EMC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7 (EMC) - */ - -typedef struct { /*!< (@ 0x40005000) EMC Structure */ - __IO uint32_t CONTROL; /*!< (@ 0x40005000) Controls operation of the memory controller. */ - __I uint32_t STATUS; /*!< (@ 0x40005004) Provides EMC status information. */ - __IO uint32_t CONFIG; /*!< (@ 0x40005008) Configures operation of the memory controller. */ - __I uint32_t RESERVED0[5]; - __IO uint32_t DYNAMICCONTROL; /*!< (@ 0x40005020) Controls dynamic memory operation. */ - __IO uint32_t DYNAMICREFRESH; /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */ - __IO uint32_t DYNAMICREADCONFIG; /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */ - __I uint32_t RESERVED1; - __IO uint32_t DYNAMICRP; /*!< (@ 0x40005030) Selects the precharge command period. */ - __IO uint32_t DYNAMICRAS; /*!< (@ 0x40005034) Selects the active to precharge command period. */ - __IO uint32_t DYNAMICSREX; /*!< (@ 0x40005038) Selects the self-refresh exit time. */ - __IO uint32_t DYNAMICAPR; /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */ - __IO uint32_t DYNAMICDAL; /*!< (@ 0x40005040) Selects the data-in to active command time. */ - __IO uint32_t DYNAMICWR; /*!< (@ 0x40005044) Selects the write recovery time. */ - __IO uint32_t DYNAMICRC; /*!< (@ 0x40005048) Selects the active to active command period. */ - __IO uint32_t DYNAMICRFC; /*!< (@ 0x4000504C) Selects the auto-refresh period. */ - __IO uint32_t DYNAMICXSR; /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */ - __IO uint32_t DYNAMICRRD; /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */ - __IO uint32_t DYNAMICMRD; /*!< (@ 0x40005058) Selects the load mode register to active command time. */ - __I uint32_t RESERVED2[9]; - __IO uint32_t STATICEXTENDEDWAIT; /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */ - __I uint32_t RESERVED3[31]; - __IO uint32_t DYNAMICCONFIG0; /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */ - __IO uint32_t DYNAMICRASCAS0; /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */ - __I uint32_t RESERVED4[6]; - __IO uint32_t DYNAMICCONFIG1; /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */ - __IO uint32_t DYNAMICRASCAS1; /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */ - __I uint32_t RESERVED5[6]; - __IO uint32_t DYNAMICCONFIG2; /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */ - __IO uint32_t DYNAMICRASCAS2; /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */ - __I uint32_t RESERVED6[6]; - __IO uint32_t DYNAMICCONFIG3; /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */ - __IO uint32_t DYNAMICRASCAS3; /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */ - __I uint32_t RESERVED7[38]; - __IO uint32_t STATICCONFIG0; /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */ - __IO uint32_t STATICWAITWEN0; /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */ - __IO uint32_t STATICWAITOEN0; /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */ - __IO uint32_t STATICWAITRD0; /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */ - __IO uint32_t STATICWAITPAG0; /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */ - __IO uint32_t STATICWAITWR0; /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */ - __IO uint32_t STATICWAITTURN0; /*!< (@ 0x40005218) Selects bus turnaround cycles */ - __I uint32_t RESERVED8; - __IO uint32_t STATICCONFIG1; /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */ - __IO uint32_t STATICWAITWEN1; /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */ - __IO uint32_t STATICWAITOEN1; /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */ - __IO uint32_t STATICWAITRD1; /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */ - __IO uint32_t STATICWAITPAG1; /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */ - __IO uint32_t STATICWAITWR1; /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */ - __IO uint32_t STATICWAITTURN1; /*!< (@ 0x40005238) Selects bus turnaround cycles */ - __I uint32_t RESERVED9; - __IO uint32_t STATICCONFIG2; /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */ - __IO uint32_t STATICWAITWEN2; /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */ - __IO uint32_t STATICWAITOEN2; /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */ - __IO uint32_t STATICWAITRD2; /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */ - __IO uint32_t STATICWAITPAG2; /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */ - __IO uint32_t STATICWAITWR2; /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */ - __IO uint32_t STATICWAITTURN2; /*!< (@ 0x40005258) Selects bus turnaround cycles */ - __I uint32_t RESERVED10; - __IO uint32_t STATICCONFIG3; /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */ - __IO uint32_t STATICWAITWEN3; /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */ - __IO uint32_t STATICWAITOEN3; /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */ - __IO uint32_t STATICWAITRD3; /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */ - __IO uint32_t STATICWAITPAG3; /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */ - __IO uint32_t STATICWAITWR3; /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */ - __IO uint32_t STATICWAITTURN3; /*!< (@ 0x40005278) Selects bus turnaround cycles */ -} LPC_EMC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- USB0 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB0) - */ - -typedef struct { /*!< (@ 0x40006000) USB0 Structure */ - __I uint32_t RESERVED0[64]; - __I uint32_t CAPLENGTH; /*!< (@ 0x40006100) Capability register length */ - __I uint32_t HCSPARAMS; /*!< (@ 0x40006104) Host controller structural parameters */ - __I uint32_t HCCPARAMS; /*!< (@ 0x40006108) Host controller capability parameters */ - __I uint32_t RESERVED1[5]; - __I uint32_t DCIVERSION; /*!< (@ 0x40006120) Device interface version number */ - __I uint32_t RESERVED2[7]; - - union { - __IO uint32_t USBCMD_H; /*!< (@ 0x40006140) USB command (host mode) */ - __IO uint32_t USBCMD_D; /*!< (@ 0x40006140) USB command (device mode) */ - }; - - union { - __IO uint32_t USBSTS_H; /*!< (@ 0x40006144) USB status (host mode) */ - __IO uint32_t USBSTS_D; /*!< (@ 0x40006144) USB status (device mode) */ - }; - - union { - __IO uint32_t USBINTR_H; /*!< (@ 0x40006148) USB interrupt enable (host mode) */ - __IO uint32_t USBINTR_D; /*!< (@ 0x40006148) USB interrupt enable (device mode) */ - }; - - union { - __IO uint32_t FRINDEX_H; /*!< (@ 0x4000614C) USB frame index (host mode) */ - __IO uint32_t FRINDEX_D; /*!< (@ 0x4000614C) USB frame index (device mode) */ - }; - __I uint32_t RESERVED3; - - union { - __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40006154) Frame list base address (host mode) */ - __IO uint32_t DEVICEADDR; /*!< (@ 0x40006154) USB device address (device mode) */ - }; - - union { - __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */ - __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */ - }; - __IO uint32_t TTCTRL; /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */ - __IO uint32_t BURSTSIZE; /*!< (@ 0x40006160) Programmable burst size */ - __IO uint32_t TXFILLTUNING; /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */ - __I uint32_t RESERVED4[3]; - __IO uint32_t BINTERVAL; /*!< (@ 0x40006174) Length of virtual frame */ - __IO uint32_t ENDPTNAK; /*!< (@ 0x40006178) Endpoint NAK (device mode) */ - __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */ - __I uint32_t RESERVED5; - - union { - __IO uint32_t PORTSC1_H; /*!< (@ 0x40006184) Port 1 status/control (host mode) */ - __IO uint32_t PORTSC1_D; /*!< (@ 0x40006184) Port 1 status/control (device mode) */ - }; - __I uint32_t RESERVED6[7]; - __IO uint32_t OTGSC; /*!< (@ 0x400061A4) OTG status and control */ - - union { - __IO uint32_t USBMODE_H; /*!< (@ 0x400061A8) USB mode (host mode) */ - __IO uint32_t USBMODE_D; /*!< (@ 0x400061A8) USB device mode (device mode) */ - }; - __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400061AC) Endpoint setup status */ - __IO uint32_t ENDPTPRIME; /*!< (@ 0x400061B0) Endpoint initialization */ - __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400061B4) Endpoint de-initialization */ - __I uint32_t ENDPTSTAT; /*!< (@ 0x400061B8) Endpoint status */ - __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400061BC) Endpoint complete */ - __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400061C0) Endpoint control 0 */ - __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400061C4) Endpoint control */ - __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400061C8) Endpoint control */ - __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400061CC) Endpoint control */ - __IO uint32_t ENDPTCTRL4; /*!< (@ 0x400061D0) Endpoint control */ - __IO uint32_t ENDPTCTRL5; /*!< (@ 0x400061D4) Endpoint control */ -} LPC_USB0_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- USB1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB1) - */ - -typedef struct { /*!< (@ 0x40007000) USB1 Structure */ - __I uint32_t RESERVED0[64]; - __I uint32_t CAPLENGTH; /*!< (@ 0x40007100) Capability register length */ - __I uint32_t HCSPARAMS; /*!< (@ 0x40007104) Host controller structural parameters */ - __I uint32_t HCCPARAMS; /*!< (@ 0x40007108) Host controller capability parameters */ - __I uint32_t RESERVED1[5]; - __I uint32_t DCIVERSION; /*!< (@ 0x40007120) Device interface version number */ - __I uint32_t RESERVED2[7]; - - union { - __IO uint32_t USBCMD_H; /*!< (@ 0x40007140) USB command (host mode) */ - __IO uint32_t USBCMD_D; /*!< (@ 0x40007140) USB command (device mode) */ - }; - - union { - __IO uint32_t USBSTS_H; /*!< (@ 0x40007144) USB status (host mode) */ - __IO uint32_t USBSTS_D; /*!< (@ 0x40007144) USB status (device mode) */ - }; - - union { - __IO uint32_t USBINTR_H; /*!< (@ 0x40007148) USB interrupt enable (host mode) */ - __IO uint32_t USBINTR_D; /*!< (@ 0x40007148) USB interrupt enable (device mode) */ - }; - - union { - __IO uint32_t FRINDEX_H; /*!< (@ 0x4000714C) USB frame index (host mode) */ - __I uint32_t FRINDEX_D; /*!< (@ 0x4000714C) USB frame index (device mode) */ - }; - __I uint32_t RESERVED3; - - union { - __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40007154) Frame list base address */ - __IO uint32_t DEVICEADDR; /*!< (@ 0x40007154) USB device address */ - }; - - union { - __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */ - __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */ - }; - __IO uint32_t TTCTRL; /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */ - __IO uint32_t BURSTSIZE; /*!< (@ 0x40007160) Programmable burst size */ - __IO uint32_t TXFILLTUNING; /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */ - __I uint32_t RESERVED4[2]; - __IO uint32_t ULPIVIEWPORT; /*!< (@ 0x40007170) ULPI viewport */ - __IO uint32_t BINTERVAL; /*!< (@ 0x40007174) Length of virtual frame */ - __IO uint32_t ENDPTNAK; /*!< (@ 0x40007178) Endpoint NAK (device mode) */ - __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */ - __I uint32_t RESERVED5; - - union { - __IO uint32_t PORTSC1_H; /*!< (@ 0x40007184) Port 1 status/control (host mode) */ - __IO uint32_t PORTSC1_D; /*!< (@ 0x40007184) Port 1 status/control (device mode) */ - }; - __I uint32_t RESERVED6[8]; - - union { - __IO uint32_t USBMODE_H; /*!< (@ 0x400071A8) USB mode (host mode) */ - __IO uint32_t USBMODE_D; /*!< (@ 0x400071A8) USB mode (device mode) */ - }; - __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400071AC) Endpoint setup status */ - __IO uint32_t ENDPTPRIME; /*!< (@ 0x400071B0) Endpoint initialization */ - __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400071B4) Endpoint de-initialization */ - __I uint32_t ENDPTSTAT; /*!< (@ 0x400071B8) Endpoint status */ - __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400071BC) Endpoint complete */ - __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400071C0) Endpoint control 0 */ - __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400071C4) Endpoint control */ - __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400071C8) Endpoint control */ - __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400071CC) Endpoint control */ -} LPC_USB1_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- LCD ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7 (LCD) - */ - -typedef struct { /*!< (@ 0x40008000) LCD Structure */ - __IO uint32_t TIMH; /*!< (@ 0x40008000) Horizontal Timing Control register */ - __IO uint32_t TIMV; /*!< (@ 0x40008004) Vertical Timing Control register */ - __IO uint32_t POL; /*!< (@ 0x40008008) Clock and Signal Polarity Control register */ - __IO uint32_t LE; /*!< (@ 0x4000800C) Line End Control register */ - __IO uint32_t UPBASE; /*!< (@ 0x40008010) Upper Panel Frame Base Address register */ - __IO uint32_t LPBASE; /*!< (@ 0x40008014) Lower Panel Frame Base Address register */ - __IO uint32_t CTRL; /*!< (@ 0x40008018) LCD Control register */ - __IO uint32_t INTMSK; /*!< (@ 0x4000801C) Interrupt Mask register */ - __I uint32_t INTRAW; /*!< (@ 0x40008020) Raw Interrupt Status register */ - __I uint32_t INTSTAT; /*!< (@ 0x40008024) Masked Interrupt Status register */ - __O uint32_t INTCLR; /*!< (@ 0x40008028) Interrupt Clear register */ - __I uint32_t UPCURR; /*!< (@ 0x4000802C) Upper Panel Current Address Value register */ - __I uint32_t LPCURR; /*!< (@ 0x40008030) Lower Panel Current Address Value register */ - __I uint32_t RESERVED0[115]; - __IO uint32_t PAL[256]; /*!< (@ 0x40008200) 256x16-bit Color Palette registers */ - __I uint32_t RESERVED1[128]; - __IO uint32_t CRSR_IMG[256]; /*!< (@ 0x40008800) Cursor Image registers */ - __IO uint32_t CRSR_CTRL; /*!< (@ 0x40008C00) Cursor Control register */ - __IO uint32_t CRSR_CFG; /*!< (@ 0x40008C04) Cursor Configuration register */ - __IO uint32_t CRSR_PAL0; /*!< (@ 0x40008C08) Cursor Palette register 0 */ - __IO uint32_t CRSR_PAL1; /*!< (@ 0x40008C0C) Cursor Palette register 1 */ - __IO uint32_t CRSR_XY; /*!< (@ 0x40008C10) Cursor XY Position register */ - __IO uint32_t CRSR_CLIP; /*!< (@ 0x40008C14) Cursor Clip Position register */ - __I uint32_t RESERVED2[2]; - __IO uint32_t CRSR_INTMSK; /*!< (@ 0x40008C20) Cursor Interrupt Mask register */ - __O uint32_t CRSR_INTCLR; /*!< (@ 0x40008C24) Cursor Interrupt Clear register */ - __I uint32_t CRSR_INTRAW; /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */ - __I uint32_t CRSR_INTSTAT; /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */ -} LPC_LCD_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- ETHERNET ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=1/20/2011 Major revision=0 Minor revision=7 (ETHERNET) - */ - -typedef struct { /*!< (@ 0x40010000) ETHERNET Structure */ - __IO uint32_t MAC_CONFIG; /*!< (@ 0x40010000) MAC configuration register */ - __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x40010004) MAC frame filter */ - __IO uint32_t MAC_HASHTABLE_HIGH; /*!< (@ 0x40010008) Hash table high register */ - __IO uint32_t MAC_HASHTABLE_LOW; /*!< (@ 0x4001000C) Hash table low register */ - __IO uint32_t MAC_MII_ADDR; /*!< (@ 0x40010010) MII address register */ - __IO uint32_t MAC_MII_DATA; /*!< (@ 0x40010014) MII data register */ - __IO uint32_t MAC_FLOW_CTRL; /*!< (@ 0x40010018) Flow control register */ - __IO uint32_t MAC_VLAN_TAG; /*!< (@ 0x4001001C) VLAN tag register */ - __I uint32_t RESERVED0; - __IO uint32_t MAC_DEBUG; /*!< (@ 0x40010024) Debug register */ - __IO uint32_t MAC_RWAKE_FRFLT; /*!< (@ 0x40010028) Remote wake-up frame filter */ - __IO uint32_t MAC_PMT_CTRL_STAT; /*!< (@ 0x4001002C) PMT control and status */ - __I uint32_t RESERVED1[2]; - __IO uint32_t MAC_INTR; /*!< (@ 0x40010038) Interrupt status register */ - __IO uint32_t MAC_INTR_MASK; /*!< (@ 0x4001003C) Interrupt mask register */ - __IO uint32_t MAC_ADDR0_HIGH; /*!< (@ 0x40010040) MAC address 0 high register */ - __IO uint32_t MAC_ADDR0_LOW; /*!< (@ 0x40010044) MAC address 0 low register */ - __I uint32_t RESERVED2[430]; - __IO uint32_t MAC_TIMESTP_CTRL; /*!< (@ 0x40010700) Time stamp control register */ - __I uint32_t RESERVED3[575]; - __IO uint32_t DMA_BUS_MODE; /*!< (@ 0x40011000) Bus Mode Register */ - __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< (@ 0x40011004) Transmit poll demand register */ - __IO uint32_t DMA_REC_POLL_DEMAND; /*!< (@ 0x40011008) Receive poll demand register */ - __IO uint32_t DMA_REC_DES_ADDR; /*!< (@ 0x4001100C) Receive descriptor list address register */ - __IO uint32_t DMA_TRANS_DES_ADDR; /*!< (@ 0x40011010) Transmit descriptor list address register */ - __IO uint32_t DMA_STAT; /*!< (@ 0x40011014) Status register */ - __IO uint32_t DMA_OP_MODE; /*!< (@ 0x40011018) Operation mode register */ - __IO uint32_t DMA_INT_EN; /*!< (@ 0x4001101C) Interrupt enable register */ - __IO uint32_t DMA_MFRM_BUFOF; /*!< (@ 0x40011020) Missed frame and buffer overflow register */ - __IO uint32_t DMA_REC_INT_WDT; /*!< (@ 0x40011024) Receive interrupt watchdog timer register */ - __I uint32_t RESERVED4[8]; - __IO uint32_t DMA_CURHOST_TRANS_DES; /*!< (@ 0x40011048) Current host transmit descriptor register */ - __IO uint32_t DMA_CURHOST_REC_DES; /*!< (@ 0x4001104C) Current host receive descriptor register */ - __IO uint32_t DMA_CURHOST_TRANS_BUF; /*!< (@ 0x40011050) Current host transmit buffer address register */ - __IO uint32_t DMA_CURHOST_REC_BUF; /*!< (@ 0x40011054) Current host receive buffer address register */ -} LPC_ETHERNET_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- ATIMER ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6 (ATIMER) - */ - -typedef struct { /*!< (@ 0x40040000) ATIMER Structure */ - __IO uint32_t DOWNCOUNTER; /*!< (@ 0x40040000) Downcounter register */ - __IO uint32_t PRESET; /*!< (@ 0x40040004) Preset value register */ - __I uint32_t RESERVED0[1012]; - __O uint32_t CLR_EN; /*!< (@ 0x40040FD8) Interrupt clear enable register */ - __O uint32_t SET_EN; /*!< (@ 0x40040FDC) Interrupt set enable register */ - __I uint32_t STATUS; /*!< (@ 0x40040FE0) Status register */ - __I uint32_t ENABLE; /*!< (@ 0x40040FE4) Enable register */ - __O uint32_t CLR_STAT; /*!< (@ 0x40040FE8) Clear register */ - __O uint32_t SET_STAT; /*!< (@ 0x40040FEC) Set register */ -} LPC_ATIMER_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- REGFILE ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7 (REGFILE) - */ - -typedef struct { /*!< (@ 0x40041000) REGFILE Structure */ - __IO uint32_t REGFILE[64]; /*!< (@ 0x40041000) General purpose storage register */ -} LPC_REGFILE_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- PMC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (PMC) - */ - -typedef struct { /*!< (@ 0x40042000) PMC Structure */ - __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< (@ 0x40042000) Hardware sleep event enable register */ - __I uint32_t RESERVED0[6]; - __IO uint32_t PD0_SLEEP0_MODE; /*!< (@ 0x4004201C) Sleep power mode register */ -} LPC_PMC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- CREG ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Configuration Registers (CREG) Modification date=8/19/2011 Major revision=0 Minor revision=14 (CREG) - */ - -typedef struct { /*!< (@ 0x40043000) CREG Structure */ - __I uint32_t IRCTRM; /*!< (@ 0x40043000) IRC trim register */ - __IO uint32_t CREG0; /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */ - __IO uint32_t PMUCON; /*!< (@ 0x40043008) Power mode control register. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t M3MEMMAP; /*!< (@ 0x40043100) ARM Cortex-M3 memory mapping */ - __I uint32_t RESERVED1[5]; - __IO uint32_t CREG5; /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */ - __IO uint32_t DMAMUX; /*!< (@ 0x4004311C) DMA muxing control */ - __I uint32_t RESERVED2[2]; - __IO uint32_t ETBCFG; /*!< (@ 0x40043128) ETB RAM configuration */ - __IO uint32_t CREG6; /*!< (@ 0x4004312C) Chip configuration register 6 */ - __I uint32_t RESERVED3[52]; - __I uint32_t CHIPID; /*!< (@ 0x40043200) Part ID */ -} LPC_CREG_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- EVENTROUTER ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Event router Modification date=1/20/2011 Major revision=0 Minor revision=7 (EVENTROUTER) - */ - -typedef struct { /*!< (@ 0x40044000) EVENTROUTER Structure */ - __IO uint32_t HILO; /*!< (@ 0x40044000) Level configuration register */ - __IO uint32_t EDGE; /*!< (@ 0x40044004) Edge configuration */ - __I uint32_t RESERVED0[1012]; - __O uint32_t CLR_EN; /*!< (@ 0x40044FD8) Event clear enable register */ - __O uint32_t SET_EN; /*!< (@ 0x40044FDC) Event set enable register */ - __I uint32_t STATUS; /*!< (@ 0x40044FE0) Status register */ - __I uint32_t ENABLE; /*!< (@ 0x40044FE4) Enable register */ - __O uint32_t CLR_STAT; /*!< (@ 0x40044FE8) Clear register */ - __O uint32_t SET_STAT; /*!< (@ 0x40044FEC) Set register */ -} LPC_EVENTROUTER_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- RTC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (RTC) - */ - -typedef struct { /*!< (@ 0x40046000) RTC Structure */ - __O uint32_t ILR; /*!< (@ 0x40046000) Interrupt Location Register */ - __I uint32_t RESERVED0; - __IO uint32_t CCR; /*!< (@ 0x40046008) Clock Control Register */ - __IO uint32_t CIIR; /*!< (@ 0x4004600C) Counter Increment Interrupt Register */ - __IO uint32_t AMR; /*!< (@ 0x40046010) Alarm Mask Register */ - __I uint32_t CTIME0; /*!< (@ 0x40046014) Consolidated Time Register 0 */ - __I uint32_t CTIME1; /*!< (@ 0x40046018) Consolidated Time Register 1 */ - __I uint32_t CTIME2; /*!< (@ 0x4004601C) Consolidated Time Register 2 */ - __IO uint32_t SEC; /*!< (@ 0x40046020) Seconds Register */ - __IO uint32_t MIN; /*!< (@ 0x40046024) Minutes Register */ - __IO uint32_t HRS; /*!< (@ 0x40046028) Hours Register */ - __IO uint32_t DOM; /*!< (@ 0x4004602C) Day of Month Register */ - __IO uint32_t DOW; /*!< (@ 0x40046030) Day of Week Register */ - __IO uint32_t DOY; /*!< (@ 0x40046034) Day of Year Register */ - __IO uint32_t MONTH; /*!< (@ 0x40046038) Months Register */ - __IO uint32_t YEAR; /*!< (@ 0x4004603C) Years Register */ - __IO uint32_t CALIBRATION; /*!< (@ 0x40046040) Calibration Value Register */ - __I uint32_t RESERVED1[7]; - __IO uint32_t ASEC; /*!< (@ 0x40046060) Alarm value for Seconds */ - __IO uint32_t AMIN; /*!< (@ 0x40046064) Alarm value for Minutes */ - __IO uint32_t AHRS; /*!< (@ 0x40046068) Alarm value for Hours */ - __IO uint32_t ADOM; /*!< (@ 0x4004606C) Alarm value for Day of Month */ - __IO uint32_t ADOW; /*!< (@ 0x40046070) Alarm value for Day of Week */ - __IO uint32_t ADOY; /*!< (@ 0x40046074) Alarm value for Day of Year */ - __IO uint32_t AMON; /*!< (@ 0x40046078) Alarm value for Months */ - __IO uint32_t AYRS; /*!< (@ 0x4004607C) Alarm value for Year */ -} LPC_RTC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- CGU ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1 (CGU) - */ - -typedef struct { /*!< (@ 0x40050000) CGU Structure */ - __I uint32_t RESERVED0[5]; - __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */ - __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */ - __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0 (USB) status register */ - __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0 (USB) control register */ - __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0 (USB) M-divider register */ - __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */ - __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0 (audio) status register */ - __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0 (audio) control register */ - __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0 (audio) M-divider register */ - __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */ - __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */ - __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */ - __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */ - __IO uint32_t IDIVA_CTRL; /*!< (@ 0x40050048) Integer divider A control register */ - __IO uint32_t IDIVB_CTRL; /*!< (@ 0x4005004C) Integer divider B control register */ - __IO uint32_t IDIVC_CTRL; /*!< (@ 0x40050050) Integer divider C control register */ - __IO uint32_t IDIVD_CTRL; /*!< (@ 0x40050054) Integer divider D control register */ - __IO uint32_t IDIVE_CTRL; /*!< (@ 0x40050058) Integer divider E control register */ - __IO uint32_t BASE_SAFE_CLK; /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */ - __IO uint32_t BASE_USB0_CLK; /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */ - __IO uint32_t BASE_PERIPH_CLK; /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */ - __IO uint32_t BASE_USB1_CLK; /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */ - __IO uint32_t BASE_M3_CLK; /*!< (@ 0x4005006C) Output stage control register */ - __IO uint32_t BASE_SPIFI_CLK; /*!< (@ 0x40050070) Output stage control register */ - __IO uint32_t BASE_SPI_CLK; /*!< (@ 0x40050074) Output stage control register */ - __IO uint32_t BASE_PHY_RX_CLK; /*!< (@ 0x40050078) Output stage control register */ - __IO uint32_t BASE_PHY_TX_CLK; /*!< (@ 0x4005007C) Output stage control register */ - __IO uint32_t BASE_APB1_CLK; /*!< (@ 0x40050080) Output stage control register */ - __IO uint32_t BASE_APB3_CLK; /*!< (@ 0x40050084) Output stage control register */ - __IO uint32_t BASE_LCD_CLK; /*!< (@ 0x40050088) Output stage control register */ - __IO uint32_t RESERVED2; - __IO uint32_t BASE_SDIO_CLK; /*!< (@ 0x40050090) Output stage control register */ - __IO uint32_t BASE_SSP0_CLK; /*!< (@ 0x40050094) Output stage control register */ - __IO uint32_t BASE_SSP1_CLK; /*!< (@ 0x40050098) Output stage control register */ - __IO uint32_t BASE_UART0_CLK; /*!< (@ 0x4005009C) Output stage control register */ - __IO uint32_t BASE_UART1_CLK; /*!< (@ 0x400500A0) Output stage control register */ - __IO uint32_t BASE_UART2_CLK; /*!< (@ 0x400500A4) Output stage control register */ - __IO uint32_t BASE_UART3_CLK; /*!< (@ 0x400500A8) Output stage control register */ - __IO uint32_t BASE_OUT_CLK; /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */ - __I uint32_t RESERVED3[4]; - __IO uint32_t BASE_APLL_CLK; /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */ - __IO uint32_t BASE_CGU_OUT0_CLK; /*!< (@ 0x400500C4) Output stage 26 control register for base clock BASE_CGU_OUT0_CLK */ - __IO uint32_t BASE_CGU_OUT1_CLK; /*!< (@ 0x400500C8) Output stage 27 control register for base clock BASE_CGU_OUT1_CLK */ -} LPC_CGU_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- CCU1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU1) - */ - -typedef struct { /*!< (@ 0x40051000) CCU1 Structure */ - __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */ - __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */ - __I uint32_t RESERVED0[62]; - __IO uint32_t CLK_APB3_BUS_CFG; /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */ - __I uint32_t CLK_APB3_BUS_STAT; /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */ - __IO uint32_t CLK_APB3_I2C1_CFG; /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */ - __I uint32_t CLK_APB3_I2C1_STAT; /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */ - __IO uint32_t CLK_APB3_DAC_CFG; /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */ - __I uint32_t CLK_APB3_DAC_STAT; /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */ - __IO uint32_t CLK_APB3_ADC0_CFG; /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */ - __I uint32_t CLK_APB3_ADC0_STAT; /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */ - __IO uint32_t CLK_APB3_ADC1_CFG; /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */ - __I uint32_t CLK_APB3_ADC1_STAT; /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */ - __IO uint32_t CLK_APB3_CAN0_CFG; /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */ - __I uint32_t CLK_APB3_CAN0_STAT; /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */ - __I uint32_t RESERVED1[52]; - __IO uint32_t CLK_APB1_BUS_CFG; /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */ - __I uint32_t CLK_APB1_BUS_STAT; /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */ - __IO uint32_t CLK_APB1_MOTOCONPWM_CFG; /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */ - __I uint32_t CLK_APB1_MOTOCONPWM_STAT; /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */ - __IO uint32_t CLK_ABP1_I2C0_CFG; /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */ - __I uint32_t CLK_APB1_I2C0_STAT; /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */ - __IO uint32_t CLK_APB1_I2S_CFG; /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */ - __I uint32_t CLK_APB1_I2S_STAT; /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */ - __IO uint32_t CLK_APB1_CAN1_CFG; /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */ - __I uint32_t CLK_APB1_CAN1_STAT; /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */ - __I uint32_t RESERVED2[54]; - __IO uint32_t CLK_SPIFI_CFG; /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */ - __I uint32_t CLK_SPIFI_STAT; /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */ - __I uint32_t RESERVED3[62]; - __IO uint32_t CLK_M3_BUS_CFG; /*!< (@ 0x40051400) CLK_M3_BUS clock configuration register */ - __I uint32_t CLK_M3_BUS_STAT; /*!< (@ 0x40051404) CLK_M3_BUSclock status register */ - __IO uint32_t CLK_M3_SPIFI_CFG; /*!< (@ 0x40051408) CLK_M3_SPIFI clock configuration register */ - __I uint32_t CLK_M3_SPIFI_STAT; /*!< (@ 0x4005140C) CLK_M3_SPIFI clock status register */ - __IO uint32_t CLK_M3_GPIO_CFG; /*!< (@ 0x40051410) CLK_M3_GPIO clock configuration register */ - __I uint32_t CLK_M3_GPIO_STAT; /*!< (@ 0x40051414) CLK_M3_GPIO clock status register */ - __IO uint32_t CLK_M3_LCD_CFG; /*!< (@ 0x40051418) CLK_M3_LCD clock configuration register */ - __I uint32_t CLK_M3_LCD_STAT; /*!< (@ 0x4005141C) CLK_M3_LCD clock status register */ - __IO uint32_t CLK_M3_ETHERNET_CFG; /*!< (@ 0x40051420) CLK_M3_ETHERNET clock configuration register */ - __I uint32_t CLK_M3_ETHERNET_STAT; /*!< (@ 0x40051424) CLK_M3_ETHERNET clock status register */ - __IO uint32_t CLK_M3_USB0_CFG; /*!< (@ 0x40051428) CLK_M3_USB0 clock configuration register */ - __I uint32_t CLK_M3_USB0_STAT; /*!< (@ 0x4005142C) CLK_M3_USB0 clock status register */ - __IO uint32_t CLK_M3_EMC_CFG; /*!< (@ 0x40051430) CLK_M3_EMC clock configuration register */ - __I uint32_t CLK_M3_EMC_STAT; /*!< (@ 0x40051434) CLK_M3_EMC clock status register */ - __IO uint32_t CLK_M3_SDIO_CFG; /*!< (@ 0x40051438) CLK_M3_SDIO clock configuration register */ - __I uint32_t CLK_M3_SDIO_STAT; /*!< (@ 0x4005143C) CLK_M3_SDIO clock status register */ - __IO uint32_t CLK_M3_DMA_CFG; /*!< (@ 0x40051440) CLK_M3_DMA clock configuration register */ - __I uint32_t CLK_M3_DMA_STAT; /*!< (@ 0x40051444) CLK_M3_DMA clock status register */ - __IO uint32_t CLK_M3_M3CORE_CFG; /*!< (@ 0x40051448) CLK_M3_M3CORE clock configuration register */ - __I uint32_t CLK_M3_M3CORE_STAT; /*!< (@ 0x4005144C) CLK_M3_M3CORE clock status register */ - __I uint32_t RESERVED4[6]; - __IO uint32_t CLK_M3_SCT_CFG; /*!< (@ 0x40051468) CLK_M3_SCT clock configuration register */ - __I uint32_t CLK_M3_SCT_STAT; /*!< (@ 0x4005146C) CLK_M3_SCT clock status register */ - __IO uint32_t CLK_M3_USB1_CFG; /*!< (@ 0x40051470) CLK_M3_USB1 clock configuration register */ - __I uint32_t CLK_M3_USB1_STAT; /*!< (@ 0x40051474) CLK_M3_USB1 clock status register */ - __IO uint32_t CLK_M3_EMCDIV_CFG; /*!< (@ 0x40051478) CLK_M3_EMCDIV clock configuration register */ - __I uint32_t CLK_M3_EMCDIV_STAT; /*!< (@ 0x4005147C) CLK_M3_EMCDIV clock status register */ - __I uint32_t RESERVED5[32]; - __IO uint32_t CLK_M3_WWDT_CFG; /*!< (@ 0x40051500) CLK_M3_WWDT clock configuration register */ - __I uint32_t CLK_M3_WWDT_STAT; /*!< (@ 0x40051504) CLK_M3_WWDT clock status register */ - __IO uint32_t CLK_M3_USART0_CFG; /*!< (@ 0x40051508) CLK_M3_USART0 clock configuration register */ - __I uint32_t CLK_M3_USART0_STAT; /*!< (@ 0x4005150C) CLK_M3_USART0 clock status register */ - __IO uint32_t CLK_M3_UART1_CFG; /*!< (@ 0x40051510) CLK_M3_UART1 clock configuration register */ - __I uint32_t CLK_M3_UART1_STAT; /*!< (@ 0x40051514) CLK_M3_UART1 clock status register */ - __IO uint32_t CLK_M3_SSP0_CFG; /*!< (@ 0x40051518) CLK_M3_SSP0 clock configuration register */ - __I uint32_t CLK_M3_SSP0_STAT; /*!< (@ 0x4005151C) CLK_M3_SSP0 clock status register */ - __IO uint32_t CLK_M3_TIMER0_CFG; /*!< (@ 0x40051520) CLK_M3_TIMER0 clock configuration register */ - __I uint32_t CLK_M3_TIMER0_STAT; /*!< (@ 0x40051524) CLK_M3_TIMER0 clock status register */ - __IO uint32_t CLK_M3_TIMER1_CFG; /*!< (@ 0x40051528) CLK_M3_TIMER1clock configuration register */ - __I uint32_t CLK_M3_TIMER1_STAT; /*!< (@ 0x4005152C) CLK_M3_TIMER1 clock status register */ - __IO uint32_t CLK_M3_SCU_CFG; /*!< (@ 0x40051530) CLK_M3_SCU clock configuration register */ - __I uint32_t CLK_M3_SCU_STAT; /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */ - __IO uint32_t CLK_M3_CREG_CFG; /*!< (@ 0x40051538) CLK_M3_CREGclock configuration register */ - __I uint32_t CLK_M3_CREG_STAT; /*!< (@ 0x4005153C) CLK_M3_CREG clock status register */ - __I uint32_t RESERVED6[48]; - __IO uint32_t CLK_M3_RITIMER_CFG; /*!< (@ 0x40051600) CLK_M3_RITIMER clock configuration register */ - __I uint32_t CLK_M3_RITIMER_STAT; /*!< (@ 0x40051604) CLK_M3_RITIMER clock status register */ - __IO uint32_t CLK_M3_USART2_CFG; /*!< (@ 0x40051608) CLK_M3_USART2 clock configuration register */ - __I uint32_t CLK_M3_USART2_STAT; /*!< (@ 0x4005160C) CLK_M3_USART2 clock status register */ - __IO uint32_t CLK_M3_USART3_CFG; /*!< (@ 0x40051610) CLK_M3_USART3 clock configuration register */ - __I uint32_t CLK_M3_USART3_STAT; /*!< (@ 0x40051614) CLK_M3_USART3 clock status register */ - __IO uint32_t CLK_M3_TIMER2_CFG; /*!< (@ 0x40051618) CLK_M3_TIMER2 clock configuration register */ - __I uint32_t CLK_M3_TIMER2_STAT; /*!< (@ 0x4005161C) CLK_M3_TIMER2 clock status register */ - __IO uint32_t CLK_M3_TIMER3_CFG; /*!< (@ 0x40051620) CLK_M3_TIMER3 clock configuration register */ - __I uint32_t CLK_M3_TIMER3_STAT; /*!< (@ 0x40051624) CLK_M3_TIMER3 clock status register */ - __IO uint32_t CLK_M3_SSP1_CFG; /*!< (@ 0x40051628) CLK_M3_SSP1 clock configuration register */ - __I uint32_t CLK_M3_SSP1_STAT; /*!< (@ 0x4005162C) CLK_M3_SSP1 clock status register */ - __IO uint32_t CLK_M3_QEI_CFG; /*!< (@ 0x40051630) CLK_M3_QEIclock configuration register */ - __I uint32_t CLK_M3_QEI_STAT; /*!< (@ 0x40051634) CLK_M3_QEI clock status register */ - __I uint32_t RESERVED7[114]; - __IO uint32_t CLK_USB0_CFG; /*!< (@ 0x40051800) CLK_M3_USB0 clock configuration register */ - __I uint32_t CLK_USB0_STAT; /*!< (@ 0x40051804) CLK_USB0 clock status register */ - __I uint32_t RESERVED8[62]; - __IO uint32_t CLK_USB1_CFG; /*!< (@ 0x40051900) CLK_USB1 clock configuration register */ - __I uint32_t CLK_USB1_STAT; /*!< (@ 0x40051904) CLK_USB1 clock status register */ - __I uint32_t RESERVED9[126]; - __IO uint32_t CLK_VADC_CFG; /*!< (@ 0x40051B00) CLK_VADC clock configuration register */ - __I uint32_t CLK_VADC_STAT; /*!< (@ 0x40051B04) CLK_VADC clock status register */ -} LPC_CCU1_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- CCU2 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU2) - */ - -typedef struct { /*!< (@ 0x40052000) CCU2 Structure */ - __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */ - __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */ - __I uint32_t RESERVED0[62]; - __IO uint32_t CLK_APLL_CFG; /*!< (@ 0x40052100) CLK_APLL clock configuration register */ - __I uint32_t CLK_APLL_STAT; /*!< (@ 0x40052104) CLK_APLL clock status register */ - __I uint32_t RESERVED1[62]; - __IO uint32_t CLK_APB2_USART3_CFG; /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */ - __I uint32_t CLK_APB2_USART3_STAT; /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */ - __I uint32_t RESERVED2[62]; - __IO uint32_t CLK_APB2_USART2_CFG; /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */ - __I uint32_t CLK_APB2_USART2_STAT; /*!< (@ 0x40052304) CLK_APB2_USART clock status register */ - __I uint32_t RESERVED3[62]; - __IO uint32_t CLK_APB0_UART1_CFG; /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */ - __I uint32_t CLK_APB0_UART1_STAT; /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */ - __I uint32_t RESERVED4[62]; - __IO uint32_t CLK_APB0_USART0_CFG; /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */ - __I uint32_t CLK_APB0_USART0_STAT; /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */ - __I uint32_t RESERVED5[62]; - __IO uint32_t CLK_APB2_SSP1_CFG; /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */ - __I uint32_t CLK_APB2_SSP1_STAT; /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */ - __I uint32_t RESERVED6[62]; - __IO uint32_t CLK_APB0_SSP0_CFG; /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */ - __I uint32_t CLK_APB0_SSP0_STAT; /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */ - __I uint32_t RESERVED7[62]; - __IO uint32_t CLK_SDIO_CFG; /*!< (@ 0x40052800) CLK_SDIO clock configuration register */ - __I uint32_t CLK_SDIO_STAT; /*!< (@ 0x40052804) CLK_SDIO clock status register */ -} LPC_CCU2_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- RGU ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13 (RGU) - */ - -typedef struct { /*!< (@ 0x40053000) RGU Structure */ - __I uint32_t RESERVED0[64]; - __O uint32_t RESET_CTRL0; /*!< (@ 0x40053100) Reset control register 0 */ - __O uint32_t RESET_CTRL1; /*!< (@ 0x40053104) Reset control register 1 */ - __I uint32_t RESERVED1[2]; - __IO uint32_t RESET_STATUS0; /*!< (@ 0x40053110) Reset status register 0 */ - __IO uint32_t RESET_STATUS1; /*!< (@ 0x40053114) Reset status register 1 */ - __IO uint32_t RESET_STATUS2; /*!< (@ 0x40053118) Reset status register 2 */ - __IO uint32_t RESET_STATUS3; /*!< (@ 0x4005311C) Reset status register 3 */ - __I uint32_t RESERVED2[12]; - __I uint32_t RESET_ACTIVE_STATUS0; /*!< (@ 0x40053150) Reset active status register 0 */ - __I uint32_t RESET_ACTIVE_STATUS1; /*!< (@ 0x40053154) Reset active status register 1 */ - __I uint32_t RESERVED3[170]; - __IO uint32_t RESET_EXT_STAT0; /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */ - __IO uint32_t RESET_EXT_STAT1; /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */ - __IO uint32_t RESET_EXT_STAT2; /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */ - __I uint32_t RESERVED4; - __IO uint32_t RESET_EXT_STAT4; /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */ - __IO uint32_t RESET_EXT_STAT5; /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */ - __I uint32_t RESERVED5[2]; - __IO uint32_t RESET_EXT_STAT8; /*!< (@ 0x40053420) Reset external status register */ - __IO uint32_t RESET_EXT_STAT9; /*!< (@ 0x40053424) Reset external status register */ - __I uint32_t RESERVED6[3]; - __IO uint32_t RESET_EXT_STAT13; /*!< (@ 0x40053434) Reset external status register */ - __I uint32_t RESERVED7[2]; - __IO uint32_t RESET_EXT_STAT16; /*!< (@ 0x40053440) Reset external status register */ - __IO uint32_t RESET_EXT_STAT17; /*!< (@ 0x40053444) Reset external status register */ - __IO uint32_t RESET_EXT_STAT18; /*!< (@ 0x40053448) Reset external status register */ - __IO uint32_t RESET_EXT_STAT19; /*!< (@ 0x4005344C) Reset external status register */ - __IO uint32_t RESET_EXT_STAT20; /*!< (@ 0x40053450) Reset external status register */ - __IO uint32_t RESET_EXT_STAT21; /*!< (@ 0x40053454) Reset external status register */ - __IO uint32_t RESET_EXT_STAT22; /*!< (@ 0x40053458) Reset external status register */ - __IO uint32_t RESET_EXT_STAT23; /*!< (@ 0x4005345C) Reset external status register */ - __I uint32_t RESERVED8[4]; - __IO uint32_t RESET_EXT_STAT28; /*!< (@ 0x40053470) Reset external status register */ - __I uint32_t RESERVED9[3]; - __IO uint32_t RESET_EXT_STAT32; /*!< (@ 0x40053480) Reset external status register */ - __IO uint32_t RESET_EXT_STAT33; /*!< (@ 0x40053484) Reset external status register */ - __IO uint32_t RESET_EXT_STAT34; /*!< (@ 0x40053488) Reset external status register */ - __IO uint32_t RESET_EXT_STAT35; /*!< (@ 0x4005348C) Reset external status register */ - __IO uint32_t RESET_EXT_STAT36; /*!< (@ 0x40053490) Reset external status register */ - __IO uint32_t RESET_EXT_STAT37; /*!< (@ 0x40053494) Reset external status register */ - __IO uint32_t RESET_EXT_STAT38; /*!< (@ 0x40053498) Reset external status register */ - __IO uint32_t RESET_EXT_STAT39; /*!< (@ 0x4005349C) Reset external status register */ - __IO uint32_t RESET_EXT_STAT40; /*!< (@ 0x400534A0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT41; /*!< (@ 0x400534A4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT42; /*!< (@ 0x400534A8) Reset external status register */ - __I uint32_t RESERVED10; - __IO uint32_t RESET_EXT_STAT44; /*!< (@ 0x400534B0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT45; /*!< (@ 0x400534B4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT46; /*!< (@ 0x400534B8) Reset external status register */ - __IO uint32_t RESET_EXT_STAT47; /*!< (@ 0x400534BC) Reset external status register */ - __IO uint32_t RESET_EXT_STAT48; /*!< (@ 0x400534C0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT49; /*!< (@ 0x400534C4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT50; /*!< (@ 0x400534C8) Reset external status register */ - __IO uint32_t RESET_EXT_STAT51; /*!< (@ 0x400534CC) Reset external status register */ - __IO uint32_t RESET_EXT_STAT52; /*!< (@ 0x400534D0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT53; /*!< (@ 0x400534D4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT54; /*!< (@ 0x400534D8) Reset external status register */ - __IO uint32_t RESET_EXT_STAT55; /*!< (@ 0x400534DC) Reset external status register */ -} LPC_RGU_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- WWDT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (WWDT) - */ - -typedef struct { /*!< (@ 0x40080000) WWDT Structure */ - __IO uint32_t MOD; /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ - __IO uint32_t TC; /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */ - __O uint32_t FEED; /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */ - __I uint32_t TV; /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ - __I uint32_t RESERVED0; - __IO uint32_t WARNINT; /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */ - __IO uint32_t WINDOW; /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */ -} LPC_WWDT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- USARTn ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (USARTn) - */ - -typedef struct { /*!< (@ 0x400xx000) USARTn Structure */ - - union { - __IO uint32_t DLL; /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ - __O uint32_t THR; /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */ - __I uint32_t RBR; /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */ - }; - - union { - __IO uint32_t IER; /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */ - __IO uint32_t DLM; /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ - }; - - union { - __O uint32_t FCR; /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */ - __I uint32_t IIR; /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ - }; - __IO uint32_t LCR; /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */ - __I uint32_t RESERVED0[1]; - __I uint32_t LSR; /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ - __I uint32_t RESERVED1[1]; - __IO uint32_t SCR; /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */ - __IO uint32_t ACR; /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ - __IO uint32_t ICR; /*!< (@ 0x400xx024) IrDA control register (UART3 only) */ - __IO uint32_t FDR; /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ - __IO uint32_t OSR; /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */ - __I uint32_t RESERVED2[4]; - __IO uint32_t HDEN; /*!< (@ 0x400xx03C) Half-duplex enable Register */ - __I uint32_t RESERVED3[1]; - __IO uint32_t SCICTRL; /*!< (@ 0x400xx048) Smart card interface control register */ - __IO uint32_t RS485CTRL; /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ - __IO uint32_t RS485ADRMATCH; /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ - __IO uint32_t RS485DLY; /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */ - __IO uint32_t SYNCCTRL; /*!< (@ 0x400xx058) Synchronous mode control register. */ - __IO uint32_t TER; /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */ -} LPC_USARTn_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- UART1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (UART1) - */ - -typedef struct { /*!< (@ 0x40082000) UART1 Structure */ - - union { - __IO uint32_t DLL; /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - __O uint32_t THR; /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ - __I uint32_t RBR; /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ - }; - - union { - __IO uint32_t IER; /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */ - __IO uint32_t DLM; /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */ - }; - - union { - __O uint32_t FCR; /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */ - __I uint32_t IIR; /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ - }; - __IO uint32_t LCR; /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */ - __IO uint32_t MCR; /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */ - __I uint32_t LSR; /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ - __I uint32_t MSR; /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */ - __IO uint32_t SCR; /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */ - __IO uint32_t ACR; /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ - __I uint32_t RESERVED0; - __IO uint32_t FDR; /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ - __I uint32_t RESERVED1; - __IO uint32_t TER; /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */ - __I uint32_t RESERVED2[6]; - __IO uint32_t RS485CTRL; /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ - __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ - __IO uint32_t RS485DLY; /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */ - __I uint32_t FIFOLVL; /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */ -} LPC_UART1_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SSPn ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (SSP0) - */ - -typedef struct { /*!< (@ 0x400xx000) SSPn Structure */ - __IO uint32_t CR0; /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ - __IO uint32_t CR1; /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */ - __IO uint32_t DR; /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ - __I uint32_t SR; /*!< (@ 0x400xx00C) Status Register */ - __IO uint32_t CPSR; /*!< (@ 0x400xx010) Clock Prescale Register */ - __IO uint32_t IMSC; /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */ - __I uint32_t RIS; /*!< (@ 0x400xx018) Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< (@ 0x400xx01C) Masked Interrupt Status Register */ - __O uint32_t ICR; /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */ - __IO uint32_t DMACR; /*!< (@ 0x400xx024) SSPn DMA control register */ -} LPC_SSPn_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMERn ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (TIMERn) - */ - -typedef struct { /*!< (@ 0x400xx000) TIMERn Structure */ - __IO uint32_t IR; /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ - __IO uint32_t TCR; /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ - __IO uint32_t TC; /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */ - __IO uint32_t PR; /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */ - __IO uint32_t PC; /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ - __IO uint32_t MCR; /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ - __IO uint32_t MR[4]; /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ - __IO uint32_t CCR; /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ - __IO uint32_t CR[4]; /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */ - __IO uint32_t EMR; /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */ - __I uint32_t RESERVED0[12]; - __IO uint32_t CTCR; /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -} LPC_TIMERn_Type; - - - - -// ------------------------------------------------------------------------------------------------ -// ----- SCU ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10 (SCU) - */ - -typedef struct { /*!< (@ 0x40086000) SCU Structure */ - __IO uint32_t SFSP0_0; /*!< (@ 0x40086000) Pin configuration register for pins P0 */ - __IO uint32_t SFSP0_1; /*!< (@ 0x40086004) Pin configuration register for pins P0 */ - __I uint32_t RESERVED0[30]; - __IO uint32_t SFSP1_0; /*!< (@ 0x40086080) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_1; /*!< (@ 0x40086084) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_2; /*!< (@ 0x40086088) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_3; /*!< (@ 0x4008608C) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_4; /*!< (@ 0x40086090) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_5; /*!< (@ 0x40086094) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_6; /*!< (@ 0x40086098) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_7; /*!< (@ 0x4008609C) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_8; /*!< (@ 0x400860A0) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_9; /*!< (@ 0x400860A4) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_10; /*!< (@ 0x400860A8) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_11; /*!< (@ 0x400860AC) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_12; /*!< (@ 0x400860B0) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_13; /*!< (@ 0x400860B4) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_14; /*!< (@ 0x400860B8) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_15; /*!< (@ 0x400860BC) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_16; /*!< (@ 0x400860C0) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_17; /*!< (@ 0x400860C4) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_18; /*!< (@ 0x400860C8) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_19; /*!< (@ 0x400860CC) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_20; /*!< (@ 0x400860D0) Pin configuration register for pins P1 */ - __I uint32_t RESERVED1[11]; - __IO uint32_t SFSP2_0; /*!< (@ 0x40086100) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_1; /*!< (@ 0x40086104) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_2; /*!< (@ 0x40086108) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_3; /*!< (@ 0x4008610C) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_4; /*!< (@ 0x40086110) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_5; /*!< (@ 0x40086114) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_6; /*!< (@ 0x40086118) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_7; /*!< (@ 0x4008611C) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_8; /*!< (@ 0x40086120) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_9; /*!< (@ 0x40086124) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_10; /*!< (@ 0x40086128) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_11; /*!< (@ 0x4008612C) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_12; /*!< (@ 0x40086130) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_13; /*!< (@ 0x40086134) Pin configuration register for pins P2 */ - __I uint32_t RESERVED2[18]; - __IO uint32_t SFSP3_0; /*!< (@ 0x40086180) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_1; /*!< (@ 0x40086184) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_2; /*!< (@ 0x40086188) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_3; /*!< (@ 0x4008618C) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_4; /*!< (@ 0x40086190) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_5; /*!< (@ 0x40086194) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_6; /*!< (@ 0x40086198) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_7; /*!< (@ 0x4008619C) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_8; /*!< (@ 0x400861A0) Pin configuration register for pins P3 */ - __I uint32_t RESERVED3[23]; - __IO uint32_t SFSP4_0; /*!< (@ 0x40086200) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_1; /*!< (@ 0x40086204) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_2; /*!< (@ 0x40086208) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_3; /*!< (@ 0x4008620C) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_4; /*!< (@ 0x40086210) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_5; /*!< (@ 0x40086214) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_6; /*!< (@ 0x40086218) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_7; /*!< (@ 0x4008621C) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_8; /*!< (@ 0x40086220) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_9; /*!< (@ 0x40086224) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_10; /*!< (@ 0x40086228) Pin configuration register for pins P4 */ - __I uint32_t RESERVED4[21]; - __IO uint32_t SFSP5_0; /*!< (@ 0x40086280) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_1; /*!< (@ 0x40086284) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_2; /*!< (@ 0x40086288) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_3; /*!< (@ 0x4008628C) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_4; /*!< (@ 0x40086290) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_5; /*!< (@ 0x40086294) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_6; /*!< (@ 0x40086298) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_7; /*!< (@ 0x4008629C) Pin configuration register for pins P5 */ - __I uint32_t RESERVED5[24]; - __IO uint32_t SFSP6_0; /*!< (@ 0x40086300) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_1; /*!< (@ 0x40086304) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_2; /*!< (@ 0x40086308) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_3; /*!< (@ 0x4008630C) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_4; /*!< (@ 0x40086310) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_5; /*!< (@ 0x40086314) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_6; /*!< (@ 0x40086318) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_7; /*!< (@ 0x4008631C) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_8; /*!< (@ 0x40086320) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_9; /*!< (@ 0x40086324) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_10; /*!< (@ 0x40086328) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_11; /*!< (@ 0x4008632C) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_12; /*!< (@ 0x40086330) Pin configuration register for pins P6 */ - __I uint32_t RESERVED6[19]; - __IO uint32_t SFSP7_0; /*!< (@ 0x40086380) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_1; /*!< (@ 0x40086384) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_2; /*!< (@ 0x40086388) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_3; /*!< (@ 0x4008638C) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_4; /*!< (@ 0x40086390) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_5; /*!< (@ 0x40086394) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_6; /*!< (@ 0x40086398) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_7; /*!< (@ 0x4008639C) Pin configuration register for pins P7 */ - __I uint32_t RESERVED7[24]; - __IO uint32_t SFSP8_0; /*!< (@ 0x40086400) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_1; /*!< (@ 0x40086404) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_2; /*!< (@ 0x40086408) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_3; /*!< (@ 0x4008640C) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_4; /*!< (@ 0x40086410) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_5; /*!< (@ 0x40086414) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_6; /*!< (@ 0x40086418) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_7; /*!< (@ 0x4008641C) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_8; /*!< (@ 0x40086420) Pin configuration register for pins P8 */ - __I uint32_t RESERVED8[23]; - __IO uint32_t SFSP9_0; /*!< (@ 0x40086480) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_1; /*!< (@ 0x40086484) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_2; /*!< (@ 0x40086488) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_3; /*!< (@ 0x4008648C) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_4; /*!< (@ 0x40086490) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_5; /*!< (@ 0x40086494) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_6; /*!< (@ 0x40086498) Pin configuration register for pins P9 */ - __I uint32_t RESERVED9[25]; - __IO uint32_t SFSPA_0; /*!< (@ 0x40086500) Pin configuration register for pins PA */ - __IO uint32_t SFSPA_1; /*!< (@ 0x40086504) Pin configuration register for pins PA */ - __IO uint32_t SFSPA_2; /*!< (@ 0x40086508) Pin configuration register for pins PA */ - __IO uint32_t SFSPA_3; /*!< (@ 0x4008650C) Pin configuration register for pins PA */ - __IO uint32_t SFSPA_4; /*!< (@ 0x40086510) Pin configuration register for pins PA */ - __I uint32_t RESERVED10[27]; - __IO uint32_t SFSPB_0; /*!< (@ 0x40086580) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_1; /*!< (@ 0x40086584) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_2; /*!< (@ 0x40086588) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_3; /*!< (@ 0x4008658C) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_4; /*!< (@ 0x40086590) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_5; /*!< (@ 0x40086594) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_6; /*!< (@ 0x40086598) Pin configuration register for pins PB */ - __I uint32_t RESERVED11[25]; - __IO uint32_t SFSPC_0; /*!< (@ 0x40086600) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_1; /*!< (@ 0x40086604) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_2; /*!< (@ 0x40086608) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_3; /*!< (@ 0x4008660C) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_4; /*!< (@ 0x40086610) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_5; /*!< (@ 0x40086614) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_6; /*!< (@ 0x40086618) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_7; /*!< (@ 0x4008661C) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_8; /*!< (@ 0x40086620) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_9; /*!< (@ 0x40086624) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_10; /*!< (@ 0x40086628) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_11; /*!< (@ 0x4008662C) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_12; /*!< (@ 0x40086630) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_13; /*!< (@ 0x40086634) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_14; /*!< (@ 0x40086638) Pin configuration register for pins PC */ - __I uint32_t RESERVED12[17]; - __IO uint32_t SFSPD_0; /*!< (@ 0x40086680) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_1; /*!< (@ 0x40086684) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_2; /*!< (@ 0x40086688) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_3; /*!< (@ 0x4008668C) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_4; /*!< (@ 0x40086690) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_5; /*!< (@ 0x40086694) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_6; /*!< (@ 0x40086698) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_7; /*!< (@ 0x4008669C) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_8; /*!< (@ 0x400866A0) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_9; /*!< (@ 0x400866A4) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_10; /*!< (@ 0x400866A8) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_11; /*!< (@ 0x400866AC) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_12; /*!< (@ 0x400866B0) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_13; /*!< (@ 0x400866B4) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_14; /*!< (@ 0x400866B8) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_15; /*!< (@ 0x400866BC) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_16; /*!< (@ 0x400866C0) Pin configuration register for pins PD */ - __I uint32_t RESERVED13[15]; - __IO uint32_t SFSPE_0; /*!< (@ 0x40086700) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_1; /*!< (@ 0x40086704) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_2; /*!< (@ 0x40086708) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_3; /*!< (@ 0x4008670C) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_4; /*!< (@ 0x40086710) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_5; /*!< (@ 0x40086714) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_6; /*!< (@ 0x40086718) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_7; /*!< (@ 0x4008671C) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_8; /*!< (@ 0x40086720) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_9; /*!< (@ 0x40086724) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_10; /*!< (@ 0x40086728) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_11; /*!< (@ 0x4008672C) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_12; /*!< (@ 0x40086730) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_13; /*!< (@ 0x40086734) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_14; /*!< (@ 0x40086738) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_15; /*!< (@ 0x4008673C) Pin configuration register for pins PE */ - __I uint32_t RESERVED14[16]; - __IO uint32_t SFSPF_0; /*!< (@ 0x40086780) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_1; /*!< (@ 0x40086784) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_2; /*!< (@ 0x40086788) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_3; /*!< (@ 0x4008678C) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_4; /*!< (@ 0x40086790) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_5; /*!< (@ 0x40086794) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_6; /*!< (@ 0x40086798) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_7; /*!< (@ 0x4008679C) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_8; /*!< (@ 0x400867A0) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_9; /*!< (@ 0x400867A4) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_10; /*!< (@ 0x400867A8) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_11; /*!< (@ 0x400867AC) Pin configuration register for pins PF */ - __I uint32_t RESERVED15[276]; - __IO uint32_t SFSCLK_0; /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */ - __IO uint32_t SFSCLK_1; /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */ - __IO uint32_t SFSCLK_2; /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */ - __IO uint32_t SFSCLK_3; /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */ - __I uint32_t RESERVED16[28]; - __IO uint32_t SFSUSB; /*!< (@ 0x40086C80) Pin configuration register for */ - __IO uint32_t SFSI2C0; /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */ - __IO uint32_t ENAIO0; /*!< (@ 0x40086C88) ADC0 function select register */ - __IO uint32_t ENAIO1; /*!< (@ 0x40086C8C) ADC1 function select register */ - __IO uint32_t ENAIO2; /*!< (@ 0x40086C90) Analog function select register */ - __I uint32_t RESERVED17[27]; - __IO uint32_t EMCDELAYCLK; /*!< (@ 0x40086D00) EMC clock delay register */ - __I uint32_t RESERVED18[63]; - __IO uint32_t PINTSEL0; /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */ - __IO uint32_t PINTSEL1; /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */ -} LPC_SCU_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PIN_INT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief GPIO pin interrupt (GPIO_PIN_INT) - */ - -typedef struct { /*!< (@ 0x40087000) GPIO_PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0x40087000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */ - __O uint32_t SIENR; /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */ - __O uint32_t CIENR; /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */ - __O uint32_t SIENF; /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __O uint32_t CIENF; /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0x40087024) Pin Interrupt Status register */ -} LPC_GPIO_PIN_INT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INTn ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn) - */ - -typedef struct { /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40088000) GPIO grouped interrupt control register */ - __I uint32_t RESERVED0[7]; - __IO uint32_t PORT_POL0; /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL1; /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL2; /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL3; /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL4; /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL5; /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL6; /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL7; /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_ENA0; /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA1; /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA2; /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA3; /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA4; /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA5; /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA6; /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA7; /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */ -} LPC_GPIO_GROUP_INTn_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- MCPWM ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7 (MCPWM) - */ - -typedef struct { /*!< (@ 0x400A0000) MCPWM Structure */ - __I uint32_t CON; /*!< (@ 0x400A0000) PWM Control read address */ - __O uint32_t CON_SET; /*!< (@ 0x400A0004) PWM Control set address */ - __O uint32_t CON_CLR; /*!< (@ 0x400A0008) PWM Control clear address */ - __I uint32_t CAPCON; /*!< (@ 0x400A000C) Capture Control read address */ - __O uint32_t CAPCON_SET; /*!< (@ 0x400A0010) Capture Control set address */ - __O uint32_t CAPCON_CLR; /*!< (@ 0x400A0014) Event Control clear address */ - __IO uint32_t TC[3]; /*!< (@ 0x400A0018) Timer Counter register */ - __IO uint32_t LIM[3]; /*!< (@ 0x400A0024) Limit register */ - __IO uint32_t MAT[3]; /*!< (@ 0x400A0030) Match register */ - __IO uint32_t DT; /*!< (@ 0x400A003C) Dead time register */ - __IO uint32_t CCP; /*!< (@ 0x400A0040) Communication Pattern register */ - __I uint32_t CAP[3]; /*!< (@ 0x400A0044) Capture register */ - __I uint32_t INTEN; /*!< (@ 0x400A0050) Interrupt Enable read address */ - __O uint32_t INTEN_SET; /*!< (@ 0x400A0054) Interrupt Enable set address */ - __O uint32_t INTEN_CLR; /*!< (@ 0x400A0058) Interrupt Enable clear address */ - __I uint32_t CNTCON; /*!< (@ 0x400A005C) Count Control read address */ - __O uint32_t CNTCON_SET; /*!< (@ 0x400A0060) Count Control set address */ - __O uint32_t CNTCON_CLR; /*!< (@ 0x400A0064) Count Control clear address */ - __I uint32_t INTF; /*!< (@ 0x400A0068) Interrupt flags read address */ - __O uint32_t INTF_SET; /*!< (@ 0x400A006C) Interrupt flags set address */ - __O uint32_t INTF_CLR; /*!< (@ 0x400A0070) Interrupt flags clear address */ - __O uint32_t CAP_CLR; /*!< (@ 0x400A0074) Capture clear address */ -} LPC_MCPWM_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C0 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx I2C0/1-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Cn) - */ - -typedef struct { /*!< (@ 0x400xx000) I2C0 Structure */ - __IO uint32_t CONSET; /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */ - __I uint32_t STAT; /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */ - __IO uint32_t DAT; /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */ - __IO uint32_t ADR0; /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ - __IO uint32_t SCLH; /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */ - __IO uint32_t SCLL; /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */ - __O uint32_t CONCLR; /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */ - __IO uint32_t MMCTRL; /*!< (@ 0x400xx01C) Monitor mode control register. */ - __IO uint32_t ADR1; /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ - __IO uint32_t ADR2; /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ - __IO uint32_t ADR3; /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ - __I uint32_t DATA_BUFFER; /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */ - __IO uint32_t MASK[4]; /*!< (@ 0x400xx030) I2C Slave address mask register */ -} LPC_I2Cn_Type; - -// ------------------------------------------------------------------------------------------------ -// ----- I2Sn ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Sn) - 0x400A2000 / 0x400A3000 - */ - -typedef struct { /*!< (@ 0x400Ax000) I2S Structure */ - __IO uint32_t DAO; /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */ - __IO uint32_t DAI; /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */ - __O uint32_t TXFIFO; /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */ - __I uint32_t RXFIFO; /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */ - __I uint32_t STATE; /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */ - __IO uint32_t DMA1; /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */ - __IO uint32_t DMA2; /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */ - __IO uint32_t IRQ; /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */ - __IO uint32_t TXRATE; /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */ - __IO uint32_t RXRATE; /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */ - __IO uint32_t TXBITRATE; /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */ - __IO uint32_t RXBITRATE; /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */ - __IO uint32_t TXMODE; /*!< (@ 0x400Ax030) I2S Transmit mode control. */ - __IO uint32_t RXMODE; /*!< (@ 0x400Ax034) I2S Receive mode control. */ -} LPC_I2Sn_Type; - -// ------------------------------------------------------------------------------------------------ -// ----- C_CANn ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7 (C_CANn) - 0x400A4000 / 0x400E2000 - */ - -typedef struct { /*!< (@ 0x400E2000) C_CAN Structure */ - __IO uint32_t CNTL; /*!< (@ 0x400E2000) CAN control */ - __IO uint32_t STAT; /*!< (@ 0x400E2004) Status register */ - __I uint32_t EC; /*!< (@ 0x400E2008) Error counter */ - __IO uint32_t BT; /*!< (@ 0x400E200C) Bit timing register */ - __I uint32_t INT; /*!< (@ 0x400E2010) Interrupt register */ - __IO uint32_t TEST; /*!< (@ 0x400E2014) Test register */ - __IO uint32_t BRPE; /*!< (@ 0x400E2018) Baud rate prescaler extension register */ - __I uint32_t RESERVED0; - __IO uint32_t IF1_CMDREQ; /*!< (@ 0x400E2020) Message interface command request */ - - union { - __IO uint32_t IF1_CMDMSK_R; /*!< (@ 0x400E2024) Message interface command mask (read direction) */ - __IO uint32_t IF1_CMDMSK_W; /*!< (@ 0x400E2024) Message interface command mask (write direction) */ - }; - __IO uint32_t IF1_MSK1; /*!< (@ 0x400E2028) Message interface mask 1 */ - __IO uint32_t IF1_MSK2; /*!< (@ 0x400E202C) Message interface 1 mask 2 */ - __IO uint32_t IF1_ARB1; /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */ - __IO uint32_t IF1_ARB2; /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */ - __IO uint32_t IF1_MCTRL; /*!< (@ 0x400E2038) Message interface 1 message control */ - __IO uint32_t IF1_DA1; /*!< (@ 0x400E203C) Message interface data A1 */ - __IO uint32_t IF1_DA2; /*!< (@ 0x400E2040) Message interface 1 data A2 */ - __IO uint32_t IF1_DB1; /*!< (@ 0x400E2044) Message interface 1 data B1 */ - __IO uint32_t IF1_DB2; /*!< (@ 0x400E2048) Message interface 1 data B2 */ - __I uint32_t RESERVED1[13]; - __IO uint32_t IF2_CMDREQ; /*!< (@ 0x400E2080) Message interface command request */ - - union { - __IO uint32_t IF2_CMDMSK_R; /*!< (@ 0x400E2084) Message interface command mask (read direction) */ - __IO uint32_t IF2_CMDMSK_W; /*!< (@ 0x400E2084) Message interface command mask (write direction) */ - }; - __IO uint32_t IF2_MSK1; /*!< (@ 0x400E2088) Message interface mask 1 */ - __IO uint32_t IF2_MSK2; /*!< (@ 0x400E208C) Message interface 1 mask 2 */ - __IO uint32_t IF2_ARB1; /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */ - __IO uint32_t IF2_ARB2; /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */ - __IO uint32_t IF2_MCTRL; /*!< (@ 0x400E2098) Message interface 1 message control */ - __IO uint32_t IF2_DA1; /*!< (@ 0x400E209C) Message interface data A1 */ - __IO uint32_t IF2_DA2; /*!< (@ 0x400E20A0) Message interface 1 data A2 */ - __IO uint32_t IF2_DB1; /*!< (@ 0x400E20A4) Message interface 1 data B1 */ - __IO uint32_t IF2_DB2; /*!< (@ 0x400E20A8) Message interface 1 data B2 */ - __I uint32_t RESERVED2[21]; - __I uint32_t TXREQ1; /*!< (@ 0x400E2100) Transmission request 1 */ - __I uint32_t TXREQ2; /*!< (@ 0x400E2104) Transmission request 2 */ - __I uint32_t RESERVED3[6]; - __I uint32_t ND1; /*!< (@ 0x400E2120) New data 1 */ - __I uint32_t ND2; /*!< (@ 0x400E2124) New data 2 */ - __I uint32_t RESERVED4[6]; - __I uint32_t IR1; /*!< (@ 0x400E2140) Interrupt pending 1 */ - __I uint32_t IR2; /*!< (@ 0x400E2144) Interrupt pending 2 */ - __I uint32_t RESERVED5[6]; - __I uint32_t MSGV1; /*!< (@ 0x400E2160) Message valid 1 */ - __I uint32_t MSGV2; /*!< (@ 0x400E2164) Message valid 2 */ - __I uint32_t RESERVED6[6]; - __IO uint32_t CLKDIV; /*!< (@ 0x400E2180) CAN clock divider register */ -} LPC_C_CANn_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- RITIMER ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (RITIMER) - */ - -typedef struct { /*!< (@ 0x400C0000) RITIMER Structure */ - __IO uint32_t COMPVAL; /*!< (@ 0x400C0000) Compare register */ - __IO uint32_t MASK; /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */ - __IO uint32_t CTRL; /*!< (@ 0x400C0008) Control register. */ - __IO uint32_t COUNTER; /*!< (@ 0x400C000C) 32-bit counter */ -} LPC_RITIMER_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- QEI ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7 (QEI) - */ - -typedef struct { /*!< (@ 0x400C6000) QEI Structure */ - __O uint32_t CON; /*!< (@ 0x400C6000) Control register */ - __I uint32_t STAT; /*!< (@ 0x400C6004) Encoder status register */ - __IO uint32_t CONF; /*!< (@ 0x400C6008) Configuration register */ - __I uint32_t POS; /*!< (@ 0x400C600C) Position register */ - __IO uint32_t MAXPOS; /*!< (@ 0x400C6010) Maximum position register */ - __IO uint32_t CMPOS0; /*!< (@ 0x400C6014) position compare register 0 */ - __IO uint32_t CMPOS1; /*!< (@ 0x400C6018) position compare register 1 */ - __IO uint32_t CMPOS2; /*!< (@ 0x400C601C) position compare register 2 */ - __I uint32_t INXCNT; /*!< (@ 0x400C6020) Index count register */ - __IO uint32_t INXCMP0; /*!< (@ 0x400C6024) Index compare register 0 */ - __IO uint32_t LOAD; /*!< (@ 0x400C6028) Velocity timer reload register */ - __I uint32_t TIME; /*!< (@ 0x400C602C) Velocity timer register */ - __I uint32_t VEL; /*!< (@ 0x400C6030) Velocity counter register */ - __I uint32_t CAP; /*!< (@ 0x400C6034) Velocity capture register */ - __IO uint32_t VELCOMP; /*!< (@ 0x400C6038) Velocity compare register */ - __IO uint32_t FILTERPHA; /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */ - __IO uint32_t FILTERPHB; /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */ - __IO uint32_t FILTERINX; /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */ - __IO uint32_t WINDOW; /*!< (@ 0x400C6048) Index acceptance window register */ - __IO uint32_t INXCMP1; /*!< (@ 0x400C604C) Index compare register 1 */ - __IO uint32_t INXCMP2; /*!< (@ 0x400C6050) Index compare register 2 */ - __I uint32_t RESERVED0[993]; - __O uint32_t IEC; /*!< (@ 0x400C6FD8) Interrupt enable clear register */ - __O uint32_t IES; /*!< (@ 0x400C6FDC) Interrupt enable set register */ - __I uint32_t INTSTAT; /*!< (@ 0x400C6FE0) Interrupt status register */ - __I uint32_t IE; /*!< (@ 0x400C6FE4) Interrupt enable register */ - __O uint32_t CLR; /*!< (@ 0x400C6FE8) Interrupt status clear register */ - __O uint32_t SET; /*!< (@ 0x400C6FEC) Interrupt status set register */ -} LPC_QEI_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GIMA ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=Falcon Chapter title=Global Input Multiplexer Array (GIMA) Modification date=3/25/2011 Major revision=0 Minor revision=4 (GIMA) - */ - -typedef struct { /*!< (@ 0x400C7000) GIMA Structure */ - __IO uint32_t CAP0_0_IN; /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */ - __IO uint32_t CAP0_1_IN; /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */ - __IO uint32_t CAP0_2_IN; /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */ - __IO uint32_t CAP0_3_IN; /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */ - __IO uint32_t CAP1_0_IN; /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */ - __IO uint32_t CAP1_1_IN; /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */ - __IO uint32_t CAP1_2_IN; /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */ - __IO uint32_t CAP1_3_IN; /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */ - __IO uint32_t CAP2_0_IN; /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */ - __IO uint32_t CAP2_1_IN; /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */ - __IO uint32_t CAP2_2_IN; /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */ - __IO uint32_t CAP2_3_IN; /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */ - __IO uint32_t CAP3_0_IN; /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */ - __IO uint32_t CAP3_1_IN; /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */ - __IO uint32_t CAP3_2_IN; /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */ - __IO uint32_t CAP3_3_IN; /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */ - __IO uint32_t CTIN_0_IN; /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */ - __IO uint32_t CTIN_1_IN; /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */ - __IO uint32_t CTIN_2_IN; /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */ - __IO uint32_t CTIN_3_IN; /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */ - __IO uint32_t CTIN_4_IN; /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */ - __IO uint32_t CTIN_5_IN; /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */ - __IO uint32_t CTIN_6_IN; /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */ - __IO uint32_t CTIN_7_IN; /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */ - __IO uint32_t VADC_TRIGGER_IN; /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */ - __IO uint32_t EVENTROUTER_13_IN; /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */ - __IO uint32_t EVENTROUTER_14_IN; /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */ - __IO uint32_t EVENTROUTER_16_IN; /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */ - __IO uint32_t ADCSTART0_IN; /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */ - __IO uint32_t ADCSTART1_IN; /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */ -} LPC_GIMA_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- DAC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7 (DAC) - */ - -typedef struct { /*!< (@ 0x400E1000) DAC Structure */ - __IO uint32_t CR; /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */ - __IO uint32_t CTRL; /*!< (@ 0x400E1004) DAC control register. */ - __IO uint32_t CNTVAL; /*!< (@ 0x400E1008) DAC counter value register. */ -} LPC_DAC_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- ADCn ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7 (ADCn) - 0x400E3000 / 0x400E4000 - */ - -typedef struct { /*!< (@ 0x400Ex000) ADCn Structure */ - __IO uint32_t CR; /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */ - __I uint32_t GDR; /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */ - __I uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */ - __I uint32_t DR[8]; /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */ - __I uint32_t STAT; /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */ -} LPC_ADCn_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief GPIO port (GPIO_PORT) - */ - -typedef struct { /*!< (@ 0x400F4000) GPIO_PORT Structure */ - __IO uint8_t B[256]; /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */ - __I uint32_t RESERVED0[960]; - __IO uint32_t W[256]; /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */ - __I uint32_t RESERVED1[768]; - __IO uint32_t DIR[8]; /*!< (@ 0x400F6000) Direction registers port n */ - __I uint32_t RESERVED2[24]; - __IO uint32_t MASK[8]; /*!< (@ 0x400F6080) Mask register port n */ - __I uint32_t RESERVED3[24]; - __IO uint32_t PIN[8]; /*!< (@ 0x400F6100) Portpin register port n */ - __I uint32_t RESERVED4[24]; - __IO uint32_t MPIN[8]; /*!< (@ 0x400F6180) Masked port register port n */ - __I uint32_t RESERVED5[24]; - __IO uint32_t SET[8]; /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */ - __I uint32_t RESERVED6[24]; - __O uint32_t CLR[8]; /*!< (@ 0x400F6280) Clear port n */ - __I uint32_t RESERVED7[24]; - __O uint32_t NOT[8]; /*!< (@ 0x400F6300) Toggle port n */ -} LPC_GPIO_PORT_Type; - - - -/******************************************** -** End of section using anonymous unions ** -*********************************************/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma pop -#else - #error Not supported compiler type -#endif - - -#ifdef CMSIS_BITPOSITIONS -// ------------------------------------------------------------------------------------------------ -// ----- SCT Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- SCT_CONFIG ------------------------------------------- -#define SCT_CONFIG_UNIFY_Pos 0 /*!< SCT CONFIG: UNIFY Position */ -#define SCT_CONFIG_UNIFY_Msk (0x01UL << SCT_CONFIG_UNIFY_Pos) /*!< SCT CONFIG: UNIFY Mask */ -#define SCT_CONFIG_CLKMODE_Pos 1 /*!< SCT CONFIG: CLKMODE Position */ -#define SCT_CONFIG_CLKMODE_Msk (0x03UL << SCT_CONFIG_CLKMODE_Pos) /*!< SCT CONFIG: CLKMODE Mask */ -#define SCT_CONFIG_CLKSEL_Pos 3 /*!< SCT CONFIG: CLKSEL Position */ -#define SCT_CONFIG_CLKSEL_Msk (0x0fUL << SCT_CONFIG_CLKSEL_Pos) /*!< SCT CONFIG: CLKSEL Mask */ -#define SCT_CONFIG_NORELAODL_NORELOADU_Pos 7 /*!< SCT CONFIG: NORELAODL_NORELOADU Position */ -#define SCT_CONFIG_NORELAODL_NORELOADU_Msk (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos) /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */ -#define SCT_CONFIG_NORELOADH_Pos 8 /*!< SCT CONFIG: NORELOADH Position */ -#define SCT_CONFIG_NORELOADH_Msk (0x01UL << SCT_CONFIG_NORELOADH_Pos) /*!< SCT CONFIG: NORELOADH Mask */ -#define SCT_CONFIG_INSYNCn_Pos 9 /*!< SCT CONFIG: INSYNCn Position */ -#define SCT_CONFIG_INSYNCn_Msk (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos) /*!< SCT CONFIG: INSYNCn Mask */ - -// ---------------------------------------- SCT_CTRL -------------------------------------------- -#define SCT_CTRL_DOWN_L_Pos 0 /*!< SCT CTRL: DOWN_L Position */ -#define SCT_CTRL_DOWN_L_Msk (0x01UL << SCT_CTRL_DOWN_L_Pos) /*!< SCT CTRL: DOWN_L Mask */ -#define SCT_CTRL_STOP_L_Pos 1 /*!< SCT CTRL: STOP_L Position */ -#define SCT_CTRL_STOP_L_Msk (0x01UL << SCT_CTRL_STOP_L_Pos) /*!< SCT CTRL: STOP_L Mask */ -#define SCT_CTRL_HALT_L_Pos 2 /*!< SCT CTRL: HALT_L Position */ -#define SCT_CTRL_HALT_L_Msk (0x01UL << SCT_CTRL_HALT_L_Pos) /*!< SCT CTRL: HALT_L Mask */ -#define SCT_CTRL_CLRCTR_L_Pos 3 /*!< SCT CTRL: CLRCTR_L Position */ -#define SCT_CTRL_CLRCTR_L_Msk (0x01UL << SCT_CTRL_CLRCTR_L_Pos) /*!< SCT CTRL: CLRCTR_L Mask */ -#define SCT_CTRL_BIDIR_L_Pos 4 /*!< SCT CTRL: BIDIR_L Position */ -#define SCT_CTRL_BIDIR_L_Msk (0x01UL << SCT_CTRL_BIDIR_L_Pos) /*!< SCT CTRL: BIDIR_L Mask */ -#define SCT_CTRL_PRE_L_Pos 5 /*!< SCT CTRL: PRE_L Position */ -#define SCT_CTRL_PRE_L_Msk (0x000000ffUL << SCT_CTRL_PRE_L_Pos) /*!< SCT CTRL: PRE_L Mask */ -#define SCT_CTRL_DOWN_H_Pos 16 /*!< SCT CTRL: DOWN_H Position */ -#define SCT_CTRL_DOWN_H_Msk (0x01UL << SCT_CTRL_DOWN_H_Pos) /*!< SCT CTRL: DOWN_H Mask */ -#define SCT_CTRL_STOP_H_Pos 17 /*!< SCT CTRL: STOP_H Position */ -#define SCT_CTRL_STOP_H_Msk (0x01UL << SCT_CTRL_STOP_H_Pos) /*!< SCT CTRL: STOP_H Mask */ -#define SCT_CTRL_HALT_H_Pos 18 /*!< SCT CTRL: HALT_H Position */ -#define SCT_CTRL_HALT_H_Msk (0x01UL << SCT_CTRL_HALT_H_Pos) /*!< SCT CTRL: HALT_H Mask */ -#define SCT_CTRL_CLRCTR_H_Pos 19 /*!< SCT CTRL: CLRCTR_H Position */ -#define SCT_CTRL_CLRCTR_H_Msk (0x01UL << SCT_CTRL_CLRCTR_H_Pos) /*!< SCT CTRL: CLRCTR_H Mask */ -#define SCT_CTRL_BIDIR_H_Pos 20 /*!< SCT CTRL: BIDIR_H Position */ -#define SCT_CTRL_BIDIR_H_Msk (0x01UL << SCT_CTRL_BIDIR_H_Pos) /*!< SCT CTRL: BIDIR_H Mask */ -#define SCT_CTRL_PRE_H_Pos 21 /*!< SCT CTRL: PRE_H Position */ -#define SCT_CTRL_PRE_H_Msk (0x000000ffUL << SCT_CTRL_PRE_H_Pos) /*!< SCT CTRL: PRE_H Mask */ - -// ---------------------------------------- SCT_LIMIT ------------------------------------------- -#define SCT_LIMIT_LIMMSK_L_Pos 0 /*!< SCT LIMIT: LIMMSK_L Position */ -#define SCT_LIMIT_LIMMSK_L_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos) /*!< SCT LIMIT: LIMMSK_L Mask */ -#define SCT_LIMIT_LIMMSK_H_Pos 16 /*!< SCT LIMIT: LIMMSK_H Position */ -#define SCT_LIMIT_LIMMSK_H_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos) /*!< SCT LIMIT: LIMMSK_H Mask */ - -// ---------------------------------------- SCT_HALT -------------------------------------------- -#define SCT_HALT_HALTMSK_L_Pos 0 /*!< SCT HALT: HALTMSK_L Position */ -#define SCT_HALT_HALTMSK_L_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos) /*!< SCT HALT: HALTMSK_L Mask */ -#define SCT_HALT_HALTMSK_H_Pos 16 /*!< SCT HALT: HALTMSK_H Position */ -#define SCT_HALT_HALTMSK_H_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos) /*!< SCT HALT: HALTMSK_H Mask */ - -// ---------------------------------------- SCT_STOP -------------------------------------------- -#define SCT_STOP_STOPMSK_L_Pos 0 /*!< SCT STOP: STOPMSK_L Position */ -#define SCT_STOP_STOPMSK_L_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos) /*!< SCT STOP: STOPMSK_L Mask */ -#define SCT_STOP_STOPMSK_H_Pos 16 /*!< SCT STOP: STOPMSK_H Position */ -#define SCT_STOP_STOPMSK_H_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos) /*!< SCT STOP: STOPMSK_H Mask */ - -// ---------------------------------------- SCT_START ------------------------------------------- -#define SCT_START_STARTMSK_L_Pos 0 /*!< SCT START: STARTMSK_L Position */ -#define SCT_START_STARTMSK_L_Msk (0x0000ffffUL << SCT_START_STARTMSK_L_Pos) /*!< SCT START: STARTMSK_L Mask */ -#define SCT_START_STARTMSK_H_Pos 16 /*!< SCT START: STARTMSK_H Position */ -#define SCT_START_STARTMSK_H_Msk (0x0000ffffUL << SCT_START_STARTMSK_H_Pos) /*!< SCT START: STARTMSK_H Mask */ - -// ---------------------------------------- SCT_COUNT ------------------------------------------- -#define SCT_COUNT_CTR_L_Pos 0 /*!< SCT COUNT: CTR_L Position */ -#define SCT_COUNT_CTR_L_Msk (0x0000ffffUL << SCT_COUNT_CTR_L_Pos) /*!< SCT COUNT: CTR_L Mask */ -#define SCT_COUNT_CTR_H_Pos 16 /*!< SCT COUNT: CTR_H Position */ -#define SCT_COUNT_CTR_H_Msk (0x0000ffffUL << SCT_COUNT_CTR_H_Pos) /*!< SCT COUNT: CTR_H Mask */ - -// ---------------------------------------- SCT_STATE ------------------------------------------- -#define SCT_STATE_STATE_L_Pos 0 /*!< SCT STATE: STATE_L Position */ -#define SCT_STATE_STATE_L_Msk (0x1fUL << SCT_STATE_STATE_L_Pos) /*!< SCT STATE: STATE_L Mask */ -#define SCT_STATE_STATE_H_Pos 16 /*!< SCT STATE: STATE_H Position */ -#define SCT_STATE_STATE_H_Msk (0x1fUL << SCT_STATE_STATE_H_Pos) /*!< SCT STATE: STATE_H Mask */ - -// ---------------------------------------- SCT_INPUT ------------------------------------------- -#define SCT_INPUT_AIN0_Pos 0 /*!< SCT INPUT: AIN0 Position */ -#define SCT_INPUT_AIN0_Msk (0x01UL << SCT_INPUT_AIN0_Pos) /*!< SCT INPUT: AIN0 Mask */ -#define SCT_INPUT_AIN1_Pos 1 /*!< SCT INPUT: AIN1 Position */ -#define SCT_INPUT_AIN1_Msk (0x01UL << SCT_INPUT_AIN1_Pos) /*!< SCT INPUT: AIN1 Mask */ -#define SCT_INPUT_AIN2_Pos 2 /*!< SCT INPUT: AIN2 Position */ -#define SCT_INPUT_AIN2_Msk (0x01UL << SCT_INPUT_AIN2_Pos) /*!< SCT INPUT: AIN2 Mask */ -#define SCT_INPUT_AIN3_Pos 3 /*!< SCT INPUT: AIN3 Position */ -#define SCT_INPUT_AIN3_Msk (0x01UL << SCT_INPUT_AIN3_Pos) /*!< SCT INPUT: AIN3 Mask */ -#define SCT_INPUT_AIN4_Pos 4 /*!< SCT INPUT: AIN4 Position */ -#define SCT_INPUT_AIN4_Msk (0x01UL << SCT_INPUT_AIN4_Pos) /*!< SCT INPUT: AIN4 Mask */ -#define SCT_INPUT_AIN5_Pos 5 /*!< SCT INPUT: AIN5 Position */ -#define SCT_INPUT_AIN5_Msk (0x01UL << SCT_INPUT_AIN5_Pos) /*!< SCT INPUT: AIN5 Mask */ -#define SCT_INPUT_AIN6_Pos 6 /*!< SCT INPUT: AIN6 Position */ -#define SCT_INPUT_AIN6_Msk (0x01UL << SCT_INPUT_AIN6_Pos) /*!< SCT INPUT: AIN6 Mask */ -#define SCT_INPUT_AIN7_Pos 7 /*!< SCT INPUT: AIN7 Position */ -#define SCT_INPUT_AIN7_Msk (0x01UL << SCT_INPUT_AIN7_Pos) /*!< SCT INPUT: AIN7 Mask */ -#define SCT_INPUT_SIN0_Pos 16 /*!< SCT INPUT: SIN0 Position */ -#define SCT_INPUT_SIN0_Msk (0x01UL << SCT_INPUT_SIN0_Pos) /*!< SCT INPUT: SIN0 Mask */ -#define SCT_INPUT_SIN1_Pos 17 /*!< SCT INPUT: SIN1 Position */ -#define SCT_INPUT_SIN1_Msk (0x01UL << SCT_INPUT_SIN1_Pos) /*!< SCT INPUT: SIN1 Mask */ -#define SCT_INPUT_SIN2_Pos 18 /*!< SCT INPUT: SIN2 Position */ -#define SCT_INPUT_SIN2_Msk (0x01UL << SCT_INPUT_SIN2_Pos) /*!< SCT INPUT: SIN2 Mask */ -#define SCT_INPUT_SIN3_Pos 19 /*!< SCT INPUT: SIN3 Position */ -#define SCT_INPUT_SIN3_Msk (0x01UL << SCT_INPUT_SIN3_Pos) /*!< SCT INPUT: SIN3 Mask */ -#define SCT_INPUT_SIN4_Pos 20 /*!< SCT INPUT: SIN4 Position */ -#define SCT_INPUT_SIN4_Msk (0x01UL << SCT_INPUT_SIN4_Pos) /*!< SCT INPUT: SIN4 Mask */ -#define SCT_INPUT_SIN5_Pos 21 /*!< SCT INPUT: SIN5 Position */ -#define SCT_INPUT_SIN5_Msk (0x01UL << SCT_INPUT_SIN5_Pos) /*!< SCT INPUT: SIN5 Mask */ -#define SCT_INPUT_SIN6_Pos 22 /*!< SCT INPUT: SIN6 Position */ -#define SCT_INPUT_SIN6_Msk (0x01UL << SCT_INPUT_SIN6_Pos) /*!< SCT INPUT: SIN6 Mask */ -#define SCT_INPUT_SIN7_Pos 23 /*!< SCT INPUT: SIN7 Position */ -#define SCT_INPUT_SIN7_Msk (0x01UL << SCT_INPUT_SIN7_Pos) /*!< SCT INPUT: SIN7 Mask */ - -// --------------------------------------- SCT_REGMODE ------------------------------------------ -#define SCT_REGMODE_REGMOD_L0_Pos 0 /*!< SCT REGMODE: REGMOD_L0 Position */ -#define SCT_REGMODE_REGMOD_L0_Msk (0x01UL << SCT_REGMODE_REGMOD_L0_Pos) /*!< SCT REGMODE: REGMOD_L0 Mask */ -#define SCT_REGMODE_REGMOD_L1_Pos 1 /*!< SCT REGMODE: REGMOD_L1 Position */ -#define SCT_REGMODE_REGMOD_L1_Msk (0x01UL << SCT_REGMODE_REGMOD_L1_Pos) /*!< SCT REGMODE: REGMOD_L1 Mask */ -#define SCT_REGMODE_REGMOD_L2_Pos 2 /*!< SCT REGMODE: REGMOD_L2 Position */ -#define SCT_REGMODE_REGMOD_L2_Msk (0x01UL << SCT_REGMODE_REGMOD_L2_Pos) /*!< SCT REGMODE: REGMOD_L2 Mask */ -#define SCT_REGMODE_REGMOD_L3_Pos 3 /*!< SCT REGMODE: REGMOD_L3 Position */ -#define SCT_REGMODE_REGMOD_L3_Msk (0x01UL << SCT_REGMODE_REGMOD_L3_Pos) /*!< SCT REGMODE: REGMOD_L3 Mask */ -#define SCT_REGMODE_REGMOD_L4_Pos 4 /*!< SCT REGMODE: REGMOD_L4 Position */ -#define SCT_REGMODE_REGMOD_L4_Msk (0x01UL << SCT_REGMODE_REGMOD_L4_Pos) /*!< SCT REGMODE: REGMOD_L4 Mask */ -#define SCT_REGMODE_REGMOD_L5_Pos 5 /*!< SCT REGMODE: REGMOD_L5 Position */ -#define SCT_REGMODE_REGMOD_L5_Msk (0x01UL << SCT_REGMODE_REGMOD_L5_Pos) /*!< SCT REGMODE: REGMOD_L5 Mask */ -#define SCT_REGMODE_REGMOD_L6_Pos 6 /*!< SCT REGMODE: REGMOD_L6 Position */ -#define SCT_REGMODE_REGMOD_L6_Msk (0x01UL << SCT_REGMODE_REGMOD_L6_Pos) /*!< SCT REGMODE: REGMOD_L6 Mask */ -#define SCT_REGMODE_REGMOD_L7_Pos 7 /*!< SCT REGMODE: REGMOD_L7 Position */ -#define SCT_REGMODE_REGMOD_L7_Msk (0x01UL << SCT_REGMODE_REGMOD_L7_Pos) /*!< SCT REGMODE: REGMOD_L7 Mask */ -#define SCT_REGMODE_REGMOD_L8_Pos 8 /*!< SCT REGMODE: REGMOD_L8 Position */ -#define SCT_REGMODE_REGMOD_L8_Msk (0x01UL << SCT_REGMODE_REGMOD_L8_Pos) /*!< SCT REGMODE: REGMOD_L8 Mask */ -#define SCT_REGMODE_REGMOD_L9_Pos 9 /*!< SCT REGMODE: REGMOD_L9 Position */ -#define SCT_REGMODE_REGMOD_L9_Msk (0x01UL << SCT_REGMODE_REGMOD_L9_Pos) /*!< SCT REGMODE: REGMOD_L9 Mask */ -#define SCT_REGMODE_REGMOD_L10_Pos 10 /*!< SCT REGMODE: REGMOD_L10 Position */ -#define SCT_REGMODE_REGMOD_L10_Msk (0x01UL << SCT_REGMODE_REGMOD_L10_Pos) /*!< SCT REGMODE: REGMOD_L10 Mask */ -#define SCT_REGMODE_REGMOD_L11_Pos 11 /*!< SCT REGMODE: REGMOD_L11 Position */ -#define SCT_REGMODE_REGMOD_L11_Msk (0x01UL << SCT_REGMODE_REGMOD_L11_Pos) /*!< SCT REGMODE: REGMOD_L11 Mask */ -#define SCT_REGMODE_REGMOD_L12_Pos 12 /*!< SCT REGMODE: REGMOD_L12 Position */ -#define SCT_REGMODE_REGMOD_L12_Msk (0x01UL << SCT_REGMODE_REGMOD_L12_Pos) /*!< SCT REGMODE: REGMOD_L12 Mask */ -#define SCT_REGMODE_REGMOD_L13_Pos 13 /*!< SCT REGMODE: REGMOD_L13 Position */ -#define SCT_REGMODE_REGMOD_L13_Msk (0x01UL << SCT_REGMODE_REGMOD_L13_Pos) /*!< SCT REGMODE: REGMOD_L13 Mask */ -#define SCT_REGMODE_REGMOD_L14_Pos 14 /*!< SCT REGMODE: REGMOD_L14 Position */ -#define SCT_REGMODE_REGMOD_L14_Msk (0x01UL << SCT_REGMODE_REGMOD_L14_Pos) /*!< SCT REGMODE: REGMOD_L14 Mask */ -#define SCT_REGMODE_REGMOD_L15_Pos 15 /*!< SCT REGMODE: REGMOD_L15 Position */ -#define SCT_REGMODE_REGMOD_L15_Msk (0x01UL << SCT_REGMODE_REGMOD_L15_Pos) /*!< SCT REGMODE: REGMOD_L15 Mask */ -#define SCT_REGMODE_REGMOD_H16_Pos 16 /*!< SCT REGMODE: REGMOD_H16 Position */ -#define SCT_REGMODE_REGMOD_H16_Msk (0x01UL << SCT_REGMODE_REGMOD_H16_Pos) /*!< SCT REGMODE: REGMOD_H16 Mask */ -#define SCT_REGMODE_REGMOD_H17_Pos 17 /*!< SCT REGMODE: REGMOD_H17 Position */ -#define SCT_REGMODE_REGMOD_H17_Msk (0x01UL << SCT_REGMODE_REGMOD_H17_Pos) /*!< SCT REGMODE: REGMOD_H17 Mask */ -#define SCT_REGMODE_REGMOD_H18_Pos 18 /*!< SCT REGMODE: REGMOD_H18 Position */ -#define SCT_REGMODE_REGMOD_H18_Msk (0x01UL << SCT_REGMODE_REGMOD_H18_Pos) /*!< SCT REGMODE: REGMOD_H18 Mask */ -#define SCT_REGMODE_REGMOD_H19_Pos 19 /*!< SCT REGMODE: REGMOD_H19 Position */ -#define SCT_REGMODE_REGMOD_H19_Msk (0x01UL << SCT_REGMODE_REGMOD_H19_Pos) /*!< SCT REGMODE: REGMOD_H19 Mask */ -#define SCT_REGMODE_REGMOD_H20_Pos 20 /*!< SCT REGMODE: REGMOD_H20 Position */ -#define SCT_REGMODE_REGMOD_H20_Msk (0x01UL << SCT_REGMODE_REGMOD_H20_Pos) /*!< SCT REGMODE: REGMOD_H20 Mask */ -#define SCT_REGMODE_REGMOD_H21_Pos 21 /*!< SCT REGMODE: REGMOD_H21 Position */ -#define SCT_REGMODE_REGMOD_H21_Msk (0x01UL << SCT_REGMODE_REGMOD_H21_Pos) /*!< SCT REGMODE: REGMOD_H21 Mask */ -#define SCT_REGMODE_REGMOD_H22_Pos 22 /*!< SCT REGMODE: REGMOD_H22 Position */ -#define SCT_REGMODE_REGMOD_H22_Msk (0x01UL << SCT_REGMODE_REGMOD_H22_Pos) /*!< SCT REGMODE: REGMOD_H22 Mask */ -#define SCT_REGMODE_REGMOD_H23_Pos 23 /*!< SCT REGMODE: REGMOD_H23 Position */ -#define SCT_REGMODE_REGMOD_H23_Msk (0x01UL << SCT_REGMODE_REGMOD_H23_Pos) /*!< SCT REGMODE: REGMOD_H23 Mask */ -#define SCT_REGMODE_REGMOD_H24_Pos 24 /*!< SCT REGMODE: REGMOD_H24 Position */ -#define SCT_REGMODE_REGMOD_H24_Msk (0x01UL << SCT_REGMODE_REGMOD_H24_Pos) /*!< SCT REGMODE: REGMOD_H24 Mask */ -#define SCT_REGMODE_REGMOD_H25_Pos 25 /*!< SCT REGMODE: REGMOD_H25 Position */ -#define SCT_REGMODE_REGMOD_H25_Msk (0x01UL << SCT_REGMODE_REGMOD_H25_Pos) /*!< SCT REGMODE: REGMOD_H25 Mask */ -#define SCT_REGMODE_REGMOD_H26_Pos 26 /*!< SCT REGMODE: REGMOD_H26 Position */ -#define SCT_REGMODE_REGMOD_H26_Msk (0x01UL << SCT_REGMODE_REGMOD_H26_Pos) /*!< SCT REGMODE: REGMOD_H26 Mask */ -#define SCT_REGMODE_REGMOD_H27_Pos 27 /*!< SCT REGMODE: REGMOD_H27 Position */ -#define SCT_REGMODE_REGMOD_H27_Msk (0x01UL << SCT_REGMODE_REGMOD_H27_Pos) /*!< SCT REGMODE: REGMOD_H27 Mask */ -#define SCT_REGMODE_REGMOD_H28_Pos 28 /*!< SCT REGMODE: REGMOD_H28 Position */ -#define SCT_REGMODE_REGMOD_H28_Msk (0x01UL << SCT_REGMODE_REGMOD_H28_Pos) /*!< SCT REGMODE: REGMOD_H28 Mask */ -#define SCT_REGMODE_REGMOD_H29_Pos 29 /*!< SCT REGMODE: REGMOD_H29 Position */ -#define SCT_REGMODE_REGMOD_H29_Msk (0x01UL << SCT_REGMODE_REGMOD_H29_Pos) /*!< SCT REGMODE: REGMOD_H29 Mask */ -#define SCT_REGMODE_REGMOD_H30_Pos 30 /*!< SCT REGMODE: REGMOD_H30 Position */ -#define SCT_REGMODE_REGMOD_H30_Msk (0x01UL << SCT_REGMODE_REGMOD_H30_Pos) /*!< SCT REGMODE: REGMOD_H30 Mask */ -#define SCT_REGMODE_REGMOD_H31_Pos 31 /*!< SCT REGMODE: REGMOD_H31 Position */ -#define SCT_REGMODE_REGMOD_H31_Msk (0x01UL << SCT_REGMODE_REGMOD_H31_Pos) /*!< SCT REGMODE: REGMOD_H31 Mask */ - -// --------------------------------------- SCT_OUTPUT ------------------------------------------- -#define SCT_OUTPUT_OUT0_Pos 0 /*!< SCT OUTPUT: OUT0 Position */ -#define SCT_OUTPUT_OUT0_Msk (0x01UL << SCT_OUTPUT_OUT0_Pos) /*!< SCT OUTPUT: OUT0 Mask */ -#define SCT_OUTPUT_OUT1_Pos 1 /*!< SCT OUTPUT: OUT1 Position */ -#define SCT_OUTPUT_OUT1_Msk (0x01UL << SCT_OUTPUT_OUT1_Pos) /*!< SCT OUTPUT: OUT1 Mask */ -#define SCT_OUTPUT_OUT2_Pos 2 /*!< SCT OUTPUT: OUT2 Position */ -#define SCT_OUTPUT_OUT2_Msk (0x01UL << SCT_OUTPUT_OUT2_Pos) /*!< SCT OUTPUT: OUT2 Mask */ -#define SCT_OUTPUT_OUT3_Pos 3 /*!< SCT OUTPUT: OUT3 Position */ -#define SCT_OUTPUT_OUT3_Msk (0x01UL << SCT_OUTPUT_OUT3_Pos) /*!< SCT OUTPUT: OUT3 Mask */ -#define SCT_OUTPUT_OUT4_Pos 4 /*!< SCT OUTPUT: OUT4 Position */ -#define SCT_OUTPUT_OUT4_Msk (0x01UL << SCT_OUTPUT_OUT4_Pos) /*!< SCT OUTPUT: OUT4 Mask */ -#define SCT_OUTPUT_OUT5_Pos 5 /*!< SCT OUTPUT: OUT5 Position */ -#define SCT_OUTPUT_OUT5_Msk (0x01UL << SCT_OUTPUT_OUT5_Pos) /*!< SCT OUTPUT: OUT5 Mask */ -#define SCT_OUTPUT_OUT6_Pos 6 /*!< SCT OUTPUT: OUT6 Position */ -#define SCT_OUTPUT_OUT6_Msk (0x01UL << SCT_OUTPUT_OUT6_Pos) /*!< SCT OUTPUT: OUT6 Mask */ -#define SCT_OUTPUT_OUT7_Pos 7 /*!< SCT OUTPUT: OUT7 Position */ -#define SCT_OUTPUT_OUT7_Msk (0x01UL << SCT_OUTPUT_OUT7_Pos) /*!< SCT OUTPUT: OUT7 Mask */ -#define SCT_OUTPUT_OUT8_Pos 8 /*!< SCT OUTPUT: OUT8 Position */ -#define SCT_OUTPUT_OUT8_Msk (0x01UL << SCT_OUTPUT_OUT8_Pos) /*!< SCT OUTPUT: OUT8 Mask */ -#define SCT_OUTPUT_OUT9_Pos 9 /*!< SCT OUTPUT: OUT9 Position */ -#define SCT_OUTPUT_OUT9_Msk (0x01UL << SCT_OUTPUT_OUT9_Pos) /*!< SCT OUTPUT: OUT9 Mask */ -#define SCT_OUTPUT_OUT10_Pos 10 /*!< SCT OUTPUT: OUT10 Position */ -#define SCT_OUTPUT_OUT10_Msk (0x01UL << SCT_OUTPUT_OUT10_Pos) /*!< SCT OUTPUT: OUT10 Mask */ -#define SCT_OUTPUT_OUT11_Pos 11 /*!< SCT OUTPUT: OUT11 Position */ -#define SCT_OUTPUT_OUT11_Msk (0x01UL << SCT_OUTPUT_OUT11_Pos) /*!< SCT OUTPUT: OUT11 Mask */ -#define SCT_OUTPUT_OUT12_Pos 12 /*!< SCT OUTPUT: OUT12 Position */ -#define SCT_OUTPUT_OUT12_Msk (0x01UL << SCT_OUTPUT_OUT12_Pos) /*!< SCT OUTPUT: OUT12 Mask */ -#define SCT_OUTPUT_OUT13_Pos 13 /*!< SCT OUTPUT: OUT13 Position */ -#define SCT_OUTPUT_OUT13_Msk (0x01UL << SCT_OUTPUT_OUT13_Pos) /*!< SCT OUTPUT: OUT13 Mask */ -#define SCT_OUTPUT_OUT14_Pos 14 /*!< SCT OUTPUT: OUT14 Position */ -#define SCT_OUTPUT_OUT14_Msk (0x01UL << SCT_OUTPUT_OUT14_Pos) /*!< SCT OUTPUT: OUT14 Mask */ -#define SCT_OUTPUT_OUT15_Pos 15 /*!< SCT OUTPUT: OUT15 Position */ -#define SCT_OUTPUT_OUT15_Msk (0x01UL << SCT_OUTPUT_OUT15_Pos) /*!< SCT OUTPUT: OUT15 Mask */ - -// ------------------------------------ SCT_OUTPUTDIRCTRL --------------------------------------- -#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos 0 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos 2 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos 4 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos 6 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos 8 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos 10 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos 12 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos 14 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos 16 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos 18 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos 20 /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos 22 /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos 24 /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos 26 /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos 28 /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos 30 /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask */ - -// ----------------------------------------- SCT_RES -------------------------------------------- -#define SCT_RES_O0RES_Pos 0 /*!< SCT RES: O0RES Position */ -#define SCT_RES_O0RES_Msk (0x03UL << SCT_RES_O0RES_Pos) /*!< SCT RES: O0RES Mask */ -#define SCT_RES_O1RES_Pos 2 /*!< SCT RES: O1RES Position */ -#define SCT_RES_O1RES_Msk (0x03UL << SCT_RES_O1RES_Pos) /*!< SCT RES: O1RES Mask */ -#define SCT_RES_O2RES_Pos 4 /*!< SCT RES: O2RES Position */ -#define SCT_RES_O2RES_Msk (0x03UL << SCT_RES_O2RES_Pos) /*!< SCT RES: O2RES Mask */ -#define SCT_RES_O3RES_Pos 6 /*!< SCT RES: O3RES Position */ -#define SCT_RES_O3RES_Msk (0x03UL << SCT_RES_O3RES_Pos) /*!< SCT RES: O3RES Mask */ -#define SCT_RES_O4RES_Pos 8 /*!< SCT RES: O4RES Position */ -#define SCT_RES_O4RES_Msk (0x03UL << SCT_RES_O4RES_Pos) /*!< SCT RES: O4RES Mask */ -#define SCT_RES_O5RES_Pos 10 /*!< SCT RES: O5RES Position */ -#define SCT_RES_O5RES_Msk (0x03UL << SCT_RES_O5RES_Pos) /*!< SCT RES: O5RES Mask */ -#define SCT_RES_O6RES_Pos 12 /*!< SCT RES: O6RES Position */ -#define SCT_RES_O6RES_Msk (0x03UL << SCT_RES_O6RES_Pos) /*!< SCT RES: O6RES Mask */ -#define SCT_RES_O7RES_Pos 14 /*!< SCT RES: O7RES Position */ -#define SCT_RES_O7RES_Msk (0x03UL << SCT_RES_O7RES_Pos) /*!< SCT RES: O7RES Mask */ -#define SCT_RES_O8RES_Pos 16 /*!< SCT RES: O8RES Position */ -#define SCT_RES_O8RES_Msk (0x03UL << SCT_RES_O8RES_Pos) /*!< SCT RES: O8RES Mask */ -#define SCT_RES_O9RES_Pos 18 /*!< SCT RES: O9RES Position */ -#define SCT_RES_O9RES_Msk (0x03UL << SCT_RES_O9RES_Pos) /*!< SCT RES: O9RES Mask */ -#define SCT_RES_O10RES_Pos 20 /*!< SCT RES: O10RES Position */ -#define SCT_RES_O10RES_Msk (0x03UL << SCT_RES_O10RES_Pos) /*!< SCT RES: O10RES Mask */ -#define SCT_RES_O11RES_Pos 22 /*!< SCT RES: O11RES Position */ -#define SCT_RES_O11RES_Msk (0x03UL << SCT_RES_O11RES_Pos) /*!< SCT RES: O11RES Mask */ -#define SCT_RES_O12RES_Pos 24 /*!< SCT RES: O12RES Position */ -#define SCT_RES_O12RES_Msk (0x03UL << SCT_RES_O12RES_Pos) /*!< SCT RES: O12RES Mask */ -#define SCT_RES_O13RES_Pos 26 /*!< SCT RES: O13RES Position */ -#define SCT_RES_O13RES_Msk (0x03UL << SCT_RES_O13RES_Pos) /*!< SCT RES: O13RES Mask */ -#define SCT_RES_O14RES_Pos 28 /*!< SCT RES: O14RES Position */ -#define SCT_RES_O14RES_Msk (0x03UL << SCT_RES_O14RES_Pos) /*!< SCT RES: O14RES Mask */ -#define SCT_RES_O15RES_Pos 30 /*!< SCT RES: O15RES Position */ -#define SCT_RES_O15RES_Msk (0x03UL << SCT_RES_O15RES_Pos) /*!< SCT RES: O15RES Mask */ - -// --------------------------------------- SCT_DMAREQ0 ------------------------------------------ -#define SCT_DMAREQ0_DEV_0_0_Pos 0 /*!< SCT DMAREQ0: DEV_0_0 Position */ -#define SCT_DMAREQ0_DEV_0_0_Msk (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos) /*!< SCT DMAREQ0: DEV_0_0 Mask */ -#define SCT_DMAREQ0_DEV_0_1_Pos 1 /*!< SCT DMAREQ0: DEV_0_1 Position */ -#define SCT_DMAREQ0_DEV_0_1_Msk (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos) /*!< SCT DMAREQ0: DEV_0_1 Mask */ -#define SCT_DMAREQ0_DEV_0_2_Pos 2 /*!< SCT DMAREQ0: DEV_0_2 Position */ -#define SCT_DMAREQ0_DEV_0_2_Msk (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos) /*!< SCT DMAREQ0: DEV_0_2 Mask */ -#define SCT_DMAREQ0_DEV_0_3_Pos 3 /*!< SCT DMAREQ0: DEV_0_3 Position */ -#define SCT_DMAREQ0_DEV_0_3_Msk (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos) /*!< SCT DMAREQ0: DEV_0_3 Mask */ -#define SCT_DMAREQ0_DEV_0_4_Pos 4 /*!< SCT DMAREQ0: DEV_0_4 Position */ -#define SCT_DMAREQ0_DEV_0_4_Msk (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos) /*!< SCT DMAREQ0: DEV_0_4 Mask */ -#define SCT_DMAREQ0_DEV_0_5_Pos 5 /*!< SCT DMAREQ0: DEV_0_5 Position */ -#define SCT_DMAREQ0_DEV_0_5_Msk (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos) /*!< SCT DMAREQ0: DEV_0_5 Mask */ -#define SCT_DMAREQ0_DEV_0_6_Pos 6 /*!< SCT DMAREQ0: DEV_0_6 Position */ -#define SCT_DMAREQ0_DEV_0_6_Msk (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos) /*!< SCT DMAREQ0: DEV_0_6 Mask */ -#define SCT_DMAREQ0_DEV_0_7_Pos 7 /*!< SCT DMAREQ0: DEV_0_7 Position */ -#define SCT_DMAREQ0_DEV_0_7_Msk (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos) /*!< SCT DMAREQ0: DEV_0_7 Mask */ -#define SCT_DMAREQ0_DEV_0_8_Pos 8 /*!< SCT DMAREQ0: DEV_0_8 Position */ -#define SCT_DMAREQ0_DEV_0_8_Msk (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos) /*!< SCT DMAREQ0: DEV_0_8 Mask */ -#define SCT_DMAREQ0_DEV_0_9_Pos 9 /*!< SCT DMAREQ0: DEV_0_9 Position */ -#define SCT_DMAREQ0_DEV_0_9_Msk (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos) /*!< SCT DMAREQ0: DEV_0_9 Mask */ -#define SCT_DMAREQ0_DEV_0_10_Pos 10 /*!< SCT DMAREQ0: DEV_0_10 Position */ -#define SCT_DMAREQ0_DEV_0_10_Msk (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos) /*!< SCT DMAREQ0: DEV_0_10 Mask */ -#define SCT_DMAREQ0_DEV_0_11_Pos 11 /*!< SCT DMAREQ0: DEV_0_11 Position */ -#define SCT_DMAREQ0_DEV_0_11_Msk (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos) /*!< SCT DMAREQ0: DEV_0_11 Mask */ -#define SCT_DMAREQ0_DEV_0_12_Pos 12 /*!< SCT DMAREQ0: DEV_0_12 Position */ -#define SCT_DMAREQ0_DEV_0_12_Msk (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos) /*!< SCT DMAREQ0: DEV_0_12 Mask */ -#define SCT_DMAREQ0_DEV_0_13_Pos 13 /*!< SCT DMAREQ0: DEV_0_13 Position */ -#define SCT_DMAREQ0_DEV_0_13_Msk (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos) /*!< SCT DMAREQ0: DEV_0_13 Mask */ -#define SCT_DMAREQ0_DEV_0_14_Pos 14 /*!< SCT DMAREQ0: DEV_0_14 Position */ -#define SCT_DMAREQ0_DEV_0_14_Msk (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos) /*!< SCT DMAREQ0: DEV_0_14 Mask */ -#define SCT_DMAREQ0_DEV_0_15_Pos 15 /*!< SCT DMAREQ0: DEV_0_15 Position */ -#define SCT_DMAREQ0_DEV_0_15_Msk (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos) /*!< SCT DMAREQ0: DEV_0_15 Mask */ -#define SCT_DMAREQ0_DRL0_Pos 30 /*!< SCT DMAREQ0: DRL0 Position */ -#define SCT_DMAREQ0_DRL0_Msk (0x01UL << SCT_DMAREQ0_DRL0_Pos) /*!< SCT DMAREQ0: DRL0 Mask */ -#define SCT_DMAREQ0_DRQ0_Pos 31 /*!< SCT DMAREQ0: DRQ0 Position */ -#define SCT_DMAREQ0_DRQ0_Msk (0x01UL << SCT_DMAREQ0_DRQ0_Pos) /*!< SCT DMAREQ0: DRQ0 Mask */ - -// --------------------------------------- SCT_DMAREQ1 ------------------------------------------ -#define SCT_DMAREQ1_DEV_1_0_Pos 0 /*!< SCT DMAREQ1: DEV_1_0 Position */ -#define SCT_DMAREQ1_DEV_1_0_Msk (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos) /*!< SCT DMAREQ1: DEV_1_0 Mask */ -#define SCT_DMAREQ1_DEV_1_1_Pos 1 /*!< SCT DMAREQ1: DEV_1_1 Position */ -#define SCT_DMAREQ1_DEV_1_1_Msk (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos) /*!< SCT DMAREQ1: DEV_1_1 Mask */ -#define SCT_DMAREQ1_DEV_1_2_Pos 2 /*!< SCT DMAREQ1: DEV_1_2 Position */ -#define SCT_DMAREQ1_DEV_1_2_Msk (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos) /*!< SCT DMAREQ1: DEV_1_2 Mask */ -#define SCT_DMAREQ1_DEV_1_3_Pos 3 /*!< SCT DMAREQ1: DEV_1_3 Position */ -#define SCT_DMAREQ1_DEV_1_3_Msk (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos) /*!< SCT DMAREQ1: DEV_1_3 Mask */ -#define SCT_DMAREQ1_DEV_1_4_Pos 4 /*!< SCT DMAREQ1: DEV_1_4 Position */ -#define SCT_DMAREQ1_DEV_1_4_Msk (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos) /*!< SCT DMAREQ1: DEV_1_4 Mask */ -#define SCT_DMAREQ1_DEV_1_5_Pos 5 /*!< SCT DMAREQ1: DEV_1_5 Position */ -#define SCT_DMAREQ1_DEV_1_5_Msk (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos) /*!< SCT DMAREQ1: DEV_1_5 Mask */ -#define SCT_DMAREQ1_DEV_1_6_Pos 6 /*!< SCT DMAREQ1: DEV_1_6 Position */ -#define SCT_DMAREQ1_DEV_1_6_Msk (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos) /*!< SCT DMAREQ1: DEV_1_6 Mask */ -#define SCT_DMAREQ1_DEV_1_7_Pos 7 /*!< SCT DMAREQ1: DEV_1_7 Position */ -#define SCT_DMAREQ1_DEV_1_7_Msk (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos) /*!< SCT DMAREQ1: DEV_1_7 Mask */ -#define SCT_DMAREQ1_DEV_1_8_Pos 8 /*!< SCT DMAREQ1: DEV_1_8 Position */ -#define SCT_DMAREQ1_DEV_1_8_Msk (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos) /*!< SCT DMAREQ1: DEV_1_8 Mask */ -#define SCT_DMAREQ1_DEV_1_9_Pos 9 /*!< SCT DMAREQ1: DEV_1_9 Position */ -#define SCT_DMAREQ1_DEV_1_9_Msk (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos) /*!< SCT DMAREQ1: DEV_1_9 Mask */ -#define SCT_DMAREQ1_DEV_1_10_Pos 10 /*!< SCT DMAREQ1: DEV_1_10 Position */ -#define SCT_DMAREQ1_DEV_1_10_Msk (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos) /*!< SCT DMAREQ1: DEV_1_10 Mask */ -#define SCT_DMAREQ1_DEV_1_11_Pos 11 /*!< SCT DMAREQ1: DEV_1_11 Position */ -#define SCT_DMAREQ1_DEV_1_11_Msk (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos) /*!< SCT DMAREQ1: DEV_1_11 Mask */ -#define SCT_DMAREQ1_DEV_1_12_Pos 12 /*!< SCT DMAREQ1: DEV_1_12 Position */ -#define SCT_DMAREQ1_DEV_1_12_Msk (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos) /*!< SCT DMAREQ1: DEV_1_12 Mask */ -#define SCT_DMAREQ1_DEV_1_13_Pos 13 /*!< SCT DMAREQ1: DEV_1_13 Position */ -#define SCT_DMAREQ1_DEV_1_13_Msk (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos) /*!< SCT DMAREQ1: DEV_1_13 Mask */ -#define SCT_DMAREQ1_DEV_1_14_Pos 14 /*!< SCT DMAREQ1: DEV_1_14 Position */ -#define SCT_DMAREQ1_DEV_1_14_Msk (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos) /*!< SCT DMAREQ1: DEV_1_14 Mask */ -#define SCT_DMAREQ1_DEV_1_15_Pos 15 /*!< SCT DMAREQ1: DEV_1_15 Position */ -#define SCT_DMAREQ1_DEV_1_15_Msk (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos) /*!< SCT DMAREQ1: DEV_1_15 Mask */ -#define SCT_DMAREQ1_DRL1_Pos 30 /*!< SCT DMAREQ1: DRL1 Position */ -#define SCT_DMAREQ1_DRL1_Msk (0x01UL << SCT_DMAREQ1_DRL1_Pos) /*!< SCT DMAREQ1: DRL1 Mask */ -#define SCT_DMAREQ1_DRQ1_Pos 31 /*!< SCT DMAREQ1: DRQ1 Position */ -#define SCT_DMAREQ1_DRQ1_Msk (0x01UL << SCT_DMAREQ1_DRQ1_Pos) /*!< SCT DMAREQ1: DRQ1 Mask */ - -// ---------------------------------------- SCT_EVEN -------------------------------------------- -#define SCT_EVEN_IEN0_Pos 0 /*!< SCT EVEN: IEN0 Position */ -#define SCT_EVEN_IEN0_Msk (0x01UL << SCT_EVEN_IEN0_Pos) /*!< SCT EVEN: IEN0 Mask */ -#define SCT_EVEN_IEN1_Pos 1 /*!< SCT EVEN: IEN1 Position */ -#define SCT_EVEN_IEN1_Msk (0x01UL << SCT_EVEN_IEN1_Pos) /*!< SCT EVEN: IEN1 Mask */ -#define SCT_EVEN_IEN2_Pos 2 /*!< SCT EVEN: IEN2 Position */ -#define SCT_EVEN_IEN2_Msk (0x01UL << SCT_EVEN_IEN2_Pos) /*!< SCT EVEN: IEN2 Mask */ -#define SCT_EVEN_IEN3_Pos 3 /*!< SCT EVEN: IEN3 Position */ -#define SCT_EVEN_IEN3_Msk (0x01UL << SCT_EVEN_IEN3_Pos) /*!< SCT EVEN: IEN3 Mask */ -#define SCT_EVEN_IEN4_Pos 4 /*!< SCT EVEN: IEN4 Position */ -#define SCT_EVEN_IEN4_Msk (0x01UL << SCT_EVEN_IEN4_Pos) /*!< SCT EVEN: IEN4 Mask */ -#define SCT_EVEN_IEN5_Pos 5 /*!< SCT EVEN: IEN5 Position */ -#define SCT_EVEN_IEN5_Msk (0x01UL << SCT_EVEN_IEN5_Pos) /*!< SCT EVEN: IEN5 Mask */ -#define SCT_EVEN_IEN6_Pos 6 /*!< SCT EVEN: IEN6 Position */ -#define SCT_EVEN_IEN6_Msk (0x01UL << SCT_EVEN_IEN6_Pos) /*!< SCT EVEN: IEN6 Mask */ -#define SCT_EVEN_IEN7_Pos 7 /*!< SCT EVEN: IEN7 Position */ -#define SCT_EVEN_IEN7_Msk (0x01UL << SCT_EVEN_IEN7_Pos) /*!< SCT EVEN: IEN7 Mask */ -#define SCT_EVEN_IEN8_Pos 8 /*!< SCT EVEN: IEN8 Position */ -#define SCT_EVEN_IEN8_Msk (0x01UL << SCT_EVEN_IEN8_Pos) /*!< SCT EVEN: IEN8 Mask */ -#define SCT_EVEN_IEN9_Pos 9 /*!< SCT EVEN: IEN9 Position */ -#define SCT_EVEN_IEN9_Msk (0x01UL << SCT_EVEN_IEN9_Pos) /*!< SCT EVEN: IEN9 Mask */ -#define SCT_EVEN_IEN10_Pos 10 /*!< SCT EVEN: IEN10 Position */ -#define SCT_EVEN_IEN10_Msk (0x01UL << SCT_EVEN_IEN10_Pos) /*!< SCT EVEN: IEN10 Mask */ -#define SCT_EVEN_IEN11_Pos 11 /*!< SCT EVEN: IEN11 Position */ -#define SCT_EVEN_IEN11_Msk (0x01UL << SCT_EVEN_IEN11_Pos) /*!< SCT EVEN: IEN11 Mask */ -#define SCT_EVEN_IEN12_Pos 12 /*!< SCT EVEN: IEN12 Position */ -#define SCT_EVEN_IEN12_Msk (0x01UL << SCT_EVEN_IEN12_Pos) /*!< SCT EVEN: IEN12 Mask */ -#define SCT_EVEN_IEN13_Pos 13 /*!< SCT EVEN: IEN13 Position */ -#define SCT_EVEN_IEN13_Msk (0x01UL << SCT_EVEN_IEN13_Pos) /*!< SCT EVEN: IEN13 Mask */ -#define SCT_EVEN_IEN14_Pos 14 /*!< SCT EVEN: IEN14 Position */ -#define SCT_EVEN_IEN14_Msk (0x01UL << SCT_EVEN_IEN14_Pos) /*!< SCT EVEN: IEN14 Mask */ -#define SCT_EVEN_IEN15_Pos 15 /*!< SCT EVEN: IEN15 Position */ -#define SCT_EVEN_IEN15_Msk (0x01UL << SCT_EVEN_IEN15_Pos) /*!< SCT EVEN: IEN15 Mask */ - -// --------------------------------------- SCT_EVFLAG ------------------------------------------- -#define SCT_EVFLAG_FLAG0_Pos 0 /*!< SCT EVFLAG: FLAG0 Position */ -#define SCT_EVFLAG_FLAG0_Msk (0x01UL << SCT_EVFLAG_FLAG0_Pos) /*!< SCT EVFLAG: FLAG0 Mask */ -#define SCT_EVFLAG_FLAG1_Pos 1 /*!< SCT EVFLAG: FLAG1 Position */ -#define SCT_EVFLAG_FLAG1_Msk (0x01UL << SCT_EVFLAG_FLAG1_Pos) /*!< SCT EVFLAG: FLAG1 Mask */ -#define SCT_EVFLAG_FLAG2_Pos 2 /*!< SCT EVFLAG: FLAG2 Position */ -#define SCT_EVFLAG_FLAG2_Msk (0x01UL << SCT_EVFLAG_FLAG2_Pos) /*!< SCT EVFLAG: FLAG2 Mask */ -#define SCT_EVFLAG_FLAG3_Pos 3 /*!< SCT EVFLAG: FLAG3 Position */ -#define SCT_EVFLAG_FLAG3_Msk (0x01UL << SCT_EVFLAG_FLAG3_Pos) /*!< SCT EVFLAG: FLAG3 Mask */ -#define SCT_EVFLAG_FLAG4_Pos 4 /*!< SCT EVFLAG: FLAG4 Position */ -#define SCT_EVFLAG_FLAG4_Msk (0x01UL << SCT_EVFLAG_FLAG4_Pos) /*!< SCT EVFLAG: FLAG4 Mask */ -#define SCT_EVFLAG_FLAG5_Pos 5 /*!< SCT EVFLAG: FLAG5 Position */ -#define SCT_EVFLAG_FLAG5_Msk (0x01UL << SCT_EVFLAG_FLAG5_Pos) /*!< SCT EVFLAG: FLAG5 Mask */ -#define SCT_EVFLAG_FLAG6_Pos 6 /*!< SCT EVFLAG: FLAG6 Position */ -#define SCT_EVFLAG_FLAG6_Msk (0x01UL << SCT_EVFLAG_FLAG6_Pos) /*!< SCT EVFLAG: FLAG6 Mask */ -#define SCT_EVFLAG_FLAG7_Pos 7 /*!< SCT EVFLAG: FLAG7 Position */ -#define SCT_EVFLAG_FLAG7_Msk (0x01UL << SCT_EVFLAG_FLAG7_Pos) /*!< SCT EVFLAG: FLAG7 Mask */ -#define SCT_EVFLAG_FLAG8_Pos 8 /*!< SCT EVFLAG: FLAG8 Position */ -#define SCT_EVFLAG_FLAG8_Msk (0x01UL << SCT_EVFLAG_FLAG8_Pos) /*!< SCT EVFLAG: FLAG8 Mask */ -#define SCT_EVFLAG_FLAG9_Pos 9 /*!< SCT EVFLAG: FLAG9 Position */ -#define SCT_EVFLAG_FLAG9_Msk (0x01UL << SCT_EVFLAG_FLAG9_Pos) /*!< SCT EVFLAG: FLAG9 Mask */ -#define SCT_EVFLAG_FLAG10_Pos 10 /*!< SCT EVFLAG: FLAG10 Position */ -#define SCT_EVFLAG_FLAG10_Msk (0x01UL << SCT_EVFLAG_FLAG10_Pos) /*!< SCT EVFLAG: FLAG10 Mask */ -#define SCT_EVFLAG_FLAG11_Pos 11 /*!< SCT EVFLAG: FLAG11 Position */ -#define SCT_EVFLAG_FLAG11_Msk (0x01UL << SCT_EVFLAG_FLAG11_Pos) /*!< SCT EVFLAG: FLAG11 Mask */ -#define SCT_EVFLAG_FLAG12_Pos 12 /*!< SCT EVFLAG: FLAG12 Position */ -#define SCT_EVFLAG_FLAG12_Msk (0x01UL << SCT_EVFLAG_FLAG12_Pos) /*!< SCT EVFLAG: FLAG12 Mask */ -#define SCT_EVFLAG_FLAG13_Pos 13 /*!< SCT EVFLAG: FLAG13 Position */ -#define SCT_EVFLAG_FLAG13_Msk (0x01UL << SCT_EVFLAG_FLAG13_Pos) /*!< SCT EVFLAG: FLAG13 Mask */ -#define SCT_EVFLAG_FLAG14_Pos 14 /*!< SCT EVFLAG: FLAG14 Position */ -#define SCT_EVFLAG_FLAG14_Msk (0x01UL << SCT_EVFLAG_FLAG14_Pos) /*!< SCT EVFLAG: FLAG14 Mask */ -#define SCT_EVFLAG_FLAG15_Pos 15 /*!< SCT EVFLAG: FLAG15 Position */ -#define SCT_EVFLAG_FLAG15_Msk (0x01UL << SCT_EVFLAG_FLAG15_Pos) /*!< SCT EVFLAG: FLAG15 Mask */ - -// ---------------------------------------- SCT_CONEN ------------------------------------------- -#define SCT_CONEN_NCEN0_Pos 0 /*!< SCT CONEN: NCEN0 Position */ -#define SCT_CONEN_NCEN0_Msk (0x01UL << SCT_CONEN_NCEN0_Pos) /*!< SCT CONEN: NCEN0 Mask */ -#define SCT_CONEN_NCEN1_Pos 1 /*!< SCT CONEN: NCEN1 Position */ -#define SCT_CONEN_NCEN1_Msk (0x01UL << SCT_CONEN_NCEN1_Pos) /*!< SCT CONEN: NCEN1 Mask */ -#define SCT_CONEN_NCEN2_Pos 2 /*!< SCT CONEN: NCEN2 Position */ -#define SCT_CONEN_NCEN2_Msk (0x01UL << SCT_CONEN_NCEN2_Pos) /*!< SCT CONEN: NCEN2 Mask */ -#define SCT_CONEN_NCEN3_Pos 3 /*!< SCT CONEN: NCEN3 Position */ -#define SCT_CONEN_NCEN3_Msk (0x01UL << SCT_CONEN_NCEN3_Pos) /*!< SCT CONEN: NCEN3 Mask */ -#define SCT_CONEN_NCEN4_Pos 4 /*!< SCT CONEN: NCEN4 Position */ -#define SCT_CONEN_NCEN4_Msk (0x01UL << SCT_CONEN_NCEN4_Pos) /*!< SCT CONEN: NCEN4 Mask */ -#define SCT_CONEN_NCEN5_Pos 5 /*!< SCT CONEN: NCEN5 Position */ -#define SCT_CONEN_NCEN5_Msk (0x01UL << SCT_CONEN_NCEN5_Pos) /*!< SCT CONEN: NCEN5 Mask */ -#define SCT_CONEN_NCEN6_Pos 6 /*!< SCT CONEN: NCEN6 Position */ -#define SCT_CONEN_NCEN6_Msk (0x01UL << SCT_CONEN_NCEN6_Pos) /*!< SCT CONEN: NCEN6 Mask */ -#define SCT_CONEN_NCEN7_Pos 7 /*!< SCT CONEN: NCEN7 Position */ -#define SCT_CONEN_NCEN7_Msk (0x01UL << SCT_CONEN_NCEN7_Pos) /*!< SCT CONEN: NCEN7 Mask */ -#define SCT_CONEN_NCEN8_Pos 8 /*!< SCT CONEN: NCEN8 Position */ -#define SCT_CONEN_NCEN8_Msk (0x01UL << SCT_CONEN_NCEN8_Pos) /*!< SCT CONEN: NCEN8 Mask */ -#define SCT_CONEN_NCEN9_Pos 9 /*!< SCT CONEN: NCEN9 Position */ -#define SCT_CONEN_NCEN9_Msk (0x01UL << SCT_CONEN_NCEN9_Pos) /*!< SCT CONEN: NCEN9 Mask */ -#define SCT_CONEN_NCEN10_Pos 10 /*!< SCT CONEN: NCEN10 Position */ -#define SCT_CONEN_NCEN10_Msk (0x01UL << SCT_CONEN_NCEN10_Pos) /*!< SCT CONEN: NCEN10 Mask */ -#define SCT_CONEN_NCEN11_Pos 11 /*!< SCT CONEN: NCEN11 Position */ -#define SCT_CONEN_NCEN11_Msk (0x01UL << SCT_CONEN_NCEN11_Pos) /*!< SCT CONEN: NCEN11 Mask */ -#define SCT_CONEN_NCEN12_Pos 12 /*!< SCT CONEN: NCEN12 Position */ -#define SCT_CONEN_NCEN12_Msk (0x01UL << SCT_CONEN_NCEN12_Pos) /*!< SCT CONEN: NCEN12 Mask */ -#define SCT_CONEN_NCEN13_Pos 13 /*!< SCT CONEN: NCEN13 Position */ -#define SCT_CONEN_NCEN13_Msk (0x01UL << SCT_CONEN_NCEN13_Pos) /*!< SCT CONEN: NCEN13 Mask */ -#define SCT_CONEN_NCEN14_Pos 14 /*!< SCT CONEN: NCEN14 Position */ -#define SCT_CONEN_NCEN14_Msk (0x01UL << SCT_CONEN_NCEN14_Pos) /*!< SCT CONEN: NCEN14 Mask */ -#define SCT_CONEN_NCEN15_Pos 15 /*!< SCT CONEN: NCEN15 Position */ -#define SCT_CONEN_NCEN15_Msk (0x01UL << SCT_CONEN_NCEN15_Pos) /*!< SCT CONEN: NCEN15 Mask */ - -// --------------------------------------- SCT_CONFLAG ------------------------------------------ -#define SCT_CONFLAG_NCFLAG0_Pos 0 /*!< SCT CONFLAG: NCFLAG0 Position */ -#define SCT_CONFLAG_NCFLAG0_Msk (0x01UL << SCT_CONFLAG_NCFLAG0_Pos) /*!< SCT CONFLAG: NCFLAG0 Mask */ -#define SCT_CONFLAG_NCFLAG1_Pos 1 /*!< SCT CONFLAG: NCFLAG1 Position */ -#define SCT_CONFLAG_NCFLAG1_Msk (0x01UL << SCT_CONFLAG_NCFLAG1_Pos) /*!< SCT CONFLAG: NCFLAG1 Mask */ -#define SCT_CONFLAG_NCFLAG2_Pos 2 /*!< SCT CONFLAG: NCFLAG2 Position */ -#define SCT_CONFLAG_NCFLAG2_Msk (0x01UL << SCT_CONFLAG_NCFLAG2_Pos) /*!< SCT CONFLAG: NCFLAG2 Mask */ -#define SCT_CONFLAG_NCFLAG3_Pos 3 /*!< SCT CONFLAG: NCFLAG3 Position */ -#define SCT_CONFLAG_NCFLAG3_Msk (0x01UL << SCT_CONFLAG_NCFLAG3_Pos) /*!< SCT CONFLAG: NCFLAG3 Mask */ -#define SCT_CONFLAG_NCFLAG4_Pos 4 /*!< SCT CONFLAG: NCFLAG4 Position */ -#define SCT_CONFLAG_NCFLAG4_Msk (0x01UL << SCT_CONFLAG_NCFLAG4_Pos) /*!< SCT CONFLAG: NCFLAG4 Mask */ -#define SCT_CONFLAG_NCFLAG5_Pos 5 /*!< SCT CONFLAG: NCFLAG5 Position */ -#define SCT_CONFLAG_NCFLAG5_Msk (0x01UL << SCT_CONFLAG_NCFLAG5_Pos) /*!< SCT CONFLAG: NCFLAG5 Mask */ -#define SCT_CONFLAG_NCFLAG6_Pos 6 /*!< SCT CONFLAG: NCFLAG6 Position */ -#define SCT_CONFLAG_NCFLAG6_Msk (0x01UL << SCT_CONFLAG_NCFLAG6_Pos) /*!< SCT CONFLAG: NCFLAG6 Mask */ -#define SCT_CONFLAG_NCFLAG7_Pos 7 /*!< SCT CONFLAG: NCFLAG7 Position */ -#define SCT_CONFLAG_NCFLAG7_Msk (0x01UL << SCT_CONFLAG_NCFLAG7_Pos) /*!< SCT CONFLAG: NCFLAG7 Mask */ -#define SCT_CONFLAG_NCFLAG8_Pos 8 /*!< SCT CONFLAG: NCFLAG8 Position */ -#define SCT_CONFLAG_NCFLAG8_Msk (0x01UL << SCT_CONFLAG_NCFLAG8_Pos) /*!< SCT CONFLAG: NCFLAG8 Mask */ -#define SCT_CONFLAG_NCFLAG9_Pos 9 /*!< SCT CONFLAG: NCFLAG9 Position */ -#define SCT_CONFLAG_NCFLAG9_Msk (0x01UL << SCT_CONFLAG_NCFLAG9_Pos) /*!< SCT CONFLAG: NCFLAG9 Mask */ -#define SCT_CONFLAG_NCFLAG10_Pos 10 /*!< SCT CONFLAG: NCFLAG10 Position */ -#define SCT_CONFLAG_NCFLAG10_Msk (0x01UL << SCT_CONFLAG_NCFLAG10_Pos) /*!< SCT CONFLAG: NCFLAG10 Mask */ -#define SCT_CONFLAG_NCFLAG11_Pos 11 /*!< SCT CONFLAG: NCFLAG11 Position */ -#define SCT_CONFLAG_NCFLAG11_Msk (0x01UL << SCT_CONFLAG_NCFLAG11_Pos) /*!< SCT CONFLAG: NCFLAG11 Mask */ -#define SCT_CONFLAG_NCFLAG12_Pos 12 /*!< SCT CONFLAG: NCFLAG12 Position */ -#define SCT_CONFLAG_NCFLAG12_Msk (0x01UL << SCT_CONFLAG_NCFLAG12_Pos) /*!< SCT CONFLAG: NCFLAG12 Mask */ -#define SCT_CONFLAG_NCFLAG13_Pos 13 /*!< SCT CONFLAG: NCFLAG13 Position */ -#define SCT_CONFLAG_NCFLAG13_Msk (0x01UL << SCT_CONFLAG_NCFLAG13_Pos) /*!< SCT CONFLAG: NCFLAG13 Mask */ -#define SCT_CONFLAG_NCFLAG14_Pos 14 /*!< SCT CONFLAG: NCFLAG14 Position */ -#define SCT_CONFLAG_NCFLAG14_Msk (0x01UL << SCT_CONFLAG_NCFLAG14_Pos) /*!< SCT CONFLAG: NCFLAG14 Mask */ -#define SCT_CONFLAG_NCFLAG15_Pos 15 /*!< SCT CONFLAG: NCFLAG15 Position */ -#define SCT_CONFLAG_NCFLAG15_Msk (0x01UL << SCT_CONFLAG_NCFLAG15_Pos) /*!< SCT CONFLAG: NCFLAG15 Mask */ -#define SCT_CONFLAG_BUSERRL_Pos 30 /*!< SCT CONFLAG: BUSERRL Position */ -#define SCT_CONFLAG_BUSERRL_Msk (0x01UL << SCT_CONFLAG_BUSERRL_Pos) /*!< SCT CONFLAG: BUSERRL Mask */ -#define SCT_CONFLAG_BUSERRH_Pos 31 /*!< SCT CONFLAG: BUSERRH Position */ -#define SCT_CONFLAG_BUSERRH_Msk (0x01UL << SCT_CONFLAG_BUSERRH_Pos) /*!< SCT CONFLAG: BUSERRH Mask */ - -// --------------------------------------- SCT_MATCH0 ------------------------------------------- -#define SCT_MATCH0_MATCHn_L_Pos 0 /*!< SCT MATCH0: MATCHn_L Position */ -#define SCT_MATCH0_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos) /*!< SCT MATCH0: MATCHn_L Mask */ -#define SCT_MATCH0_MATCHn_H_Pos 16 /*!< SCT MATCH0: MATCHn_H Position */ -#define SCT_MATCH0_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos) /*!< SCT MATCH0: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP0 -------------------------------------------- -#define SCT_CAP0_CAPn_L_Pos 0 /*!< SCT CAP0: CAPn_L Position */ -#define SCT_CAP0_CAPn_L_Msk (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos) /*!< SCT CAP0: CAPn_L Mask */ -#define SCT_CAP0_CAPn_H_Pos 16 /*!< SCT CAP0: CAPn_H Position */ -#define SCT_CAP0_CAPn_H_Msk (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos) /*!< SCT CAP0: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH1 ------------------------------------------- -#define SCT_MATCH1_MATCHn_L_Pos 0 /*!< SCT MATCH1: MATCHn_L Position */ -#define SCT_MATCH1_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos) /*!< SCT MATCH1: MATCHn_L Mask */ -#define SCT_MATCH1_MATCHn_H_Pos 16 /*!< SCT MATCH1: MATCHn_H Position */ -#define SCT_MATCH1_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos) /*!< SCT MATCH1: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP1 -------------------------------------------- -#define SCT_CAP1_CAPn_L_Pos 0 /*!< SCT CAP1: CAPn_L Position */ -#define SCT_CAP1_CAPn_L_Msk (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos) /*!< SCT CAP1: CAPn_L Mask */ -#define SCT_CAP1_CAPn_H_Pos 16 /*!< SCT CAP1: CAPn_H Position */ -#define SCT_CAP1_CAPn_H_Msk (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos) /*!< SCT CAP1: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH2 ------------------------------------------- -#define SCT_MATCH2_MATCHn_L_Pos 0 /*!< SCT MATCH2: MATCHn_L Position */ -#define SCT_MATCH2_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos) /*!< SCT MATCH2: MATCHn_L Mask */ -#define SCT_MATCH2_MATCHn_H_Pos 16 /*!< SCT MATCH2: MATCHn_H Position */ -#define SCT_MATCH2_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos) /*!< SCT MATCH2: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP2 -------------------------------------------- -#define SCT_CAP2_CAPn_L_Pos 0 /*!< SCT CAP2: CAPn_L Position */ -#define SCT_CAP2_CAPn_L_Msk (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos) /*!< SCT CAP2: CAPn_L Mask */ -#define SCT_CAP2_CAPn_H_Pos 16 /*!< SCT CAP2: CAPn_H Position */ -#define SCT_CAP2_CAPn_H_Msk (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos) /*!< SCT CAP2: CAPn_H Mask */ - -// ---------------------------------------- SCT_CAP3 -------------------------------------------- -#define SCT_CAP3_CAPn_L_Pos 0 /*!< SCT CAP3: CAPn_L Position */ -#define SCT_CAP3_CAPn_L_Msk (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos) /*!< SCT CAP3: CAPn_L Mask */ -#define SCT_CAP3_CAPn_H_Pos 16 /*!< SCT CAP3: CAPn_H Position */ -#define SCT_CAP3_CAPn_H_Msk (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos) /*!< SCT CAP3: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH3 ------------------------------------------- -#define SCT_MATCH3_MATCHn_L_Pos 0 /*!< SCT MATCH3: MATCHn_L Position */ -#define SCT_MATCH3_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos) /*!< SCT MATCH3: MATCHn_L Mask */ -#define SCT_MATCH3_MATCHn_H_Pos 16 /*!< SCT MATCH3: MATCHn_H Position */ -#define SCT_MATCH3_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos) /*!< SCT MATCH3: MATCHn_H Mask */ - -// --------------------------------------- SCT_MATCH4 ------------------------------------------- -#define SCT_MATCH4_MATCHn_L_Pos 0 /*!< SCT MATCH4: MATCHn_L Position */ -#define SCT_MATCH4_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos) /*!< SCT MATCH4: MATCHn_L Mask */ -#define SCT_MATCH4_MATCHn_H_Pos 16 /*!< SCT MATCH4: MATCHn_H Position */ -#define SCT_MATCH4_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos) /*!< SCT MATCH4: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP4 -------------------------------------------- -#define SCT_CAP4_CAPn_L_Pos 0 /*!< SCT CAP4: CAPn_L Position */ -#define SCT_CAP4_CAPn_L_Msk (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos) /*!< SCT CAP4: CAPn_L Mask */ -#define SCT_CAP4_CAPn_H_Pos 16 /*!< SCT CAP4: CAPn_H Position */ -#define SCT_CAP4_CAPn_H_Msk (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos) /*!< SCT CAP4: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH5 ------------------------------------------- -#define SCT_MATCH5_MATCHn_L_Pos 0 /*!< SCT MATCH5: MATCHn_L Position */ -#define SCT_MATCH5_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos) /*!< SCT MATCH5: MATCHn_L Mask */ -#define SCT_MATCH5_MATCHn_H_Pos 16 /*!< SCT MATCH5: MATCHn_H Position */ -#define SCT_MATCH5_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos) /*!< SCT MATCH5: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP5 -------------------------------------------- -#define SCT_CAP5_CAPn_L_Pos 0 /*!< SCT CAP5: CAPn_L Position */ -#define SCT_CAP5_CAPn_L_Msk (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos) /*!< SCT CAP5: CAPn_L Mask */ -#define SCT_CAP5_CAPn_H_Pos 16 /*!< SCT CAP5: CAPn_H Position */ -#define SCT_CAP5_CAPn_H_Msk (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos) /*!< SCT CAP5: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH6 ------------------------------------------- -#define SCT_MATCH6_MATCHn_L_Pos 0 /*!< SCT MATCH6: MATCHn_L Position */ -#define SCT_MATCH6_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos) /*!< SCT MATCH6: MATCHn_L Mask */ -#define SCT_MATCH6_MATCHn_H_Pos 16 /*!< SCT MATCH6: MATCHn_H Position */ -#define SCT_MATCH6_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos) /*!< SCT MATCH6: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP6 -------------------------------------------- -#define SCT_CAP6_CAPn_L_Pos 0 /*!< SCT CAP6: CAPn_L Position */ -#define SCT_CAP6_CAPn_L_Msk (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos) /*!< SCT CAP6: CAPn_L Mask */ -#define SCT_CAP6_CAPn_H_Pos 16 /*!< SCT CAP6: CAPn_H Position */ -#define SCT_CAP6_CAPn_H_Msk (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos) /*!< SCT CAP6: CAPn_H Mask */ - -// ---------------------------------------- SCT_CAP7 -------------------------------------------- -#define SCT_CAP7_CAPn_L_Pos 0 /*!< SCT CAP7: CAPn_L Position */ -#define SCT_CAP7_CAPn_L_Msk (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos) /*!< SCT CAP7: CAPn_L Mask */ -#define SCT_CAP7_CAPn_H_Pos 16 /*!< SCT CAP7: CAPn_H Position */ -#define SCT_CAP7_CAPn_H_Msk (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos) /*!< SCT CAP7: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH7 ------------------------------------------- -#define SCT_MATCH7_MATCHn_L_Pos 0 /*!< SCT MATCH7: MATCHn_L Position */ -#define SCT_MATCH7_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos) /*!< SCT MATCH7: MATCHn_L Mask */ -#define SCT_MATCH7_MATCHn_H_Pos 16 /*!< SCT MATCH7: MATCHn_H Position */ -#define SCT_MATCH7_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos) /*!< SCT MATCH7: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP8 -------------------------------------------- -#define SCT_CAP8_CAPn_L_Pos 0 /*!< SCT CAP8: CAPn_L Position */ -#define SCT_CAP8_CAPn_L_Msk (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos) /*!< SCT CAP8: CAPn_L Mask */ -#define SCT_CAP8_CAPn_H_Pos 16 /*!< SCT CAP8: CAPn_H Position */ -#define SCT_CAP8_CAPn_H_Msk (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos) /*!< SCT CAP8: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH8 ------------------------------------------- -#define SCT_MATCH8_MATCHn_L_Pos 0 /*!< SCT MATCH8: MATCHn_L Position */ -#define SCT_MATCH8_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos) /*!< SCT MATCH8: MATCHn_L Mask */ -#define SCT_MATCH8_MATCHn_H_Pos 16 /*!< SCT MATCH8: MATCHn_H Position */ -#define SCT_MATCH8_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos) /*!< SCT MATCH8: MATCHn_H Mask */ - -// --------------------------------------- SCT_MATCH9 ------------------------------------------- -#define SCT_MATCH9_MATCHn_L_Pos 0 /*!< SCT MATCH9: MATCHn_L Position */ -#define SCT_MATCH9_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos) /*!< SCT MATCH9: MATCHn_L Mask */ -#define SCT_MATCH9_MATCHn_H_Pos 16 /*!< SCT MATCH9: MATCHn_H Position */ -#define SCT_MATCH9_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos) /*!< SCT MATCH9: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP9 -------------------------------------------- -#define SCT_CAP9_CAPn_L_Pos 0 /*!< SCT CAP9: CAPn_L Position */ -#define SCT_CAP9_CAPn_L_Msk (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos) /*!< SCT CAP9: CAPn_L Mask */ -#define SCT_CAP9_CAPn_H_Pos 16 /*!< SCT CAP9: CAPn_H Position */ -#define SCT_CAP9_CAPn_H_Msk (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos) /*!< SCT CAP9: CAPn_H Mask */ - -// ---------------------------------------- SCT_CAP10 ------------------------------------------- -#define SCT_CAP10_CAPn_L_Pos 0 /*!< SCT CAP10: CAPn_L Position */ -#define SCT_CAP10_CAPn_L_Msk (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos) /*!< SCT CAP10: CAPn_L Mask */ -#define SCT_CAP10_CAPn_H_Pos 16 /*!< SCT CAP10: CAPn_H Position */ -#define SCT_CAP10_CAPn_H_Msk (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos) /*!< SCT CAP10: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH10 ------------------------------------------ -#define SCT_MATCH10_MATCHn_L_Pos 0 /*!< SCT MATCH10: MATCHn_L Position */ -#define SCT_MATCH10_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos) /*!< SCT MATCH10: MATCHn_L Mask */ -#define SCT_MATCH10_MATCHn_H_Pos 16 /*!< SCT MATCH10: MATCHn_H Position */ -#define SCT_MATCH10_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos) /*!< SCT MATCH10: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP11 ------------------------------------------- -#define SCT_CAP11_CAPn_L_Pos 0 /*!< SCT CAP11: CAPn_L Position */ -#define SCT_CAP11_CAPn_L_Msk (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos) /*!< SCT CAP11: CAPn_L Mask */ -#define SCT_CAP11_CAPn_H_Pos 16 /*!< SCT CAP11: CAPn_H Position */ -#define SCT_CAP11_CAPn_H_Msk (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos) /*!< SCT CAP11: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH11 ------------------------------------------ -#define SCT_MATCH11_MATCHn_L_Pos 0 /*!< SCT MATCH11: MATCHn_L Position */ -#define SCT_MATCH11_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos) /*!< SCT MATCH11: MATCHn_L Mask */ -#define SCT_MATCH11_MATCHn_H_Pos 16 /*!< SCT MATCH11: MATCHn_H Position */ -#define SCT_MATCH11_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos) /*!< SCT MATCH11: MATCHn_H Mask */ - -// --------------------------------------- SCT_MATCH12 ------------------------------------------ -#define SCT_MATCH12_MATCHn_L_Pos 0 /*!< SCT MATCH12: MATCHn_L Position */ -#define SCT_MATCH12_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos) /*!< SCT MATCH12: MATCHn_L Mask */ -#define SCT_MATCH12_MATCHn_H_Pos 16 /*!< SCT MATCH12: MATCHn_H Position */ -#define SCT_MATCH12_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos) /*!< SCT MATCH12: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP12 ------------------------------------------- -#define SCT_CAP12_CAPn_L_Pos 0 /*!< SCT CAP12: CAPn_L Position */ -#define SCT_CAP12_CAPn_L_Msk (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos) /*!< SCT CAP12: CAPn_L Mask */ -#define SCT_CAP12_CAPn_H_Pos 16 /*!< SCT CAP12: CAPn_H Position */ -#define SCT_CAP12_CAPn_H_Msk (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos) /*!< SCT CAP12: CAPn_H Mask */ - -// ---------------------------------------- SCT_CAP13 ------------------------------------------- -#define SCT_CAP13_CAPn_L_Pos 0 /*!< SCT CAP13: CAPn_L Position */ -#define SCT_CAP13_CAPn_L_Msk (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos) /*!< SCT CAP13: CAPn_L Mask */ -#define SCT_CAP13_CAPn_H_Pos 16 /*!< SCT CAP13: CAPn_H Position */ -#define SCT_CAP13_CAPn_H_Msk (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos) /*!< SCT CAP13: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH13 ------------------------------------------ -#define SCT_MATCH13_MATCHn_L_Pos 0 /*!< SCT MATCH13: MATCHn_L Position */ -#define SCT_MATCH13_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos) /*!< SCT MATCH13: MATCHn_L Mask */ -#define SCT_MATCH13_MATCHn_H_Pos 16 /*!< SCT MATCH13: MATCHn_H Position */ -#define SCT_MATCH13_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos) /*!< SCT MATCH13: MATCHn_H Mask */ - -// --------------------------------------- SCT_MATCH14 ------------------------------------------ -#define SCT_MATCH14_MATCHn_L_Pos 0 /*!< SCT MATCH14: MATCHn_L Position */ -#define SCT_MATCH14_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos) /*!< SCT MATCH14: MATCHn_L Mask */ -#define SCT_MATCH14_MATCHn_H_Pos 16 /*!< SCT MATCH14: MATCHn_H Position */ -#define SCT_MATCH14_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos) /*!< SCT MATCH14: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP14 ------------------------------------------- -#define SCT_CAP14_CAPn_L_Pos 0 /*!< SCT CAP14: CAPn_L Position */ -#define SCT_CAP14_CAPn_L_Msk (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos) /*!< SCT CAP14: CAPn_L Mask */ -#define SCT_CAP14_CAPn_H_Pos 16 /*!< SCT CAP14: CAPn_H Position */ -#define SCT_CAP14_CAPn_H_Msk (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos) /*!< SCT CAP14: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH15 ------------------------------------------ -#define SCT_MATCH15_MATCHn_L_Pos 0 /*!< SCT MATCH15: MATCHn_L Position */ -#define SCT_MATCH15_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos) /*!< SCT MATCH15: MATCHn_L Mask */ -#define SCT_MATCH15_MATCHn_H_Pos 16 /*!< SCT MATCH15: MATCHn_H Position */ -#define SCT_MATCH15_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos) /*!< SCT MATCH15: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP15 ------------------------------------------- -#define SCT_CAP15_CAPn_L_Pos 0 /*!< SCT CAP15: CAPn_L Position */ -#define SCT_CAP15_CAPn_L_Msk (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos) /*!< SCT CAP15: CAPn_L Mask */ -#define SCT_CAP15_CAPn_H_Pos 16 /*!< SCT CAP15: CAPn_H Position */ -#define SCT_CAP15_CAPn_H_Msk (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos) /*!< SCT CAP15: CAPn_H Mask */ - -// -------------------------------------- SCT_MATCHREL0 ----------------------------------------- -#define SCT_MATCHREL0_RELOADn_L_Pos 0 /*!< SCT MATCHREL0: RELOADn_L Position */ -#define SCT_MATCHREL0_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos) /*!< SCT MATCHREL0: RELOADn_L Mask */ -#define SCT_MATCHREL0_RELOADn_H_Pos 16 /*!< SCT MATCHREL0: RELOADn_H Position */ -#define SCT_MATCHREL0_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos) /*!< SCT MATCHREL0: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL0 ------------------------------------------ -#define SCT_CAPCTRL0_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL0: CAPCONn_L0 Position */ -#define SCT_CAPCTRL0_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos) /*!< SCT CAPCTRL0: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL0: CAPCONn_L1 Position */ -#define SCT_CAPCTRL0_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos) /*!< SCT CAPCTRL0: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL0: CAPCONn_L2 Position */ -#define SCT_CAPCTRL0_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos) /*!< SCT CAPCTRL0: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL0: CAPCONn_L3 Position */ -#define SCT_CAPCTRL0_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos) /*!< SCT CAPCTRL0: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL0: CAPCONn_L4 Position */ -#define SCT_CAPCTRL0_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos) /*!< SCT CAPCTRL0: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL0: CAPCONn_L5 Position */ -#define SCT_CAPCTRL0_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos) /*!< SCT CAPCTRL0: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL0: CAPCONn_L6 Position */ -#define SCT_CAPCTRL0_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos) /*!< SCT CAPCTRL0: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL0: CAPCONn_L7 Position */ -#define SCT_CAPCTRL0_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos) /*!< SCT CAPCTRL0: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL0: CAPCONn_L8 Position */ -#define SCT_CAPCTRL0_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos) /*!< SCT CAPCTRL0: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL0: CAPCONn_L9 Position */ -#define SCT_CAPCTRL0_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos) /*!< SCT CAPCTRL0: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL0: CAPCONn_L10 Position */ -#define SCT_CAPCTRL0_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos) /*!< SCT CAPCTRL0: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL0: CAPCONn_L11 Position */ -#define SCT_CAPCTRL0_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos) /*!< SCT CAPCTRL0: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL0: CAPCONn_L12 Position */ -#define SCT_CAPCTRL0_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos) /*!< SCT CAPCTRL0: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL0: CAPCONn_L13 Position */ -#define SCT_CAPCTRL0_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos) /*!< SCT CAPCTRL0: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL0: CAPCONn_L14 Position */ -#define SCT_CAPCTRL0_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos) /*!< SCT CAPCTRL0: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL0: CAPCONn_L15 Position */ -#define SCT_CAPCTRL0_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos) /*!< SCT CAPCTRL0: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL0_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL0: CAPCONn_H Position */ -#define SCT_CAPCTRL0_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos) /*!< SCT CAPCTRL0: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL1 ----------------------------------------- -#define SCT_MATCHREL1_RELOADn_L_Pos 0 /*!< SCT MATCHREL1: RELOADn_L Position */ -#define SCT_MATCHREL1_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos) /*!< SCT MATCHREL1: RELOADn_L Mask */ -#define SCT_MATCHREL1_RELOADn_H_Pos 16 /*!< SCT MATCHREL1: RELOADn_H Position */ -#define SCT_MATCHREL1_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos) /*!< SCT MATCHREL1: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL1 ------------------------------------------ -#define SCT_CAPCTRL1_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL1: CAPCONn_L0 Position */ -#define SCT_CAPCTRL1_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos) /*!< SCT CAPCTRL1: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL1: CAPCONn_L1 Position */ -#define SCT_CAPCTRL1_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos) /*!< SCT CAPCTRL1: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL1: CAPCONn_L2 Position */ -#define SCT_CAPCTRL1_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos) /*!< SCT CAPCTRL1: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL1: CAPCONn_L3 Position */ -#define SCT_CAPCTRL1_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos) /*!< SCT CAPCTRL1: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL1: CAPCONn_L4 Position */ -#define SCT_CAPCTRL1_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos) /*!< SCT CAPCTRL1: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL1: CAPCONn_L5 Position */ -#define SCT_CAPCTRL1_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos) /*!< SCT CAPCTRL1: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL1: CAPCONn_L6 Position */ -#define SCT_CAPCTRL1_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos) /*!< SCT CAPCTRL1: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL1: CAPCONn_L7 Position */ -#define SCT_CAPCTRL1_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos) /*!< SCT CAPCTRL1: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL1: CAPCONn_L8 Position */ -#define SCT_CAPCTRL1_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos) /*!< SCT CAPCTRL1: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL1: CAPCONn_L9 Position */ -#define SCT_CAPCTRL1_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos) /*!< SCT CAPCTRL1: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL1: CAPCONn_L10 Position */ -#define SCT_CAPCTRL1_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos) /*!< SCT CAPCTRL1: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL1: CAPCONn_L11 Position */ -#define SCT_CAPCTRL1_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos) /*!< SCT CAPCTRL1: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL1: CAPCONn_L12 Position */ -#define SCT_CAPCTRL1_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos) /*!< SCT CAPCTRL1: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL1: CAPCONn_L13 Position */ -#define SCT_CAPCTRL1_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos) /*!< SCT CAPCTRL1: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL1: CAPCONn_L14 Position */ -#define SCT_CAPCTRL1_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos) /*!< SCT CAPCTRL1: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL1: CAPCONn_L15 Position */ -#define SCT_CAPCTRL1_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos) /*!< SCT CAPCTRL1: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL1_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL1: CAPCONn_H Position */ -#define SCT_CAPCTRL1_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos) /*!< SCT CAPCTRL1: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL2 ----------------------------------------- -#define SCT_MATCHREL2_RELOADn_L_Pos 0 /*!< SCT MATCHREL2: RELOADn_L Position */ -#define SCT_MATCHREL2_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos) /*!< SCT MATCHREL2: RELOADn_L Mask */ -#define SCT_MATCHREL2_RELOADn_H_Pos 16 /*!< SCT MATCHREL2: RELOADn_H Position */ -#define SCT_MATCHREL2_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos) /*!< SCT MATCHREL2: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL2 ------------------------------------------ -#define SCT_CAPCTRL2_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL2: CAPCONn_L0 Position */ -#define SCT_CAPCTRL2_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos) /*!< SCT CAPCTRL2: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL2: CAPCONn_L1 Position */ -#define SCT_CAPCTRL2_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos) /*!< SCT CAPCTRL2: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL2: CAPCONn_L2 Position */ -#define SCT_CAPCTRL2_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos) /*!< SCT CAPCTRL2: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL2: CAPCONn_L3 Position */ -#define SCT_CAPCTRL2_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos) /*!< SCT CAPCTRL2: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL2: CAPCONn_L4 Position */ -#define SCT_CAPCTRL2_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos) /*!< SCT CAPCTRL2: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL2: CAPCONn_L5 Position */ -#define SCT_CAPCTRL2_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos) /*!< SCT CAPCTRL2: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL2: CAPCONn_L6 Position */ -#define SCT_CAPCTRL2_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos) /*!< SCT CAPCTRL2: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL2: CAPCONn_L7 Position */ -#define SCT_CAPCTRL2_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos) /*!< SCT CAPCTRL2: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL2: CAPCONn_L8 Position */ -#define SCT_CAPCTRL2_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos) /*!< SCT CAPCTRL2: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL2: CAPCONn_L9 Position */ -#define SCT_CAPCTRL2_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos) /*!< SCT CAPCTRL2: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL2: CAPCONn_L10 Position */ -#define SCT_CAPCTRL2_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos) /*!< SCT CAPCTRL2: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL2: CAPCONn_L11 Position */ -#define SCT_CAPCTRL2_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos) /*!< SCT CAPCTRL2: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL2: CAPCONn_L12 Position */ -#define SCT_CAPCTRL2_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos) /*!< SCT CAPCTRL2: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL2: CAPCONn_L13 Position */ -#define SCT_CAPCTRL2_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos) /*!< SCT CAPCTRL2: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL2: CAPCONn_L14 Position */ -#define SCT_CAPCTRL2_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos) /*!< SCT CAPCTRL2: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL2: CAPCONn_L15 Position */ -#define SCT_CAPCTRL2_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos) /*!< SCT CAPCTRL2: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL2_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL2: CAPCONn_H Position */ -#define SCT_CAPCTRL2_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos) /*!< SCT CAPCTRL2: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL3 ----------------------------------------- -#define SCT_MATCHREL3_RELOADn_L_Pos 0 /*!< SCT MATCHREL3: RELOADn_L Position */ -#define SCT_MATCHREL3_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos) /*!< SCT MATCHREL3: RELOADn_L Mask */ -#define SCT_MATCHREL3_RELOADn_H_Pos 16 /*!< SCT MATCHREL3: RELOADn_H Position */ -#define SCT_MATCHREL3_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos) /*!< SCT MATCHREL3: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL3 ------------------------------------------ -#define SCT_CAPCTRL3_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL3: CAPCONn_L0 Position */ -#define SCT_CAPCTRL3_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos) /*!< SCT CAPCTRL3: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL3: CAPCONn_L1 Position */ -#define SCT_CAPCTRL3_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos) /*!< SCT CAPCTRL3: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL3: CAPCONn_L2 Position */ -#define SCT_CAPCTRL3_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos) /*!< SCT CAPCTRL3: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL3: CAPCONn_L3 Position */ -#define SCT_CAPCTRL3_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos) /*!< SCT CAPCTRL3: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL3: CAPCONn_L4 Position */ -#define SCT_CAPCTRL3_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos) /*!< SCT CAPCTRL3: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL3: CAPCONn_L5 Position */ -#define SCT_CAPCTRL3_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos) /*!< SCT CAPCTRL3: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL3: CAPCONn_L6 Position */ -#define SCT_CAPCTRL3_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos) /*!< SCT CAPCTRL3: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL3: CAPCONn_L7 Position */ -#define SCT_CAPCTRL3_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos) /*!< SCT CAPCTRL3: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL3: CAPCONn_L8 Position */ -#define SCT_CAPCTRL3_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos) /*!< SCT CAPCTRL3: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL3: CAPCONn_L9 Position */ -#define SCT_CAPCTRL3_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos) /*!< SCT CAPCTRL3: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL3: CAPCONn_L10 Position */ -#define SCT_CAPCTRL3_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos) /*!< SCT CAPCTRL3: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL3: CAPCONn_L11 Position */ -#define SCT_CAPCTRL3_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos) /*!< SCT CAPCTRL3: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL3: CAPCONn_L12 Position */ -#define SCT_CAPCTRL3_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos) /*!< SCT CAPCTRL3: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL3: CAPCONn_L13 Position */ -#define SCT_CAPCTRL3_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos) /*!< SCT CAPCTRL3: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL3: CAPCONn_L14 Position */ -#define SCT_CAPCTRL3_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos) /*!< SCT CAPCTRL3: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL3: CAPCONn_L15 Position */ -#define SCT_CAPCTRL3_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos) /*!< SCT CAPCTRL3: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL3_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL3: CAPCONn_H Position */ -#define SCT_CAPCTRL3_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos) /*!< SCT CAPCTRL3: CAPCONn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL4 ------------------------------------------ -#define SCT_CAPCTRL4_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL4: CAPCONn_L0 Position */ -#define SCT_CAPCTRL4_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos) /*!< SCT CAPCTRL4: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL4: CAPCONn_L1 Position */ -#define SCT_CAPCTRL4_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos) /*!< SCT CAPCTRL4: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL4: CAPCONn_L2 Position */ -#define SCT_CAPCTRL4_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos) /*!< SCT CAPCTRL4: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL4: CAPCONn_L3 Position */ -#define SCT_CAPCTRL4_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos) /*!< SCT CAPCTRL4: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL4: CAPCONn_L4 Position */ -#define SCT_CAPCTRL4_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos) /*!< SCT CAPCTRL4: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL4: CAPCONn_L5 Position */ -#define SCT_CAPCTRL4_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos) /*!< SCT CAPCTRL4: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL4: CAPCONn_L6 Position */ -#define SCT_CAPCTRL4_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos) /*!< SCT CAPCTRL4: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL4: CAPCONn_L7 Position */ -#define SCT_CAPCTRL4_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos) /*!< SCT CAPCTRL4: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL4: CAPCONn_L8 Position */ -#define SCT_CAPCTRL4_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos) /*!< SCT CAPCTRL4: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL4: CAPCONn_L9 Position */ -#define SCT_CAPCTRL4_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos) /*!< SCT CAPCTRL4: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL4: CAPCONn_L10 Position */ -#define SCT_CAPCTRL4_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos) /*!< SCT CAPCTRL4: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL4: CAPCONn_L11 Position */ -#define SCT_CAPCTRL4_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos) /*!< SCT CAPCTRL4: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL4: CAPCONn_L12 Position */ -#define SCT_CAPCTRL4_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos) /*!< SCT CAPCTRL4: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL4: CAPCONn_L13 Position */ -#define SCT_CAPCTRL4_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos) /*!< SCT CAPCTRL4: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL4: CAPCONn_L14 Position */ -#define SCT_CAPCTRL4_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos) /*!< SCT CAPCTRL4: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL4: CAPCONn_L15 Position */ -#define SCT_CAPCTRL4_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos) /*!< SCT CAPCTRL4: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL4_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL4: CAPCONn_H Position */ -#define SCT_CAPCTRL4_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos) /*!< SCT CAPCTRL4: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL4 ----------------------------------------- -#define SCT_MATCHREL4_RELOADn_L_Pos 0 /*!< SCT MATCHREL4: RELOADn_L Position */ -#define SCT_MATCHREL4_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos) /*!< SCT MATCHREL4: RELOADn_L Mask */ -#define SCT_MATCHREL4_RELOADn_H_Pos 16 /*!< SCT MATCHREL4: RELOADn_H Position */ -#define SCT_MATCHREL4_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos) /*!< SCT MATCHREL4: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL5 ------------------------------------------ -#define SCT_CAPCTRL5_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL5: CAPCONn_L0 Position */ -#define SCT_CAPCTRL5_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos) /*!< SCT CAPCTRL5: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL5: CAPCONn_L1 Position */ -#define SCT_CAPCTRL5_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos) /*!< SCT CAPCTRL5: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL5: CAPCONn_L2 Position */ -#define SCT_CAPCTRL5_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos) /*!< SCT CAPCTRL5: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL5: CAPCONn_L3 Position */ -#define SCT_CAPCTRL5_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos) /*!< SCT CAPCTRL5: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL5: CAPCONn_L4 Position */ -#define SCT_CAPCTRL5_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos) /*!< SCT CAPCTRL5: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL5: CAPCONn_L5 Position */ -#define SCT_CAPCTRL5_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos) /*!< SCT CAPCTRL5: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL5: CAPCONn_L6 Position */ -#define SCT_CAPCTRL5_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos) /*!< SCT CAPCTRL5: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL5: CAPCONn_L7 Position */ -#define SCT_CAPCTRL5_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos) /*!< SCT CAPCTRL5: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL5: CAPCONn_L8 Position */ -#define SCT_CAPCTRL5_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos) /*!< SCT CAPCTRL5: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL5: CAPCONn_L9 Position */ -#define SCT_CAPCTRL5_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos) /*!< SCT CAPCTRL5: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL5: CAPCONn_L10 Position */ -#define SCT_CAPCTRL5_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos) /*!< SCT CAPCTRL5: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL5: CAPCONn_L11 Position */ -#define SCT_CAPCTRL5_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos) /*!< SCT CAPCTRL5: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL5: CAPCONn_L12 Position */ -#define SCT_CAPCTRL5_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos) /*!< SCT CAPCTRL5: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL5: CAPCONn_L13 Position */ -#define SCT_CAPCTRL5_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos) /*!< SCT CAPCTRL5: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL5: CAPCONn_L14 Position */ -#define SCT_CAPCTRL5_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos) /*!< SCT CAPCTRL5: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL5: CAPCONn_L15 Position */ -#define SCT_CAPCTRL5_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos) /*!< SCT CAPCTRL5: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL5_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL5: CAPCONn_H Position */ -#define SCT_CAPCTRL5_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos) /*!< SCT CAPCTRL5: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL5 ----------------------------------------- -#define SCT_MATCHREL5_RELOADn_L_Pos 0 /*!< SCT MATCHREL5: RELOADn_L Position */ -#define SCT_MATCHREL5_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos) /*!< SCT MATCHREL5: RELOADn_L Mask */ -#define SCT_MATCHREL5_RELOADn_H_Pos 16 /*!< SCT MATCHREL5: RELOADn_H Position */ -#define SCT_MATCHREL5_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos) /*!< SCT MATCHREL5: RELOADn_H Mask */ - -// -------------------------------------- SCT_MATCHREL6 ----------------------------------------- -#define SCT_MATCHREL6_RELOADn_L_Pos 0 /*!< SCT MATCHREL6: RELOADn_L Position */ -#define SCT_MATCHREL6_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos) /*!< SCT MATCHREL6: RELOADn_L Mask */ -#define SCT_MATCHREL6_RELOADn_H_Pos 16 /*!< SCT MATCHREL6: RELOADn_H Position */ -#define SCT_MATCHREL6_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos) /*!< SCT MATCHREL6: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL6 ------------------------------------------ -#define SCT_CAPCTRL6_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL6: CAPCONn_L0 Position */ -#define SCT_CAPCTRL6_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos) /*!< SCT CAPCTRL6: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL6: CAPCONn_L1 Position */ -#define SCT_CAPCTRL6_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos) /*!< SCT CAPCTRL6: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL6: CAPCONn_L2 Position */ -#define SCT_CAPCTRL6_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos) /*!< SCT CAPCTRL6: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL6: CAPCONn_L3 Position */ -#define SCT_CAPCTRL6_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos) /*!< SCT CAPCTRL6: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL6: CAPCONn_L4 Position */ -#define SCT_CAPCTRL6_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos) /*!< SCT CAPCTRL6: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL6: CAPCONn_L5 Position */ -#define SCT_CAPCTRL6_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos) /*!< SCT CAPCTRL6: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL6: CAPCONn_L6 Position */ -#define SCT_CAPCTRL6_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos) /*!< SCT CAPCTRL6: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL6: CAPCONn_L7 Position */ -#define SCT_CAPCTRL6_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos) /*!< SCT CAPCTRL6: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL6: CAPCONn_L8 Position */ -#define SCT_CAPCTRL6_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos) /*!< SCT CAPCTRL6: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL6: CAPCONn_L9 Position */ -#define SCT_CAPCTRL6_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos) /*!< SCT CAPCTRL6: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL6: CAPCONn_L10 Position */ -#define SCT_CAPCTRL6_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos) /*!< SCT CAPCTRL6: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL6: CAPCONn_L11 Position */ -#define SCT_CAPCTRL6_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos) /*!< SCT CAPCTRL6: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL6: CAPCONn_L12 Position */ -#define SCT_CAPCTRL6_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos) /*!< SCT CAPCTRL6: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL6: CAPCONn_L13 Position */ -#define SCT_CAPCTRL6_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos) /*!< SCT CAPCTRL6: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL6: CAPCONn_L14 Position */ -#define SCT_CAPCTRL6_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos) /*!< SCT CAPCTRL6: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL6: CAPCONn_L15 Position */ -#define SCT_CAPCTRL6_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos) /*!< SCT CAPCTRL6: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL6_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL6: CAPCONn_H Position */ -#define SCT_CAPCTRL6_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos) /*!< SCT CAPCTRL6: CAPCONn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL7 ------------------------------------------ -#define SCT_CAPCTRL7_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL7: CAPCONn_L0 Position */ -#define SCT_CAPCTRL7_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos) /*!< SCT CAPCTRL7: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL7: CAPCONn_L1 Position */ -#define SCT_CAPCTRL7_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos) /*!< SCT CAPCTRL7: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL7: CAPCONn_L2 Position */ -#define SCT_CAPCTRL7_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos) /*!< SCT CAPCTRL7: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL7: CAPCONn_L3 Position */ -#define SCT_CAPCTRL7_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos) /*!< SCT CAPCTRL7: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL7: CAPCONn_L4 Position */ -#define SCT_CAPCTRL7_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos) /*!< SCT CAPCTRL7: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL7: CAPCONn_L5 Position */ -#define SCT_CAPCTRL7_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos) /*!< SCT CAPCTRL7: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL7: CAPCONn_L6 Position */ -#define SCT_CAPCTRL7_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos) /*!< SCT CAPCTRL7: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL7: CAPCONn_L7 Position */ -#define SCT_CAPCTRL7_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos) /*!< SCT CAPCTRL7: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL7: CAPCONn_L8 Position */ -#define SCT_CAPCTRL7_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos) /*!< SCT CAPCTRL7: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL7: CAPCONn_L9 Position */ -#define SCT_CAPCTRL7_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos) /*!< SCT CAPCTRL7: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL7: CAPCONn_L10 Position */ -#define SCT_CAPCTRL7_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos) /*!< SCT CAPCTRL7: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL7: CAPCONn_L11 Position */ -#define SCT_CAPCTRL7_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos) /*!< SCT CAPCTRL7: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL7: CAPCONn_L12 Position */ -#define SCT_CAPCTRL7_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos) /*!< SCT CAPCTRL7: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL7: CAPCONn_L13 Position */ -#define SCT_CAPCTRL7_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos) /*!< SCT CAPCTRL7: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL7: CAPCONn_L14 Position */ -#define SCT_CAPCTRL7_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos) /*!< SCT CAPCTRL7: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL7: CAPCONn_L15 Position */ -#define SCT_CAPCTRL7_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos) /*!< SCT CAPCTRL7: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL7_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL7: CAPCONn_H Position */ -#define SCT_CAPCTRL7_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos) /*!< SCT CAPCTRL7: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL7 ----------------------------------------- -#define SCT_MATCHREL7_RELOADn_L_Pos 0 /*!< SCT MATCHREL7: RELOADn_L Position */ -#define SCT_MATCHREL7_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos) /*!< SCT MATCHREL7: RELOADn_L Mask */ -#define SCT_MATCHREL7_RELOADn_H_Pos 16 /*!< SCT MATCHREL7: RELOADn_H Position */ -#define SCT_MATCHREL7_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos) /*!< SCT MATCHREL7: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL8 ------------------------------------------ -#define SCT_CAPCTRL8_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL8: CAPCONn_L0 Position */ -#define SCT_CAPCTRL8_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos) /*!< SCT CAPCTRL8: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL8: CAPCONn_L1 Position */ -#define SCT_CAPCTRL8_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos) /*!< SCT CAPCTRL8: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL8: CAPCONn_L2 Position */ -#define SCT_CAPCTRL8_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos) /*!< SCT CAPCTRL8: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL8: CAPCONn_L3 Position */ -#define SCT_CAPCTRL8_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos) /*!< SCT CAPCTRL8: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL8: CAPCONn_L4 Position */ -#define SCT_CAPCTRL8_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos) /*!< SCT CAPCTRL8: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL8: CAPCONn_L5 Position */ -#define SCT_CAPCTRL8_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos) /*!< SCT CAPCTRL8: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL8: CAPCONn_L6 Position */ -#define SCT_CAPCTRL8_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos) /*!< SCT CAPCTRL8: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL8: CAPCONn_L7 Position */ -#define SCT_CAPCTRL8_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos) /*!< SCT CAPCTRL8: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL8: CAPCONn_L8 Position */ -#define SCT_CAPCTRL8_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos) /*!< SCT CAPCTRL8: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL8: CAPCONn_L9 Position */ -#define SCT_CAPCTRL8_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos) /*!< SCT CAPCTRL8: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL8: CAPCONn_L10 Position */ -#define SCT_CAPCTRL8_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos) /*!< SCT CAPCTRL8: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL8: CAPCONn_L11 Position */ -#define SCT_CAPCTRL8_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos) /*!< SCT CAPCTRL8: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL8: CAPCONn_L12 Position */ -#define SCT_CAPCTRL8_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos) /*!< SCT CAPCTRL8: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL8: CAPCONn_L13 Position */ -#define SCT_CAPCTRL8_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos) /*!< SCT CAPCTRL8: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL8: CAPCONn_L14 Position */ -#define SCT_CAPCTRL8_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos) /*!< SCT CAPCTRL8: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL8: CAPCONn_L15 Position */ -#define SCT_CAPCTRL8_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos) /*!< SCT CAPCTRL8: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL8_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL8: CAPCONn_H Position */ -#define SCT_CAPCTRL8_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos) /*!< SCT CAPCTRL8: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL8 ----------------------------------------- -#define SCT_MATCHREL8_RELOADn_L_Pos 0 /*!< SCT MATCHREL8: RELOADn_L Position */ -#define SCT_MATCHREL8_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos) /*!< SCT MATCHREL8: RELOADn_L Mask */ -#define SCT_MATCHREL8_RELOADn_H_Pos 16 /*!< SCT MATCHREL8: RELOADn_H Position */ -#define SCT_MATCHREL8_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos) /*!< SCT MATCHREL8: RELOADn_H Mask */ - -// -------------------------------------- SCT_MATCHREL9 ----------------------------------------- -#define SCT_MATCHREL9_RELOADn_L_Pos 0 /*!< SCT MATCHREL9: RELOADn_L Position */ -#define SCT_MATCHREL9_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos) /*!< SCT MATCHREL9: RELOADn_L Mask */ -#define SCT_MATCHREL9_RELOADn_H_Pos 16 /*!< SCT MATCHREL9: RELOADn_H Position */ -#define SCT_MATCHREL9_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos) /*!< SCT MATCHREL9: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL9 ------------------------------------------ -#define SCT_CAPCTRL9_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL9: CAPCONn_L0 Position */ -#define SCT_CAPCTRL9_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos) /*!< SCT CAPCTRL9: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL9: CAPCONn_L1 Position */ -#define SCT_CAPCTRL9_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos) /*!< SCT CAPCTRL9: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL9: CAPCONn_L2 Position */ -#define SCT_CAPCTRL9_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos) /*!< SCT CAPCTRL9: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL9: CAPCONn_L3 Position */ -#define SCT_CAPCTRL9_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos) /*!< SCT CAPCTRL9: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL9: CAPCONn_L4 Position */ -#define SCT_CAPCTRL9_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos) /*!< SCT CAPCTRL9: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL9: CAPCONn_L5 Position */ -#define SCT_CAPCTRL9_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos) /*!< SCT CAPCTRL9: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL9: CAPCONn_L6 Position */ -#define SCT_CAPCTRL9_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos) /*!< SCT CAPCTRL9: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL9: CAPCONn_L7 Position */ -#define SCT_CAPCTRL9_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos) /*!< SCT CAPCTRL9: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL9: CAPCONn_L8 Position */ -#define SCT_CAPCTRL9_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos) /*!< SCT CAPCTRL9: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL9: CAPCONn_L9 Position */ -#define SCT_CAPCTRL9_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos) /*!< SCT CAPCTRL9: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL9: CAPCONn_L10 Position */ -#define SCT_CAPCTRL9_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos) /*!< SCT CAPCTRL9: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL9: CAPCONn_L11 Position */ -#define SCT_CAPCTRL9_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos) /*!< SCT CAPCTRL9: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL9: CAPCONn_L12 Position */ -#define SCT_CAPCTRL9_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos) /*!< SCT CAPCTRL9: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL9: CAPCONn_L13 Position */ -#define SCT_CAPCTRL9_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos) /*!< SCT CAPCTRL9: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL9: CAPCONn_L14 Position */ -#define SCT_CAPCTRL9_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos) /*!< SCT CAPCTRL9: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL9: CAPCONn_L15 Position */ -#define SCT_CAPCTRL9_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos) /*!< SCT CAPCTRL9: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL9_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL9: CAPCONn_H Position */ -#define SCT_CAPCTRL9_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos) /*!< SCT CAPCTRL9: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL10 ----------------------------------------- -#define SCT_MATCHREL10_RELOADn_L_Pos 0 /*!< SCT MATCHREL10: RELOADn_L Position */ -#define SCT_MATCHREL10_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos) /*!< SCT MATCHREL10: RELOADn_L Mask */ -#define SCT_MATCHREL10_RELOADn_H_Pos 16 /*!< SCT MATCHREL10: RELOADn_H Position */ -#define SCT_MATCHREL10_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos) /*!< SCT MATCHREL10: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL10 ----------------------------------------- -#define SCT_CAPCTRL10_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL10: CAPCONn_L0 Position */ -#define SCT_CAPCTRL10_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos) /*!< SCT CAPCTRL10: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL10: CAPCONn_L1 Position */ -#define SCT_CAPCTRL10_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos) /*!< SCT CAPCTRL10: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL10: CAPCONn_L2 Position */ -#define SCT_CAPCTRL10_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos) /*!< SCT CAPCTRL10: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL10: CAPCONn_L3 Position */ -#define SCT_CAPCTRL10_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos) /*!< SCT CAPCTRL10: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL10: CAPCONn_L4 Position */ -#define SCT_CAPCTRL10_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos) /*!< SCT CAPCTRL10: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL10: CAPCONn_L5 Position */ -#define SCT_CAPCTRL10_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos) /*!< SCT CAPCTRL10: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL10: CAPCONn_L6 Position */ -#define SCT_CAPCTRL10_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos) /*!< SCT CAPCTRL10: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL10: CAPCONn_L7 Position */ -#define SCT_CAPCTRL10_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos) /*!< SCT CAPCTRL10: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL10: CAPCONn_L8 Position */ -#define SCT_CAPCTRL10_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos) /*!< SCT CAPCTRL10: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL10: CAPCONn_L9 Position */ -#define SCT_CAPCTRL10_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos) /*!< SCT CAPCTRL10: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL10: CAPCONn_L10 Position */ -#define SCT_CAPCTRL10_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos) /*!< SCT CAPCTRL10: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL10: CAPCONn_L11 Position */ -#define SCT_CAPCTRL10_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos) /*!< SCT CAPCTRL10: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL10: CAPCONn_L12 Position */ -#define SCT_CAPCTRL10_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos) /*!< SCT CAPCTRL10: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL10: CAPCONn_L13 Position */ -#define SCT_CAPCTRL10_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos) /*!< SCT CAPCTRL10: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL10: CAPCONn_L14 Position */ -#define SCT_CAPCTRL10_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos) /*!< SCT CAPCTRL10: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL10: CAPCONn_L15 Position */ -#define SCT_CAPCTRL10_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos) /*!< SCT CAPCTRL10: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL10_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL10: CAPCONn_H Position */ -#define SCT_CAPCTRL10_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos) /*!< SCT CAPCTRL10: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL11 ----------------------------------------- -#define SCT_MATCHREL11_RELOADn_L_Pos 0 /*!< SCT MATCHREL11: RELOADn_L Position */ -#define SCT_MATCHREL11_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos) /*!< SCT MATCHREL11: RELOADn_L Mask */ -#define SCT_MATCHREL11_RELOADn_H_Pos 16 /*!< SCT MATCHREL11: RELOADn_H Position */ -#define SCT_MATCHREL11_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos) /*!< SCT MATCHREL11: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL11 ----------------------------------------- -#define SCT_CAPCTRL11_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL11: CAPCONn_L0 Position */ -#define SCT_CAPCTRL11_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos) /*!< SCT CAPCTRL11: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL11: CAPCONn_L1 Position */ -#define SCT_CAPCTRL11_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos) /*!< SCT CAPCTRL11: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL11: CAPCONn_L2 Position */ -#define SCT_CAPCTRL11_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos) /*!< SCT CAPCTRL11: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL11: CAPCONn_L3 Position */ -#define SCT_CAPCTRL11_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos) /*!< SCT CAPCTRL11: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL11: CAPCONn_L4 Position */ -#define SCT_CAPCTRL11_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos) /*!< SCT CAPCTRL11: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL11: CAPCONn_L5 Position */ -#define SCT_CAPCTRL11_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos) /*!< SCT CAPCTRL11: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL11: CAPCONn_L6 Position */ -#define SCT_CAPCTRL11_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos) /*!< SCT CAPCTRL11: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL11: CAPCONn_L7 Position */ -#define SCT_CAPCTRL11_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos) /*!< SCT CAPCTRL11: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL11: CAPCONn_L8 Position */ -#define SCT_CAPCTRL11_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos) /*!< SCT CAPCTRL11: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL11: CAPCONn_L9 Position */ -#define SCT_CAPCTRL11_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos) /*!< SCT CAPCTRL11: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL11: CAPCONn_L10 Position */ -#define SCT_CAPCTRL11_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos) /*!< SCT CAPCTRL11: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL11: CAPCONn_L11 Position */ -#define SCT_CAPCTRL11_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos) /*!< SCT CAPCTRL11: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL11: CAPCONn_L12 Position */ -#define SCT_CAPCTRL11_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos) /*!< SCT CAPCTRL11: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL11: CAPCONn_L13 Position */ -#define SCT_CAPCTRL11_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos) /*!< SCT CAPCTRL11: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL11: CAPCONn_L14 Position */ -#define SCT_CAPCTRL11_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos) /*!< SCT CAPCTRL11: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL11: CAPCONn_L15 Position */ -#define SCT_CAPCTRL11_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos) /*!< SCT CAPCTRL11: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL11_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL11: CAPCONn_H Position */ -#define SCT_CAPCTRL11_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos) /*!< SCT CAPCTRL11: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL12 ----------------------------------------- -#define SCT_MATCHREL12_RELOADn_L_Pos 0 /*!< SCT MATCHREL12: RELOADn_L Position */ -#define SCT_MATCHREL12_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos) /*!< SCT MATCHREL12: RELOADn_L Mask */ -#define SCT_MATCHREL12_RELOADn_H_Pos 16 /*!< SCT MATCHREL12: RELOADn_H Position */ -#define SCT_MATCHREL12_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos) /*!< SCT MATCHREL12: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL12 ----------------------------------------- -#define SCT_CAPCTRL12_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL12: CAPCONn_L0 Position */ -#define SCT_CAPCTRL12_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos) /*!< SCT CAPCTRL12: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL12: CAPCONn_L1 Position */ -#define SCT_CAPCTRL12_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos) /*!< SCT CAPCTRL12: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL12: CAPCONn_L2 Position */ -#define SCT_CAPCTRL12_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos) /*!< SCT CAPCTRL12: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL12: CAPCONn_L3 Position */ -#define SCT_CAPCTRL12_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos) /*!< SCT CAPCTRL12: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL12: CAPCONn_L4 Position */ -#define SCT_CAPCTRL12_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos) /*!< SCT CAPCTRL12: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL12: CAPCONn_L5 Position */ -#define SCT_CAPCTRL12_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos) /*!< SCT CAPCTRL12: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL12: CAPCONn_L6 Position */ -#define SCT_CAPCTRL12_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos) /*!< SCT CAPCTRL12: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL12: CAPCONn_L7 Position */ -#define SCT_CAPCTRL12_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos) /*!< SCT CAPCTRL12: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL12: CAPCONn_L8 Position */ -#define SCT_CAPCTRL12_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos) /*!< SCT CAPCTRL12: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL12: CAPCONn_L9 Position */ -#define SCT_CAPCTRL12_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos) /*!< SCT CAPCTRL12: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL12: CAPCONn_L10 Position */ -#define SCT_CAPCTRL12_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos) /*!< SCT CAPCTRL12: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL12: CAPCONn_L11 Position */ -#define SCT_CAPCTRL12_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos) /*!< SCT CAPCTRL12: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL12: CAPCONn_L12 Position */ -#define SCT_CAPCTRL12_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos) /*!< SCT CAPCTRL12: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL12: CAPCONn_L13 Position */ -#define SCT_CAPCTRL12_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos) /*!< SCT CAPCTRL12: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL12: CAPCONn_L14 Position */ -#define SCT_CAPCTRL12_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos) /*!< SCT CAPCTRL12: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL12: CAPCONn_L15 Position */ -#define SCT_CAPCTRL12_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos) /*!< SCT CAPCTRL12: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL12_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL12: CAPCONn_H Position */ -#define SCT_CAPCTRL12_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos) /*!< SCT CAPCTRL12: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL13 ----------------------------------------- -#define SCT_MATCHREL13_RELOADn_L_Pos 0 /*!< SCT MATCHREL13: RELOADn_L Position */ -#define SCT_MATCHREL13_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos) /*!< SCT MATCHREL13: RELOADn_L Mask */ -#define SCT_MATCHREL13_RELOADn_H_Pos 16 /*!< SCT MATCHREL13: RELOADn_H Position */ -#define SCT_MATCHREL13_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos) /*!< SCT MATCHREL13: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL13 ----------------------------------------- -#define SCT_CAPCTRL13_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL13: CAPCONn_L0 Position */ -#define SCT_CAPCTRL13_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos) /*!< SCT CAPCTRL13: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL13: CAPCONn_L1 Position */ -#define SCT_CAPCTRL13_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos) /*!< SCT CAPCTRL13: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL13: CAPCONn_L2 Position */ -#define SCT_CAPCTRL13_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos) /*!< SCT CAPCTRL13: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL13: CAPCONn_L3 Position */ -#define SCT_CAPCTRL13_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos) /*!< SCT CAPCTRL13: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL13: CAPCONn_L4 Position */ -#define SCT_CAPCTRL13_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos) /*!< SCT CAPCTRL13: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL13: CAPCONn_L5 Position */ -#define SCT_CAPCTRL13_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos) /*!< SCT CAPCTRL13: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL13: CAPCONn_L6 Position */ -#define SCT_CAPCTRL13_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos) /*!< SCT CAPCTRL13: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL13: CAPCONn_L7 Position */ -#define SCT_CAPCTRL13_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos) /*!< SCT CAPCTRL13: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL13: CAPCONn_L8 Position */ -#define SCT_CAPCTRL13_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos) /*!< SCT CAPCTRL13: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL13: CAPCONn_L9 Position */ -#define SCT_CAPCTRL13_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos) /*!< SCT CAPCTRL13: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL13: CAPCONn_L10 Position */ -#define SCT_CAPCTRL13_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos) /*!< SCT CAPCTRL13: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL13: CAPCONn_L11 Position */ -#define SCT_CAPCTRL13_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos) /*!< SCT CAPCTRL13: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL13: CAPCONn_L12 Position */ -#define SCT_CAPCTRL13_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos) /*!< SCT CAPCTRL13: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL13: CAPCONn_L13 Position */ -#define SCT_CAPCTRL13_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos) /*!< SCT CAPCTRL13: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL13: CAPCONn_L14 Position */ -#define SCT_CAPCTRL13_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos) /*!< SCT CAPCTRL13: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL13: CAPCONn_L15 Position */ -#define SCT_CAPCTRL13_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos) /*!< SCT CAPCTRL13: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL13_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL13: CAPCONn_H Position */ -#define SCT_CAPCTRL13_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos) /*!< SCT CAPCTRL13: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL14 ----------------------------------------- -#define SCT_MATCHREL14_RELOADn_L_Pos 0 /*!< SCT MATCHREL14: RELOADn_L Position */ -#define SCT_MATCHREL14_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos) /*!< SCT MATCHREL14: RELOADn_L Mask */ -#define SCT_MATCHREL14_RELOADn_H_Pos 16 /*!< SCT MATCHREL14: RELOADn_H Position */ -#define SCT_MATCHREL14_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos) /*!< SCT MATCHREL14: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL14 ----------------------------------------- -#define SCT_CAPCTRL14_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL14: CAPCONn_L0 Position */ -#define SCT_CAPCTRL14_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos) /*!< SCT CAPCTRL14: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL14: CAPCONn_L1 Position */ -#define SCT_CAPCTRL14_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos) /*!< SCT CAPCTRL14: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL14: CAPCONn_L2 Position */ -#define SCT_CAPCTRL14_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos) /*!< SCT CAPCTRL14: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL14: CAPCONn_L3 Position */ -#define SCT_CAPCTRL14_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos) /*!< SCT CAPCTRL14: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL14: CAPCONn_L4 Position */ -#define SCT_CAPCTRL14_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos) /*!< SCT CAPCTRL14: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL14: CAPCONn_L5 Position */ -#define SCT_CAPCTRL14_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos) /*!< SCT CAPCTRL14: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL14: CAPCONn_L6 Position */ -#define SCT_CAPCTRL14_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos) /*!< SCT CAPCTRL14: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL14: CAPCONn_L7 Position */ -#define SCT_CAPCTRL14_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos) /*!< SCT CAPCTRL14: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL14: CAPCONn_L8 Position */ -#define SCT_CAPCTRL14_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos) /*!< SCT CAPCTRL14: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL14: CAPCONn_L9 Position */ -#define SCT_CAPCTRL14_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos) /*!< SCT CAPCTRL14: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL14: CAPCONn_L10 Position */ -#define SCT_CAPCTRL14_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos) /*!< SCT CAPCTRL14: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL14: CAPCONn_L11 Position */ -#define SCT_CAPCTRL14_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos) /*!< SCT CAPCTRL14: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL14: CAPCONn_L12 Position */ -#define SCT_CAPCTRL14_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos) /*!< SCT CAPCTRL14: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL14: CAPCONn_L13 Position */ -#define SCT_CAPCTRL14_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos) /*!< SCT CAPCTRL14: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL14: CAPCONn_L14 Position */ -#define SCT_CAPCTRL14_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos) /*!< SCT CAPCTRL14: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL14: CAPCONn_L15 Position */ -#define SCT_CAPCTRL14_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos) /*!< SCT CAPCTRL14: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL14_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL14: CAPCONn_H Position */ -#define SCT_CAPCTRL14_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos) /*!< SCT CAPCTRL14: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL15 ----------------------------------------- -#define SCT_MATCHREL15_RELOADn_L_Pos 0 /*!< SCT MATCHREL15: RELOADn_L Position */ -#define SCT_MATCHREL15_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos) /*!< SCT MATCHREL15: RELOADn_L Mask */ -#define SCT_MATCHREL15_RELOADn_H_Pos 16 /*!< SCT MATCHREL15: RELOADn_H Position */ -#define SCT_MATCHREL15_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos) /*!< SCT MATCHREL15: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL15 ----------------------------------------- -#define SCT_CAPCTRL15_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL15: CAPCONn_L0 Position */ -#define SCT_CAPCTRL15_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos) /*!< SCT CAPCTRL15: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL15: CAPCONn_L1 Position */ -#define SCT_CAPCTRL15_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos) /*!< SCT CAPCTRL15: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL15: CAPCONn_L2 Position */ -#define SCT_CAPCTRL15_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos) /*!< SCT CAPCTRL15: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL15: CAPCONn_L3 Position */ -#define SCT_CAPCTRL15_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos) /*!< SCT CAPCTRL15: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL15: CAPCONn_L4 Position */ -#define SCT_CAPCTRL15_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos) /*!< SCT CAPCTRL15: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL15: CAPCONn_L5 Position */ -#define SCT_CAPCTRL15_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos) /*!< SCT CAPCTRL15: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL15: CAPCONn_L6 Position */ -#define SCT_CAPCTRL15_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos) /*!< SCT CAPCTRL15: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL15: CAPCONn_L7 Position */ -#define SCT_CAPCTRL15_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos) /*!< SCT CAPCTRL15: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL15: CAPCONn_L8 Position */ -#define SCT_CAPCTRL15_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos) /*!< SCT CAPCTRL15: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL15: CAPCONn_L9 Position */ -#define SCT_CAPCTRL15_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos) /*!< SCT CAPCTRL15: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL15: CAPCONn_L10 Position */ -#define SCT_CAPCTRL15_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos) /*!< SCT CAPCTRL15: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL15: CAPCONn_L11 Position */ -#define SCT_CAPCTRL15_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos) /*!< SCT CAPCTRL15: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL15: CAPCONn_L12 Position */ -#define SCT_CAPCTRL15_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos) /*!< SCT CAPCTRL15: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL15: CAPCONn_L13 Position */ -#define SCT_CAPCTRL15_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos) /*!< SCT CAPCTRL15: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL15: CAPCONn_L14 Position */ -#define SCT_CAPCTRL15_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos) /*!< SCT CAPCTRL15: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL15: CAPCONn_L15 Position */ -#define SCT_CAPCTRL15_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos) /*!< SCT CAPCTRL15: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL15_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL15: CAPCONn_H Position */ -#define SCT_CAPCTRL15_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos) /*!< SCT CAPCTRL15: CAPCONn_H Mask */ - -// ------------------------------------- SCT_EVSTATEMSK0 ---------------------------------------- -#define SCT_EVSTATEMSK0_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL0 ------------------------------------------ -#define SCT_EVCTRL0_MATCHSEL_Pos 0 /*!< SCT EVCTRL0: MATCHSEL Position */ -#define SCT_EVCTRL0_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos) /*!< SCT EVCTRL0: MATCHSEL Mask */ -#define SCT_EVCTRL0_HEVENT_Pos 4 /*!< SCT EVCTRL0: HEVENT Position */ -#define SCT_EVCTRL0_HEVENT_Msk (0x01UL << SCT_EVCTRL0_HEVENT_Pos) /*!< SCT EVCTRL0: HEVENT Mask */ -#define SCT_EVCTRL0_OUTSEL_Pos 5 /*!< SCT EVCTRL0: OUTSEL Position */ -#define SCT_EVCTRL0_OUTSEL_Msk (0x01UL << SCT_EVCTRL0_OUTSEL_Pos) /*!< SCT EVCTRL0: OUTSEL Mask */ -#define SCT_EVCTRL0_IOSEL_Pos 6 /*!< SCT EVCTRL0: IOSEL Position */ -#define SCT_EVCTRL0_IOSEL_Msk (0x0fUL << SCT_EVCTRL0_IOSEL_Pos) /*!< SCT EVCTRL0: IOSEL Mask */ -#define SCT_EVCTRL0_IOCOND_Pos 10 /*!< SCT EVCTRL0: IOCOND Position */ -#define SCT_EVCTRL0_IOCOND_Msk (0x03UL << SCT_EVCTRL0_IOCOND_Pos) /*!< SCT EVCTRL0: IOCOND Mask */ -#define SCT_EVCTRL0_COMBMODE_Pos 12 /*!< SCT EVCTRL0: COMBMODE Position */ -#define SCT_EVCTRL0_COMBMODE_Msk (0x03UL << SCT_EVCTRL0_COMBMODE_Pos) /*!< SCT EVCTRL0: COMBMODE Mask */ -#define SCT_EVCTRL0_STATELD_Pos 14 /*!< SCT EVCTRL0: STATELD Position */ -#define SCT_EVCTRL0_STATELD_Msk (0x01UL << SCT_EVCTRL0_STATELD_Pos) /*!< SCT EVCTRL0: STATELD Mask */ -#define SCT_EVCTRL0_STATEV_Pos 15 /*!< SCT EVCTRL0: STATEV Position */ -#define SCT_EVCTRL0_STATEV_Msk (0x1fUL << SCT_EVCTRL0_STATEV_Pos) /*!< SCT EVCTRL0: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK1 ---------------------------------------- -#define SCT_EVSTATEMSK1_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL1 ------------------------------------------ -#define SCT_EVCTRL1_MATCHSEL_Pos 0 /*!< SCT EVCTRL1: MATCHSEL Position */ -#define SCT_EVCTRL1_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos) /*!< SCT EVCTRL1: MATCHSEL Mask */ -#define SCT_EVCTRL1_HEVENT_Pos 4 /*!< SCT EVCTRL1: HEVENT Position */ -#define SCT_EVCTRL1_HEVENT_Msk (0x01UL << SCT_EVCTRL1_HEVENT_Pos) /*!< SCT EVCTRL1: HEVENT Mask */ -#define SCT_EVCTRL1_OUTSEL_Pos 5 /*!< SCT EVCTRL1: OUTSEL Position */ -#define SCT_EVCTRL1_OUTSEL_Msk (0x01UL << SCT_EVCTRL1_OUTSEL_Pos) /*!< SCT EVCTRL1: OUTSEL Mask */ -#define SCT_EVCTRL1_IOSEL_Pos 6 /*!< SCT EVCTRL1: IOSEL Position */ -#define SCT_EVCTRL1_IOSEL_Msk (0x0fUL << SCT_EVCTRL1_IOSEL_Pos) /*!< SCT EVCTRL1: IOSEL Mask */ -#define SCT_EVCTRL1_IOCOND_Pos 10 /*!< SCT EVCTRL1: IOCOND Position */ -#define SCT_EVCTRL1_IOCOND_Msk (0x03UL << SCT_EVCTRL1_IOCOND_Pos) /*!< SCT EVCTRL1: IOCOND Mask */ -#define SCT_EVCTRL1_COMBMODE_Pos 12 /*!< SCT EVCTRL1: COMBMODE Position */ -#define SCT_EVCTRL1_COMBMODE_Msk (0x03UL << SCT_EVCTRL1_COMBMODE_Pos) /*!< SCT EVCTRL1: COMBMODE Mask */ -#define SCT_EVCTRL1_STATELD_Pos 14 /*!< SCT EVCTRL1: STATELD Position */ -#define SCT_EVCTRL1_STATELD_Msk (0x01UL << SCT_EVCTRL1_STATELD_Pos) /*!< SCT EVCTRL1: STATELD Mask */ -#define SCT_EVCTRL1_STATEV_Pos 15 /*!< SCT EVCTRL1: STATEV Position */ -#define SCT_EVCTRL1_STATEV_Msk (0x1fUL << SCT_EVCTRL1_STATEV_Pos) /*!< SCT EVCTRL1: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK2 ---------------------------------------- -#define SCT_EVSTATEMSK2_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL2 ------------------------------------------ -#define SCT_EVCTRL2_MATCHSEL_Pos 0 /*!< SCT EVCTRL2: MATCHSEL Position */ -#define SCT_EVCTRL2_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos) /*!< SCT EVCTRL2: MATCHSEL Mask */ -#define SCT_EVCTRL2_HEVENT_Pos 4 /*!< SCT EVCTRL2: HEVENT Position */ -#define SCT_EVCTRL2_HEVENT_Msk (0x01UL << SCT_EVCTRL2_HEVENT_Pos) /*!< SCT EVCTRL2: HEVENT Mask */ -#define SCT_EVCTRL2_OUTSEL_Pos 5 /*!< SCT EVCTRL2: OUTSEL Position */ -#define SCT_EVCTRL2_OUTSEL_Msk (0x01UL << SCT_EVCTRL2_OUTSEL_Pos) /*!< SCT EVCTRL2: OUTSEL Mask */ -#define SCT_EVCTRL2_IOSEL_Pos 6 /*!< SCT EVCTRL2: IOSEL Position */ -#define SCT_EVCTRL2_IOSEL_Msk (0x0fUL << SCT_EVCTRL2_IOSEL_Pos) /*!< SCT EVCTRL2: IOSEL Mask */ -#define SCT_EVCTRL2_IOCOND_Pos 10 /*!< SCT EVCTRL2: IOCOND Position */ -#define SCT_EVCTRL2_IOCOND_Msk (0x03UL << SCT_EVCTRL2_IOCOND_Pos) /*!< SCT EVCTRL2: IOCOND Mask */ -#define SCT_EVCTRL2_COMBMODE_Pos 12 /*!< SCT EVCTRL2: COMBMODE Position */ -#define SCT_EVCTRL2_COMBMODE_Msk (0x03UL << SCT_EVCTRL2_COMBMODE_Pos) /*!< SCT EVCTRL2: COMBMODE Mask */ -#define SCT_EVCTRL2_STATELD_Pos 14 /*!< SCT EVCTRL2: STATELD Position */ -#define SCT_EVCTRL2_STATELD_Msk (0x01UL << SCT_EVCTRL2_STATELD_Pos) /*!< SCT EVCTRL2: STATELD Mask */ -#define SCT_EVCTRL2_STATEV_Pos 15 /*!< SCT EVCTRL2: STATEV Position */ -#define SCT_EVCTRL2_STATEV_Msk (0x1fUL << SCT_EVCTRL2_STATEV_Pos) /*!< SCT EVCTRL2: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK3 ---------------------------------------- -#define SCT_EVSTATEMSK3_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL3 ------------------------------------------ -#define SCT_EVCTRL3_MATCHSEL_Pos 0 /*!< SCT EVCTRL3: MATCHSEL Position */ -#define SCT_EVCTRL3_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos) /*!< SCT EVCTRL3: MATCHSEL Mask */ -#define SCT_EVCTRL3_HEVENT_Pos 4 /*!< SCT EVCTRL3: HEVENT Position */ -#define SCT_EVCTRL3_HEVENT_Msk (0x01UL << SCT_EVCTRL3_HEVENT_Pos) /*!< SCT EVCTRL3: HEVENT Mask */ -#define SCT_EVCTRL3_OUTSEL_Pos 5 /*!< SCT EVCTRL3: OUTSEL Position */ -#define SCT_EVCTRL3_OUTSEL_Msk (0x01UL << SCT_EVCTRL3_OUTSEL_Pos) /*!< SCT EVCTRL3: OUTSEL Mask */ -#define SCT_EVCTRL3_IOSEL_Pos 6 /*!< SCT EVCTRL3: IOSEL Position */ -#define SCT_EVCTRL3_IOSEL_Msk (0x0fUL << SCT_EVCTRL3_IOSEL_Pos) /*!< SCT EVCTRL3: IOSEL Mask */ -#define SCT_EVCTRL3_IOCOND_Pos 10 /*!< SCT EVCTRL3: IOCOND Position */ -#define SCT_EVCTRL3_IOCOND_Msk (0x03UL << SCT_EVCTRL3_IOCOND_Pos) /*!< SCT EVCTRL3: IOCOND Mask */ -#define SCT_EVCTRL3_COMBMODE_Pos 12 /*!< SCT EVCTRL3: COMBMODE Position */ -#define SCT_EVCTRL3_COMBMODE_Msk (0x03UL << SCT_EVCTRL3_COMBMODE_Pos) /*!< SCT EVCTRL3: COMBMODE Mask */ -#define SCT_EVCTRL3_STATELD_Pos 14 /*!< SCT EVCTRL3: STATELD Position */ -#define SCT_EVCTRL3_STATELD_Msk (0x01UL << SCT_EVCTRL3_STATELD_Pos) /*!< SCT EVCTRL3: STATELD Mask */ -#define SCT_EVCTRL3_STATEV_Pos 15 /*!< SCT EVCTRL3: STATEV Position */ -#define SCT_EVCTRL3_STATEV_Msk (0x1fUL << SCT_EVCTRL3_STATEV_Pos) /*!< SCT EVCTRL3: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK4 ---------------------------------------- -#define SCT_EVSTATEMSK4_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL4 ------------------------------------------ -#define SCT_EVCTRL4_MATCHSEL_Pos 0 /*!< SCT EVCTRL4: MATCHSEL Position */ -#define SCT_EVCTRL4_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos) /*!< SCT EVCTRL4: MATCHSEL Mask */ -#define SCT_EVCTRL4_HEVENT_Pos 4 /*!< SCT EVCTRL4: HEVENT Position */ -#define SCT_EVCTRL4_HEVENT_Msk (0x01UL << SCT_EVCTRL4_HEVENT_Pos) /*!< SCT EVCTRL4: HEVENT Mask */ -#define SCT_EVCTRL4_OUTSEL_Pos 5 /*!< SCT EVCTRL4: OUTSEL Position */ -#define SCT_EVCTRL4_OUTSEL_Msk (0x01UL << SCT_EVCTRL4_OUTSEL_Pos) /*!< SCT EVCTRL4: OUTSEL Mask */ -#define SCT_EVCTRL4_IOSEL_Pos 6 /*!< SCT EVCTRL4: IOSEL Position */ -#define SCT_EVCTRL4_IOSEL_Msk (0x0fUL << SCT_EVCTRL4_IOSEL_Pos) /*!< SCT EVCTRL4: IOSEL Mask */ -#define SCT_EVCTRL4_IOCOND_Pos 10 /*!< SCT EVCTRL4: IOCOND Position */ -#define SCT_EVCTRL4_IOCOND_Msk (0x03UL << SCT_EVCTRL4_IOCOND_Pos) /*!< SCT EVCTRL4: IOCOND Mask */ -#define SCT_EVCTRL4_COMBMODE_Pos 12 /*!< SCT EVCTRL4: COMBMODE Position */ -#define SCT_EVCTRL4_COMBMODE_Msk (0x03UL << SCT_EVCTRL4_COMBMODE_Pos) /*!< SCT EVCTRL4: COMBMODE Mask */ -#define SCT_EVCTRL4_STATELD_Pos 14 /*!< SCT EVCTRL4: STATELD Position */ -#define SCT_EVCTRL4_STATELD_Msk (0x01UL << SCT_EVCTRL4_STATELD_Pos) /*!< SCT EVCTRL4: STATELD Mask */ -#define SCT_EVCTRL4_STATEV_Pos 15 /*!< SCT EVCTRL4: STATEV Position */ -#define SCT_EVCTRL4_STATEV_Msk (0x1fUL << SCT_EVCTRL4_STATEV_Pos) /*!< SCT EVCTRL4: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK5 ---------------------------------------- -#define SCT_EVSTATEMSK5_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL5 ------------------------------------------ -#define SCT_EVCTRL5_MATCHSEL_Pos 0 /*!< SCT EVCTRL5: MATCHSEL Position */ -#define SCT_EVCTRL5_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos) /*!< SCT EVCTRL5: MATCHSEL Mask */ -#define SCT_EVCTRL5_HEVENT_Pos 4 /*!< SCT EVCTRL5: HEVENT Position */ -#define SCT_EVCTRL5_HEVENT_Msk (0x01UL << SCT_EVCTRL5_HEVENT_Pos) /*!< SCT EVCTRL5: HEVENT Mask */ -#define SCT_EVCTRL5_OUTSEL_Pos 5 /*!< SCT EVCTRL5: OUTSEL Position */ -#define SCT_EVCTRL5_OUTSEL_Msk (0x01UL << SCT_EVCTRL5_OUTSEL_Pos) /*!< SCT EVCTRL5: OUTSEL Mask */ -#define SCT_EVCTRL5_IOSEL_Pos 6 /*!< SCT EVCTRL5: IOSEL Position */ -#define SCT_EVCTRL5_IOSEL_Msk (0x0fUL << SCT_EVCTRL5_IOSEL_Pos) /*!< SCT EVCTRL5: IOSEL Mask */ -#define SCT_EVCTRL5_IOCOND_Pos 10 /*!< SCT EVCTRL5: IOCOND Position */ -#define SCT_EVCTRL5_IOCOND_Msk (0x03UL << SCT_EVCTRL5_IOCOND_Pos) /*!< SCT EVCTRL5: IOCOND Mask */ -#define SCT_EVCTRL5_COMBMODE_Pos 12 /*!< SCT EVCTRL5: COMBMODE Position */ -#define SCT_EVCTRL5_COMBMODE_Msk (0x03UL << SCT_EVCTRL5_COMBMODE_Pos) /*!< SCT EVCTRL5: COMBMODE Mask */ -#define SCT_EVCTRL5_STATELD_Pos 14 /*!< SCT EVCTRL5: STATELD Position */ -#define SCT_EVCTRL5_STATELD_Msk (0x01UL << SCT_EVCTRL5_STATELD_Pos) /*!< SCT EVCTRL5: STATELD Mask */ -#define SCT_EVCTRL5_STATEV_Pos 15 /*!< SCT EVCTRL5: STATEV Position */ -#define SCT_EVCTRL5_STATEV_Msk (0x1fUL << SCT_EVCTRL5_STATEV_Pos) /*!< SCT EVCTRL5: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK6 ---------------------------------------- -#define SCT_EVSTATEMSK6_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL6 ------------------------------------------ -#define SCT_EVCTRL6_MATCHSEL_Pos 0 /*!< SCT EVCTRL6: MATCHSEL Position */ -#define SCT_EVCTRL6_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos) /*!< SCT EVCTRL6: MATCHSEL Mask */ -#define SCT_EVCTRL6_HEVENT_Pos 4 /*!< SCT EVCTRL6: HEVENT Position */ -#define SCT_EVCTRL6_HEVENT_Msk (0x01UL << SCT_EVCTRL6_HEVENT_Pos) /*!< SCT EVCTRL6: HEVENT Mask */ -#define SCT_EVCTRL6_OUTSEL_Pos 5 /*!< SCT EVCTRL6: OUTSEL Position */ -#define SCT_EVCTRL6_OUTSEL_Msk (0x01UL << SCT_EVCTRL6_OUTSEL_Pos) /*!< SCT EVCTRL6: OUTSEL Mask */ -#define SCT_EVCTRL6_IOSEL_Pos 6 /*!< SCT EVCTRL6: IOSEL Position */ -#define SCT_EVCTRL6_IOSEL_Msk (0x0fUL << SCT_EVCTRL6_IOSEL_Pos) /*!< SCT EVCTRL6: IOSEL Mask */ -#define SCT_EVCTRL6_IOCOND_Pos 10 /*!< SCT EVCTRL6: IOCOND Position */ -#define SCT_EVCTRL6_IOCOND_Msk (0x03UL << SCT_EVCTRL6_IOCOND_Pos) /*!< SCT EVCTRL6: IOCOND Mask */ -#define SCT_EVCTRL6_COMBMODE_Pos 12 /*!< SCT EVCTRL6: COMBMODE Position */ -#define SCT_EVCTRL6_COMBMODE_Msk (0x03UL << SCT_EVCTRL6_COMBMODE_Pos) /*!< SCT EVCTRL6: COMBMODE Mask */ -#define SCT_EVCTRL6_STATELD_Pos 14 /*!< SCT EVCTRL6: STATELD Position */ -#define SCT_EVCTRL6_STATELD_Msk (0x01UL << SCT_EVCTRL6_STATELD_Pos) /*!< SCT EVCTRL6: STATELD Mask */ -#define SCT_EVCTRL6_STATEV_Pos 15 /*!< SCT EVCTRL6: STATEV Position */ -#define SCT_EVCTRL6_STATEV_Msk (0x1fUL << SCT_EVCTRL6_STATEV_Pos) /*!< SCT EVCTRL6: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK7 ---------------------------------------- -#define SCT_EVSTATEMSK7_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL7 ------------------------------------------ -#define SCT_EVCTRL7_MATCHSEL_Pos 0 /*!< SCT EVCTRL7: MATCHSEL Position */ -#define SCT_EVCTRL7_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos) /*!< SCT EVCTRL7: MATCHSEL Mask */ -#define SCT_EVCTRL7_HEVENT_Pos 4 /*!< SCT EVCTRL7: HEVENT Position */ -#define SCT_EVCTRL7_HEVENT_Msk (0x01UL << SCT_EVCTRL7_HEVENT_Pos) /*!< SCT EVCTRL7: HEVENT Mask */ -#define SCT_EVCTRL7_OUTSEL_Pos 5 /*!< SCT EVCTRL7: OUTSEL Position */ -#define SCT_EVCTRL7_OUTSEL_Msk (0x01UL << SCT_EVCTRL7_OUTSEL_Pos) /*!< SCT EVCTRL7: OUTSEL Mask */ -#define SCT_EVCTRL7_IOSEL_Pos 6 /*!< SCT EVCTRL7: IOSEL Position */ -#define SCT_EVCTRL7_IOSEL_Msk (0x0fUL << SCT_EVCTRL7_IOSEL_Pos) /*!< SCT EVCTRL7: IOSEL Mask */ -#define SCT_EVCTRL7_IOCOND_Pos 10 /*!< SCT EVCTRL7: IOCOND Position */ -#define SCT_EVCTRL7_IOCOND_Msk (0x03UL << SCT_EVCTRL7_IOCOND_Pos) /*!< SCT EVCTRL7: IOCOND Mask */ -#define SCT_EVCTRL7_COMBMODE_Pos 12 /*!< SCT EVCTRL7: COMBMODE Position */ -#define SCT_EVCTRL7_COMBMODE_Msk (0x03UL << SCT_EVCTRL7_COMBMODE_Pos) /*!< SCT EVCTRL7: COMBMODE Mask */ -#define SCT_EVCTRL7_STATELD_Pos 14 /*!< SCT EVCTRL7: STATELD Position */ -#define SCT_EVCTRL7_STATELD_Msk (0x01UL << SCT_EVCTRL7_STATELD_Pos) /*!< SCT EVCTRL7: STATELD Mask */ -#define SCT_EVCTRL7_STATEV_Pos 15 /*!< SCT EVCTRL7: STATEV Position */ -#define SCT_EVCTRL7_STATEV_Msk (0x1fUL << SCT_EVCTRL7_STATEV_Pos) /*!< SCT EVCTRL7: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK8 ---------------------------------------- -#define SCT_EVSTATEMSK8_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL8 ------------------------------------------ -#define SCT_EVCTRL8_MATCHSEL_Pos 0 /*!< SCT EVCTRL8: MATCHSEL Position */ -#define SCT_EVCTRL8_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos) /*!< SCT EVCTRL8: MATCHSEL Mask */ -#define SCT_EVCTRL8_HEVENT_Pos 4 /*!< SCT EVCTRL8: HEVENT Position */ -#define SCT_EVCTRL8_HEVENT_Msk (0x01UL << SCT_EVCTRL8_HEVENT_Pos) /*!< SCT EVCTRL8: HEVENT Mask */ -#define SCT_EVCTRL8_OUTSEL_Pos 5 /*!< SCT EVCTRL8: OUTSEL Position */ -#define SCT_EVCTRL8_OUTSEL_Msk (0x01UL << SCT_EVCTRL8_OUTSEL_Pos) /*!< SCT EVCTRL8: OUTSEL Mask */ -#define SCT_EVCTRL8_IOSEL_Pos 6 /*!< SCT EVCTRL8: IOSEL Position */ -#define SCT_EVCTRL8_IOSEL_Msk (0x0fUL << SCT_EVCTRL8_IOSEL_Pos) /*!< SCT EVCTRL8: IOSEL Mask */ -#define SCT_EVCTRL8_IOCOND_Pos 10 /*!< SCT EVCTRL8: IOCOND Position */ -#define SCT_EVCTRL8_IOCOND_Msk (0x03UL << SCT_EVCTRL8_IOCOND_Pos) /*!< SCT EVCTRL8: IOCOND Mask */ -#define SCT_EVCTRL8_COMBMODE_Pos 12 /*!< SCT EVCTRL8: COMBMODE Position */ -#define SCT_EVCTRL8_COMBMODE_Msk (0x03UL << SCT_EVCTRL8_COMBMODE_Pos) /*!< SCT EVCTRL8: COMBMODE Mask */ -#define SCT_EVCTRL8_STATELD_Pos 14 /*!< SCT EVCTRL8: STATELD Position */ -#define SCT_EVCTRL8_STATELD_Msk (0x01UL << SCT_EVCTRL8_STATELD_Pos) /*!< SCT EVCTRL8: STATELD Mask */ -#define SCT_EVCTRL8_STATEV_Pos 15 /*!< SCT EVCTRL8: STATEV Position */ -#define SCT_EVCTRL8_STATEV_Msk (0x1fUL << SCT_EVCTRL8_STATEV_Pos) /*!< SCT EVCTRL8: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK9 ---------------------------------------- -#define SCT_EVSTATEMSK9_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL9 ------------------------------------------ -#define SCT_EVCTRL9_MATCHSEL_Pos 0 /*!< SCT EVCTRL9: MATCHSEL Position */ -#define SCT_EVCTRL9_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos) /*!< SCT EVCTRL9: MATCHSEL Mask */ -#define SCT_EVCTRL9_HEVENT_Pos 4 /*!< SCT EVCTRL9: HEVENT Position */ -#define SCT_EVCTRL9_HEVENT_Msk (0x01UL << SCT_EVCTRL9_HEVENT_Pos) /*!< SCT EVCTRL9: HEVENT Mask */ -#define SCT_EVCTRL9_OUTSEL_Pos 5 /*!< SCT EVCTRL9: OUTSEL Position */ -#define SCT_EVCTRL9_OUTSEL_Msk (0x01UL << SCT_EVCTRL9_OUTSEL_Pos) /*!< SCT EVCTRL9: OUTSEL Mask */ -#define SCT_EVCTRL9_IOSEL_Pos 6 /*!< SCT EVCTRL9: IOSEL Position */ -#define SCT_EVCTRL9_IOSEL_Msk (0x0fUL << SCT_EVCTRL9_IOSEL_Pos) /*!< SCT EVCTRL9: IOSEL Mask */ -#define SCT_EVCTRL9_IOCOND_Pos 10 /*!< SCT EVCTRL9: IOCOND Position */ -#define SCT_EVCTRL9_IOCOND_Msk (0x03UL << SCT_EVCTRL9_IOCOND_Pos) /*!< SCT EVCTRL9: IOCOND Mask */ -#define SCT_EVCTRL9_COMBMODE_Pos 12 /*!< SCT EVCTRL9: COMBMODE Position */ -#define SCT_EVCTRL9_COMBMODE_Msk (0x03UL << SCT_EVCTRL9_COMBMODE_Pos) /*!< SCT EVCTRL9: COMBMODE Mask */ -#define SCT_EVCTRL9_STATELD_Pos 14 /*!< SCT EVCTRL9: STATELD Position */ -#define SCT_EVCTRL9_STATELD_Msk (0x01UL << SCT_EVCTRL9_STATELD_Pos) /*!< SCT EVCTRL9: STATELD Mask */ -#define SCT_EVCTRL9_STATEV_Pos 15 /*!< SCT EVCTRL9: STATEV Position */ -#define SCT_EVCTRL9_STATEV_Msk (0x1fUL << SCT_EVCTRL9_STATEV_Pos) /*!< SCT EVCTRL9: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK10 ---------------------------------------- -#define SCT_EVSTATEMSK10_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL10 ------------------------------------------ -#define SCT_EVCTRL10_MATCHSEL_Pos 0 /*!< SCT EVCTRL10: MATCHSEL Position */ -#define SCT_EVCTRL10_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos) /*!< SCT EVCTRL10: MATCHSEL Mask */ -#define SCT_EVCTRL10_HEVENT_Pos 4 /*!< SCT EVCTRL10: HEVENT Position */ -#define SCT_EVCTRL10_HEVENT_Msk (0x01UL << SCT_EVCTRL10_HEVENT_Pos) /*!< SCT EVCTRL10: HEVENT Mask */ -#define SCT_EVCTRL10_OUTSEL_Pos 5 /*!< SCT EVCTRL10: OUTSEL Position */ -#define SCT_EVCTRL10_OUTSEL_Msk (0x01UL << SCT_EVCTRL10_OUTSEL_Pos) /*!< SCT EVCTRL10: OUTSEL Mask */ -#define SCT_EVCTRL10_IOSEL_Pos 6 /*!< SCT EVCTRL10: IOSEL Position */ -#define SCT_EVCTRL10_IOSEL_Msk (0x0fUL << SCT_EVCTRL10_IOSEL_Pos) /*!< SCT EVCTRL10: IOSEL Mask */ -#define SCT_EVCTRL10_IOCOND_Pos 10 /*!< SCT EVCTRL10: IOCOND Position */ -#define SCT_EVCTRL10_IOCOND_Msk (0x03UL << SCT_EVCTRL10_IOCOND_Pos) /*!< SCT EVCTRL10: IOCOND Mask */ -#define SCT_EVCTRL10_COMBMODE_Pos 12 /*!< SCT EVCTRL10: COMBMODE Position */ -#define SCT_EVCTRL10_COMBMODE_Msk (0x03UL << SCT_EVCTRL10_COMBMODE_Pos) /*!< SCT EVCTRL10: COMBMODE Mask */ -#define SCT_EVCTRL10_STATELD_Pos 14 /*!< SCT EVCTRL10: STATELD Position */ -#define SCT_EVCTRL10_STATELD_Msk (0x01UL << SCT_EVCTRL10_STATELD_Pos) /*!< SCT EVCTRL10: STATELD Mask */ -#define SCT_EVCTRL10_STATEV_Pos 15 /*!< SCT EVCTRL10: STATEV Position */ -#define SCT_EVCTRL10_STATEV_Msk (0x1fUL << SCT_EVCTRL10_STATEV_Pos) /*!< SCT EVCTRL10: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK11 ---------------------------------------- -#define SCT_EVSTATEMSK11_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL11 ------------------------------------------ -#define SCT_EVCTRL11_MATCHSEL_Pos 0 /*!< SCT EVCTRL11: MATCHSEL Position */ -#define SCT_EVCTRL11_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos) /*!< SCT EVCTRL11: MATCHSEL Mask */ -#define SCT_EVCTRL11_HEVENT_Pos 4 /*!< SCT EVCTRL11: HEVENT Position */ -#define SCT_EVCTRL11_HEVENT_Msk (0x01UL << SCT_EVCTRL11_HEVENT_Pos) /*!< SCT EVCTRL11: HEVENT Mask */ -#define SCT_EVCTRL11_OUTSEL_Pos 5 /*!< SCT EVCTRL11: OUTSEL Position */ -#define SCT_EVCTRL11_OUTSEL_Msk (0x01UL << SCT_EVCTRL11_OUTSEL_Pos) /*!< SCT EVCTRL11: OUTSEL Mask */ -#define SCT_EVCTRL11_IOSEL_Pos 6 /*!< SCT EVCTRL11: IOSEL Position */ -#define SCT_EVCTRL11_IOSEL_Msk (0x0fUL << SCT_EVCTRL11_IOSEL_Pos) /*!< SCT EVCTRL11: IOSEL Mask */ -#define SCT_EVCTRL11_IOCOND_Pos 10 /*!< SCT EVCTRL11: IOCOND Position */ -#define SCT_EVCTRL11_IOCOND_Msk (0x03UL << SCT_EVCTRL11_IOCOND_Pos) /*!< SCT EVCTRL11: IOCOND Mask */ -#define SCT_EVCTRL11_COMBMODE_Pos 12 /*!< SCT EVCTRL11: COMBMODE Position */ -#define SCT_EVCTRL11_COMBMODE_Msk (0x03UL << SCT_EVCTRL11_COMBMODE_Pos) /*!< SCT EVCTRL11: COMBMODE Mask */ -#define SCT_EVCTRL11_STATELD_Pos 14 /*!< SCT EVCTRL11: STATELD Position */ -#define SCT_EVCTRL11_STATELD_Msk (0x01UL << SCT_EVCTRL11_STATELD_Pos) /*!< SCT EVCTRL11: STATELD Mask */ -#define SCT_EVCTRL11_STATEV_Pos 15 /*!< SCT EVCTRL11: STATEV Position */ -#define SCT_EVCTRL11_STATEV_Msk (0x1fUL << SCT_EVCTRL11_STATEV_Pos) /*!< SCT EVCTRL11: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK12 ---------------------------------------- -#define SCT_EVSTATEMSK12_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL12 ------------------------------------------ -#define SCT_EVCTRL12_MATCHSEL_Pos 0 /*!< SCT EVCTRL12: MATCHSEL Position */ -#define SCT_EVCTRL12_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos) /*!< SCT EVCTRL12: MATCHSEL Mask */ -#define SCT_EVCTRL12_HEVENT_Pos 4 /*!< SCT EVCTRL12: HEVENT Position */ -#define SCT_EVCTRL12_HEVENT_Msk (0x01UL << SCT_EVCTRL12_HEVENT_Pos) /*!< SCT EVCTRL12: HEVENT Mask */ -#define SCT_EVCTRL12_OUTSEL_Pos 5 /*!< SCT EVCTRL12: OUTSEL Position */ -#define SCT_EVCTRL12_OUTSEL_Msk (0x01UL << SCT_EVCTRL12_OUTSEL_Pos) /*!< SCT EVCTRL12: OUTSEL Mask */ -#define SCT_EVCTRL12_IOSEL_Pos 6 /*!< SCT EVCTRL12: IOSEL Position */ -#define SCT_EVCTRL12_IOSEL_Msk (0x0fUL << SCT_EVCTRL12_IOSEL_Pos) /*!< SCT EVCTRL12: IOSEL Mask */ -#define SCT_EVCTRL12_IOCOND_Pos 10 /*!< SCT EVCTRL12: IOCOND Position */ -#define SCT_EVCTRL12_IOCOND_Msk (0x03UL << SCT_EVCTRL12_IOCOND_Pos) /*!< SCT EVCTRL12: IOCOND Mask */ -#define SCT_EVCTRL12_COMBMODE_Pos 12 /*!< SCT EVCTRL12: COMBMODE Position */ -#define SCT_EVCTRL12_COMBMODE_Msk (0x03UL << SCT_EVCTRL12_COMBMODE_Pos) /*!< SCT EVCTRL12: COMBMODE Mask */ -#define SCT_EVCTRL12_STATELD_Pos 14 /*!< SCT EVCTRL12: STATELD Position */ -#define SCT_EVCTRL12_STATELD_Msk (0x01UL << SCT_EVCTRL12_STATELD_Pos) /*!< SCT EVCTRL12: STATELD Mask */ -#define SCT_EVCTRL12_STATEV_Pos 15 /*!< SCT EVCTRL12: STATEV Position */ -#define SCT_EVCTRL12_STATEV_Msk (0x1fUL << SCT_EVCTRL12_STATEV_Pos) /*!< SCT EVCTRL12: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK13 ---------------------------------------- -#define SCT_EVSTATEMSK13_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL13 ------------------------------------------ -#define SCT_EVCTRL13_MATCHSEL_Pos 0 /*!< SCT EVCTRL13: MATCHSEL Position */ -#define SCT_EVCTRL13_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos) /*!< SCT EVCTRL13: MATCHSEL Mask */ -#define SCT_EVCTRL13_HEVENT_Pos 4 /*!< SCT EVCTRL13: HEVENT Position */ -#define SCT_EVCTRL13_HEVENT_Msk (0x01UL << SCT_EVCTRL13_HEVENT_Pos) /*!< SCT EVCTRL13: HEVENT Mask */ -#define SCT_EVCTRL13_OUTSEL_Pos 5 /*!< SCT EVCTRL13: OUTSEL Position */ -#define SCT_EVCTRL13_OUTSEL_Msk (0x01UL << SCT_EVCTRL13_OUTSEL_Pos) /*!< SCT EVCTRL13: OUTSEL Mask */ -#define SCT_EVCTRL13_IOSEL_Pos 6 /*!< SCT EVCTRL13: IOSEL Position */ -#define SCT_EVCTRL13_IOSEL_Msk (0x0fUL << SCT_EVCTRL13_IOSEL_Pos) /*!< SCT EVCTRL13: IOSEL Mask */ -#define SCT_EVCTRL13_IOCOND_Pos 10 /*!< SCT EVCTRL13: IOCOND Position */ -#define SCT_EVCTRL13_IOCOND_Msk (0x03UL << SCT_EVCTRL13_IOCOND_Pos) /*!< SCT EVCTRL13: IOCOND Mask */ -#define SCT_EVCTRL13_COMBMODE_Pos 12 /*!< SCT EVCTRL13: COMBMODE Position */ -#define SCT_EVCTRL13_COMBMODE_Msk (0x03UL << SCT_EVCTRL13_COMBMODE_Pos) /*!< SCT EVCTRL13: COMBMODE Mask */ -#define SCT_EVCTRL13_STATELD_Pos 14 /*!< SCT EVCTRL13: STATELD Position */ -#define SCT_EVCTRL13_STATELD_Msk (0x01UL << SCT_EVCTRL13_STATELD_Pos) /*!< SCT EVCTRL13: STATELD Mask */ -#define SCT_EVCTRL13_STATEV_Pos 15 /*!< SCT EVCTRL13: STATEV Position */ -#define SCT_EVCTRL13_STATEV_Msk (0x1fUL << SCT_EVCTRL13_STATEV_Pos) /*!< SCT EVCTRL13: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK14 ---------------------------------------- -#define SCT_EVSTATEMSK14_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL14 ------------------------------------------ -#define SCT_EVCTRL14_MATCHSEL_Pos 0 /*!< SCT EVCTRL14: MATCHSEL Position */ -#define SCT_EVCTRL14_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos) /*!< SCT EVCTRL14: MATCHSEL Mask */ -#define SCT_EVCTRL14_HEVENT_Pos 4 /*!< SCT EVCTRL14: HEVENT Position */ -#define SCT_EVCTRL14_HEVENT_Msk (0x01UL << SCT_EVCTRL14_HEVENT_Pos) /*!< SCT EVCTRL14: HEVENT Mask */ -#define SCT_EVCTRL14_OUTSEL_Pos 5 /*!< SCT EVCTRL14: OUTSEL Position */ -#define SCT_EVCTRL14_OUTSEL_Msk (0x01UL << SCT_EVCTRL14_OUTSEL_Pos) /*!< SCT EVCTRL14: OUTSEL Mask */ -#define SCT_EVCTRL14_IOSEL_Pos 6 /*!< SCT EVCTRL14: IOSEL Position */ -#define SCT_EVCTRL14_IOSEL_Msk (0x0fUL << SCT_EVCTRL14_IOSEL_Pos) /*!< SCT EVCTRL14: IOSEL Mask */ -#define SCT_EVCTRL14_IOCOND_Pos 10 /*!< SCT EVCTRL14: IOCOND Position */ -#define SCT_EVCTRL14_IOCOND_Msk (0x03UL << SCT_EVCTRL14_IOCOND_Pos) /*!< SCT EVCTRL14: IOCOND Mask */ -#define SCT_EVCTRL14_COMBMODE_Pos 12 /*!< SCT EVCTRL14: COMBMODE Position */ -#define SCT_EVCTRL14_COMBMODE_Msk (0x03UL << SCT_EVCTRL14_COMBMODE_Pos) /*!< SCT EVCTRL14: COMBMODE Mask */ -#define SCT_EVCTRL14_STATELD_Pos 14 /*!< SCT EVCTRL14: STATELD Position */ -#define SCT_EVCTRL14_STATELD_Msk (0x01UL << SCT_EVCTRL14_STATELD_Pos) /*!< SCT EVCTRL14: STATELD Mask */ -#define SCT_EVCTRL14_STATEV_Pos 15 /*!< SCT EVCTRL14: STATEV Position */ -#define SCT_EVCTRL14_STATEV_Msk (0x1fUL << SCT_EVCTRL14_STATEV_Pos) /*!< SCT EVCTRL14: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK15 ---------------------------------------- -#define SCT_EVSTATEMSK15_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL15 ------------------------------------------ -#define SCT_EVCTRL15_MATCHSEL_Pos 0 /*!< SCT EVCTRL15: MATCHSEL Position */ -#define SCT_EVCTRL15_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos) /*!< SCT EVCTRL15: MATCHSEL Mask */ -#define SCT_EVCTRL15_HEVENT_Pos 4 /*!< SCT EVCTRL15: HEVENT Position */ -#define SCT_EVCTRL15_HEVENT_Msk (0x01UL << SCT_EVCTRL15_HEVENT_Pos) /*!< SCT EVCTRL15: HEVENT Mask */ -#define SCT_EVCTRL15_OUTSEL_Pos 5 /*!< SCT EVCTRL15: OUTSEL Position */ -#define SCT_EVCTRL15_OUTSEL_Msk (0x01UL << SCT_EVCTRL15_OUTSEL_Pos) /*!< SCT EVCTRL15: OUTSEL Mask */ -#define SCT_EVCTRL15_IOSEL_Pos 6 /*!< SCT EVCTRL15: IOSEL Position */ -#define SCT_EVCTRL15_IOSEL_Msk (0x0fUL << SCT_EVCTRL15_IOSEL_Pos) /*!< SCT EVCTRL15: IOSEL Mask */ -#define SCT_EVCTRL15_IOCOND_Pos 10 /*!< SCT EVCTRL15: IOCOND Position */ -#define SCT_EVCTRL15_IOCOND_Msk (0x03UL << SCT_EVCTRL15_IOCOND_Pos) /*!< SCT EVCTRL15: IOCOND Mask */ -#define SCT_EVCTRL15_COMBMODE_Pos 12 /*!< SCT EVCTRL15: COMBMODE Position */ -#define SCT_EVCTRL15_COMBMODE_Msk (0x03UL << SCT_EVCTRL15_COMBMODE_Pos) /*!< SCT EVCTRL15: COMBMODE Mask */ -#define SCT_EVCTRL15_STATELD_Pos 14 /*!< SCT EVCTRL15: STATELD Position */ -#define SCT_EVCTRL15_STATELD_Msk (0x01UL << SCT_EVCTRL15_STATELD_Pos) /*!< SCT EVCTRL15: STATELD Mask */ -#define SCT_EVCTRL15_STATEV_Pos 15 /*!< SCT EVCTRL15: STATEV Position */ -#define SCT_EVCTRL15_STATEV_Msk (0x1fUL << SCT_EVCTRL15_STATEV_Pos) /*!< SCT EVCTRL15: STATEV Mask */ - -// ------------------------------------- SCT_OUTPUTSET0 ----------------------------------------- -#define SCT_OUTPUTSET0_SETn0_Pos 0 /*!< SCT OUTPUTSET0: SETn0 Position */ -#define SCT_OUTPUTSET0_SETn0_Msk (0x01UL << SCT_OUTPUTSET0_SETn0_Pos) /*!< SCT OUTPUTSET0: SETn0 Mask */ -#define SCT_OUTPUTSET0_SETn1_Pos 1 /*!< SCT OUTPUTSET0: SETn1 Position */ -#define SCT_OUTPUTSET0_SETn1_Msk (0x01UL << SCT_OUTPUTSET0_SETn1_Pos) /*!< SCT OUTPUTSET0: SETn1 Mask */ -#define SCT_OUTPUTSET0_SETn2_Pos 2 /*!< SCT OUTPUTSET0: SETn2 Position */ -#define SCT_OUTPUTSET0_SETn2_Msk (0x01UL << SCT_OUTPUTSET0_SETn2_Pos) /*!< SCT OUTPUTSET0: SETn2 Mask */ -#define SCT_OUTPUTSET0_SETn3_Pos 3 /*!< SCT OUTPUTSET0: SETn3 Position */ -#define SCT_OUTPUTSET0_SETn3_Msk (0x01UL << SCT_OUTPUTSET0_SETn3_Pos) /*!< SCT OUTPUTSET0: SETn3 Mask */ -#define SCT_OUTPUTSET0_SETn4_Pos 4 /*!< SCT OUTPUTSET0: SETn4 Position */ -#define SCT_OUTPUTSET0_SETn4_Msk (0x01UL << SCT_OUTPUTSET0_SETn4_Pos) /*!< SCT OUTPUTSET0: SETn4 Mask */ -#define SCT_OUTPUTSET0_SETn5_Pos 5 /*!< SCT OUTPUTSET0: SETn5 Position */ -#define SCT_OUTPUTSET0_SETn5_Msk (0x01UL << SCT_OUTPUTSET0_SETn5_Pos) /*!< SCT OUTPUTSET0: SETn5 Mask */ -#define SCT_OUTPUTSET0_SETn6_Pos 6 /*!< SCT OUTPUTSET0: SETn6 Position */ -#define SCT_OUTPUTSET0_SETn6_Msk (0x01UL << SCT_OUTPUTSET0_SETn6_Pos) /*!< SCT OUTPUTSET0: SETn6 Mask */ -#define SCT_OUTPUTSET0_SETn7_Pos 7 /*!< SCT OUTPUTSET0: SETn7 Position */ -#define SCT_OUTPUTSET0_SETn7_Msk (0x01UL << SCT_OUTPUTSET0_SETn7_Pos) /*!< SCT OUTPUTSET0: SETn7 Mask */ -#define SCT_OUTPUTSET0_SETn8_Pos 8 /*!< SCT OUTPUTSET0: SETn8 Position */ -#define SCT_OUTPUTSET0_SETn8_Msk (0x01UL << SCT_OUTPUTSET0_SETn8_Pos) /*!< SCT OUTPUTSET0: SETn8 Mask */ -#define SCT_OUTPUTSET0_SETn9_Pos 9 /*!< SCT OUTPUTSET0: SETn9 Position */ -#define SCT_OUTPUTSET0_SETn9_Msk (0x01UL << SCT_OUTPUTSET0_SETn9_Pos) /*!< SCT OUTPUTSET0: SETn9 Mask */ -#define SCT_OUTPUTSET0_SETn10_Pos 10 /*!< SCT OUTPUTSET0: SETn10 Position */ -#define SCT_OUTPUTSET0_SETn10_Msk (0x01UL << SCT_OUTPUTSET0_SETn10_Pos) /*!< SCT OUTPUTSET0: SETn10 Mask */ -#define SCT_OUTPUTSET0_SETn11_Pos 11 /*!< SCT OUTPUTSET0: SETn11 Position */ -#define SCT_OUTPUTSET0_SETn11_Msk (0x01UL << SCT_OUTPUTSET0_SETn11_Pos) /*!< SCT OUTPUTSET0: SETn11 Mask */ -#define SCT_OUTPUTSET0_SETn12_Pos 12 /*!< SCT OUTPUTSET0: SETn12 Position */ -#define SCT_OUTPUTSET0_SETn12_Msk (0x01UL << SCT_OUTPUTSET0_SETn12_Pos) /*!< SCT OUTPUTSET0: SETn12 Mask */ -#define SCT_OUTPUTSET0_SETn13_Pos 13 /*!< SCT OUTPUTSET0: SETn13 Position */ -#define SCT_OUTPUTSET0_SETn13_Msk (0x01UL << SCT_OUTPUTSET0_SETn13_Pos) /*!< SCT OUTPUTSET0: SETn13 Mask */ -#define SCT_OUTPUTSET0_SETn14_Pos 14 /*!< SCT OUTPUTSET0: SETn14 Position */ -#define SCT_OUTPUTSET0_SETn14_Msk (0x01UL << SCT_OUTPUTSET0_SETn14_Pos) /*!< SCT OUTPUTSET0: SETn14 Mask */ -#define SCT_OUTPUTSET0_SETn15_Pos 15 /*!< SCT OUTPUTSET0: SETn15 Position */ -#define SCT_OUTPUTSET0_SETn15_Msk (0x01UL << SCT_OUTPUTSET0_SETn15_Pos) /*!< SCT OUTPUTSET0: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR0 ----------------------------------------- -#define SCT_OUTPUTCLR0_CLRn0_Pos 0 /*!< SCT OUTPUTCLR0: CLRn0 Position */ -#define SCT_OUTPUTCLR0_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos) /*!< SCT OUTPUTCLR0: CLRn0 Mask */ -#define SCT_OUTPUTCLR0_CLRn1_Pos 1 /*!< SCT OUTPUTCLR0: CLRn1 Position */ -#define SCT_OUTPUTCLR0_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos) /*!< SCT OUTPUTCLR0: CLRn1 Mask */ -#define SCT_OUTPUTCLR0_CLRn2_Pos 2 /*!< SCT OUTPUTCLR0: CLRn2 Position */ -#define SCT_OUTPUTCLR0_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos) /*!< SCT OUTPUTCLR0: CLRn2 Mask */ -#define SCT_OUTPUTCLR0_CLRn3_Pos 3 /*!< SCT OUTPUTCLR0: CLRn3 Position */ -#define SCT_OUTPUTCLR0_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos) /*!< SCT OUTPUTCLR0: CLRn3 Mask */ -#define SCT_OUTPUTCLR0_CLRn4_Pos 4 /*!< SCT OUTPUTCLR0: CLRn4 Position */ -#define SCT_OUTPUTCLR0_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos) /*!< SCT OUTPUTCLR0: CLRn4 Mask */ -#define SCT_OUTPUTCLR0_CLRn5_Pos 5 /*!< SCT OUTPUTCLR0: CLRn5 Position */ -#define SCT_OUTPUTCLR0_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos) /*!< SCT OUTPUTCLR0: CLRn5 Mask */ -#define SCT_OUTPUTCLR0_CLRn6_Pos 6 /*!< SCT OUTPUTCLR0: CLRn6 Position */ -#define SCT_OUTPUTCLR0_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos) /*!< SCT OUTPUTCLR0: CLRn6 Mask */ -#define SCT_OUTPUTCLR0_CLRn7_Pos 7 /*!< SCT OUTPUTCLR0: CLRn7 Position */ -#define SCT_OUTPUTCLR0_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos) /*!< SCT OUTPUTCLR0: CLRn7 Mask */ -#define SCT_OUTPUTCLR0_CLRn8_Pos 8 /*!< SCT OUTPUTCLR0: CLRn8 Position */ -#define SCT_OUTPUTCLR0_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos) /*!< SCT OUTPUTCLR0: CLRn8 Mask */ -#define SCT_OUTPUTCLR0_CLRn9_Pos 9 /*!< SCT OUTPUTCLR0: CLRn9 Position */ -#define SCT_OUTPUTCLR0_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos) /*!< SCT OUTPUTCLR0: CLRn9 Mask */ -#define SCT_OUTPUTCLR0_CLRn10_Pos 10 /*!< SCT OUTPUTCLR0: CLRn10 Position */ -#define SCT_OUTPUTCLR0_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos) /*!< SCT OUTPUTCLR0: CLRn10 Mask */ -#define SCT_OUTPUTCLR0_CLRn11_Pos 11 /*!< SCT OUTPUTCLR0: CLRn11 Position */ -#define SCT_OUTPUTCLR0_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos) /*!< SCT OUTPUTCLR0: CLRn11 Mask */ -#define SCT_OUTPUTCLR0_CLRn12_Pos 12 /*!< SCT OUTPUTCLR0: CLRn12 Position */ -#define SCT_OUTPUTCLR0_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos) /*!< SCT OUTPUTCLR0: CLRn12 Mask */ -#define SCT_OUTPUTCLR0_CLRn13_Pos 13 /*!< SCT OUTPUTCLR0: CLRn13 Position */ -#define SCT_OUTPUTCLR0_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos) /*!< SCT OUTPUTCLR0: CLRn13 Mask */ -#define SCT_OUTPUTCLR0_CLRn14_Pos 14 /*!< SCT OUTPUTCLR0: CLRn14 Position */ -#define SCT_OUTPUTCLR0_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos) /*!< SCT OUTPUTCLR0: CLRn14 Mask */ -#define SCT_OUTPUTCLR0_CLRn15_Pos 15 /*!< SCT OUTPUTCLR0: CLRn15 Position */ -#define SCT_OUTPUTCLR0_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos) /*!< SCT OUTPUTCLR0: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET1 ----------------------------------------- -#define SCT_OUTPUTSET1_SETn0_Pos 0 /*!< SCT OUTPUTSET1: SETn0 Position */ -#define SCT_OUTPUTSET1_SETn0_Msk (0x01UL << SCT_OUTPUTSET1_SETn0_Pos) /*!< SCT OUTPUTSET1: SETn0 Mask */ -#define SCT_OUTPUTSET1_SETn1_Pos 1 /*!< SCT OUTPUTSET1: SETn1 Position */ -#define SCT_OUTPUTSET1_SETn1_Msk (0x01UL << SCT_OUTPUTSET1_SETn1_Pos) /*!< SCT OUTPUTSET1: SETn1 Mask */ -#define SCT_OUTPUTSET1_SETn2_Pos 2 /*!< SCT OUTPUTSET1: SETn2 Position */ -#define SCT_OUTPUTSET1_SETn2_Msk (0x01UL << SCT_OUTPUTSET1_SETn2_Pos) /*!< SCT OUTPUTSET1: SETn2 Mask */ -#define SCT_OUTPUTSET1_SETn3_Pos 3 /*!< SCT OUTPUTSET1: SETn3 Position */ -#define SCT_OUTPUTSET1_SETn3_Msk (0x01UL << SCT_OUTPUTSET1_SETn3_Pos) /*!< SCT OUTPUTSET1: SETn3 Mask */ -#define SCT_OUTPUTSET1_SETn4_Pos 4 /*!< SCT OUTPUTSET1: SETn4 Position */ -#define SCT_OUTPUTSET1_SETn4_Msk (0x01UL << SCT_OUTPUTSET1_SETn4_Pos) /*!< SCT OUTPUTSET1: SETn4 Mask */ -#define SCT_OUTPUTSET1_SETn5_Pos 5 /*!< SCT OUTPUTSET1: SETn5 Position */ -#define SCT_OUTPUTSET1_SETn5_Msk (0x01UL << SCT_OUTPUTSET1_SETn5_Pos) /*!< SCT OUTPUTSET1: SETn5 Mask */ -#define SCT_OUTPUTSET1_SETn6_Pos 6 /*!< SCT OUTPUTSET1: SETn6 Position */ -#define SCT_OUTPUTSET1_SETn6_Msk (0x01UL << SCT_OUTPUTSET1_SETn6_Pos) /*!< SCT OUTPUTSET1: SETn6 Mask */ -#define SCT_OUTPUTSET1_SETn7_Pos 7 /*!< SCT OUTPUTSET1: SETn7 Position */ -#define SCT_OUTPUTSET1_SETn7_Msk (0x01UL << SCT_OUTPUTSET1_SETn7_Pos) /*!< SCT OUTPUTSET1: SETn7 Mask */ -#define SCT_OUTPUTSET1_SETn8_Pos 8 /*!< SCT OUTPUTSET1: SETn8 Position */ -#define SCT_OUTPUTSET1_SETn8_Msk (0x01UL << SCT_OUTPUTSET1_SETn8_Pos) /*!< SCT OUTPUTSET1: SETn8 Mask */ -#define SCT_OUTPUTSET1_SETn9_Pos 9 /*!< SCT OUTPUTSET1: SETn9 Position */ -#define SCT_OUTPUTSET1_SETn9_Msk (0x01UL << SCT_OUTPUTSET1_SETn9_Pos) /*!< SCT OUTPUTSET1: SETn9 Mask */ -#define SCT_OUTPUTSET1_SETn10_Pos 10 /*!< SCT OUTPUTSET1: SETn10 Position */ -#define SCT_OUTPUTSET1_SETn10_Msk (0x01UL << SCT_OUTPUTSET1_SETn10_Pos) /*!< SCT OUTPUTSET1: SETn10 Mask */ -#define SCT_OUTPUTSET1_SETn11_Pos 11 /*!< SCT OUTPUTSET1: SETn11 Position */ -#define SCT_OUTPUTSET1_SETn11_Msk (0x01UL << SCT_OUTPUTSET1_SETn11_Pos) /*!< SCT OUTPUTSET1: SETn11 Mask */ -#define SCT_OUTPUTSET1_SETn12_Pos 12 /*!< SCT OUTPUTSET1: SETn12 Position */ -#define SCT_OUTPUTSET1_SETn12_Msk (0x01UL << SCT_OUTPUTSET1_SETn12_Pos) /*!< SCT OUTPUTSET1: SETn12 Mask */ -#define SCT_OUTPUTSET1_SETn13_Pos 13 /*!< SCT OUTPUTSET1: SETn13 Position */ -#define SCT_OUTPUTSET1_SETn13_Msk (0x01UL << SCT_OUTPUTSET1_SETn13_Pos) /*!< SCT OUTPUTSET1: SETn13 Mask */ -#define SCT_OUTPUTSET1_SETn14_Pos 14 /*!< SCT OUTPUTSET1: SETn14 Position */ -#define SCT_OUTPUTSET1_SETn14_Msk (0x01UL << SCT_OUTPUTSET1_SETn14_Pos) /*!< SCT OUTPUTSET1: SETn14 Mask */ -#define SCT_OUTPUTSET1_SETn15_Pos 15 /*!< SCT OUTPUTSET1: SETn15 Position */ -#define SCT_OUTPUTSET1_SETn15_Msk (0x01UL << SCT_OUTPUTSET1_SETn15_Pos) /*!< SCT OUTPUTSET1: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR1 ----------------------------------------- -#define SCT_OUTPUTCLR1_CLRn0_Pos 0 /*!< SCT OUTPUTCLR1: CLRn0 Position */ -#define SCT_OUTPUTCLR1_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos) /*!< SCT OUTPUTCLR1: CLRn0 Mask */ -#define SCT_OUTPUTCLR1_CLRn1_Pos 1 /*!< SCT OUTPUTCLR1: CLRn1 Position */ -#define SCT_OUTPUTCLR1_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos) /*!< SCT OUTPUTCLR1: CLRn1 Mask */ -#define SCT_OUTPUTCLR1_CLRn2_Pos 2 /*!< SCT OUTPUTCLR1: CLRn2 Position */ -#define SCT_OUTPUTCLR1_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos) /*!< SCT OUTPUTCLR1: CLRn2 Mask */ -#define SCT_OUTPUTCLR1_CLRn3_Pos 3 /*!< SCT OUTPUTCLR1: CLRn3 Position */ -#define SCT_OUTPUTCLR1_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos) /*!< SCT OUTPUTCLR1: CLRn3 Mask */ -#define SCT_OUTPUTCLR1_CLRn4_Pos 4 /*!< SCT OUTPUTCLR1: CLRn4 Position */ -#define SCT_OUTPUTCLR1_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos) /*!< SCT OUTPUTCLR1: CLRn4 Mask */ -#define SCT_OUTPUTCLR1_CLRn5_Pos 5 /*!< SCT OUTPUTCLR1: CLRn5 Position */ -#define SCT_OUTPUTCLR1_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos) /*!< SCT OUTPUTCLR1: CLRn5 Mask */ -#define SCT_OUTPUTCLR1_CLRn6_Pos 6 /*!< SCT OUTPUTCLR1: CLRn6 Position */ -#define SCT_OUTPUTCLR1_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos) /*!< SCT OUTPUTCLR1: CLRn6 Mask */ -#define SCT_OUTPUTCLR1_CLRn7_Pos 7 /*!< SCT OUTPUTCLR1: CLRn7 Position */ -#define SCT_OUTPUTCLR1_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos) /*!< SCT OUTPUTCLR1: CLRn7 Mask */ -#define SCT_OUTPUTCLR1_CLRn8_Pos 8 /*!< SCT OUTPUTCLR1: CLRn8 Position */ -#define SCT_OUTPUTCLR1_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos) /*!< SCT OUTPUTCLR1: CLRn8 Mask */ -#define SCT_OUTPUTCLR1_CLRn9_Pos 9 /*!< SCT OUTPUTCLR1: CLRn9 Position */ -#define SCT_OUTPUTCLR1_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos) /*!< SCT OUTPUTCLR1: CLRn9 Mask */ -#define SCT_OUTPUTCLR1_CLRn10_Pos 10 /*!< SCT OUTPUTCLR1: CLRn10 Position */ -#define SCT_OUTPUTCLR1_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos) /*!< SCT OUTPUTCLR1: CLRn10 Mask */ -#define SCT_OUTPUTCLR1_CLRn11_Pos 11 /*!< SCT OUTPUTCLR1: CLRn11 Position */ -#define SCT_OUTPUTCLR1_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos) /*!< SCT OUTPUTCLR1: CLRn11 Mask */ -#define SCT_OUTPUTCLR1_CLRn12_Pos 12 /*!< SCT OUTPUTCLR1: CLRn12 Position */ -#define SCT_OUTPUTCLR1_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos) /*!< SCT OUTPUTCLR1: CLRn12 Mask */ -#define SCT_OUTPUTCLR1_CLRn13_Pos 13 /*!< SCT OUTPUTCLR1: CLRn13 Position */ -#define SCT_OUTPUTCLR1_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos) /*!< SCT OUTPUTCLR1: CLRn13 Mask */ -#define SCT_OUTPUTCLR1_CLRn14_Pos 14 /*!< SCT OUTPUTCLR1: CLRn14 Position */ -#define SCT_OUTPUTCLR1_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos) /*!< SCT OUTPUTCLR1: CLRn14 Mask */ -#define SCT_OUTPUTCLR1_CLRn15_Pos 15 /*!< SCT OUTPUTCLR1: CLRn15 Position */ -#define SCT_OUTPUTCLR1_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos) /*!< SCT OUTPUTCLR1: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET2 ----------------------------------------- -#define SCT_OUTPUTSET2_SETn0_Pos 0 /*!< SCT OUTPUTSET2: SETn0 Position */ -#define SCT_OUTPUTSET2_SETn0_Msk (0x01UL << SCT_OUTPUTSET2_SETn0_Pos) /*!< SCT OUTPUTSET2: SETn0 Mask */ -#define SCT_OUTPUTSET2_SETn1_Pos 1 /*!< SCT OUTPUTSET2: SETn1 Position */ -#define SCT_OUTPUTSET2_SETn1_Msk (0x01UL << SCT_OUTPUTSET2_SETn1_Pos) /*!< SCT OUTPUTSET2: SETn1 Mask */ -#define SCT_OUTPUTSET2_SETn2_Pos 2 /*!< SCT OUTPUTSET2: SETn2 Position */ -#define SCT_OUTPUTSET2_SETn2_Msk (0x01UL << SCT_OUTPUTSET2_SETn2_Pos) /*!< SCT OUTPUTSET2: SETn2 Mask */ -#define SCT_OUTPUTSET2_SETn3_Pos 3 /*!< SCT OUTPUTSET2: SETn3 Position */ -#define SCT_OUTPUTSET2_SETn3_Msk (0x01UL << SCT_OUTPUTSET2_SETn3_Pos) /*!< SCT OUTPUTSET2: SETn3 Mask */ -#define SCT_OUTPUTSET2_SETn4_Pos 4 /*!< SCT OUTPUTSET2: SETn4 Position */ -#define SCT_OUTPUTSET2_SETn4_Msk (0x01UL << SCT_OUTPUTSET2_SETn4_Pos) /*!< SCT OUTPUTSET2: SETn4 Mask */ -#define SCT_OUTPUTSET2_SETn5_Pos 5 /*!< SCT OUTPUTSET2: SETn5 Position */ -#define SCT_OUTPUTSET2_SETn5_Msk (0x01UL << SCT_OUTPUTSET2_SETn5_Pos) /*!< SCT OUTPUTSET2: SETn5 Mask */ -#define SCT_OUTPUTSET2_SETn6_Pos 6 /*!< SCT OUTPUTSET2: SETn6 Position */ -#define SCT_OUTPUTSET2_SETn6_Msk (0x01UL << SCT_OUTPUTSET2_SETn6_Pos) /*!< SCT OUTPUTSET2: SETn6 Mask */ -#define SCT_OUTPUTSET2_SETn7_Pos 7 /*!< SCT OUTPUTSET2: SETn7 Position */ -#define SCT_OUTPUTSET2_SETn7_Msk (0x01UL << SCT_OUTPUTSET2_SETn7_Pos) /*!< SCT OUTPUTSET2: SETn7 Mask */ -#define SCT_OUTPUTSET2_SETn8_Pos 8 /*!< SCT OUTPUTSET2: SETn8 Position */ -#define SCT_OUTPUTSET2_SETn8_Msk (0x01UL << SCT_OUTPUTSET2_SETn8_Pos) /*!< SCT OUTPUTSET2: SETn8 Mask */ -#define SCT_OUTPUTSET2_SETn9_Pos 9 /*!< SCT OUTPUTSET2: SETn9 Position */ -#define SCT_OUTPUTSET2_SETn9_Msk (0x01UL << SCT_OUTPUTSET2_SETn9_Pos) /*!< SCT OUTPUTSET2: SETn9 Mask */ -#define SCT_OUTPUTSET2_SETn10_Pos 10 /*!< SCT OUTPUTSET2: SETn10 Position */ -#define SCT_OUTPUTSET2_SETn10_Msk (0x01UL << SCT_OUTPUTSET2_SETn10_Pos) /*!< SCT OUTPUTSET2: SETn10 Mask */ -#define SCT_OUTPUTSET2_SETn11_Pos 11 /*!< SCT OUTPUTSET2: SETn11 Position */ -#define SCT_OUTPUTSET2_SETn11_Msk (0x01UL << SCT_OUTPUTSET2_SETn11_Pos) /*!< SCT OUTPUTSET2: SETn11 Mask */ -#define SCT_OUTPUTSET2_SETn12_Pos 12 /*!< SCT OUTPUTSET2: SETn12 Position */ -#define SCT_OUTPUTSET2_SETn12_Msk (0x01UL << SCT_OUTPUTSET2_SETn12_Pos) /*!< SCT OUTPUTSET2: SETn12 Mask */ -#define SCT_OUTPUTSET2_SETn13_Pos 13 /*!< SCT OUTPUTSET2: SETn13 Position */ -#define SCT_OUTPUTSET2_SETn13_Msk (0x01UL << SCT_OUTPUTSET2_SETn13_Pos) /*!< SCT OUTPUTSET2: SETn13 Mask */ -#define SCT_OUTPUTSET2_SETn14_Pos 14 /*!< SCT OUTPUTSET2: SETn14 Position */ -#define SCT_OUTPUTSET2_SETn14_Msk (0x01UL << SCT_OUTPUTSET2_SETn14_Pos) /*!< SCT OUTPUTSET2: SETn14 Mask */ -#define SCT_OUTPUTSET2_SETn15_Pos 15 /*!< SCT OUTPUTSET2: SETn15 Position */ -#define SCT_OUTPUTSET2_SETn15_Msk (0x01UL << SCT_OUTPUTSET2_SETn15_Pos) /*!< SCT OUTPUTSET2: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR2 ----------------------------------------- -#define SCT_OUTPUTCLR2_CLRn0_Pos 0 /*!< SCT OUTPUTCLR2: CLRn0 Position */ -#define SCT_OUTPUTCLR2_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos) /*!< SCT OUTPUTCLR2: CLRn0 Mask */ -#define SCT_OUTPUTCLR2_CLRn1_Pos 1 /*!< SCT OUTPUTCLR2: CLRn1 Position */ -#define SCT_OUTPUTCLR2_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos) /*!< SCT OUTPUTCLR2: CLRn1 Mask */ -#define SCT_OUTPUTCLR2_CLRn2_Pos 2 /*!< SCT OUTPUTCLR2: CLRn2 Position */ -#define SCT_OUTPUTCLR2_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos) /*!< SCT OUTPUTCLR2: CLRn2 Mask */ -#define SCT_OUTPUTCLR2_CLRn3_Pos 3 /*!< SCT OUTPUTCLR2: CLRn3 Position */ -#define SCT_OUTPUTCLR2_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos) /*!< SCT OUTPUTCLR2: CLRn3 Mask */ -#define SCT_OUTPUTCLR2_CLRn4_Pos 4 /*!< SCT OUTPUTCLR2: CLRn4 Position */ -#define SCT_OUTPUTCLR2_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos) /*!< SCT OUTPUTCLR2: CLRn4 Mask */ -#define SCT_OUTPUTCLR2_CLRn5_Pos 5 /*!< SCT OUTPUTCLR2: CLRn5 Position */ -#define SCT_OUTPUTCLR2_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos) /*!< SCT OUTPUTCLR2: CLRn5 Mask */ -#define SCT_OUTPUTCLR2_CLRn6_Pos 6 /*!< SCT OUTPUTCLR2: CLRn6 Position */ -#define SCT_OUTPUTCLR2_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos) /*!< SCT OUTPUTCLR2: CLRn6 Mask */ -#define SCT_OUTPUTCLR2_CLRn7_Pos 7 /*!< SCT OUTPUTCLR2: CLRn7 Position */ -#define SCT_OUTPUTCLR2_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos) /*!< SCT OUTPUTCLR2: CLRn7 Mask */ -#define SCT_OUTPUTCLR2_CLRn8_Pos 8 /*!< SCT OUTPUTCLR2: CLRn8 Position */ -#define SCT_OUTPUTCLR2_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos) /*!< SCT OUTPUTCLR2: CLRn8 Mask */ -#define SCT_OUTPUTCLR2_CLRn9_Pos 9 /*!< SCT OUTPUTCLR2: CLRn9 Position */ -#define SCT_OUTPUTCLR2_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos) /*!< SCT OUTPUTCLR2: CLRn9 Mask */ -#define SCT_OUTPUTCLR2_CLRn10_Pos 10 /*!< SCT OUTPUTCLR2: CLRn10 Position */ -#define SCT_OUTPUTCLR2_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos) /*!< SCT OUTPUTCLR2: CLRn10 Mask */ -#define SCT_OUTPUTCLR2_CLRn11_Pos 11 /*!< SCT OUTPUTCLR2: CLRn11 Position */ -#define SCT_OUTPUTCLR2_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos) /*!< SCT OUTPUTCLR2: CLRn11 Mask */ -#define SCT_OUTPUTCLR2_CLRn12_Pos 12 /*!< SCT OUTPUTCLR2: CLRn12 Position */ -#define SCT_OUTPUTCLR2_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos) /*!< SCT OUTPUTCLR2: CLRn12 Mask */ -#define SCT_OUTPUTCLR2_CLRn13_Pos 13 /*!< SCT OUTPUTCLR2: CLRn13 Position */ -#define SCT_OUTPUTCLR2_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos) /*!< SCT OUTPUTCLR2: CLRn13 Mask */ -#define SCT_OUTPUTCLR2_CLRn14_Pos 14 /*!< SCT OUTPUTCLR2: CLRn14 Position */ -#define SCT_OUTPUTCLR2_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos) /*!< SCT OUTPUTCLR2: CLRn14 Mask */ -#define SCT_OUTPUTCLR2_CLRn15_Pos 15 /*!< SCT OUTPUTCLR2: CLRn15 Position */ -#define SCT_OUTPUTCLR2_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos) /*!< SCT OUTPUTCLR2: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET3 ----------------------------------------- -#define SCT_OUTPUTSET3_SETn0_Pos 0 /*!< SCT OUTPUTSET3: SETn0 Position */ -#define SCT_OUTPUTSET3_SETn0_Msk (0x01UL << SCT_OUTPUTSET3_SETn0_Pos) /*!< SCT OUTPUTSET3: SETn0 Mask */ -#define SCT_OUTPUTSET3_SETn1_Pos 1 /*!< SCT OUTPUTSET3: SETn1 Position */ -#define SCT_OUTPUTSET3_SETn1_Msk (0x01UL << SCT_OUTPUTSET3_SETn1_Pos) /*!< SCT OUTPUTSET3: SETn1 Mask */ -#define SCT_OUTPUTSET3_SETn2_Pos 2 /*!< SCT OUTPUTSET3: SETn2 Position */ -#define SCT_OUTPUTSET3_SETn2_Msk (0x01UL << SCT_OUTPUTSET3_SETn2_Pos) /*!< SCT OUTPUTSET3: SETn2 Mask */ -#define SCT_OUTPUTSET3_SETn3_Pos 3 /*!< SCT OUTPUTSET3: SETn3 Position */ -#define SCT_OUTPUTSET3_SETn3_Msk (0x01UL << SCT_OUTPUTSET3_SETn3_Pos) /*!< SCT OUTPUTSET3: SETn3 Mask */ -#define SCT_OUTPUTSET3_SETn4_Pos 4 /*!< SCT OUTPUTSET3: SETn4 Position */ -#define SCT_OUTPUTSET3_SETn4_Msk (0x01UL << SCT_OUTPUTSET3_SETn4_Pos) /*!< SCT OUTPUTSET3: SETn4 Mask */ -#define SCT_OUTPUTSET3_SETn5_Pos 5 /*!< SCT OUTPUTSET3: SETn5 Position */ -#define SCT_OUTPUTSET3_SETn5_Msk (0x01UL << SCT_OUTPUTSET3_SETn5_Pos) /*!< SCT OUTPUTSET3: SETn5 Mask */ -#define SCT_OUTPUTSET3_SETn6_Pos 6 /*!< SCT OUTPUTSET3: SETn6 Position */ -#define SCT_OUTPUTSET3_SETn6_Msk (0x01UL << SCT_OUTPUTSET3_SETn6_Pos) /*!< SCT OUTPUTSET3: SETn6 Mask */ -#define SCT_OUTPUTSET3_SETn7_Pos 7 /*!< SCT OUTPUTSET3: SETn7 Position */ -#define SCT_OUTPUTSET3_SETn7_Msk (0x01UL << SCT_OUTPUTSET3_SETn7_Pos) /*!< SCT OUTPUTSET3: SETn7 Mask */ -#define SCT_OUTPUTSET3_SETn8_Pos 8 /*!< SCT OUTPUTSET3: SETn8 Position */ -#define SCT_OUTPUTSET3_SETn8_Msk (0x01UL << SCT_OUTPUTSET3_SETn8_Pos) /*!< SCT OUTPUTSET3: SETn8 Mask */ -#define SCT_OUTPUTSET3_SETn9_Pos 9 /*!< SCT OUTPUTSET3: SETn9 Position */ -#define SCT_OUTPUTSET3_SETn9_Msk (0x01UL << SCT_OUTPUTSET3_SETn9_Pos) /*!< SCT OUTPUTSET3: SETn9 Mask */ -#define SCT_OUTPUTSET3_SETn10_Pos 10 /*!< SCT OUTPUTSET3: SETn10 Position */ -#define SCT_OUTPUTSET3_SETn10_Msk (0x01UL << SCT_OUTPUTSET3_SETn10_Pos) /*!< SCT OUTPUTSET3: SETn10 Mask */ -#define SCT_OUTPUTSET3_SETn11_Pos 11 /*!< SCT OUTPUTSET3: SETn11 Position */ -#define SCT_OUTPUTSET3_SETn11_Msk (0x01UL << SCT_OUTPUTSET3_SETn11_Pos) /*!< SCT OUTPUTSET3: SETn11 Mask */ -#define SCT_OUTPUTSET3_SETn12_Pos 12 /*!< SCT OUTPUTSET3: SETn12 Position */ -#define SCT_OUTPUTSET3_SETn12_Msk (0x01UL << SCT_OUTPUTSET3_SETn12_Pos) /*!< SCT OUTPUTSET3: SETn12 Mask */ -#define SCT_OUTPUTSET3_SETn13_Pos 13 /*!< SCT OUTPUTSET3: SETn13 Position */ -#define SCT_OUTPUTSET3_SETn13_Msk (0x01UL << SCT_OUTPUTSET3_SETn13_Pos) /*!< SCT OUTPUTSET3: SETn13 Mask */ -#define SCT_OUTPUTSET3_SETn14_Pos 14 /*!< SCT OUTPUTSET3: SETn14 Position */ -#define SCT_OUTPUTSET3_SETn14_Msk (0x01UL << SCT_OUTPUTSET3_SETn14_Pos) /*!< SCT OUTPUTSET3: SETn14 Mask */ -#define SCT_OUTPUTSET3_SETn15_Pos 15 /*!< SCT OUTPUTSET3: SETn15 Position */ -#define SCT_OUTPUTSET3_SETn15_Msk (0x01UL << SCT_OUTPUTSET3_SETn15_Pos) /*!< SCT OUTPUTSET3: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR3 ----------------------------------------- -#define SCT_OUTPUTCLR3_CLRn0_Pos 0 /*!< SCT OUTPUTCLR3: CLRn0 Position */ -#define SCT_OUTPUTCLR3_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos) /*!< SCT OUTPUTCLR3: CLRn0 Mask */ -#define SCT_OUTPUTCLR3_CLRn1_Pos 1 /*!< SCT OUTPUTCLR3: CLRn1 Position */ -#define SCT_OUTPUTCLR3_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos) /*!< SCT OUTPUTCLR3: CLRn1 Mask */ -#define SCT_OUTPUTCLR3_CLRn2_Pos 2 /*!< SCT OUTPUTCLR3: CLRn2 Position */ -#define SCT_OUTPUTCLR3_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos) /*!< SCT OUTPUTCLR3: CLRn2 Mask */ -#define SCT_OUTPUTCLR3_CLRn3_Pos 3 /*!< SCT OUTPUTCLR3: CLRn3 Position */ -#define SCT_OUTPUTCLR3_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos) /*!< SCT OUTPUTCLR3: CLRn3 Mask */ -#define SCT_OUTPUTCLR3_CLRn4_Pos 4 /*!< SCT OUTPUTCLR3: CLRn4 Position */ -#define SCT_OUTPUTCLR3_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos) /*!< SCT OUTPUTCLR3: CLRn4 Mask */ -#define SCT_OUTPUTCLR3_CLRn5_Pos 5 /*!< SCT OUTPUTCLR3: CLRn5 Position */ -#define SCT_OUTPUTCLR3_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos) /*!< SCT OUTPUTCLR3: CLRn5 Mask */ -#define SCT_OUTPUTCLR3_CLRn6_Pos 6 /*!< SCT OUTPUTCLR3: CLRn6 Position */ -#define SCT_OUTPUTCLR3_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos) /*!< SCT OUTPUTCLR3: CLRn6 Mask */ -#define SCT_OUTPUTCLR3_CLRn7_Pos 7 /*!< SCT OUTPUTCLR3: CLRn7 Position */ -#define SCT_OUTPUTCLR3_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos) /*!< SCT OUTPUTCLR3: CLRn7 Mask */ -#define SCT_OUTPUTCLR3_CLRn8_Pos 8 /*!< SCT OUTPUTCLR3: CLRn8 Position */ -#define SCT_OUTPUTCLR3_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos) /*!< SCT OUTPUTCLR3: CLRn8 Mask */ -#define SCT_OUTPUTCLR3_CLRn9_Pos 9 /*!< SCT OUTPUTCLR3: CLRn9 Position */ -#define SCT_OUTPUTCLR3_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos) /*!< SCT OUTPUTCLR3: CLRn9 Mask */ -#define SCT_OUTPUTCLR3_CLRn10_Pos 10 /*!< SCT OUTPUTCLR3: CLRn10 Position */ -#define SCT_OUTPUTCLR3_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos) /*!< SCT OUTPUTCLR3: CLRn10 Mask */ -#define SCT_OUTPUTCLR3_CLRn11_Pos 11 /*!< SCT OUTPUTCLR3: CLRn11 Position */ -#define SCT_OUTPUTCLR3_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos) /*!< SCT OUTPUTCLR3: CLRn11 Mask */ -#define SCT_OUTPUTCLR3_CLRn12_Pos 12 /*!< SCT OUTPUTCLR3: CLRn12 Position */ -#define SCT_OUTPUTCLR3_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos) /*!< SCT OUTPUTCLR3: CLRn12 Mask */ -#define SCT_OUTPUTCLR3_CLRn13_Pos 13 /*!< SCT OUTPUTCLR3: CLRn13 Position */ -#define SCT_OUTPUTCLR3_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos) /*!< SCT OUTPUTCLR3: CLRn13 Mask */ -#define SCT_OUTPUTCLR3_CLRn14_Pos 14 /*!< SCT OUTPUTCLR3: CLRn14 Position */ -#define SCT_OUTPUTCLR3_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos) /*!< SCT OUTPUTCLR3: CLRn14 Mask */ -#define SCT_OUTPUTCLR3_CLRn15_Pos 15 /*!< SCT OUTPUTCLR3: CLRn15 Position */ -#define SCT_OUTPUTCLR3_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos) /*!< SCT OUTPUTCLR3: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET4 ----------------------------------------- -#define SCT_OUTPUTSET4_SETn0_Pos 0 /*!< SCT OUTPUTSET4: SETn0 Position */ -#define SCT_OUTPUTSET4_SETn0_Msk (0x01UL << SCT_OUTPUTSET4_SETn0_Pos) /*!< SCT OUTPUTSET4: SETn0 Mask */ -#define SCT_OUTPUTSET4_SETn1_Pos 1 /*!< SCT OUTPUTSET4: SETn1 Position */ -#define SCT_OUTPUTSET4_SETn1_Msk (0x01UL << SCT_OUTPUTSET4_SETn1_Pos) /*!< SCT OUTPUTSET4: SETn1 Mask */ -#define SCT_OUTPUTSET4_SETn2_Pos 2 /*!< SCT OUTPUTSET4: SETn2 Position */ -#define SCT_OUTPUTSET4_SETn2_Msk (0x01UL << SCT_OUTPUTSET4_SETn2_Pos) /*!< SCT OUTPUTSET4: SETn2 Mask */ -#define SCT_OUTPUTSET4_SETn3_Pos 3 /*!< SCT OUTPUTSET4: SETn3 Position */ -#define SCT_OUTPUTSET4_SETn3_Msk (0x01UL << SCT_OUTPUTSET4_SETn3_Pos) /*!< SCT OUTPUTSET4: SETn3 Mask */ -#define SCT_OUTPUTSET4_SETn4_Pos 4 /*!< SCT OUTPUTSET4: SETn4 Position */ -#define SCT_OUTPUTSET4_SETn4_Msk (0x01UL << SCT_OUTPUTSET4_SETn4_Pos) /*!< SCT OUTPUTSET4: SETn4 Mask */ -#define SCT_OUTPUTSET4_SETn5_Pos 5 /*!< SCT OUTPUTSET4: SETn5 Position */ -#define SCT_OUTPUTSET4_SETn5_Msk (0x01UL << SCT_OUTPUTSET4_SETn5_Pos) /*!< SCT OUTPUTSET4: SETn5 Mask */ -#define SCT_OUTPUTSET4_SETn6_Pos 6 /*!< SCT OUTPUTSET4: SETn6 Position */ -#define SCT_OUTPUTSET4_SETn6_Msk (0x01UL << SCT_OUTPUTSET4_SETn6_Pos) /*!< SCT OUTPUTSET4: SETn6 Mask */ -#define SCT_OUTPUTSET4_SETn7_Pos 7 /*!< SCT OUTPUTSET4: SETn7 Position */ -#define SCT_OUTPUTSET4_SETn7_Msk (0x01UL << SCT_OUTPUTSET4_SETn7_Pos) /*!< SCT OUTPUTSET4: SETn7 Mask */ -#define SCT_OUTPUTSET4_SETn8_Pos 8 /*!< SCT OUTPUTSET4: SETn8 Position */ -#define SCT_OUTPUTSET4_SETn8_Msk (0x01UL << SCT_OUTPUTSET4_SETn8_Pos) /*!< SCT OUTPUTSET4: SETn8 Mask */ -#define SCT_OUTPUTSET4_SETn9_Pos 9 /*!< SCT OUTPUTSET4: SETn9 Position */ -#define SCT_OUTPUTSET4_SETn9_Msk (0x01UL << SCT_OUTPUTSET4_SETn9_Pos) /*!< SCT OUTPUTSET4: SETn9 Mask */ -#define SCT_OUTPUTSET4_SETn10_Pos 10 /*!< SCT OUTPUTSET4: SETn10 Position */ -#define SCT_OUTPUTSET4_SETn10_Msk (0x01UL << SCT_OUTPUTSET4_SETn10_Pos) /*!< SCT OUTPUTSET4: SETn10 Mask */ -#define SCT_OUTPUTSET4_SETn11_Pos 11 /*!< SCT OUTPUTSET4: SETn11 Position */ -#define SCT_OUTPUTSET4_SETn11_Msk (0x01UL << SCT_OUTPUTSET4_SETn11_Pos) /*!< SCT OUTPUTSET4: SETn11 Mask */ -#define SCT_OUTPUTSET4_SETn12_Pos 12 /*!< SCT OUTPUTSET4: SETn12 Position */ -#define SCT_OUTPUTSET4_SETn12_Msk (0x01UL << SCT_OUTPUTSET4_SETn12_Pos) /*!< SCT OUTPUTSET4: SETn12 Mask */ -#define SCT_OUTPUTSET4_SETn13_Pos 13 /*!< SCT OUTPUTSET4: SETn13 Position */ -#define SCT_OUTPUTSET4_SETn13_Msk (0x01UL << SCT_OUTPUTSET4_SETn13_Pos) /*!< SCT OUTPUTSET4: SETn13 Mask */ -#define SCT_OUTPUTSET4_SETn14_Pos 14 /*!< SCT OUTPUTSET4: SETn14 Position */ -#define SCT_OUTPUTSET4_SETn14_Msk (0x01UL << SCT_OUTPUTSET4_SETn14_Pos) /*!< SCT OUTPUTSET4: SETn14 Mask */ -#define SCT_OUTPUTSET4_SETn15_Pos 15 /*!< SCT OUTPUTSET4: SETn15 Position */ -#define SCT_OUTPUTSET4_SETn15_Msk (0x01UL << SCT_OUTPUTSET4_SETn15_Pos) /*!< SCT OUTPUTSET4: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR4 ----------------------------------------- -#define SCT_OUTPUTCLR4_CLRn0_Pos 0 /*!< SCT OUTPUTCLR4: CLRn0 Position */ -#define SCT_OUTPUTCLR4_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos) /*!< SCT OUTPUTCLR4: CLRn0 Mask */ -#define SCT_OUTPUTCLR4_CLRn1_Pos 1 /*!< SCT OUTPUTCLR4: CLRn1 Position */ -#define SCT_OUTPUTCLR4_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos) /*!< SCT OUTPUTCLR4: CLRn1 Mask */ -#define SCT_OUTPUTCLR4_CLRn2_Pos 2 /*!< SCT OUTPUTCLR4: CLRn2 Position */ -#define SCT_OUTPUTCLR4_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos) /*!< SCT OUTPUTCLR4: CLRn2 Mask */ -#define SCT_OUTPUTCLR4_CLRn3_Pos 3 /*!< SCT OUTPUTCLR4: CLRn3 Position */ -#define SCT_OUTPUTCLR4_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos) /*!< SCT OUTPUTCLR4: CLRn3 Mask */ -#define SCT_OUTPUTCLR4_CLRn4_Pos 4 /*!< SCT OUTPUTCLR4: CLRn4 Position */ -#define SCT_OUTPUTCLR4_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos) /*!< SCT OUTPUTCLR4: CLRn4 Mask */ -#define SCT_OUTPUTCLR4_CLRn5_Pos 5 /*!< SCT OUTPUTCLR4: CLRn5 Position */ -#define SCT_OUTPUTCLR4_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos) /*!< SCT OUTPUTCLR4: CLRn5 Mask */ -#define SCT_OUTPUTCLR4_CLRn6_Pos 6 /*!< SCT OUTPUTCLR4: CLRn6 Position */ -#define SCT_OUTPUTCLR4_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos) /*!< SCT OUTPUTCLR4: CLRn6 Mask */ -#define SCT_OUTPUTCLR4_CLRn7_Pos 7 /*!< SCT OUTPUTCLR4: CLRn7 Position */ -#define SCT_OUTPUTCLR4_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos) /*!< SCT OUTPUTCLR4: CLRn7 Mask */ -#define SCT_OUTPUTCLR4_CLRn8_Pos 8 /*!< SCT OUTPUTCLR4: CLRn8 Position */ -#define SCT_OUTPUTCLR4_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos) /*!< SCT OUTPUTCLR4: CLRn8 Mask */ -#define SCT_OUTPUTCLR4_CLRn9_Pos 9 /*!< SCT OUTPUTCLR4: CLRn9 Position */ -#define SCT_OUTPUTCLR4_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos) /*!< SCT OUTPUTCLR4: CLRn9 Mask */ -#define SCT_OUTPUTCLR4_CLRn10_Pos 10 /*!< SCT OUTPUTCLR4: CLRn10 Position */ -#define SCT_OUTPUTCLR4_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos) /*!< SCT OUTPUTCLR4: CLRn10 Mask */ -#define SCT_OUTPUTCLR4_CLRn11_Pos 11 /*!< SCT OUTPUTCLR4: CLRn11 Position */ -#define SCT_OUTPUTCLR4_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos) /*!< SCT OUTPUTCLR4: CLRn11 Mask */ -#define SCT_OUTPUTCLR4_CLRn12_Pos 12 /*!< SCT OUTPUTCLR4: CLRn12 Position */ -#define SCT_OUTPUTCLR4_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos) /*!< SCT OUTPUTCLR4: CLRn12 Mask */ -#define SCT_OUTPUTCLR4_CLRn13_Pos 13 /*!< SCT OUTPUTCLR4: CLRn13 Position */ -#define SCT_OUTPUTCLR4_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos) /*!< SCT OUTPUTCLR4: CLRn13 Mask */ -#define SCT_OUTPUTCLR4_CLRn14_Pos 14 /*!< SCT OUTPUTCLR4: CLRn14 Position */ -#define SCT_OUTPUTCLR4_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos) /*!< SCT OUTPUTCLR4: CLRn14 Mask */ -#define SCT_OUTPUTCLR4_CLRn15_Pos 15 /*!< SCT OUTPUTCLR4: CLRn15 Position */ -#define SCT_OUTPUTCLR4_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos) /*!< SCT OUTPUTCLR4: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET5 ----------------------------------------- -#define SCT_OUTPUTSET5_SETn0_Pos 0 /*!< SCT OUTPUTSET5: SETn0 Position */ -#define SCT_OUTPUTSET5_SETn0_Msk (0x01UL << SCT_OUTPUTSET5_SETn0_Pos) /*!< SCT OUTPUTSET5: SETn0 Mask */ -#define SCT_OUTPUTSET5_SETn1_Pos 1 /*!< SCT OUTPUTSET5: SETn1 Position */ -#define SCT_OUTPUTSET5_SETn1_Msk (0x01UL << SCT_OUTPUTSET5_SETn1_Pos) /*!< SCT OUTPUTSET5: SETn1 Mask */ -#define SCT_OUTPUTSET5_SETn2_Pos 2 /*!< SCT OUTPUTSET5: SETn2 Position */ -#define SCT_OUTPUTSET5_SETn2_Msk (0x01UL << SCT_OUTPUTSET5_SETn2_Pos) /*!< SCT OUTPUTSET5: SETn2 Mask */ -#define SCT_OUTPUTSET5_SETn3_Pos 3 /*!< SCT OUTPUTSET5: SETn3 Position */ -#define SCT_OUTPUTSET5_SETn3_Msk (0x01UL << SCT_OUTPUTSET5_SETn3_Pos) /*!< SCT OUTPUTSET5: SETn3 Mask */ -#define SCT_OUTPUTSET5_SETn4_Pos 4 /*!< SCT OUTPUTSET5: SETn4 Position */ -#define SCT_OUTPUTSET5_SETn4_Msk (0x01UL << SCT_OUTPUTSET5_SETn4_Pos) /*!< SCT OUTPUTSET5: SETn4 Mask */ -#define SCT_OUTPUTSET5_SETn5_Pos 5 /*!< SCT OUTPUTSET5: SETn5 Position */ -#define SCT_OUTPUTSET5_SETn5_Msk (0x01UL << SCT_OUTPUTSET5_SETn5_Pos) /*!< SCT OUTPUTSET5: SETn5 Mask */ -#define SCT_OUTPUTSET5_SETn6_Pos 6 /*!< SCT OUTPUTSET5: SETn6 Position */ -#define SCT_OUTPUTSET5_SETn6_Msk (0x01UL << SCT_OUTPUTSET5_SETn6_Pos) /*!< SCT OUTPUTSET5: SETn6 Mask */ -#define SCT_OUTPUTSET5_SETn7_Pos 7 /*!< SCT OUTPUTSET5: SETn7 Position */ -#define SCT_OUTPUTSET5_SETn7_Msk (0x01UL << SCT_OUTPUTSET5_SETn7_Pos) /*!< SCT OUTPUTSET5: SETn7 Mask */ -#define SCT_OUTPUTSET5_SETn8_Pos 8 /*!< SCT OUTPUTSET5: SETn8 Position */ -#define SCT_OUTPUTSET5_SETn8_Msk (0x01UL << SCT_OUTPUTSET5_SETn8_Pos) /*!< SCT OUTPUTSET5: SETn8 Mask */ -#define SCT_OUTPUTSET5_SETn9_Pos 9 /*!< SCT OUTPUTSET5: SETn9 Position */ -#define SCT_OUTPUTSET5_SETn9_Msk (0x01UL << SCT_OUTPUTSET5_SETn9_Pos) /*!< SCT OUTPUTSET5: SETn9 Mask */ -#define SCT_OUTPUTSET5_SETn10_Pos 10 /*!< SCT OUTPUTSET5: SETn10 Position */ -#define SCT_OUTPUTSET5_SETn10_Msk (0x01UL << SCT_OUTPUTSET5_SETn10_Pos) /*!< SCT OUTPUTSET5: SETn10 Mask */ -#define SCT_OUTPUTSET5_SETn11_Pos 11 /*!< SCT OUTPUTSET5: SETn11 Position */ -#define SCT_OUTPUTSET5_SETn11_Msk (0x01UL << SCT_OUTPUTSET5_SETn11_Pos) /*!< SCT OUTPUTSET5: SETn11 Mask */ -#define SCT_OUTPUTSET5_SETn12_Pos 12 /*!< SCT OUTPUTSET5: SETn12 Position */ -#define SCT_OUTPUTSET5_SETn12_Msk (0x01UL << SCT_OUTPUTSET5_SETn12_Pos) /*!< SCT OUTPUTSET5: SETn12 Mask */ -#define SCT_OUTPUTSET5_SETn13_Pos 13 /*!< SCT OUTPUTSET5: SETn13 Position */ -#define SCT_OUTPUTSET5_SETn13_Msk (0x01UL << SCT_OUTPUTSET5_SETn13_Pos) /*!< SCT OUTPUTSET5: SETn13 Mask */ -#define SCT_OUTPUTSET5_SETn14_Pos 14 /*!< SCT OUTPUTSET5: SETn14 Position */ -#define SCT_OUTPUTSET5_SETn14_Msk (0x01UL << SCT_OUTPUTSET5_SETn14_Pos) /*!< SCT OUTPUTSET5: SETn14 Mask */ -#define SCT_OUTPUTSET5_SETn15_Pos 15 /*!< SCT OUTPUTSET5: SETn15 Position */ -#define SCT_OUTPUTSET5_SETn15_Msk (0x01UL << SCT_OUTPUTSET5_SETn15_Pos) /*!< SCT OUTPUTSET5: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR5 ----------------------------------------- -#define SCT_OUTPUTCLR5_CLRn0_Pos 0 /*!< SCT OUTPUTCLR5: CLRn0 Position */ -#define SCT_OUTPUTCLR5_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos) /*!< SCT OUTPUTCLR5: CLRn0 Mask */ -#define SCT_OUTPUTCLR5_CLRn1_Pos 1 /*!< SCT OUTPUTCLR5: CLRn1 Position */ -#define SCT_OUTPUTCLR5_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos) /*!< SCT OUTPUTCLR5: CLRn1 Mask */ -#define SCT_OUTPUTCLR5_CLRn2_Pos 2 /*!< SCT OUTPUTCLR5: CLRn2 Position */ -#define SCT_OUTPUTCLR5_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos) /*!< SCT OUTPUTCLR5: CLRn2 Mask */ -#define SCT_OUTPUTCLR5_CLRn3_Pos 3 /*!< SCT OUTPUTCLR5: CLRn3 Position */ -#define SCT_OUTPUTCLR5_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos) /*!< SCT OUTPUTCLR5: CLRn3 Mask */ -#define SCT_OUTPUTCLR5_CLRn4_Pos 4 /*!< SCT OUTPUTCLR5: CLRn4 Position */ -#define SCT_OUTPUTCLR5_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos) /*!< SCT OUTPUTCLR5: CLRn4 Mask */ -#define SCT_OUTPUTCLR5_CLRn5_Pos 5 /*!< SCT OUTPUTCLR5: CLRn5 Position */ -#define SCT_OUTPUTCLR5_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos) /*!< SCT OUTPUTCLR5: CLRn5 Mask */ -#define SCT_OUTPUTCLR5_CLRn6_Pos 6 /*!< SCT OUTPUTCLR5: CLRn6 Position */ -#define SCT_OUTPUTCLR5_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos) /*!< SCT OUTPUTCLR5: CLRn6 Mask */ -#define SCT_OUTPUTCLR5_CLRn7_Pos 7 /*!< SCT OUTPUTCLR5: CLRn7 Position */ -#define SCT_OUTPUTCLR5_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos) /*!< SCT OUTPUTCLR5: CLRn7 Mask */ -#define SCT_OUTPUTCLR5_CLRn8_Pos 8 /*!< SCT OUTPUTCLR5: CLRn8 Position */ -#define SCT_OUTPUTCLR5_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos) /*!< SCT OUTPUTCLR5: CLRn8 Mask */ -#define SCT_OUTPUTCLR5_CLRn9_Pos 9 /*!< SCT OUTPUTCLR5: CLRn9 Position */ -#define SCT_OUTPUTCLR5_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos) /*!< SCT OUTPUTCLR5: CLRn9 Mask */ -#define SCT_OUTPUTCLR5_CLRn10_Pos 10 /*!< SCT OUTPUTCLR5: CLRn10 Position */ -#define SCT_OUTPUTCLR5_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos) /*!< SCT OUTPUTCLR5: CLRn10 Mask */ -#define SCT_OUTPUTCLR5_CLRn11_Pos 11 /*!< SCT OUTPUTCLR5: CLRn11 Position */ -#define SCT_OUTPUTCLR5_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos) /*!< SCT OUTPUTCLR5: CLRn11 Mask */ -#define SCT_OUTPUTCLR5_CLRn12_Pos 12 /*!< SCT OUTPUTCLR5: CLRn12 Position */ -#define SCT_OUTPUTCLR5_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos) /*!< SCT OUTPUTCLR5: CLRn12 Mask */ -#define SCT_OUTPUTCLR5_CLRn13_Pos 13 /*!< SCT OUTPUTCLR5: CLRn13 Position */ -#define SCT_OUTPUTCLR5_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos) /*!< SCT OUTPUTCLR5: CLRn13 Mask */ -#define SCT_OUTPUTCLR5_CLRn14_Pos 14 /*!< SCT OUTPUTCLR5: CLRn14 Position */ -#define SCT_OUTPUTCLR5_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos) /*!< SCT OUTPUTCLR5: CLRn14 Mask */ -#define SCT_OUTPUTCLR5_CLRn15_Pos 15 /*!< SCT OUTPUTCLR5: CLRn15 Position */ -#define SCT_OUTPUTCLR5_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos) /*!< SCT OUTPUTCLR5: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET6 ----------------------------------------- -#define SCT_OUTPUTSET6_SETn0_Pos 0 /*!< SCT OUTPUTSET6: SETn0 Position */ -#define SCT_OUTPUTSET6_SETn0_Msk (0x01UL << SCT_OUTPUTSET6_SETn0_Pos) /*!< SCT OUTPUTSET6: SETn0 Mask */ -#define SCT_OUTPUTSET6_SETn1_Pos 1 /*!< SCT OUTPUTSET6: SETn1 Position */ -#define SCT_OUTPUTSET6_SETn1_Msk (0x01UL << SCT_OUTPUTSET6_SETn1_Pos) /*!< SCT OUTPUTSET6: SETn1 Mask */ -#define SCT_OUTPUTSET6_SETn2_Pos 2 /*!< SCT OUTPUTSET6: SETn2 Position */ -#define SCT_OUTPUTSET6_SETn2_Msk (0x01UL << SCT_OUTPUTSET6_SETn2_Pos) /*!< SCT OUTPUTSET6: SETn2 Mask */ -#define SCT_OUTPUTSET6_SETn3_Pos 3 /*!< SCT OUTPUTSET6: SETn3 Position */ -#define SCT_OUTPUTSET6_SETn3_Msk (0x01UL << SCT_OUTPUTSET6_SETn3_Pos) /*!< SCT OUTPUTSET6: SETn3 Mask */ -#define SCT_OUTPUTSET6_SETn4_Pos 4 /*!< SCT OUTPUTSET6: SETn4 Position */ -#define SCT_OUTPUTSET6_SETn4_Msk (0x01UL << SCT_OUTPUTSET6_SETn4_Pos) /*!< SCT OUTPUTSET6: SETn4 Mask */ -#define SCT_OUTPUTSET6_SETn5_Pos 5 /*!< SCT OUTPUTSET6: SETn5 Position */ -#define SCT_OUTPUTSET6_SETn5_Msk (0x01UL << SCT_OUTPUTSET6_SETn5_Pos) /*!< SCT OUTPUTSET6: SETn5 Mask */ -#define SCT_OUTPUTSET6_SETn6_Pos 6 /*!< SCT OUTPUTSET6: SETn6 Position */ -#define SCT_OUTPUTSET6_SETn6_Msk (0x01UL << SCT_OUTPUTSET6_SETn6_Pos) /*!< SCT OUTPUTSET6: SETn6 Mask */ -#define SCT_OUTPUTSET6_SETn7_Pos 7 /*!< SCT OUTPUTSET6: SETn7 Position */ -#define SCT_OUTPUTSET6_SETn7_Msk (0x01UL << SCT_OUTPUTSET6_SETn7_Pos) /*!< SCT OUTPUTSET6: SETn7 Mask */ -#define SCT_OUTPUTSET6_SETn8_Pos 8 /*!< SCT OUTPUTSET6: SETn8 Position */ -#define SCT_OUTPUTSET6_SETn8_Msk (0x01UL << SCT_OUTPUTSET6_SETn8_Pos) /*!< SCT OUTPUTSET6: SETn8 Mask */ -#define SCT_OUTPUTSET6_SETn9_Pos 9 /*!< SCT OUTPUTSET6: SETn9 Position */ -#define SCT_OUTPUTSET6_SETn9_Msk (0x01UL << SCT_OUTPUTSET6_SETn9_Pos) /*!< SCT OUTPUTSET6: SETn9 Mask */ -#define SCT_OUTPUTSET6_SETn10_Pos 10 /*!< SCT OUTPUTSET6: SETn10 Position */ -#define SCT_OUTPUTSET6_SETn10_Msk (0x01UL << SCT_OUTPUTSET6_SETn10_Pos) /*!< SCT OUTPUTSET6: SETn10 Mask */ -#define SCT_OUTPUTSET6_SETn11_Pos 11 /*!< SCT OUTPUTSET6: SETn11 Position */ -#define SCT_OUTPUTSET6_SETn11_Msk (0x01UL << SCT_OUTPUTSET6_SETn11_Pos) /*!< SCT OUTPUTSET6: SETn11 Mask */ -#define SCT_OUTPUTSET6_SETn12_Pos 12 /*!< SCT OUTPUTSET6: SETn12 Position */ -#define SCT_OUTPUTSET6_SETn12_Msk (0x01UL << SCT_OUTPUTSET6_SETn12_Pos) /*!< SCT OUTPUTSET6: SETn12 Mask */ -#define SCT_OUTPUTSET6_SETn13_Pos 13 /*!< SCT OUTPUTSET6: SETn13 Position */ -#define SCT_OUTPUTSET6_SETn13_Msk (0x01UL << SCT_OUTPUTSET6_SETn13_Pos) /*!< SCT OUTPUTSET6: SETn13 Mask */ -#define SCT_OUTPUTSET6_SETn14_Pos 14 /*!< SCT OUTPUTSET6: SETn14 Position */ -#define SCT_OUTPUTSET6_SETn14_Msk (0x01UL << SCT_OUTPUTSET6_SETn14_Pos) /*!< SCT OUTPUTSET6: SETn14 Mask */ -#define SCT_OUTPUTSET6_SETn15_Pos 15 /*!< SCT OUTPUTSET6: SETn15 Position */ -#define SCT_OUTPUTSET6_SETn15_Msk (0x01UL << SCT_OUTPUTSET6_SETn15_Pos) /*!< SCT OUTPUTSET6: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR6 ----------------------------------------- -#define SCT_OUTPUTCLR6_CLRn0_Pos 0 /*!< SCT OUTPUTCLR6: CLRn0 Position */ -#define SCT_OUTPUTCLR6_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos) /*!< SCT OUTPUTCLR6: CLRn0 Mask */ -#define SCT_OUTPUTCLR6_CLRn1_Pos 1 /*!< SCT OUTPUTCLR6: CLRn1 Position */ -#define SCT_OUTPUTCLR6_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos) /*!< SCT OUTPUTCLR6: CLRn1 Mask */ -#define SCT_OUTPUTCLR6_CLRn2_Pos 2 /*!< SCT OUTPUTCLR6: CLRn2 Position */ -#define SCT_OUTPUTCLR6_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos) /*!< SCT OUTPUTCLR6: CLRn2 Mask */ -#define SCT_OUTPUTCLR6_CLRn3_Pos 3 /*!< SCT OUTPUTCLR6: CLRn3 Position */ -#define SCT_OUTPUTCLR6_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos) /*!< SCT OUTPUTCLR6: CLRn3 Mask */ -#define SCT_OUTPUTCLR6_CLRn4_Pos 4 /*!< SCT OUTPUTCLR6: CLRn4 Position */ -#define SCT_OUTPUTCLR6_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos) /*!< SCT OUTPUTCLR6: CLRn4 Mask */ -#define SCT_OUTPUTCLR6_CLRn5_Pos 5 /*!< SCT OUTPUTCLR6: CLRn5 Position */ -#define SCT_OUTPUTCLR6_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos) /*!< SCT OUTPUTCLR6: CLRn5 Mask */ -#define SCT_OUTPUTCLR6_CLRn6_Pos 6 /*!< SCT OUTPUTCLR6: CLRn6 Position */ -#define SCT_OUTPUTCLR6_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos) /*!< SCT OUTPUTCLR6: CLRn6 Mask */ -#define SCT_OUTPUTCLR6_CLRn7_Pos 7 /*!< SCT OUTPUTCLR6: CLRn7 Position */ -#define SCT_OUTPUTCLR6_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos) /*!< SCT OUTPUTCLR6: CLRn7 Mask */ -#define SCT_OUTPUTCLR6_CLRn8_Pos 8 /*!< SCT OUTPUTCLR6: CLRn8 Position */ -#define SCT_OUTPUTCLR6_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos) /*!< SCT OUTPUTCLR6: CLRn8 Mask */ -#define SCT_OUTPUTCLR6_CLRn9_Pos 9 /*!< SCT OUTPUTCLR6: CLRn9 Position */ -#define SCT_OUTPUTCLR6_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos) /*!< SCT OUTPUTCLR6: CLRn9 Mask */ -#define SCT_OUTPUTCLR6_CLRn10_Pos 10 /*!< SCT OUTPUTCLR6: CLRn10 Position */ -#define SCT_OUTPUTCLR6_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos) /*!< SCT OUTPUTCLR6: CLRn10 Mask */ -#define SCT_OUTPUTCLR6_CLRn11_Pos 11 /*!< SCT OUTPUTCLR6: CLRn11 Position */ -#define SCT_OUTPUTCLR6_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos) /*!< SCT OUTPUTCLR6: CLRn11 Mask */ -#define SCT_OUTPUTCLR6_CLRn12_Pos 12 /*!< SCT OUTPUTCLR6: CLRn12 Position */ -#define SCT_OUTPUTCLR6_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos) /*!< SCT OUTPUTCLR6: CLRn12 Mask */ -#define SCT_OUTPUTCLR6_CLRn13_Pos 13 /*!< SCT OUTPUTCLR6: CLRn13 Position */ -#define SCT_OUTPUTCLR6_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos) /*!< SCT OUTPUTCLR6: CLRn13 Mask */ -#define SCT_OUTPUTCLR6_CLRn14_Pos 14 /*!< SCT OUTPUTCLR6: CLRn14 Position */ -#define SCT_OUTPUTCLR6_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos) /*!< SCT OUTPUTCLR6: CLRn14 Mask */ -#define SCT_OUTPUTCLR6_CLRn15_Pos 15 /*!< SCT OUTPUTCLR6: CLRn15 Position */ -#define SCT_OUTPUTCLR6_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos) /*!< SCT OUTPUTCLR6: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET7 ----------------------------------------- -#define SCT_OUTPUTSET7_SETn0_Pos 0 /*!< SCT OUTPUTSET7: SETn0 Position */ -#define SCT_OUTPUTSET7_SETn0_Msk (0x01UL << SCT_OUTPUTSET7_SETn0_Pos) /*!< SCT OUTPUTSET7: SETn0 Mask */ -#define SCT_OUTPUTSET7_SETn1_Pos 1 /*!< SCT OUTPUTSET7: SETn1 Position */ -#define SCT_OUTPUTSET7_SETn1_Msk (0x01UL << SCT_OUTPUTSET7_SETn1_Pos) /*!< SCT OUTPUTSET7: SETn1 Mask */ -#define SCT_OUTPUTSET7_SETn2_Pos 2 /*!< SCT OUTPUTSET7: SETn2 Position */ -#define SCT_OUTPUTSET7_SETn2_Msk (0x01UL << SCT_OUTPUTSET7_SETn2_Pos) /*!< SCT OUTPUTSET7: SETn2 Mask */ -#define SCT_OUTPUTSET7_SETn3_Pos 3 /*!< SCT OUTPUTSET7: SETn3 Position */ -#define SCT_OUTPUTSET7_SETn3_Msk (0x01UL << SCT_OUTPUTSET7_SETn3_Pos) /*!< SCT OUTPUTSET7: SETn3 Mask */ -#define SCT_OUTPUTSET7_SETn4_Pos 4 /*!< SCT OUTPUTSET7: SETn4 Position */ -#define SCT_OUTPUTSET7_SETn4_Msk (0x01UL << SCT_OUTPUTSET7_SETn4_Pos) /*!< SCT OUTPUTSET7: SETn4 Mask */ -#define SCT_OUTPUTSET7_SETn5_Pos 5 /*!< SCT OUTPUTSET7: SETn5 Position */ -#define SCT_OUTPUTSET7_SETn5_Msk (0x01UL << SCT_OUTPUTSET7_SETn5_Pos) /*!< SCT OUTPUTSET7: SETn5 Mask */ -#define SCT_OUTPUTSET7_SETn6_Pos 6 /*!< SCT OUTPUTSET7: SETn6 Position */ -#define SCT_OUTPUTSET7_SETn6_Msk (0x01UL << SCT_OUTPUTSET7_SETn6_Pos) /*!< SCT OUTPUTSET7: SETn6 Mask */ -#define SCT_OUTPUTSET7_SETn7_Pos 7 /*!< SCT OUTPUTSET7: SETn7 Position */ -#define SCT_OUTPUTSET7_SETn7_Msk (0x01UL << SCT_OUTPUTSET7_SETn7_Pos) /*!< SCT OUTPUTSET7: SETn7 Mask */ -#define SCT_OUTPUTSET7_SETn8_Pos 8 /*!< SCT OUTPUTSET7: SETn8 Position */ -#define SCT_OUTPUTSET7_SETn8_Msk (0x01UL << SCT_OUTPUTSET7_SETn8_Pos) /*!< SCT OUTPUTSET7: SETn8 Mask */ -#define SCT_OUTPUTSET7_SETn9_Pos 9 /*!< SCT OUTPUTSET7: SETn9 Position */ -#define SCT_OUTPUTSET7_SETn9_Msk (0x01UL << SCT_OUTPUTSET7_SETn9_Pos) /*!< SCT OUTPUTSET7: SETn9 Mask */ -#define SCT_OUTPUTSET7_SETn10_Pos 10 /*!< SCT OUTPUTSET7: SETn10 Position */ -#define SCT_OUTPUTSET7_SETn10_Msk (0x01UL << SCT_OUTPUTSET7_SETn10_Pos) /*!< SCT OUTPUTSET7: SETn10 Mask */ -#define SCT_OUTPUTSET7_SETn11_Pos 11 /*!< SCT OUTPUTSET7: SETn11 Position */ -#define SCT_OUTPUTSET7_SETn11_Msk (0x01UL << SCT_OUTPUTSET7_SETn11_Pos) /*!< SCT OUTPUTSET7: SETn11 Mask */ -#define SCT_OUTPUTSET7_SETn12_Pos 12 /*!< SCT OUTPUTSET7: SETn12 Position */ -#define SCT_OUTPUTSET7_SETn12_Msk (0x01UL << SCT_OUTPUTSET7_SETn12_Pos) /*!< SCT OUTPUTSET7: SETn12 Mask */ -#define SCT_OUTPUTSET7_SETn13_Pos 13 /*!< SCT OUTPUTSET7: SETn13 Position */ -#define SCT_OUTPUTSET7_SETn13_Msk (0x01UL << SCT_OUTPUTSET7_SETn13_Pos) /*!< SCT OUTPUTSET7: SETn13 Mask */ -#define SCT_OUTPUTSET7_SETn14_Pos 14 /*!< SCT OUTPUTSET7: SETn14 Position */ -#define SCT_OUTPUTSET7_SETn14_Msk (0x01UL << SCT_OUTPUTSET7_SETn14_Pos) /*!< SCT OUTPUTSET7: SETn14 Mask */ -#define SCT_OUTPUTSET7_SETn15_Pos 15 /*!< SCT OUTPUTSET7: SETn15 Position */ -#define SCT_OUTPUTSET7_SETn15_Msk (0x01UL << SCT_OUTPUTSET7_SETn15_Pos) /*!< SCT OUTPUTSET7: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR7 ----------------------------------------- -#define SCT_OUTPUTCLR7_CLRn0_Pos 0 /*!< SCT OUTPUTCLR7: CLRn0 Position */ -#define SCT_OUTPUTCLR7_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos) /*!< SCT OUTPUTCLR7: CLRn0 Mask */ -#define SCT_OUTPUTCLR7_CLRn1_Pos 1 /*!< SCT OUTPUTCLR7: CLRn1 Position */ -#define SCT_OUTPUTCLR7_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos) /*!< SCT OUTPUTCLR7: CLRn1 Mask */ -#define SCT_OUTPUTCLR7_CLRn2_Pos 2 /*!< SCT OUTPUTCLR7: CLRn2 Position */ -#define SCT_OUTPUTCLR7_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos) /*!< SCT OUTPUTCLR7: CLRn2 Mask */ -#define SCT_OUTPUTCLR7_CLRn3_Pos 3 /*!< SCT OUTPUTCLR7: CLRn3 Position */ -#define SCT_OUTPUTCLR7_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos) /*!< SCT OUTPUTCLR7: CLRn3 Mask */ -#define SCT_OUTPUTCLR7_CLRn4_Pos 4 /*!< SCT OUTPUTCLR7: CLRn4 Position */ -#define SCT_OUTPUTCLR7_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos) /*!< SCT OUTPUTCLR7: CLRn4 Mask */ -#define SCT_OUTPUTCLR7_CLRn5_Pos 5 /*!< SCT OUTPUTCLR7: CLRn5 Position */ -#define SCT_OUTPUTCLR7_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos) /*!< SCT OUTPUTCLR7: CLRn5 Mask */ -#define SCT_OUTPUTCLR7_CLRn6_Pos 6 /*!< SCT OUTPUTCLR7: CLRn6 Position */ -#define SCT_OUTPUTCLR7_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos) /*!< SCT OUTPUTCLR7: CLRn6 Mask */ -#define SCT_OUTPUTCLR7_CLRn7_Pos 7 /*!< SCT OUTPUTCLR7: CLRn7 Position */ -#define SCT_OUTPUTCLR7_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos) /*!< SCT OUTPUTCLR7: CLRn7 Mask */ -#define SCT_OUTPUTCLR7_CLRn8_Pos 8 /*!< SCT OUTPUTCLR7: CLRn8 Position */ -#define SCT_OUTPUTCLR7_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos) /*!< SCT OUTPUTCLR7: CLRn8 Mask */ -#define SCT_OUTPUTCLR7_CLRn9_Pos 9 /*!< SCT OUTPUTCLR7: CLRn9 Position */ -#define SCT_OUTPUTCLR7_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos) /*!< SCT OUTPUTCLR7: CLRn9 Mask */ -#define SCT_OUTPUTCLR7_CLRn10_Pos 10 /*!< SCT OUTPUTCLR7: CLRn10 Position */ -#define SCT_OUTPUTCLR7_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos) /*!< SCT OUTPUTCLR7: CLRn10 Mask */ -#define SCT_OUTPUTCLR7_CLRn11_Pos 11 /*!< SCT OUTPUTCLR7: CLRn11 Position */ -#define SCT_OUTPUTCLR7_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos) /*!< SCT OUTPUTCLR7: CLRn11 Mask */ -#define SCT_OUTPUTCLR7_CLRn12_Pos 12 /*!< SCT OUTPUTCLR7: CLRn12 Position */ -#define SCT_OUTPUTCLR7_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos) /*!< SCT OUTPUTCLR7: CLRn12 Mask */ -#define SCT_OUTPUTCLR7_CLRn13_Pos 13 /*!< SCT OUTPUTCLR7: CLRn13 Position */ -#define SCT_OUTPUTCLR7_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos) /*!< SCT OUTPUTCLR7: CLRn13 Mask */ -#define SCT_OUTPUTCLR7_CLRn14_Pos 14 /*!< SCT OUTPUTCLR7: CLRn14 Position */ -#define SCT_OUTPUTCLR7_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos) /*!< SCT OUTPUTCLR7: CLRn14 Mask */ -#define SCT_OUTPUTCLR7_CLRn15_Pos 15 /*!< SCT OUTPUTCLR7: CLRn15 Position */ -#define SCT_OUTPUTCLR7_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos) /*!< SCT OUTPUTCLR7: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET8 ----------------------------------------- -#define SCT_OUTPUTSET8_SETn0_Pos 0 /*!< SCT OUTPUTSET8: SETn0 Position */ -#define SCT_OUTPUTSET8_SETn0_Msk (0x01UL << SCT_OUTPUTSET8_SETn0_Pos) /*!< SCT OUTPUTSET8: SETn0 Mask */ -#define SCT_OUTPUTSET8_SETn1_Pos 1 /*!< SCT OUTPUTSET8: SETn1 Position */ -#define SCT_OUTPUTSET8_SETn1_Msk (0x01UL << SCT_OUTPUTSET8_SETn1_Pos) /*!< SCT OUTPUTSET8: SETn1 Mask */ -#define SCT_OUTPUTSET8_SETn2_Pos 2 /*!< SCT OUTPUTSET8: SETn2 Position */ -#define SCT_OUTPUTSET8_SETn2_Msk (0x01UL << SCT_OUTPUTSET8_SETn2_Pos) /*!< SCT OUTPUTSET8: SETn2 Mask */ -#define SCT_OUTPUTSET8_SETn3_Pos 3 /*!< SCT OUTPUTSET8: SETn3 Position */ -#define SCT_OUTPUTSET8_SETn3_Msk (0x01UL << SCT_OUTPUTSET8_SETn3_Pos) /*!< SCT OUTPUTSET8: SETn3 Mask */ -#define SCT_OUTPUTSET8_SETn4_Pos 4 /*!< SCT OUTPUTSET8: SETn4 Position */ -#define SCT_OUTPUTSET8_SETn4_Msk (0x01UL << SCT_OUTPUTSET8_SETn4_Pos) /*!< SCT OUTPUTSET8: SETn4 Mask */ -#define SCT_OUTPUTSET8_SETn5_Pos 5 /*!< SCT OUTPUTSET8: SETn5 Position */ -#define SCT_OUTPUTSET8_SETn5_Msk (0x01UL << SCT_OUTPUTSET8_SETn5_Pos) /*!< SCT OUTPUTSET8: SETn5 Mask */ -#define SCT_OUTPUTSET8_SETn6_Pos 6 /*!< SCT OUTPUTSET8: SETn6 Position */ -#define SCT_OUTPUTSET8_SETn6_Msk (0x01UL << SCT_OUTPUTSET8_SETn6_Pos) /*!< SCT OUTPUTSET8: SETn6 Mask */ -#define SCT_OUTPUTSET8_SETn7_Pos 7 /*!< SCT OUTPUTSET8: SETn7 Position */ -#define SCT_OUTPUTSET8_SETn7_Msk (0x01UL << SCT_OUTPUTSET8_SETn7_Pos) /*!< SCT OUTPUTSET8: SETn7 Mask */ -#define SCT_OUTPUTSET8_SETn8_Pos 8 /*!< SCT OUTPUTSET8: SETn8 Position */ -#define SCT_OUTPUTSET8_SETn8_Msk (0x01UL << SCT_OUTPUTSET8_SETn8_Pos) /*!< SCT OUTPUTSET8: SETn8 Mask */ -#define SCT_OUTPUTSET8_SETn9_Pos 9 /*!< SCT OUTPUTSET8: SETn9 Position */ -#define SCT_OUTPUTSET8_SETn9_Msk (0x01UL << SCT_OUTPUTSET8_SETn9_Pos) /*!< SCT OUTPUTSET8: SETn9 Mask */ -#define SCT_OUTPUTSET8_SETn10_Pos 10 /*!< SCT OUTPUTSET8: SETn10 Position */ -#define SCT_OUTPUTSET8_SETn10_Msk (0x01UL << SCT_OUTPUTSET8_SETn10_Pos) /*!< SCT OUTPUTSET8: SETn10 Mask */ -#define SCT_OUTPUTSET8_SETn11_Pos 11 /*!< SCT OUTPUTSET8: SETn11 Position */ -#define SCT_OUTPUTSET8_SETn11_Msk (0x01UL << SCT_OUTPUTSET8_SETn11_Pos) /*!< SCT OUTPUTSET8: SETn11 Mask */ -#define SCT_OUTPUTSET8_SETn12_Pos 12 /*!< SCT OUTPUTSET8: SETn12 Position */ -#define SCT_OUTPUTSET8_SETn12_Msk (0x01UL << SCT_OUTPUTSET8_SETn12_Pos) /*!< SCT OUTPUTSET8: SETn12 Mask */ -#define SCT_OUTPUTSET8_SETn13_Pos 13 /*!< SCT OUTPUTSET8: SETn13 Position */ -#define SCT_OUTPUTSET8_SETn13_Msk (0x01UL << SCT_OUTPUTSET8_SETn13_Pos) /*!< SCT OUTPUTSET8: SETn13 Mask */ -#define SCT_OUTPUTSET8_SETn14_Pos 14 /*!< SCT OUTPUTSET8: SETn14 Position */ -#define SCT_OUTPUTSET8_SETn14_Msk (0x01UL << SCT_OUTPUTSET8_SETn14_Pos) /*!< SCT OUTPUTSET8: SETn14 Mask */ -#define SCT_OUTPUTSET8_SETn15_Pos 15 /*!< SCT OUTPUTSET8: SETn15 Position */ -#define SCT_OUTPUTSET8_SETn15_Msk (0x01UL << SCT_OUTPUTSET8_SETn15_Pos) /*!< SCT OUTPUTSET8: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR8 ----------------------------------------- -#define SCT_OUTPUTCLR8_CLRn0_Pos 0 /*!< SCT OUTPUTCLR8: CLRn0 Position */ -#define SCT_OUTPUTCLR8_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos) /*!< SCT OUTPUTCLR8: CLRn0 Mask */ -#define SCT_OUTPUTCLR8_CLRn1_Pos 1 /*!< SCT OUTPUTCLR8: CLRn1 Position */ -#define SCT_OUTPUTCLR8_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos) /*!< SCT OUTPUTCLR8: CLRn1 Mask */ -#define SCT_OUTPUTCLR8_CLRn2_Pos 2 /*!< SCT OUTPUTCLR8: CLRn2 Position */ -#define SCT_OUTPUTCLR8_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos) /*!< SCT OUTPUTCLR8: CLRn2 Mask */ -#define SCT_OUTPUTCLR8_CLRn3_Pos 3 /*!< SCT OUTPUTCLR8: CLRn3 Position */ -#define SCT_OUTPUTCLR8_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos) /*!< SCT OUTPUTCLR8: CLRn3 Mask */ -#define SCT_OUTPUTCLR8_CLRn4_Pos 4 /*!< SCT OUTPUTCLR8: CLRn4 Position */ -#define SCT_OUTPUTCLR8_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos) /*!< SCT OUTPUTCLR8: CLRn4 Mask */ -#define SCT_OUTPUTCLR8_CLRn5_Pos 5 /*!< SCT OUTPUTCLR8: CLRn5 Position */ -#define SCT_OUTPUTCLR8_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos) /*!< SCT OUTPUTCLR8: CLRn5 Mask */ -#define SCT_OUTPUTCLR8_CLRn6_Pos 6 /*!< SCT OUTPUTCLR8: CLRn6 Position */ -#define SCT_OUTPUTCLR8_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos) /*!< SCT OUTPUTCLR8: CLRn6 Mask */ -#define SCT_OUTPUTCLR8_CLRn7_Pos 7 /*!< SCT OUTPUTCLR8: CLRn7 Position */ -#define SCT_OUTPUTCLR8_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos) /*!< SCT OUTPUTCLR8: CLRn7 Mask */ -#define SCT_OUTPUTCLR8_CLRn8_Pos 8 /*!< SCT OUTPUTCLR8: CLRn8 Position */ -#define SCT_OUTPUTCLR8_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos) /*!< SCT OUTPUTCLR8: CLRn8 Mask */ -#define SCT_OUTPUTCLR8_CLRn9_Pos 9 /*!< SCT OUTPUTCLR8: CLRn9 Position */ -#define SCT_OUTPUTCLR8_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos) /*!< SCT OUTPUTCLR8: CLRn9 Mask */ -#define SCT_OUTPUTCLR8_CLRn10_Pos 10 /*!< SCT OUTPUTCLR8: CLRn10 Position */ -#define SCT_OUTPUTCLR8_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos) /*!< SCT OUTPUTCLR8: CLRn10 Mask */ -#define SCT_OUTPUTCLR8_CLRn11_Pos 11 /*!< SCT OUTPUTCLR8: CLRn11 Position */ -#define SCT_OUTPUTCLR8_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos) /*!< SCT OUTPUTCLR8: CLRn11 Mask */ -#define SCT_OUTPUTCLR8_CLRn12_Pos 12 /*!< SCT OUTPUTCLR8: CLRn12 Position */ -#define SCT_OUTPUTCLR8_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos) /*!< SCT OUTPUTCLR8: CLRn12 Mask */ -#define SCT_OUTPUTCLR8_CLRn13_Pos 13 /*!< SCT OUTPUTCLR8: CLRn13 Position */ -#define SCT_OUTPUTCLR8_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos) /*!< SCT OUTPUTCLR8: CLRn13 Mask */ -#define SCT_OUTPUTCLR8_CLRn14_Pos 14 /*!< SCT OUTPUTCLR8: CLRn14 Position */ -#define SCT_OUTPUTCLR8_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos) /*!< SCT OUTPUTCLR8: CLRn14 Mask */ -#define SCT_OUTPUTCLR8_CLRn15_Pos 15 /*!< SCT OUTPUTCLR8: CLRn15 Position */ -#define SCT_OUTPUTCLR8_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos) /*!< SCT OUTPUTCLR8: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET9 ----------------------------------------- -#define SCT_OUTPUTSET9_SETn0_Pos 0 /*!< SCT OUTPUTSET9: SETn0 Position */ -#define SCT_OUTPUTSET9_SETn0_Msk (0x01UL << SCT_OUTPUTSET9_SETn0_Pos) /*!< SCT OUTPUTSET9: SETn0 Mask */ -#define SCT_OUTPUTSET9_SETn1_Pos 1 /*!< SCT OUTPUTSET9: SETn1 Position */ -#define SCT_OUTPUTSET9_SETn1_Msk (0x01UL << SCT_OUTPUTSET9_SETn1_Pos) /*!< SCT OUTPUTSET9: SETn1 Mask */ -#define SCT_OUTPUTSET9_SETn2_Pos 2 /*!< SCT OUTPUTSET9: SETn2 Position */ -#define SCT_OUTPUTSET9_SETn2_Msk (0x01UL << SCT_OUTPUTSET9_SETn2_Pos) /*!< SCT OUTPUTSET9: SETn2 Mask */ -#define SCT_OUTPUTSET9_SETn3_Pos 3 /*!< SCT OUTPUTSET9: SETn3 Position */ -#define SCT_OUTPUTSET9_SETn3_Msk (0x01UL << SCT_OUTPUTSET9_SETn3_Pos) /*!< SCT OUTPUTSET9: SETn3 Mask */ -#define SCT_OUTPUTSET9_SETn4_Pos 4 /*!< SCT OUTPUTSET9: SETn4 Position */ -#define SCT_OUTPUTSET9_SETn4_Msk (0x01UL << SCT_OUTPUTSET9_SETn4_Pos) /*!< SCT OUTPUTSET9: SETn4 Mask */ -#define SCT_OUTPUTSET9_SETn5_Pos 5 /*!< SCT OUTPUTSET9: SETn5 Position */ -#define SCT_OUTPUTSET9_SETn5_Msk (0x01UL << SCT_OUTPUTSET9_SETn5_Pos) /*!< SCT OUTPUTSET9: SETn5 Mask */ -#define SCT_OUTPUTSET9_SETn6_Pos 6 /*!< SCT OUTPUTSET9: SETn6 Position */ -#define SCT_OUTPUTSET9_SETn6_Msk (0x01UL << SCT_OUTPUTSET9_SETn6_Pos) /*!< SCT OUTPUTSET9: SETn6 Mask */ -#define SCT_OUTPUTSET9_SETn7_Pos 7 /*!< SCT OUTPUTSET9: SETn7 Position */ -#define SCT_OUTPUTSET9_SETn7_Msk (0x01UL << SCT_OUTPUTSET9_SETn7_Pos) /*!< SCT OUTPUTSET9: SETn7 Mask */ -#define SCT_OUTPUTSET9_SETn8_Pos 8 /*!< SCT OUTPUTSET9: SETn8 Position */ -#define SCT_OUTPUTSET9_SETn8_Msk (0x01UL << SCT_OUTPUTSET9_SETn8_Pos) /*!< SCT OUTPUTSET9: SETn8 Mask */ -#define SCT_OUTPUTSET9_SETn9_Pos 9 /*!< SCT OUTPUTSET9: SETn9 Position */ -#define SCT_OUTPUTSET9_SETn9_Msk (0x01UL << SCT_OUTPUTSET9_SETn9_Pos) /*!< SCT OUTPUTSET9: SETn9 Mask */ -#define SCT_OUTPUTSET9_SETn10_Pos 10 /*!< SCT OUTPUTSET9: SETn10 Position */ -#define SCT_OUTPUTSET9_SETn10_Msk (0x01UL << SCT_OUTPUTSET9_SETn10_Pos) /*!< SCT OUTPUTSET9: SETn10 Mask */ -#define SCT_OUTPUTSET9_SETn11_Pos 11 /*!< SCT OUTPUTSET9: SETn11 Position */ -#define SCT_OUTPUTSET9_SETn11_Msk (0x01UL << SCT_OUTPUTSET9_SETn11_Pos) /*!< SCT OUTPUTSET9: SETn11 Mask */ -#define SCT_OUTPUTSET9_SETn12_Pos 12 /*!< SCT OUTPUTSET9: SETn12 Position */ -#define SCT_OUTPUTSET9_SETn12_Msk (0x01UL << SCT_OUTPUTSET9_SETn12_Pos) /*!< SCT OUTPUTSET9: SETn12 Mask */ -#define SCT_OUTPUTSET9_SETn13_Pos 13 /*!< SCT OUTPUTSET9: SETn13 Position */ -#define SCT_OUTPUTSET9_SETn13_Msk (0x01UL << SCT_OUTPUTSET9_SETn13_Pos) /*!< SCT OUTPUTSET9: SETn13 Mask */ -#define SCT_OUTPUTSET9_SETn14_Pos 14 /*!< SCT OUTPUTSET9: SETn14 Position */ -#define SCT_OUTPUTSET9_SETn14_Msk (0x01UL << SCT_OUTPUTSET9_SETn14_Pos) /*!< SCT OUTPUTSET9: SETn14 Mask */ -#define SCT_OUTPUTSET9_SETn15_Pos 15 /*!< SCT OUTPUTSET9: SETn15 Position */ -#define SCT_OUTPUTSET9_SETn15_Msk (0x01UL << SCT_OUTPUTSET9_SETn15_Pos) /*!< SCT OUTPUTSET9: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR9 ----------------------------------------- -#define SCT_OUTPUTCLR9_CLRn0_Pos 0 /*!< SCT OUTPUTCLR9: CLRn0 Position */ -#define SCT_OUTPUTCLR9_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos) /*!< SCT OUTPUTCLR9: CLRn0 Mask */ -#define SCT_OUTPUTCLR9_CLRn1_Pos 1 /*!< SCT OUTPUTCLR9: CLRn1 Position */ -#define SCT_OUTPUTCLR9_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos) /*!< SCT OUTPUTCLR9: CLRn1 Mask */ -#define SCT_OUTPUTCLR9_CLRn2_Pos 2 /*!< SCT OUTPUTCLR9: CLRn2 Position */ -#define SCT_OUTPUTCLR9_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos) /*!< SCT OUTPUTCLR9: CLRn2 Mask */ -#define SCT_OUTPUTCLR9_CLRn3_Pos 3 /*!< SCT OUTPUTCLR9: CLRn3 Position */ -#define SCT_OUTPUTCLR9_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos) /*!< SCT OUTPUTCLR9: CLRn3 Mask */ -#define SCT_OUTPUTCLR9_CLRn4_Pos 4 /*!< SCT OUTPUTCLR9: CLRn4 Position */ -#define SCT_OUTPUTCLR9_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos) /*!< SCT OUTPUTCLR9: CLRn4 Mask */ -#define SCT_OUTPUTCLR9_CLRn5_Pos 5 /*!< SCT OUTPUTCLR9: CLRn5 Position */ -#define SCT_OUTPUTCLR9_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos) /*!< SCT OUTPUTCLR9: CLRn5 Mask */ -#define SCT_OUTPUTCLR9_CLRn6_Pos 6 /*!< SCT OUTPUTCLR9: CLRn6 Position */ -#define SCT_OUTPUTCLR9_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos) /*!< SCT OUTPUTCLR9: CLRn6 Mask */ -#define SCT_OUTPUTCLR9_CLRn7_Pos 7 /*!< SCT OUTPUTCLR9: CLRn7 Position */ -#define SCT_OUTPUTCLR9_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos) /*!< SCT OUTPUTCLR9: CLRn7 Mask */ -#define SCT_OUTPUTCLR9_CLRn8_Pos 8 /*!< SCT OUTPUTCLR9: CLRn8 Position */ -#define SCT_OUTPUTCLR9_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos) /*!< SCT OUTPUTCLR9: CLRn8 Mask */ -#define SCT_OUTPUTCLR9_CLRn9_Pos 9 /*!< SCT OUTPUTCLR9: CLRn9 Position */ -#define SCT_OUTPUTCLR9_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos) /*!< SCT OUTPUTCLR9: CLRn9 Mask */ -#define SCT_OUTPUTCLR9_CLRn10_Pos 10 /*!< SCT OUTPUTCLR9: CLRn10 Position */ -#define SCT_OUTPUTCLR9_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos) /*!< SCT OUTPUTCLR9: CLRn10 Mask */ -#define SCT_OUTPUTCLR9_CLRn11_Pos 11 /*!< SCT OUTPUTCLR9: CLRn11 Position */ -#define SCT_OUTPUTCLR9_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos) /*!< SCT OUTPUTCLR9: CLRn11 Mask */ -#define SCT_OUTPUTCLR9_CLRn12_Pos 12 /*!< SCT OUTPUTCLR9: CLRn12 Position */ -#define SCT_OUTPUTCLR9_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos) /*!< SCT OUTPUTCLR9: CLRn12 Mask */ -#define SCT_OUTPUTCLR9_CLRn13_Pos 13 /*!< SCT OUTPUTCLR9: CLRn13 Position */ -#define SCT_OUTPUTCLR9_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos) /*!< SCT OUTPUTCLR9: CLRn13 Mask */ -#define SCT_OUTPUTCLR9_CLRn14_Pos 14 /*!< SCT OUTPUTCLR9: CLRn14 Position */ -#define SCT_OUTPUTCLR9_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos) /*!< SCT OUTPUTCLR9: CLRn14 Mask */ -#define SCT_OUTPUTCLR9_CLRn15_Pos 15 /*!< SCT OUTPUTCLR9: CLRn15 Position */ -#define SCT_OUTPUTCLR9_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos) /*!< SCT OUTPUTCLR9: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET10 ---------------------------------------- -#define SCT_OUTPUTSET10_SETn0_Pos 0 /*!< SCT OUTPUTSET10: SETn0 Position */ -#define SCT_OUTPUTSET10_SETn0_Msk (0x01UL << SCT_OUTPUTSET10_SETn0_Pos) /*!< SCT OUTPUTSET10: SETn0 Mask */ -#define SCT_OUTPUTSET10_SETn1_Pos 1 /*!< SCT OUTPUTSET10: SETn1 Position */ -#define SCT_OUTPUTSET10_SETn1_Msk (0x01UL << SCT_OUTPUTSET10_SETn1_Pos) /*!< SCT OUTPUTSET10: SETn1 Mask */ -#define SCT_OUTPUTSET10_SETn2_Pos 2 /*!< SCT OUTPUTSET10: SETn2 Position */ -#define SCT_OUTPUTSET10_SETn2_Msk (0x01UL << SCT_OUTPUTSET10_SETn2_Pos) /*!< SCT OUTPUTSET10: SETn2 Mask */ -#define SCT_OUTPUTSET10_SETn3_Pos 3 /*!< SCT OUTPUTSET10: SETn3 Position */ -#define SCT_OUTPUTSET10_SETn3_Msk (0x01UL << SCT_OUTPUTSET10_SETn3_Pos) /*!< SCT OUTPUTSET10: SETn3 Mask */ -#define SCT_OUTPUTSET10_SETn4_Pos 4 /*!< SCT OUTPUTSET10: SETn4 Position */ -#define SCT_OUTPUTSET10_SETn4_Msk (0x01UL << SCT_OUTPUTSET10_SETn4_Pos) /*!< SCT OUTPUTSET10: SETn4 Mask */ -#define SCT_OUTPUTSET10_SETn5_Pos 5 /*!< SCT OUTPUTSET10: SETn5 Position */ -#define SCT_OUTPUTSET10_SETn5_Msk (0x01UL << SCT_OUTPUTSET10_SETn5_Pos) /*!< SCT OUTPUTSET10: SETn5 Mask */ -#define SCT_OUTPUTSET10_SETn6_Pos 6 /*!< SCT OUTPUTSET10: SETn6 Position */ -#define SCT_OUTPUTSET10_SETn6_Msk (0x01UL << SCT_OUTPUTSET10_SETn6_Pos) /*!< SCT OUTPUTSET10: SETn6 Mask */ -#define SCT_OUTPUTSET10_SETn7_Pos 7 /*!< SCT OUTPUTSET10: SETn7 Position */ -#define SCT_OUTPUTSET10_SETn7_Msk (0x01UL << SCT_OUTPUTSET10_SETn7_Pos) /*!< SCT OUTPUTSET10: SETn7 Mask */ -#define SCT_OUTPUTSET10_SETn8_Pos 8 /*!< SCT OUTPUTSET10: SETn8 Position */ -#define SCT_OUTPUTSET10_SETn8_Msk (0x01UL << SCT_OUTPUTSET10_SETn8_Pos) /*!< SCT OUTPUTSET10: SETn8 Mask */ -#define SCT_OUTPUTSET10_SETn9_Pos 9 /*!< SCT OUTPUTSET10: SETn9 Position */ -#define SCT_OUTPUTSET10_SETn9_Msk (0x01UL << SCT_OUTPUTSET10_SETn9_Pos) /*!< SCT OUTPUTSET10: SETn9 Mask */ -#define SCT_OUTPUTSET10_SETn10_Pos 10 /*!< SCT OUTPUTSET10: SETn10 Position */ -#define SCT_OUTPUTSET10_SETn10_Msk (0x01UL << SCT_OUTPUTSET10_SETn10_Pos) /*!< SCT OUTPUTSET10: SETn10 Mask */ -#define SCT_OUTPUTSET10_SETn11_Pos 11 /*!< SCT OUTPUTSET10: SETn11 Position */ -#define SCT_OUTPUTSET10_SETn11_Msk (0x01UL << SCT_OUTPUTSET10_SETn11_Pos) /*!< SCT OUTPUTSET10: SETn11 Mask */ -#define SCT_OUTPUTSET10_SETn12_Pos 12 /*!< SCT OUTPUTSET10: SETn12 Position */ -#define SCT_OUTPUTSET10_SETn12_Msk (0x01UL << SCT_OUTPUTSET10_SETn12_Pos) /*!< SCT OUTPUTSET10: SETn12 Mask */ -#define SCT_OUTPUTSET10_SETn13_Pos 13 /*!< SCT OUTPUTSET10: SETn13 Position */ -#define SCT_OUTPUTSET10_SETn13_Msk (0x01UL << SCT_OUTPUTSET10_SETn13_Pos) /*!< SCT OUTPUTSET10: SETn13 Mask */ -#define SCT_OUTPUTSET10_SETn14_Pos 14 /*!< SCT OUTPUTSET10: SETn14 Position */ -#define SCT_OUTPUTSET10_SETn14_Msk (0x01UL << SCT_OUTPUTSET10_SETn14_Pos) /*!< SCT OUTPUTSET10: SETn14 Mask */ -#define SCT_OUTPUTSET10_SETn15_Pos 15 /*!< SCT OUTPUTSET10: SETn15 Position */ -#define SCT_OUTPUTSET10_SETn15_Msk (0x01UL << SCT_OUTPUTSET10_SETn15_Pos) /*!< SCT OUTPUTSET10: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR10 ---------------------------------------- -#define SCT_OUTPUTCLR10_CLRn0_Pos 0 /*!< SCT OUTPUTCLR10: CLRn0 Position */ -#define SCT_OUTPUTCLR10_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos) /*!< SCT OUTPUTCLR10: CLRn0 Mask */ -#define SCT_OUTPUTCLR10_CLRn1_Pos 1 /*!< SCT OUTPUTCLR10: CLRn1 Position */ -#define SCT_OUTPUTCLR10_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos) /*!< SCT OUTPUTCLR10: CLRn1 Mask */ -#define SCT_OUTPUTCLR10_CLRn2_Pos 2 /*!< SCT OUTPUTCLR10: CLRn2 Position */ -#define SCT_OUTPUTCLR10_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos) /*!< SCT OUTPUTCLR10: CLRn2 Mask */ -#define SCT_OUTPUTCLR10_CLRn3_Pos 3 /*!< SCT OUTPUTCLR10: CLRn3 Position */ -#define SCT_OUTPUTCLR10_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos) /*!< SCT OUTPUTCLR10: CLRn3 Mask */ -#define SCT_OUTPUTCLR10_CLRn4_Pos 4 /*!< SCT OUTPUTCLR10: CLRn4 Position */ -#define SCT_OUTPUTCLR10_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos) /*!< SCT OUTPUTCLR10: CLRn4 Mask */ -#define SCT_OUTPUTCLR10_CLRn5_Pos 5 /*!< SCT OUTPUTCLR10: CLRn5 Position */ -#define SCT_OUTPUTCLR10_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos) /*!< SCT OUTPUTCLR10: CLRn5 Mask */ -#define SCT_OUTPUTCLR10_CLRn6_Pos 6 /*!< SCT OUTPUTCLR10: CLRn6 Position */ -#define SCT_OUTPUTCLR10_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos) /*!< SCT OUTPUTCLR10: CLRn6 Mask */ -#define SCT_OUTPUTCLR10_CLRn7_Pos 7 /*!< SCT OUTPUTCLR10: CLRn7 Position */ -#define SCT_OUTPUTCLR10_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos) /*!< SCT OUTPUTCLR10: CLRn7 Mask */ -#define SCT_OUTPUTCLR10_CLRn8_Pos 8 /*!< SCT OUTPUTCLR10: CLRn8 Position */ -#define SCT_OUTPUTCLR10_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos) /*!< SCT OUTPUTCLR10: CLRn8 Mask */ -#define SCT_OUTPUTCLR10_CLRn9_Pos 9 /*!< SCT OUTPUTCLR10: CLRn9 Position */ -#define SCT_OUTPUTCLR10_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos) /*!< SCT OUTPUTCLR10: CLRn9 Mask */ -#define SCT_OUTPUTCLR10_CLRn10_Pos 10 /*!< SCT OUTPUTCLR10: CLRn10 Position */ -#define SCT_OUTPUTCLR10_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos) /*!< SCT OUTPUTCLR10: CLRn10 Mask */ -#define SCT_OUTPUTCLR10_CLRn11_Pos 11 /*!< SCT OUTPUTCLR10: CLRn11 Position */ -#define SCT_OUTPUTCLR10_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos) /*!< SCT OUTPUTCLR10: CLRn11 Mask */ -#define SCT_OUTPUTCLR10_CLRn12_Pos 12 /*!< SCT OUTPUTCLR10: CLRn12 Position */ -#define SCT_OUTPUTCLR10_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos) /*!< SCT OUTPUTCLR10: CLRn12 Mask */ -#define SCT_OUTPUTCLR10_CLRn13_Pos 13 /*!< SCT OUTPUTCLR10: CLRn13 Position */ -#define SCT_OUTPUTCLR10_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos) /*!< SCT OUTPUTCLR10: CLRn13 Mask */ -#define SCT_OUTPUTCLR10_CLRn14_Pos 14 /*!< SCT OUTPUTCLR10: CLRn14 Position */ -#define SCT_OUTPUTCLR10_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos) /*!< SCT OUTPUTCLR10: CLRn14 Mask */ -#define SCT_OUTPUTCLR10_CLRn15_Pos 15 /*!< SCT OUTPUTCLR10: CLRn15 Position */ -#define SCT_OUTPUTCLR10_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos) /*!< SCT OUTPUTCLR10: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET11 ---------------------------------------- -#define SCT_OUTPUTSET11_SETn0_Pos 0 /*!< SCT OUTPUTSET11: SETn0 Position */ -#define SCT_OUTPUTSET11_SETn0_Msk (0x01UL << SCT_OUTPUTSET11_SETn0_Pos) /*!< SCT OUTPUTSET11: SETn0 Mask */ -#define SCT_OUTPUTSET11_SETn1_Pos 1 /*!< SCT OUTPUTSET11: SETn1 Position */ -#define SCT_OUTPUTSET11_SETn1_Msk (0x01UL << SCT_OUTPUTSET11_SETn1_Pos) /*!< SCT OUTPUTSET11: SETn1 Mask */ -#define SCT_OUTPUTSET11_SETn2_Pos 2 /*!< SCT OUTPUTSET11: SETn2 Position */ -#define SCT_OUTPUTSET11_SETn2_Msk (0x01UL << SCT_OUTPUTSET11_SETn2_Pos) /*!< SCT OUTPUTSET11: SETn2 Mask */ -#define SCT_OUTPUTSET11_SETn3_Pos 3 /*!< SCT OUTPUTSET11: SETn3 Position */ -#define SCT_OUTPUTSET11_SETn3_Msk (0x01UL << SCT_OUTPUTSET11_SETn3_Pos) /*!< SCT OUTPUTSET11: SETn3 Mask */ -#define SCT_OUTPUTSET11_SETn4_Pos 4 /*!< SCT OUTPUTSET11: SETn4 Position */ -#define SCT_OUTPUTSET11_SETn4_Msk (0x01UL << SCT_OUTPUTSET11_SETn4_Pos) /*!< SCT OUTPUTSET11: SETn4 Mask */ -#define SCT_OUTPUTSET11_SETn5_Pos 5 /*!< SCT OUTPUTSET11: SETn5 Position */ -#define SCT_OUTPUTSET11_SETn5_Msk (0x01UL << SCT_OUTPUTSET11_SETn5_Pos) /*!< SCT OUTPUTSET11: SETn5 Mask */ -#define SCT_OUTPUTSET11_SETn6_Pos 6 /*!< SCT OUTPUTSET11: SETn6 Position */ -#define SCT_OUTPUTSET11_SETn6_Msk (0x01UL << SCT_OUTPUTSET11_SETn6_Pos) /*!< SCT OUTPUTSET11: SETn6 Mask */ -#define SCT_OUTPUTSET11_SETn7_Pos 7 /*!< SCT OUTPUTSET11: SETn7 Position */ -#define SCT_OUTPUTSET11_SETn7_Msk (0x01UL << SCT_OUTPUTSET11_SETn7_Pos) /*!< SCT OUTPUTSET11: SETn7 Mask */ -#define SCT_OUTPUTSET11_SETn8_Pos 8 /*!< SCT OUTPUTSET11: SETn8 Position */ -#define SCT_OUTPUTSET11_SETn8_Msk (0x01UL << SCT_OUTPUTSET11_SETn8_Pos) /*!< SCT OUTPUTSET11: SETn8 Mask */ -#define SCT_OUTPUTSET11_SETn9_Pos 9 /*!< SCT OUTPUTSET11: SETn9 Position */ -#define SCT_OUTPUTSET11_SETn9_Msk (0x01UL << SCT_OUTPUTSET11_SETn9_Pos) /*!< SCT OUTPUTSET11: SETn9 Mask */ -#define SCT_OUTPUTSET11_SETn10_Pos 10 /*!< SCT OUTPUTSET11: SETn10 Position */ -#define SCT_OUTPUTSET11_SETn10_Msk (0x01UL << SCT_OUTPUTSET11_SETn10_Pos) /*!< SCT OUTPUTSET11: SETn10 Mask */ -#define SCT_OUTPUTSET11_SETn11_Pos 11 /*!< SCT OUTPUTSET11: SETn11 Position */ -#define SCT_OUTPUTSET11_SETn11_Msk (0x01UL << SCT_OUTPUTSET11_SETn11_Pos) /*!< SCT OUTPUTSET11: SETn11 Mask */ -#define SCT_OUTPUTSET11_SETn12_Pos 12 /*!< SCT OUTPUTSET11: SETn12 Position */ -#define SCT_OUTPUTSET11_SETn12_Msk (0x01UL << SCT_OUTPUTSET11_SETn12_Pos) /*!< SCT OUTPUTSET11: SETn12 Mask */ -#define SCT_OUTPUTSET11_SETn13_Pos 13 /*!< SCT OUTPUTSET11: SETn13 Position */ -#define SCT_OUTPUTSET11_SETn13_Msk (0x01UL << SCT_OUTPUTSET11_SETn13_Pos) /*!< SCT OUTPUTSET11: SETn13 Mask */ -#define SCT_OUTPUTSET11_SETn14_Pos 14 /*!< SCT OUTPUTSET11: SETn14 Position */ -#define SCT_OUTPUTSET11_SETn14_Msk (0x01UL << SCT_OUTPUTSET11_SETn14_Pos) /*!< SCT OUTPUTSET11: SETn14 Mask */ -#define SCT_OUTPUTSET11_SETn15_Pos 15 /*!< SCT OUTPUTSET11: SETn15 Position */ -#define SCT_OUTPUTSET11_SETn15_Msk (0x01UL << SCT_OUTPUTSET11_SETn15_Pos) /*!< SCT OUTPUTSET11: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR11 ---------------------------------------- -#define SCT_OUTPUTCLR11_CLRn0_Pos 0 /*!< SCT OUTPUTCLR11: CLRn0 Position */ -#define SCT_OUTPUTCLR11_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos) /*!< SCT OUTPUTCLR11: CLRn0 Mask */ -#define SCT_OUTPUTCLR11_CLRn1_Pos 1 /*!< SCT OUTPUTCLR11: CLRn1 Position */ -#define SCT_OUTPUTCLR11_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos) /*!< SCT OUTPUTCLR11: CLRn1 Mask */ -#define SCT_OUTPUTCLR11_CLRn2_Pos 2 /*!< SCT OUTPUTCLR11: CLRn2 Position */ -#define SCT_OUTPUTCLR11_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos) /*!< SCT OUTPUTCLR11: CLRn2 Mask */ -#define SCT_OUTPUTCLR11_CLRn3_Pos 3 /*!< SCT OUTPUTCLR11: CLRn3 Position */ -#define SCT_OUTPUTCLR11_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos) /*!< SCT OUTPUTCLR11: CLRn3 Mask */ -#define SCT_OUTPUTCLR11_CLRn4_Pos 4 /*!< SCT OUTPUTCLR11: CLRn4 Position */ -#define SCT_OUTPUTCLR11_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos) /*!< SCT OUTPUTCLR11: CLRn4 Mask */ -#define SCT_OUTPUTCLR11_CLRn5_Pos 5 /*!< SCT OUTPUTCLR11: CLRn5 Position */ -#define SCT_OUTPUTCLR11_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos) /*!< SCT OUTPUTCLR11: CLRn5 Mask */ -#define SCT_OUTPUTCLR11_CLRn6_Pos 6 /*!< SCT OUTPUTCLR11: CLRn6 Position */ -#define SCT_OUTPUTCLR11_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos) /*!< SCT OUTPUTCLR11: CLRn6 Mask */ -#define SCT_OUTPUTCLR11_CLRn7_Pos 7 /*!< SCT OUTPUTCLR11: CLRn7 Position */ -#define SCT_OUTPUTCLR11_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos) /*!< SCT OUTPUTCLR11: CLRn7 Mask */ -#define SCT_OUTPUTCLR11_CLRn8_Pos 8 /*!< SCT OUTPUTCLR11: CLRn8 Position */ -#define SCT_OUTPUTCLR11_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos) /*!< SCT OUTPUTCLR11: CLRn8 Mask */ -#define SCT_OUTPUTCLR11_CLRn9_Pos 9 /*!< SCT OUTPUTCLR11: CLRn9 Position */ -#define SCT_OUTPUTCLR11_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos) /*!< SCT OUTPUTCLR11: CLRn9 Mask */ -#define SCT_OUTPUTCLR11_CLRn10_Pos 10 /*!< SCT OUTPUTCLR11: CLRn10 Position */ -#define SCT_OUTPUTCLR11_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos) /*!< SCT OUTPUTCLR11: CLRn10 Mask */ -#define SCT_OUTPUTCLR11_CLRn11_Pos 11 /*!< SCT OUTPUTCLR11: CLRn11 Position */ -#define SCT_OUTPUTCLR11_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos) /*!< SCT OUTPUTCLR11: CLRn11 Mask */ -#define SCT_OUTPUTCLR11_CLRn12_Pos 12 /*!< SCT OUTPUTCLR11: CLRn12 Position */ -#define SCT_OUTPUTCLR11_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos) /*!< SCT OUTPUTCLR11: CLRn12 Mask */ -#define SCT_OUTPUTCLR11_CLRn13_Pos 13 /*!< SCT OUTPUTCLR11: CLRn13 Position */ -#define SCT_OUTPUTCLR11_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos) /*!< SCT OUTPUTCLR11: CLRn13 Mask */ -#define SCT_OUTPUTCLR11_CLRn14_Pos 14 /*!< SCT OUTPUTCLR11: CLRn14 Position */ -#define SCT_OUTPUTCLR11_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos) /*!< SCT OUTPUTCLR11: CLRn14 Mask */ -#define SCT_OUTPUTCLR11_CLRn15_Pos 15 /*!< SCT OUTPUTCLR11: CLRn15 Position */ -#define SCT_OUTPUTCLR11_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos) /*!< SCT OUTPUTCLR11: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET12 ---------------------------------------- -#define SCT_OUTPUTSET12_SETn0_Pos 0 /*!< SCT OUTPUTSET12: SETn0 Position */ -#define SCT_OUTPUTSET12_SETn0_Msk (0x01UL << SCT_OUTPUTSET12_SETn0_Pos) /*!< SCT OUTPUTSET12: SETn0 Mask */ -#define SCT_OUTPUTSET12_SETn1_Pos 1 /*!< SCT OUTPUTSET12: SETn1 Position */ -#define SCT_OUTPUTSET12_SETn1_Msk (0x01UL << SCT_OUTPUTSET12_SETn1_Pos) /*!< SCT OUTPUTSET12: SETn1 Mask */ -#define SCT_OUTPUTSET12_SETn2_Pos 2 /*!< SCT OUTPUTSET12: SETn2 Position */ -#define SCT_OUTPUTSET12_SETn2_Msk (0x01UL << SCT_OUTPUTSET12_SETn2_Pos) /*!< SCT OUTPUTSET12: SETn2 Mask */ -#define SCT_OUTPUTSET12_SETn3_Pos 3 /*!< SCT OUTPUTSET12: SETn3 Position */ -#define SCT_OUTPUTSET12_SETn3_Msk (0x01UL << SCT_OUTPUTSET12_SETn3_Pos) /*!< SCT OUTPUTSET12: SETn3 Mask */ -#define SCT_OUTPUTSET12_SETn4_Pos 4 /*!< SCT OUTPUTSET12: SETn4 Position */ -#define SCT_OUTPUTSET12_SETn4_Msk (0x01UL << SCT_OUTPUTSET12_SETn4_Pos) /*!< SCT OUTPUTSET12: SETn4 Mask */ -#define SCT_OUTPUTSET12_SETn5_Pos 5 /*!< SCT OUTPUTSET12: SETn5 Position */ -#define SCT_OUTPUTSET12_SETn5_Msk (0x01UL << SCT_OUTPUTSET12_SETn5_Pos) /*!< SCT OUTPUTSET12: SETn5 Mask */ -#define SCT_OUTPUTSET12_SETn6_Pos 6 /*!< SCT OUTPUTSET12: SETn6 Position */ -#define SCT_OUTPUTSET12_SETn6_Msk (0x01UL << SCT_OUTPUTSET12_SETn6_Pos) /*!< SCT OUTPUTSET12: SETn6 Mask */ -#define SCT_OUTPUTSET12_SETn7_Pos 7 /*!< SCT OUTPUTSET12: SETn7 Position */ -#define SCT_OUTPUTSET12_SETn7_Msk (0x01UL << SCT_OUTPUTSET12_SETn7_Pos) /*!< SCT OUTPUTSET12: SETn7 Mask */ -#define SCT_OUTPUTSET12_SETn8_Pos 8 /*!< SCT OUTPUTSET12: SETn8 Position */ -#define SCT_OUTPUTSET12_SETn8_Msk (0x01UL << SCT_OUTPUTSET12_SETn8_Pos) /*!< SCT OUTPUTSET12: SETn8 Mask */ -#define SCT_OUTPUTSET12_SETn9_Pos 9 /*!< SCT OUTPUTSET12: SETn9 Position */ -#define SCT_OUTPUTSET12_SETn9_Msk (0x01UL << SCT_OUTPUTSET12_SETn9_Pos) /*!< SCT OUTPUTSET12: SETn9 Mask */ -#define SCT_OUTPUTSET12_SETn10_Pos 10 /*!< SCT OUTPUTSET12: SETn10 Position */ -#define SCT_OUTPUTSET12_SETn10_Msk (0x01UL << SCT_OUTPUTSET12_SETn10_Pos) /*!< SCT OUTPUTSET12: SETn10 Mask */ -#define SCT_OUTPUTSET12_SETn11_Pos 11 /*!< SCT OUTPUTSET12: SETn11 Position */ -#define SCT_OUTPUTSET12_SETn11_Msk (0x01UL << SCT_OUTPUTSET12_SETn11_Pos) /*!< SCT OUTPUTSET12: SETn11 Mask */ -#define SCT_OUTPUTSET12_SETn12_Pos 12 /*!< SCT OUTPUTSET12: SETn12 Position */ -#define SCT_OUTPUTSET12_SETn12_Msk (0x01UL << SCT_OUTPUTSET12_SETn12_Pos) /*!< SCT OUTPUTSET12: SETn12 Mask */ -#define SCT_OUTPUTSET12_SETn13_Pos 13 /*!< SCT OUTPUTSET12: SETn13 Position */ -#define SCT_OUTPUTSET12_SETn13_Msk (0x01UL << SCT_OUTPUTSET12_SETn13_Pos) /*!< SCT OUTPUTSET12: SETn13 Mask */ -#define SCT_OUTPUTSET12_SETn14_Pos 14 /*!< SCT OUTPUTSET12: SETn14 Position */ -#define SCT_OUTPUTSET12_SETn14_Msk (0x01UL << SCT_OUTPUTSET12_SETn14_Pos) /*!< SCT OUTPUTSET12: SETn14 Mask */ -#define SCT_OUTPUTSET12_SETn15_Pos 15 /*!< SCT OUTPUTSET12: SETn15 Position */ -#define SCT_OUTPUTSET12_SETn15_Msk (0x01UL << SCT_OUTPUTSET12_SETn15_Pos) /*!< SCT OUTPUTSET12: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR12 ---------------------------------------- -#define SCT_OUTPUTCLR12_CLRn0_Pos 0 /*!< SCT OUTPUTCLR12: CLRn0 Position */ -#define SCT_OUTPUTCLR12_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos) /*!< SCT OUTPUTCLR12: CLRn0 Mask */ -#define SCT_OUTPUTCLR12_CLRn1_Pos 1 /*!< SCT OUTPUTCLR12: CLRn1 Position */ -#define SCT_OUTPUTCLR12_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos) /*!< SCT OUTPUTCLR12: CLRn1 Mask */ -#define SCT_OUTPUTCLR12_CLRn2_Pos 2 /*!< SCT OUTPUTCLR12: CLRn2 Position */ -#define SCT_OUTPUTCLR12_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos) /*!< SCT OUTPUTCLR12: CLRn2 Mask */ -#define SCT_OUTPUTCLR12_CLRn3_Pos 3 /*!< SCT OUTPUTCLR12: CLRn3 Position */ -#define SCT_OUTPUTCLR12_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos) /*!< SCT OUTPUTCLR12: CLRn3 Mask */ -#define SCT_OUTPUTCLR12_CLRn4_Pos 4 /*!< SCT OUTPUTCLR12: CLRn4 Position */ -#define SCT_OUTPUTCLR12_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos) /*!< SCT OUTPUTCLR12: CLRn4 Mask */ -#define SCT_OUTPUTCLR12_CLRn5_Pos 5 /*!< SCT OUTPUTCLR12: CLRn5 Position */ -#define SCT_OUTPUTCLR12_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos) /*!< SCT OUTPUTCLR12: CLRn5 Mask */ -#define SCT_OUTPUTCLR12_CLRn6_Pos 6 /*!< SCT OUTPUTCLR12: CLRn6 Position */ -#define SCT_OUTPUTCLR12_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos) /*!< SCT OUTPUTCLR12: CLRn6 Mask */ -#define SCT_OUTPUTCLR12_CLRn7_Pos 7 /*!< SCT OUTPUTCLR12: CLRn7 Position */ -#define SCT_OUTPUTCLR12_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos) /*!< SCT OUTPUTCLR12: CLRn7 Mask */ -#define SCT_OUTPUTCLR12_CLRn8_Pos 8 /*!< SCT OUTPUTCLR12: CLRn8 Position */ -#define SCT_OUTPUTCLR12_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos) /*!< SCT OUTPUTCLR12: CLRn8 Mask */ -#define SCT_OUTPUTCLR12_CLRn9_Pos 9 /*!< SCT OUTPUTCLR12: CLRn9 Position */ -#define SCT_OUTPUTCLR12_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos) /*!< SCT OUTPUTCLR12: CLRn9 Mask */ -#define SCT_OUTPUTCLR12_CLRn10_Pos 10 /*!< SCT OUTPUTCLR12: CLRn10 Position */ -#define SCT_OUTPUTCLR12_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos) /*!< SCT OUTPUTCLR12: CLRn10 Mask */ -#define SCT_OUTPUTCLR12_CLRn11_Pos 11 /*!< SCT OUTPUTCLR12: CLRn11 Position */ -#define SCT_OUTPUTCLR12_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos) /*!< SCT OUTPUTCLR12: CLRn11 Mask */ -#define SCT_OUTPUTCLR12_CLRn12_Pos 12 /*!< SCT OUTPUTCLR12: CLRn12 Position */ -#define SCT_OUTPUTCLR12_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos) /*!< SCT OUTPUTCLR12: CLRn12 Mask */ -#define SCT_OUTPUTCLR12_CLRn13_Pos 13 /*!< SCT OUTPUTCLR12: CLRn13 Position */ -#define SCT_OUTPUTCLR12_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos) /*!< SCT OUTPUTCLR12: CLRn13 Mask */ -#define SCT_OUTPUTCLR12_CLRn14_Pos 14 /*!< SCT OUTPUTCLR12: CLRn14 Position */ -#define SCT_OUTPUTCLR12_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos) /*!< SCT OUTPUTCLR12: CLRn14 Mask */ -#define SCT_OUTPUTCLR12_CLRn15_Pos 15 /*!< SCT OUTPUTCLR12: CLRn15 Position */ -#define SCT_OUTPUTCLR12_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos) /*!< SCT OUTPUTCLR12: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET13 ---------------------------------------- -#define SCT_OUTPUTSET13_SETn0_Pos 0 /*!< SCT OUTPUTSET13: SETn0 Position */ -#define SCT_OUTPUTSET13_SETn0_Msk (0x01UL << SCT_OUTPUTSET13_SETn0_Pos) /*!< SCT OUTPUTSET13: SETn0 Mask */ -#define SCT_OUTPUTSET13_SETn1_Pos 1 /*!< SCT OUTPUTSET13: SETn1 Position */ -#define SCT_OUTPUTSET13_SETn1_Msk (0x01UL << SCT_OUTPUTSET13_SETn1_Pos) /*!< SCT OUTPUTSET13: SETn1 Mask */ -#define SCT_OUTPUTSET13_SETn2_Pos 2 /*!< SCT OUTPUTSET13: SETn2 Position */ -#define SCT_OUTPUTSET13_SETn2_Msk (0x01UL << SCT_OUTPUTSET13_SETn2_Pos) /*!< SCT OUTPUTSET13: SETn2 Mask */ -#define SCT_OUTPUTSET13_SETn3_Pos 3 /*!< SCT OUTPUTSET13: SETn3 Position */ -#define SCT_OUTPUTSET13_SETn3_Msk (0x01UL << SCT_OUTPUTSET13_SETn3_Pos) /*!< SCT OUTPUTSET13: SETn3 Mask */ -#define SCT_OUTPUTSET13_SETn4_Pos 4 /*!< SCT OUTPUTSET13: SETn4 Position */ -#define SCT_OUTPUTSET13_SETn4_Msk (0x01UL << SCT_OUTPUTSET13_SETn4_Pos) /*!< SCT OUTPUTSET13: SETn4 Mask */ -#define SCT_OUTPUTSET13_SETn5_Pos 5 /*!< SCT OUTPUTSET13: SETn5 Position */ -#define SCT_OUTPUTSET13_SETn5_Msk (0x01UL << SCT_OUTPUTSET13_SETn5_Pos) /*!< SCT OUTPUTSET13: SETn5 Mask */ -#define SCT_OUTPUTSET13_SETn6_Pos 6 /*!< SCT OUTPUTSET13: SETn6 Position */ -#define SCT_OUTPUTSET13_SETn6_Msk (0x01UL << SCT_OUTPUTSET13_SETn6_Pos) /*!< SCT OUTPUTSET13: SETn6 Mask */ -#define SCT_OUTPUTSET13_SETn7_Pos 7 /*!< SCT OUTPUTSET13: SETn7 Position */ -#define SCT_OUTPUTSET13_SETn7_Msk (0x01UL << SCT_OUTPUTSET13_SETn7_Pos) /*!< SCT OUTPUTSET13: SETn7 Mask */ -#define SCT_OUTPUTSET13_SETn8_Pos 8 /*!< SCT OUTPUTSET13: SETn8 Position */ -#define SCT_OUTPUTSET13_SETn8_Msk (0x01UL << SCT_OUTPUTSET13_SETn8_Pos) /*!< SCT OUTPUTSET13: SETn8 Mask */ -#define SCT_OUTPUTSET13_SETn9_Pos 9 /*!< SCT OUTPUTSET13: SETn9 Position */ -#define SCT_OUTPUTSET13_SETn9_Msk (0x01UL << SCT_OUTPUTSET13_SETn9_Pos) /*!< SCT OUTPUTSET13: SETn9 Mask */ -#define SCT_OUTPUTSET13_SETn10_Pos 10 /*!< SCT OUTPUTSET13: SETn10 Position */ -#define SCT_OUTPUTSET13_SETn10_Msk (0x01UL << SCT_OUTPUTSET13_SETn10_Pos) /*!< SCT OUTPUTSET13: SETn10 Mask */ -#define SCT_OUTPUTSET13_SETn11_Pos 11 /*!< SCT OUTPUTSET13: SETn11 Position */ -#define SCT_OUTPUTSET13_SETn11_Msk (0x01UL << SCT_OUTPUTSET13_SETn11_Pos) /*!< SCT OUTPUTSET13: SETn11 Mask */ -#define SCT_OUTPUTSET13_SETn12_Pos 12 /*!< SCT OUTPUTSET13: SETn12 Position */ -#define SCT_OUTPUTSET13_SETn12_Msk (0x01UL << SCT_OUTPUTSET13_SETn12_Pos) /*!< SCT OUTPUTSET13: SETn12 Mask */ -#define SCT_OUTPUTSET13_SETn13_Pos 13 /*!< SCT OUTPUTSET13: SETn13 Position */ -#define SCT_OUTPUTSET13_SETn13_Msk (0x01UL << SCT_OUTPUTSET13_SETn13_Pos) /*!< SCT OUTPUTSET13: SETn13 Mask */ -#define SCT_OUTPUTSET13_SETn14_Pos 14 /*!< SCT OUTPUTSET13: SETn14 Position */ -#define SCT_OUTPUTSET13_SETn14_Msk (0x01UL << SCT_OUTPUTSET13_SETn14_Pos) /*!< SCT OUTPUTSET13: SETn14 Mask */ -#define SCT_OUTPUTSET13_SETn15_Pos 15 /*!< SCT OUTPUTSET13: SETn15 Position */ -#define SCT_OUTPUTSET13_SETn15_Msk (0x01UL << SCT_OUTPUTSET13_SETn15_Pos) /*!< SCT OUTPUTSET13: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR13 ---------------------------------------- -#define SCT_OUTPUTCLR13_CLRn0_Pos 0 /*!< SCT OUTPUTCLR13: CLRn0 Position */ -#define SCT_OUTPUTCLR13_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos) /*!< SCT OUTPUTCLR13: CLRn0 Mask */ -#define SCT_OUTPUTCLR13_CLRn1_Pos 1 /*!< SCT OUTPUTCLR13: CLRn1 Position */ -#define SCT_OUTPUTCLR13_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos) /*!< SCT OUTPUTCLR13: CLRn1 Mask */ -#define SCT_OUTPUTCLR13_CLRn2_Pos 2 /*!< SCT OUTPUTCLR13: CLRn2 Position */ -#define SCT_OUTPUTCLR13_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos) /*!< SCT OUTPUTCLR13: CLRn2 Mask */ -#define SCT_OUTPUTCLR13_CLRn3_Pos 3 /*!< SCT OUTPUTCLR13: CLRn3 Position */ -#define SCT_OUTPUTCLR13_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos) /*!< SCT OUTPUTCLR13: CLRn3 Mask */ -#define SCT_OUTPUTCLR13_CLRn4_Pos 4 /*!< SCT OUTPUTCLR13: CLRn4 Position */ -#define SCT_OUTPUTCLR13_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos) /*!< SCT OUTPUTCLR13: CLRn4 Mask */ -#define SCT_OUTPUTCLR13_CLRn5_Pos 5 /*!< SCT OUTPUTCLR13: CLRn5 Position */ -#define SCT_OUTPUTCLR13_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos) /*!< SCT OUTPUTCLR13: CLRn5 Mask */ -#define SCT_OUTPUTCLR13_CLRn6_Pos 6 /*!< SCT OUTPUTCLR13: CLRn6 Position */ -#define SCT_OUTPUTCLR13_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos) /*!< SCT OUTPUTCLR13: CLRn6 Mask */ -#define SCT_OUTPUTCLR13_CLRn7_Pos 7 /*!< SCT OUTPUTCLR13: CLRn7 Position */ -#define SCT_OUTPUTCLR13_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos) /*!< SCT OUTPUTCLR13: CLRn7 Mask */ -#define SCT_OUTPUTCLR13_CLRn8_Pos 8 /*!< SCT OUTPUTCLR13: CLRn8 Position */ -#define SCT_OUTPUTCLR13_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos) /*!< SCT OUTPUTCLR13: CLRn8 Mask */ -#define SCT_OUTPUTCLR13_CLRn9_Pos 9 /*!< SCT OUTPUTCLR13: CLRn9 Position */ -#define SCT_OUTPUTCLR13_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos) /*!< SCT OUTPUTCLR13: CLRn9 Mask */ -#define SCT_OUTPUTCLR13_CLRn10_Pos 10 /*!< SCT OUTPUTCLR13: CLRn10 Position */ -#define SCT_OUTPUTCLR13_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos) /*!< SCT OUTPUTCLR13: CLRn10 Mask */ -#define SCT_OUTPUTCLR13_CLRn11_Pos 11 /*!< SCT OUTPUTCLR13: CLRn11 Position */ -#define SCT_OUTPUTCLR13_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos) /*!< SCT OUTPUTCLR13: CLRn11 Mask */ -#define SCT_OUTPUTCLR13_CLRn12_Pos 12 /*!< SCT OUTPUTCLR13: CLRn12 Position */ -#define SCT_OUTPUTCLR13_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos) /*!< SCT OUTPUTCLR13: CLRn12 Mask */ -#define SCT_OUTPUTCLR13_CLRn13_Pos 13 /*!< SCT OUTPUTCLR13: CLRn13 Position */ -#define SCT_OUTPUTCLR13_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos) /*!< SCT OUTPUTCLR13: CLRn13 Mask */ -#define SCT_OUTPUTCLR13_CLRn14_Pos 14 /*!< SCT OUTPUTCLR13: CLRn14 Position */ -#define SCT_OUTPUTCLR13_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos) /*!< SCT OUTPUTCLR13: CLRn14 Mask */ -#define SCT_OUTPUTCLR13_CLRn15_Pos 15 /*!< SCT OUTPUTCLR13: CLRn15 Position */ -#define SCT_OUTPUTCLR13_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos) /*!< SCT OUTPUTCLR13: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET14 ---------------------------------------- -#define SCT_OUTPUTSET14_SETn0_Pos 0 /*!< SCT OUTPUTSET14: SETn0 Position */ -#define SCT_OUTPUTSET14_SETn0_Msk (0x01UL << SCT_OUTPUTSET14_SETn0_Pos) /*!< SCT OUTPUTSET14: SETn0 Mask */ -#define SCT_OUTPUTSET14_SETn1_Pos 1 /*!< SCT OUTPUTSET14: SETn1 Position */ -#define SCT_OUTPUTSET14_SETn1_Msk (0x01UL << SCT_OUTPUTSET14_SETn1_Pos) /*!< SCT OUTPUTSET14: SETn1 Mask */ -#define SCT_OUTPUTSET14_SETn2_Pos 2 /*!< SCT OUTPUTSET14: SETn2 Position */ -#define SCT_OUTPUTSET14_SETn2_Msk (0x01UL << SCT_OUTPUTSET14_SETn2_Pos) /*!< SCT OUTPUTSET14: SETn2 Mask */ -#define SCT_OUTPUTSET14_SETn3_Pos 3 /*!< SCT OUTPUTSET14: SETn3 Position */ -#define SCT_OUTPUTSET14_SETn3_Msk (0x01UL << SCT_OUTPUTSET14_SETn3_Pos) /*!< SCT OUTPUTSET14: SETn3 Mask */ -#define SCT_OUTPUTSET14_SETn4_Pos 4 /*!< SCT OUTPUTSET14: SETn4 Position */ -#define SCT_OUTPUTSET14_SETn4_Msk (0x01UL << SCT_OUTPUTSET14_SETn4_Pos) /*!< SCT OUTPUTSET14: SETn4 Mask */ -#define SCT_OUTPUTSET14_SETn5_Pos 5 /*!< SCT OUTPUTSET14: SETn5 Position */ -#define SCT_OUTPUTSET14_SETn5_Msk (0x01UL << SCT_OUTPUTSET14_SETn5_Pos) /*!< SCT OUTPUTSET14: SETn5 Mask */ -#define SCT_OUTPUTSET14_SETn6_Pos 6 /*!< SCT OUTPUTSET14: SETn6 Position */ -#define SCT_OUTPUTSET14_SETn6_Msk (0x01UL << SCT_OUTPUTSET14_SETn6_Pos) /*!< SCT OUTPUTSET14: SETn6 Mask */ -#define SCT_OUTPUTSET14_SETn7_Pos 7 /*!< SCT OUTPUTSET14: SETn7 Position */ -#define SCT_OUTPUTSET14_SETn7_Msk (0x01UL << SCT_OUTPUTSET14_SETn7_Pos) /*!< SCT OUTPUTSET14: SETn7 Mask */ -#define SCT_OUTPUTSET14_SETn8_Pos 8 /*!< SCT OUTPUTSET14: SETn8 Position */ -#define SCT_OUTPUTSET14_SETn8_Msk (0x01UL << SCT_OUTPUTSET14_SETn8_Pos) /*!< SCT OUTPUTSET14: SETn8 Mask */ -#define SCT_OUTPUTSET14_SETn9_Pos 9 /*!< SCT OUTPUTSET14: SETn9 Position */ -#define SCT_OUTPUTSET14_SETn9_Msk (0x01UL << SCT_OUTPUTSET14_SETn9_Pos) /*!< SCT OUTPUTSET14: SETn9 Mask */ -#define SCT_OUTPUTSET14_SETn10_Pos 10 /*!< SCT OUTPUTSET14: SETn10 Position */ -#define SCT_OUTPUTSET14_SETn10_Msk (0x01UL << SCT_OUTPUTSET14_SETn10_Pos) /*!< SCT OUTPUTSET14: SETn10 Mask */ -#define SCT_OUTPUTSET14_SETn11_Pos 11 /*!< SCT OUTPUTSET14: SETn11 Position */ -#define SCT_OUTPUTSET14_SETn11_Msk (0x01UL << SCT_OUTPUTSET14_SETn11_Pos) /*!< SCT OUTPUTSET14: SETn11 Mask */ -#define SCT_OUTPUTSET14_SETn12_Pos 12 /*!< SCT OUTPUTSET14: SETn12 Position */ -#define SCT_OUTPUTSET14_SETn12_Msk (0x01UL << SCT_OUTPUTSET14_SETn12_Pos) /*!< SCT OUTPUTSET14: SETn12 Mask */ -#define SCT_OUTPUTSET14_SETn13_Pos 13 /*!< SCT OUTPUTSET14: SETn13 Position */ -#define SCT_OUTPUTSET14_SETn13_Msk (0x01UL << SCT_OUTPUTSET14_SETn13_Pos) /*!< SCT OUTPUTSET14: SETn13 Mask */ -#define SCT_OUTPUTSET14_SETn14_Pos 14 /*!< SCT OUTPUTSET14: SETn14 Position */ -#define SCT_OUTPUTSET14_SETn14_Msk (0x01UL << SCT_OUTPUTSET14_SETn14_Pos) /*!< SCT OUTPUTSET14: SETn14 Mask */ -#define SCT_OUTPUTSET14_SETn15_Pos 15 /*!< SCT OUTPUTSET14: SETn15 Position */ -#define SCT_OUTPUTSET14_SETn15_Msk (0x01UL << SCT_OUTPUTSET14_SETn15_Pos) /*!< SCT OUTPUTSET14: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR14 ---------------------------------------- -#define SCT_OUTPUTCLR14_CLRn0_Pos 0 /*!< SCT OUTPUTCLR14: CLRn0 Position */ -#define SCT_OUTPUTCLR14_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos) /*!< SCT OUTPUTCLR14: CLRn0 Mask */ -#define SCT_OUTPUTCLR14_CLRn1_Pos 1 /*!< SCT OUTPUTCLR14: CLRn1 Position */ -#define SCT_OUTPUTCLR14_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos) /*!< SCT OUTPUTCLR14: CLRn1 Mask */ -#define SCT_OUTPUTCLR14_CLRn2_Pos 2 /*!< SCT OUTPUTCLR14: CLRn2 Position */ -#define SCT_OUTPUTCLR14_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos) /*!< SCT OUTPUTCLR14: CLRn2 Mask */ -#define SCT_OUTPUTCLR14_CLRn3_Pos 3 /*!< SCT OUTPUTCLR14: CLRn3 Position */ -#define SCT_OUTPUTCLR14_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos) /*!< SCT OUTPUTCLR14: CLRn3 Mask */ -#define SCT_OUTPUTCLR14_CLRn4_Pos 4 /*!< SCT OUTPUTCLR14: CLRn4 Position */ -#define SCT_OUTPUTCLR14_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos) /*!< SCT OUTPUTCLR14: CLRn4 Mask */ -#define SCT_OUTPUTCLR14_CLRn5_Pos 5 /*!< SCT OUTPUTCLR14: CLRn5 Position */ -#define SCT_OUTPUTCLR14_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos) /*!< SCT OUTPUTCLR14: CLRn5 Mask */ -#define SCT_OUTPUTCLR14_CLRn6_Pos 6 /*!< SCT OUTPUTCLR14: CLRn6 Position */ -#define SCT_OUTPUTCLR14_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos) /*!< SCT OUTPUTCLR14: CLRn6 Mask */ -#define SCT_OUTPUTCLR14_CLRn7_Pos 7 /*!< SCT OUTPUTCLR14: CLRn7 Position */ -#define SCT_OUTPUTCLR14_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos) /*!< SCT OUTPUTCLR14: CLRn7 Mask */ -#define SCT_OUTPUTCLR14_CLRn8_Pos 8 /*!< SCT OUTPUTCLR14: CLRn8 Position */ -#define SCT_OUTPUTCLR14_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos) /*!< SCT OUTPUTCLR14: CLRn8 Mask */ -#define SCT_OUTPUTCLR14_CLRn9_Pos 9 /*!< SCT OUTPUTCLR14: CLRn9 Position */ -#define SCT_OUTPUTCLR14_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos) /*!< SCT OUTPUTCLR14: CLRn9 Mask */ -#define SCT_OUTPUTCLR14_CLRn10_Pos 10 /*!< SCT OUTPUTCLR14: CLRn10 Position */ -#define SCT_OUTPUTCLR14_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos) /*!< SCT OUTPUTCLR14: CLRn10 Mask */ -#define SCT_OUTPUTCLR14_CLRn11_Pos 11 /*!< SCT OUTPUTCLR14: CLRn11 Position */ -#define SCT_OUTPUTCLR14_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos) /*!< SCT OUTPUTCLR14: CLRn11 Mask */ -#define SCT_OUTPUTCLR14_CLRn12_Pos 12 /*!< SCT OUTPUTCLR14: CLRn12 Position */ -#define SCT_OUTPUTCLR14_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos) /*!< SCT OUTPUTCLR14: CLRn12 Mask */ -#define SCT_OUTPUTCLR14_CLRn13_Pos 13 /*!< SCT OUTPUTCLR14: CLRn13 Position */ -#define SCT_OUTPUTCLR14_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos) /*!< SCT OUTPUTCLR14: CLRn13 Mask */ -#define SCT_OUTPUTCLR14_CLRn14_Pos 14 /*!< SCT OUTPUTCLR14: CLRn14 Position */ -#define SCT_OUTPUTCLR14_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos) /*!< SCT OUTPUTCLR14: CLRn14 Mask */ -#define SCT_OUTPUTCLR14_CLRn15_Pos 15 /*!< SCT OUTPUTCLR14: CLRn15 Position */ -#define SCT_OUTPUTCLR14_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos) /*!< SCT OUTPUTCLR14: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET15 ---------------------------------------- -#define SCT_OUTPUTSET15_SETn0_Pos 0 /*!< SCT OUTPUTSET15: SETn0 Position */ -#define SCT_OUTPUTSET15_SETn0_Msk (0x01UL << SCT_OUTPUTSET15_SETn0_Pos) /*!< SCT OUTPUTSET15: SETn0 Mask */ -#define SCT_OUTPUTSET15_SETn1_Pos 1 /*!< SCT OUTPUTSET15: SETn1 Position */ -#define SCT_OUTPUTSET15_SETn1_Msk (0x01UL << SCT_OUTPUTSET15_SETn1_Pos) /*!< SCT OUTPUTSET15: SETn1 Mask */ -#define SCT_OUTPUTSET15_SETn2_Pos 2 /*!< SCT OUTPUTSET15: SETn2 Position */ -#define SCT_OUTPUTSET15_SETn2_Msk (0x01UL << SCT_OUTPUTSET15_SETn2_Pos) /*!< SCT OUTPUTSET15: SETn2 Mask */ -#define SCT_OUTPUTSET15_SETn3_Pos 3 /*!< SCT OUTPUTSET15: SETn3 Position */ -#define SCT_OUTPUTSET15_SETn3_Msk (0x01UL << SCT_OUTPUTSET15_SETn3_Pos) /*!< SCT OUTPUTSET15: SETn3 Mask */ -#define SCT_OUTPUTSET15_SETn4_Pos 4 /*!< SCT OUTPUTSET15: SETn4 Position */ -#define SCT_OUTPUTSET15_SETn4_Msk (0x01UL << SCT_OUTPUTSET15_SETn4_Pos) /*!< SCT OUTPUTSET15: SETn4 Mask */ -#define SCT_OUTPUTSET15_SETn5_Pos 5 /*!< SCT OUTPUTSET15: SETn5 Position */ -#define SCT_OUTPUTSET15_SETn5_Msk (0x01UL << SCT_OUTPUTSET15_SETn5_Pos) /*!< SCT OUTPUTSET15: SETn5 Mask */ -#define SCT_OUTPUTSET15_SETn6_Pos 6 /*!< SCT OUTPUTSET15: SETn6 Position */ -#define SCT_OUTPUTSET15_SETn6_Msk (0x01UL << SCT_OUTPUTSET15_SETn6_Pos) /*!< SCT OUTPUTSET15: SETn6 Mask */ -#define SCT_OUTPUTSET15_SETn7_Pos 7 /*!< SCT OUTPUTSET15: SETn7 Position */ -#define SCT_OUTPUTSET15_SETn7_Msk (0x01UL << SCT_OUTPUTSET15_SETn7_Pos) /*!< SCT OUTPUTSET15: SETn7 Mask */ -#define SCT_OUTPUTSET15_SETn8_Pos 8 /*!< SCT OUTPUTSET15: SETn8 Position */ -#define SCT_OUTPUTSET15_SETn8_Msk (0x01UL << SCT_OUTPUTSET15_SETn8_Pos) /*!< SCT OUTPUTSET15: SETn8 Mask */ -#define SCT_OUTPUTSET15_SETn9_Pos 9 /*!< SCT OUTPUTSET15: SETn9 Position */ -#define SCT_OUTPUTSET15_SETn9_Msk (0x01UL << SCT_OUTPUTSET15_SETn9_Pos) /*!< SCT OUTPUTSET15: SETn9 Mask */ -#define SCT_OUTPUTSET15_SETn10_Pos 10 /*!< SCT OUTPUTSET15: SETn10 Position */ -#define SCT_OUTPUTSET15_SETn10_Msk (0x01UL << SCT_OUTPUTSET15_SETn10_Pos) /*!< SCT OUTPUTSET15: SETn10 Mask */ -#define SCT_OUTPUTSET15_SETn11_Pos 11 /*!< SCT OUTPUTSET15: SETn11 Position */ -#define SCT_OUTPUTSET15_SETn11_Msk (0x01UL << SCT_OUTPUTSET15_SETn11_Pos) /*!< SCT OUTPUTSET15: SETn11 Mask */ -#define SCT_OUTPUTSET15_SETn12_Pos 12 /*!< SCT OUTPUTSET15: SETn12 Position */ -#define SCT_OUTPUTSET15_SETn12_Msk (0x01UL << SCT_OUTPUTSET15_SETn12_Pos) /*!< SCT OUTPUTSET15: SETn12 Mask */ -#define SCT_OUTPUTSET15_SETn13_Pos 13 /*!< SCT OUTPUTSET15: SETn13 Position */ -#define SCT_OUTPUTSET15_SETn13_Msk (0x01UL << SCT_OUTPUTSET15_SETn13_Pos) /*!< SCT OUTPUTSET15: SETn13 Mask */ -#define SCT_OUTPUTSET15_SETn14_Pos 14 /*!< SCT OUTPUTSET15: SETn14 Position */ -#define SCT_OUTPUTSET15_SETn14_Msk (0x01UL << SCT_OUTPUTSET15_SETn14_Pos) /*!< SCT OUTPUTSET15: SETn14 Mask */ -#define SCT_OUTPUTSET15_SETn15_Pos 15 /*!< SCT OUTPUTSET15: SETn15 Position */ -#define SCT_OUTPUTSET15_SETn15_Msk (0x01UL << SCT_OUTPUTSET15_SETn15_Pos) /*!< SCT OUTPUTSET15: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR15 ---------------------------------------- -#define SCT_OUTPUTCLR15_CLRn0_Pos 0 /*!< SCT OUTPUTCLR15: CLRn0 Position */ -#define SCT_OUTPUTCLR15_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos) /*!< SCT OUTPUTCLR15: CLRn0 Mask */ -#define SCT_OUTPUTCLR15_CLRn1_Pos 1 /*!< SCT OUTPUTCLR15: CLRn1 Position */ -#define SCT_OUTPUTCLR15_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos) /*!< SCT OUTPUTCLR15: CLRn1 Mask */ -#define SCT_OUTPUTCLR15_CLRn2_Pos 2 /*!< SCT OUTPUTCLR15: CLRn2 Position */ -#define SCT_OUTPUTCLR15_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos) /*!< SCT OUTPUTCLR15: CLRn2 Mask */ -#define SCT_OUTPUTCLR15_CLRn3_Pos 3 /*!< SCT OUTPUTCLR15: CLRn3 Position */ -#define SCT_OUTPUTCLR15_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos) /*!< SCT OUTPUTCLR15: CLRn3 Mask */ -#define SCT_OUTPUTCLR15_CLRn4_Pos 4 /*!< SCT OUTPUTCLR15: CLRn4 Position */ -#define SCT_OUTPUTCLR15_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos) /*!< SCT OUTPUTCLR15: CLRn4 Mask */ -#define SCT_OUTPUTCLR15_CLRn5_Pos 5 /*!< SCT OUTPUTCLR15: CLRn5 Position */ -#define SCT_OUTPUTCLR15_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos) /*!< SCT OUTPUTCLR15: CLRn5 Mask */ -#define SCT_OUTPUTCLR15_CLRn6_Pos 6 /*!< SCT OUTPUTCLR15: CLRn6 Position */ -#define SCT_OUTPUTCLR15_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos) /*!< SCT OUTPUTCLR15: CLRn6 Mask */ -#define SCT_OUTPUTCLR15_CLRn7_Pos 7 /*!< SCT OUTPUTCLR15: CLRn7 Position */ -#define SCT_OUTPUTCLR15_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos) /*!< SCT OUTPUTCLR15: CLRn7 Mask */ -#define SCT_OUTPUTCLR15_CLRn8_Pos 8 /*!< SCT OUTPUTCLR15: CLRn8 Position */ -#define SCT_OUTPUTCLR15_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos) /*!< SCT OUTPUTCLR15: CLRn8 Mask */ -#define SCT_OUTPUTCLR15_CLRn9_Pos 9 /*!< SCT OUTPUTCLR15: CLRn9 Position */ -#define SCT_OUTPUTCLR15_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos) /*!< SCT OUTPUTCLR15: CLRn9 Mask */ -#define SCT_OUTPUTCLR15_CLRn10_Pos 10 /*!< SCT OUTPUTCLR15: CLRn10 Position */ -#define SCT_OUTPUTCLR15_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos) /*!< SCT OUTPUTCLR15: CLRn10 Mask */ -#define SCT_OUTPUTCLR15_CLRn11_Pos 11 /*!< SCT OUTPUTCLR15: CLRn11 Position */ -#define SCT_OUTPUTCLR15_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos) /*!< SCT OUTPUTCLR15: CLRn11 Mask */ -#define SCT_OUTPUTCLR15_CLRn12_Pos 12 /*!< SCT OUTPUTCLR15: CLRn12 Position */ -#define SCT_OUTPUTCLR15_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos) /*!< SCT OUTPUTCLR15: CLRn12 Mask */ -#define SCT_OUTPUTCLR15_CLRn13_Pos 13 /*!< SCT OUTPUTCLR15: CLRn13 Position */ -#define SCT_OUTPUTCLR15_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos) /*!< SCT OUTPUTCLR15: CLRn13 Mask */ -#define SCT_OUTPUTCLR15_CLRn14_Pos 14 /*!< SCT OUTPUTCLR15: CLRn14 Position */ -#define SCT_OUTPUTCLR15_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos) /*!< SCT OUTPUTCLR15: CLRn14 Mask */ -#define SCT_OUTPUTCLR15_CLRn15_Pos 15 /*!< SCT OUTPUTCLR15: CLRn15 Position */ -#define SCT_OUTPUTCLR15_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos) /*!< SCT OUTPUTCLR15: CLRn15 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPDMA Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// -------------------------------------- GPDMA_INTSTAT ----------------------------------------- -#define GPDMA_INTSTAT_INTSTAT0_Pos 0 /*!< GPDMA INTSTAT: INTSTAT0 Position */ -#define GPDMA_INTSTAT_INTSTAT0_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos) /*!< GPDMA INTSTAT: INTSTAT0 Mask */ -#define GPDMA_INTSTAT_INTSTAT1_Pos 1 /*!< GPDMA INTSTAT: INTSTAT1 Position */ -#define GPDMA_INTSTAT_INTSTAT1_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos) /*!< GPDMA INTSTAT: INTSTAT1 Mask */ -#define GPDMA_INTSTAT_INTSTAT2_Pos 2 /*!< GPDMA INTSTAT: INTSTAT2 Position */ -#define GPDMA_INTSTAT_INTSTAT2_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos) /*!< GPDMA INTSTAT: INTSTAT2 Mask */ -#define GPDMA_INTSTAT_INTSTAT3_Pos 3 /*!< GPDMA INTSTAT: INTSTAT3 Position */ -#define GPDMA_INTSTAT_INTSTAT3_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos) /*!< GPDMA INTSTAT: INTSTAT3 Mask */ -#define GPDMA_INTSTAT_INTSTAT4_Pos 4 /*!< GPDMA INTSTAT: INTSTAT4 Position */ -#define GPDMA_INTSTAT_INTSTAT4_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos) /*!< GPDMA INTSTAT: INTSTAT4 Mask */ -#define GPDMA_INTSTAT_INTSTAT5_Pos 5 /*!< GPDMA INTSTAT: INTSTAT5 Position */ -#define GPDMA_INTSTAT_INTSTAT5_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos) /*!< GPDMA INTSTAT: INTSTAT5 Mask */ -#define GPDMA_INTSTAT_INTSTAT6_Pos 6 /*!< GPDMA INTSTAT: INTSTAT6 Position */ -#define GPDMA_INTSTAT_INTSTAT6_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos) /*!< GPDMA INTSTAT: INTSTAT6 Mask */ -#define GPDMA_INTSTAT_INTSTAT7_Pos 7 /*!< GPDMA INTSTAT: INTSTAT7 Position */ -#define GPDMA_INTSTAT_INTSTAT7_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos) /*!< GPDMA INTSTAT: INTSTAT7 Mask */ - -// ------------------------------------- GPDMA_INTTCSTAT ---------------------------------------- -#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos 0 /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos 1 /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos 2 /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos 3 /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos 4 /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos 5 /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos 6 /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos 7 /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask */ - -// ------------------------------------ GPDMA_INTTCCLEAR ---------------------------------------- -#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos 0 /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos 1 /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos 2 /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos 3 /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos 4 /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos 5 /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos 6 /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos 7 /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask */ - -// ------------------------------------ GPDMA_INTERRSTAT ---------------------------------------- -#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos 0 /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos 1 /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos 2 /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos 3 /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos 4 /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos 5 /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos 6 /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos 7 /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask */ - -// ------------------------------------- GPDMA_INTERRCLR ---------------------------------------- -#define GPDMA_INTERRCLR_INTERRCLR0_Pos 0 /*!< GPDMA INTERRCLR: INTERRCLR0 Position */ -#define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos) /*!< GPDMA INTERRCLR: INTERRCLR0 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR1_Pos 1 /*!< GPDMA INTERRCLR: INTERRCLR1 Position */ -#define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos) /*!< GPDMA INTERRCLR: INTERRCLR1 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR2_Pos 2 /*!< GPDMA INTERRCLR: INTERRCLR2 Position */ -#define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos) /*!< GPDMA INTERRCLR: INTERRCLR2 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR3_Pos 3 /*!< GPDMA INTERRCLR: INTERRCLR3 Position */ -#define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos) /*!< GPDMA INTERRCLR: INTERRCLR3 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR4_Pos 4 /*!< GPDMA INTERRCLR: INTERRCLR4 Position */ -#define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos) /*!< GPDMA INTERRCLR: INTERRCLR4 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR5_Pos 5 /*!< GPDMA INTERRCLR: INTERRCLR5 Position */ -#define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos) /*!< GPDMA INTERRCLR: INTERRCLR5 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR6_Pos 6 /*!< GPDMA INTERRCLR: INTERRCLR6 Position */ -#define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos) /*!< GPDMA INTERRCLR: INTERRCLR6 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR7_Pos 7 /*!< GPDMA INTERRCLR: INTERRCLR7 Position */ -#define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos) /*!< GPDMA INTERRCLR: INTERRCLR7 Mask */ - -// ----------------------------------- GPDMA_RAWINTTCSTAT --------------------------------------- -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos 0 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos 1 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos 2 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos 3 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos 4 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos 5 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos 6 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos 7 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */ - -// ----------------------------------- GPDMA_RAWINTERRSTAT -------------------------------------- -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos 0 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos 1 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos 2 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos 3 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos 4 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos 5 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos 6 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos 7 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */ - -// ------------------------------------- GPDMA_ENBLDCHNS ---------------------------------------- -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos 0 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos 1 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos 2 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos 3 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos 4 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos 5 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos 6 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos 7 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */ - -// ------------------------------------- GPDMA_SOFTBREQ ----------------------------------------- -#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos 0 /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos 1 /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos 2 /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos 3 /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos 4 /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos 5 /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos 6 /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos 7 /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos 8 /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos 9 /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos 10 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos 11 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos 12 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos 13 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos 14 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos 15 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask */ - -// ------------------------------------- GPDMA_SOFTSREQ ----------------------------------------- -#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos 0 /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos 1 /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos 2 /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos 3 /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos 4 /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos 5 /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos 6 /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos 7 /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos 8 /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos 9 /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos 10 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos 11 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos 12 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos 13 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos 14 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos 15 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask */ - -// ------------------------------------- GPDMA_SOFTLBREQ ---------------------------------------- -#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos 0 /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos 1 /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos 2 /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos 3 /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos 4 /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos 5 /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos 6 /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos 7 /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos 8 /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos 9 /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos 10 /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos 11 /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos 12 /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos 13 /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos 14 /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos 15 /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask */ - -// ------------------------------------- GPDMA_SOFTLSREQ ---------------------------------------- -#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos 0 /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos 1 /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos 2 /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos 3 /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos 4 /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos 5 /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos 6 /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos 7 /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos 8 /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos 9 /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos 10 /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos 11 /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos 12 /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos 13 /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos 14 /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos 15 /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask */ - -// -------------------------------------- GPDMA_CONFIG ------------------------------------------ -#define GPDMA_CONFIG_E_Pos 0 /*!< GPDMA CONFIG: E Position */ -#define GPDMA_CONFIG_E_Msk (0x01UL << GPDMA_CONFIG_E_Pos) /*!< GPDMA CONFIG: E Mask */ -#define GPDMA_CONFIG_M0_Pos 1 /*!< GPDMA CONFIG: M0 Position */ -#define GPDMA_CONFIG_M0_Msk (0x01UL << GPDMA_CONFIG_M0_Pos) /*!< GPDMA CONFIG: M0 Mask */ -#define GPDMA_CONFIG_M1_Pos 2 /*!< GPDMA CONFIG: M1 Position */ -#define GPDMA_CONFIG_M1_Msk (0x01UL << GPDMA_CONFIG_M1_Pos) /*!< GPDMA CONFIG: M1 Mask */ - -// --------------------------------------- GPDMA_SYNC ------------------------------------------- -#define GPDMA_SYNC_DMACSYNC0_Pos 0 /*!< GPDMA SYNC: DMACSYNC0 Position */ -#define GPDMA_SYNC_DMACSYNC0_Msk (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos) /*!< GPDMA SYNC: DMACSYNC0 Mask */ -#define GPDMA_SYNC_DMACSYNC1_Pos 1 /*!< GPDMA SYNC: DMACSYNC1 Position */ -#define GPDMA_SYNC_DMACSYNC1_Msk (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos) /*!< GPDMA SYNC: DMACSYNC1 Mask */ -#define GPDMA_SYNC_DMACSYNC2_Pos 2 /*!< GPDMA SYNC: DMACSYNC2 Position */ -#define GPDMA_SYNC_DMACSYNC2_Msk (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos) /*!< GPDMA SYNC: DMACSYNC2 Mask */ -#define GPDMA_SYNC_DMACSYNC3_Pos 3 /*!< GPDMA SYNC: DMACSYNC3 Position */ -#define GPDMA_SYNC_DMACSYNC3_Msk (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos) /*!< GPDMA SYNC: DMACSYNC3 Mask */ -#define GPDMA_SYNC_DMACSYNC4_Pos 4 /*!< GPDMA SYNC: DMACSYNC4 Position */ -#define GPDMA_SYNC_DMACSYNC4_Msk (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos) /*!< GPDMA SYNC: DMACSYNC4 Mask */ -#define GPDMA_SYNC_DMACSYNC5_Pos 5 /*!< GPDMA SYNC: DMACSYNC5 Position */ -#define GPDMA_SYNC_DMACSYNC5_Msk (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos) /*!< GPDMA SYNC: DMACSYNC5 Mask */ -#define GPDMA_SYNC_DMACSYNC6_Pos 6 /*!< GPDMA SYNC: DMACSYNC6 Position */ -#define GPDMA_SYNC_DMACSYNC6_Msk (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos) /*!< GPDMA SYNC: DMACSYNC6 Mask */ -#define GPDMA_SYNC_DMACSYNC7_Pos 7 /*!< GPDMA SYNC: DMACSYNC7 Position */ -#define GPDMA_SYNC_DMACSYNC7_Msk (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos) /*!< GPDMA SYNC: DMACSYNC7 Mask */ -#define GPDMA_SYNC_DMACSYNC8_Pos 8 /*!< GPDMA SYNC: DMACSYNC8 Position */ -#define GPDMA_SYNC_DMACSYNC8_Msk (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos) /*!< GPDMA SYNC: DMACSYNC8 Mask */ -#define GPDMA_SYNC_DMACSYNC9_Pos 9 /*!< GPDMA SYNC: DMACSYNC9 Position */ -#define GPDMA_SYNC_DMACSYNC9_Msk (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos) /*!< GPDMA SYNC: DMACSYNC9 Mask */ -#define GPDMA_SYNC_DMACSYNC10_Pos 10 /*!< GPDMA SYNC: DMACSYNC10 Position */ -#define GPDMA_SYNC_DMACSYNC10_Msk (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos) /*!< GPDMA SYNC: DMACSYNC10 Mask */ -#define GPDMA_SYNC_DMACSYNC11_Pos 11 /*!< GPDMA SYNC: DMACSYNC11 Position */ -#define GPDMA_SYNC_DMACSYNC11_Msk (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos) /*!< GPDMA SYNC: DMACSYNC11 Mask */ -#define GPDMA_SYNC_DMACSYNC12_Pos 12 /*!< GPDMA SYNC: DMACSYNC12 Position */ -#define GPDMA_SYNC_DMACSYNC12_Msk (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos) /*!< GPDMA SYNC: DMACSYNC12 Mask */ -#define GPDMA_SYNC_DMACSYNC13_Pos 13 /*!< GPDMA SYNC: DMACSYNC13 Position */ -#define GPDMA_SYNC_DMACSYNC13_Msk (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos) /*!< GPDMA SYNC: DMACSYNC13 Mask */ -#define GPDMA_SYNC_DMACSYNC14_Pos 14 /*!< GPDMA SYNC: DMACSYNC14 Position */ -#define GPDMA_SYNC_DMACSYNC14_Msk (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos) /*!< GPDMA SYNC: DMACSYNC14 Mask */ -#define GPDMA_SYNC_DMACSYNC15_Pos 15 /*!< GPDMA SYNC: DMACSYNC15 Position */ -#define GPDMA_SYNC_DMACSYNC15_Msk (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos) /*!< GPDMA SYNC: DMACSYNC15 Mask */ - -// ------------------------------------- GPDMA_C0SRCADDR ---------------------------------------- -#define GPDMA_C0SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C0SRCADDR: SRCADDR Position */ -#define GPDMA_C0SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos) /*!< GPDMA C0SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C0DESTADDR ---------------------------------------- -#define GPDMA_C0DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C0DESTADDR: DESTADDR Position */ -#define GPDMA_C0DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos) /*!< GPDMA C0DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C0LLI ------------------------------------------ -#define GPDMA_C0LLI_LM_Pos 0 /*!< GPDMA C0LLI: LM Position */ -#define GPDMA_C0LLI_LM_Msk (0x01UL << GPDMA_C0LLI_LM_Pos) /*!< GPDMA C0LLI: LM Mask */ -#define GPDMA_C0LLI_R_Pos 1 /*!< GPDMA C0LLI: R Position */ -#define GPDMA_C0LLI_R_Msk (0x01UL << GPDMA_C0LLI_R_Pos) /*!< GPDMA C0LLI: R Mask */ -#define GPDMA_C0LLI_LLI_Pos 2 /*!< GPDMA C0LLI: LLI Position */ -#define GPDMA_C0LLI_LLI_Msk (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos) /*!< GPDMA C0LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C0CONTROL ---------------------------------------- -#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C0CONTROL_SBSIZE_Pos 12 /*!< GPDMA C0CONTROL: SBSIZE Position */ -#define GPDMA_C0CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos) /*!< GPDMA C0CONTROL: SBSIZE Mask */ -#define GPDMA_C0CONTROL_DBSIZE_Pos 15 /*!< GPDMA C0CONTROL: DBSIZE Position */ -#define GPDMA_C0CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos) /*!< GPDMA C0CONTROL: DBSIZE Mask */ -#define GPDMA_C0CONTROL_SWIDTH_Pos 18 /*!< GPDMA C0CONTROL: SWIDTH Position */ -#define GPDMA_C0CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos) /*!< GPDMA C0CONTROL: SWIDTH Mask */ -#define GPDMA_C0CONTROL_DWIDTH_Pos 21 /*!< GPDMA C0CONTROL: DWIDTH Position */ -#define GPDMA_C0CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos) /*!< GPDMA C0CONTROL: DWIDTH Mask */ -#define GPDMA_C0CONTROL_S_Pos 24 /*!< GPDMA C0CONTROL: S Position */ -#define GPDMA_C0CONTROL_S_Msk (0x01UL << GPDMA_C0CONTROL_S_Pos) /*!< GPDMA C0CONTROL: S Mask */ -#define GPDMA_C0CONTROL_D_Pos 25 /*!< GPDMA C0CONTROL: D Position */ -#define GPDMA_C0CONTROL_D_Msk (0x01UL << GPDMA_C0CONTROL_D_Pos) /*!< GPDMA C0CONTROL: D Mask */ -#define GPDMA_C0CONTROL_SI_Pos 26 /*!< GPDMA C0CONTROL: SI Position */ -#define GPDMA_C0CONTROL_SI_Msk (0x01UL << GPDMA_C0CONTROL_SI_Pos) /*!< GPDMA C0CONTROL: SI Mask */ -#define GPDMA_C0CONTROL_DI_Pos 27 /*!< GPDMA C0CONTROL: DI Position */ -#define GPDMA_C0CONTROL_DI_Msk (0x01UL << GPDMA_C0CONTROL_DI_Pos) /*!< GPDMA C0CONTROL: DI Mask */ -#define GPDMA_C0CONTROL_PROT1_Pos 28 /*!< GPDMA C0CONTROL: PROT1 Position */ -#define GPDMA_C0CONTROL_PROT1_Msk (0x01UL << GPDMA_C0CONTROL_PROT1_Pos) /*!< GPDMA C0CONTROL: PROT1 Mask */ -#define GPDMA_C0CONTROL_PROT2_Pos 29 /*!< GPDMA C0CONTROL: PROT2 Position */ -#define GPDMA_C0CONTROL_PROT2_Msk (0x01UL << GPDMA_C0CONTROL_PROT2_Pos) /*!< GPDMA C0CONTROL: PROT2 Mask */ -#define GPDMA_C0CONTROL_PROT3_Pos 30 /*!< GPDMA C0CONTROL: PROT3 Position */ -#define GPDMA_C0CONTROL_PROT3_Msk (0x01UL << GPDMA_C0CONTROL_PROT3_Pos) /*!< GPDMA C0CONTROL: PROT3 Mask */ -#define GPDMA_C0CONTROL_I_Pos 31 /*!< GPDMA C0CONTROL: I Position */ -#define GPDMA_C0CONTROL_I_Msk (0x01UL << GPDMA_C0CONTROL_I_Pos) /*!< GPDMA C0CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C0CONFIG ----------------------------------------- -#define GPDMA_C0CONFIG_E_Pos 0 /*!< GPDMA C0CONFIG: E Position */ -#define GPDMA_C0CONFIG_E_Msk (0x01UL << GPDMA_C0CONFIG_E_Pos) /*!< GPDMA C0CONFIG: E Mask */ -#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C0CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C0CONFIG: FLOWCNTRL Position */ -#define GPDMA_C0CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C0CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C0CONFIG_IE_Pos 14 /*!< GPDMA C0CONFIG: IE Position */ -#define GPDMA_C0CONFIG_IE_Msk (0x01UL << GPDMA_C0CONFIG_IE_Pos) /*!< GPDMA C0CONFIG: IE Mask */ -#define GPDMA_C0CONFIG_ITC_Pos 15 /*!< GPDMA C0CONFIG: ITC Position */ -#define GPDMA_C0CONFIG_ITC_Msk (0x01UL << GPDMA_C0CONFIG_ITC_Pos) /*!< GPDMA C0CONFIG: ITC Mask */ -#define GPDMA_C0CONFIG_L_Pos 16 /*!< GPDMA C0CONFIG: L Position */ -#define GPDMA_C0CONFIG_L_Msk (0x01UL << GPDMA_C0CONFIG_L_Pos) /*!< GPDMA C0CONFIG: L Mask */ -#define GPDMA_C0CONFIG_A_Pos 17 /*!< GPDMA C0CONFIG: A Position */ -#define GPDMA_C0CONFIG_A_Msk (0x01UL << GPDMA_C0CONFIG_A_Pos) /*!< GPDMA C0CONFIG: A Mask */ -#define GPDMA_C0CONFIG_H_Pos 18 /*!< GPDMA C0CONFIG: H Position */ -#define GPDMA_C0CONFIG_H_Msk (0x01UL << GPDMA_C0CONFIG_H_Pos) /*!< GPDMA C0CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C1SRCADDR ---------------------------------------- -#define GPDMA_C1SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C1SRCADDR: SRCADDR Position */ -#define GPDMA_C1SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos) /*!< GPDMA C1SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C1DESTADDR ---------------------------------------- -#define GPDMA_C1DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C1DESTADDR: DESTADDR Position */ -#define GPDMA_C1DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos) /*!< GPDMA C1DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C1LLI ------------------------------------------ -#define GPDMA_C1LLI_LM_Pos 0 /*!< GPDMA C1LLI: LM Position */ -#define GPDMA_C1LLI_LM_Msk (0x01UL << GPDMA_C1LLI_LM_Pos) /*!< GPDMA C1LLI: LM Mask */ -#define GPDMA_C1LLI_R_Pos 1 /*!< GPDMA C1LLI: R Position */ -#define GPDMA_C1LLI_R_Msk (0x01UL << GPDMA_C1LLI_R_Pos) /*!< GPDMA C1LLI: R Mask */ -#define GPDMA_C1LLI_LLI_Pos 2 /*!< GPDMA C1LLI: LLI Position */ -#define GPDMA_C1LLI_LLI_Msk (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos) /*!< GPDMA C1LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C1CONTROL ---------------------------------------- -#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C1CONTROL_SBSIZE_Pos 12 /*!< GPDMA C1CONTROL: SBSIZE Position */ -#define GPDMA_C1CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos) /*!< GPDMA C1CONTROL: SBSIZE Mask */ -#define GPDMA_C1CONTROL_DBSIZE_Pos 15 /*!< GPDMA C1CONTROL: DBSIZE Position */ -#define GPDMA_C1CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos) /*!< GPDMA C1CONTROL: DBSIZE Mask */ -#define GPDMA_C1CONTROL_SWIDTH_Pos 18 /*!< GPDMA C1CONTROL: SWIDTH Position */ -#define GPDMA_C1CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos) /*!< GPDMA C1CONTROL: SWIDTH Mask */ -#define GPDMA_C1CONTROL_DWIDTH_Pos 21 /*!< GPDMA C1CONTROL: DWIDTH Position */ -#define GPDMA_C1CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos) /*!< GPDMA C1CONTROL: DWIDTH Mask */ -#define GPDMA_C1CONTROL_S_Pos 24 /*!< GPDMA C1CONTROL: S Position */ -#define GPDMA_C1CONTROL_S_Msk (0x01UL << GPDMA_C1CONTROL_S_Pos) /*!< GPDMA C1CONTROL: S Mask */ -#define GPDMA_C1CONTROL_D_Pos 25 /*!< GPDMA C1CONTROL: D Position */ -#define GPDMA_C1CONTROL_D_Msk (0x01UL << GPDMA_C1CONTROL_D_Pos) /*!< GPDMA C1CONTROL: D Mask */ -#define GPDMA_C1CONTROL_SI_Pos 26 /*!< GPDMA C1CONTROL: SI Position */ -#define GPDMA_C1CONTROL_SI_Msk (0x01UL << GPDMA_C1CONTROL_SI_Pos) /*!< GPDMA C1CONTROL: SI Mask */ -#define GPDMA_C1CONTROL_DI_Pos 27 /*!< GPDMA C1CONTROL: DI Position */ -#define GPDMA_C1CONTROL_DI_Msk (0x01UL << GPDMA_C1CONTROL_DI_Pos) /*!< GPDMA C1CONTROL: DI Mask */ -#define GPDMA_C1CONTROL_PROT1_Pos 28 /*!< GPDMA C1CONTROL: PROT1 Position */ -#define GPDMA_C1CONTROL_PROT1_Msk (0x01UL << GPDMA_C1CONTROL_PROT1_Pos) /*!< GPDMA C1CONTROL: PROT1 Mask */ -#define GPDMA_C1CONTROL_PROT2_Pos 29 /*!< GPDMA C1CONTROL: PROT2 Position */ -#define GPDMA_C1CONTROL_PROT2_Msk (0x01UL << GPDMA_C1CONTROL_PROT2_Pos) /*!< GPDMA C1CONTROL: PROT2 Mask */ -#define GPDMA_C1CONTROL_PROT3_Pos 30 /*!< GPDMA C1CONTROL: PROT3 Position */ -#define GPDMA_C1CONTROL_PROT3_Msk (0x01UL << GPDMA_C1CONTROL_PROT3_Pos) /*!< GPDMA C1CONTROL: PROT3 Mask */ -#define GPDMA_C1CONTROL_I_Pos 31 /*!< GPDMA C1CONTROL: I Position */ -#define GPDMA_C1CONTROL_I_Msk (0x01UL << GPDMA_C1CONTROL_I_Pos) /*!< GPDMA C1CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C1CONFIG ----------------------------------------- -#define GPDMA_C1CONFIG_E_Pos 0 /*!< GPDMA C1CONFIG: E Position */ -#define GPDMA_C1CONFIG_E_Msk (0x01UL << GPDMA_C1CONFIG_E_Pos) /*!< GPDMA C1CONFIG: E Mask */ -#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C1CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C1CONFIG: FLOWCNTRL Position */ -#define GPDMA_C1CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C1CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C1CONFIG_IE_Pos 14 /*!< GPDMA C1CONFIG: IE Position */ -#define GPDMA_C1CONFIG_IE_Msk (0x01UL << GPDMA_C1CONFIG_IE_Pos) /*!< GPDMA C1CONFIG: IE Mask */ -#define GPDMA_C1CONFIG_ITC_Pos 15 /*!< GPDMA C1CONFIG: ITC Position */ -#define GPDMA_C1CONFIG_ITC_Msk (0x01UL << GPDMA_C1CONFIG_ITC_Pos) /*!< GPDMA C1CONFIG: ITC Mask */ -#define GPDMA_C1CONFIG_L_Pos 16 /*!< GPDMA C1CONFIG: L Position */ -#define GPDMA_C1CONFIG_L_Msk (0x01UL << GPDMA_C1CONFIG_L_Pos) /*!< GPDMA C1CONFIG: L Mask */ -#define GPDMA_C1CONFIG_A_Pos 17 /*!< GPDMA C1CONFIG: A Position */ -#define GPDMA_C1CONFIG_A_Msk (0x01UL << GPDMA_C1CONFIG_A_Pos) /*!< GPDMA C1CONFIG: A Mask */ -#define GPDMA_C1CONFIG_H_Pos 18 /*!< GPDMA C1CONFIG: H Position */ -#define GPDMA_C1CONFIG_H_Msk (0x01UL << GPDMA_C1CONFIG_H_Pos) /*!< GPDMA C1CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C2SRCADDR ---------------------------------------- -#define GPDMA_C2SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C2SRCADDR: SRCADDR Position */ -#define GPDMA_C2SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos) /*!< GPDMA C2SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C2DESTADDR ---------------------------------------- -#define GPDMA_C2DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C2DESTADDR: DESTADDR Position */ -#define GPDMA_C2DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos) /*!< GPDMA C2DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C2LLI ------------------------------------------ -#define GPDMA_C2LLI_LM_Pos 0 /*!< GPDMA C2LLI: LM Position */ -#define GPDMA_C2LLI_LM_Msk (0x01UL << GPDMA_C2LLI_LM_Pos) /*!< GPDMA C2LLI: LM Mask */ -#define GPDMA_C2LLI_R_Pos 1 /*!< GPDMA C2LLI: R Position */ -#define GPDMA_C2LLI_R_Msk (0x01UL << GPDMA_C2LLI_R_Pos) /*!< GPDMA C2LLI: R Mask */ -#define GPDMA_C2LLI_LLI_Pos 2 /*!< GPDMA C2LLI: LLI Position */ -#define GPDMA_C2LLI_LLI_Msk (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos) /*!< GPDMA C2LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C2CONTROL ---------------------------------------- -#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C2CONTROL_SBSIZE_Pos 12 /*!< GPDMA C2CONTROL: SBSIZE Position */ -#define GPDMA_C2CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos) /*!< GPDMA C2CONTROL: SBSIZE Mask */ -#define GPDMA_C2CONTROL_DBSIZE_Pos 15 /*!< GPDMA C2CONTROL: DBSIZE Position */ -#define GPDMA_C2CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos) /*!< GPDMA C2CONTROL: DBSIZE Mask */ -#define GPDMA_C2CONTROL_SWIDTH_Pos 18 /*!< GPDMA C2CONTROL: SWIDTH Position */ -#define GPDMA_C2CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos) /*!< GPDMA C2CONTROL: SWIDTH Mask */ -#define GPDMA_C2CONTROL_DWIDTH_Pos 21 /*!< GPDMA C2CONTROL: DWIDTH Position */ -#define GPDMA_C2CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos) /*!< GPDMA C2CONTROL: DWIDTH Mask */ -#define GPDMA_C2CONTROL_S_Pos 24 /*!< GPDMA C2CONTROL: S Position */ -#define GPDMA_C2CONTROL_S_Msk (0x01UL << GPDMA_C2CONTROL_S_Pos) /*!< GPDMA C2CONTROL: S Mask */ -#define GPDMA_C2CONTROL_D_Pos 25 /*!< GPDMA C2CONTROL: D Position */ -#define GPDMA_C2CONTROL_D_Msk (0x01UL << GPDMA_C2CONTROL_D_Pos) /*!< GPDMA C2CONTROL: D Mask */ -#define GPDMA_C2CONTROL_SI_Pos 26 /*!< GPDMA C2CONTROL: SI Position */ -#define GPDMA_C2CONTROL_SI_Msk (0x01UL << GPDMA_C2CONTROL_SI_Pos) /*!< GPDMA C2CONTROL: SI Mask */ -#define GPDMA_C2CONTROL_DI_Pos 27 /*!< GPDMA C2CONTROL: DI Position */ -#define GPDMA_C2CONTROL_DI_Msk (0x01UL << GPDMA_C2CONTROL_DI_Pos) /*!< GPDMA C2CONTROL: DI Mask */ -#define GPDMA_C2CONTROL_PROT1_Pos 28 /*!< GPDMA C2CONTROL: PROT1 Position */ -#define GPDMA_C2CONTROL_PROT1_Msk (0x01UL << GPDMA_C2CONTROL_PROT1_Pos) /*!< GPDMA C2CONTROL: PROT1 Mask */ -#define GPDMA_C2CONTROL_PROT2_Pos 29 /*!< GPDMA C2CONTROL: PROT2 Position */ -#define GPDMA_C2CONTROL_PROT2_Msk (0x01UL << GPDMA_C2CONTROL_PROT2_Pos) /*!< GPDMA C2CONTROL: PROT2 Mask */ -#define GPDMA_C2CONTROL_PROT3_Pos 30 /*!< GPDMA C2CONTROL: PROT3 Position */ -#define GPDMA_C2CONTROL_PROT3_Msk (0x01UL << GPDMA_C2CONTROL_PROT3_Pos) /*!< GPDMA C2CONTROL: PROT3 Mask */ -#define GPDMA_C2CONTROL_I_Pos 31 /*!< GPDMA C2CONTROL: I Position */ -#define GPDMA_C2CONTROL_I_Msk (0x01UL << GPDMA_C2CONTROL_I_Pos) /*!< GPDMA C2CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C2CONFIG ----------------------------------------- -#define GPDMA_C2CONFIG_E_Pos 0 /*!< GPDMA C2CONFIG: E Position */ -#define GPDMA_C2CONFIG_E_Msk (0x01UL << GPDMA_C2CONFIG_E_Pos) /*!< GPDMA C2CONFIG: E Mask */ -#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C2CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C2CONFIG: FLOWCNTRL Position */ -#define GPDMA_C2CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C2CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C2CONFIG_IE_Pos 14 /*!< GPDMA C2CONFIG: IE Position */ -#define GPDMA_C2CONFIG_IE_Msk (0x01UL << GPDMA_C2CONFIG_IE_Pos) /*!< GPDMA C2CONFIG: IE Mask */ -#define GPDMA_C2CONFIG_ITC_Pos 15 /*!< GPDMA C2CONFIG: ITC Position */ -#define GPDMA_C2CONFIG_ITC_Msk (0x01UL << GPDMA_C2CONFIG_ITC_Pos) /*!< GPDMA C2CONFIG: ITC Mask */ -#define GPDMA_C2CONFIG_L_Pos 16 /*!< GPDMA C2CONFIG: L Position */ -#define GPDMA_C2CONFIG_L_Msk (0x01UL << GPDMA_C2CONFIG_L_Pos) /*!< GPDMA C2CONFIG: L Mask */ -#define GPDMA_C2CONFIG_A_Pos 17 /*!< GPDMA C2CONFIG: A Position */ -#define GPDMA_C2CONFIG_A_Msk (0x01UL << GPDMA_C2CONFIG_A_Pos) /*!< GPDMA C2CONFIG: A Mask */ -#define GPDMA_C2CONFIG_H_Pos 18 /*!< GPDMA C2CONFIG: H Position */ -#define GPDMA_C2CONFIG_H_Msk (0x01UL << GPDMA_C2CONFIG_H_Pos) /*!< GPDMA C2CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C3SRCADDR ---------------------------------------- -#define GPDMA_C3SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C3SRCADDR: SRCADDR Position */ -#define GPDMA_C3SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos) /*!< GPDMA C3SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C3DESTADDR ---------------------------------------- -#define GPDMA_C3DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C3DESTADDR: DESTADDR Position */ -#define GPDMA_C3DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos) /*!< GPDMA C3DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C3LLI ------------------------------------------ -#define GPDMA_C3LLI_LM_Pos 0 /*!< GPDMA C3LLI: LM Position */ -#define GPDMA_C3LLI_LM_Msk (0x01UL << GPDMA_C3LLI_LM_Pos) /*!< GPDMA C3LLI: LM Mask */ -#define GPDMA_C3LLI_R_Pos 1 /*!< GPDMA C3LLI: R Position */ -#define GPDMA_C3LLI_R_Msk (0x01UL << GPDMA_C3LLI_R_Pos) /*!< GPDMA C3LLI: R Mask */ -#define GPDMA_C3LLI_LLI_Pos 2 /*!< GPDMA C3LLI: LLI Position */ -#define GPDMA_C3LLI_LLI_Msk (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos) /*!< GPDMA C3LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C3CONTROL ---------------------------------------- -#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C3CONTROL_SBSIZE_Pos 12 /*!< GPDMA C3CONTROL: SBSIZE Position */ -#define GPDMA_C3CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos) /*!< GPDMA C3CONTROL: SBSIZE Mask */ -#define GPDMA_C3CONTROL_DBSIZE_Pos 15 /*!< GPDMA C3CONTROL: DBSIZE Position */ -#define GPDMA_C3CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos) /*!< GPDMA C3CONTROL: DBSIZE Mask */ -#define GPDMA_C3CONTROL_SWIDTH_Pos 18 /*!< GPDMA C3CONTROL: SWIDTH Position */ -#define GPDMA_C3CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos) /*!< GPDMA C3CONTROL: SWIDTH Mask */ -#define GPDMA_C3CONTROL_DWIDTH_Pos 21 /*!< GPDMA C3CONTROL: DWIDTH Position */ -#define GPDMA_C3CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos) /*!< GPDMA C3CONTROL: DWIDTH Mask */ -#define GPDMA_C3CONTROL_S_Pos 24 /*!< GPDMA C3CONTROL: S Position */ -#define GPDMA_C3CONTROL_S_Msk (0x01UL << GPDMA_C3CONTROL_S_Pos) /*!< GPDMA C3CONTROL: S Mask */ -#define GPDMA_C3CONTROL_D_Pos 25 /*!< GPDMA C3CONTROL: D Position */ -#define GPDMA_C3CONTROL_D_Msk (0x01UL << GPDMA_C3CONTROL_D_Pos) /*!< GPDMA C3CONTROL: D Mask */ -#define GPDMA_C3CONTROL_SI_Pos 26 /*!< GPDMA C3CONTROL: SI Position */ -#define GPDMA_C3CONTROL_SI_Msk (0x01UL << GPDMA_C3CONTROL_SI_Pos) /*!< GPDMA C3CONTROL: SI Mask */ -#define GPDMA_C3CONTROL_DI_Pos 27 /*!< GPDMA C3CONTROL: DI Position */ -#define GPDMA_C3CONTROL_DI_Msk (0x01UL << GPDMA_C3CONTROL_DI_Pos) /*!< GPDMA C3CONTROL: DI Mask */ -#define GPDMA_C3CONTROL_PROT1_Pos 28 /*!< GPDMA C3CONTROL: PROT1 Position */ -#define GPDMA_C3CONTROL_PROT1_Msk (0x01UL << GPDMA_C3CONTROL_PROT1_Pos) /*!< GPDMA C3CONTROL: PROT1 Mask */ -#define GPDMA_C3CONTROL_PROT2_Pos 29 /*!< GPDMA C3CONTROL: PROT2 Position */ -#define GPDMA_C3CONTROL_PROT2_Msk (0x01UL << GPDMA_C3CONTROL_PROT2_Pos) /*!< GPDMA C3CONTROL: PROT2 Mask */ -#define GPDMA_C3CONTROL_PROT3_Pos 30 /*!< GPDMA C3CONTROL: PROT3 Position */ -#define GPDMA_C3CONTROL_PROT3_Msk (0x01UL << GPDMA_C3CONTROL_PROT3_Pos) /*!< GPDMA C3CONTROL: PROT3 Mask */ -#define GPDMA_C3CONTROL_I_Pos 31 /*!< GPDMA C3CONTROL: I Position */ -#define GPDMA_C3CONTROL_I_Msk (0x01UL << GPDMA_C3CONTROL_I_Pos) /*!< GPDMA C3CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C3CONFIG ----------------------------------------- -#define GPDMA_C3CONFIG_E_Pos 0 /*!< GPDMA C3CONFIG: E Position */ -#define GPDMA_C3CONFIG_E_Msk (0x01UL << GPDMA_C3CONFIG_E_Pos) /*!< GPDMA C3CONFIG: E Mask */ -#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C3CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C3CONFIG: FLOWCNTRL Position */ -#define GPDMA_C3CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C3CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C3CONFIG_IE_Pos 14 /*!< GPDMA C3CONFIG: IE Position */ -#define GPDMA_C3CONFIG_IE_Msk (0x01UL << GPDMA_C3CONFIG_IE_Pos) /*!< GPDMA C3CONFIG: IE Mask */ -#define GPDMA_C3CONFIG_ITC_Pos 15 /*!< GPDMA C3CONFIG: ITC Position */ -#define GPDMA_C3CONFIG_ITC_Msk (0x01UL << GPDMA_C3CONFIG_ITC_Pos) /*!< GPDMA C3CONFIG: ITC Mask */ -#define GPDMA_C3CONFIG_L_Pos 16 /*!< GPDMA C3CONFIG: L Position */ -#define GPDMA_C3CONFIG_L_Msk (0x01UL << GPDMA_C3CONFIG_L_Pos) /*!< GPDMA C3CONFIG: L Mask */ -#define GPDMA_C3CONFIG_A_Pos 17 /*!< GPDMA C3CONFIG: A Position */ -#define GPDMA_C3CONFIG_A_Msk (0x01UL << GPDMA_C3CONFIG_A_Pos) /*!< GPDMA C3CONFIG: A Mask */ -#define GPDMA_C3CONFIG_H_Pos 18 /*!< GPDMA C3CONFIG: H Position */ -#define GPDMA_C3CONFIG_H_Msk (0x01UL << GPDMA_C3CONFIG_H_Pos) /*!< GPDMA C3CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C4SRCADDR ---------------------------------------- -#define GPDMA_C4SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C4SRCADDR: SRCADDR Position */ -#define GPDMA_C4SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos) /*!< GPDMA C4SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C4DESTADDR ---------------------------------------- -#define GPDMA_C4DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C4DESTADDR: DESTADDR Position */ -#define GPDMA_C4DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos) /*!< GPDMA C4DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C4LLI ------------------------------------------ -#define GPDMA_C4LLI_LM_Pos 0 /*!< GPDMA C4LLI: LM Position */ -#define GPDMA_C4LLI_LM_Msk (0x01UL << GPDMA_C4LLI_LM_Pos) /*!< GPDMA C4LLI: LM Mask */ -#define GPDMA_C4LLI_R_Pos 1 /*!< GPDMA C4LLI: R Position */ -#define GPDMA_C4LLI_R_Msk (0x01UL << GPDMA_C4LLI_R_Pos) /*!< GPDMA C4LLI: R Mask */ -#define GPDMA_C4LLI_LLI_Pos 2 /*!< GPDMA C4LLI: LLI Position */ -#define GPDMA_C4LLI_LLI_Msk (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos) /*!< GPDMA C4LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C4CONTROL ---------------------------------------- -#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C4CONTROL_SBSIZE_Pos 12 /*!< GPDMA C4CONTROL: SBSIZE Position */ -#define GPDMA_C4CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos) /*!< GPDMA C4CONTROL: SBSIZE Mask */ -#define GPDMA_C4CONTROL_DBSIZE_Pos 15 /*!< GPDMA C4CONTROL: DBSIZE Position */ -#define GPDMA_C4CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos) /*!< GPDMA C4CONTROL: DBSIZE Mask */ -#define GPDMA_C4CONTROL_SWIDTH_Pos 18 /*!< GPDMA C4CONTROL: SWIDTH Position */ -#define GPDMA_C4CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos) /*!< GPDMA C4CONTROL: SWIDTH Mask */ -#define GPDMA_C4CONTROL_DWIDTH_Pos 21 /*!< GPDMA C4CONTROL: DWIDTH Position */ -#define GPDMA_C4CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos) /*!< GPDMA C4CONTROL: DWIDTH Mask */ -#define GPDMA_C4CONTROL_S_Pos 24 /*!< GPDMA C4CONTROL: S Position */ -#define GPDMA_C4CONTROL_S_Msk (0x01UL << GPDMA_C4CONTROL_S_Pos) /*!< GPDMA C4CONTROL: S Mask */ -#define GPDMA_C4CONTROL_D_Pos 25 /*!< GPDMA C4CONTROL: D Position */ -#define GPDMA_C4CONTROL_D_Msk (0x01UL << GPDMA_C4CONTROL_D_Pos) /*!< GPDMA C4CONTROL: D Mask */ -#define GPDMA_C4CONTROL_SI_Pos 26 /*!< GPDMA C4CONTROL: SI Position */ -#define GPDMA_C4CONTROL_SI_Msk (0x01UL << GPDMA_C4CONTROL_SI_Pos) /*!< GPDMA C4CONTROL: SI Mask */ -#define GPDMA_C4CONTROL_DI_Pos 27 /*!< GPDMA C4CONTROL: DI Position */ -#define GPDMA_C4CONTROL_DI_Msk (0x01UL << GPDMA_C4CONTROL_DI_Pos) /*!< GPDMA C4CONTROL: DI Mask */ -#define GPDMA_C4CONTROL_PROT1_Pos 28 /*!< GPDMA C4CONTROL: PROT1 Position */ -#define GPDMA_C4CONTROL_PROT1_Msk (0x01UL << GPDMA_C4CONTROL_PROT1_Pos) /*!< GPDMA C4CONTROL: PROT1 Mask */ -#define GPDMA_C4CONTROL_PROT2_Pos 29 /*!< GPDMA C4CONTROL: PROT2 Position */ -#define GPDMA_C4CONTROL_PROT2_Msk (0x01UL << GPDMA_C4CONTROL_PROT2_Pos) /*!< GPDMA C4CONTROL: PROT2 Mask */ -#define GPDMA_C4CONTROL_PROT3_Pos 30 /*!< GPDMA C4CONTROL: PROT3 Position */ -#define GPDMA_C4CONTROL_PROT3_Msk (0x01UL << GPDMA_C4CONTROL_PROT3_Pos) /*!< GPDMA C4CONTROL: PROT3 Mask */ -#define GPDMA_C4CONTROL_I_Pos 31 /*!< GPDMA C4CONTROL: I Position */ -#define GPDMA_C4CONTROL_I_Msk (0x01UL << GPDMA_C4CONTROL_I_Pos) /*!< GPDMA C4CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C4CONFIG ----------------------------------------- -#define GPDMA_C4CONFIG_E_Pos 0 /*!< GPDMA C4CONFIG: E Position */ -#define GPDMA_C4CONFIG_E_Msk (0x01UL << GPDMA_C4CONFIG_E_Pos) /*!< GPDMA C4CONFIG: E Mask */ -#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C4CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C4CONFIG: FLOWCNTRL Position */ -#define GPDMA_C4CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C4CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C4CONFIG_IE_Pos 14 /*!< GPDMA C4CONFIG: IE Position */ -#define GPDMA_C4CONFIG_IE_Msk (0x01UL << GPDMA_C4CONFIG_IE_Pos) /*!< GPDMA C4CONFIG: IE Mask */ -#define GPDMA_C4CONFIG_ITC_Pos 15 /*!< GPDMA C4CONFIG: ITC Position */ -#define GPDMA_C4CONFIG_ITC_Msk (0x01UL << GPDMA_C4CONFIG_ITC_Pos) /*!< GPDMA C4CONFIG: ITC Mask */ -#define GPDMA_C4CONFIG_L_Pos 16 /*!< GPDMA C4CONFIG: L Position */ -#define GPDMA_C4CONFIG_L_Msk (0x01UL << GPDMA_C4CONFIG_L_Pos) /*!< GPDMA C4CONFIG: L Mask */ -#define GPDMA_C4CONFIG_A_Pos 17 /*!< GPDMA C4CONFIG: A Position */ -#define GPDMA_C4CONFIG_A_Msk (0x01UL << GPDMA_C4CONFIG_A_Pos) /*!< GPDMA C4CONFIG: A Mask */ -#define GPDMA_C4CONFIG_H_Pos 18 /*!< GPDMA C4CONFIG: H Position */ -#define GPDMA_C4CONFIG_H_Msk (0x01UL << GPDMA_C4CONFIG_H_Pos) /*!< GPDMA C4CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C5SRCADDR ---------------------------------------- -#define GPDMA_C5SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C5SRCADDR: SRCADDR Position */ -#define GPDMA_C5SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos) /*!< GPDMA C5SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C5DESTADDR ---------------------------------------- -#define GPDMA_C5DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C5DESTADDR: DESTADDR Position */ -#define GPDMA_C5DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos) /*!< GPDMA C5DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C5LLI ------------------------------------------ -#define GPDMA_C5LLI_LM_Pos 0 /*!< GPDMA C5LLI: LM Position */ -#define GPDMA_C5LLI_LM_Msk (0x01UL << GPDMA_C5LLI_LM_Pos) /*!< GPDMA C5LLI: LM Mask */ -#define GPDMA_C5LLI_R_Pos 1 /*!< GPDMA C5LLI: R Position */ -#define GPDMA_C5LLI_R_Msk (0x01UL << GPDMA_C5LLI_R_Pos) /*!< GPDMA C5LLI: R Mask */ -#define GPDMA_C5LLI_LLI_Pos 2 /*!< GPDMA C5LLI: LLI Position */ -#define GPDMA_C5LLI_LLI_Msk (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos) /*!< GPDMA C5LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C5CONTROL ---------------------------------------- -#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C5CONTROL_SBSIZE_Pos 12 /*!< GPDMA C5CONTROL: SBSIZE Position */ -#define GPDMA_C5CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos) /*!< GPDMA C5CONTROL: SBSIZE Mask */ -#define GPDMA_C5CONTROL_DBSIZE_Pos 15 /*!< GPDMA C5CONTROL: DBSIZE Position */ -#define GPDMA_C5CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos) /*!< GPDMA C5CONTROL: DBSIZE Mask */ -#define GPDMA_C5CONTROL_SWIDTH_Pos 18 /*!< GPDMA C5CONTROL: SWIDTH Position */ -#define GPDMA_C5CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos) /*!< GPDMA C5CONTROL: SWIDTH Mask */ -#define GPDMA_C5CONTROL_DWIDTH_Pos 21 /*!< GPDMA C5CONTROL: DWIDTH Position */ -#define GPDMA_C5CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos) /*!< GPDMA C5CONTROL: DWIDTH Mask */ -#define GPDMA_C5CONTROL_S_Pos 24 /*!< GPDMA C5CONTROL: S Position */ -#define GPDMA_C5CONTROL_S_Msk (0x01UL << GPDMA_C5CONTROL_S_Pos) /*!< GPDMA C5CONTROL: S Mask */ -#define GPDMA_C5CONTROL_D_Pos 25 /*!< GPDMA C5CONTROL: D Position */ -#define GPDMA_C5CONTROL_D_Msk (0x01UL << GPDMA_C5CONTROL_D_Pos) /*!< GPDMA C5CONTROL: D Mask */ -#define GPDMA_C5CONTROL_SI_Pos 26 /*!< GPDMA C5CONTROL: SI Position */ -#define GPDMA_C5CONTROL_SI_Msk (0x01UL << GPDMA_C5CONTROL_SI_Pos) /*!< GPDMA C5CONTROL: SI Mask */ -#define GPDMA_C5CONTROL_DI_Pos 27 /*!< GPDMA C5CONTROL: DI Position */ -#define GPDMA_C5CONTROL_DI_Msk (0x01UL << GPDMA_C5CONTROL_DI_Pos) /*!< GPDMA C5CONTROL: DI Mask */ -#define GPDMA_C5CONTROL_PROT1_Pos 28 /*!< GPDMA C5CONTROL: PROT1 Position */ -#define GPDMA_C5CONTROL_PROT1_Msk (0x01UL << GPDMA_C5CONTROL_PROT1_Pos) /*!< GPDMA C5CONTROL: PROT1 Mask */ -#define GPDMA_C5CONTROL_PROT2_Pos 29 /*!< GPDMA C5CONTROL: PROT2 Position */ -#define GPDMA_C5CONTROL_PROT2_Msk (0x01UL << GPDMA_C5CONTROL_PROT2_Pos) /*!< GPDMA C5CONTROL: PROT2 Mask */ -#define GPDMA_C5CONTROL_PROT3_Pos 30 /*!< GPDMA C5CONTROL: PROT3 Position */ -#define GPDMA_C5CONTROL_PROT3_Msk (0x01UL << GPDMA_C5CONTROL_PROT3_Pos) /*!< GPDMA C5CONTROL: PROT3 Mask */ -#define GPDMA_C5CONTROL_I_Pos 31 /*!< GPDMA C5CONTROL: I Position */ -#define GPDMA_C5CONTROL_I_Msk (0x01UL << GPDMA_C5CONTROL_I_Pos) /*!< GPDMA C5CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C5CONFIG ----------------------------------------- -#define GPDMA_C5CONFIG_E_Pos 0 /*!< GPDMA C5CONFIG: E Position */ -#define GPDMA_C5CONFIG_E_Msk (0x01UL << GPDMA_C5CONFIG_E_Pos) /*!< GPDMA C5CONFIG: E Mask */ -#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C5CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C5CONFIG: FLOWCNTRL Position */ -#define GPDMA_C5CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C5CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C5CONFIG_IE_Pos 14 /*!< GPDMA C5CONFIG: IE Position */ -#define GPDMA_C5CONFIG_IE_Msk (0x01UL << GPDMA_C5CONFIG_IE_Pos) /*!< GPDMA C5CONFIG: IE Mask */ -#define GPDMA_C5CONFIG_ITC_Pos 15 /*!< GPDMA C5CONFIG: ITC Position */ -#define GPDMA_C5CONFIG_ITC_Msk (0x01UL << GPDMA_C5CONFIG_ITC_Pos) /*!< GPDMA C5CONFIG: ITC Mask */ -#define GPDMA_C5CONFIG_L_Pos 16 /*!< GPDMA C5CONFIG: L Position */ -#define GPDMA_C5CONFIG_L_Msk (0x01UL << GPDMA_C5CONFIG_L_Pos) /*!< GPDMA C5CONFIG: L Mask */ -#define GPDMA_C5CONFIG_A_Pos 17 /*!< GPDMA C5CONFIG: A Position */ -#define GPDMA_C5CONFIG_A_Msk (0x01UL << GPDMA_C5CONFIG_A_Pos) /*!< GPDMA C5CONFIG: A Mask */ -#define GPDMA_C5CONFIG_H_Pos 18 /*!< GPDMA C5CONFIG: H Position */ -#define GPDMA_C5CONFIG_H_Msk (0x01UL << GPDMA_C5CONFIG_H_Pos) /*!< GPDMA C5CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C6SRCADDR ---------------------------------------- -#define GPDMA_C6SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C6SRCADDR: SRCADDR Position */ -#define GPDMA_C6SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos) /*!< GPDMA C6SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C6DESTADDR ---------------------------------------- -#define GPDMA_C6DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C6DESTADDR: DESTADDR Position */ -#define GPDMA_C6DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos) /*!< GPDMA C6DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C6LLI ------------------------------------------ -#define GPDMA_C6LLI_LM_Pos 0 /*!< GPDMA C6LLI: LM Position */ -#define GPDMA_C6LLI_LM_Msk (0x01UL << GPDMA_C6LLI_LM_Pos) /*!< GPDMA C6LLI: LM Mask */ -#define GPDMA_C6LLI_R_Pos 1 /*!< GPDMA C6LLI: R Position */ -#define GPDMA_C6LLI_R_Msk (0x01UL << GPDMA_C6LLI_R_Pos) /*!< GPDMA C6LLI: R Mask */ -#define GPDMA_C6LLI_LLI_Pos 2 /*!< GPDMA C6LLI: LLI Position */ -#define GPDMA_C6LLI_LLI_Msk (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos) /*!< GPDMA C6LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C6CONTROL ---------------------------------------- -#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C6CONTROL_SBSIZE_Pos 12 /*!< GPDMA C6CONTROL: SBSIZE Position */ -#define GPDMA_C6CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos) /*!< GPDMA C6CONTROL: SBSIZE Mask */ -#define GPDMA_C6CONTROL_DBSIZE_Pos 15 /*!< GPDMA C6CONTROL: DBSIZE Position */ -#define GPDMA_C6CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos) /*!< GPDMA C6CONTROL: DBSIZE Mask */ -#define GPDMA_C6CONTROL_SWIDTH_Pos 18 /*!< GPDMA C6CONTROL: SWIDTH Position */ -#define GPDMA_C6CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos) /*!< GPDMA C6CONTROL: SWIDTH Mask */ -#define GPDMA_C6CONTROL_DWIDTH_Pos 21 /*!< GPDMA C6CONTROL: DWIDTH Position */ -#define GPDMA_C6CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos) /*!< GPDMA C6CONTROL: DWIDTH Mask */ -#define GPDMA_C6CONTROL_S_Pos 24 /*!< GPDMA C6CONTROL: S Position */ -#define GPDMA_C6CONTROL_S_Msk (0x01UL << GPDMA_C6CONTROL_S_Pos) /*!< GPDMA C6CONTROL: S Mask */ -#define GPDMA_C6CONTROL_D_Pos 25 /*!< GPDMA C6CONTROL: D Position */ -#define GPDMA_C6CONTROL_D_Msk (0x01UL << GPDMA_C6CONTROL_D_Pos) /*!< GPDMA C6CONTROL: D Mask */ -#define GPDMA_C6CONTROL_SI_Pos 26 /*!< GPDMA C6CONTROL: SI Position */ -#define GPDMA_C6CONTROL_SI_Msk (0x01UL << GPDMA_C6CONTROL_SI_Pos) /*!< GPDMA C6CONTROL: SI Mask */ -#define GPDMA_C6CONTROL_DI_Pos 27 /*!< GPDMA C6CONTROL: DI Position */ -#define GPDMA_C6CONTROL_DI_Msk (0x01UL << GPDMA_C6CONTROL_DI_Pos) /*!< GPDMA C6CONTROL: DI Mask */ -#define GPDMA_C6CONTROL_PROT1_Pos 28 /*!< GPDMA C6CONTROL: PROT1 Position */ -#define GPDMA_C6CONTROL_PROT1_Msk (0x01UL << GPDMA_C6CONTROL_PROT1_Pos) /*!< GPDMA C6CONTROL: PROT1 Mask */ -#define GPDMA_C6CONTROL_PROT2_Pos 29 /*!< GPDMA C6CONTROL: PROT2 Position */ -#define GPDMA_C6CONTROL_PROT2_Msk (0x01UL << GPDMA_C6CONTROL_PROT2_Pos) /*!< GPDMA C6CONTROL: PROT2 Mask */ -#define GPDMA_C6CONTROL_PROT3_Pos 30 /*!< GPDMA C6CONTROL: PROT3 Position */ -#define GPDMA_C6CONTROL_PROT3_Msk (0x01UL << GPDMA_C6CONTROL_PROT3_Pos) /*!< GPDMA C6CONTROL: PROT3 Mask */ -#define GPDMA_C6CONTROL_I_Pos 31 /*!< GPDMA C6CONTROL: I Position */ -#define GPDMA_C6CONTROL_I_Msk (0x01UL << GPDMA_C6CONTROL_I_Pos) /*!< GPDMA C6CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C6CONFIG ----------------------------------------- -#define GPDMA_C6CONFIG_E_Pos 0 /*!< GPDMA C6CONFIG: E Position */ -#define GPDMA_C6CONFIG_E_Msk (0x01UL << GPDMA_C6CONFIG_E_Pos) /*!< GPDMA C6CONFIG: E Mask */ -#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C6CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C6CONFIG: FLOWCNTRL Position */ -#define GPDMA_C6CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C6CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C6CONFIG_IE_Pos 14 /*!< GPDMA C6CONFIG: IE Position */ -#define GPDMA_C6CONFIG_IE_Msk (0x01UL << GPDMA_C6CONFIG_IE_Pos) /*!< GPDMA C6CONFIG: IE Mask */ -#define GPDMA_C6CONFIG_ITC_Pos 15 /*!< GPDMA C6CONFIG: ITC Position */ -#define GPDMA_C6CONFIG_ITC_Msk (0x01UL << GPDMA_C6CONFIG_ITC_Pos) /*!< GPDMA C6CONFIG: ITC Mask */ -#define GPDMA_C6CONFIG_L_Pos 16 /*!< GPDMA C6CONFIG: L Position */ -#define GPDMA_C6CONFIG_L_Msk (0x01UL << GPDMA_C6CONFIG_L_Pos) /*!< GPDMA C6CONFIG: L Mask */ -#define GPDMA_C6CONFIG_A_Pos 17 /*!< GPDMA C6CONFIG: A Position */ -#define GPDMA_C6CONFIG_A_Msk (0x01UL << GPDMA_C6CONFIG_A_Pos) /*!< GPDMA C6CONFIG: A Mask */ -#define GPDMA_C6CONFIG_H_Pos 18 /*!< GPDMA C6CONFIG: H Position */ -#define GPDMA_C6CONFIG_H_Msk (0x01UL << GPDMA_C6CONFIG_H_Pos) /*!< GPDMA C6CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C7SRCADDR ---------------------------------------- -#define GPDMA_C7SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C7SRCADDR: SRCADDR Position */ -#define GPDMA_C7SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos) /*!< GPDMA C7SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C7DESTADDR ---------------------------------------- -#define GPDMA_C7DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C7DESTADDR: DESTADDR Position */ -#define GPDMA_C7DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos) /*!< GPDMA C7DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C7LLI ------------------------------------------ -#define GPDMA_C7LLI_LM_Pos 0 /*!< GPDMA C7LLI: LM Position */ -#define GPDMA_C7LLI_LM_Msk (0x01UL << GPDMA_C7LLI_LM_Pos) /*!< GPDMA C7LLI: LM Mask */ -#define GPDMA_C7LLI_R_Pos 1 /*!< GPDMA C7LLI: R Position */ -#define GPDMA_C7LLI_R_Msk (0x01UL << GPDMA_C7LLI_R_Pos) /*!< GPDMA C7LLI: R Mask */ -#define GPDMA_C7LLI_LLI_Pos 2 /*!< GPDMA C7LLI: LLI Position */ -#define GPDMA_C7LLI_LLI_Msk (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos) /*!< GPDMA C7LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C7CONTROL ---------------------------------------- -#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C7CONTROL_SBSIZE_Pos 12 /*!< GPDMA C7CONTROL: SBSIZE Position */ -#define GPDMA_C7CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos) /*!< GPDMA C7CONTROL: SBSIZE Mask */ -#define GPDMA_C7CONTROL_DBSIZE_Pos 15 /*!< GPDMA C7CONTROL: DBSIZE Position */ -#define GPDMA_C7CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos) /*!< GPDMA C7CONTROL: DBSIZE Mask */ -#define GPDMA_C7CONTROL_SWIDTH_Pos 18 /*!< GPDMA C7CONTROL: SWIDTH Position */ -#define GPDMA_C7CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos) /*!< GPDMA C7CONTROL: SWIDTH Mask */ -#define GPDMA_C7CONTROL_DWIDTH_Pos 21 /*!< GPDMA C7CONTROL: DWIDTH Position */ -#define GPDMA_C7CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos) /*!< GPDMA C7CONTROL: DWIDTH Mask */ -#define GPDMA_C7CONTROL_S_Pos 24 /*!< GPDMA C7CONTROL: S Position */ -#define GPDMA_C7CONTROL_S_Msk (0x01UL << GPDMA_C7CONTROL_S_Pos) /*!< GPDMA C7CONTROL: S Mask */ -#define GPDMA_C7CONTROL_D_Pos 25 /*!< GPDMA C7CONTROL: D Position */ -#define GPDMA_C7CONTROL_D_Msk (0x01UL << GPDMA_C7CONTROL_D_Pos) /*!< GPDMA C7CONTROL: D Mask */ -#define GPDMA_C7CONTROL_SI_Pos 26 /*!< GPDMA C7CONTROL: SI Position */ -#define GPDMA_C7CONTROL_SI_Msk (0x01UL << GPDMA_C7CONTROL_SI_Pos) /*!< GPDMA C7CONTROL: SI Mask */ -#define GPDMA_C7CONTROL_DI_Pos 27 /*!< GPDMA C7CONTROL: DI Position */ -#define GPDMA_C7CONTROL_DI_Msk (0x01UL << GPDMA_C7CONTROL_DI_Pos) /*!< GPDMA C7CONTROL: DI Mask */ -#define GPDMA_C7CONTROL_PROT1_Pos 28 /*!< GPDMA C7CONTROL: PROT1 Position */ -#define GPDMA_C7CONTROL_PROT1_Msk (0x01UL << GPDMA_C7CONTROL_PROT1_Pos) /*!< GPDMA C7CONTROL: PROT1 Mask */ -#define GPDMA_C7CONTROL_PROT2_Pos 29 /*!< GPDMA C7CONTROL: PROT2 Position */ -#define GPDMA_C7CONTROL_PROT2_Msk (0x01UL << GPDMA_C7CONTROL_PROT2_Pos) /*!< GPDMA C7CONTROL: PROT2 Mask */ -#define GPDMA_C7CONTROL_PROT3_Pos 30 /*!< GPDMA C7CONTROL: PROT3 Position */ -#define GPDMA_C7CONTROL_PROT3_Msk (0x01UL << GPDMA_C7CONTROL_PROT3_Pos) /*!< GPDMA C7CONTROL: PROT3 Mask */ -#define GPDMA_C7CONTROL_I_Pos 31 /*!< GPDMA C7CONTROL: I Position */ -#define GPDMA_C7CONTROL_I_Msk (0x01UL << GPDMA_C7CONTROL_I_Pos) /*!< GPDMA C7CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C7CONFIG ----------------------------------------- -#define GPDMA_C7CONFIG_E_Pos 0 /*!< GPDMA C7CONFIG: E Position */ -#define GPDMA_C7CONFIG_E_Msk (0x01UL << GPDMA_C7CONFIG_E_Pos) /*!< GPDMA C7CONFIG: E Mask */ -#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C7CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C7CONFIG: FLOWCNTRL Position */ -#define GPDMA_C7CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C7CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C7CONFIG_IE_Pos 14 /*!< GPDMA C7CONFIG: IE Position */ -#define GPDMA_C7CONFIG_IE_Msk (0x01UL << GPDMA_C7CONFIG_IE_Pos) /*!< GPDMA C7CONFIG: IE Mask */ -#define GPDMA_C7CONFIG_ITC_Pos 15 /*!< GPDMA C7CONFIG: ITC Position */ -#define GPDMA_C7CONFIG_ITC_Msk (0x01UL << GPDMA_C7CONFIG_ITC_Pos) /*!< GPDMA C7CONFIG: ITC Mask */ -#define GPDMA_C7CONFIG_L_Pos 16 /*!< GPDMA C7CONFIG: L Position */ -#define GPDMA_C7CONFIG_L_Msk (0x01UL << GPDMA_C7CONFIG_L_Pos) /*!< GPDMA C7CONFIG: L Mask */ -#define GPDMA_C7CONFIG_A_Pos 17 /*!< GPDMA C7CONFIG: A Position */ -#define GPDMA_C7CONFIG_A_Msk (0x01UL << GPDMA_C7CONFIG_A_Pos) /*!< GPDMA C7CONFIG: A Mask */ -#define GPDMA_C7CONFIG_H_Pos 18 /*!< GPDMA C7CONFIG: H Position */ -#define GPDMA_C7CONFIG_H_Msk (0x01UL << GPDMA_C7CONFIG_H_Pos) /*!< GPDMA C7CONFIG: H Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SDMMC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- SDMMC_CTRL ------------------------------------------- -#define SDMMC_CTRL_CONTROLLER_RESET_Pos 0 /*!< SDMMC CTRL: CONTROLLER_RESET Position */ -#define SDMMC_CTRL_CONTROLLER_RESET_Msk (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos) /*!< SDMMC CTRL: CONTROLLER_RESET Mask */ -#define SDMMC_CTRL_FIFO_RESET_Pos 1 /*!< SDMMC CTRL: FIFO_RESET Position */ -#define SDMMC_CTRL_FIFO_RESET_Msk (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos) /*!< SDMMC CTRL: FIFO_RESET Mask */ -#define SDMMC_CTRL_DMA_RESET_Pos 2 /*!< SDMMC CTRL: DMA_RESET Position */ -#define SDMMC_CTRL_DMA_RESET_Msk (0x01UL << SDMMC_CTRL_DMA_RESET_Pos) /*!< SDMMC CTRL: DMA_RESET Mask */ -#define SDMMC_CTRL_INT_ENABLE_Pos 4 /*!< SDMMC CTRL: INT_ENABLE Position */ -#define SDMMC_CTRL_INT_ENABLE_Msk (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos) /*!< SDMMC CTRL: INT_ENABLE Mask */ -#define SDMMC_CTRL_DMA_ENABLE_Pos 5 /*!< SDMMC CTRL: DMA_ENABLE Position */ -#define SDMMC_CTRL_DMA_ENABLE_Msk (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos) /*!< SDMMC CTRL: DMA_ENABLE Mask */ -#define SDMMC_CTRL_READ_WAIT_Pos 6 /*!< SDMMC CTRL: READ_WAIT Position */ -#define SDMMC_CTRL_READ_WAIT_Msk (0x01UL << SDMMC_CTRL_READ_WAIT_Pos) /*!< SDMMC CTRL: READ_WAIT Mask */ -#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos 7 /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */ -#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos) /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask */ -#define SDMMC_CTRL_ABORT_READ_DATA_Pos 8 /*!< SDMMC CTRL: ABORT_READ_DATA Position */ -#define SDMMC_CTRL_ABORT_READ_DATA_Msk (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos) /*!< SDMMC CTRL: ABORT_READ_DATA Mask */ -#define SDMMC_CTRL_SEND_CCSD_Pos 9 /*!< SDMMC CTRL: SEND_CCSD Position */ -#define SDMMC_CTRL_SEND_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos) /*!< SDMMC CTRL: SEND_CCSD Mask */ -#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos 10 /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */ -#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos) /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */ -#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos 11 /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */ -#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos) /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */ -#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos 16 /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */ -#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask */ -#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos 20 /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */ -#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask */ -#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos 24 /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */ -#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos) /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask */ -#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos 25 /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */ -#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos) /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask */ - -// --------------------------------------- SDMMC_PWREN ------------------------------------------ -#define SDMMC_PWREN_POWER_ENABLE_Pos 0 /*!< SDMMC PWREN: POWER_ENABLE Position */ -#define SDMMC_PWREN_POWER_ENABLE_Msk (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos) /*!< SDMMC PWREN: POWER_ENABLE Mask */ - -// -------------------------------------- SDMMC_CLKDIV ------------------------------------------ -#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos 0 /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */ -#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask */ -#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos 8 /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */ -#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask */ -#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos 16 /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */ -#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask */ -#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos 24 /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */ -#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask */ - -// -------------------------------------- SDMMC_CLKSRC ------------------------------------------ -#define SDMMC_CLKSRC_CLK_SOURCE_Pos 0 /*!< SDMMC CLKSRC: CLK_SOURCE Position */ -#define SDMMC_CLKSRC_CLK_SOURCE_Msk (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos) /*!< SDMMC CLKSRC: CLK_SOURCE Mask */ - -// -------------------------------------- SDMMC_CLKENA ------------------------------------------ -#define SDMMC_CLKENA_CCLK_ENABLE_Pos 0 /*!< SDMMC CLKENA: CCLK_ENABLE Position */ -#define SDMMC_CLKENA_CCLK_ENABLE_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos) /*!< SDMMC CLKENA: CCLK_ENABLE Mask */ -#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos 16 /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */ -#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos) /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask */ - -// --------------------------------------- SDMMC_TMOUT ------------------------------------------ -#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos 0 /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */ -#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos) /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask */ -#define SDMMC_TMOUT_DATA_TIMEOUT_Pos 8 /*!< SDMMC TMOUT: DATA_TIMEOUT Position */ -#define SDMMC_TMOUT_DATA_TIMEOUT_Msk (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos) /*!< SDMMC TMOUT: DATA_TIMEOUT Mask */ - -// --------------------------------------- SDMMC_CTYPE ------------------------------------------ -#define SDMMC_CTYPE_CARD_WIDTH0_Pos 0 /*!< SDMMC CTYPE: CARD_WIDTH0 Position */ -#define SDMMC_CTYPE_CARD_WIDTH0_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos) /*!< SDMMC CTYPE: CARD_WIDTH0 Mask */ -#define SDMMC_CTYPE_CARD_WIDTH1_Pos 16 /*!< SDMMC CTYPE: CARD_WIDTH1 Position */ -#define SDMMC_CTYPE_CARD_WIDTH1_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos) /*!< SDMMC CTYPE: CARD_WIDTH1 Mask */ - -// -------------------------------------- SDMMC_BLKSIZ ------------------------------------------ -#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos 0 /*!< SDMMC BLKSIZ: BLOCK_SIZE Position */ -#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos) /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask */ - -// -------------------------------------- SDMMC_BYTCNT ------------------------------------------ -#define SDMMC_BYTCNT_BYTE_COUNT_Pos 0 /*!< SDMMC BYTCNT: BYTE_COUNT Position */ -#define SDMMC_BYTCNT_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos) /*!< SDMMC BYTCNT: BYTE_COUNT Mask */ - -// -------------------------------------- SDMMC_INTMASK ----------------------------------------- -#define SDMMC_INTMASK_CDET_Pos 0 /*!< SDMMC INTMASK: CDET Position */ -#define SDMMC_INTMASK_CDET_Msk (0x01UL << SDMMC_INTMASK_CDET_Pos) /*!< SDMMC INTMASK: CDET Mask */ -#define SDMMC_INTMASK_RE_Pos 1 /*!< SDMMC INTMASK: RE Position */ -#define SDMMC_INTMASK_RE_Msk (0x01UL << SDMMC_INTMASK_RE_Pos) /*!< SDMMC INTMASK: RE Mask */ -#define SDMMC_INTMASK_CDONE_Pos 2 /*!< SDMMC INTMASK: CDONE Position */ -#define SDMMC_INTMASK_CDONE_Msk (0x01UL << SDMMC_INTMASK_CDONE_Pos) /*!< SDMMC INTMASK: CDONE Mask */ -#define SDMMC_INTMASK_DTO_Pos 3 /*!< SDMMC INTMASK: DTO Position */ -#define SDMMC_INTMASK_DTO_Msk (0x01UL << SDMMC_INTMASK_DTO_Pos) /*!< SDMMC INTMASK: DTO Mask */ -#define SDMMC_INTMASK_TXDR_Pos 4 /*!< SDMMC INTMASK: TXDR Position */ -#define SDMMC_INTMASK_TXDR_Msk (0x01UL << SDMMC_INTMASK_TXDR_Pos) /*!< SDMMC INTMASK: TXDR Mask */ -#define SDMMC_INTMASK_RXDR_Pos 5 /*!< SDMMC INTMASK: RXDR Position */ -#define SDMMC_INTMASK_RXDR_Msk (0x01UL << SDMMC_INTMASK_RXDR_Pos) /*!< SDMMC INTMASK: RXDR Mask */ -#define SDMMC_INTMASK_RCRC_Pos 6 /*!< SDMMC INTMASK: RCRC Position */ -#define SDMMC_INTMASK_RCRC_Msk (0x01UL << SDMMC_INTMASK_RCRC_Pos) /*!< SDMMC INTMASK: RCRC Mask */ -#define SDMMC_INTMASK_DCRC_Pos 7 /*!< SDMMC INTMASK: DCRC Position */ -#define SDMMC_INTMASK_DCRC_Msk (0x01UL << SDMMC_INTMASK_DCRC_Pos) /*!< SDMMC INTMASK: DCRC Mask */ -#define SDMMC_INTMASK_RTO_Pos 8 /*!< SDMMC INTMASK: RTO Position */ -#define SDMMC_INTMASK_RTO_Msk (0x01UL << SDMMC_INTMASK_RTO_Pos) /*!< SDMMC INTMASK: RTO Mask */ -#define SDMMC_INTMASK_DRTO_Pos 9 /*!< SDMMC INTMASK: DRTO Position */ -#define SDMMC_INTMASK_DRTO_Msk (0x01UL << SDMMC_INTMASK_DRTO_Pos) /*!< SDMMC INTMASK: DRTO Mask */ -#define SDMMC_INTMASK_HTO_Pos 10 /*!< SDMMC INTMASK: HTO Position */ -#define SDMMC_INTMASK_HTO_Msk (0x01UL << SDMMC_INTMASK_HTO_Pos) /*!< SDMMC INTMASK: HTO Mask */ -#define SDMMC_INTMASK_FRUN_Pos 11 /*!< SDMMC INTMASK: FRUN Position */ -#define SDMMC_INTMASK_FRUN_Msk (0x01UL << SDMMC_INTMASK_FRUN_Pos) /*!< SDMMC INTMASK: FRUN Mask */ -#define SDMMC_INTMASK_HLE_Pos 12 /*!< SDMMC INTMASK: HLE Position */ -#define SDMMC_INTMASK_HLE_Msk (0x01UL << SDMMC_INTMASK_HLE_Pos) /*!< SDMMC INTMASK: HLE Mask */ -#define SDMMC_INTMASK_SBE_Pos 13 /*!< SDMMC INTMASK: SBE Position */ -#define SDMMC_INTMASK_SBE_Msk (0x01UL << SDMMC_INTMASK_SBE_Pos) /*!< SDMMC INTMASK: SBE Mask */ -#define SDMMC_INTMASK_ACD_Pos 14 /*!< SDMMC INTMASK: ACD Position */ -#define SDMMC_INTMASK_ACD_Msk (0x01UL << SDMMC_INTMASK_ACD_Pos) /*!< SDMMC INTMASK: ACD Mask */ -#define SDMMC_INTMASK_EBE_Pos 15 /*!< SDMMC INTMASK: EBE Position */ -#define SDMMC_INTMASK_EBE_Msk (0x01UL << SDMMC_INTMASK_EBE_Pos) /*!< SDMMC INTMASK: EBE Mask */ -#define SDMMC_INTMASK_SDIO_INT_MASK_Pos 16 /*!< SDMMC INTMASK: SDIO_INT_MASK Position */ -#define SDMMC_INTMASK_SDIO_INT_MASK_Msk (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos) /*!< SDMMC INTMASK: SDIO_INT_MASK Mask */ - -// -------------------------------------- SDMMC_CMDARG ------------------------------------------ -#define SDMMC_CMDARG_CMD_ARG_Pos 0 /*!< SDMMC CMDARG: CMD_ARG Position */ -#define SDMMC_CMDARG_CMD_ARG_Msk (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos) /*!< SDMMC CMDARG: CMD_ARG Mask */ - -// ---------------------------------------- SDMMC_CMD ------------------------------------------- -#define SDMMC_CMD_CMD_INDEX_Pos 0 /*!< SDMMC CMD: CMD_INDEX Position */ -#define SDMMC_CMD_CMD_INDEX_Msk (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos) /*!< SDMMC CMD: CMD_INDEX Mask */ -#define SDMMC_CMD_RESPONSE_EXPECT_Pos 6 /*!< SDMMC CMD: RESPONSE_EXPECT Position */ -#define SDMMC_CMD_RESPONSE_EXPECT_Msk (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos) /*!< SDMMC CMD: RESPONSE_EXPECT Mask */ -#define SDMMC_CMD_RESPONSE_LENGTH_Pos 7 /*!< SDMMC CMD: RESPONSE_LENGTH Position */ -#define SDMMC_CMD_RESPONSE_LENGTH_Msk (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos) /*!< SDMMC CMD: RESPONSE_LENGTH Mask */ -#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos 8 /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */ -#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos) /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask */ -#define SDMMC_CMD_DATA_EXPECTED_Pos 9 /*!< SDMMC CMD: DATA_EXPECTED Position */ -#define SDMMC_CMD_DATA_EXPECTED_Msk (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos) /*!< SDMMC CMD: DATA_EXPECTED Mask */ -#define SDMMC_CMD_READ_WRITE_Pos 10 /*!< SDMMC CMD: READ_WRITE Position */ -#define SDMMC_CMD_READ_WRITE_Msk (0x01UL << SDMMC_CMD_READ_WRITE_Pos) /*!< SDMMC CMD: READ_WRITE Mask */ -#define SDMMC_CMD_TRANSFER_MODE_Pos 11 /*!< SDMMC CMD: TRANSFER_MODE Position */ -#define SDMMC_CMD_TRANSFER_MODE_Msk (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos) /*!< SDMMC CMD: TRANSFER_MODE Mask */ -#define SDMMC_CMD_SEND_AUTO_STOP_Pos 12 /*!< SDMMC CMD: SEND_AUTO_STOP Position */ -#define SDMMC_CMD_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos) /*!< SDMMC CMD: SEND_AUTO_STOP Mask */ -#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos 13 /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */ -#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos) /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */ -#define SDMMC_CMD_STOP_ABORT_CMd_Pos 14 /*!< SDMMC CMD: STOP_ABORT_CMd Position */ -#define SDMMC_CMD_STOP_ABORT_CMd_Msk (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos) /*!< SDMMC CMD: STOP_ABORT_CMd Mask */ -#define SDMMC_CMD_SEND_INITIALIZATION_Pos 15 /*!< SDMMC CMD: SEND_INITIALIZATION Position */ -#define SDMMC_CMD_SEND_INITIALIZATION_Msk (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos) /*!< SDMMC CMD: SEND_INITIALIZATION Mask */ -#define SDMMC_CMD_CARD_NUMBER_Pos 16 /*!< SDMMC CMD: CARD_NUMBER Position */ -#define SDMMC_CMD_CARD_NUMBER_Msk (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos) /*!< SDMMC CMD: CARD_NUMBER Mask */ -#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos 21 /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */ -#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos) /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */ -#define SDMMC_CMD_READ_CEATA_DEVICE_Pos 22 /*!< SDMMC CMD: READ_CEATA_DEVICE Position */ -#define SDMMC_CMD_READ_CEATA_DEVICE_Msk (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos) /*!< SDMMC CMD: READ_CEATA_DEVICE Mask */ -#define SDMMC_CMD_CCS_EXPECTED_Pos 23 /*!< SDMMC CMD: CCS_EXPECTED Position */ -#define SDMMC_CMD_CCS_EXPECTED_Msk (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos) /*!< SDMMC CMD: CCS_EXPECTED Mask */ -#define SDMMC_CMD_ENABLE_BOOT_Pos 24 /*!< SDMMC CMD: ENABLE_BOOT Position */ -#define SDMMC_CMD_ENABLE_BOOT_Msk (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos) /*!< SDMMC CMD: ENABLE_BOOT Mask */ -#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos 25 /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */ -#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos) /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask */ -#define SDMMC_CMD_DISABLE_BOOT_Pos 26 /*!< SDMMC CMD: DISABLE_BOOT Position */ -#define SDMMC_CMD_DISABLE_BOOT_Msk (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos) /*!< SDMMC CMD: DISABLE_BOOT Mask */ -#define SDMMC_CMD_BOOT_MODE_Pos 27 /*!< SDMMC CMD: BOOT_MODE Position */ -#define SDMMC_CMD_BOOT_MODE_Msk (0x01UL << SDMMC_CMD_BOOT_MODE_Pos) /*!< SDMMC CMD: BOOT_MODE Mask */ -#define SDMMC_CMD_VOLT_SWITCH_Pos 28 /*!< SDMMC CMD: VOLT_SWITCH Position */ -#define SDMMC_CMD_VOLT_SWITCH_Msk (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos) /*!< SDMMC CMD: VOLT_SWITCH Mask */ -#define SDMMC_CMD_START_CMD_Pos 31 /*!< SDMMC CMD: START_CMD Position */ -#define SDMMC_CMD_START_CMD_Msk (0x01UL << SDMMC_CMD_START_CMD_Pos) /*!< SDMMC CMD: START_CMD Mask */ - -// --------------------------------------- SDMMC_RESP0 ------------------------------------------ -#define SDMMC_RESP0_RESPONSE0_Pos 0 /*!< SDMMC RESP0: RESPONSE0 Position */ -#define SDMMC_RESP0_RESPONSE0_Msk (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos) /*!< SDMMC RESP0: RESPONSE0 Mask */ - -// --------------------------------------- SDMMC_RESP1 ------------------------------------------ -#define SDMMC_RESP1_RESPONSE1_Pos 0 /*!< SDMMC RESP1: RESPONSE1 Position */ -#define SDMMC_RESP1_RESPONSE1_Msk (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos) /*!< SDMMC RESP1: RESPONSE1 Mask */ - -// --------------------------------------- SDMMC_RESP2 ------------------------------------------ -#define SDMMC_RESP2_RESPONSE2_Pos 0 /*!< SDMMC RESP2: RESPONSE2 Position */ -#define SDMMC_RESP2_RESPONSE2_Msk (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos) /*!< SDMMC RESP2: RESPONSE2 Mask */ - -// --------------------------------------- SDMMC_RESP3 ------------------------------------------ -#define SDMMC_RESP3_RESPONSE3_Pos 0 /*!< SDMMC RESP3: RESPONSE3 Position */ -#define SDMMC_RESP3_RESPONSE3_Msk (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos) /*!< SDMMC RESP3: RESPONSE3 Mask */ - -// -------------------------------------- SDMMC_MINTSTS ----------------------------------------- -#define SDMMC_MINTSTS_CDET_Pos 0 /*!< SDMMC MINTSTS: CDET Position */ -#define SDMMC_MINTSTS_CDET_Msk (0x01UL << SDMMC_MINTSTS_CDET_Pos) /*!< SDMMC MINTSTS: CDET Mask */ -#define SDMMC_MINTSTS_RE_Pos 1 /*!< SDMMC MINTSTS: RE Position */ -#define SDMMC_MINTSTS_RE_Msk (0x01UL << SDMMC_MINTSTS_RE_Pos) /*!< SDMMC MINTSTS: RE Mask */ -#define SDMMC_MINTSTS_CDONE_Pos 2 /*!< SDMMC MINTSTS: CDONE Position */ -#define SDMMC_MINTSTS_CDONE_Msk (0x01UL << SDMMC_MINTSTS_CDONE_Pos) /*!< SDMMC MINTSTS: CDONE Mask */ -#define SDMMC_MINTSTS_DTO_Pos 3 /*!< SDMMC MINTSTS: DTO Position */ -#define SDMMC_MINTSTS_DTO_Msk (0x01UL << SDMMC_MINTSTS_DTO_Pos) /*!< SDMMC MINTSTS: DTO Mask */ -#define SDMMC_MINTSTS_TXDR_Pos 4 /*!< SDMMC MINTSTS: TXDR Position */ -#define SDMMC_MINTSTS_TXDR_Msk (0x01UL << SDMMC_MINTSTS_TXDR_Pos) /*!< SDMMC MINTSTS: TXDR Mask */ -#define SDMMC_MINTSTS_RXDR_Pos 5 /*!< SDMMC MINTSTS: RXDR Position */ -#define SDMMC_MINTSTS_RXDR_Msk (0x01UL << SDMMC_MINTSTS_RXDR_Pos) /*!< SDMMC MINTSTS: RXDR Mask */ -#define SDMMC_MINTSTS_RCRC_Pos 6 /*!< SDMMC MINTSTS: RCRC Position */ -#define SDMMC_MINTSTS_RCRC_Msk (0x01UL << SDMMC_MINTSTS_RCRC_Pos) /*!< SDMMC MINTSTS: RCRC Mask */ -#define SDMMC_MINTSTS_DCRC_Pos 7 /*!< SDMMC MINTSTS: DCRC Position */ -#define SDMMC_MINTSTS_DCRC_Msk (0x01UL << SDMMC_MINTSTS_DCRC_Pos) /*!< SDMMC MINTSTS: DCRC Mask */ -#define SDMMC_MINTSTS_RTO_Pos 8 /*!< SDMMC MINTSTS: RTO Position */ -#define SDMMC_MINTSTS_RTO_Msk (0x01UL << SDMMC_MINTSTS_RTO_Pos) /*!< SDMMC MINTSTS: RTO Mask */ -#define SDMMC_MINTSTS_DRTO_Pos 9 /*!< SDMMC MINTSTS: DRTO Position */ -#define SDMMC_MINTSTS_DRTO_Msk (0x01UL << SDMMC_MINTSTS_DRTO_Pos) /*!< SDMMC MINTSTS: DRTO Mask */ -#define SDMMC_MINTSTS_HTO_Pos 10 /*!< SDMMC MINTSTS: HTO Position */ -#define SDMMC_MINTSTS_HTO_Msk (0x01UL << SDMMC_MINTSTS_HTO_Pos) /*!< SDMMC MINTSTS: HTO Mask */ -#define SDMMC_MINTSTS_FRUN_Pos 11 /*!< SDMMC MINTSTS: FRUN Position */ -#define SDMMC_MINTSTS_FRUN_Msk (0x01UL << SDMMC_MINTSTS_FRUN_Pos) /*!< SDMMC MINTSTS: FRUN Mask */ -#define SDMMC_MINTSTS_HLE_Pos 12 /*!< SDMMC MINTSTS: HLE Position */ -#define SDMMC_MINTSTS_HLE_Msk (0x01UL << SDMMC_MINTSTS_HLE_Pos) /*!< SDMMC MINTSTS: HLE Mask */ -#define SDMMC_MINTSTS_SBE_Pos 13 /*!< SDMMC MINTSTS: SBE Position */ -#define SDMMC_MINTSTS_SBE_Msk (0x01UL << SDMMC_MINTSTS_SBE_Pos) /*!< SDMMC MINTSTS: SBE Mask */ -#define SDMMC_MINTSTS_ACD_Pos 14 /*!< SDMMC MINTSTS: ACD Position */ -#define SDMMC_MINTSTS_ACD_Msk (0x01UL << SDMMC_MINTSTS_ACD_Pos) /*!< SDMMC MINTSTS: ACD Mask */ -#define SDMMC_MINTSTS_EBE_Pos 15 /*!< SDMMC MINTSTS: EBE Position */ -#define SDMMC_MINTSTS_EBE_Msk (0x01UL << SDMMC_MINTSTS_EBE_Pos) /*!< SDMMC MINTSTS: EBE Mask */ -#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */ -#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask */ - -// -------------------------------------- SDMMC_RINTSTS ----------------------------------------- -#define SDMMC_RINTSTS_CDET_Pos 0 /*!< SDMMC RINTSTS: CDET Position */ -#define SDMMC_RINTSTS_CDET_Msk (0x01UL << SDMMC_RINTSTS_CDET_Pos) /*!< SDMMC RINTSTS: CDET Mask */ -#define SDMMC_RINTSTS_RE_Pos 1 /*!< SDMMC RINTSTS: RE Position */ -#define SDMMC_RINTSTS_RE_Msk (0x01UL << SDMMC_RINTSTS_RE_Pos) /*!< SDMMC RINTSTS: RE Mask */ -#define SDMMC_RINTSTS_CDONE_Pos 2 /*!< SDMMC RINTSTS: CDONE Position */ -#define SDMMC_RINTSTS_CDONE_Msk (0x01UL << SDMMC_RINTSTS_CDONE_Pos) /*!< SDMMC RINTSTS: CDONE Mask */ -#define SDMMC_RINTSTS_DTO_Pos 3 /*!< SDMMC RINTSTS: DTO Position */ -#define SDMMC_RINTSTS_DTO_Msk (0x01UL << SDMMC_RINTSTS_DTO_Pos) /*!< SDMMC RINTSTS: DTO Mask */ -#define SDMMC_RINTSTS_TXDR_Pos 4 /*!< SDMMC RINTSTS: TXDR Position */ -#define SDMMC_RINTSTS_TXDR_Msk (0x01UL << SDMMC_RINTSTS_TXDR_Pos) /*!< SDMMC RINTSTS: TXDR Mask */ -#define SDMMC_RINTSTS_RXDR_Pos 5 /*!< SDMMC RINTSTS: RXDR Position */ -#define SDMMC_RINTSTS_RXDR_Msk (0x01UL << SDMMC_RINTSTS_RXDR_Pos) /*!< SDMMC RINTSTS: RXDR Mask */ -#define SDMMC_RINTSTS_RCRC_Pos 6 /*!< SDMMC RINTSTS: RCRC Position */ -#define SDMMC_RINTSTS_RCRC_Msk (0x01UL << SDMMC_RINTSTS_RCRC_Pos) /*!< SDMMC RINTSTS: RCRC Mask */ -#define SDMMC_RINTSTS_DCRC_Pos 7 /*!< SDMMC RINTSTS: DCRC Position */ -#define SDMMC_RINTSTS_DCRC_Msk (0x01UL << SDMMC_RINTSTS_DCRC_Pos) /*!< SDMMC RINTSTS: DCRC Mask */ -#define SDMMC_RINTSTS_RTO_BAR_Pos 8 /*!< SDMMC RINTSTS: RTO_BAR Position */ -#define SDMMC_RINTSTS_RTO_BAR_Msk (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos) /*!< SDMMC RINTSTS: RTO_BAR Mask */ -#define SDMMC_RINTSTS_DRTO_BDS_Pos 9 /*!< SDMMC RINTSTS: DRTO_BDS Position */ -#define SDMMC_RINTSTS_DRTO_BDS_Msk (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos) /*!< SDMMC RINTSTS: DRTO_BDS Mask */ -#define SDMMC_RINTSTS_HTO_Pos 10 /*!< SDMMC RINTSTS: HTO Position */ -#define SDMMC_RINTSTS_HTO_Msk (0x01UL << SDMMC_RINTSTS_HTO_Pos) /*!< SDMMC RINTSTS: HTO Mask */ -#define SDMMC_RINTSTS_FRUN_Pos 11 /*!< SDMMC RINTSTS: FRUN Position */ -#define SDMMC_RINTSTS_FRUN_Msk (0x01UL << SDMMC_RINTSTS_FRUN_Pos) /*!< SDMMC RINTSTS: FRUN Mask */ -#define SDMMC_RINTSTS_HLE_Pos 12 /*!< SDMMC RINTSTS: HLE Position */ -#define SDMMC_RINTSTS_HLE_Msk (0x01UL << SDMMC_RINTSTS_HLE_Pos) /*!< SDMMC RINTSTS: HLE Mask */ -#define SDMMC_RINTSTS_SBE_Pos 13 /*!< SDMMC RINTSTS: SBE Position */ -#define SDMMC_RINTSTS_SBE_Msk (0x01UL << SDMMC_RINTSTS_SBE_Pos) /*!< SDMMC RINTSTS: SBE Mask */ -#define SDMMC_RINTSTS_ACD_Pos 14 /*!< SDMMC RINTSTS: ACD Position */ -#define SDMMC_RINTSTS_ACD_Msk (0x01UL << SDMMC_RINTSTS_ACD_Pos) /*!< SDMMC RINTSTS: ACD Mask */ -#define SDMMC_RINTSTS_EBE_Pos 15 /*!< SDMMC RINTSTS: EBE Position */ -#define SDMMC_RINTSTS_EBE_Msk (0x01UL << SDMMC_RINTSTS_EBE_Pos) /*!< SDMMC RINTSTS: EBE Mask */ -#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */ -#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask */ - -// -------------------------------------- SDMMC_STATUS ------------------------------------------ -#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos 0 /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */ -#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */ -#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos 1 /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */ -#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */ -#define SDMMC_STATUS_FIFO_EMPTY_Pos 2 /*!< SDMMC STATUS: FIFO_EMPTY Position */ -#define SDMMC_STATUS_FIFO_EMPTY_Msk (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos) /*!< SDMMC STATUS: FIFO_EMPTY Mask */ -#define SDMMC_STATUS_FIFO_FULL_Pos 3 /*!< SDMMC STATUS: FIFO_FULL Position */ -#define SDMMC_STATUS_FIFO_FULL_Msk (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos) /*!< SDMMC STATUS: FIFO_FULL Mask */ -#define SDMMC_STATUS_CMDFSMSTATES_Pos 4 /*!< SDMMC STATUS: CMDFSMSTATES Position */ -#define SDMMC_STATUS_CMDFSMSTATES_Msk (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos) /*!< SDMMC STATUS: CMDFSMSTATES Mask */ -#define SDMMC_STATUS_DATA_3_STATUS_Pos 8 /*!< SDMMC STATUS: DATA_3_STATUS Position */ -#define SDMMC_STATUS_DATA_3_STATUS_Msk (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos) /*!< SDMMC STATUS: DATA_3_STATUS Mask */ -#define SDMMC_STATUS_DATA_BUSY_Pos 9 /*!< SDMMC STATUS: DATA_BUSY Position */ -#define SDMMC_STATUS_DATA_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos) /*!< SDMMC STATUS: DATA_BUSY Mask */ -#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos 10 /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */ -#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos) /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */ -#define SDMMC_STATUS_RESPONSE_INDEX_Pos 11 /*!< SDMMC STATUS: RESPONSE_INDEX Position */ -#define SDMMC_STATUS_RESPONSE_INDEX_Msk (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos) /*!< SDMMC STATUS: RESPONSE_INDEX Mask */ -#define SDMMC_STATUS_FIFO_COUNT_Pos 17 /*!< SDMMC STATUS: FIFO_COUNT Position */ -#define SDMMC_STATUS_FIFO_COUNT_Msk (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos) /*!< SDMMC STATUS: FIFO_COUNT Mask */ -#define SDMMC_STATUS_DMA_ACK_Pos 30 /*!< SDMMC STATUS: DMA_ACK Position */ -#define SDMMC_STATUS_DMA_ACK_Msk (0x01UL << SDMMC_STATUS_DMA_ACK_Pos) /*!< SDMMC STATUS: DMA_ACK Mask */ -#define SDMMC_STATUS_DMA_REQ_Pos 31 /*!< SDMMC STATUS: DMA_REQ Position */ -#define SDMMC_STATUS_DMA_REQ_Msk (0x01UL << SDMMC_STATUS_DMA_REQ_Pos) /*!< SDMMC STATUS: DMA_REQ Mask */ - -// -------------------------------------- SDMMC_FIFOTH ------------------------------------------ -#define SDMMC_FIFOTH_TX_WMARK_Pos 0 /*!< SDMMC FIFOTH: TX_WMARK Position */ -#define SDMMC_FIFOTH_TX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos) /*!< SDMMC FIFOTH: TX_WMARK Mask */ -#define SDMMC_FIFOTH_RX_WMARK_Pos 16 /*!< SDMMC FIFOTH: RX_WMARK Position */ -#define SDMMC_FIFOTH_RX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos) /*!< SDMMC FIFOTH: RX_WMARK Mask */ -#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos 28 /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */ -#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */ - -// -------------------------------------- SDMMC_CDETECT ----------------------------------------- -#define SDMMC_CDETECT_CARD_DETECT_N_Pos 0 /*!< SDMMC CDETECT: CARD_DETECT_N Position */ -#define SDMMC_CDETECT_CARD_DETECT_N_Msk (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos) /*!< SDMMC CDETECT: CARD_DETECT_N Mask */ - -// -------------------------------------- SDMMC_WRTPRT ------------------------------------------ -#define SDMMC_WRTPRT_WRITE_PROTECT_Pos 0 /*!< SDMMC WRTPRT: WRITE_PROTECT Position */ -#define SDMMC_WRTPRT_WRITE_PROTECT_Msk (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos) /*!< SDMMC WRTPRT: WRITE_PROTECT Mask */ - -// --------------------------------------- SDMMC_GPIO ------------------------------------------- -#define SDMMC_GPIO_GPI_Pos 0 /*!< SDMMC GPIO: GPI Position */ -#define SDMMC_GPIO_GPI_Msk (0x000000ffUL << SDMMC_GPIO_GPI_Pos) /*!< SDMMC GPIO: GPI Mask */ -#define SDMMC_GPIO_GPO_Pos 8 /*!< SDMMC GPIO: GPO Position */ -#define SDMMC_GPIO_GPO_Msk (0x0000ffffUL << SDMMC_GPIO_GPO_Pos) /*!< SDMMC GPIO: GPO Mask */ - -// -------------------------------------- SDMMC_TCBCNT ------------------------------------------ -#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos 0 /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */ -#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos) /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */ - -// -------------------------------------- SDMMC_TBBCNT ------------------------------------------ -#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos 0 /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */ -#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos) /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */ - -// -------------------------------------- SDMMC_DEBNCE ------------------------------------------ -#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos 0 /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */ -#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos) /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask */ - -// --------------------------------------- SDMMC_USRID ------------------------------------------ -#define SDMMC_USRID_USRID_Pos 0 /*!< SDMMC USRID: USRID Position */ -#define SDMMC_USRID_USRID_Msk (0xffffffffUL << SDMMC_USRID_USRID_Pos) /*!< SDMMC USRID: USRID Mask */ - -// --------------------------------------- SDMMC_VERID ------------------------------------------ -#define SDMMC_VERID_VERID_Pos 0 /*!< SDMMC VERID: VERID Position */ -#define SDMMC_VERID_VERID_Msk (0xffffffffUL << SDMMC_VERID_VERID_Pos) /*!< SDMMC VERID: VERID Mask */ - -// -------------------------------------- SDMMC_UHS_REG ----------------------------------------- -#define SDMMC_UHS_REG_VOLT_REG_Pos 0 /*!< SDMMC UHS_REG: VOLT_REG Position */ -#define SDMMC_UHS_REG_VOLT_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos) /*!< SDMMC UHS_REG: VOLT_REG Mask */ -#define SDMMC_UHS_REG_DDR_REG_Pos 16 /*!< SDMMC UHS_REG: DDR_REG Position */ -#define SDMMC_UHS_REG_DDR_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos) /*!< SDMMC UHS_REG: DDR_REG Mask */ - -// --------------------------------------- SDMMC_RST_N ------------------------------------------ -#define SDMMC_RST_N_CARD_RESET_Pos 0 /*!< SDMMC RST_N: CARD_RESET Position */ -#define SDMMC_RST_N_CARD_RESET_Msk (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos) /*!< SDMMC RST_N: CARD_RESET Mask */ - -// --------------------------------------- SDMMC_BMOD ------------------------------------------- -#define SDMMC_BMOD_SWR_Pos 0 /*!< SDMMC BMOD: SWR Position */ -#define SDMMC_BMOD_SWR_Msk (0x01UL << SDMMC_BMOD_SWR_Pos) /*!< SDMMC BMOD: SWR Mask */ -#define SDMMC_BMOD_FB_Pos 1 /*!< SDMMC BMOD: FB Position */ -#define SDMMC_BMOD_FB_Msk (0x01UL << SDMMC_BMOD_FB_Pos) /*!< SDMMC BMOD: FB Mask */ -#define SDMMC_BMOD_DSL_Pos 2 /*!< SDMMC BMOD: DSL Position */ -#define SDMMC_BMOD_DSL_Msk (0x1fUL << SDMMC_BMOD_DSL_Pos) /*!< SDMMC BMOD: DSL Mask */ -#define SDMMC_BMOD_DE_Pos 7 /*!< SDMMC BMOD: DE Position */ -#define SDMMC_BMOD_DE_Msk (0x01UL << SDMMC_BMOD_DE_Pos) /*!< SDMMC BMOD: DE Mask */ -#define SDMMC_BMOD_PBL_Pos 8 /*!< SDMMC BMOD: PBL Position */ -#define SDMMC_BMOD_PBL_Msk (0x07UL << SDMMC_BMOD_PBL_Pos) /*!< SDMMC BMOD: PBL Mask */ - -// -------------------------------------- SDMMC_PLDMND ------------------------------------------ -#define SDMMC_PLDMND_PD_Pos 0 /*!< SDMMC PLDMND: PD Position */ -#define SDMMC_PLDMND_PD_Msk (0xffffffffUL << SDMMC_PLDMND_PD_Pos) /*!< SDMMC PLDMND: PD Mask */ - -// -------------------------------------- SDMMC_DBADDR ------------------------------------------ -#define SDMMC_DBADDR_SDL_Pos 0 /*!< SDMMC DBADDR: SDL Position */ -#define SDMMC_DBADDR_SDL_Msk (0xffffffffUL << SDMMC_DBADDR_SDL_Pos) /*!< SDMMC DBADDR: SDL Mask */ - -// --------------------------------------- SDMMC_IDSTS ------------------------------------------ -#define SDMMC_IDSTS_TI_Pos 0 /*!< SDMMC IDSTS: TI Position */ -#define SDMMC_IDSTS_TI_Msk (0x01UL << SDMMC_IDSTS_TI_Pos) /*!< SDMMC IDSTS: TI Mask */ -#define SDMMC_IDSTS_RI_Pos 1 /*!< SDMMC IDSTS: RI Position */ -#define SDMMC_IDSTS_RI_Msk (0x01UL << SDMMC_IDSTS_RI_Pos) /*!< SDMMC IDSTS: RI Mask */ -#define SDMMC_IDSTS_FBE_Pos 2 /*!< SDMMC IDSTS: FBE Position */ -#define SDMMC_IDSTS_FBE_Msk (0x01UL << SDMMC_IDSTS_FBE_Pos) /*!< SDMMC IDSTS: FBE Mask */ -#define SDMMC_IDSTS_DU_Pos 4 /*!< SDMMC IDSTS: DU Position */ -#define SDMMC_IDSTS_DU_Msk (0x01UL << SDMMC_IDSTS_DU_Pos) /*!< SDMMC IDSTS: DU Mask */ -#define SDMMC_IDSTS_CES_Pos 5 /*!< SDMMC IDSTS: CES Position */ -#define SDMMC_IDSTS_CES_Msk (0x01UL << SDMMC_IDSTS_CES_Pos) /*!< SDMMC IDSTS: CES Mask */ -#define SDMMC_IDSTS_NIS_Pos 8 /*!< SDMMC IDSTS: NIS Position */ -#define SDMMC_IDSTS_NIS_Msk (0x01UL << SDMMC_IDSTS_NIS_Pos) /*!< SDMMC IDSTS: NIS Mask */ -#define SDMMC_IDSTS_AIS_Pos 9 /*!< SDMMC IDSTS: AIS Position */ -#define SDMMC_IDSTS_AIS_Msk (0x01UL << SDMMC_IDSTS_AIS_Pos) /*!< SDMMC IDSTS: AIS Mask */ -#define SDMMC_IDSTS_EB_Pos 10 /*!< SDMMC IDSTS: EB Position */ -#define SDMMC_IDSTS_EB_Msk (0x07UL << SDMMC_IDSTS_EB_Pos) /*!< SDMMC IDSTS: EB Mask */ -#define SDMMC_IDSTS_FSM_Pos 13 /*!< SDMMC IDSTS: FSM Position */ -#define SDMMC_IDSTS_FSM_Msk (0x0fUL << SDMMC_IDSTS_FSM_Pos) /*!< SDMMC IDSTS: FSM Mask */ - -// -------------------------------------- SDMMC_IDINTEN ----------------------------------------- -#define SDMMC_IDINTEN_TI_Pos 0 /*!< SDMMC IDINTEN: TI Position */ -#define SDMMC_IDINTEN_TI_Msk (0x01UL << SDMMC_IDINTEN_TI_Pos) /*!< SDMMC IDINTEN: TI Mask */ -#define SDMMC_IDINTEN_RI_Pos 1 /*!< SDMMC IDINTEN: RI Position */ -#define SDMMC_IDINTEN_RI_Msk (0x01UL << SDMMC_IDINTEN_RI_Pos) /*!< SDMMC IDINTEN: RI Mask */ -#define SDMMC_IDINTEN_FBE_Pos 2 /*!< SDMMC IDINTEN: FBE Position */ -#define SDMMC_IDINTEN_FBE_Msk (0x01UL << SDMMC_IDINTEN_FBE_Pos) /*!< SDMMC IDINTEN: FBE Mask */ -#define SDMMC_IDINTEN_DU_Pos 4 /*!< SDMMC IDINTEN: DU Position */ -#define SDMMC_IDINTEN_DU_Msk (0x01UL << SDMMC_IDINTEN_DU_Pos) /*!< SDMMC IDINTEN: DU Mask */ -#define SDMMC_IDINTEN_CES_Pos 5 /*!< SDMMC IDINTEN: CES Position */ -#define SDMMC_IDINTEN_CES_Msk (0x01UL << SDMMC_IDINTEN_CES_Pos) /*!< SDMMC IDINTEN: CES Mask */ -#define SDMMC_IDINTEN_NIS_Pos 8 /*!< SDMMC IDINTEN: NIS Position */ -#define SDMMC_IDINTEN_NIS_Msk (0x01UL << SDMMC_IDINTEN_NIS_Pos) /*!< SDMMC IDINTEN: NIS Mask */ -#define SDMMC_IDINTEN_AIS_Pos 9 /*!< SDMMC IDINTEN: AIS Position */ -#define SDMMC_IDINTEN_AIS_Msk (0x01UL << SDMMC_IDINTEN_AIS_Pos) /*!< SDMMC IDINTEN: AIS Mask */ - -// -------------------------------------- SDMMC_DSCADDR ----------------------------------------- -#define SDMMC_DSCADDR_HDA_Pos 0 /*!< SDMMC DSCADDR: HDA Position */ -#define SDMMC_DSCADDR_HDA_Msk (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos) /*!< SDMMC DSCADDR: HDA Mask */ - -// -------------------------------------- SDMMC_BUFADDR ----------------------------------------- -#define SDMMC_BUFADDR_HBA_Pos 0 /*!< SDMMC BUFADDR: HBA Position */ -#define SDMMC_BUFADDR_HBA_Msk (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos) /*!< SDMMC BUFADDR: HBA Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- EMC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- EMC_CONTROL ------------------------------------------ -#define EMC_CONTROL_E_Pos 0 /*!< EMC CONTROL: E Position */ -#define EMC_CONTROL_E_Msk (0x01UL << EMC_CONTROL_E_Pos) /*!< EMC CONTROL: E Mask */ -#define EMC_CONTROL_M_Pos 1 /*!< EMC CONTROL: M Position */ -#define EMC_CONTROL_M_Msk (0x01UL << EMC_CONTROL_M_Pos) /*!< EMC CONTROL: M Mask */ -#define EMC_CONTROL_L_Pos 2 /*!< EMC CONTROL: L Position */ -#define EMC_CONTROL_L_Msk (0x01UL << EMC_CONTROL_L_Pos) /*!< EMC CONTROL: L Mask */ - -// --------------------------------------- EMC_STATUS ------------------------------------------- -#define EMC_STATUS_B_Pos 0 /*!< EMC STATUS: B Position */ -#define EMC_STATUS_B_Msk (0x01UL << EMC_STATUS_B_Pos) /*!< EMC STATUS: B Mask */ -#define EMC_STATUS_S_Pos 1 /*!< EMC STATUS: S Position */ -#define EMC_STATUS_S_Msk (0x01UL << EMC_STATUS_S_Pos) /*!< EMC STATUS: S Mask */ -#define EMC_STATUS_SA_Pos 2 /*!< EMC STATUS: SA Position */ -#define EMC_STATUS_SA_Msk (0x01UL << EMC_STATUS_SA_Pos) /*!< EMC STATUS: SA Mask */ - -// --------------------------------------- EMC_CONFIG ------------------------------------------- -#define EMC_CONFIG_EM_Pos 0 /*!< EMC CONFIG: EM Position */ -#define EMC_CONFIG_EM_Msk (0x01UL << EMC_CONFIG_EM_Pos) /*!< EMC CONFIG: EM Mask */ -#define EMC_CONFIG_CR_Pos 8 /*!< EMC CONFIG: CR Position */ -#define EMC_CONFIG_CR_Msk (0x01UL << EMC_CONFIG_CR_Pos) /*!< EMC CONFIG: CR Mask */ - -// ----------------------------------- EMC_DYNAMICCONTROL --------------------------------------- -#define EMC_DYNAMICCONTROL_CE_Pos 0 /*!< EMC DYNAMICCONTROL: CE Position */ -#define EMC_DYNAMICCONTROL_CE_Msk (0x01UL << EMC_DYNAMICCONTROL_CE_Pos) /*!< EMC DYNAMICCONTROL: CE Mask */ -#define EMC_DYNAMICCONTROL_CS_Pos 1 /*!< EMC DYNAMICCONTROL: CS Position */ -#define EMC_DYNAMICCONTROL_CS_Msk (0x01UL << EMC_DYNAMICCONTROL_CS_Pos) /*!< EMC DYNAMICCONTROL: CS Mask */ -#define EMC_DYNAMICCONTROL_SR_Pos 2 /*!< EMC DYNAMICCONTROL: SR Position */ -#define EMC_DYNAMICCONTROL_SR_Msk (0x01UL << EMC_DYNAMICCONTROL_SR_Pos) /*!< EMC DYNAMICCONTROL: SR Mask */ -#define EMC_DYNAMICCONTROL_MMC_Pos 5 /*!< EMC DYNAMICCONTROL: MMC Position */ -#define EMC_DYNAMICCONTROL_MMC_Msk (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos) /*!< EMC DYNAMICCONTROL: MMC Mask */ -#define EMC_DYNAMICCONTROL_I_Pos 7 /*!< EMC DYNAMICCONTROL: I Position */ -#define EMC_DYNAMICCONTROL_I_Msk (0x03UL << EMC_DYNAMICCONTROL_I_Pos) /*!< EMC DYNAMICCONTROL: I Mask */ -#define EMC_DYNAMICCONTROL_DP_Pos 13 /*!< EMC DYNAMICCONTROL: DP Position */ -#define EMC_DYNAMICCONTROL_DP_Msk (0x01UL << EMC_DYNAMICCONTROL_DP_Pos) /*!< EMC DYNAMICCONTROL: DP Mask */ - -// ----------------------------------- EMC_DYNAMICREFRESH --------------------------------------- -#define EMC_DYNAMICREFRESH_REFRESH_Pos 0 /*!< EMC DYNAMICREFRESH: REFRESH Position */ -#define EMC_DYNAMICREFRESH_REFRESH_Msk (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos) /*!< EMC DYNAMICREFRESH: REFRESH Mask */ - -// ---------------------------------- EMC_DYNAMICREADCONFIG ------------------------------------- -#define EMC_DYNAMICREADCONFIG_RD_Pos 0 /*!< EMC DYNAMICREADCONFIG: RD Position */ -#define EMC_DYNAMICREADCONFIG_RD_Msk (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos) /*!< EMC DYNAMICREADCONFIG: RD Mask */ - -// -------------------------------------- EMC_DYNAMICRP ----------------------------------------- -#define EMC_DYNAMICRP_tRP_Pos 0 /*!< EMC DYNAMICRP: tRP Position */ -#define EMC_DYNAMICRP_tRP_Msk (0x0fUL << EMC_DYNAMICRP_tRP_Pos) /*!< EMC DYNAMICRP: tRP Mask */ - -// ------------------------------------- EMC_DYNAMICRAS ----------------------------------------- -#define EMC_DYNAMICRAS_tRAS_Pos 0 /*!< EMC DYNAMICRAS: tRAS Position */ -#define EMC_DYNAMICRAS_tRAS_Msk (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos) /*!< EMC DYNAMICRAS: tRAS Mask */ - -// ------------------------------------- EMC_DYNAMICSREX ---------------------------------------- -#define EMC_DYNAMICSREX_tSREX_Pos 0 /*!< EMC DYNAMICSREX: tSREX Position */ -#define EMC_DYNAMICSREX_tSREX_Msk (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos) /*!< EMC DYNAMICSREX: tSREX Mask */ - -// ------------------------------------- EMC_DYNAMICAPR ----------------------------------------- -#define EMC_DYNAMICAPR_tAPR_Pos 0 /*!< EMC DYNAMICAPR: tAPR Position */ -#define EMC_DYNAMICAPR_tAPR_Msk (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos) /*!< EMC DYNAMICAPR: tAPR Mask */ - -// ------------------------------------- EMC_DYNAMICDAL ----------------------------------------- -#define EMC_DYNAMICDAL_tDAL_Pos 0 /*!< EMC DYNAMICDAL: tDAL Position */ -#define EMC_DYNAMICDAL_tDAL_Msk (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos) /*!< EMC DYNAMICDAL: tDAL Mask */ - -// -------------------------------------- EMC_DYNAMICWR ----------------------------------------- -#define EMC_DYNAMICWR_tWR_Pos 0 /*!< EMC DYNAMICWR: tWR Position */ -#define EMC_DYNAMICWR_tWR_Msk (0x0fUL << EMC_DYNAMICWR_tWR_Pos) /*!< EMC DYNAMICWR: tWR Mask */ - -// -------------------------------------- EMC_DYNAMICRC ----------------------------------------- -#define EMC_DYNAMICRC_tRC_Pos 0 /*!< EMC DYNAMICRC: tRC Position */ -#define EMC_DYNAMICRC_tRC_Msk (0x1fUL << EMC_DYNAMICRC_tRC_Pos) /*!< EMC DYNAMICRC: tRC Mask */ - -// ------------------------------------- EMC_DYNAMICRFC ----------------------------------------- -#define EMC_DYNAMICRFC_tRFC_Pos 0 /*!< EMC DYNAMICRFC: tRFC Position */ -#define EMC_DYNAMICRFC_tRFC_Msk (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos) /*!< EMC DYNAMICRFC: tRFC Mask */ - -// ------------------------------------- EMC_DYNAMICXSR ----------------------------------------- -#define EMC_DYNAMICXSR_tXSR_Pos 0 /*!< EMC DYNAMICXSR: tXSR Position */ -#define EMC_DYNAMICXSR_tXSR_Msk (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos) /*!< EMC DYNAMICXSR: tXSR Mask */ - -// ------------------------------------- EMC_DYNAMICRRD ----------------------------------------- -#define EMC_DYNAMICRRD_tRRD_Pos 0 /*!< EMC DYNAMICRRD: tRRD Position */ -#define EMC_DYNAMICRRD_tRRD_Msk (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos) /*!< EMC DYNAMICRRD: tRRD Mask */ - -// ------------------------------------- EMC_DYNAMICMRD ----------------------------------------- -#define EMC_DYNAMICMRD_tMRD_Pos 0 /*!< EMC DYNAMICMRD: tMRD Position */ -#define EMC_DYNAMICMRD_tMRD_Msk (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos) /*!< EMC DYNAMICMRD: tMRD Mask */ - -// --------------------------------- EMC_STATICEXTENDEDWAIT ------------------------------------- -#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos 0 /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */ -#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */ - -// ----------------------------------- EMC_DYNAMICCONFIG0 --------------------------------------- -#define EMC_DYNAMICCONFIG0_MD_Pos 3 /*!< EMC DYNAMICCONFIG0: MD Position */ -#define EMC_DYNAMICCONFIG0_MD_Msk (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos) /*!< EMC DYNAMICCONFIG0: MD Mask */ -#define EMC_DYNAMICCONFIG0_AM0_Pos 7 /*!< EMC DYNAMICCONFIG0: AM0 Position */ -#define EMC_DYNAMICCONFIG0_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos) /*!< EMC DYNAMICCONFIG0: AM0 Mask */ -#define EMC_DYNAMICCONFIG0_AM1_Pos 14 /*!< EMC DYNAMICCONFIG0: AM1 Position */ -#define EMC_DYNAMICCONFIG0_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos) /*!< EMC DYNAMICCONFIG0: AM1 Mask */ -#define EMC_DYNAMICCONFIG0_B_Pos 19 /*!< EMC DYNAMICCONFIG0: B Position */ -#define EMC_DYNAMICCONFIG0_B_Msk (0x01UL << EMC_DYNAMICCONFIG0_B_Pos) /*!< EMC DYNAMICCONFIG0: B Mask */ -#define EMC_DYNAMICCONFIG0_P_Pos 20 /*!< EMC DYNAMICCONFIG0: P Position */ -#define EMC_DYNAMICCONFIG0_P_Msk (0x01UL << EMC_DYNAMICCONFIG0_P_Pos) /*!< EMC DYNAMICCONFIG0: P Mask */ - -// ----------------------------------- EMC_DYNAMICRASCAS0 --------------------------------------- -#define EMC_DYNAMICRASCAS0_RAS_Pos 0 /*!< EMC DYNAMICRASCAS0: RAS Position */ -#define EMC_DYNAMICRASCAS0_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos) /*!< EMC DYNAMICRASCAS0: RAS Mask */ -#define EMC_DYNAMICRASCAS0_CAS_Pos 8 /*!< EMC DYNAMICRASCAS0: CAS Position */ -#define EMC_DYNAMICRASCAS0_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos) /*!< EMC DYNAMICRASCAS0: CAS Mask */ - -// ----------------------------------- EMC_DYNAMICCONFIG1 --------------------------------------- -#define EMC_DYNAMICCONFIG1_MD_Pos 3 /*!< EMC DYNAMICCONFIG1: MD Position */ -#define EMC_DYNAMICCONFIG1_MD_Msk (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos) /*!< EMC DYNAMICCONFIG1: MD Mask */ -#define EMC_DYNAMICCONFIG1_AM0_Pos 7 /*!< EMC DYNAMICCONFIG1: AM0 Position */ -#define EMC_DYNAMICCONFIG1_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos) /*!< EMC DYNAMICCONFIG1: AM0 Mask */ -#define EMC_DYNAMICCONFIG1_AM1_Pos 14 /*!< EMC DYNAMICCONFIG1: AM1 Position */ -#define EMC_DYNAMICCONFIG1_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos) /*!< EMC DYNAMICCONFIG1: AM1 Mask */ -#define EMC_DYNAMICCONFIG1_B_Pos 19 /*!< EMC DYNAMICCONFIG1: B Position */ -#define EMC_DYNAMICCONFIG1_B_Msk (0x01UL << EMC_DYNAMICCONFIG1_B_Pos) /*!< EMC DYNAMICCONFIG1: B Mask */ -#define EMC_DYNAMICCONFIG1_P_Pos 20 /*!< EMC DYNAMICCONFIG1: P Position */ -#define EMC_DYNAMICCONFIG1_P_Msk (0x01UL << EMC_DYNAMICCONFIG1_P_Pos) /*!< EMC DYNAMICCONFIG1: P Mask */ - -// ----------------------------------- EMC_DYNAMICRASCAS1 --------------------------------------- -#define EMC_DYNAMICRASCAS1_RAS_Pos 0 /*!< EMC DYNAMICRASCAS1: RAS Position */ -#define EMC_DYNAMICRASCAS1_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos) /*!< EMC DYNAMICRASCAS1: RAS Mask */ -#define EMC_DYNAMICRASCAS1_CAS_Pos 8 /*!< EMC DYNAMICRASCAS1: CAS Position */ -#define EMC_DYNAMICRASCAS1_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos) /*!< EMC DYNAMICRASCAS1: CAS Mask */ - -// ----------------------------------- EMC_DYNAMICCONFIG2 --------------------------------------- -#define EMC_DYNAMICCONFIG2_MD_Pos 3 /*!< EMC DYNAMICCONFIG2: MD Position */ -#define EMC_DYNAMICCONFIG2_MD_Msk (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos) /*!< EMC DYNAMICCONFIG2: MD Mask */ -#define EMC_DYNAMICCONFIG2_AM0_Pos 7 /*!< EMC DYNAMICCONFIG2: AM0 Position */ -#define EMC_DYNAMICCONFIG2_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos) /*!< EMC DYNAMICCONFIG2: AM0 Mask */ -#define EMC_DYNAMICCONFIG2_AM1_Pos 14 /*!< EMC DYNAMICCONFIG2: AM1 Position */ -#define EMC_DYNAMICCONFIG2_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos) /*!< EMC DYNAMICCONFIG2: AM1 Mask */ -#define EMC_DYNAMICCONFIG2_B_Pos 19 /*!< EMC DYNAMICCONFIG2: B Position */ -#define EMC_DYNAMICCONFIG2_B_Msk (0x01UL << EMC_DYNAMICCONFIG2_B_Pos) /*!< EMC DYNAMICCONFIG2: B Mask */ -#define EMC_DYNAMICCONFIG2_P_Pos 20 /*!< EMC DYNAMICCONFIG2: P Position */ -#define EMC_DYNAMICCONFIG2_P_Msk (0x01UL << EMC_DYNAMICCONFIG2_P_Pos) /*!< EMC DYNAMICCONFIG2: P Mask */ - -// ----------------------------------- EMC_DYNAMICRASCAS2 --------------------------------------- -#define EMC_DYNAMICRASCAS2_RAS_Pos 0 /*!< EMC DYNAMICRASCAS2: RAS Position */ -#define EMC_DYNAMICRASCAS2_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos) /*!< EMC DYNAMICRASCAS2: RAS Mask */ -#define EMC_DYNAMICRASCAS2_CAS_Pos 8 /*!< EMC DYNAMICRASCAS2: CAS Position */ -#define EMC_DYNAMICRASCAS2_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos) /*!< EMC DYNAMICRASCAS2: CAS Mask */ - -// ----------------------------------- EMC_DYNAMICCONFIG3 --------------------------------------- -#define EMC_DYNAMICCONFIG3_MD_Pos 3 /*!< EMC DYNAMICCONFIG3: MD Position */ -#define EMC_DYNAMICCONFIG3_MD_Msk (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos) /*!< EMC DYNAMICCONFIG3: MD Mask */ -#define EMC_DYNAMICCONFIG3_AM0_Pos 7 /*!< EMC DYNAMICCONFIG3: AM0 Position */ -#define EMC_DYNAMICCONFIG3_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos) /*!< EMC DYNAMICCONFIG3: AM0 Mask */ -#define EMC_DYNAMICCONFIG3_AM1_Pos 14 /*!< EMC DYNAMICCONFIG3: AM1 Position */ -#define EMC_DYNAMICCONFIG3_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos) /*!< EMC DYNAMICCONFIG3: AM1 Mask */ -#define EMC_DYNAMICCONFIG3_B_Pos 19 /*!< EMC DYNAMICCONFIG3: B Position */ -#define EMC_DYNAMICCONFIG3_B_Msk (0x01UL << EMC_DYNAMICCONFIG3_B_Pos) /*!< EMC DYNAMICCONFIG3: B Mask */ -#define EMC_DYNAMICCONFIG3_P_Pos 20 /*!< EMC DYNAMICCONFIG3: P Position */ -#define EMC_DYNAMICCONFIG3_P_Msk (0x01UL << EMC_DYNAMICCONFIG3_P_Pos) /*!< EMC DYNAMICCONFIG3: P Mask */ - -// ----------------------------------- EMC_DYNAMICRASCAS3 --------------------------------------- -#define EMC_DYNAMICRASCAS3_RAS_Pos 0 /*!< EMC DYNAMICRASCAS3: RAS Position */ -#define EMC_DYNAMICRASCAS3_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos) /*!< EMC DYNAMICRASCAS3: RAS Mask */ -#define EMC_DYNAMICRASCAS3_CAS_Pos 8 /*!< EMC DYNAMICRASCAS3: CAS Position */ -#define EMC_DYNAMICRASCAS3_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos) /*!< EMC DYNAMICRASCAS3: CAS Mask */ - -// ------------------------------------ EMC_STATICCONFIG0 --------------------------------------- -#define EMC_STATICCONFIG0_MW_Pos 0 /*!< EMC STATICCONFIG0: MW Position */ -#define EMC_STATICCONFIG0_MW_Msk (0x03UL << EMC_STATICCONFIG0_MW_Pos) /*!< EMC STATICCONFIG0: MW Mask */ -#define EMC_STATICCONFIG0_PM_Pos 3 /*!< EMC STATICCONFIG0: PM Position */ -#define EMC_STATICCONFIG0_PM_Msk (0x01UL << EMC_STATICCONFIG0_PM_Pos) /*!< EMC STATICCONFIG0: PM Mask */ -#define EMC_STATICCONFIG0_PC_Pos 6 /*!< EMC STATICCONFIG0: PC Position */ -#define EMC_STATICCONFIG0_PC_Msk (0x01UL << EMC_STATICCONFIG0_PC_Pos) /*!< EMC STATICCONFIG0: PC Mask */ -#define EMC_STATICCONFIG0_PB_Pos 7 /*!< EMC STATICCONFIG0: PB Position */ -#define EMC_STATICCONFIG0_PB_Msk (0x01UL << EMC_STATICCONFIG0_PB_Pos) /*!< EMC STATICCONFIG0: PB Mask */ -#define EMC_STATICCONFIG0_EW_Pos 8 /*!< EMC STATICCONFIG0: EW Position */ -#define EMC_STATICCONFIG0_EW_Msk (0x01UL << EMC_STATICCONFIG0_EW_Pos) /*!< EMC STATICCONFIG0: EW Mask */ -#define EMC_STATICCONFIG0_B_Pos 19 /*!< EMC STATICCONFIG0: B Position */ -#define EMC_STATICCONFIG0_B_Msk (0x01UL << EMC_STATICCONFIG0_B_Pos) /*!< EMC STATICCONFIG0: B Mask */ -#define EMC_STATICCONFIG0_P_Pos 20 /*!< EMC STATICCONFIG0: P Position */ -#define EMC_STATICCONFIG0_P_Msk (0x01UL << EMC_STATICCONFIG0_P_Pos) /*!< EMC STATICCONFIG0: P Mask */ - -// ----------------------------------- EMC_STATICWAITWEN0 --------------------------------------- -#define EMC_STATICWAITWEN0_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN0: WAITWEN Position */ -#define EMC_STATICWAITWEN0_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos) /*!< EMC STATICWAITWEN0: WAITWEN Mask */ - -// ----------------------------------- EMC_STATICWAITOEN0 --------------------------------------- -#define EMC_STATICWAITOEN0_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN0: WAITOEN Position */ -#define EMC_STATICWAITOEN0_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos) /*!< EMC STATICWAITOEN0: WAITOEN Mask */ - -// ------------------------------------ EMC_STATICWAITRD0 --------------------------------------- -#define EMC_STATICWAITRD0_WAITRD_Pos 0 /*!< EMC STATICWAITRD0: WAITRD Position */ -#define EMC_STATICWAITRD0_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos) /*!< EMC STATICWAITRD0: WAITRD Mask */ - -// ----------------------------------- EMC_STATICWAITPAG0 --------------------------------------- -#define EMC_STATICWAITPAG0_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG0: WAITPAGE Position */ -#define EMC_STATICWAITPAG0_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos) /*!< EMC STATICWAITPAG0: WAITPAGE Mask */ - -// ------------------------------------ EMC_STATICWAITWR0 --------------------------------------- -#define EMC_STATICWAITWR0_WAITWR_Pos 0 /*!< EMC STATICWAITWR0: WAITWR Position */ -#define EMC_STATICWAITWR0_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos) /*!< EMC STATICWAITWR0: WAITWR Mask */ - -// ----------------------------------- EMC_STATICWAITTURN0 -------------------------------------- -#define EMC_STATICWAITTURN0_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN0: WAITTURN Position */ -#define EMC_STATICWAITTURN0_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos) /*!< EMC STATICWAITTURN0: WAITTURN Mask */ - -// ------------------------------------ EMC_STATICCONFIG1 --------------------------------------- -#define EMC_STATICCONFIG1_MW_Pos 0 /*!< EMC STATICCONFIG1: MW Position */ -#define EMC_STATICCONFIG1_MW_Msk (0x03UL << EMC_STATICCONFIG1_MW_Pos) /*!< EMC STATICCONFIG1: MW Mask */ -#define EMC_STATICCONFIG1_PM_Pos 3 /*!< EMC STATICCONFIG1: PM Position */ -#define EMC_STATICCONFIG1_PM_Msk (0x01UL << EMC_STATICCONFIG1_PM_Pos) /*!< EMC STATICCONFIG1: PM Mask */ -#define EMC_STATICCONFIG1_PC_Pos 6 /*!< EMC STATICCONFIG1: PC Position */ -#define EMC_STATICCONFIG1_PC_Msk (0x01UL << EMC_STATICCONFIG1_PC_Pos) /*!< EMC STATICCONFIG1: PC Mask */ -#define EMC_STATICCONFIG1_PB_Pos 7 /*!< EMC STATICCONFIG1: PB Position */ -#define EMC_STATICCONFIG1_PB_Msk (0x01UL << EMC_STATICCONFIG1_PB_Pos) /*!< EMC STATICCONFIG1: PB Mask */ -#define EMC_STATICCONFIG1_EW_Pos 8 /*!< EMC STATICCONFIG1: EW Position */ -#define EMC_STATICCONFIG1_EW_Msk (0x01UL << EMC_STATICCONFIG1_EW_Pos) /*!< EMC STATICCONFIG1: EW Mask */ -#define EMC_STATICCONFIG1_B_Pos 19 /*!< EMC STATICCONFIG1: B Position */ -#define EMC_STATICCONFIG1_B_Msk (0x01UL << EMC_STATICCONFIG1_B_Pos) /*!< EMC STATICCONFIG1: B Mask */ -#define EMC_STATICCONFIG1_P_Pos 20 /*!< EMC STATICCONFIG1: P Position */ -#define EMC_STATICCONFIG1_P_Msk (0x01UL << EMC_STATICCONFIG1_P_Pos) /*!< EMC STATICCONFIG1: P Mask */ - -// ----------------------------------- EMC_STATICWAITWEN1 --------------------------------------- -#define EMC_STATICWAITWEN1_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN1: WAITWEN Position */ -#define EMC_STATICWAITWEN1_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos) /*!< EMC STATICWAITWEN1: WAITWEN Mask */ - -// ----------------------------------- EMC_STATICWAITOEN1 --------------------------------------- -#define EMC_STATICWAITOEN1_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN1: WAITOEN Position */ -#define EMC_STATICWAITOEN1_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos) /*!< EMC STATICWAITOEN1: WAITOEN Mask */ - -// ------------------------------------ EMC_STATICWAITRD1 --------------------------------------- -#define EMC_STATICWAITRD1_WAITRD_Pos 0 /*!< EMC STATICWAITRD1: WAITRD Position */ -#define EMC_STATICWAITRD1_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos) /*!< EMC STATICWAITRD1: WAITRD Mask */ - -// ----------------------------------- EMC_STATICWAITPAG1 --------------------------------------- -#define EMC_STATICWAITPAG1_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG1: WAITPAGE Position */ -#define EMC_STATICWAITPAG1_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos) /*!< EMC STATICWAITPAG1: WAITPAGE Mask */ - -// ------------------------------------ EMC_STATICWAITWR1 --------------------------------------- -#define EMC_STATICWAITWR1_WAITWR_Pos 0 /*!< EMC STATICWAITWR1: WAITWR Position */ -#define EMC_STATICWAITWR1_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos) /*!< EMC STATICWAITWR1: WAITWR Mask */ - -// ----------------------------------- EMC_STATICWAITTURN1 -------------------------------------- -#define EMC_STATICWAITTURN1_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN1: WAITTURN Position */ -#define EMC_STATICWAITTURN1_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos) /*!< EMC STATICWAITTURN1: WAITTURN Mask */ - -// ------------------------------------ EMC_STATICCONFIG2 --------------------------------------- -#define EMC_STATICCONFIG2_MW_Pos 0 /*!< EMC STATICCONFIG2: MW Position */ -#define EMC_STATICCONFIG2_MW_Msk (0x03UL << EMC_STATICCONFIG2_MW_Pos) /*!< EMC STATICCONFIG2: MW Mask */ -#define EMC_STATICCONFIG2_PM_Pos 3 /*!< EMC STATICCONFIG2: PM Position */ -#define EMC_STATICCONFIG2_PM_Msk (0x01UL << EMC_STATICCONFIG2_PM_Pos) /*!< EMC STATICCONFIG2: PM Mask */ -#define EMC_STATICCONFIG2_PC_Pos 6 /*!< EMC STATICCONFIG2: PC Position */ -#define EMC_STATICCONFIG2_PC_Msk (0x01UL << EMC_STATICCONFIG2_PC_Pos) /*!< EMC STATICCONFIG2: PC Mask */ -#define EMC_STATICCONFIG2_PB_Pos 7 /*!< EMC STATICCONFIG2: PB Position */ -#define EMC_STATICCONFIG2_PB_Msk (0x01UL << EMC_STATICCONFIG2_PB_Pos) /*!< EMC STATICCONFIG2: PB Mask */ -#define EMC_STATICCONFIG2_EW_Pos 8 /*!< EMC STATICCONFIG2: EW Position */ -#define EMC_STATICCONFIG2_EW_Msk (0x01UL << EMC_STATICCONFIG2_EW_Pos) /*!< EMC STATICCONFIG2: EW Mask */ -#define EMC_STATICCONFIG2_B_Pos 19 /*!< EMC STATICCONFIG2: B Position */ -#define EMC_STATICCONFIG2_B_Msk (0x01UL << EMC_STATICCONFIG2_B_Pos) /*!< EMC STATICCONFIG2: B Mask */ -#define EMC_STATICCONFIG2_P_Pos 20 /*!< EMC STATICCONFIG2: P Position */ -#define EMC_STATICCONFIG2_P_Msk (0x01UL << EMC_STATICCONFIG2_P_Pos) /*!< EMC STATICCONFIG2: P Mask */ - -// ----------------------------------- EMC_STATICWAITWEN2 --------------------------------------- -#define EMC_STATICWAITWEN2_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN2: WAITWEN Position */ -#define EMC_STATICWAITWEN2_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos) /*!< EMC STATICWAITWEN2: WAITWEN Mask */ - -// ----------------------------------- EMC_STATICWAITOEN2 --------------------------------------- -#define EMC_STATICWAITOEN2_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN2: WAITOEN Position */ -#define EMC_STATICWAITOEN2_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos) /*!< EMC STATICWAITOEN2: WAITOEN Mask */ - -// ------------------------------------ EMC_STATICWAITRD2 --------------------------------------- -#define EMC_STATICWAITRD2_WAITRD_Pos 0 /*!< EMC STATICWAITRD2: WAITRD Position */ -#define EMC_STATICWAITRD2_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos) /*!< EMC STATICWAITRD2: WAITRD Mask */ - -// ----------------------------------- EMC_STATICWAITPAG2 --------------------------------------- -#define EMC_STATICWAITPAG2_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG2: WAITPAGE Position */ -#define EMC_STATICWAITPAG2_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos) /*!< EMC STATICWAITPAG2: WAITPAGE Mask */ - -// ------------------------------------ EMC_STATICWAITWR2 --------------------------------------- -#define EMC_STATICWAITWR2_WAITWR_Pos 0 /*!< EMC STATICWAITWR2: WAITWR Position */ -#define EMC_STATICWAITWR2_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos) /*!< EMC STATICWAITWR2: WAITWR Mask */ - -// ----------------------------------- EMC_STATICWAITTURN2 -------------------------------------- -#define EMC_STATICWAITTURN2_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN2: WAITTURN Position */ -#define EMC_STATICWAITTURN2_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos) /*!< EMC STATICWAITTURN2: WAITTURN Mask */ - -// ------------------------------------ EMC_STATICCONFIG3 --------------------------------------- -#define EMC_STATICCONFIG3_MW_Pos 0 /*!< EMC STATICCONFIG3: MW Position */ -#define EMC_STATICCONFIG3_MW_Msk (0x03UL << EMC_STATICCONFIG3_MW_Pos) /*!< EMC STATICCONFIG3: MW Mask */ -#define EMC_STATICCONFIG3_PM_Pos 3 /*!< EMC STATICCONFIG3: PM Position */ -#define EMC_STATICCONFIG3_PM_Msk (0x01UL << EMC_STATICCONFIG3_PM_Pos) /*!< EMC STATICCONFIG3: PM Mask */ -#define EMC_STATICCONFIG3_PC_Pos 6 /*!< EMC STATICCONFIG3: PC Position */ -#define EMC_STATICCONFIG3_PC_Msk (0x01UL << EMC_STATICCONFIG3_PC_Pos) /*!< EMC STATICCONFIG3: PC Mask */ -#define EMC_STATICCONFIG3_PB_Pos 7 /*!< EMC STATICCONFIG3: PB Position */ -#define EMC_STATICCONFIG3_PB_Msk (0x01UL << EMC_STATICCONFIG3_PB_Pos) /*!< EMC STATICCONFIG3: PB Mask */ -#define EMC_STATICCONFIG3_EW_Pos 8 /*!< EMC STATICCONFIG3: EW Position */ -#define EMC_STATICCONFIG3_EW_Msk (0x01UL << EMC_STATICCONFIG3_EW_Pos) /*!< EMC STATICCONFIG3: EW Mask */ -#define EMC_STATICCONFIG3_B_Pos 19 /*!< EMC STATICCONFIG3: B Position */ -#define EMC_STATICCONFIG3_B_Msk (0x01UL << EMC_STATICCONFIG3_B_Pos) /*!< EMC STATICCONFIG3: B Mask */ -#define EMC_STATICCONFIG3_P_Pos 20 /*!< EMC STATICCONFIG3: P Position */ -#define EMC_STATICCONFIG3_P_Msk (0x01UL << EMC_STATICCONFIG3_P_Pos) /*!< EMC STATICCONFIG3: P Mask */ - -// ----------------------------------- EMC_STATICWAITWEN3 --------------------------------------- -#define EMC_STATICWAITWEN3_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN3: WAITWEN Position */ -#define EMC_STATICWAITWEN3_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos) /*!< EMC STATICWAITWEN3: WAITWEN Mask */ - -// ----------------------------------- EMC_STATICWAITOEN3 --------------------------------------- -#define EMC_STATICWAITOEN3_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN3: WAITOEN Position */ -#define EMC_STATICWAITOEN3_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos) /*!< EMC STATICWAITOEN3: WAITOEN Mask */ - -// ------------------------------------ EMC_STATICWAITRD3 --------------------------------------- -#define EMC_STATICWAITRD3_WAITRD_Pos 0 /*!< EMC STATICWAITRD3: WAITRD Position */ -#define EMC_STATICWAITRD3_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos) /*!< EMC STATICWAITRD3: WAITRD Mask */ - -// ----------------------------------- EMC_STATICWAITPAG3 --------------------------------------- -#define EMC_STATICWAITPAG3_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG3: WAITPAGE Position */ -#define EMC_STATICWAITPAG3_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos) /*!< EMC STATICWAITPAG3: WAITPAGE Mask */ - -// ------------------------------------ EMC_STATICWAITWR3 --------------------------------------- -#define EMC_STATICWAITWR3_WAITWR_Pos 0 /*!< EMC STATICWAITWR3: WAITWR Position */ -#define EMC_STATICWAITWR3_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos) /*!< EMC STATICWAITWR3: WAITWR Mask */ - -// ----------------------------------- EMC_STATICWAITTURN3 -------------------------------------- -#define EMC_STATICWAITTURN3_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN3: WAITTURN Position */ -#define EMC_STATICWAITTURN3_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos) /*!< EMC STATICWAITTURN3: WAITTURN Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USB0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- USB0_CAPLENGTH ----------------------------------------- -#define USB0_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB0 CAPLENGTH: CAPLENGTH Position */ -#define USB0_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos) /*!< USB0 CAPLENGTH: CAPLENGTH Mask */ -#define USB0_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB0 CAPLENGTH: HCIVERSION Position */ -#define USB0_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos) /*!< USB0 CAPLENGTH: HCIVERSION Mask */ - -// ------------------------------------- USB0_HCSPARAMS ----------------------------------------- -#define USB0_HCSPARAMS_N_PORTS_Pos 0 /*!< USB0 HCSPARAMS: N_PORTS Position */ -#define USB0_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos) /*!< USB0 HCSPARAMS: N_PORTS Mask */ -#define USB0_HCSPARAMS_PPC_Pos 4 /*!< USB0 HCSPARAMS: PPC Position */ -#define USB0_HCSPARAMS_PPC_Msk (0x01UL << USB0_HCSPARAMS_PPC_Pos) /*!< USB0 HCSPARAMS: PPC Mask */ -#define USB0_HCSPARAMS_N_PCC_Pos 8 /*!< USB0 HCSPARAMS: N_PCC Position */ -#define USB0_HCSPARAMS_N_PCC_Msk (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos) /*!< USB0 HCSPARAMS: N_PCC Mask */ -#define USB0_HCSPARAMS_N_CC_Pos 12 /*!< USB0 HCSPARAMS: N_CC Position */ -#define USB0_HCSPARAMS_N_CC_Msk (0x0fUL << USB0_HCSPARAMS_N_CC_Pos) /*!< USB0 HCSPARAMS: N_CC Mask */ -#define USB0_HCSPARAMS_PI_Pos 16 /*!< USB0 HCSPARAMS: PI Position */ -#define USB0_HCSPARAMS_PI_Msk (0x01UL << USB0_HCSPARAMS_PI_Pos) /*!< USB0 HCSPARAMS: PI Mask */ -#define USB0_HCSPARAMS_N_PTT_Pos 20 /*!< USB0 HCSPARAMS: N_PTT Position */ -#define USB0_HCSPARAMS_N_PTT_Msk (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos) /*!< USB0 HCSPARAMS: N_PTT Mask */ -#define USB0_HCSPARAMS_N_TT_Pos 24 /*!< USB0 HCSPARAMS: N_TT Position */ -#define USB0_HCSPARAMS_N_TT_Msk (0x0fUL << USB0_HCSPARAMS_N_TT_Pos) /*!< USB0 HCSPARAMS: N_TT Mask */ - -// ------------------------------------- USB0_HCCPARAMS ----------------------------------------- -#define USB0_HCCPARAMS_ADC_Pos 0 /*!< USB0 HCCPARAMS: ADC Position */ -#define USB0_HCCPARAMS_ADC_Msk (0x01UL << USB0_HCCPARAMS_ADC_Pos) /*!< USB0 HCCPARAMS: ADC Mask */ -#define USB0_HCCPARAMS_PFL_Pos 1 /*!< USB0 HCCPARAMS: PFL Position */ -#define USB0_HCCPARAMS_PFL_Msk (0x01UL << USB0_HCCPARAMS_PFL_Pos) /*!< USB0 HCCPARAMS: PFL Mask */ -#define USB0_HCCPARAMS_ASP_Pos 2 /*!< USB0 HCCPARAMS: ASP Position */ -#define USB0_HCCPARAMS_ASP_Msk (0x01UL << USB0_HCCPARAMS_ASP_Pos) /*!< USB0 HCCPARAMS: ASP Mask */ -#define USB0_HCCPARAMS_IST_Pos 4 /*!< USB0 HCCPARAMS: IST Position */ -#define USB0_HCCPARAMS_IST_Msk (0x0fUL << USB0_HCCPARAMS_IST_Pos) /*!< USB0 HCCPARAMS: IST Mask */ -#define USB0_HCCPARAMS_EECP_Pos 8 /*!< USB0 HCCPARAMS: EECP Position */ -#define USB0_HCCPARAMS_EECP_Msk (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos) /*!< USB0 HCCPARAMS: EECP Mask */ - -// ------------------------------------- USB0_DCIVERSION ---------------------------------------- -#define USB0_DCIVERSION_DCIVERSION_Pos 0 /*!< USB0 DCIVERSION: DCIVERSION Position */ -#define USB0_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos) /*!< USB0 DCIVERSION: DCIVERSION Mask */ - -// -------------------------------------- USB0_USBCMD_D ----------------------------------------- -#define USB0_USBCMD_D_RS_Pos 0 /*!< USB0 USBCMD_D: RS Position */ -#define USB0_USBCMD_D_RS_Msk (0x01UL << USB0_USBCMD_D_RS_Pos) /*!< USB0 USBCMD_D: RS Mask */ -#define USB0_USBCMD_D_RST_Pos 1 /*!< USB0 USBCMD_D: RST Position */ -#define USB0_USBCMD_D_RST_Msk (0x01UL << USB0_USBCMD_D_RST_Pos) /*!< USB0 USBCMD_D: RST Mask */ -#define USB0_USBCMD_D_SUTW_Pos 13 /*!< USB0 USBCMD_D: SUTW Position */ -#define USB0_USBCMD_D_SUTW_Msk (0x01UL << USB0_USBCMD_D_SUTW_Pos) /*!< USB0 USBCMD_D: SUTW Mask */ -#define USB0_USBCMD_D_ATDTW_Pos 14 /*!< USB0 USBCMD_D: ATDTW Position */ -#define USB0_USBCMD_D_ATDTW_Msk (0x01UL << USB0_USBCMD_D_ATDTW_Pos) /*!< USB0 USBCMD_D: ATDTW Mask */ -#define USB0_USBCMD_D_ITC_Pos 16 /*!< USB0 USBCMD_D: ITC Position */ -#define USB0_USBCMD_D_ITC_Msk (0x000000ffUL << USB0_USBCMD_D_ITC_Pos) /*!< USB0 USBCMD_D: ITC Mask */ - -// -------------------------------------- USB0_USBCMD_H ----------------------------------------- -#define USB0_USBCMD_H_RS_Pos 0 /*!< USB0 USBCMD_H: RS Position */ -#define USB0_USBCMD_H_RS_Msk (0x01UL << USB0_USBCMD_H_RS_Pos) /*!< USB0 USBCMD_H: RS Mask */ -#define USB0_USBCMD_H_RST_Pos 1 /*!< USB0 USBCMD_H: RST Position */ -#define USB0_USBCMD_H_RST_Msk (0x01UL << USB0_USBCMD_H_RST_Pos) /*!< USB0 USBCMD_H: RST Mask */ -#define USB0_USBCMD_H_FS0_Pos 2 /*!< USB0 USBCMD_H: FS0 Position */ -#define USB0_USBCMD_H_FS0_Msk (0x01UL << USB0_USBCMD_H_FS0_Pos) /*!< USB0 USBCMD_H: FS0 Mask */ -#define USB0_USBCMD_H_FS1_Pos 3 /*!< USB0 USBCMD_H: FS1 Position */ -#define USB0_USBCMD_H_FS1_Msk (0x01UL << USB0_USBCMD_H_FS1_Pos) /*!< USB0 USBCMD_H: FS1 Mask */ -#define USB0_USBCMD_H_PSE_Pos 4 /*!< USB0 USBCMD_H: PSE Position */ -#define USB0_USBCMD_H_PSE_Msk (0x01UL << USB0_USBCMD_H_PSE_Pos) /*!< USB0 USBCMD_H: PSE Mask */ -#define USB0_USBCMD_H_ASE_Pos 5 /*!< USB0 USBCMD_H: ASE Position */ -#define USB0_USBCMD_H_ASE_Msk (0x01UL << USB0_USBCMD_H_ASE_Pos) /*!< USB0 USBCMD_H: ASE Mask */ -#define USB0_USBCMD_H_IAA_Pos 6 /*!< USB0 USBCMD_H: IAA Position */ -#define USB0_USBCMD_H_IAA_Msk (0x01UL << USB0_USBCMD_H_IAA_Pos) /*!< USB0 USBCMD_H: IAA Mask */ -#define USB0_USBCMD_H_ASP1_0_Pos 8 /*!< USB0 USBCMD_H: ASP1_0 Position */ -#define USB0_USBCMD_H_ASP1_0_Msk (0x03UL << USB0_USBCMD_H_ASP1_0_Pos) /*!< USB0 USBCMD_H: ASP1_0 Mask */ -#define USB0_USBCMD_H_ASPE_Pos 11 /*!< USB0 USBCMD_H: ASPE Position */ -#define USB0_USBCMD_H_ASPE_Msk (0x01UL << USB0_USBCMD_H_ASPE_Pos) /*!< USB0 USBCMD_H: ASPE Mask */ -#define USB0_USBCMD_H_FS2_Pos 15 /*!< USB0 USBCMD_H: FS2 Position */ -#define USB0_USBCMD_H_FS2_Msk (0x01UL << USB0_USBCMD_H_FS2_Pos) /*!< USB0 USBCMD_H: FS2 Mask */ -#define USB0_USBCMD_H_ITC_Pos 16 /*!< USB0 USBCMD_H: ITC Position */ -#define USB0_USBCMD_H_ITC_Msk (0x000000ffUL << USB0_USBCMD_H_ITC_Pos) /*!< USB0 USBCMD_H: ITC Mask */ - -// -------------------------------------- USB0_USBSTS_D ----------------------------------------- -#define USB0_USBSTS_D_UI_Pos 0 /*!< USB0 USBSTS_D: UI Position */ -#define USB0_USBSTS_D_UI_Msk (0x01UL << USB0_USBSTS_D_UI_Pos) /*!< USB0 USBSTS_D: UI Mask */ -#define USB0_USBSTS_D_UEI_Pos 1 /*!< USB0 USBSTS_D: UEI Position */ -#define USB0_USBSTS_D_UEI_Msk (0x01UL << USB0_USBSTS_D_UEI_Pos) /*!< USB0 USBSTS_D: UEI Mask */ -#define USB0_USBSTS_D_PCI_Pos 2 /*!< USB0 USBSTS_D: PCI Position */ -#define USB0_USBSTS_D_PCI_Msk (0x01UL << USB0_USBSTS_D_PCI_Pos) /*!< USB0 USBSTS_D: PCI Mask */ -#define USB0_USBSTS_D_AAI_Pos 5 /*!< USB0 USBSTS_D: AAI Position */ -#define USB0_USBSTS_D_AAI_Msk (0x01UL << USB0_USBSTS_D_AAI_Pos) /*!< USB0 USBSTS_D: AAI Mask */ -#define USB0_USBSTS_D_URI_Pos 6 /*!< USB0 USBSTS_D: URI Position */ -#define USB0_USBSTS_D_URI_Msk (0x01UL << USB0_USBSTS_D_URI_Pos) /*!< USB0 USBSTS_D: URI Mask */ -#define USB0_USBSTS_D_SRI_Pos 7 /*!< USB0 USBSTS_D: SRI Position */ -#define USB0_USBSTS_D_SRI_Msk (0x01UL << USB0_USBSTS_D_SRI_Pos) /*!< USB0 USBSTS_D: SRI Mask */ -#define USB0_USBSTS_D_SLI_Pos 8 /*!< USB0 USBSTS_D: SLI Position */ -#define USB0_USBSTS_D_SLI_Msk (0x01UL << USB0_USBSTS_D_SLI_Pos) /*!< USB0 USBSTS_D: SLI Mask */ -#define USB0_USBSTS_D_NAKI_Pos 16 /*!< USB0 USBSTS_D: NAKI Position */ -#define USB0_USBSTS_D_NAKI_Msk (0x01UL << USB0_USBSTS_D_NAKI_Pos) /*!< USB0 USBSTS_D: NAKI Mask */ - -// -------------------------------------- USB0_USBSTS_H ----------------------------------------- -#define USB0_USBSTS_H_UI_Pos 0 /*!< USB0 USBSTS_H: UI Position */ -#define USB0_USBSTS_H_UI_Msk (0x01UL << USB0_USBSTS_H_UI_Pos) /*!< USB0 USBSTS_H: UI Mask */ -#define USB0_USBSTS_H_UEI_Pos 1 /*!< USB0 USBSTS_H: UEI Position */ -#define USB0_USBSTS_H_UEI_Msk (0x01UL << USB0_USBSTS_H_UEI_Pos) /*!< USB0 USBSTS_H: UEI Mask */ -#define USB0_USBSTS_H_PCI_Pos 2 /*!< USB0 USBSTS_H: PCI Position */ -#define USB0_USBSTS_H_PCI_Msk (0x01UL << USB0_USBSTS_H_PCI_Pos) /*!< USB0 USBSTS_H: PCI Mask */ -#define USB0_USBSTS_H_FRI_Pos 3 /*!< USB0 USBSTS_H: FRI Position */ -#define USB0_USBSTS_H_FRI_Msk (0x01UL << USB0_USBSTS_H_FRI_Pos) /*!< USB0 USBSTS_H: FRI Mask */ -#define USB0_USBSTS_H_AAI_Pos 5 /*!< USB0 USBSTS_H: AAI Position */ -#define USB0_USBSTS_H_AAI_Msk (0x01UL << USB0_USBSTS_H_AAI_Pos) /*!< USB0 USBSTS_H: AAI Mask */ -#define USB0_USBSTS_H_SRI_Pos 7 /*!< USB0 USBSTS_H: SRI Position */ -#define USB0_USBSTS_H_SRI_Msk (0x01UL << USB0_USBSTS_H_SRI_Pos) /*!< USB0 USBSTS_H: SRI Mask */ -#define USB0_USBSTS_H_HCH_Pos 12 /*!< USB0 USBSTS_H: HCH Position */ -#define USB0_USBSTS_H_HCH_Msk (0x01UL << USB0_USBSTS_H_HCH_Pos) /*!< USB0 USBSTS_H: HCH Mask */ -#define USB0_USBSTS_H_RCL_Pos 13 /*!< USB0 USBSTS_H: RCL Position */ -#define USB0_USBSTS_H_RCL_Msk (0x01UL << USB0_USBSTS_H_RCL_Pos) /*!< USB0 USBSTS_H: RCL Mask */ -#define USB0_USBSTS_H_PS_Pos 14 /*!< USB0 USBSTS_H: PS Position */ -#define USB0_USBSTS_H_PS_Msk (0x01UL << USB0_USBSTS_H_PS_Pos) /*!< USB0 USBSTS_H: PS Mask */ -#define USB0_USBSTS_H_AS_Pos 15 /*!< USB0 USBSTS_H: AS Position */ -#define USB0_USBSTS_H_AS_Msk (0x01UL << USB0_USBSTS_H_AS_Pos) /*!< USB0 USBSTS_H: AS Mask */ -#define USB0_USBSTS_H_UAI_Pos 18 /*!< USB0 USBSTS_H: UAI Position */ -#define USB0_USBSTS_H_UAI_Msk (0x01UL << USB0_USBSTS_H_UAI_Pos) /*!< USB0 USBSTS_H: UAI Mask */ -#define USB0_USBSTS_H_UPI_Pos 19 /*!< USB0 USBSTS_H: UPI Position */ -#define USB0_USBSTS_H_UPI_Msk (0x01UL << USB0_USBSTS_H_UPI_Pos) /*!< USB0 USBSTS_H: UPI Mask */ - -// ------------------------------------- USB0_USBINTR_D ----------------------------------------- -#define USB0_USBINTR_D_UE_Pos 0 /*!< USB0 USBINTR_D: UE Position */ -#define USB0_USBINTR_D_UE_Msk (0x01UL << USB0_USBINTR_D_UE_Pos) /*!< USB0 USBINTR_D: UE Mask */ -#define USB0_USBINTR_D_UEE_Pos 1 /*!< USB0 USBINTR_D: UEE Position */ -#define USB0_USBINTR_D_UEE_Msk (0x01UL << USB0_USBINTR_D_UEE_Pos) /*!< USB0 USBINTR_D: UEE Mask */ -#define USB0_USBINTR_D_PCE_Pos 2 /*!< USB0 USBINTR_D: PCE Position */ -#define USB0_USBINTR_D_PCE_Msk (0x01UL << USB0_USBINTR_D_PCE_Pos) /*!< USB0 USBINTR_D: PCE Mask */ -#define USB0_USBINTR_D_URE_Pos 6 /*!< USB0 USBINTR_D: URE Position */ -#define USB0_USBINTR_D_URE_Msk (0x01UL << USB0_USBINTR_D_URE_Pos) /*!< USB0 USBINTR_D: URE Mask */ -#define USB0_USBINTR_D_SRE_Pos 7 /*!< USB0 USBINTR_D: SRE Position */ -#define USB0_USBINTR_D_SRE_Msk (0x01UL << USB0_USBINTR_D_SRE_Pos) /*!< USB0 USBINTR_D: SRE Mask */ -#define USB0_USBINTR_D_SLE_Pos 8 /*!< USB0 USBINTR_D: SLE Position */ -#define USB0_USBINTR_D_SLE_Msk (0x01UL << USB0_USBINTR_D_SLE_Pos) /*!< USB0 USBINTR_D: SLE Mask */ -#define USB0_USBINTR_D_NAKE_Pos 16 /*!< USB0 USBINTR_D: NAKE Position */ -#define USB0_USBINTR_D_NAKE_Msk (0x01UL << USB0_USBINTR_D_NAKE_Pos) /*!< USB0 USBINTR_D: NAKE Mask */ - -// ------------------------------------- USB0_USBINTR_H ----------------------------------------- -#define USB0_USBINTR_H_UE_Pos 0 /*!< USB0 USBINTR_H: UE Position */ -#define USB0_USBINTR_H_UE_Msk (0x01UL << USB0_USBINTR_H_UE_Pos) /*!< USB0 USBINTR_H: UE Mask */ -#define USB0_USBINTR_H_UEE_Pos 1 /*!< USB0 USBINTR_H: UEE Position */ -#define USB0_USBINTR_H_UEE_Msk (0x01UL << USB0_USBINTR_H_UEE_Pos) /*!< USB0 USBINTR_H: UEE Mask */ -#define USB0_USBINTR_H_PCE_Pos 2 /*!< USB0 USBINTR_H: PCE Position */ -#define USB0_USBINTR_H_PCE_Msk (0x01UL << USB0_USBINTR_H_PCE_Pos) /*!< USB0 USBINTR_H: PCE Mask */ -#define USB0_USBINTR_H_FRE_Pos 3 /*!< USB0 USBINTR_H: FRE Position */ -#define USB0_USBINTR_H_FRE_Msk (0x01UL << USB0_USBINTR_H_FRE_Pos) /*!< USB0 USBINTR_H: FRE Mask */ -#define USB0_USBINTR_H_AAE_Pos 5 /*!< USB0 USBINTR_H: AAE Position */ -#define USB0_USBINTR_H_AAE_Msk (0x01UL << USB0_USBINTR_H_AAE_Pos) /*!< USB0 USBINTR_H: AAE Mask */ -#define USB0_USBINTR_H_SRE_Pos 7 /*!< USB0 USBINTR_H: SRE Position */ -#define USB0_USBINTR_H_SRE_Msk (0x01UL << USB0_USBINTR_H_SRE_Pos) /*!< USB0 USBINTR_H: SRE Mask */ -#define USB0_USBINTR_H_UAIE_Pos 18 /*!< USB0 USBINTR_H: UAIE Position */ -#define USB0_USBINTR_H_UAIE_Msk (0x01UL << USB0_USBINTR_H_UAIE_Pos) /*!< USB0 USBINTR_H: UAIE Mask */ -#define USB0_USBINTR_H_UPIA_Pos 19 /*!< USB0 USBINTR_H: UPIA Position */ -#define USB0_USBINTR_H_UPIA_Msk (0x01UL << USB0_USBINTR_H_UPIA_Pos) /*!< USB0 USBINTR_H: UPIA Mask */ - -// ------------------------------------- USB0_FRINDEX_D ----------------------------------------- -#define USB0_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */ -#define USB0_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask */ -#define USB0_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */ -#define USB0_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask */ - -// ------------------------------------- USB0_FRINDEX_H ----------------------------------------- -#define USB0_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */ -#define USB0_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask */ -#define USB0_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */ -#define USB0_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask */ - -// ------------------------------------- USB0_DEVICEADDR ---------------------------------------- -#define USB0_DEVICEADDR_USBADRA_Pos 24 /*!< USB0 DEVICEADDR: USBADRA Position */ -#define USB0_DEVICEADDR_USBADRA_Msk (0x01UL << USB0_DEVICEADDR_USBADRA_Pos) /*!< USB0 DEVICEADDR: USBADRA Mask */ -#define USB0_DEVICEADDR_USBADR_Pos 25 /*!< USB0 DEVICEADDR: USBADR Position */ -#define USB0_DEVICEADDR_USBADR_Msk (0x7fUL << USB0_DEVICEADDR_USBADR_Pos) /*!< USB0 DEVICEADDR: USBADR Mask */ - -// ---------------------------------- USB0_PERIODICLISTBASE ------------------------------------- -#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */ -#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */ - -// ---------------------------------- USB0_ENDPOINTLISTADDR ------------------------------------- -#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */ -#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */ - -// ----------------------------------- USB0_ASYNCLISTADDR --------------------------------------- -#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */ -#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */ - -// --------------------------------------- USB0_TTCTRL ------------------------------------------ -#define USB0_TTCTRL_TTHA_Pos 24 /*!< USB0 TTCTRL: TTHA Position */ -#define USB0_TTCTRL_TTHA_Msk (0x7fUL << USB0_TTCTRL_TTHA_Pos) /*!< USB0 TTCTRL: TTHA Mask */ - -// ------------------------------------- USB0_BURSTSIZE ----------------------------------------- -#define USB0_BURSTSIZE_RXPBURST_Pos 0 /*!< USB0 BURSTSIZE: RXPBURST Position */ -#define USB0_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos) /*!< USB0 BURSTSIZE: RXPBURST Mask */ -#define USB0_BURSTSIZE_TXPBURST_Pos 8 /*!< USB0 BURSTSIZE: TXPBURST Position */ -#define USB0_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos) /*!< USB0 BURSTSIZE: TXPBURST Mask */ - -// ------------------------------------ USB0_TXFILLTUNING --------------------------------------- -#define USB0_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB0 TXFILLTUNING: TXSCHOH Position */ -#define USB0_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos) /*!< USB0 TXFILLTUNING: TXSCHOH Mask */ -#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */ -#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */ -#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */ -#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */ - -// ------------------------------------- USB0_BINTERVAL ----------------------------------------- -#define USB0_BINTERVAL_BINT_Pos 0 /*!< USB0 BINTERVAL: BINT Position */ -#define USB0_BINTERVAL_BINT_Msk (0x0fUL << USB0_BINTERVAL_BINT_Pos) /*!< USB0 BINTERVAL: BINT Mask */ - -// -------------------------------------- USB0_ENDPTNAK ----------------------------------------- -#define USB0_ENDPTNAK_EPRN0_Pos 0 /*!< USB0 ENDPTNAK: EPRN0 Position */ -#define USB0_ENDPTNAK_EPRN0_Msk (0x01UL << USB0_ENDPTNAK_EPRN0_Pos) /*!< USB0 ENDPTNAK: EPRN0 Mask */ -#define USB0_ENDPTNAK_EPRN1_Pos 1 /*!< USB0 ENDPTNAK: EPRN1 Position */ -#define USB0_ENDPTNAK_EPRN1_Msk (0x01UL << USB0_ENDPTNAK_EPRN1_Pos) /*!< USB0 ENDPTNAK: EPRN1 Mask */ -#define USB0_ENDPTNAK_EPRN2_Pos 2 /*!< USB0 ENDPTNAK: EPRN2 Position */ -#define USB0_ENDPTNAK_EPRN2_Msk (0x01UL << USB0_ENDPTNAK_EPRN2_Pos) /*!< USB0 ENDPTNAK: EPRN2 Mask */ -#define USB0_ENDPTNAK_EPRN3_Pos 3 /*!< USB0 ENDPTNAK: EPRN3 Position */ -#define USB0_ENDPTNAK_EPRN3_Msk (0x01UL << USB0_ENDPTNAK_EPRN3_Pos) /*!< USB0 ENDPTNAK: EPRN3 Mask */ -#define USB0_ENDPTNAK_EPRN4_Pos 4 /*!< USB0 ENDPTNAK: EPRN4 Position */ -#define USB0_ENDPTNAK_EPRN4_Msk (0x01UL << USB0_ENDPTNAK_EPRN4_Pos) /*!< USB0 ENDPTNAK: EPRN4 Mask */ -#define USB0_ENDPTNAK_EPRN5_Pos 5 /*!< USB0 ENDPTNAK: EPRN5 Position */ -#define USB0_ENDPTNAK_EPRN5_Msk (0x01UL << USB0_ENDPTNAK_EPRN5_Pos) /*!< USB0 ENDPTNAK: EPRN5 Mask */ -#define USB0_ENDPTNAK_EPTN0_Pos 16 /*!< USB0 ENDPTNAK: EPTN0 Position */ -#define USB0_ENDPTNAK_EPTN0_Msk (0x01UL << USB0_ENDPTNAK_EPTN0_Pos) /*!< USB0 ENDPTNAK: EPTN0 Mask */ -#define USB0_ENDPTNAK_EPTN1_Pos 17 /*!< USB0 ENDPTNAK: EPTN1 Position */ -#define USB0_ENDPTNAK_EPTN1_Msk (0x01UL << USB0_ENDPTNAK_EPTN1_Pos) /*!< USB0 ENDPTNAK: EPTN1 Mask */ -#define USB0_ENDPTNAK_EPTN2_Pos 18 /*!< USB0 ENDPTNAK: EPTN2 Position */ -#define USB0_ENDPTNAK_EPTN2_Msk (0x01UL << USB0_ENDPTNAK_EPTN2_Pos) /*!< USB0 ENDPTNAK: EPTN2 Mask */ -#define USB0_ENDPTNAK_EPTN3_Pos 19 /*!< USB0 ENDPTNAK: EPTN3 Position */ -#define USB0_ENDPTNAK_EPTN3_Msk (0x01UL << USB0_ENDPTNAK_EPTN3_Pos) /*!< USB0 ENDPTNAK: EPTN3 Mask */ -#define USB0_ENDPTNAK_EPTN4_Pos 20 /*!< USB0 ENDPTNAK: EPTN4 Position */ -#define USB0_ENDPTNAK_EPTN4_Msk (0x01UL << USB0_ENDPTNAK_EPTN4_Pos) /*!< USB0 ENDPTNAK: EPTN4 Mask */ -#define USB0_ENDPTNAK_EPTN5_Pos 21 /*!< USB0 ENDPTNAK: EPTN5 Position */ -#define USB0_ENDPTNAK_EPTN5_Msk (0x01UL << USB0_ENDPTNAK_EPTN5_Pos) /*!< USB0 ENDPTNAK: EPTN5 Mask */ - -// ------------------------------------- USB0_ENDPTNAKEN ---------------------------------------- -#define USB0_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB0 ENDPTNAKEN: EPRNE0 Position */ -#define USB0_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos) /*!< USB0 ENDPTNAKEN: EPRNE0 Mask */ -#define USB0_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB0 ENDPTNAKEN: EPRNE1 Position */ -#define USB0_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos) /*!< USB0 ENDPTNAKEN: EPRNE1 Mask */ -#define USB0_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB0 ENDPTNAKEN: EPRNE2 Position */ -#define USB0_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos) /*!< USB0 ENDPTNAKEN: EPRNE2 Mask */ -#define USB0_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB0 ENDPTNAKEN: EPRNE3 Position */ -#define USB0_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos) /*!< USB0 ENDPTNAKEN: EPRNE3 Mask */ -#define USB0_ENDPTNAKEN_EPRNE4_Pos 4 /*!< USB0 ENDPTNAKEN: EPRNE4 Position */ -#define USB0_ENDPTNAKEN_EPRNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos) /*!< USB0 ENDPTNAKEN: EPRNE4 Mask */ -#define USB0_ENDPTNAKEN_EPRNE5_Pos 5 /*!< USB0 ENDPTNAKEN: EPRNE5 Position */ -#define USB0_ENDPTNAKEN_EPRNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos) /*!< USB0 ENDPTNAKEN: EPRNE5 Mask */ -#define USB0_ENDPTNAKEN_EPTNE0_Pos 16 /*!< USB0 ENDPTNAKEN: EPTNE0 Position */ -#define USB0_ENDPTNAKEN_EPTNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos) /*!< USB0 ENDPTNAKEN: EPTNE0 Mask */ -#define USB0_ENDPTNAKEN_EPTNE1_Pos 17 /*!< USB0 ENDPTNAKEN: EPTNE1 Position */ -#define USB0_ENDPTNAKEN_EPTNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos) /*!< USB0 ENDPTNAKEN: EPTNE1 Mask */ -#define USB0_ENDPTNAKEN_EPTNE2_Pos 18 /*!< USB0 ENDPTNAKEN: EPTNE2 Position */ -#define USB0_ENDPTNAKEN_EPTNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos) /*!< USB0 ENDPTNAKEN: EPTNE2 Mask */ -#define USB0_ENDPTNAKEN_EPTNE3_Pos 19 /*!< USB0 ENDPTNAKEN: EPTNE3 Position */ -#define USB0_ENDPTNAKEN_EPTNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos) /*!< USB0 ENDPTNAKEN: EPTNE3 Mask */ -#define USB0_ENDPTNAKEN_EPTNE4_Pos 20 /*!< USB0 ENDPTNAKEN: EPTNE4 Position */ -#define USB0_ENDPTNAKEN_EPTNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos) /*!< USB0 ENDPTNAKEN: EPTNE4 Mask */ -#define USB0_ENDPTNAKEN_EPTNE5_Pos 21 /*!< USB0 ENDPTNAKEN: EPTNE5 Position */ -#define USB0_ENDPTNAKEN_EPTNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos) /*!< USB0 ENDPTNAKEN: EPTNE5 Mask */ - -// ------------------------------------- USB0_PORTSC1_D ----------------------------------------- -#define USB0_PORTSC1_D_CCS_Pos 0 /*!< USB0 PORTSC1_D: CCS Position */ -#define USB0_PORTSC1_D_CCS_Msk (0x01UL << USB0_PORTSC1_D_CCS_Pos) /*!< USB0 PORTSC1_D: CCS Mask */ -#define USB0_PORTSC1_D_PE_Pos 2 /*!< USB0 PORTSC1_D: PE Position */ -#define USB0_PORTSC1_D_PE_Msk (0x01UL << USB0_PORTSC1_D_PE_Pos) /*!< USB0 PORTSC1_D: PE Mask */ -#define USB0_PORTSC1_D_PEC_Pos 3 /*!< USB0 PORTSC1_D: PEC Position */ -#define USB0_PORTSC1_D_PEC_Msk (0x01UL << USB0_PORTSC1_D_PEC_Pos) /*!< USB0 PORTSC1_D: PEC Mask */ -#define USB0_PORTSC1_D_FPR_Pos 6 /*!< USB0 PORTSC1_D: FPR Position */ -#define USB0_PORTSC1_D_FPR_Msk (0x01UL << USB0_PORTSC1_D_FPR_Pos) /*!< USB0 PORTSC1_D: FPR Mask */ -#define USB0_PORTSC1_D_SUSP_Pos 7 /*!< USB0 PORTSC1_D: SUSP Position */ -#define USB0_PORTSC1_D_SUSP_Msk (0x01UL << USB0_PORTSC1_D_SUSP_Pos) /*!< USB0 PORTSC1_D: SUSP Mask */ -#define USB0_PORTSC1_D_PR_Pos 8 /*!< USB0 PORTSC1_D: PR Position */ -#define USB0_PORTSC1_D_PR_Msk (0x01UL << USB0_PORTSC1_D_PR_Pos) /*!< USB0 PORTSC1_D: PR Mask */ -#define USB0_PORTSC1_D_HSP_Pos 9 /*!< USB0 PORTSC1_D: HSP Position */ -#define USB0_PORTSC1_D_HSP_Msk (0x01UL << USB0_PORTSC1_D_HSP_Pos) /*!< USB0 PORTSC1_D: HSP Mask */ -#define USB0_PORTSC1_D_PIC1_0_Pos 14 /*!< USB0 PORTSC1_D: PIC1_0 Position */ -#define USB0_PORTSC1_D_PIC1_0_Msk (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos) /*!< USB0 PORTSC1_D: PIC1_0 Mask */ -#define USB0_PORTSC1_D_PTC3_0_Pos 16 /*!< USB0 PORTSC1_D: PTC3_0 Position */ -#define USB0_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos) /*!< USB0 PORTSC1_D: PTC3_0 Mask */ -#define USB0_PORTSC1_D_PHCD_Pos 23 /*!< USB0 PORTSC1_D: PHCD Position */ -#define USB0_PORTSC1_D_PHCD_Msk (0x01UL << USB0_PORTSC1_D_PHCD_Pos) /*!< USB0 PORTSC1_D: PHCD Mask */ -#define USB0_PORTSC1_D_PFSC_Pos 24 /*!< USB0 PORTSC1_D: PFSC Position */ -#define USB0_PORTSC1_D_PFSC_Msk (0x01UL << USB0_PORTSC1_D_PFSC_Pos) /*!< USB0 PORTSC1_D: PFSC Mask */ -#define USB0_PORTSC1_D_PSPD_Pos 26 /*!< USB0 PORTSC1_D: PSPD Position */ -#define USB0_PORTSC1_D_PSPD_Msk (0x03UL << USB0_PORTSC1_D_PSPD_Pos) /*!< USB0 PORTSC1_D: PSPD Mask */ - -// ------------------------------------- USB0_PORTSC1_H ----------------------------------------- -#define USB0_PORTSC1_H_CCS_Pos 0 /*!< USB0 PORTSC1_H: CCS Position */ -#define USB0_PORTSC1_H_CCS_Msk (0x01UL << USB0_PORTSC1_H_CCS_Pos) /*!< USB0 PORTSC1_H: CCS Mask */ -#define USB0_PORTSC1_H_CSC_Pos 1 /*!< USB0 PORTSC1_H: CSC Position */ -#define USB0_PORTSC1_H_CSC_Msk (0x01UL << USB0_PORTSC1_H_CSC_Pos) /*!< USB0 PORTSC1_H: CSC Mask */ -#define USB0_PORTSC1_H_PE_Pos 2 /*!< USB0 PORTSC1_H: PE Position */ -#define USB0_PORTSC1_H_PE_Msk (0x01UL << USB0_PORTSC1_H_PE_Pos) /*!< USB0 PORTSC1_H: PE Mask */ -#define USB0_PORTSC1_H_PEC_Pos 3 /*!< USB0 PORTSC1_H: PEC Position */ -#define USB0_PORTSC1_H_PEC_Msk (0x01UL << USB0_PORTSC1_H_PEC_Pos) /*!< USB0 PORTSC1_H: PEC Mask */ -#define USB0_PORTSC1_H_OCA_Pos 4 /*!< USB0 PORTSC1_H: OCA Position */ -#define USB0_PORTSC1_H_OCA_Msk (0x01UL << USB0_PORTSC1_H_OCA_Pos) /*!< USB0 PORTSC1_H: OCA Mask */ -#define USB0_PORTSC1_H_OCC_Pos 5 /*!< USB0 PORTSC1_H: OCC Position */ -#define USB0_PORTSC1_H_OCC_Msk (0x01UL << USB0_PORTSC1_H_OCC_Pos) /*!< USB0 PORTSC1_H: OCC Mask */ -#define USB0_PORTSC1_H_FPR_Pos 6 /*!< USB0 PORTSC1_H: FPR Position */ -#define USB0_PORTSC1_H_FPR_Msk (0x01UL << USB0_PORTSC1_H_FPR_Pos) /*!< USB0 PORTSC1_H: FPR Mask */ -#define USB0_PORTSC1_H_SUSP_Pos 7 /*!< USB0 PORTSC1_H: SUSP Position */ -#define USB0_PORTSC1_H_SUSP_Msk (0x01UL << USB0_PORTSC1_H_SUSP_Pos) /*!< USB0 PORTSC1_H: SUSP Mask */ -#define USB0_PORTSC1_H_PR_Pos 8 /*!< USB0 PORTSC1_H: PR Position */ -#define USB0_PORTSC1_H_PR_Msk (0x01UL << USB0_PORTSC1_H_PR_Pos) /*!< USB0 PORTSC1_H: PR Mask */ -#define USB0_PORTSC1_H_HSP_Pos 9 /*!< USB0 PORTSC1_H: HSP Position */ -#define USB0_PORTSC1_H_HSP_Msk (0x01UL << USB0_PORTSC1_H_HSP_Pos) /*!< USB0 PORTSC1_H: HSP Mask */ -#define USB0_PORTSC1_H_LS_Pos 10 /*!< USB0 PORTSC1_H: LS Position */ -#define USB0_PORTSC1_H_LS_Msk (0x03UL << USB0_PORTSC1_H_LS_Pos) /*!< USB0 PORTSC1_H: LS Mask */ -#define USB0_PORTSC1_H_PP_Pos 12 /*!< USB0 PORTSC1_H: PP Position */ -#define USB0_PORTSC1_H_PP_Msk (0x01UL << USB0_PORTSC1_H_PP_Pos) /*!< USB0 PORTSC1_H: PP Mask */ -#define USB0_PORTSC1_H_PIC1_0_Pos 14 /*!< USB0 PORTSC1_H: PIC1_0 Position */ -#define USB0_PORTSC1_H_PIC1_0_Msk (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos) /*!< USB0 PORTSC1_H: PIC1_0 Mask */ -#define USB0_PORTSC1_H_PTC3_0_Pos 16 /*!< USB0 PORTSC1_H: PTC3_0 Position */ -#define USB0_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos) /*!< USB0 PORTSC1_H: PTC3_0 Mask */ -#define USB0_PORTSC1_H_WKCN_Pos 20 /*!< USB0 PORTSC1_H: WKCN Position */ -#define USB0_PORTSC1_H_WKCN_Msk (0x01UL << USB0_PORTSC1_H_WKCN_Pos) /*!< USB0 PORTSC1_H: WKCN Mask */ -#define USB0_PORTSC1_H_WKDC_Pos 21 /*!< USB0 PORTSC1_H: WKDC Position */ -#define USB0_PORTSC1_H_WKDC_Msk (0x01UL << USB0_PORTSC1_H_WKDC_Pos) /*!< USB0 PORTSC1_H: WKDC Mask */ -#define USB0_PORTSC1_H_WKOC_Pos 22 /*!< USB0 PORTSC1_H: WKOC Position */ -#define USB0_PORTSC1_H_WKOC_Msk (0x01UL << USB0_PORTSC1_H_WKOC_Pos) /*!< USB0 PORTSC1_H: WKOC Mask */ -#define USB0_PORTSC1_H_PHCD_Pos 23 /*!< USB0 PORTSC1_H: PHCD Position */ -#define USB0_PORTSC1_H_PHCD_Msk (0x01UL << USB0_PORTSC1_H_PHCD_Pos) /*!< USB0 PORTSC1_H: PHCD Mask */ -#define USB0_PORTSC1_H_PFSC_Pos 24 /*!< USB0 PORTSC1_H: PFSC Position */ -#define USB0_PORTSC1_H_PFSC_Msk (0x01UL << USB0_PORTSC1_H_PFSC_Pos) /*!< USB0 PORTSC1_H: PFSC Mask */ -#define USB0_PORTSC1_H_PSPD_Pos 26 /*!< USB0 PORTSC1_H: PSPD Position */ -#define USB0_PORTSC1_H_PSPD_Msk (0x03UL << USB0_PORTSC1_H_PSPD_Pos) /*!< USB0 PORTSC1_H: PSPD Mask */ - -// --------------------------------------- USB0_OTGSC ------------------------------------------- -#define USB0_OTGSC_VD_Pos 0 /*!< USB0 OTGSC: VD Position */ -#define USB0_OTGSC_VD_Msk (0x01UL << USB0_OTGSC_VD_Pos) /*!< USB0 OTGSC: VD Mask */ -#define USB0_OTGSC_VC_Pos 1 /*!< USB0 OTGSC: VC Position */ -#define USB0_OTGSC_VC_Msk (0x01UL << USB0_OTGSC_VC_Pos) /*!< USB0 OTGSC: VC Mask */ -#define USB0_OTGSC_HAAR_Pos 2 /*!< USB0 OTGSC: HAAR Position */ -#define USB0_OTGSC_HAAR_Msk (0x01UL << USB0_OTGSC_HAAR_Pos) /*!< USB0 OTGSC: HAAR Mask */ -#define USB0_OTGSC_OT_Pos 3 /*!< USB0 OTGSC: OT Position */ -#define USB0_OTGSC_OT_Msk (0x01UL << USB0_OTGSC_OT_Pos) /*!< USB0 OTGSC: OT Mask */ -#define USB0_OTGSC_DP_Pos 4 /*!< USB0 OTGSC: DP Position */ -#define USB0_OTGSC_DP_Msk (0x01UL << USB0_OTGSC_DP_Pos) /*!< USB0 OTGSC: DP Mask */ -#define USB0_OTGSC_IDPU_Pos 5 /*!< USB0 OTGSC: IDPU Position */ -#define USB0_OTGSC_IDPU_Msk (0x01UL << USB0_OTGSC_IDPU_Pos) /*!< USB0 OTGSC: IDPU Mask */ -#define USB0_OTGSC_HADP_Pos 6 /*!< USB0 OTGSC: HADP Position */ -#define USB0_OTGSC_HADP_Msk (0x01UL << USB0_OTGSC_HADP_Pos) /*!< USB0 OTGSC: HADP Mask */ -#define USB0_OTGSC_HABA_Pos 7 /*!< USB0 OTGSC: HABA Position */ -#define USB0_OTGSC_HABA_Msk (0x01UL << USB0_OTGSC_HABA_Pos) /*!< USB0 OTGSC: HABA Mask */ -#define USB0_OTGSC_ID_Pos 8 /*!< USB0 OTGSC: ID Position */ -#define USB0_OTGSC_ID_Msk (0x01UL << USB0_OTGSC_ID_Pos) /*!< USB0 OTGSC: ID Mask */ -#define USB0_OTGSC_AVV_Pos 9 /*!< USB0 OTGSC: AVV Position */ -#define USB0_OTGSC_AVV_Msk (0x01UL << USB0_OTGSC_AVV_Pos) /*!< USB0 OTGSC: AVV Mask */ -#define USB0_OTGSC_ASV_Pos 10 /*!< USB0 OTGSC: ASV Position */ -#define USB0_OTGSC_ASV_Msk (0x01UL << USB0_OTGSC_ASV_Pos) /*!< USB0 OTGSC: ASV Mask */ -#define USB0_OTGSC_BSV_Pos 11 /*!< USB0 OTGSC: BSV Position */ -#define USB0_OTGSC_BSV_Msk (0x01UL << USB0_OTGSC_BSV_Pos) /*!< USB0 OTGSC: BSV Mask */ -#define USB0_OTGSC_BSE_Pos 12 /*!< USB0 OTGSC: BSE Position */ -#define USB0_OTGSC_BSE_Msk (0x01UL << USB0_OTGSC_BSE_Pos) /*!< USB0 OTGSC: BSE Mask */ -#define USB0_OTGSC_MS1T_Pos 13 /*!< USB0 OTGSC: MS1T Position */ -#define USB0_OTGSC_MS1T_Msk (0x01UL << USB0_OTGSC_MS1T_Pos) /*!< USB0 OTGSC: MS1T Mask */ -#define USB0_OTGSC_DPS_Pos 14 /*!< USB0 OTGSC: DPS Position */ -#define USB0_OTGSC_DPS_Msk (0x01UL << USB0_OTGSC_DPS_Pos) /*!< USB0 OTGSC: DPS Mask */ -#define USB0_OTGSC_IDIS_Pos 16 /*!< USB0 OTGSC: IDIS Position */ -#define USB0_OTGSC_IDIS_Msk (0x01UL << USB0_OTGSC_IDIS_Pos) /*!< USB0 OTGSC: IDIS Mask */ -#define USB0_OTGSC_AVVIS_Pos 17 /*!< USB0 OTGSC: AVVIS Position */ -#define USB0_OTGSC_AVVIS_Msk (0x01UL << USB0_OTGSC_AVVIS_Pos) /*!< USB0 OTGSC: AVVIS Mask */ -#define USB0_OTGSC_ASVIS_Pos 18 /*!< USB0 OTGSC: ASVIS Position */ -#define USB0_OTGSC_ASVIS_Msk (0x01UL << USB0_OTGSC_ASVIS_Pos) /*!< USB0 OTGSC: ASVIS Mask */ -#define USB0_OTGSC_BSVIS_Pos 19 /*!< USB0 OTGSC: BSVIS Position */ -#define USB0_OTGSC_BSVIS_Msk (0x01UL << USB0_OTGSC_BSVIS_Pos) /*!< USB0 OTGSC: BSVIS Mask */ -#define USB0_OTGSC_BSEIS_Pos 20 /*!< USB0 OTGSC: BSEIS Position */ -#define USB0_OTGSC_BSEIS_Msk (0x01UL << USB0_OTGSC_BSEIS_Pos) /*!< USB0 OTGSC: BSEIS Mask */ -#define USB0_OTGSC_ms1S_Pos 21 /*!< USB0 OTGSC: ms1S Position */ -#define USB0_OTGSC_ms1S_Msk (0x01UL << USB0_OTGSC_ms1S_Pos) /*!< USB0 OTGSC: ms1S Mask */ -#define USB0_OTGSC_DPIS_Pos 22 /*!< USB0 OTGSC: DPIS Position */ -#define USB0_OTGSC_DPIS_Msk (0x01UL << USB0_OTGSC_DPIS_Pos) /*!< USB0 OTGSC: DPIS Mask */ -#define USB0_OTGSC_IDIE_Pos 24 /*!< USB0 OTGSC: IDIE Position */ -#define USB0_OTGSC_IDIE_Msk (0x01UL << USB0_OTGSC_IDIE_Pos) /*!< USB0 OTGSC: IDIE Mask */ -#define USB0_OTGSC_AVVIE_Pos 25 /*!< USB0 OTGSC: AVVIE Position */ -#define USB0_OTGSC_AVVIE_Msk (0x01UL << USB0_OTGSC_AVVIE_Pos) /*!< USB0 OTGSC: AVVIE Mask */ -#define USB0_OTGSC_ASVIE_Pos 26 /*!< USB0 OTGSC: ASVIE Position */ -#define USB0_OTGSC_ASVIE_Msk (0x01UL << USB0_OTGSC_ASVIE_Pos) /*!< USB0 OTGSC: ASVIE Mask */ -#define USB0_OTGSC_BSVIE_Pos 27 /*!< USB0 OTGSC: BSVIE Position */ -#define USB0_OTGSC_BSVIE_Msk (0x01UL << USB0_OTGSC_BSVIE_Pos) /*!< USB0 OTGSC: BSVIE Mask */ -#define USB0_OTGSC_BSEIE_Pos 28 /*!< USB0 OTGSC: BSEIE Position */ -#define USB0_OTGSC_BSEIE_Msk (0x01UL << USB0_OTGSC_BSEIE_Pos) /*!< USB0 OTGSC: BSEIE Mask */ -#define USB0_OTGSC_MS1E_Pos 29 /*!< USB0 OTGSC: MS1E Position */ -#define USB0_OTGSC_MS1E_Msk (0x01UL << USB0_OTGSC_MS1E_Pos) /*!< USB0 OTGSC: MS1E Mask */ -#define USB0_OTGSC_DPIE_Pos 30 /*!< USB0 OTGSC: DPIE Position */ -#define USB0_OTGSC_DPIE_Msk (0x01UL << USB0_OTGSC_DPIE_Pos) /*!< USB0 OTGSC: DPIE Mask */ - -// ------------------------------------- USB0_USBMODE_D ----------------------------------------- -#define USB0_USBMODE_D_CM1_0_Pos 0 /*!< USB0 USBMODE_D: CM1_0 Position */ -#define USB0_USBMODE_D_CM1_0_Msk (0x03UL << USB0_USBMODE_D_CM1_0_Pos) /*!< USB0 USBMODE_D: CM1_0 Mask */ -#define USB0_USBMODE_D_ES_Pos 2 /*!< USB0 USBMODE_D: ES Position */ -#define USB0_USBMODE_D_ES_Msk (0x01UL << USB0_USBMODE_D_ES_Pos) /*!< USB0 USBMODE_D: ES Mask */ -#define USB0_USBMODE_D_SLOM_Pos 3 /*!< USB0 USBMODE_D: SLOM Position */ -#define USB0_USBMODE_D_SLOM_Msk (0x01UL << USB0_USBMODE_D_SLOM_Pos) /*!< USB0 USBMODE_D: SLOM Mask */ -#define USB0_USBMODE_D_SDIS_Pos 4 /*!< USB0 USBMODE_D: SDIS Position */ -#define USB0_USBMODE_D_SDIS_Msk (0x01UL << USB0_USBMODE_D_SDIS_Pos) /*!< USB0 USBMODE_D: SDIS Mask */ - -// ------------------------------------- USB0_USBMODE_H ----------------------------------------- -#define USB0_USBMODE_H_CM_Pos 0 /*!< USB0 USBMODE_H: CM Position */ -#define USB0_USBMODE_H_CM_Msk (0x03UL << USB0_USBMODE_H_CM_Pos) /*!< USB0 USBMODE_H: CM Mask */ -#define USB0_USBMODE_H_ES_Pos 2 /*!< USB0 USBMODE_H: ES Position */ -#define USB0_USBMODE_H_ES_Msk (0x01UL << USB0_USBMODE_H_ES_Pos) /*!< USB0 USBMODE_H: ES Mask */ -#define USB0_USBMODE_H_SDIS_Pos 4 /*!< USB0 USBMODE_H: SDIS Position */ -#define USB0_USBMODE_H_SDIS_Msk (0x01UL << USB0_USBMODE_H_SDIS_Pos) /*!< USB0 USBMODE_H: SDIS Mask */ -#define USB0_USBMODE_H_VBPS_Pos 5 /*!< USB0 USBMODE_H: VBPS Position */ -#define USB0_USBMODE_H_VBPS_Msk (0x01UL << USB0_USBMODE_H_VBPS_Pos) /*!< USB0 USBMODE_H: VBPS Mask */ - -// ----------------------------------- USB0_ENDPTSETUPSTAT -------------------------------------- -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos 4 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos 5 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */ - -// ------------------------------------- USB0_ENDPTPRIME ---------------------------------------- -#define USB0_ENDPTPRIME_PERB0_Pos 0 /*!< USB0 ENDPTPRIME: PERB0 Position */ -#define USB0_ENDPTPRIME_PERB0_Msk (0x01UL << USB0_ENDPTPRIME_PERB0_Pos) /*!< USB0 ENDPTPRIME: PERB0 Mask */ -#define USB0_ENDPTPRIME_PERB1_Pos 1 /*!< USB0 ENDPTPRIME: PERB1 Position */ -#define USB0_ENDPTPRIME_PERB1_Msk (0x01UL << USB0_ENDPTPRIME_PERB1_Pos) /*!< USB0 ENDPTPRIME: PERB1 Mask */ -#define USB0_ENDPTPRIME_PERB2_Pos 2 /*!< USB0 ENDPTPRIME: PERB2 Position */ -#define USB0_ENDPTPRIME_PERB2_Msk (0x01UL << USB0_ENDPTPRIME_PERB2_Pos) /*!< USB0 ENDPTPRIME: PERB2 Mask */ -#define USB0_ENDPTPRIME_PERB3_Pos 3 /*!< USB0 ENDPTPRIME: PERB3 Position */ -#define USB0_ENDPTPRIME_PERB3_Msk (0x01UL << USB0_ENDPTPRIME_PERB3_Pos) /*!< USB0 ENDPTPRIME: PERB3 Mask */ -#define USB0_ENDPTPRIME_PERB4_Pos 4 /*!< USB0 ENDPTPRIME: PERB4 Position */ -#define USB0_ENDPTPRIME_PERB4_Msk (0x01UL << USB0_ENDPTPRIME_PERB4_Pos) /*!< USB0 ENDPTPRIME: PERB4 Mask */ -#define USB0_ENDPTPRIME_PERB5_Pos 5 /*!< USB0 ENDPTPRIME: PERB5 Position */ -#define USB0_ENDPTPRIME_PERB5_Msk (0x01UL << USB0_ENDPTPRIME_PERB5_Pos) /*!< USB0 ENDPTPRIME: PERB5 Mask */ -#define USB0_ENDPTPRIME_PETB0_Pos 16 /*!< USB0 ENDPTPRIME: PETB0 Position */ -#define USB0_ENDPTPRIME_PETB0_Msk (0x01UL << USB0_ENDPTPRIME_PETB0_Pos) /*!< USB0 ENDPTPRIME: PETB0 Mask */ -#define USB0_ENDPTPRIME_PETB1_Pos 17 /*!< USB0 ENDPTPRIME: PETB1 Position */ -#define USB0_ENDPTPRIME_PETB1_Msk (0x01UL << USB0_ENDPTPRIME_PETB1_Pos) /*!< USB0 ENDPTPRIME: PETB1 Mask */ -#define USB0_ENDPTPRIME_PETB2_Pos 18 /*!< USB0 ENDPTPRIME: PETB2 Position */ -#define USB0_ENDPTPRIME_PETB2_Msk (0x01UL << USB0_ENDPTPRIME_PETB2_Pos) /*!< USB0 ENDPTPRIME: PETB2 Mask */ -#define USB0_ENDPTPRIME_PETB3_Pos 19 /*!< USB0 ENDPTPRIME: PETB3 Position */ -#define USB0_ENDPTPRIME_PETB3_Msk (0x01UL << USB0_ENDPTPRIME_PETB3_Pos) /*!< USB0 ENDPTPRIME: PETB3 Mask */ -#define USB0_ENDPTPRIME_PETB4_Pos 20 /*!< USB0 ENDPTPRIME: PETB4 Position */ -#define USB0_ENDPTPRIME_PETB4_Msk (0x01UL << USB0_ENDPTPRIME_PETB4_Pos) /*!< USB0 ENDPTPRIME: PETB4 Mask */ -#define USB0_ENDPTPRIME_PETB5_Pos 21 /*!< USB0 ENDPTPRIME: PETB5 Position */ -#define USB0_ENDPTPRIME_PETB5_Msk (0x01UL << USB0_ENDPTPRIME_PETB5_Pos) /*!< USB0 ENDPTPRIME: PETB5 Mask */ - -// ------------------------------------- USB0_ENDPTFLUSH ---------------------------------------- -#define USB0_ENDPTFLUSH_FERB0_Pos 0 /*!< USB0 ENDPTFLUSH: FERB0 Position */ -#define USB0_ENDPTFLUSH_FERB0_Msk (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos) /*!< USB0 ENDPTFLUSH: FERB0 Mask */ -#define USB0_ENDPTFLUSH_FERB1_Pos 1 /*!< USB0 ENDPTFLUSH: FERB1 Position */ -#define USB0_ENDPTFLUSH_FERB1_Msk (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos) /*!< USB0 ENDPTFLUSH: FERB1 Mask */ -#define USB0_ENDPTFLUSH_FERB2_Pos 2 /*!< USB0 ENDPTFLUSH: FERB2 Position */ -#define USB0_ENDPTFLUSH_FERB2_Msk (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos) /*!< USB0 ENDPTFLUSH: FERB2 Mask */ -#define USB0_ENDPTFLUSH_FERB3_Pos 3 /*!< USB0 ENDPTFLUSH: FERB3 Position */ -#define USB0_ENDPTFLUSH_FERB3_Msk (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos) /*!< USB0 ENDPTFLUSH: FERB3 Mask */ -#define USB0_ENDPTFLUSH_FERB4_Pos 4 /*!< USB0 ENDPTFLUSH: FERB4 Position */ -#define USB0_ENDPTFLUSH_FERB4_Msk (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos) /*!< USB0 ENDPTFLUSH: FERB4 Mask */ -#define USB0_ENDPTFLUSH_FERB5_Pos 5 /*!< USB0 ENDPTFLUSH: FERB5 Position */ -#define USB0_ENDPTFLUSH_FERB5_Msk (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos) /*!< USB0 ENDPTFLUSH: FERB5 Mask */ -#define USB0_ENDPTFLUSH_FETB0_Pos 16 /*!< USB0 ENDPTFLUSH: FETB0 Position */ -#define USB0_ENDPTFLUSH_FETB0_Msk (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos) /*!< USB0 ENDPTFLUSH: FETB0 Mask */ -#define USB0_ENDPTFLUSH_FETB1_Pos 17 /*!< USB0 ENDPTFLUSH: FETB1 Position */ -#define USB0_ENDPTFLUSH_FETB1_Msk (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos) /*!< USB0 ENDPTFLUSH: FETB1 Mask */ -#define USB0_ENDPTFLUSH_FETB2_Pos 18 /*!< USB0 ENDPTFLUSH: FETB2 Position */ -#define USB0_ENDPTFLUSH_FETB2_Msk (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos) /*!< USB0 ENDPTFLUSH: FETB2 Mask */ -#define USB0_ENDPTFLUSH_FETB3_Pos 19 /*!< USB0 ENDPTFLUSH: FETB3 Position */ -#define USB0_ENDPTFLUSH_FETB3_Msk (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos) /*!< USB0 ENDPTFLUSH: FETB3 Mask */ -#define USB0_ENDPTFLUSH_FETB4_Pos 20 /*!< USB0 ENDPTFLUSH: FETB4 Position */ -#define USB0_ENDPTFLUSH_FETB4_Msk (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos) /*!< USB0 ENDPTFLUSH: FETB4 Mask */ -#define USB0_ENDPTFLUSH_FETB5_Pos 21 /*!< USB0 ENDPTFLUSH: FETB5 Position */ -#define USB0_ENDPTFLUSH_FETB5_Msk (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos) /*!< USB0 ENDPTFLUSH: FETB5 Mask */ - -// ------------------------------------- USB0_ENDPTSTAT ----------------------------------------- -#define USB0_ENDPTSTAT_ERBR0_Pos 0 /*!< USB0 ENDPTSTAT: ERBR0 Position */ -#define USB0_ENDPTSTAT_ERBR0_Msk (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos) /*!< USB0 ENDPTSTAT: ERBR0 Mask */ -#define USB0_ENDPTSTAT_ERBR1_Pos 1 /*!< USB0 ENDPTSTAT: ERBR1 Position */ -#define USB0_ENDPTSTAT_ERBR1_Msk (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos) /*!< USB0 ENDPTSTAT: ERBR1 Mask */ -#define USB0_ENDPTSTAT_ERBR2_Pos 2 /*!< USB0 ENDPTSTAT: ERBR2 Position */ -#define USB0_ENDPTSTAT_ERBR2_Msk (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos) /*!< USB0 ENDPTSTAT: ERBR2 Mask */ -#define USB0_ENDPTSTAT_ERBR3_Pos 3 /*!< USB0 ENDPTSTAT: ERBR3 Position */ -#define USB0_ENDPTSTAT_ERBR3_Msk (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos) /*!< USB0 ENDPTSTAT: ERBR3 Mask */ -#define USB0_ENDPTSTAT_ERBR4_Pos 4 /*!< USB0 ENDPTSTAT: ERBR4 Position */ -#define USB0_ENDPTSTAT_ERBR4_Msk (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos) /*!< USB0 ENDPTSTAT: ERBR4 Mask */ -#define USB0_ENDPTSTAT_ERBR5_Pos 5 /*!< USB0 ENDPTSTAT: ERBR5 Position */ -#define USB0_ENDPTSTAT_ERBR5_Msk (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos) /*!< USB0 ENDPTSTAT: ERBR5 Mask */ -#define USB0_ENDPTSTAT_ETBR0_Pos 16 /*!< USB0 ENDPTSTAT: ETBR0 Position */ -#define USB0_ENDPTSTAT_ETBR0_Msk (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos) /*!< USB0 ENDPTSTAT: ETBR0 Mask */ -#define USB0_ENDPTSTAT_ETBR1_Pos 17 /*!< USB0 ENDPTSTAT: ETBR1 Position */ -#define USB0_ENDPTSTAT_ETBR1_Msk (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos) /*!< USB0 ENDPTSTAT: ETBR1 Mask */ -#define USB0_ENDPTSTAT_ETBR2_Pos 18 /*!< USB0 ENDPTSTAT: ETBR2 Position */ -#define USB0_ENDPTSTAT_ETBR2_Msk (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos) /*!< USB0 ENDPTSTAT: ETBR2 Mask */ -#define USB0_ENDPTSTAT_ETBR3_Pos 19 /*!< USB0 ENDPTSTAT: ETBR3 Position */ -#define USB0_ENDPTSTAT_ETBR3_Msk (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos) /*!< USB0 ENDPTSTAT: ETBR3 Mask */ -#define USB0_ENDPTSTAT_ETBR4_Pos 20 /*!< USB0 ENDPTSTAT: ETBR4 Position */ -#define USB0_ENDPTSTAT_ETBR4_Msk (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos) /*!< USB0 ENDPTSTAT: ETBR4 Mask */ -#define USB0_ENDPTSTAT_ETBR5_Pos 21 /*!< USB0 ENDPTSTAT: ETBR5 Position */ -#define USB0_ENDPTSTAT_ETBR5_Msk (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos) /*!< USB0 ENDPTSTAT: ETBR5 Mask */ - -// ----------------------------------- USB0_ENDPTCOMPLETE --------------------------------------- -#define USB0_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB0 ENDPTCOMPLETE: ERCE0 Position */ -#define USB0_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB0 ENDPTCOMPLETE: ERCE1 Position */ -#define USB0_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB0 ENDPTCOMPLETE: ERCE2 Position */ -#define USB0_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB0 ENDPTCOMPLETE: ERCE3 Position */ -#define USB0_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE4_Pos 4 /*!< USB0 ENDPTCOMPLETE: ERCE4 Position */ -#define USB0_ENDPTCOMPLETE_ERCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE5_Pos 5 /*!< USB0 ENDPTCOMPLETE: ERCE5 Position */ -#define USB0_ENDPTCOMPLETE_ERCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB0 ENDPTCOMPLETE: ETCE0 Position */ -#define USB0_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB0 ENDPTCOMPLETE: ETCE1 Position */ -#define USB0_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB0 ENDPTCOMPLETE: ETCE2 Position */ -#define USB0_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB0 ENDPTCOMPLETE: ETCE3 Position */ -#define USB0_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE4_Pos 20 /*!< USB0 ENDPTCOMPLETE: ETCE4 Position */ -#define USB0_ENDPTCOMPLETE_ETCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE5_Pos 21 /*!< USB0 ENDPTCOMPLETE: ETCE5 Position */ -#define USB0_ENDPTCOMPLETE_ETCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask */ - -// ------------------------------------- USB0_ENDPTCTRL0 ---------------------------------------- -#define USB0_ENDPTCTRL0_RXS_Pos 0 /*!< USB0 ENDPTCTRL0: RXS Position */ -#define USB0_ENDPTCTRL0_RXS_Msk (0x01UL << USB0_ENDPTCTRL0_RXS_Pos) /*!< USB0 ENDPTCTRL0: RXS Mask */ -#define USB0_ENDPTCTRL0_RXT1_0_Pos 2 /*!< USB0 ENDPTCTRL0: RXT1_0 Position */ -#define USB0_ENDPTCTRL0_RXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos) /*!< USB0 ENDPTCTRL0: RXT1_0 Mask */ -#define USB0_ENDPTCTRL0_RXE_Pos 7 /*!< USB0 ENDPTCTRL0: RXE Position */ -#define USB0_ENDPTCTRL0_RXE_Msk (0x01UL << USB0_ENDPTCTRL0_RXE_Pos) /*!< USB0 ENDPTCTRL0: RXE Mask */ -#define USB0_ENDPTCTRL0_TXS_Pos 16 /*!< USB0 ENDPTCTRL0: TXS Position */ -#define USB0_ENDPTCTRL0_TXS_Msk (0x01UL << USB0_ENDPTCTRL0_TXS_Pos) /*!< USB0 ENDPTCTRL0: TXS Mask */ -#define USB0_ENDPTCTRL0_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL0: TXT1_0 Position */ -#define USB0_ENDPTCTRL0_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos) /*!< USB0 ENDPTCTRL0: TXT1_0 Mask */ -#define USB0_ENDPTCTRL0_TXE_Pos 23 /*!< USB0 ENDPTCTRL0: TXE Position */ -#define USB0_ENDPTCTRL0_TXE_Msk (0x01UL << USB0_ENDPTCTRL0_TXE_Pos) /*!< USB0 ENDPTCTRL0: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL1 ---------------------------------------- -#define USB0_ENDPTCTRL1_RXS_Pos 0 /*!< USB0 ENDPTCTRL1: RXS Position */ -#define USB0_ENDPTCTRL1_RXS_Msk (0x01UL << USB0_ENDPTCTRL1_RXS_Pos) /*!< USB0 ENDPTCTRL1: RXS Mask */ -#define USB0_ENDPTCTRL1_RXT_Pos 2 /*!< USB0 ENDPTCTRL1: RXT Position */ -#define USB0_ENDPTCTRL1_RXT_Msk (0x03UL << USB0_ENDPTCTRL1_RXT_Pos) /*!< USB0 ENDPTCTRL1: RXT Mask */ -#define USB0_ENDPTCTRL1_RXI_Pos 5 /*!< USB0 ENDPTCTRL1: RXI Position */ -#define USB0_ENDPTCTRL1_RXI_Msk (0x01UL << USB0_ENDPTCTRL1_RXI_Pos) /*!< USB0 ENDPTCTRL1: RXI Mask */ -#define USB0_ENDPTCTRL1_RXR_Pos 6 /*!< USB0 ENDPTCTRL1: RXR Position */ -#define USB0_ENDPTCTRL1_RXR_Msk (0x01UL << USB0_ENDPTCTRL1_RXR_Pos) /*!< USB0 ENDPTCTRL1: RXR Mask */ -#define USB0_ENDPTCTRL1_RXE_Pos 7 /*!< USB0 ENDPTCTRL1: RXE Position */ -#define USB0_ENDPTCTRL1_RXE_Msk (0x01UL << USB0_ENDPTCTRL1_RXE_Pos) /*!< USB0 ENDPTCTRL1: RXE Mask */ -#define USB0_ENDPTCTRL1_TXS_Pos 16 /*!< USB0 ENDPTCTRL1: TXS Position */ -#define USB0_ENDPTCTRL1_TXS_Msk (0x01UL << USB0_ENDPTCTRL1_TXS_Pos) /*!< USB0 ENDPTCTRL1: TXS Mask */ -#define USB0_ENDPTCTRL1_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL1: TXT1_0 Position */ -#define USB0_ENDPTCTRL1_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos) /*!< USB0 ENDPTCTRL1: TXT1_0 Mask */ -#define USB0_ENDPTCTRL1_TXI_Pos 21 /*!< USB0 ENDPTCTRL1: TXI Position */ -#define USB0_ENDPTCTRL1_TXI_Msk (0x01UL << USB0_ENDPTCTRL1_TXI_Pos) /*!< USB0 ENDPTCTRL1: TXI Mask */ -#define USB0_ENDPTCTRL1_TXR_Pos 22 /*!< USB0 ENDPTCTRL1: TXR Position */ -#define USB0_ENDPTCTRL1_TXR_Msk (0x01UL << USB0_ENDPTCTRL1_TXR_Pos) /*!< USB0 ENDPTCTRL1: TXR Mask */ -#define USB0_ENDPTCTRL1_TXE_Pos 23 /*!< USB0 ENDPTCTRL1: TXE Position */ -#define USB0_ENDPTCTRL1_TXE_Msk (0x01UL << USB0_ENDPTCTRL1_TXE_Pos) /*!< USB0 ENDPTCTRL1: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL2 ---------------------------------------- -#define USB0_ENDPTCTRL2_RXS_Pos 0 /*!< USB0 ENDPTCTRL2: RXS Position */ -#define USB0_ENDPTCTRL2_RXS_Msk (0x01UL << USB0_ENDPTCTRL2_RXS_Pos) /*!< USB0 ENDPTCTRL2: RXS Mask */ -#define USB0_ENDPTCTRL2_RXT_Pos 2 /*!< USB0 ENDPTCTRL2: RXT Position */ -#define USB0_ENDPTCTRL2_RXT_Msk (0x03UL << USB0_ENDPTCTRL2_RXT_Pos) /*!< USB0 ENDPTCTRL2: RXT Mask */ -#define USB0_ENDPTCTRL2_RXI_Pos 5 /*!< USB0 ENDPTCTRL2: RXI Position */ -#define USB0_ENDPTCTRL2_RXI_Msk (0x01UL << USB0_ENDPTCTRL2_RXI_Pos) /*!< USB0 ENDPTCTRL2: RXI Mask */ -#define USB0_ENDPTCTRL2_RXR_Pos 6 /*!< USB0 ENDPTCTRL2: RXR Position */ -#define USB0_ENDPTCTRL2_RXR_Msk (0x01UL << USB0_ENDPTCTRL2_RXR_Pos) /*!< USB0 ENDPTCTRL2: RXR Mask */ -#define USB0_ENDPTCTRL2_RXE_Pos 7 /*!< USB0 ENDPTCTRL2: RXE Position */ -#define USB0_ENDPTCTRL2_RXE_Msk (0x01UL << USB0_ENDPTCTRL2_RXE_Pos) /*!< USB0 ENDPTCTRL2: RXE Mask */ -#define USB0_ENDPTCTRL2_TXS_Pos 16 /*!< USB0 ENDPTCTRL2: TXS Position */ -#define USB0_ENDPTCTRL2_TXS_Msk (0x01UL << USB0_ENDPTCTRL2_TXS_Pos) /*!< USB0 ENDPTCTRL2: TXS Mask */ -#define USB0_ENDPTCTRL2_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL2: TXT1_0 Position */ -#define USB0_ENDPTCTRL2_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos) /*!< USB0 ENDPTCTRL2: TXT1_0 Mask */ -#define USB0_ENDPTCTRL2_TXI_Pos 21 /*!< USB0 ENDPTCTRL2: TXI Position */ -#define USB0_ENDPTCTRL2_TXI_Msk (0x01UL << USB0_ENDPTCTRL2_TXI_Pos) /*!< USB0 ENDPTCTRL2: TXI Mask */ -#define USB0_ENDPTCTRL2_TXR_Pos 22 /*!< USB0 ENDPTCTRL2: TXR Position */ -#define USB0_ENDPTCTRL2_TXR_Msk (0x01UL << USB0_ENDPTCTRL2_TXR_Pos) /*!< USB0 ENDPTCTRL2: TXR Mask */ -#define USB0_ENDPTCTRL2_TXE_Pos 23 /*!< USB0 ENDPTCTRL2: TXE Position */ -#define USB0_ENDPTCTRL2_TXE_Msk (0x01UL << USB0_ENDPTCTRL2_TXE_Pos) /*!< USB0 ENDPTCTRL2: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL3 ---------------------------------------- -#define USB0_ENDPTCTRL3_RXS_Pos 0 /*!< USB0 ENDPTCTRL3: RXS Position */ -#define USB0_ENDPTCTRL3_RXS_Msk (0x01UL << USB0_ENDPTCTRL3_RXS_Pos) /*!< USB0 ENDPTCTRL3: RXS Mask */ -#define USB0_ENDPTCTRL3_RXT_Pos 2 /*!< USB0 ENDPTCTRL3: RXT Position */ -#define USB0_ENDPTCTRL3_RXT_Msk (0x03UL << USB0_ENDPTCTRL3_RXT_Pos) /*!< USB0 ENDPTCTRL3: RXT Mask */ -#define USB0_ENDPTCTRL3_RXI_Pos 5 /*!< USB0 ENDPTCTRL3: RXI Position */ -#define USB0_ENDPTCTRL3_RXI_Msk (0x01UL << USB0_ENDPTCTRL3_RXI_Pos) /*!< USB0 ENDPTCTRL3: RXI Mask */ -#define USB0_ENDPTCTRL3_RXR_Pos 6 /*!< USB0 ENDPTCTRL3: RXR Position */ -#define USB0_ENDPTCTRL3_RXR_Msk (0x01UL << USB0_ENDPTCTRL3_RXR_Pos) /*!< USB0 ENDPTCTRL3: RXR Mask */ -#define USB0_ENDPTCTRL3_RXE_Pos 7 /*!< USB0 ENDPTCTRL3: RXE Position */ -#define USB0_ENDPTCTRL3_RXE_Msk (0x01UL << USB0_ENDPTCTRL3_RXE_Pos) /*!< USB0 ENDPTCTRL3: RXE Mask */ -#define USB0_ENDPTCTRL3_TXS_Pos 16 /*!< USB0 ENDPTCTRL3: TXS Position */ -#define USB0_ENDPTCTRL3_TXS_Msk (0x01UL << USB0_ENDPTCTRL3_TXS_Pos) /*!< USB0 ENDPTCTRL3: TXS Mask */ -#define USB0_ENDPTCTRL3_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL3: TXT1_0 Position */ -#define USB0_ENDPTCTRL3_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos) /*!< USB0 ENDPTCTRL3: TXT1_0 Mask */ -#define USB0_ENDPTCTRL3_TXI_Pos 21 /*!< USB0 ENDPTCTRL3: TXI Position */ -#define USB0_ENDPTCTRL3_TXI_Msk (0x01UL << USB0_ENDPTCTRL3_TXI_Pos) /*!< USB0 ENDPTCTRL3: TXI Mask */ -#define USB0_ENDPTCTRL3_TXR_Pos 22 /*!< USB0 ENDPTCTRL3: TXR Position */ -#define USB0_ENDPTCTRL3_TXR_Msk (0x01UL << USB0_ENDPTCTRL3_TXR_Pos) /*!< USB0 ENDPTCTRL3: TXR Mask */ -#define USB0_ENDPTCTRL3_TXE_Pos 23 /*!< USB0 ENDPTCTRL3: TXE Position */ -#define USB0_ENDPTCTRL3_TXE_Msk (0x01UL << USB0_ENDPTCTRL3_TXE_Pos) /*!< USB0 ENDPTCTRL3: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL4 ---------------------------------------- -#define USB0_ENDPTCTRL4_RXS_Pos 0 /*!< USB0 ENDPTCTRL4: RXS Position */ -#define USB0_ENDPTCTRL4_RXS_Msk (0x01UL << USB0_ENDPTCTRL4_RXS_Pos) /*!< USB0 ENDPTCTRL4: RXS Mask */ -#define USB0_ENDPTCTRL4_RXT_Pos 2 /*!< USB0 ENDPTCTRL4: RXT Position */ -#define USB0_ENDPTCTRL4_RXT_Msk (0x03UL << USB0_ENDPTCTRL4_RXT_Pos) /*!< USB0 ENDPTCTRL4: RXT Mask */ -#define USB0_ENDPTCTRL4_RXI_Pos 5 /*!< USB0 ENDPTCTRL4: RXI Position */ -#define USB0_ENDPTCTRL4_RXI_Msk (0x01UL << USB0_ENDPTCTRL4_RXI_Pos) /*!< USB0 ENDPTCTRL4: RXI Mask */ -#define USB0_ENDPTCTRL4_RXR_Pos 6 /*!< USB0 ENDPTCTRL4: RXR Position */ -#define USB0_ENDPTCTRL4_RXR_Msk (0x01UL << USB0_ENDPTCTRL4_RXR_Pos) /*!< USB0 ENDPTCTRL4: RXR Mask */ -#define USB0_ENDPTCTRL4_RXE_Pos 7 /*!< USB0 ENDPTCTRL4: RXE Position */ -#define USB0_ENDPTCTRL4_RXE_Msk (0x01UL << USB0_ENDPTCTRL4_RXE_Pos) /*!< USB0 ENDPTCTRL4: RXE Mask */ -#define USB0_ENDPTCTRL4_TXS_Pos 16 /*!< USB0 ENDPTCTRL4: TXS Position */ -#define USB0_ENDPTCTRL4_TXS_Msk (0x01UL << USB0_ENDPTCTRL4_TXS_Pos) /*!< USB0 ENDPTCTRL4: TXS Mask */ -#define USB0_ENDPTCTRL4_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL4: TXT1_0 Position */ -#define USB0_ENDPTCTRL4_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos) /*!< USB0 ENDPTCTRL4: TXT1_0 Mask */ -#define USB0_ENDPTCTRL4_TXI_Pos 21 /*!< USB0 ENDPTCTRL4: TXI Position */ -#define USB0_ENDPTCTRL4_TXI_Msk (0x01UL << USB0_ENDPTCTRL4_TXI_Pos) /*!< USB0 ENDPTCTRL4: TXI Mask */ -#define USB0_ENDPTCTRL4_TXR_Pos 22 /*!< USB0 ENDPTCTRL4: TXR Position */ -#define USB0_ENDPTCTRL4_TXR_Msk (0x01UL << USB0_ENDPTCTRL4_TXR_Pos) /*!< USB0 ENDPTCTRL4: TXR Mask */ -#define USB0_ENDPTCTRL4_TXE_Pos 23 /*!< USB0 ENDPTCTRL4: TXE Position */ -#define USB0_ENDPTCTRL4_TXE_Msk (0x01UL << USB0_ENDPTCTRL4_TXE_Pos) /*!< USB0 ENDPTCTRL4: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL5 ---------------------------------------- -#define USB0_ENDPTCTRL5_RXS_Pos 0 /*!< USB0 ENDPTCTRL5: RXS Position */ -#define USB0_ENDPTCTRL5_RXS_Msk (0x01UL << USB0_ENDPTCTRL5_RXS_Pos) /*!< USB0 ENDPTCTRL5: RXS Mask */ -#define USB0_ENDPTCTRL5_RXT_Pos 2 /*!< USB0 ENDPTCTRL5: RXT Position */ -#define USB0_ENDPTCTRL5_RXT_Msk (0x03UL << USB0_ENDPTCTRL5_RXT_Pos) /*!< USB0 ENDPTCTRL5: RXT Mask */ -#define USB0_ENDPTCTRL5_RXI_Pos 5 /*!< USB0 ENDPTCTRL5: RXI Position */ -#define USB0_ENDPTCTRL5_RXI_Msk (0x01UL << USB0_ENDPTCTRL5_RXI_Pos) /*!< USB0 ENDPTCTRL5: RXI Mask */ -#define USB0_ENDPTCTRL5_RXR_Pos 6 /*!< USB0 ENDPTCTRL5: RXR Position */ -#define USB0_ENDPTCTRL5_RXR_Msk (0x01UL << USB0_ENDPTCTRL5_RXR_Pos) /*!< USB0 ENDPTCTRL5: RXR Mask */ -#define USB0_ENDPTCTRL5_RXE_Pos 7 /*!< USB0 ENDPTCTRL5: RXE Position */ -#define USB0_ENDPTCTRL5_RXE_Msk (0x01UL << USB0_ENDPTCTRL5_RXE_Pos) /*!< USB0 ENDPTCTRL5: RXE Mask */ -#define USB0_ENDPTCTRL5_TXS_Pos 16 /*!< USB0 ENDPTCTRL5: TXS Position */ -#define USB0_ENDPTCTRL5_TXS_Msk (0x01UL << USB0_ENDPTCTRL5_TXS_Pos) /*!< USB0 ENDPTCTRL5: TXS Mask */ -#define USB0_ENDPTCTRL5_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL5: TXT1_0 Position */ -#define USB0_ENDPTCTRL5_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos) /*!< USB0 ENDPTCTRL5: TXT1_0 Mask */ -#define USB0_ENDPTCTRL5_TXI_Pos 21 /*!< USB0 ENDPTCTRL5: TXI Position */ -#define USB0_ENDPTCTRL5_TXI_Msk (0x01UL << USB0_ENDPTCTRL5_TXI_Pos) /*!< USB0 ENDPTCTRL5: TXI Mask */ -#define USB0_ENDPTCTRL5_TXR_Pos 22 /*!< USB0 ENDPTCTRL5: TXR Position */ -#define USB0_ENDPTCTRL5_TXR_Msk (0x01UL << USB0_ENDPTCTRL5_TXR_Pos) /*!< USB0 ENDPTCTRL5: TXR Mask */ -#define USB0_ENDPTCTRL5_TXE_Pos 23 /*!< USB0 ENDPTCTRL5: TXE Position */ -#define USB0_ENDPTCTRL5_TXE_Msk (0x01UL << USB0_ENDPTCTRL5_TXE_Pos) /*!< USB0 ENDPTCTRL5: TXE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USB1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- USB1_CAPLENGTH ----------------------------------------- -#define USB1_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB1 CAPLENGTH: CAPLENGTH Position */ -#define USB1_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos) /*!< USB1 CAPLENGTH: CAPLENGTH Mask */ -#define USB1_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB1 CAPLENGTH: HCIVERSION Position */ -#define USB1_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos) /*!< USB1 CAPLENGTH: HCIVERSION Mask */ - -// ------------------------------------- USB1_HCSPARAMS ----------------------------------------- -#define USB1_HCSPARAMS_N_PORTS_Pos 0 /*!< USB1 HCSPARAMS: N_PORTS Position */ -#define USB1_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos) /*!< USB1 HCSPARAMS: N_PORTS Mask */ -#define USB1_HCSPARAMS_PPC_Pos 4 /*!< USB1 HCSPARAMS: PPC Position */ -#define USB1_HCSPARAMS_PPC_Msk (0x01UL << USB1_HCSPARAMS_PPC_Pos) /*!< USB1 HCSPARAMS: PPC Mask */ -#define USB1_HCSPARAMS_N_PCC_Pos 8 /*!< USB1 HCSPARAMS: N_PCC Position */ -#define USB1_HCSPARAMS_N_PCC_Msk (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos) /*!< USB1 HCSPARAMS: N_PCC Mask */ -#define USB1_HCSPARAMS_N_CC_Pos 12 /*!< USB1 HCSPARAMS: N_CC Position */ -#define USB1_HCSPARAMS_N_CC_Msk (0x0fUL << USB1_HCSPARAMS_N_CC_Pos) /*!< USB1 HCSPARAMS: N_CC Mask */ -#define USB1_HCSPARAMS_PI_Pos 16 /*!< USB1 HCSPARAMS: PI Position */ -#define USB1_HCSPARAMS_PI_Msk (0x01UL << USB1_HCSPARAMS_PI_Pos) /*!< USB1 HCSPARAMS: PI Mask */ -#define USB1_HCSPARAMS_N_PTT_Pos 20 /*!< USB1 HCSPARAMS: N_PTT Position */ -#define USB1_HCSPARAMS_N_PTT_Msk (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos) /*!< USB1 HCSPARAMS: N_PTT Mask */ -#define USB1_HCSPARAMS_N_TT_Pos 24 /*!< USB1 HCSPARAMS: N_TT Position */ -#define USB1_HCSPARAMS_N_TT_Msk (0x0fUL << USB1_HCSPARAMS_N_TT_Pos) /*!< USB1 HCSPARAMS: N_TT Mask */ - -// ------------------------------------- USB1_HCCPARAMS ----------------------------------------- -#define USB1_HCCPARAMS_ADC_Pos 0 /*!< USB1 HCCPARAMS: ADC Position */ -#define USB1_HCCPARAMS_ADC_Msk (0x01UL << USB1_HCCPARAMS_ADC_Pos) /*!< USB1 HCCPARAMS: ADC Mask */ -#define USB1_HCCPARAMS_PFL_Pos 1 /*!< USB1 HCCPARAMS: PFL Position */ -#define USB1_HCCPARAMS_PFL_Msk (0x01UL << USB1_HCCPARAMS_PFL_Pos) /*!< USB1 HCCPARAMS: PFL Mask */ -#define USB1_HCCPARAMS_ASP_Pos 2 /*!< USB1 HCCPARAMS: ASP Position */ -#define USB1_HCCPARAMS_ASP_Msk (0x01UL << USB1_HCCPARAMS_ASP_Pos) /*!< USB1 HCCPARAMS: ASP Mask */ -#define USB1_HCCPARAMS_IST_Pos 4 /*!< USB1 HCCPARAMS: IST Position */ -#define USB1_HCCPARAMS_IST_Msk (0x0fUL << USB1_HCCPARAMS_IST_Pos) /*!< USB1 HCCPARAMS: IST Mask */ -#define USB1_HCCPARAMS_EECP_Pos 8 /*!< USB1 HCCPARAMS: EECP Position */ -#define USB1_HCCPARAMS_EECP_Msk (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos) /*!< USB1 HCCPARAMS: EECP Mask */ - -// ------------------------------------- USB1_DCIVERSION ---------------------------------------- -#define USB1_DCIVERSION_DCIVERSION_Pos 0 /*!< USB1 DCIVERSION: DCIVERSION Position */ -#define USB1_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos) /*!< USB1 DCIVERSION: DCIVERSION Mask */ - -// -------------------------------------- USB1_USBCMD_D ----------------------------------------- -#define USB1_USBCMD_D_RS_Pos 0 /*!< USB1 USBCMD_D: RS Position */ -#define USB1_USBCMD_D_RS_Msk (0x01UL << USB1_USBCMD_D_RS_Pos) /*!< USB1 USBCMD_D: RS Mask */ -#define USB1_USBCMD_D_RST_Pos 1 /*!< USB1 USBCMD_D: RST Position */ -#define USB1_USBCMD_D_RST_Msk (0x01UL << USB1_USBCMD_D_RST_Pos) /*!< USB1 USBCMD_D: RST Mask */ -#define USB1_USBCMD_D_SUTW_Pos 13 /*!< USB1 USBCMD_D: SUTW Position */ -#define USB1_USBCMD_D_SUTW_Msk (0x01UL << USB1_USBCMD_D_SUTW_Pos) /*!< USB1 USBCMD_D: SUTW Mask */ -#define USB1_USBCMD_D_ATDTW_Pos 14 /*!< USB1 USBCMD_D: ATDTW Position */ -#define USB1_USBCMD_D_ATDTW_Msk (0x01UL << USB1_USBCMD_D_ATDTW_Pos) /*!< USB1 USBCMD_D: ATDTW Mask */ -#define USB1_USBCMD_D_FS2_Pos 15 /*!< USB1 USBCMD_D: FS2 Position */ -#define USB1_USBCMD_D_FS2_Msk (0x01UL << USB1_USBCMD_D_FS2_Pos) /*!< USB1 USBCMD_D: FS2 Mask */ -#define USB1_USBCMD_D_ITC_Pos 16 /*!< USB1 USBCMD_D: ITC Position */ -#define USB1_USBCMD_D_ITC_Msk (0x000000ffUL << USB1_USBCMD_D_ITC_Pos) /*!< USB1 USBCMD_D: ITC Mask */ - -// -------------------------------------- USB1_USBCMD_H ----------------------------------------- -#define USB1_USBCMD_H_RS_Pos 0 /*!< USB1 USBCMD_H: RS Position */ -#define USB1_USBCMD_H_RS_Msk (0x01UL << USB1_USBCMD_H_RS_Pos) /*!< USB1 USBCMD_H: RS Mask */ -#define USB1_USBCMD_H_RST_Pos 1 /*!< USB1 USBCMD_H: RST Position */ -#define USB1_USBCMD_H_RST_Msk (0x01UL << USB1_USBCMD_H_RST_Pos) /*!< USB1 USBCMD_H: RST Mask */ -#define USB1_USBCMD_H_FS0_Pos 2 /*!< USB1 USBCMD_H: FS0 Position */ -#define USB1_USBCMD_H_FS0_Msk (0x01UL << USB1_USBCMD_H_FS0_Pos) /*!< USB1 USBCMD_H: FS0 Mask */ -#define USB1_USBCMD_H_FS1_Pos 3 /*!< USB1 USBCMD_H: FS1 Position */ -#define USB1_USBCMD_H_FS1_Msk (0x01UL << USB1_USBCMD_H_FS1_Pos) /*!< USB1 USBCMD_H: FS1 Mask */ -#define USB1_USBCMD_H_PSE_Pos 4 /*!< USB1 USBCMD_H: PSE Position */ -#define USB1_USBCMD_H_PSE_Msk (0x01UL << USB1_USBCMD_H_PSE_Pos) /*!< USB1 USBCMD_H: PSE Mask */ -#define USB1_USBCMD_H_ASE_Pos 5 /*!< USB1 USBCMD_H: ASE Position */ -#define USB1_USBCMD_H_ASE_Msk (0x01UL << USB1_USBCMD_H_ASE_Pos) /*!< USB1 USBCMD_H: ASE Mask */ -#define USB1_USBCMD_H_IAA_Pos 6 /*!< USB1 USBCMD_H: IAA Position */ -#define USB1_USBCMD_H_IAA_Msk (0x01UL << USB1_USBCMD_H_IAA_Pos) /*!< USB1 USBCMD_H: IAA Mask */ -#define USB1_USBCMD_H_ASP1_0_Pos 8 /*!< USB1 USBCMD_H: ASP1_0 Position */ -#define USB1_USBCMD_H_ASP1_0_Msk (0x03UL << USB1_USBCMD_H_ASP1_0_Pos) /*!< USB1 USBCMD_H: ASP1_0 Mask */ -#define USB1_USBCMD_H_ASPE_Pos 11 /*!< USB1 USBCMD_H: ASPE Position */ -#define USB1_USBCMD_H_ASPE_Msk (0x01UL << USB1_USBCMD_H_ASPE_Pos) /*!< USB1 USBCMD_H: ASPE Mask */ -#define USB1_USBCMD_H_FS2_Pos 15 /*!< USB1 USBCMD_H: FS2 Position */ -#define USB1_USBCMD_H_FS2_Msk (0x01UL << USB1_USBCMD_H_FS2_Pos) /*!< USB1 USBCMD_H: FS2 Mask */ -#define USB1_USBCMD_H_ITC_Pos 16 /*!< USB1 USBCMD_H: ITC Position */ -#define USB1_USBCMD_H_ITC_Msk (0x000000ffUL << USB1_USBCMD_H_ITC_Pos) /*!< USB1 USBCMD_H: ITC Mask */ - -// -------------------------------------- USB1_USBSTS_D ----------------------------------------- -#define USB1_USBSTS_D_UI_Pos 0 /*!< USB1 USBSTS_D: UI Position */ -#define USB1_USBSTS_D_UI_Msk (0x01UL << USB1_USBSTS_D_UI_Pos) /*!< USB1 USBSTS_D: UI Mask */ -#define USB1_USBSTS_D_UEI_Pos 1 /*!< USB1 USBSTS_D: UEI Position */ -#define USB1_USBSTS_D_UEI_Msk (0x01UL << USB1_USBSTS_D_UEI_Pos) /*!< USB1 USBSTS_D: UEI Mask */ -#define USB1_USBSTS_D_PCI_Pos 2 /*!< USB1 USBSTS_D: PCI Position */ -#define USB1_USBSTS_D_PCI_Msk (0x01UL << USB1_USBSTS_D_PCI_Pos) /*!< USB1 USBSTS_D: PCI Mask */ -#define USB1_USBSTS_D_URI_Pos 6 /*!< USB1 USBSTS_D: URI Position */ -#define USB1_USBSTS_D_URI_Msk (0x01UL << USB1_USBSTS_D_URI_Pos) /*!< USB1 USBSTS_D: URI Mask */ -#define USB1_USBSTS_D_SRI_Pos 7 /*!< USB1 USBSTS_D: SRI Position */ -#define USB1_USBSTS_D_SRI_Msk (0x01UL << USB1_USBSTS_D_SRI_Pos) /*!< USB1 USBSTS_D: SRI Mask */ -#define USB1_USBSTS_D_SLI_Pos 8 /*!< USB1 USBSTS_D: SLI Position */ -#define USB1_USBSTS_D_SLI_Msk (0x01UL << USB1_USBSTS_D_SLI_Pos) /*!< USB1 USBSTS_D: SLI Mask */ -#define USB1_USBSTS_D_NAKI_Pos 16 /*!< USB1 USBSTS_D: NAKI Position */ -#define USB1_USBSTS_D_NAKI_Msk (0x01UL << USB1_USBSTS_D_NAKI_Pos) /*!< USB1 USBSTS_D: NAKI Mask */ - -// -------------------------------------- USB1_USBSTS_H ----------------------------------------- -#define USB1_USBSTS_H_UI_Pos 0 /*!< USB1 USBSTS_H: UI Position */ -#define USB1_USBSTS_H_UI_Msk (0x01UL << USB1_USBSTS_H_UI_Pos) /*!< USB1 USBSTS_H: UI Mask */ -#define USB1_USBSTS_H_UEI_Pos 1 /*!< USB1 USBSTS_H: UEI Position */ -#define USB1_USBSTS_H_UEI_Msk (0x01UL << USB1_USBSTS_H_UEI_Pos) /*!< USB1 USBSTS_H: UEI Mask */ -#define USB1_USBSTS_H_PCI_Pos 2 /*!< USB1 USBSTS_H: PCI Position */ -#define USB1_USBSTS_H_PCI_Msk (0x01UL << USB1_USBSTS_H_PCI_Pos) /*!< USB1 USBSTS_H: PCI Mask */ -#define USB1_USBSTS_H_FRI_Pos 3 /*!< USB1 USBSTS_H: FRI Position */ -#define USB1_USBSTS_H_FRI_Msk (0x01UL << USB1_USBSTS_H_FRI_Pos) /*!< USB1 USBSTS_H: FRI Mask */ -#define USB1_USBSTS_H_AAI_Pos 5 /*!< USB1 USBSTS_H: AAI Position */ -#define USB1_USBSTS_H_AAI_Msk (0x01UL << USB1_USBSTS_H_AAI_Pos) /*!< USB1 USBSTS_H: AAI Mask */ -#define USB1_USBSTS_H_SRI_Pos 7 /*!< USB1 USBSTS_H: SRI Position */ -#define USB1_USBSTS_H_SRI_Msk (0x01UL << USB1_USBSTS_H_SRI_Pos) /*!< USB1 USBSTS_H: SRI Mask */ -#define USB1_USBSTS_H_SLI_Pos 8 /*!< USB1 USBSTS_H: SLI Position */ -#define USB1_USBSTS_H_SLI_Msk (0x01UL << USB1_USBSTS_H_SLI_Pos) /*!< USB1 USBSTS_H: SLI Mask */ -#define USB1_USBSTS_H_HCH_Pos 12 /*!< USB1 USBSTS_H: HCH Position */ -#define USB1_USBSTS_H_HCH_Msk (0x01UL << USB1_USBSTS_H_HCH_Pos) /*!< USB1 USBSTS_H: HCH Mask */ -#define USB1_USBSTS_H_RCL_Pos 13 /*!< USB1 USBSTS_H: RCL Position */ -#define USB1_USBSTS_H_RCL_Msk (0x01UL << USB1_USBSTS_H_RCL_Pos) /*!< USB1 USBSTS_H: RCL Mask */ -#define USB1_USBSTS_H_PS_Pos 14 /*!< USB1 USBSTS_H: PS Position */ -#define USB1_USBSTS_H_PS_Msk (0x01UL << USB1_USBSTS_H_PS_Pos) /*!< USB1 USBSTS_H: PS Mask */ -#define USB1_USBSTS_H_AS_Pos 15 /*!< USB1 USBSTS_H: AS Position */ -#define USB1_USBSTS_H_AS_Msk (0x01UL << USB1_USBSTS_H_AS_Pos) /*!< USB1 USBSTS_H: AS Mask */ -#define USB1_USBSTS_H_UAI_Pos 18 /*!< USB1 USBSTS_H: UAI Position */ -#define USB1_USBSTS_H_UAI_Msk (0x01UL << USB1_USBSTS_H_UAI_Pos) /*!< USB1 USBSTS_H: UAI Mask */ -#define USB1_USBSTS_H_UPI_Pos 19 /*!< USB1 USBSTS_H: UPI Position */ -#define USB1_USBSTS_H_UPI_Msk (0x01UL << USB1_USBSTS_H_UPI_Pos) /*!< USB1 USBSTS_H: UPI Mask */ - -// ------------------------------------- USB1_USBINTR_D ----------------------------------------- -#define USB1_USBINTR_D_UE_Pos 0 /*!< USB1 USBINTR_D: UE Position */ -#define USB1_USBINTR_D_UE_Msk (0x01UL << USB1_USBINTR_D_UE_Pos) /*!< USB1 USBINTR_D: UE Mask */ -#define USB1_USBINTR_D_UEE_Pos 1 /*!< USB1 USBINTR_D: UEE Position */ -#define USB1_USBINTR_D_UEE_Msk (0x01UL << USB1_USBINTR_D_UEE_Pos) /*!< USB1 USBINTR_D: UEE Mask */ -#define USB1_USBINTR_D_PCE_Pos 2 /*!< USB1 USBINTR_D: PCE Position */ -#define USB1_USBINTR_D_PCE_Msk (0x01UL << USB1_USBINTR_D_PCE_Pos) /*!< USB1 USBINTR_D: PCE Mask */ -#define USB1_USBINTR_D_URE_Pos 6 /*!< USB1 USBINTR_D: URE Position */ -#define USB1_USBINTR_D_URE_Msk (0x01UL << USB1_USBINTR_D_URE_Pos) /*!< USB1 USBINTR_D: URE Mask */ -#define USB1_USBINTR_D_SRE_Pos 7 /*!< USB1 USBINTR_D: SRE Position */ -#define USB1_USBINTR_D_SRE_Msk (0x01UL << USB1_USBINTR_D_SRE_Pos) /*!< USB1 USBINTR_D: SRE Mask */ -#define USB1_USBINTR_D_SLE_Pos 8 /*!< USB1 USBINTR_D: SLE Position */ -#define USB1_USBINTR_D_SLE_Msk (0x01UL << USB1_USBINTR_D_SLE_Pos) /*!< USB1 USBINTR_D: SLE Mask */ -#define USB1_USBINTR_D_NAKE_Pos 16 /*!< USB1 USBINTR_D: NAKE Position */ -#define USB1_USBINTR_D_NAKE_Msk (0x01UL << USB1_USBINTR_D_NAKE_Pos) /*!< USB1 USBINTR_D: NAKE Mask */ -#define USB1_USBINTR_D_UAIE_Pos 18 /*!< USB1 USBINTR_D: UAIE Position */ -#define USB1_USBINTR_D_UAIE_Msk (0x01UL << USB1_USBINTR_D_UAIE_Pos) /*!< USB1 USBINTR_D: UAIE Mask */ -#define USB1_USBINTR_D_UPIA_Pos 19 /*!< USB1 USBINTR_D: UPIA Position */ -#define USB1_USBINTR_D_UPIA_Msk (0x01UL << USB1_USBINTR_D_UPIA_Pos) /*!< USB1 USBINTR_D: UPIA Mask */ - -// ------------------------------------- USB1_USBINTR_H ----------------------------------------- -#define USB1_USBINTR_H_UE_Pos 0 /*!< USB1 USBINTR_H: UE Position */ -#define USB1_USBINTR_H_UE_Msk (0x01UL << USB1_USBINTR_H_UE_Pos) /*!< USB1 USBINTR_H: UE Mask */ -#define USB1_USBINTR_H_UEE_Pos 1 /*!< USB1 USBINTR_H: UEE Position */ -#define USB1_USBINTR_H_UEE_Msk (0x01UL << USB1_USBINTR_H_UEE_Pos) /*!< USB1 USBINTR_H: UEE Mask */ -#define USB1_USBINTR_H_PCE_Pos 2 /*!< USB1 USBINTR_H: PCE Position */ -#define USB1_USBINTR_H_PCE_Msk (0x01UL << USB1_USBINTR_H_PCE_Pos) /*!< USB1 USBINTR_H: PCE Mask */ -#define USB1_USBINTR_H_FRE_Pos 3 /*!< USB1 USBINTR_H: FRE Position */ -#define USB1_USBINTR_H_FRE_Msk (0x01UL << USB1_USBINTR_H_FRE_Pos) /*!< USB1 USBINTR_H: FRE Mask */ -#define USB1_USBINTR_H_AAE_Pos 5 /*!< USB1 USBINTR_H: AAE Position */ -#define USB1_USBINTR_H_AAE_Msk (0x01UL << USB1_USBINTR_H_AAE_Pos) /*!< USB1 USBINTR_H: AAE Mask */ -#define USB1_USBINTR_H_SRE_Pos 7 /*!< USB1 USBINTR_H: SRE Position */ -#define USB1_USBINTR_H_SRE_Msk (0x01UL << USB1_USBINTR_H_SRE_Pos) /*!< USB1 USBINTR_H: SRE Mask */ -#define USB1_USBINTR_H_UAIE_Pos 18 /*!< USB1 USBINTR_H: UAIE Position */ -#define USB1_USBINTR_H_UAIE_Msk (0x01UL << USB1_USBINTR_H_UAIE_Pos) /*!< USB1 USBINTR_H: UAIE Mask */ -#define USB1_USBINTR_H_UPIA_Pos 19 /*!< USB1 USBINTR_H: UPIA Position */ -#define USB1_USBINTR_H_UPIA_Msk (0x01UL << USB1_USBINTR_H_UPIA_Pos) /*!< USB1 USBINTR_H: UPIA Mask */ - -// ------------------------------------- USB1_FRINDEX_D ----------------------------------------- -#define USB1_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */ -#define USB1_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask */ -#define USB1_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */ -#define USB1_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask */ - -// ------------------------------------- USB1_FRINDEX_H ----------------------------------------- -#define USB1_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */ -#define USB1_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask */ -#define USB1_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */ -#define USB1_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask */ - -// ------------------------------------- USB1_DEVICEADDR ---------------------------------------- -#define USB1_DEVICEADDR_USBADRA_Pos 24 /*!< USB1 DEVICEADDR: USBADRA Position */ -#define USB1_DEVICEADDR_USBADRA_Msk (0x01UL << USB1_DEVICEADDR_USBADRA_Pos) /*!< USB1 DEVICEADDR: USBADRA Mask */ -#define USB1_DEVICEADDR_USBADR_Pos 25 /*!< USB1 DEVICEADDR: USBADR Position */ -#define USB1_DEVICEADDR_USBADR_Msk (0x7fUL << USB1_DEVICEADDR_USBADR_Pos) /*!< USB1 DEVICEADDR: USBADR Mask */ - -// ---------------------------------- USB1_PERIODICLISTBASE ------------------------------------- -#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */ -#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */ - -// ---------------------------------- USB1_ENDPOINTLISTADDR ------------------------------------- -#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */ -#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */ - -// ----------------------------------- USB1_ASYNCLISTADDR --------------------------------------- -#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */ -#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */ - -// --------------------------------------- USB1_TTCTRL ------------------------------------------ -#define USB1_TTCTRL_TTHA_Pos 24 /*!< USB1 TTCTRL: TTHA Position */ -#define USB1_TTCTRL_TTHA_Msk (0x7fUL << USB1_TTCTRL_TTHA_Pos) /*!< USB1 TTCTRL: TTHA Mask */ - -// ------------------------------------- USB1_BURSTSIZE ----------------------------------------- -#define USB1_BURSTSIZE_RXPBURST_Pos 0 /*!< USB1 BURSTSIZE: RXPBURST Position */ -#define USB1_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos) /*!< USB1 BURSTSIZE: RXPBURST Mask */ -#define USB1_BURSTSIZE_TXPBURST_Pos 8 /*!< USB1 BURSTSIZE: TXPBURST Position */ -#define USB1_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos) /*!< USB1 BURSTSIZE: TXPBURST Mask */ - -// ------------------------------------ USB1_TXFILLTUNING --------------------------------------- -#define USB1_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB1 TXFILLTUNING: TXSCHOH Position */ -#define USB1_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos) /*!< USB1 TXFILLTUNING: TXSCHOH Mask */ -#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */ -#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */ -#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */ -#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */ - -// ------------------------------------ USB1_ULPIVIEWPORT --------------------------------------- -#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos 0 /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */ -#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask */ -#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos 8 /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */ -#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask */ -#define USB1_ULPIVIEWPORT_ULPIADDR_Pos 16 /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */ -#define USB1_ULPIVIEWPORT_ULPIADDR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask */ -#define USB1_ULPIVIEWPORT_ULPIPORT_Pos 24 /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */ -#define USB1_ULPIVIEWPORT_ULPIPORT_Msk (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos) /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask */ -#define USB1_ULPIVIEWPORT_ULPISS_Pos 27 /*!< USB1 ULPIVIEWPORT: ULPISS Position */ -#define USB1_ULPIVIEWPORT_ULPISS_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos) /*!< USB1 ULPIVIEWPORT: ULPISS Mask */ -#define USB1_ULPIVIEWPORT_ULPIRW_Pos 29 /*!< USB1 ULPIVIEWPORT: ULPIRW Position */ -#define USB1_ULPIVIEWPORT_ULPIRW_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRW Mask */ -#define USB1_ULPIVIEWPORT_ULPIRUN_Pos 30 /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */ -#define USB1_ULPIVIEWPORT_ULPIRUN_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask */ -#define USB1_ULPIVIEWPORT_ULPIWU_Pos 31 /*!< USB1 ULPIVIEWPORT: ULPIWU Position */ -#define USB1_ULPIVIEWPORT_ULPIWU_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos) /*!< USB1 ULPIVIEWPORT: ULPIWU Mask */ - -// ------------------------------------- USB1_BINTERVAL ----------------------------------------- -#define USB1_BINTERVAL_BINT_Pos 0 /*!< USB1 BINTERVAL: BINT Position */ -#define USB1_BINTERVAL_BINT_Msk (0x0fUL << USB1_BINTERVAL_BINT_Pos) /*!< USB1 BINTERVAL: BINT Mask */ - -// -------------------------------------- USB1_ENDPTNAK ----------------------------------------- -#define USB1_ENDPTNAK_EPRN0_Pos 0 /*!< USB1 ENDPTNAK: EPRN0 Position */ -#define USB1_ENDPTNAK_EPRN0_Msk (0x01UL << USB1_ENDPTNAK_EPRN0_Pos) /*!< USB1 ENDPTNAK: EPRN0 Mask */ -#define USB1_ENDPTNAK_EPRN1_Pos 1 /*!< USB1 ENDPTNAK: EPRN1 Position */ -#define USB1_ENDPTNAK_EPRN1_Msk (0x01UL << USB1_ENDPTNAK_EPRN1_Pos) /*!< USB1 ENDPTNAK: EPRN1 Mask */ -#define USB1_ENDPTNAK_EPRN2_Pos 2 /*!< USB1 ENDPTNAK: EPRN2 Position */ -#define USB1_ENDPTNAK_EPRN2_Msk (0x01UL << USB1_ENDPTNAK_EPRN2_Pos) /*!< USB1 ENDPTNAK: EPRN2 Mask */ -#define USB1_ENDPTNAK_EPRN3_Pos 3 /*!< USB1 ENDPTNAK: EPRN3 Position */ -#define USB1_ENDPTNAK_EPRN3_Msk (0x01UL << USB1_ENDPTNAK_EPRN3_Pos) /*!< USB1 ENDPTNAK: EPRN3 Mask */ -#define USB1_ENDPTNAK_EPTN16_Pos 16 /*!< USB1 ENDPTNAK: EPTN16 Position */ -#define USB1_ENDPTNAK_EPTN16_Msk (0x01UL << USB1_ENDPTNAK_EPTN16_Pos) /*!< USB1 ENDPTNAK: EPTN16 Mask */ -#define USB1_ENDPTNAK_EPTN17_Pos 17 /*!< USB1 ENDPTNAK: EPTN17 Position */ -#define USB1_ENDPTNAK_EPTN17_Msk (0x01UL << USB1_ENDPTNAK_EPTN17_Pos) /*!< USB1 ENDPTNAK: EPTN17 Mask */ -#define USB1_ENDPTNAK_EPTN18_Pos 18 /*!< USB1 ENDPTNAK: EPTN18 Position */ -#define USB1_ENDPTNAK_EPTN18_Msk (0x01UL << USB1_ENDPTNAK_EPTN18_Pos) /*!< USB1 ENDPTNAK: EPTN18 Mask */ -#define USB1_ENDPTNAK_EPTN19_Pos 19 /*!< USB1 ENDPTNAK: EPTN19 Position */ -#define USB1_ENDPTNAK_EPTN19_Msk (0x01UL << USB1_ENDPTNAK_EPTN19_Pos) /*!< USB1 ENDPTNAK: EPTN19 Mask */ - -// ------------------------------------- USB1_ENDPTNAKEN ---------------------------------------- -#define USB1_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB1 ENDPTNAKEN: EPRNE0 Position */ -#define USB1_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos) /*!< USB1 ENDPTNAKEN: EPRNE0 Mask */ -#define USB1_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB1 ENDPTNAKEN: EPRNE1 Position */ -#define USB1_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos) /*!< USB1 ENDPTNAKEN: EPRNE1 Mask */ -#define USB1_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB1 ENDPTNAKEN: EPRNE2 Position */ -#define USB1_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos) /*!< USB1 ENDPTNAKEN: EPRNE2 Mask */ -#define USB1_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB1 ENDPTNAKEN: EPRNE3 Position */ -#define USB1_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos) /*!< USB1 ENDPTNAKEN: EPRNE3 Mask */ -#define USB1_ENDPTNAKEN_EPTNE16_Pos 16 /*!< USB1 ENDPTNAKEN: EPTNE16 Position */ -#define USB1_ENDPTNAKEN_EPTNE16_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos) /*!< USB1 ENDPTNAKEN: EPTNE16 Mask */ -#define USB1_ENDPTNAKEN_EPTNE17_Pos 17 /*!< USB1 ENDPTNAKEN: EPTNE17 Position */ -#define USB1_ENDPTNAKEN_EPTNE17_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos) /*!< USB1 ENDPTNAKEN: EPTNE17 Mask */ -#define USB1_ENDPTNAKEN_EPTNE18_Pos 18 /*!< USB1 ENDPTNAKEN: EPTNE18 Position */ -#define USB1_ENDPTNAKEN_EPTNE18_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos) /*!< USB1 ENDPTNAKEN: EPTNE18 Mask */ -#define USB1_ENDPTNAKEN_EPTNE19_Pos 19 /*!< USB1 ENDPTNAKEN: EPTNE19 Position */ -#define USB1_ENDPTNAKEN_EPTNE19_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos) /*!< USB1 ENDPTNAKEN: EPTNE19 Mask */ - -// ------------------------------------- USB1_PORTSC1_D ----------------------------------------- -#define USB1_PORTSC1_D_CCS_Pos 0 /*!< USB1 PORTSC1_D: CCS Position */ -#define USB1_PORTSC1_D_CCS_Msk (0x01UL << USB1_PORTSC1_D_CCS_Pos) /*!< USB1 PORTSC1_D: CCS Mask */ -#define USB1_PORTSC1_D_CSC_Pos 1 /*!< USB1 PORTSC1_D: CSC Position */ -#define USB1_PORTSC1_D_CSC_Msk (0x01UL << USB1_PORTSC1_D_CSC_Pos) /*!< USB1 PORTSC1_D: CSC Mask */ -#define USB1_PORTSC1_D_PE_Pos 2 /*!< USB1 PORTSC1_D: PE Position */ -#define USB1_PORTSC1_D_PE_Msk (0x01UL << USB1_PORTSC1_D_PE_Pos) /*!< USB1 PORTSC1_D: PE Mask */ -#define USB1_PORTSC1_D_PEC_Pos 3 /*!< USB1 PORTSC1_D: PEC Position */ -#define USB1_PORTSC1_D_PEC_Msk (0x01UL << USB1_PORTSC1_D_PEC_Pos) /*!< USB1 PORTSC1_D: PEC Mask */ -#define USB1_PORTSC1_D_FPR_Pos 6 /*!< USB1 PORTSC1_D: FPR Position */ -#define USB1_PORTSC1_D_FPR_Msk (0x01UL << USB1_PORTSC1_D_FPR_Pos) /*!< USB1 PORTSC1_D: FPR Mask */ -#define USB1_PORTSC1_D_SUSP_Pos 7 /*!< USB1 PORTSC1_D: SUSP Position */ -#define USB1_PORTSC1_D_SUSP_Msk (0x01UL << USB1_PORTSC1_D_SUSP_Pos) /*!< USB1 PORTSC1_D: SUSP Mask */ -#define USB1_PORTSC1_D_PR_Pos 8 /*!< USB1 PORTSC1_D: PR Position */ -#define USB1_PORTSC1_D_PR_Msk (0x01UL << USB1_PORTSC1_D_PR_Pos) /*!< USB1 PORTSC1_D: PR Mask */ -#define USB1_PORTSC1_D_HSP_Pos 9 /*!< USB1 PORTSC1_D: HSP Position */ -#define USB1_PORTSC1_D_HSP_Msk (0x01UL << USB1_PORTSC1_D_HSP_Pos) /*!< USB1 PORTSC1_D: HSP Mask */ -#define USB1_PORTSC1_D_LS_Pos 10 /*!< USB1 PORTSC1_D: LS Position */ -#define USB1_PORTSC1_D_LS_Msk (0x03UL << USB1_PORTSC1_D_LS_Pos) /*!< USB1 PORTSC1_D: LS Mask */ -#define USB1_PORTSC1_D_PP_Pos 12 /*!< USB1 PORTSC1_D: PP Position */ -#define USB1_PORTSC1_D_PP_Msk (0x01UL << USB1_PORTSC1_D_PP_Pos) /*!< USB1 PORTSC1_D: PP Mask */ -#define USB1_PORTSC1_D_PIC1_0_Pos 14 /*!< USB1 PORTSC1_D: PIC1_0 Position */ -#define USB1_PORTSC1_D_PIC1_0_Msk (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos) /*!< USB1 PORTSC1_D: PIC1_0 Mask */ -#define USB1_PORTSC1_D_PTC3_0_Pos 16 /*!< USB1 PORTSC1_D: PTC3_0 Position */ -#define USB1_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos) /*!< USB1 PORTSC1_D: PTC3_0 Mask */ -#define USB1_PORTSC1_D_PHCD_Pos 23 /*!< USB1 PORTSC1_D: PHCD Position */ -#define USB1_PORTSC1_D_PHCD_Msk (0x01UL << USB1_PORTSC1_D_PHCD_Pos) /*!< USB1 PORTSC1_D: PHCD Mask */ -#define USB1_PORTSC1_D_PFSC_Pos 24 /*!< USB1 PORTSC1_D: PFSC Position */ -#define USB1_PORTSC1_D_PFSC_Msk (0x01UL << USB1_PORTSC1_D_PFSC_Pos) /*!< USB1 PORTSC1_D: PFSC Mask */ -#define USB1_PORTSC1_D_PSPD_Pos 26 /*!< USB1 PORTSC1_D: PSPD Position */ -#define USB1_PORTSC1_D_PSPD_Msk (0x03UL << USB1_PORTSC1_D_PSPD_Pos) /*!< USB1 PORTSC1_D: PSPD Mask */ -#define USB1_PORTSC1_D_PTS_Pos 30 /*!< USB1 PORTSC1_D: PTS Position */ -#define USB1_PORTSC1_D_PTS_Msk (0x03UL << USB1_PORTSC1_D_PTS_Pos) /*!< USB1 PORTSC1_D: PTS Mask */ - -// ------------------------------------- USB1_PORTSC1_H ----------------------------------------- -#define USB1_PORTSC1_H_CCS_Pos 0 /*!< USB1 PORTSC1_H: CCS Position */ -#define USB1_PORTSC1_H_CCS_Msk (0x01UL << USB1_PORTSC1_H_CCS_Pos) /*!< USB1 PORTSC1_H: CCS Mask */ -#define USB1_PORTSC1_H_CSC_Pos 1 /*!< USB1 PORTSC1_H: CSC Position */ -#define USB1_PORTSC1_H_CSC_Msk (0x01UL << USB1_PORTSC1_H_CSC_Pos) /*!< USB1 PORTSC1_H: CSC Mask */ -#define USB1_PORTSC1_H_PE_Pos 2 /*!< USB1 PORTSC1_H: PE Position */ -#define USB1_PORTSC1_H_PE_Msk (0x01UL << USB1_PORTSC1_H_PE_Pos) /*!< USB1 PORTSC1_H: PE Mask */ -#define USB1_PORTSC1_H_PEC_Pos 3 /*!< USB1 PORTSC1_H: PEC Position */ -#define USB1_PORTSC1_H_PEC_Msk (0x01UL << USB1_PORTSC1_H_PEC_Pos) /*!< USB1 PORTSC1_H: PEC Mask */ -#define USB1_PORTSC1_H_OCA_Pos 4 /*!< USB1 PORTSC1_H: OCA Position */ -#define USB1_PORTSC1_H_OCA_Msk (0x01UL << USB1_PORTSC1_H_OCA_Pos) /*!< USB1 PORTSC1_H: OCA Mask */ -#define USB1_PORTSC1_H_OCC_Pos 5 /*!< USB1 PORTSC1_H: OCC Position */ -#define USB1_PORTSC1_H_OCC_Msk (0x01UL << USB1_PORTSC1_H_OCC_Pos) /*!< USB1 PORTSC1_H: OCC Mask */ -#define USB1_PORTSC1_H_FPR_Pos 6 /*!< USB1 PORTSC1_H: FPR Position */ -#define USB1_PORTSC1_H_FPR_Msk (0x01UL << USB1_PORTSC1_H_FPR_Pos) /*!< USB1 PORTSC1_H: FPR Mask */ -#define USB1_PORTSC1_H_SUSP_Pos 7 /*!< USB1 PORTSC1_H: SUSP Position */ -#define USB1_PORTSC1_H_SUSP_Msk (0x01UL << USB1_PORTSC1_H_SUSP_Pos) /*!< USB1 PORTSC1_H: SUSP Mask */ -#define USB1_PORTSC1_H_PR_Pos 8 /*!< USB1 PORTSC1_H: PR Position */ -#define USB1_PORTSC1_H_PR_Msk (0x01UL << USB1_PORTSC1_H_PR_Pos) /*!< USB1 PORTSC1_H: PR Mask */ -#define USB1_PORTSC1_H_HSP_Pos 9 /*!< USB1 PORTSC1_H: HSP Position */ -#define USB1_PORTSC1_H_HSP_Msk (0x01UL << USB1_PORTSC1_H_HSP_Pos) /*!< USB1 PORTSC1_H: HSP Mask */ -#define USB1_PORTSC1_H_LS_Pos 10 /*!< USB1 PORTSC1_H: LS Position */ -#define USB1_PORTSC1_H_LS_Msk (0x03UL << USB1_PORTSC1_H_LS_Pos) /*!< USB1 PORTSC1_H: LS Mask */ -#define USB1_PORTSC1_H_PP_Pos 12 /*!< USB1 PORTSC1_H: PP Position */ -#define USB1_PORTSC1_H_PP_Msk (0x01UL << USB1_PORTSC1_H_PP_Pos) /*!< USB1 PORTSC1_H: PP Mask */ -#define USB1_PORTSC1_H_PIC1_0_Pos 14 /*!< USB1 PORTSC1_H: PIC1_0 Position */ -#define USB1_PORTSC1_H_PIC1_0_Msk (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos) /*!< USB1 PORTSC1_H: PIC1_0 Mask */ -#define USB1_PORTSC1_H_PTC3_0_Pos 16 /*!< USB1 PORTSC1_H: PTC3_0 Position */ -#define USB1_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos) /*!< USB1 PORTSC1_H: PTC3_0 Mask */ -#define USB1_PORTSC1_H_WKCN_Pos 20 /*!< USB1 PORTSC1_H: WKCN Position */ -#define USB1_PORTSC1_H_WKCN_Msk (0x01UL << USB1_PORTSC1_H_WKCN_Pos) /*!< USB1 PORTSC1_H: WKCN Mask */ -#define USB1_PORTSC1_H_WKDC_Pos 21 /*!< USB1 PORTSC1_H: WKDC Position */ -#define USB1_PORTSC1_H_WKDC_Msk (0x01UL << USB1_PORTSC1_H_WKDC_Pos) /*!< USB1 PORTSC1_H: WKDC Mask */ -#define USB1_PORTSC1_H_WKOC_Pos 22 /*!< USB1 PORTSC1_H: WKOC Position */ -#define USB1_PORTSC1_H_WKOC_Msk (0x01UL << USB1_PORTSC1_H_WKOC_Pos) /*!< USB1 PORTSC1_H: WKOC Mask */ -#define USB1_PORTSC1_H_PHCD_Pos 23 /*!< USB1 PORTSC1_H: PHCD Position */ -#define USB1_PORTSC1_H_PHCD_Msk (0x01UL << USB1_PORTSC1_H_PHCD_Pos) /*!< USB1 PORTSC1_H: PHCD Mask */ -#define USB1_PORTSC1_H_PFSC_Pos 24 /*!< USB1 PORTSC1_H: PFSC Position */ -#define USB1_PORTSC1_H_PFSC_Msk (0x01UL << USB1_PORTSC1_H_PFSC_Pos) /*!< USB1 PORTSC1_H: PFSC Mask */ -#define USB1_PORTSC1_H_PSPD_Pos 26 /*!< USB1 PORTSC1_H: PSPD Position */ -#define USB1_PORTSC1_H_PSPD_Msk (0x03UL << USB1_PORTSC1_H_PSPD_Pos) /*!< USB1 PORTSC1_H: PSPD Mask */ -#define USB1_PORTSC1_H_PTS_Pos 30 /*!< USB1 PORTSC1_H: PTS Position */ -#define USB1_PORTSC1_H_PTS_Msk (0x03UL << USB1_PORTSC1_H_PTS_Pos) /*!< USB1 PORTSC1_H: PTS Mask */ - -// ------------------------------------- USB1_USBMODE_D ----------------------------------------- -#define USB1_USBMODE_D_CM1_0_Pos 0 /*!< USB1 USBMODE_D: CM1_0 Position */ -#define USB1_USBMODE_D_CM1_0_Msk (0x03UL << USB1_USBMODE_D_CM1_0_Pos) /*!< USB1 USBMODE_D: CM1_0 Mask */ -#define USB1_USBMODE_D_ES_Pos 2 /*!< USB1 USBMODE_D: ES Position */ -#define USB1_USBMODE_D_ES_Msk (0x01UL << USB1_USBMODE_D_ES_Pos) /*!< USB1 USBMODE_D: ES Mask */ -#define USB1_USBMODE_D_SLOM_Pos 3 /*!< USB1 USBMODE_D: SLOM Position */ -#define USB1_USBMODE_D_SLOM_Msk (0x01UL << USB1_USBMODE_D_SLOM_Pos) /*!< USB1 USBMODE_D: SLOM Mask */ -#define USB1_USBMODE_D_SDIS_Pos 4 /*!< USB1 USBMODE_D: SDIS Position */ -#define USB1_USBMODE_D_SDIS_Msk (0x01UL << USB1_USBMODE_D_SDIS_Pos) /*!< USB1 USBMODE_D: SDIS Mask */ - -// ------------------------------------- USB1_USBMODE_H ----------------------------------------- -#define USB1_USBMODE_H_CM1_0_Pos 0 /*!< USB1 USBMODE_H: CM1_0 Position */ -#define USB1_USBMODE_H_CM1_0_Msk (0x03UL << USB1_USBMODE_H_CM1_0_Pos) /*!< USB1 USBMODE_H: CM1_0 Mask */ -#define USB1_USBMODE_H_ES_Pos 2 /*!< USB1 USBMODE_H: ES Position */ -#define USB1_USBMODE_H_ES_Msk (0x01UL << USB1_USBMODE_H_ES_Pos) /*!< USB1 USBMODE_H: ES Mask */ -#define USB1_USBMODE_H_SDIS_Pos 4 /*!< USB1 USBMODE_H: SDIS Position */ -#define USB1_USBMODE_H_SDIS_Msk (0x01UL << USB1_USBMODE_H_SDIS_Pos) /*!< USB1 USBMODE_H: SDIS Mask */ -#define USB1_USBMODE_H_VBPS_Pos 5 /*!< USB1 USBMODE_H: VBPS Position */ -#define USB1_USBMODE_H_VBPS_Msk (0x01UL << USB1_USBMODE_H_VBPS_Pos) /*!< USB1 USBMODE_H: VBPS Mask */ - -// ----------------------------------- USB1_ENDPTSETUPSTAT -------------------------------------- -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */ - -// ------------------------------------- USB1_ENDPTPRIME ---------------------------------------- -#define USB1_ENDPTPRIME_PERB0_Pos 0 /*!< USB1 ENDPTPRIME: PERB0 Position */ -#define USB1_ENDPTPRIME_PERB0_Msk (0x01UL << USB1_ENDPTPRIME_PERB0_Pos) /*!< USB1 ENDPTPRIME: PERB0 Mask */ -#define USB1_ENDPTPRIME_PERB1_Pos 1 /*!< USB1 ENDPTPRIME: PERB1 Position */ -#define USB1_ENDPTPRIME_PERB1_Msk (0x01UL << USB1_ENDPTPRIME_PERB1_Pos) /*!< USB1 ENDPTPRIME: PERB1 Mask */ -#define USB1_ENDPTPRIME_PERB2_Pos 2 /*!< USB1 ENDPTPRIME: PERB2 Position */ -#define USB1_ENDPTPRIME_PERB2_Msk (0x01UL << USB1_ENDPTPRIME_PERB2_Pos) /*!< USB1 ENDPTPRIME: PERB2 Mask */ -#define USB1_ENDPTPRIME_PERB3_Pos 3 /*!< USB1 ENDPTPRIME: PERB3 Position */ -#define USB1_ENDPTPRIME_PERB3_Msk (0x01UL << USB1_ENDPTPRIME_PERB3_Pos) /*!< USB1 ENDPTPRIME: PERB3 Mask */ -#define USB1_ENDPTPRIME_PETB0_Pos 16 /*!< USB1 ENDPTPRIME: PETB0 Position */ -#define USB1_ENDPTPRIME_PETB0_Msk (0x01UL << USB1_ENDPTPRIME_PETB0_Pos) /*!< USB1 ENDPTPRIME: PETB0 Mask */ -#define USB1_ENDPTPRIME_PETB1_Pos 17 /*!< USB1 ENDPTPRIME: PETB1 Position */ -#define USB1_ENDPTPRIME_PETB1_Msk (0x01UL << USB1_ENDPTPRIME_PETB1_Pos) /*!< USB1 ENDPTPRIME: PETB1 Mask */ -#define USB1_ENDPTPRIME_PETB2_Pos 18 /*!< USB1 ENDPTPRIME: PETB2 Position */ -#define USB1_ENDPTPRIME_PETB2_Msk (0x01UL << USB1_ENDPTPRIME_PETB2_Pos) /*!< USB1 ENDPTPRIME: PETB2 Mask */ -#define USB1_ENDPTPRIME_PETB3_Pos 19 /*!< USB1 ENDPTPRIME: PETB3 Position */ -#define USB1_ENDPTPRIME_PETB3_Msk (0x01UL << USB1_ENDPTPRIME_PETB3_Pos) /*!< USB1 ENDPTPRIME: PETB3 Mask */ - -// ------------------------------------- USB1_ENDPTFLUSH ---------------------------------------- -#define USB1_ENDPTFLUSH_FERB0_Pos 0 /*!< USB1 ENDPTFLUSH: FERB0 Position */ -#define USB1_ENDPTFLUSH_FERB0_Msk (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos) /*!< USB1 ENDPTFLUSH: FERB0 Mask */ -#define USB1_ENDPTFLUSH_FERB1_Pos 1 /*!< USB1 ENDPTFLUSH: FERB1 Position */ -#define USB1_ENDPTFLUSH_FERB1_Msk (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos) /*!< USB1 ENDPTFLUSH: FERB1 Mask */ -#define USB1_ENDPTFLUSH_FERB2_Pos 2 /*!< USB1 ENDPTFLUSH: FERB2 Position */ -#define USB1_ENDPTFLUSH_FERB2_Msk (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos) /*!< USB1 ENDPTFLUSH: FERB2 Mask */ -#define USB1_ENDPTFLUSH_FERB3_Pos 3 /*!< USB1 ENDPTFLUSH: FERB3 Position */ -#define USB1_ENDPTFLUSH_FERB3_Msk (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos) /*!< USB1 ENDPTFLUSH: FERB3 Mask */ -#define USB1_ENDPTFLUSH_FETB0_Pos 16 /*!< USB1 ENDPTFLUSH: FETB0 Position */ -#define USB1_ENDPTFLUSH_FETB0_Msk (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos) /*!< USB1 ENDPTFLUSH: FETB0 Mask */ -#define USB1_ENDPTFLUSH_FETB1_Pos 17 /*!< USB1 ENDPTFLUSH: FETB1 Position */ -#define USB1_ENDPTFLUSH_FETB1_Msk (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos) /*!< USB1 ENDPTFLUSH: FETB1 Mask */ -#define USB1_ENDPTFLUSH_FETB2_Pos 18 /*!< USB1 ENDPTFLUSH: FETB2 Position */ -#define USB1_ENDPTFLUSH_FETB2_Msk (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos) /*!< USB1 ENDPTFLUSH: FETB2 Mask */ -#define USB1_ENDPTFLUSH_FETB3_Pos 19 /*!< USB1 ENDPTFLUSH: FETB3 Position */ -#define USB1_ENDPTFLUSH_FETB3_Msk (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos) /*!< USB1 ENDPTFLUSH: FETB3 Mask */ - -// ------------------------------------- USB1_ENDPTSTAT ----------------------------------------- -#define USB1_ENDPTSTAT_ERBR0_Pos 0 /*!< USB1 ENDPTSTAT: ERBR0 Position */ -#define USB1_ENDPTSTAT_ERBR0_Msk (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos) /*!< USB1 ENDPTSTAT: ERBR0 Mask */ -#define USB1_ENDPTSTAT_ERBR1_Pos 1 /*!< USB1 ENDPTSTAT: ERBR1 Position */ -#define USB1_ENDPTSTAT_ERBR1_Msk (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos) /*!< USB1 ENDPTSTAT: ERBR1 Mask */ -#define USB1_ENDPTSTAT_ERBR2_Pos 2 /*!< USB1 ENDPTSTAT: ERBR2 Position */ -#define USB1_ENDPTSTAT_ERBR2_Msk (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos) /*!< USB1 ENDPTSTAT: ERBR2 Mask */ -#define USB1_ENDPTSTAT_ERBR3_Pos 3 /*!< USB1 ENDPTSTAT: ERBR3 Position */ -#define USB1_ENDPTSTAT_ERBR3_Msk (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos) /*!< USB1 ENDPTSTAT: ERBR3 Mask */ -#define USB1_ENDPTSTAT_ETBR0_Pos 16 /*!< USB1 ENDPTSTAT: ETBR0 Position */ -#define USB1_ENDPTSTAT_ETBR0_Msk (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos) /*!< USB1 ENDPTSTAT: ETBR0 Mask */ -#define USB1_ENDPTSTAT_ETBR1_Pos 17 /*!< USB1 ENDPTSTAT: ETBR1 Position */ -#define USB1_ENDPTSTAT_ETBR1_Msk (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos) /*!< USB1 ENDPTSTAT: ETBR1 Mask */ -#define USB1_ENDPTSTAT_ETBR2_Pos 18 /*!< USB1 ENDPTSTAT: ETBR2 Position */ -#define USB1_ENDPTSTAT_ETBR2_Msk (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos) /*!< USB1 ENDPTSTAT: ETBR2 Mask */ -#define USB1_ENDPTSTAT_ETBR3_Pos 19 /*!< USB1 ENDPTSTAT: ETBR3 Position */ -#define USB1_ENDPTSTAT_ETBR3_Msk (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos) /*!< USB1 ENDPTSTAT: ETBR3 Mask */ - -// ----------------------------------- USB1_ENDPTCOMPLETE --------------------------------------- -#define USB1_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB1 ENDPTCOMPLETE: ERCE0 Position */ -#define USB1_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask */ -#define USB1_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB1 ENDPTCOMPLETE: ERCE1 Position */ -#define USB1_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask */ -#define USB1_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB1 ENDPTCOMPLETE: ERCE2 Position */ -#define USB1_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask */ -#define USB1_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB1 ENDPTCOMPLETE: ERCE3 Position */ -#define USB1_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask */ -#define USB1_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB1 ENDPTCOMPLETE: ETCE0 Position */ -#define USB1_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask */ -#define USB1_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB1 ENDPTCOMPLETE: ETCE1 Position */ -#define USB1_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask */ -#define USB1_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB1 ENDPTCOMPLETE: ETCE2 Position */ -#define USB1_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask */ -#define USB1_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB1 ENDPTCOMPLETE: ETCE3 Position */ -#define USB1_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask */ - -// ------------------------------------- USB1_ENDPTCTRL0 ---------------------------------------- -#define USB1_ENDPTCTRL0_RXS_Pos 0 /*!< USB1 ENDPTCTRL0: RXS Position */ -#define USB1_ENDPTCTRL0_RXS_Msk (0x01UL << USB1_ENDPTCTRL0_RXS_Pos) /*!< USB1 ENDPTCTRL0: RXS Mask */ -#define USB1_ENDPTCTRL0_RXT_Pos 2 /*!< USB1 ENDPTCTRL0: RXT Position */ -#define USB1_ENDPTCTRL0_RXT_Msk (0x03UL << USB1_ENDPTCTRL0_RXT_Pos) /*!< USB1 ENDPTCTRL0: RXT Mask */ -#define USB1_ENDPTCTRL0_RXE_Pos 7 /*!< USB1 ENDPTCTRL0: RXE Position */ -#define USB1_ENDPTCTRL0_RXE_Msk (0x01UL << USB1_ENDPTCTRL0_RXE_Pos) /*!< USB1 ENDPTCTRL0: RXE Mask */ -#define USB1_ENDPTCTRL0_TXS_Pos 16 /*!< USB1 ENDPTCTRL0: TXS Position */ -#define USB1_ENDPTCTRL0_TXS_Msk (0x01UL << USB1_ENDPTCTRL0_TXS_Pos) /*!< USB1 ENDPTCTRL0: TXS Mask */ -#define USB1_ENDPTCTRL0_TXT_Pos 18 /*!< USB1 ENDPTCTRL0: TXT Position */ -#define USB1_ENDPTCTRL0_TXT_Msk (0x03UL << USB1_ENDPTCTRL0_TXT_Pos) /*!< USB1 ENDPTCTRL0: TXT Mask */ -#define USB1_ENDPTCTRL0_TXE_Pos 23 /*!< USB1 ENDPTCTRL0: TXE Position */ -#define USB1_ENDPTCTRL0_TXE_Msk (0x01UL << USB1_ENDPTCTRL0_TXE_Pos) /*!< USB1 ENDPTCTRL0: TXE Mask */ - -// ------------------------------------- USB1_ENDPTCTRL1 ---------------------------------------- -#define USB1_ENDPTCTRL1_RXS_Pos 0 /*!< USB1 ENDPTCTRL1: RXS Position */ -#define USB1_ENDPTCTRL1_RXS_Msk (0x01UL << USB1_ENDPTCTRL1_RXS_Pos) /*!< USB1 ENDPTCTRL1: RXS Mask */ -#define USB1_ENDPTCTRL1_RXT_Pos 2 /*!< USB1 ENDPTCTRL1: RXT Position */ -#define USB1_ENDPTCTRL1_RXT_Msk (0x03UL << USB1_ENDPTCTRL1_RXT_Pos) /*!< USB1 ENDPTCTRL1: RXT Mask */ -#define USB1_ENDPTCTRL1_RXI_Pos 5 /*!< USB1 ENDPTCTRL1: RXI Position */ -#define USB1_ENDPTCTRL1_RXI_Msk (0x01UL << USB1_ENDPTCTRL1_RXI_Pos) /*!< USB1 ENDPTCTRL1: RXI Mask */ -#define USB1_ENDPTCTRL1_RXR_Pos 6 /*!< USB1 ENDPTCTRL1: RXR Position */ -#define USB1_ENDPTCTRL1_RXR_Msk (0x01UL << USB1_ENDPTCTRL1_RXR_Pos) /*!< USB1 ENDPTCTRL1: RXR Mask */ -#define USB1_ENDPTCTRL1_RXE_Pos 7 /*!< USB1 ENDPTCTRL1: RXE Position */ -#define USB1_ENDPTCTRL1_RXE_Msk (0x01UL << USB1_ENDPTCTRL1_RXE_Pos) /*!< USB1 ENDPTCTRL1: RXE Mask */ -#define USB1_ENDPTCTRL1_TXS_Pos 16 /*!< USB1 ENDPTCTRL1: TXS Position */ -#define USB1_ENDPTCTRL1_TXS_Msk (0x01UL << USB1_ENDPTCTRL1_TXS_Pos) /*!< USB1 ENDPTCTRL1: TXS Mask */ -#define USB1_ENDPTCTRL1_TXT_Pos 18 /*!< USB1 ENDPTCTRL1: TXT Position */ -#define USB1_ENDPTCTRL1_TXT_Msk (0x03UL << USB1_ENDPTCTRL1_TXT_Pos) /*!< USB1 ENDPTCTRL1: TXT Mask */ -#define USB1_ENDPTCTRL1_TXI_Pos 21 /*!< USB1 ENDPTCTRL1: TXI Position */ -#define USB1_ENDPTCTRL1_TXI_Msk (0x01UL << USB1_ENDPTCTRL1_TXI_Pos) /*!< USB1 ENDPTCTRL1: TXI Mask */ -#define USB1_ENDPTCTRL1_TXR_Pos 22 /*!< USB1 ENDPTCTRL1: TXR Position */ -#define USB1_ENDPTCTRL1_TXR_Msk (0x01UL << USB1_ENDPTCTRL1_TXR_Pos) /*!< USB1 ENDPTCTRL1: TXR Mask */ -#define USB1_ENDPTCTRL1_TXE_Pos 23 /*!< USB1 ENDPTCTRL1: TXE Position */ -#define USB1_ENDPTCTRL1_TXE_Msk (0x01UL << USB1_ENDPTCTRL1_TXE_Pos) /*!< USB1 ENDPTCTRL1: TXE Mask */ - -// ------------------------------------- USB1_ENDPTCTRL2 ---------------------------------------- -#define USB1_ENDPTCTRL2_RXS_Pos 0 /*!< USB1 ENDPTCTRL2: RXS Position */ -#define USB1_ENDPTCTRL2_RXS_Msk (0x01UL << USB1_ENDPTCTRL2_RXS_Pos) /*!< USB1 ENDPTCTRL2: RXS Mask */ -#define USB1_ENDPTCTRL2_RXT_Pos 2 /*!< USB1 ENDPTCTRL2: RXT Position */ -#define USB1_ENDPTCTRL2_RXT_Msk (0x03UL << USB1_ENDPTCTRL2_RXT_Pos) /*!< USB1 ENDPTCTRL2: RXT Mask */ -#define USB1_ENDPTCTRL2_RXI_Pos 5 /*!< USB1 ENDPTCTRL2: RXI Position */ -#define USB1_ENDPTCTRL2_RXI_Msk (0x01UL << USB1_ENDPTCTRL2_RXI_Pos) /*!< USB1 ENDPTCTRL2: RXI Mask */ -#define USB1_ENDPTCTRL2_RXR_Pos 6 /*!< USB1 ENDPTCTRL2: RXR Position */ -#define USB1_ENDPTCTRL2_RXR_Msk (0x01UL << USB1_ENDPTCTRL2_RXR_Pos) /*!< USB1 ENDPTCTRL2: RXR Mask */ -#define USB1_ENDPTCTRL2_RXE_Pos 7 /*!< USB1 ENDPTCTRL2: RXE Position */ -#define USB1_ENDPTCTRL2_RXE_Msk (0x01UL << USB1_ENDPTCTRL2_RXE_Pos) /*!< USB1 ENDPTCTRL2: RXE Mask */ -#define USB1_ENDPTCTRL2_TXS_Pos 16 /*!< USB1 ENDPTCTRL2: TXS Position */ -#define USB1_ENDPTCTRL2_TXS_Msk (0x01UL << USB1_ENDPTCTRL2_TXS_Pos) /*!< USB1 ENDPTCTRL2: TXS Mask */ -#define USB1_ENDPTCTRL2_TXT_Pos 18 /*!< USB1 ENDPTCTRL2: TXT Position */ -#define USB1_ENDPTCTRL2_TXT_Msk (0x03UL << USB1_ENDPTCTRL2_TXT_Pos) /*!< USB1 ENDPTCTRL2: TXT Mask */ -#define USB1_ENDPTCTRL2_TXI_Pos 21 /*!< USB1 ENDPTCTRL2: TXI Position */ -#define USB1_ENDPTCTRL2_TXI_Msk (0x01UL << USB1_ENDPTCTRL2_TXI_Pos) /*!< USB1 ENDPTCTRL2: TXI Mask */ -#define USB1_ENDPTCTRL2_TXR_Pos 22 /*!< USB1 ENDPTCTRL2: TXR Position */ -#define USB1_ENDPTCTRL2_TXR_Msk (0x01UL << USB1_ENDPTCTRL2_TXR_Pos) /*!< USB1 ENDPTCTRL2: TXR Mask */ -#define USB1_ENDPTCTRL2_TXE_Pos 23 /*!< USB1 ENDPTCTRL2: TXE Position */ -#define USB1_ENDPTCTRL2_TXE_Msk (0x01UL << USB1_ENDPTCTRL2_TXE_Pos) /*!< USB1 ENDPTCTRL2: TXE Mask */ - -// ------------------------------------- USB1_ENDPTCTRL3 ---------------------------------------- -#define USB1_ENDPTCTRL3_RXS_Pos 0 /*!< USB1 ENDPTCTRL3: RXS Position */ -#define USB1_ENDPTCTRL3_RXS_Msk (0x01UL << USB1_ENDPTCTRL3_RXS_Pos) /*!< USB1 ENDPTCTRL3: RXS Mask */ -#define USB1_ENDPTCTRL3_RXT_Pos 2 /*!< USB1 ENDPTCTRL3: RXT Position */ -#define USB1_ENDPTCTRL3_RXT_Msk (0x03UL << USB1_ENDPTCTRL3_RXT_Pos) /*!< USB1 ENDPTCTRL3: RXT Mask */ -#define USB1_ENDPTCTRL3_RXI_Pos 5 /*!< USB1 ENDPTCTRL3: RXI Position */ -#define USB1_ENDPTCTRL3_RXI_Msk (0x01UL << USB1_ENDPTCTRL3_RXI_Pos) /*!< USB1 ENDPTCTRL3: RXI Mask */ -#define USB1_ENDPTCTRL3_RXR_Pos 6 /*!< USB1 ENDPTCTRL3: RXR Position */ -#define USB1_ENDPTCTRL3_RXR_Msk (0x01UL << USB1_ENDPTCTRL3_RXR_Pos) /*!< USB1 ENDPTCTRL3: RXR Mask */ -#define USB1_ENDPTCTRL3_RXE_Pos 7 /*!< USB1 ENDPTCTRL3: RXE Position */ -#define USB1_ENDPTCTRL3_RXE_Msk (0x01UL << USB1_ENDPTCTRL3_RXE_Pos) /*!< USB1 ENDPTCTRL3: RXE Mask */ -#define USB1_ENDPTCTRL3_TXS_Pos 16 /*!< USB1 ENDPTCTRL3: TXS Position */ -#define USB1_ENDPTCTRL3_TXS_Msk (0x01UL << USB1_ENDPTCTRL3_TXS_Pos) /*!< USB1 ENDPTCTRL3: TXS Mask */ -#define USB1_ENDPTCTRL3_TXT_Pos 18 /*!< USB1 ENDPTCTRL3: TXT Position */ -#define USB1_ENDPTCTRL3_TXT_Msk (0x03UL << USB1_ENDPTCTRL3_TXT_Pos) /*!< USB1 ENDPTCTRL3: TXT Mask */ -#define USB1_ENDPTCTRL3_TXI_Pos 21 /*!< USB1 ENDPTCTRL3: TXI Position */ -#define USB1_ENDPTCTRL3_TXI_Msk (0x01UL << USB1_ENDPTCTRL3_TXI_Pos) /*!< USB1 ENDPTCTRL3: TXI Mask */ -#define USB1_ENDPTCTRL3_TXR_Pos 22 /*!< USB1 ENDPTCTRL3: TXR Position */ -#define USB1_ENDPTCTRL3_TXR_Msk (0x01UL << USB1_ENDPTCTRL3_TXR_Pos) /*!< USB1 ENDPTCTRL3: TXR Mask */ -#define USB1_ENDPTCTRL3_TXE_Pos 23 /*!< USB1 ENDPTCTRL3: TXE Position */ -#define USB1_ENDPTCTRL3_TXE_Msk (0x01UL << USB1_ENDPTCTRL3_TXE_Pos) /*!< USB1 ENDPTCTRL3: TXE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- LCD Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- LCD_TIMH -------------------------------------------- -#define LCD_TIMH_PPL_Pos 2 /*!< LCD TIMH: PPL Position */ -#define LCD_TIMH_PPL_Msk (0x3fUL << LCD_TIMH_PPL_Pos) /*!< LCD TIMH: PPL Mask */ -#define LCD_TIMH_HSW_Pos 8 /*!< LCD TIMH: HSW Position */ -#define LCD_TIMH_HSW_Msk (0x000000ffUL << LCD_TIMH_HSW_Pos) /*!< LCD TIMH: HSW Mask */ -#define LCD_TIMH_HFP_Pos 16 /*!< LCD TIMH: HFP Position */ -#define LCD_TIMH_HFP_Msk (0x000000ffUL << LCD_TIMH_HFP_Pos) /*!< LCD TIMH: HFP Mask */ -#define LCD_TIMH_HBP_Pos 24 /*!< LCD TIMH: HBP Position */ -#define LCD_TIMH_HBP_Msk (0x000000ffUL << LCD_TIMH_HBP_Pos) /*!< LCD TIMH: HBP Mask */ - -// ---------------------------------------- LCD_TIMV -------------------------------------------- -#define LCD_TIMV_LPP_Pos 0 /*!< LCD TIMV: LPP Position */ -#define LCD_TIMV_LPP_Msk (0x000003ffUL << LCD_TIMV_LPP_Pos) /*!< LCD TIMV: LPP Mask */ -#define LCD_TIMV_VSW_Pos 10 /*!< LCD TIMV: VSW Position */ -#define LCD_TIMV_VSW_Msk (0x3fUL << LCD_TIMV_VSW_Pos) /*!< LCD TIMV: VSW Mask */ -#define LCD_TIMV_VFP_Pos 16 /*!< LCD TIMV: VFP Position */ -#define LCD_TIMV_VFP_Msk (0x000000ffUL << LCD_TIMV_VFP_Pos) /*!< LCD TIMV: VFP Mask */ -#define LCD_TIMV_VBP_Pos 24 /*!< LCD TIMV: VBP Position */ -#define LCD_TIMV_VBP_Msk (0x000000ffUL << LCD_TIMV_VBP_Pos) /*!< LCD TIMV: VBP Mask */ - -// ----------------------------------------- LCD_POL -------------------------------------------- -#define LCD_POL_PCD_LO_Pos 0 /*!< LCD POL: PCD_LO Position */ -#define LCD_POL_PCD_LO_Msk (0x1fUL << LCD_POL_PCD_LO_Pos) /*!< LCD POL: PCD_LO Mask */ -#define LCD_POL_CLKSEL_Pos 5 /*!< LCD POL: CLKSEL Position */ -#define LCD_POL_CLKSEL_Msk (0x01UL << LCD_POL_CLKSEL_Pos) /*!< LCD POL: CLKSEL Mask */ -#define LCD_POL_ACB_Pos 6 /*!< LCD POL: ACB Position */ -#define LCD_POL_ACB_Msk (0x1fUL << LCD_POL_ACB_Pos) /*!< LCD POL: ACB Mask */ -#define LCD_POL_IVS_Pos 11 /*!< LCD POL: IVS Position */ -#define LCD_POL_IVS_Msk (0x01UL << LCD_POL_IVS_Pos) /*!< LCD POL: IVS Mask */ -#define LCD_POL_IHS_Pos 12 /*!< LCD POL: IHS Position */ -#define LCD_POL_IHS_Msk (0x01UL << LCD_POL_IHS_Pos) /*!< LCD POL: IHS Mask */ -#define LCD_POL_IPC_Pos 13 /*!< LCD POL: IPC Position */ -#define LCD_POL_IPC_Msk (0x01UL << LCD_POL_IPC_Pos) /*!< LCD POL: IPC Mask */ -#define LCD_POL_IOE_Pos 14 /*!< LCD POL: IOE Position */ -#define LCD_POL_IOE_Msk (0x01UL << LCD_POL_IOE_Pos) /*!< LCD POL: IOE Mask */ -#define LCD_POL_CPL_Pos 16 /*!< LCD POL: CPL Position */ -#define LCD_POL_CPL_Msk (0x000003ffUL << LCD_POL_CPL_Pos) /*!< LCD POL: CPL Mask */ -#define LCD_POL_BCD_Pos 26 /*!< LCD POL: BCD Position */ -#define LCD_POL_BCD_Msk (0x01UL << LCD_POL_BCD_Pos) /*!< LCD POL: BCD Mask */ -#define LCD_POL_PCD_HI_Pos 27 /*!< LCD POL: PCD_HI Position */ -#define LCD_POL_PCD_HI_Msk (0x1fUL << LCD_POL_PCD_HI_Pos) /*!< LCD POL: PCD_HI Mask */ - -// ----------------------------------------- LCD_LE --------------------------------------------- -#define LCD_LE_LED_Pos 0 /*!< LCD LE: LED Position */ -#define LCD_LE_LED_Msk (0x7fUL << LCD_LE_LED_Pos) /*!< LCD LE: LED Mask */ -#define LCD_LE_LEE_Pos 16 /*!< LCD LE: LEE Position */ -#define LCD_LE_LEE_Msk (0x01UL << LCD_LE_LEE_Pos) /*!< LCD LE: LEE Mask */ - -// --------------------------------------- LCD_UPBASE ------------------------------------------- -#define LCD_UPBASE_LCDUPBASE_Pos 3 /*!< LCD UPBASE: LCDUPBASE Position */ -#define LCD_UPBASE_LCDUPBASE_Msk (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos) /*!< LCD UPBASE: LCDUPBASE Mask */ - -// --------------------------------------- LCD_LPBASE ------------------------------------------- -#define LCD_LPBASE_LCDLPBASE_Pos 3 /*!< LCD LPBASE: LCDLPBASE Position */ -#define LCD_LPBASE_LCDLPBASE_Msk (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos) /*!< LCD LPBASE: LCDLPBASE Mask */ - -// ---------------------------------------- LCD_CTRL -------------------------------------------- -#define LCD_CTRL_LCDEN_Pos 0 /*!< LCD CTRL: LCDEN Position */ -#define LCD_CTRL_LCDEN_Msk (0x01UL << LCD_CTRL_LCDEN_Pos) /*!< LCD CTRL: LCDEN Mask */ -#define LCD_CTRL_LCDBPP_Pos 1 /*!< LCD CTRL: LCDBPP Position */ -#define LCD_CTRL_LCDBPP_Msk (0x07UL << LCD_CTRL_LCDBPP_Pos) /*!< LCD CTRL: LCDBPP Mask */ -#define LCD_CTRL_LCDBW_Pos 4 /*!< LCD CTRL: LCDBW Position */ -#define LCD_CTRL_LCDBW_Msk (0x01UL << LCD_CTRL_LCDBW_Pos) /*!< LCD CTRL: LCDBW Mask */ -#define LCD_CTRL_LCDTFT_Pos 5 /*!< LCD CTRL: LCDTFT Position */ -#define LCD_CTRL_LCDTFT_Msk (0x01UL << LCD_CTRL_LCDTFT_Pos) /*!< LCD CTRL: LCDTFT Mask */ -#define LCD_CTRL_LCDMONO8_Pos 6 /*!< LCD CTRL: LCDMONO8 Position */ -#define LCD_CTRL_LCDMONO8_Msk (0x01UL << LCD_CTRL_LCDMONO8_Pos) /*!< LCD CTRL: LCDMONO8 Mask */ -#define LCD_CTRL_LCDDUAL_Pos 7 /*!< LCD CTRL: LCDDUAL Position */ -#define LCD_CTRL_LCDDUAL_Msk (0x01UL << LCD_CTRL_LCDDUAL_Pos) /*!< LCD CTRL: LCDDUAL Mask */ -#define LCD_CTRL_BGR_Pos 8 /*!< LCD CTRL: BGR Position */ -#define LCD_CTRL_BGR_Msk (0x01UL << LCD_CTRL_BGR_Pos) /*!< LCD CTRL: BGR Mask */ -#define LCD_CTRL_BEBO_Pos 9 /*!< LCD CTRL: BEBO Position */ -#define LCD_CTRL_BEBO_Msk (0x01UL << LCD_CTRL_BEBO_Pos) /*!< LCD CTRL: BEBO Mask */ -#define LCD_CTRL_BEPO_Pos 10 /*!< LCD CTRL: BEPO Position */ -#define LCD_CTRL_BEPO_Msk (0x01UL << LCD_CTRL_BEPO_Pos) /*!< LCD CTRL: BEPO Mask */ -#define LCD_CTRL_LCDPWR_Pos 11 /*!< LCD CTRL: LCDPWR Position */ -#define LCD_CTRL_LCDPWR_Msk (0x01UL << LCD_CTRL_LCDPWR_Pos) /*!< LCD CTRL: LCDPWR Mask */ -#define LCD_CTRL_LCDVCOMP_Pos 12 /*!< LCD CTRL: LCDVCOMP Position */ -#define LCD_CTRL_LCDVCOMP_Msk (0x03UL << LCD_CTRL_LCDVCOMP_Pos) /*!< LCD CTRL: LCDVCOMP Mask */ -#define LCD_CTRL_WATERMARK_Pos 16 /*!< LCD CTRL: WATERMARK Position */ -#define LCD_CTRL_WATERMARK_Msk (0x01UL << LCD_CTRL_WATERMARK_Pos) /*!< LCD CTRL: WATERMARK Mask */ - -// --------------------------------------- LCD_INTMSK ------------------------------------------- -#define LCD_INTMSK_FUFIM_Pos 1 /*!< LCD INTMSK: FUFIM Position */ -#define LCD_INTMSK_FUFIM_Msk (0x01UL << LCD_INTMSK_FUFIM_Pos) /*!< LCD INTMSK: FUFIM Mask */ -#define LCD_INTMSK_LNBUIM_Pos 2 /*!< LCD INTMSK: LNBUIM Position */ -#define LCD_INTMSK_LNBUIM_Msk (0x01UL << LCD_INTMSK_LNBUIM_Pos) /*!< LCD INTMSK: LNBUIM Mask */ -#define LCD_INTMSK_VCOMPIM_Pos 3 /*!< LCD INTMSK: VCOMPIM Position */ -#define LCD_INTMSK_VCOMPIM_Msk (0x01UL << LCD_INTMSK_VCOMPIM_Pos) /*!< LCD INTMSK: VCOMPIM Mask */ -#define LCD_INTMSK_BERIM_Pos 4 /*!< LCD INTMSK: BERIM Position */ -#define LCD_INTMSK_BERIM_Msk (0x01UL << LCD_INTMSK_BERIM_Pos) /*!< LCD INTMSK: BERIM Mask */ - -// --------------------------------------- LCD_INTRAW ------------------------------------------- -#define LCD_INTRAW_FUFRIS_Pos 1 /*!< LCD INTRAW: FUFRIS Position */ -#define LCD_INTRAW_FUFRIS_Msk (0x01UL << LCD_INTRAW_FUFRIS_Pos) /*!< LCD INTRAW: FUFRIS Mask */ -#define LCD_INTRAW_LNBURIS_Pos 2 /*!< LCD INTRAW: LNBURIS Position */ -#define LCD_INTRAW_LNBURIS_Msk (0x01UL << LCD_INTRAW_LNBURIS_Pos) /*!< LCD INTRAW: LNBURIS Mask */ -#define LCD_INTRAW_VCOMPRIS_Pos 3 /*!< LCD INTRAW: VCOMPRIS Position */ -#define LCD_INTRAW_VCOMPRIS_Msk (0x01UL << LCD_INTRAW_VCOMPRIS_Pos) /*!< LCD INTRAW: VCOMPRIS Mask */ -#define LCD_INTRAW_BERRAW_Pos 4 /*!< LCD INTRAW: BERRAW Position */ -#define LCD_INTRAW_BERRAW_Msk (0x01UL << LCD_INTRAW_BERRAW_Pos) /*!< LCD INTRAW: BERRAW Mask */ - -// --------------------------------------- LCD_INTSTAT ------------------------------------------ -#define LCD_INTSTAT_FUFMIS_Pos 1 /*!< LCD INTSTAT: FUFMIS Position */ -#define LCD_INTSTAT_FUFMIS_Msk (0x01UL << LCD_INTSTAT_FUFMIS_Pos) /*!< LCD INTSTAT: FUFMIS Mask */ -#define LCD_INTSTAT_LNBUMIS_Pos 2 /*!< LCD INTSTAT: LNBUMIS Position */ -#define LCD_INTSTAT_LNBUMIS_Msk (0x01UL << LCD_INTSTAT_LNBUMIS_Pos) /*!< LCD INTSTAT: LNBUMIS Mask */ -#define LCD_INTSTAT_VCOMPMIS_Pos 3 /*!< LCD INTSTAT: VCOMPMIS Position */ -#define LCD_INTSTAT_VCOMPMIS_Msk (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos) /*!< LCD INTSTAT: VCOMPMIS Mask */ -#define LCD_INTSTAT_BERMIS_Pos 4 /*!< LCD INTSTAT: BERMIS Position */ -#define LCD_INTSTAT_BERMIS_Msk (0x01UL << LCD_INTSTAT_BERMIS_Pos) /*!< LCD INTSTAT: BERMIS Mask */ - -// --------------------------------------- LCD_INTCLR ------------------------------------------- -#define LCD_INTCLR_FUFIC_Pos 1 /*!< LCD INTCLR: FUFIC Position */ -#define LCD_INTCLR_FUFIC_Msk (0x01UL << LCD_INTCLR_FUFIC_Pos) /*!< LCD INTCLR: FUFIC Mask */ -#define LCD_INTCLR_LNBUIC_Pos 2 /*!< LCD INTCLR: LNBUIC Position */ -#define LCD_INTCLR_LNBUIC_Msk (0x01UL << LCD_INTCLR_LNBUIC_Pos) /*!< LCD INTCLR: LNBUIC Mask */ -#define LCD_INTCLR_VCOMPIC_Pos 3 /*!< LCD INTCLR: VCOMPIC Position */ -#define LCD_INTCLR_VCOMPIC_Msk (0x01UL << LCD_INTCLR_VCOMPIC_Pos) /*!< LCD INTCLR: VCOMPIC Mask */ -#define LCD_INTCLR_BERIC_Pos 4 /*!< LCD INTCLR: BERIC Position */ -#define LCD_INTCLR_BERIC_Msk (0x01UL << LCD_INTCLR_BERIC_Pos) /*!< LCD INTCLR: BERIC Mask */ - -// --------------------------------------- LCD_UPCURR ------------------------------------------- -#define LCD_UPCURR_LCDUPCURR_Pos 0 /*!< LCD UPCURR: LCDUPCURR Position */ -#define LCD_UPCURR_LCDUPCURR_Msk (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos) /*!< LCD UPCURR: LCDUPCURR Mask */ - -// --------------------------------------- LCD_LPCURR ------------------------------------------- -#define LCD_LPCURR_LCDLPCURR_Pos 0 /*!< LCD LPCURR: LCDLPCURR Position */ -#define LCD_LPCURR_LCDLPCURR_Msk (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos) /*!< LCD LPCURR: LCDLPCURR Mask */ - -// ---------------------------------------- LCD_PAL0 -------------------------------------------- -#define LCD_PAL0_R04_0_Pos 0 /*!< LCD PAL0: R04_0 Position */ -#define LCD_PAL0_R04_0_Msk (0x1fUL << LCD_PAL0_R04_0_Pos) /*!< LCD PAL0: R04_0 Mask */ -#define LCD_PAL0_G04_0_Pos 5 /*!< LCD PAL0: G04_0 Position */ -#define LCD_PAL0_G04_0_Msk (0x1fUL << LCD_PAL0_G04_0_Pos) /*!< LCD PAL0: G04_0 Mask */ -#define LCD_PAL0_B04_0_Pos 10 /*!< LCD PAL0: B04_0 Position */ -#define LCD_PAL0_B04_0_Msk (0x1fUL << LCD_PAL0_B04_0_Pos) /*!< LCD PAL0: B04_0 Mask */ -#define LCD_PAL0_I0_Pos 15 /*!< LCD PAL0: I0 Position */ -#define LCD_PAL0_I0_Msk (0x01UL << LCD_PAL0_I0_Pos) /*!< LCD PAL0: I0 Mask */ -#define LCD_PAL0_R14_0_Pos 16 /*!< LCD PAL0: R14_0 Position */ -#define LCD_PAL0_R14_0_Msk (0x1fUL << LCD_PAL0_R14_0_Pos) /*!< LCD PAL0: R14_0 Mask */ -#define LCD_PAL0_G14_0_Pos 21 /*!< LCD PAL0: G14_0 Position */ -#define LCD_PAL0_G14_0_Msk (0x1fUL << LCD_PAL0_G14_0_Pos) /*!< LCD PAL0: G14_0 Mask */ -#define LCD_PAL0_B14_0_Pos 26 /*!< LCD PAL0: B14_0 Position */ -#define LCD_PAL0_B14_0_Msk (0x1fUL << LCD_PAL0_B14_0_Pos) /*!< LCD PAL0: B14_0 Mask */ -#define LCD_PAL0_I1_Pos 31 /*!< LCD PAL0: I1 Position */ -#define LCD_PAL0_I1_Msk (0x01UL << LCD_PAL0_I1_Pos) /*!< LCD PAL0: I1 Mask */ - -// ---------------------------------------- LCD_PAL1 -------------------------------------------- -#define LCD_PAL1_R04_0_Pos 0 /*!< LCD PAL1: R04_0 Position */ -#define LCD_PAL1_R04_0_Msk (0x1fUL << LCD_PAL1_R04_0_Pos) /*!< LCD PAL1: R04_0 Mask */ -#define LCD_PAL1_G04_0_Pos 5 /*!< LCD PAL1: G04_0 Position */ -#define LCD_PAL1_G04_0_Msk (0x1fUL << LCD_PAL1_G04_0_Pos) /*!< LCD PAL1: G04_0 Mask */ -#define LCD_PAL1_B04_0_Pos 10 /*!< LCD PAL1: B04_0 Position */ -#define LCD_PAL1_B04_0_Msk (0x1fUL << LCD_PAL1_B04_0_Pos) /*!< LCD PAL1: B04_0 Mask */ -#define LCD_PAL1_I0_Pos 15 /*!< LCD PAL1: I0 Position */ -#define LCD_PAL1_I0_Msk (0x01UL << LCD_PAL1_I0_Pos) /*!< LCD PAL1: I0 Mask */ -#define LCD_PAL1_R14_0_Pos 16 /*!< LCD PAL1: R14_0 Position */ -#define LCD_PAL1_R14_0_Msk (0x1fUL << LCD_PAL1_R14_0_Pos) /*!< LCD PAL1: R14_0 Mask */ -#define LCD_PAL1_G14_0_Pos 21 /*!< LCD PAL1: G14_0 Position */ -#define LCD_PAL1_G14_0_Msk (0x1fUL << LCD_PAL1_G14_0_Pos) /*!< LCD PAL1: G14_0 Mask */ -#define LCD_PAL1_B14_0_Pos 26 /*!< LCD PAL1: B14_0 Position */ -#define LCD_PAL1_B14_0_Msk (0x1fUL << LCD_PAL1_B14_0_Pos) /*!< LCD PAL1: B14_0 Mask */ -#define LCD_PAL1_I1_Pos 31 /*!< LCD PAL1: I1 Position */ -#define LCD_PAL1_I1_Msk (0x01UL << LCD_PAL1_I1_Pos) /*!< LCD PAL1: I1 Mask */ - -// ---------------------------------------- LCD_PAL2 -------------------------------------------- -#define LCD_PAL2_R04_0_Pos 0 /*!< LCD PAL2: R04_0 Position */ -#define LCD_PAL2_R04_0_Msk (0x1fUL << LCD_PAL2_R04_0_Pos) /*!< LCD PAL2: R04_0 Mask */ -#define LCD_PAL2_G04_0_Pos 5 /*!< LCD PAL2: G04_0 Position */ -#define LCD_PAL2_G04_0_Msk (0x1fUL << LCD_PAL2_G04_0_Pos) /*!< LCD PAL2: G04_0 Mask */ -#define LCD_PAL2_B04_0_Pos 10 /*!< LCD PAL2: B04_0 Position */ -#define LCD_PAL2_B04_0_Msk (0x1fUL << LCD_PAL2_B04_0_Pos) /*!< LCD PAL2: B04_0 Mask */ -#define LCD_PAL2_I0_Pos 15 /*!< LCD PAL2: I0 Position */ -#define LCD_PAL2_I0_Msk (0x01UL << LCD_PAL2_I0_Pos) /*!< LCD PAL2: I0 Mask */ -#define LCD_PAL2_R14_0_Pos 16 /*!< LCD PAL2: R14_0 Position */ -#define LCD_PAL2_R14_0_Msk (0x1fUL << LCD_PAL2_R14_0_Pos) /*!< LCD PAL2: R14_0 Mask */ -#define LCD_PAL2_G14_0_Pos 21 /*!< LCD PAL2: G14_0 Position */ -#define LCD_PAL2_G14_0_Msk (0x1fUL << LCD_PAL2_G14_0_Pos) /*!< LCD PAL2: G14_0 Mask */ -#define LCD_PAL2_B14_0_Pos 26 /*!< LCD PAL2: B14_0 Position */ -#define LCD_PAL2_B14_0_Msk (0x1fUL << LCD_PAL2_B14_0_Pos) /*!< LCD PAL2: B14_0 Mask */ -#define LCD_PAL2_I1_Pos 31 /*!< LCD PAL2: I1 Position */ -#define LCD_PAL2_I1_Msk (0x01UL << LCD_PAL2_I1_Pos) /*!< LCD PAL2: I1 Mask */ - -// ---------------------------------------- LCD_PAL3 -------------------------------------------- -#define LCD_PAL3_R04_0_Pos 0 /*!< LCD PAL3: R04_0 Position */ -#define LCD_PAL3_R04_0_Msk (0x1fUL << LCD_PAL3_R04_0_Pos) /*!< LCD PAL3: R04_0 Mask */ -#define LCD_PAL3_G04_0_Pos 5 /*!< LCD PAL3: G04_0 Position */ -#define LCD_PAL3_G04_0_Msk (0x1fUL << LCD_PAL3_G04_0_Pos) /*!< LCD PAL3: G04_0 Mask */ -#define LCD_PAL3_B04_0_Pos 10 /*!< LCD PAL3: B04_0 Position */ -#define LCD_PAL3_B04_0_Msk (0x1fUL << LCD_PAL3_B04_0_Pos) /*!< LCD PAL3: B04_0 Mask */ -#define LCD_PAL3_I0_Pos 15 /*!< LCD PAL3: I0 Position */ -#define LCD_PAL3_I0_Msk (0x01UL << LCD_PAL3_I0_Pos) /*!< LCD PAL3: I0 Mask */ -#define LCD_PAL3_R14_0_Pos 16 /*!< LCD PAL3: R14_0 Position */ -#define LCD_PAL3_R14_0_Msk (0x1fUL << LCD_PAL3_R14_0_Pos) /*!< LCD PAL3: R14_0 Mask */ -#define LCD_PAL3_G14_0_Pos 21 /*!< LCD PAL3: G14_0 Position */ -#define LCD_PAL3_G14_0_Msk (0x1fUL << LCD_PAL3_G14_0_Pos) /*!< LCD PAL3: G14_0 Mask */ -#define LCD_PAL3_B14_0_Pos 26 /*!< LCD PAL3: B14_0 Position */ -#define LCD_PAL3_B14_0_Msk (0x1fUL << LCD_PAL3_B14_0_Pos) /*!< LCD PAL3: B14_0 Mask */ -#define LCD_PAL3_I1_Pos 31 /*!< LCD PAL3: I1 Position */ -#define LCD_PAL3_I1_Msk (0x01UL << LCD_PAL3_I1_Pos) /*!< LCD PAL3: I1 Mask */ - -// ---------------------------------------- LCD_PAL4 -------------------------------------------- -#define LCD_PAL4_R04_0_Pos 0 /*!< LCD PAL4: R04_0 Position */ -#define LCD_PAL4_R04_0_Msk (0x1fUL << LCD_PAL4_R04_0_Pos) /*!< LCD PAL4: R04_0 Mask */ -#define LCD_PAL4_G04_0_Pos 5 /*!< LCD PAL4: G04_0 Position */ -#define LCD_PAL4_G04_0_Msk (0x1fUL << LCD_PAL4_G04_0_Pos) /*!< LCD PAL4: G04_0 Mask */ -#define LCD_PAL4_B04_0_Pos 10 /*!< LCD PAL4: B04_0 Position */ -#define LCD_PAL4_B04_0_Msk (0x1fUL << LCD_PAL4_B04_0_Pos) /*!< LCD PAL4: B04_0 Mask */ -#define LCD_PAL4_I0_Pos 15 /*!< LCD PAL4: I0 Position */ -#define LCD_PAL4_I0_Msk (0x01UL << LCD_PAL4_I0_Pos) /*!< LCD PAL4: I0 Mask */ -#define LCD_PAL4_R14_0_Pos 16 /*!< LCD PAL4: R14_0 Position */ -#define LCD_PAL4_R14_0_Msk (0x1fUL << LCD_PAL4_R14_0_Pos) /*!< LCD PAL4: R14_0 Mask */ -#define LCD_PAL4_G14_0_Pos 21 /*!< LCD PAL4: G14_0 Position */ -#define LCD_PAL4_G14_0_Msk (0x1fUL << LCD_PAL4_G14_0_Pos) /*!< LCD PAL4: G14_0 Mask */ -#define LCD_PAL4_B14_0_Pos 26 /*!< LCD PAL4: B14_0 Position */ -#define LCD_PAL4_B14_0_Msk (0x1fUL << LCD_PAL4_B14_0_Pos) /*!< LCD PAL4: B14_0 Mask */ -#define LCD_PAL4_I1_Pos 31 /*!< LCD PAL4: I1 Position */ -#define LCD_PAL4_I1_Msk (0x01UL << LCD_PAL4_I1_Pos) /*!< LCD PAL4: I1 Mask */ - -// ---------------------------------------- LCD_PAL5 -------------------------------------------- -#define LCD_PAL5_R04_0_Pos 0 /*!< LCD PAL5: R04_0 Position */ -#define LCD_PAL5_R04_0_Msk (0x1fUL << LCD_PAL5_R04_0_Pos) /*!< LCD PAL5: R04_0 Mask */ -#define LCD_PAL5_G04_0_Pos 5 /*!< LCD PAL5: G04_0 Position */ -#define LCD_PAL5_G04_0_Msk (0x1fUL << LCD_PAL5_G04_0_Pos) /*!< LCD PAL5: G04_0 Mask */ -#define LCD_PAL5_B04_0_Pos 10 /*!< LCD PAL5: B04_0 Position */ -#define LCD_PAL5_B04_0_Msk (0x1fUL << LCD_PAL5_B04_0_Pos) /*!< LCD PAL5: B04_0 Mask */ -#define LCD_PAL5_I0_Pos 15 /*!< LCD PAL5: I0 Position */ -#define LCD_PAL5_I0_Msk (0x01UL << LCD_PAL5_I0_Pos) /*!< LCD PAL5: I0 Mask */ -#define LCD_PAL5_R14_0_Pos 16 /*!< LCD PAL5: R14_0 Position */ -#define LCD_PAL5_R14_0_Msk (0x1fUL << LCD_PAL5_R14_0_Pos) /*!< LCD PAL5: R14_0 Mask */ -#define LCD_PAL5_G14_0_Pos 21 /*!< LCD PAL5: G14_0 Position */ -#define LCD_PAL5_G14_0_Msk (0x1fUL << LCD_PAL5_G14_0_Pos) /*!< LCD PAL5: G14_0 Mask */ -#define LCD_PAL5_B14_0_Pos 26 /*!< LCD PAL5: B14_0 Position */ -#define LCD_PAL5_B14_0_Msk (0x1fUL << LCD_PAL5_B14_0_Pos) /*!< LCD PAL5: B14_0 Mask */ -#define LCD_PAL5_I1_Pos 31 /*!< LCD PAL5: I1 Position */ -#define LCD_PAL5_I1_Msk (0x01UL << LCD_PAL5_I1_Pos) /*!< LCD PAL5: I1 Mask */ - -// ---------------------------------------- LCD_PAL6 -------------------------------------------- -#define LCD_PAL6_R04_0_Pos 0 /*!< LCD PAL6: R04_0 Position */ -#define LCD_PAL6_R04_0_Msk (0x1fUL << LCD_PAL6_R04_0_Pos) /*!< LCD PAL6: R04_0 Mask */ -#define LCD_PAL6_G04_0_Pos 5 /*!< LCD PAL6: G04_0 Position */ -#define LCD_PAL6_G04_0_Msk (0x1fUL << LCD_PAL6_G04_0_Pos) /*!< LCD PAL6: G04_0 Mask */ -#define LCD_PAL6_B04_0_Pos 10 /*!< LCD PAL6: B04_0 Position */ -#define LCD_PAL6_B04_0_Msk (0x1fUL << LCD_PAL6_B04_0_Pos) /*!< LCD PAL6: B04_0 Mask */ -#define LCD_PAL6_I0_Pos 15 /*!< LCD PAL6: I0 Position */ -#define LCD_PAL6_I0_Msk (0x01UL << LCD_PAL6_I0_Pos) /*!< LCD PAL6: I0 Mask */ -#define LCD_PAL6_R14_0_Pos 16 /*!< LCD PAL6: R14_0 Position */ -#define LCD_PAL6_R14_0_Msk (0x1fUL << LCD_PAL6_R14_0_Pos) /*!< LCD PAL6: R14_0 Mask */ -#define LCD_PAL6_G14_0_Pos 21 /*!< LCD PAL6: G14_0 Position */ -#define LCD_PAL6_G14_0_Msk (0x1fUL << LCD_PAL6_G14_0_Pos) /*!< LCD PAL6: G14_0 Mask */ -#define LCD_PAL6_B14_0_Pos 26 /*!< LCD PAL6: B14_0 Position */ -#define LCD_PAL6_B14_0_Msk (0x1fUL << LCD_PAL6_B14_0_Pos) /*!< LCD PAL6: B14_0 Mask */ -#define LCD_PAL6_I1_Pos 31 /*!< LCD PAL6: I1 Position */ -#define LCD_PAL6_I1_Msk (0x01UL << LCD_PAL6_I1_Pos) /*!< LCD PAL6: I1 Mask */ - -// ---------------------------------------- LCD_PAL7 -------------------------------------------- -#define LCD_PAL7_R04_0_Pos 0 /*!< LCD PAL7: R04_0 Position */ -#define LCD_PAL7_R04_0_Msk (0x1fUL << LCD_PAL7_R04_0_Pos) /*!< LCD PAL7: R04_0 Mask */ -#define LCD_PAL7_G04_0_Pos 5 /*!< LCD PAL7: G04_0 Position */ -#define LCD_PAL7_G04_0_Msk (0x1fUL << LCD_PAL7_G04_0_Pos) /*!< LCD PAL7: G04_0 Mask */ -#define LCD_PAL7_B04_0_Pos 10 /*!< LCD PAL7: B04_0 Position */ -#define LCD_PAL7_B04_0_Msk (0x1fUL << LCD_PAL7_B04_0_Pos) /*!< LCD PAL7: B04_0 Mask */ -#define LCD_PAL7_I0_Pos 15 /*!< LCD PAL7: I0 Position */ -#define LCD_PAL7_I0_Msk (0x01UL << LCD_PAL7_I0_Pos) /*!< LCD PAL7: I0 Mask */ -#define LCD_PAL7_R14_0_Pos 16 /*!< LCD PAL7: R14_0 Position */ -#define LCD_PAL7_R14_0_Msk (0x1fUL << LCD_PAL7_R14_0_Pos) /*!< LCD PAL7: R14_0 Mask */ -#define LCD_PAL7_G14_0_Pos 21 /*!< LCD PAL7: G14_0 Position */ -#define LCD_PAL7_G14_0_Msk (0x1fUL << LCD_PAL7_G14_0_Pos) /*!< LCD PAL7: G14_0 Mask */ -#define LCD_PAL7_B14_0_Pos 26 /*!< LCD PAL7: B14_0 Position */ -#define LCD_PAL7_B14_0_Msk (0x1fUL << LCD_PAL7_B14_0_Pos) /*!< LCD PAL7: B14_0 Mask */ -#define LCD_PAL7_I1_Pos 31 /*!< LCD PAL7: I1 Position */ -#define LCD_PAL7_I1_Msk (0x01UL << LCD_PAL7_I1_Pos) /*!< LCD PAL7: I1 Mask */ - -// ---------------------------------------- LCD_PAL8 -------------------------------------------- -#define LCD_PAL8_R04_0_Pos 0 /*!< LCD PAL8: R04_0 Position */ -#define LCD_PAL8_R04_0_Msk (0x1fUL << LCD_PAL8_R04_0_Pos) /*!< LCD PAL8: R04_0 Mask */ -#define LCD_PAL8_G04_0_Pos 5 /*!< LCD PAL8: G04_0 Position */ -#define LCD_PAL8_G04_0_Msk (0x1fUL << LCD_PAL8_G04_0_Pos) /*!< LCD PAL8: G04_0 Mask */ -#define LCD_PAL8_B04_0_Pos 10 /*!< LCD PAL8: B04_0 Position */ -#define LCD_PAL8_B04_0_Msk (0x1fUL << LCD_PAL8_B04_0_Pos) /*!< LCD PAL8: B04_0 Mask */ -#define LCD_PAL8_I0_Pos 15 /*!< LCD PAL8: I0 Position */ -#define LCD_PAL8_I0_Msk (0x01UL << LCD_PAL8_I0_Pos) /*!< LCD PAL8: I0 Mask */ -#define LCD_PAL8_R14_0_Pos 16 /*!< LCD PAL8: R14_0 Position */ -#define LCD_PAL8_R14_0_Msk (0x1fUL << LCD_PAL8_R14_0_Pos) /*!< LCD PAL8: R14_0 Mask */ -#define LCD_PAL8_G14_0_Pos 21 /*!< LCD PAL8: G14_0 Position */ -#define LCD_PAL8_G14_0_Msk (0x1fUL << LCD_PAL8_G14_0_Pos) /*!< LCD PAL8: G14_0 Mask */ -#define LCD_PAL8_B14_0_Pos 26 /*!< LCD PAL8: B14_0 Position */ -#define LCD_PAL8_B14_0_Msk (0x1fUL << LCD_PAL8_B14_0_Pos) /*!< LCD PAL8: B14_0 Mask */ -#define LCD_PAL8_I1_Pos 31 /*!< LCD PAL8: I1 Position */ -#define LCD_PAL8_I1_Msk (0x01UL << LCD_PAL8_I1_Pos) /*!< LCD PAL8: I1 Mask */ - -// ---------------------------------------- LCD_PAL9 -------------------------------------------- -#define LCD_PAL9_R04_0_Pos 0 /*!< LCD PAL9: R04_0 Position */ -#define LCD_PAL9_R04_0_Msk (0x1fUL << LCD_PAL9_R04_0_Pos) /*!< LCD PAL9: R04_0 Mask */ -#define LCD_PAL9_G04_0_Pos 5 /*!< LCD PAL9: G04_0 Position */ -#define LCD_PAL9_G04_0_Msk (0x1fUL << LCD_PAL9_G04_0_Pos) /*!< LCD PAL9: G04_0 Mask */ -#define LCD_PAL9_B04_0_Pos 10 /*!< LCD PAL9: B04_0 Position */ -#define LCD_PAL9_B04_0_Msk (0x1fUL << LCD_PAL9_B04_0_Pos) /*!< LCD PAL9: B04_0 Mask */ -#define LCD_PAL9_I0_Pos 15 /*!< LCD PAL9: I0 Position */ -#define LCD_PAL9_I0_Msk (0x01UL << LCD_PAL9_I0_Pos) /*!< LCD PAL9: I0 Mask */ -#define LCD_PAL9_R14_0_Pos 16 /*!< LCD PAL9: R14_0 Position */ -#define LCD_PAL9_R14_0_Msk (0x1fUL << LCD_PAL9_R14_0_Pos) /*!< LCD PAL9: R14_0 Mask */ -#define LCD_PAL9_G14_0_Pos 21 /*!< LCD PAL9: G14_0 Position */ -#define LCD_PAL9_G14_0_Msk (0x1fUL << LCD_PAL9_G14_0_Pos) /*!< LCD PAL9: G14_0 Mask */ -#define LCD_PAL9_B14_0_Pos 26 /*!< LCD PAL9: B14_0 Position */ -#define LCD_PAL9_B14_0_Msk (0x1fUL << LCD_PAL9_B14_0_Pos) /*!< LCD PAL9: B14_0 Mask */ -#define LCD_PAL9_I1_Pos 31 /*!< LCD PAL9: I1 Position */ -#define LCD_PAL9_I1_Msk (0x01UL << LCD_PAL9_I1_Pos) /*!< LCD PAL9: I1 Mask */ - -// ---------------------------------------- LCD_PAL10 ------------------------------------------- -#define LCD_PAL10_R04_0_Pos 0 /*!< LCD PAL10: R04_0 Position */ -#define LCD_PAL10_R04_0_Msk (0x1fUL << LCD_PAL10_R04_0_Pos) /*!< LCD PAL10: R04_0 Mask */ -#define LCD_PAL10_G04_0_Pos 5 /*!< LCD PAL10: G04_0 Position */ -#define LCD_PAL10_G04_0_Msk (0x1fUL << LCD_PAL10_G04_0_Pos) /*!< LCD PAL10: G04_0 Mask */ -#define LCD_PAL10_B04_0_Pos 10 /*!< LCD PAL10: B04_0 Position */ -#define LCD_PAL10_B04_0_Msk (0x1fUL << LCD_PAL10_B04_0_Pos) /*!< LCD PAL10: B04_0 Mask */ -#define LCD_PAL10_I0_Pos 15 /*!< LCD PAL10: I0 Position */ -#define LCD_PAL10_I0_Msk (0x01UL << LCD_PAL10_I0_Pos) /*!< LCD PAL10: I0 Mask */ -#define LCD_PAL10_R14_0_Pos 16 /*!< LCD PAL10: R14_0 Position */ -#define LCD_PAL10_R14_0_Msk (0x1fUL << LCD_PAL10_R14_0_Pos) /*!< LCD PAL10: R14_0 Mask */ -#define LCD_PAL10_G14_0_Pos 21 /*!< LCD PAL10: G14_0 Position */ -#define LCD_PAL10_G14_0_Msk (0x1fUL << LCD_PAL10_G14_0_Pos) /*!< LCD PAL10: G14_0 Mask */ -#define LCD_PAL10_B14_0_Pos 26 /*!< LCD PAL10: B14_0 Position */ -#define LCD_PAL10_B14_0_Msk (0x1fUL << LCD_PAL10_B14_0_Pos) /*!< LCD PAL10: B14_0 Mask */ -#define LCD_PAL10_I1_Pos 31 /*!< LCD PAL10: I1 Position */ -#define LCD_PAL10_I1_Msk (0x01UL << LCD_PAL10_I1_Pos) /*!< LCD PAL10: I1 Mask */ - -// ---------------------------------------- LCD_PAL11 ------------------------------------------- -#define LCD_PAL11_R04_0_Pos 0 /*!< LCD PAL11: R04_0 Position */ -#define LCD_PAL11_R04_0_Msk (0x1fUL << LCD_PAL11_R04_0_Pos) /*!< LCD PAL11: R04_0 Mask */ -#define LCD_PAL11_G04_0_Pos 5 /*!< LCD PAL11: G04_0 Position */ -#define LCD_PAL11_G04_0_Msk (0x1fUL << LCD_PAL11_G04_0_Pos) /*!< LCD PAL11: G04_0 Mask */ -#define LCD_PAL11_B04_0_Pos 10 /*!< LCD PAL11: B04_0 Position */ -#define LCD_PAL11_B04_0_Msk (0x1fUL << LCD_PAL11_B04_0_Pos) /*!< LCD PAL11: B04_0 Mask */ -#define LCD_PAL11_I0_Pos 15 /*!< LCD PAL11: I0 Position */ -#define LCD_PAL11_I0_Msk (0x01UL << LCD_PAL11_I0_Pos) /*!< LCD PAL11: I0 Mask */ -#define LCD_PAL11_R14_0_Pos 16 /*!< LCD PAL11: R14_0 Position */ -#define LCD_PAL11_R14_0_Msk (0x1fUL << LCD_PAL11_R14_0_Pos) /*!< LCD PAL11: R14_0 Mask */ -#define LCD_PAL11_G14_0_Pos 21 /*!< LCD PAL11: G14_0 Position */ -#define LCD_PAL11_G14_0_Msk (0x1fUL << LCD_PAL11_G14_0_Pos) /*!< LCD PAL11: G14_0 Mask */ -#define LCD_PAL11_B14_0_Pos 26 /*!< LCD PAL11: B14_0 Position */ -#define LCD_PAL11_B14_0_Msk (0x1fUL << LCD_PAL11_B14_0_Pos) /*!< LCD PAL11: B14_0 Mask */ -#define LCD_PAL11_I1_Pos 31 /*!< LCD PAL11: I1 Position */ -#define LCD_PAL11_I1_Msk (0x01UL << LCD_PAL11_I1_Pos) /*!< LCD PAL11: I1 Mask */ - -// ---------------------------------------- LCD_PAL12 ------------------------------------------- -#define LCD_PAL12_R04_0_Pos 0 /*!< LCD PAL12: R04_0 Position */ -#define LCD_PAL12_R04_0_Msk (0x1fUL << LCD_PAL12_R04_0_Pos) /*!< LCD PAL12: R04_0 Mask */ -#define LCD_PAL12_G04_0_Pos 5 /*!< LCD PAL12: G04_0 Position */ -#define LCD_PAL12_G04_0_Msk (0x1fUL << LCD_PAL12_G04_0_Pos) /*!< LCD PAL12: G04_0 Mask */ -#define LCD_PAL12_B04_0_Pos 10 /*!< LCD PAL12: B04_0 Position */ -#define LCD_PAL12_B04_0_Msk (0x1fUL << LCD_PAL12_B04_0_Pos) /*!< LCD PAL12: B04_0 Mask */ -#define LCD_PAL12_I0_Pos 15 /*!< LCD PAL12: I0 Position */ -#define LCD_PAL12_I0_Msk (0x01UL << LCD_PAL12_I0_Pos) /*!< LCD PAL12: I0 Mask */ -#define LCD_PAL12_R14_0_Pos 16 /*!< LCD PAL12: R14_0 Position */ -#define LCD_PAL12_R14_0_Msk (0x1fUL << LCD_PAL12_R14_0_Pos) /*!< LCD PAL12: R14_0 Mask */ -#define LCD_PAL12_G14_0_Pos 21 /*!< LCD PAL12: G14_0 Position */ -#define LCD_PAL12_G14_0_Msk (0x1fUL << LCD_PAL12_G14_0_Pos) /*!< LCD PAL12: G14_0 Mask */ -#define LCD_PAL12_B14_0_Pos 26 /*!< LCD PAL12: B14_0 Position */ -#define LCD_PAL12_B14_0_Msk (0x1fUL << LCD_PAL12_B14_0_Pos) /*!< LCD PAL12: B14_0 Mask */ -#define LCD_PAL12_I1_Pos 31 /*!< LCD PAL12: I1 Position */ -#define LCD_PAL12_I1_Msk (0x01UL << LCD_PAL12_I1_Pos) /*!< LCD PAL12: I1 Mask */ - -// ---------------------------------------- LCD_PAL13 ------------------------------------------- -#define LCD_PAL13_R04_0_Pos 0 /*!< LCD PAL13: R04_0 Position */ -#define LCD_PAL13_R04_0_Msk (0x1fUL << LCD_PAL13_R04_0_Pos) /*!< LCD PAL13: R04_0 Mask */ -#define LCD_PAL13_G04_0_Pos 5 /*!< LCD PAL13: G04_0 Position */ -#define LCD_PAL13_G04_0_Msk (0x1fUL << LCD_PAL13_G04_0_Pos) /*!< LCD PAL13: G04_0 Mask */ -#define LCD_PAL13_B04_0_Pos 10 /*!< LCD PAL13: B04_0 Position */ -#define LCD_PAL13_B04_0_Msk (0x1fUL << LCD_PAL13_B04_0_Pos) /*!< LCD PAL13: B04_0 Mask */ -#define LCD_PAL13_I0_Pos 15 /*!< LCD PAL13: I0 Position */ -#define LCD_PAL13_I0_Msk (0x01UL << LCD_PAL13_I0_Pos) /*!< LCD PAL13: I0 Mask */ -#define LCD_PAL13_R14_0_Pos 16 /*!< LCD PAL13: R14_0 Position */ -#define LCD_PAL13_R14_0_Msk (0x1fUL << LCD_PAL13_R14_0_Pos) /*!< LCD PAL13: R14_0 Mask */ -#define LCD_PAL13_G14_0_Pos 21 /*!< LCD PAL13: G14_0 Position */ -#define LCD_PAL13_G14_0_Msk (0x1fUL << LCD_PAL13_G14_0_Pos) /*!< LCD PAL13: G14_0 Mask */ -#define LCD_PAL13_B14_0_Pos 26 /*!< LCD PAL13: B14_0 Position */ -#define LCD_PAL13_B14_0_Msk (0x1fUL << LCD_PAL13_B14_0_Pos) /*!< LCD PAL13: B14_0 Mask */ -#define LCD_PAL13_I1_Pos 31 /*!< LCD PAL13: I1 Position */ -#define LCD_PAL13_I1_Msk (0x01UL << LCD_PAL13_I1_Pos) /*!< LCD PAL13: I1 Mask */ - -// ---------------------------------------- LCD_PAL14 ------------------------------------------- -#define LCD_PAL14_R04_0_Pos 0 /*!< LCD PAL14: R04_0 Position */ -#define LCD_PAL14_R04_0_Msk (0x1fUL << LCD_PAL14_R04_0_Pos) /*!< LCD PAL14: R04_0 Mask */ -#define LCD_PAL14_G04_0_Pos 5 /*!< LCD PAL14: G04_0 Position */ -#define LCD_PAL14_G04_0_Msk (0x1fUL << LCD_PAL14_G04_0_Pos) /*!< LCD PAL14: G04_0 Mask */ -#define LCD_PAL14_B04_0_Pos 10 /*!< LCD PAL14: B04_0 Position */ -#define LCD_PAL14_B04_0_Msk (0x1fUL << LCD_PAL14_B04_0_Pos) /*!< LCD PAL14: B04_0 Mask */ -#define LCD_PAL14_I0_Pos 15 /*!< LCD PAL14: I0 Position */ -#define LCD_PAL14_I0_Msk (0x01UL << LCD_PAL14_I0_Pos) /*!< LCD PAL14: I0 Mask */ -#define LCD_PAL14_R14_0_Pos 16 /*!< LCD PAL14: R14_0 Position */ -#define LCD_PAL14_R14_0_Msk (0x1fUL << LCD_PAL14_R14_0_Pos) /*!< LCD PAL14: R14_0 Mask */ -#define LCD_PAL14_G14_0_Pos 21 /*!< LCD PAL14: G14_0 Position */ -#define LCD_PAL14_G14_0_Msk (0x1fUL << LCD_PAL14_G14_0_Pos) /*!< LCD PAL14: G14_0 Mask */ -#define LCD_PAL14_B14_0_Pos 26 /*!< LCD PAL14: B14_0 Position */ -#define LCD_PAL14_B14_0_Msk (0x1fUL << LCD_PAL14_B14_0_Pos) /*!< LCD PAL14: B14_0 Mask */ -#define LCD_PAL14_I1_Pos 31 /*!< LCD PAL14: I1 Position */ -#define LCD_PAL14_I1_Msk (0x01UL << LCD_PAL14_I1_Pos) /*!< LCD PAL14: I1 Mask */ - -// ---------------------------------------- LCD_PAL15 ------------------------------------------- -#define LCD_PAL15_R04_0_Pos 0 /*!< LCD PAL15: R04_0 Position */ -#define LCD_PAL15_R04_0_Msk (0x1fUL << LCD_PAL15_R04_0_Pos) /*!< LCD PAL15: R04_0 Mask */ -#define LCD_PAL15_G04_0_Pos 5 /*!< LCD PAL15: G04_0 Position */ -#define LCD_PAL15_G04_0_Msk (0x1fUL << LCD_PAL15_G04_0_Pos) /*!< LCD PAL15: G04_0 Mask */ -#define LCD_PAL15_B04_0_Pos 10 /*!< LCD PAL15: B04_0 Position */ -#define LCD_PAL15_B04_0_Msk (0x1fUL << LCD_PAL15_B04_0_Pos) /*!< LCD PAL15: B04_0 Mask */ -#define LCD_PAL15_I0_Pos 15 /*!< LCD PAL15: I0 Position */ -#define LCD_PAL15_I0_Msk (0x01UL << LCD_PAL15_I0_Pos) /*!< LCD PAL15: I0 Mask */ -#define LCD_PAL15_R14_0_Pos 16 /*!< LCD PAL15: R14_0 Position */ -#define LCD_PAL15_R14_0_Msk (0x1fUL << LCD_PAL15_R14_0_Pos) /*!< LCD PAL15: R14_0 Mask */ -#define LCD_PAL15_G14_0_Pos 21 /*!< LCD PAL15: G14_0 Position */ -#define LCD_PAL15_G14_0_Msk (0x1fUL << LCD_PAL15_G14_0_Pos) /*!< LCD PAL15: G14_0 Mask */ -#define LCD_PAL15_B14_0_Pos 26 /*!< LCD PAL15: B14_0 Position */ -#define LCD_PAL15_B14_0_Msk (0x1fUL << LCD_PAL15_B14_0_Pos) /*!< LCD PAL15: B14_0 Mask */ -#define LCD_PAL15_I1_Pos 31 /*!< LCD PAL15: I1 Position */ -#define LCD_PAL15_I1_Msk (0x01UL << LCD_PAL15_I1_Pos) /*!< LCD PAL15: I1 Mask */ - -// ---------------------------------------- LCD_PAL16 ------------------------------------------- -#define LCD_PAL16_R04_0_Pos 0 /*!< LCD PAL16: R04_0 Position */ -#define LCD_PAL16_R04_0_Msk (0x1fUL << LCD_PAL16_R04_0_Pos) /*!< LCD PAL16: R04_0 Mask */ -#define LCD_PAL16_G04_0_Pos 5 /*!< LCD PAL16: G04_0 Position */ -#define LCD_PAL16_G04_0_Msk (0x1fUL << LCD_PAL16_G04_0_Pos) /*!< LCD PAL16: G04_0 Mask */ -#define LCD_PAL16_B04_0_Pos 10 /*!< LCD PAL16: B04_0 Position */ -#define LCD_PAL16_B04_0_Msk (0x1fUL << LCD_PAL16_B04_0_Pos) /*!< LCD PAL16: B04_0 Mask */ -#define LCD_PAL16_I0_Pos 15 /*!< LCD PAL16: I0 Position */ -#define LCD_PAL16_I0_Msk (0x01UL << LCD_PAL16_I0_Pos) /*!< LCD PAL16: I0 Mask */ -#define LCD_PAL16_R14_0_Pos 16 /*!< LCD PAL16: R14_0 Position */ -#define LCD_PAL16_R14_0_Msk (0x1fUL << LCD_PAL16_R14_0_Pos) /*!< LCD PAL16: R14_0 Mask */ -#define LCD_PAL16_G14_0_Pos 21 /*!< LCD PAL16: G14_0 Position */ -#define LCD_PAL16_G14_0_Msk (0x1fUL << LCD_PAL16_G14_0_Pos) /*!< LCD PAL16: G14_0 Mask */ -#define LCD_PAL16_B14_0_Pos 26 /*!< LCD PAL16: B14_0 Position */ -#define LCD_PAL16_B14_0_Msk (0x1fUL << LCD_PAL16_B14_0_Pos) /*!< LCD PAL16: B14_0 Mask */ -#define LCD_PAL16_I1_Pos 31 /*!< LCD PAL16: I1 Position */ -#define LCD_PAL16_I1_Msk (0x01UL << LCD_PAL16_I1_Pos) /*!< LCD PAL16: I1 Mask */ - -// ---------------------------------------- LCD_PAL17 ------------------------------------------- -#define LCD_PAL17_R04_0_Pos 0 /*!< LCD PAL17: R04_0 Position */ -#define LCD_PAL17_R04_0_Msk (0x1fUL << LCD_PAL17_R04_0_Pos) /*!< LCD PAL17: R04_0 Mask */ -#define LCD_PAL17_G04_0_Pos 5 /*!< LCD PAL17: G04_0 Position */ -#define LCD_PAL17_G04_0_Msk (0x1fUL << LCD_PAL17_G04_0_Pos) /*!< LCD PAL17: G04_0 Mask */ -#define LCD_PAL17_B04_0_Pos 10 /*!< LCD PAL17: B04_0 Position */ -#define LCD_PAL17_B04_0_Msk (0x1fUL << LCD_PAL17_B04_0_Pos) /*!< LCD PAL17: B04_0 Mask */ -#define LCD_PAL17_I0_Pos 15 /*!< LCD PAL17: I0 Position */ -#define LCD_PAL17_I0_Msk (0x01UL << LCD_PAL17_I0_Pos) /*!< LCD PAL17: I0 Mask */ -#define LCD_PAL17_R14_0_Pos 16 /*!< LCD PAL17: R14_0 Position */ -#define LCD_PAL17_R14_0_Msk (0x1fUL << LCD_PAL17_R14_0_Pos) /*!< LCD PAL17: R14_0 Mask */ -#define LCD_PAL17_G14_0_Pos 21 /*!< LCD PAL17: G14_0 Position */ -#define LCD_PAL17_G14_0_Msk (0x1fUL << LCD_PAL17_G14_0_Pos) /*!< LCD PAL17: G14_0 Mask */ -#define LCD_PAL17_B14_0_Pos 26 /*!< LCD PAL17: B14_0 Position */ -#define LCD_PAL17_B14_0_Msk (0x1fUL << LCD_PAL17_B14_0_Pos) /*!< LCD PAL17: B14_0 Mask */ -#define LCD_PAL17_I1_Pos 31 /*!< LCD PAL17: I1 Position */ -#define LCD_PAL17_I1_Msk (0x01UL << LCD_PAL17_I1_Pos) /*!< LCD PAL17: I1 Mask */ - -// ---------------------------------------- LCD_PAL18 ------------------------------------------- -#define LCD_PAL18_R04_0_Pos 0 /*!< LCD PAL18: R04_0 Position */ -#define LCD_PAL18_R04_0_Msk (0x1fUL << LCD_PAL18_R04_0_Pos) /*!< LCD PAL18: R04_0 Mask */ -#define LCD_PAL18_G04_0_Pos 5 /*!< LCD PAL18: G04_0 Position */ -#define LCD_PAL18_G04_0_Msk (0x1fUL << LCD_PAL18_G04_0_Pos) /*!< LCD PAL18: G04_0 Mask */ -#define LCD_PAL18_B04_0_Pos 10 /*!< LCD PAL18: B04_0 Position */ -#define LCD_PAL18_B04_0_Msk (0x1fUL << LCD_PAL18_B04_0_Pos) /*!< LCD PAL18: B04_0 Mask */ -#define LCD_PAL18_I0_Pos 15 /*!< LCD PAL18: I0 Position */ -#define LCD_PAL18_I0_Msk (0x01UL << LCD_PAL18_I0_Pos) /*!< LCD PAL18: I0 Mask */ -#define LCD_PAL18_R14_0_Pos 16 /*!< LCD PAL18: R14_0 Position */ -#define LCD_PAL18_R14_0_Msk (0x1fUL << LCD_PAL18_R14_0_Pos) /*!< LCD PAL18: R14_0 Mask */ -#define LCD_PAL18_G14_0_Pos 21 /*!< LCD PAL18: G14_0 Position */ -#define LCD_PAL18_G14_0_Msk (0x1fUL << LCD_PAL18_G14_0_Pos) /*!< LCD PAL18: G14_0 Mask */ -#define LCD_PAL18_B14_0_Pos 26 /*!< LCD PAL18: B14_0 Position */ -#define LCD_PAL18_B14_0_Msk (0x1fUL << LCD_PAL18_B14_0_Pos) /*!< LCD PAL18: B14_0 Mask */ -#define LCD_PAL18_I1_Pos 31 /*!< LCD PAL18: I1 Position */ -#define LCD_PAL18_I1_Msk (0x01UL << LCD_PAL18_I1_Pos) /*!< LCD PAL18: I1 Mask */ - -// ---------------------------------------- LCD_PAL19 ------------------------------------------- -#define LCD_PAL19_R04_0_Pos 0 /*!< LCD PAL19: R04_0 Position */ -#define LCD_PAL19_R04_0_Msk (0x1fUL << LCD_PAL19_R04_0_Pos) /*!< LCD PAL19: R04_0 Mask */ -#define LCD_PAL19_G04_0_Pos 5 /*!< LCD PAL19: G04_0 Position */ -#define LCD_PAL19_G04_0_Msk (0x1fUL << LCD_PAL19_G04_0_Pos) /*!< LCD PAL19: G04_0 Mask */ -#define LCD_PAL19_B04_0_Pos 10 /*!< LCD PAL19: B04_0 Position */ -#define LCD_PAL19_B04_0_Msk (0x1fUL << LCD_PAL19_B04_0_Pos) /*!< LCD PAL19: B04_0 Mask */ -#define LCD_PAL19_I0_Pos 15 /*!< LCD PAL19: I0 Position */ -#define LCD_PAL19_I0_Msk (0x01UL << LCD_PAL19_I0_Pos) /*!< LCD PAL19: I0 Mask */ -#define LCD_PAL19_R14_0_Pos 16 /*!< LCD PAL19: R14_0 Position */ -#define LCD_PAL19_R14_0_Msk (0x1fUL << LCD_PAL19_R14_0_Pos) /*!< LCD PAL19: R14_0 Mask */ -#define LCD_PAL19_G14_0_Pos 21 /*!< LCD PAL19: G14_0 Position */ -#define LCD_PAL19_G14_0_Msk (0x1fUL << LCD_PAL19_G14_0_Pos) /*!< LCD PAL19: G14_0 Mask */ -#define LCD_PAL19_B14_0_Pos 26 /*!< LCD PAL19: B14_0 Position */ -#define LCD_PAL19_B14_0_Msk (0x1fUL << LCD_PAL19_B14_0_Pos) /*!< LCD PAL19: B14_0 Mask */ -#define LCD_PAL19_I1_Pos 31 /*!< LCD PAL19: I1 Position */ -#define LCD_PAL19_I1_Msk (0x01UL << LCD_PAL19_I1_Pos) /*!< LCD PAL19: I1 Mask */ - -// ---------------------------------------- LCD_PAL20 ------------------------------------------- -#define LCD_PAL20_R04_0_Pos 0 /*!< LCD PAL20: R04_0 Position */ -#define LCD_PAL20_R04_0_Msk (0x1fUL << LCD_PAL20_R04_0_Pos) /*!< LCD PAL20: R04_0 Mask */ -#define LCD_PAL20_G04_0_Pos 5 /*!< LCD PAL20: G04_0 Position */ -#define LCD_PAL20_G04_0_Msk (0x1fUL << LCD_PAL20_G04_0_Pos) /*!< LCD PAL20: G04_0 Mask */ -#define LCD_PAL20_B04_0_Pos 10 /*!< LCD PAL20: B04_0 Position */ -#define LCD_PAL20_B04_0_Msk (0x1fUL << LCD_PAL20_B04_0_Pos) /*!< LCD PAL20: B04_0 Mask */ -#define LCD_PAL20_I0_Pos 15 /*!< LCD PAL20: I0 Position */ -#define LCD_PAL20_I0_Msk (0x01UL << LCD_PAL20_I0_Pos) /*!< LCD PAL20: I0 Mask */ -#define LCD_PAL20_R14_0_Pos 16 /*!< LCD PAL20: R14_0 Position */ -#define LCD_PAL20_R14_0_Msk (0x1fUL << LCD_PAL20_R14_0_Pos) /*!< LCD PAL20: R14_0 Mask */ -#define LCD_PAL20_G14_0_Pos 21 /*!< LCD PAL20: G14_0 Position */ -#define LCD_PAL20_G14_0_Msk (0x1fUL << LCD_PAL20_G14_0_Pos) /*!< LCD PAL20: G14_0 Mask */ -#define LCD_PAL20_B14_0_Pos 26 /*!< LCD PAL20: B14_0 Position */ -#define LCD_PAL20_B14_0_Msk (0x1fUL << LCD_PAL20_B14_0_Pos) /*!< LCD PAL20: B14_0 Mask */ -#define LCD_PAL20_I1_Pos 31 /*!< LCD PAL20: I1 Position */ -#define LCD_PAL20_I1_Msk (0x01UL << LCD_PAL20_I1_Pos) /*!< LCD PAL20: I1 Mask */ - -// ---------------------------------------- LCD_PAL21 ------------------------------------------- -#define LCD_PAL21_R04_0_Pos 0 /*!< LCD PAL21: R04_0 Position */ -#define LCD_PAL21_R04_0_Msk (0x1fUL << LCD_PAL21_R04_0_Pos) /*!< LCD PAL21: R04_0 Mask */ -#define LCD_PAL21_G04_0_Pos 5 /*!< LCD PAL21: G04_0 Position */ -#define LCD_PAL21_G04_0_Msk (0x1fUL << LCD_PAL21_G04_0_Pos) /*!< LCD PAL21: G04_0 Mask */ -#define LCD_PAL21_B04_0_Pos 10 /*!< LCD PAL21: B04_0 Position */ -#define LCD_PAL21_B04_0_Msk (0x1fUL << LCD_PAL21_B04_0_Pos) /*!< LCD PAL21: B04_0 Mask */ -#define LCD_PAL21_I0_Pos 15 /*!< LCD PAL21: I0 Position */ -#define LCD_PAL21_I0_Msk (0x01UL << LCD_PAL21_I0_Pos) /*!< LCD PAL21: I0 Mask */ -#define LCD_PAL21_R14_0_Pos 16 /*!< LCD PAL21: R14_0 Position */ -#define LCD_PAL21_R14_0_Msk (0x1fUL << LCD_PAL21_R14_0_Pos) /*!< LCD PAL21: R14_0 Mask */ -#define LCD_PAL21_G14_0_Pos 21 /*!< LCD PAL21: G14_0 Position */ -#define LCD_PAL21_G14_0_Msk (0x1fUL << LCD_PAL21_G14_0_Pos) /*!< LCD PAL21: G14_0 Mask */ -#define LCD_PAL21_B14_0_Pos 26 /*!< LCD PAL21: B14_0 Position */ -#define LCD_PAL21_B14_0_Msk (0x1fUL << LCD_PAL21_B14_0_Pos) /*!< LCD PAL21: B14_0 Mask */ -#define LCD_PAL21_I1_Pos 31 /*!< LCD PAL21: I1 Position */ -#define LCD_PAL21_I1_Msk (0x01UL << LCD_PAL21_I1_Pos) /*!< LCD PAL21: I1 Mask */ - -// ---------------------------------------- LCD_PAL22 ------------------------------------------- -#define LCD_PAL22_R04_0_Pos 0 /*!< LCD PAL22: R04_0 Position */ -#define LCD_PAL22_R04_0_Msk (0x1fUL << LCD_PAL22_R04_0_Pos) /*!< LCD PAL22: R04_0 Mask */ -#define LCD_PAL22_G04_0_Pos 5 /*!< LCD PAL22: G04_0 Position */ -#define LCD_PAL22_G04_0_Msk (0x1fUL << LCD_PAL22_G04_0_Pos) /*!< LCD PAL22: G04_0 Mask */ -#define LCD_PAL22_B04_0_Pos 10 /*!< LCD PAL22: B04_0 Position */ -#define LCD_PAL22_B04_0_Msk (0x1fUL << LCD_PAL22_B04_0_Pos) /*!< LCD PAL22: B04_0 Mask */ -#define LCD_PAL22_I0_Pos 15 /*!< LCD PAL22: I0 Position */ -#define LCD_PAL22_I0_Msk (0x01UL << LCD_PAL22_I0_Pos) /*!< LCD PAL22: I0 Mask */ -#define LCD_PAL22_R14_0_Pos 16 /*!< LCD PAL22: R14_0 Position */ -#define LCD_PAL22_R14_0_Msk (0x1fUL << LCD_PAL22_R14_0_Pos) /*!< LCD PAL22: R14_0 Mask */ -#define LCD_PAL22_G14_0_Pos 21 /*!< LCD PAL22: G14_0 Position */ -#define LCD_PAL22_G14_0_Msk (0x1fUL << LCD_PAL22_G14_0_Pos) /*!< LCD PAL22: G14_0 Mask */ -#define LCD_PAL22_B14_0_Pos 26 /*!< LCD PAL22: B14_0 Position */ -#define LCD_PAL22_B14_0_Msk (0x1fUL << LCD_PAL22_B14_0_Pos) /*!< LCD PAL22: B14_0 Mask */ -#define LCD_PAL22_I1_Pos 31 /*!< LCD PAL22: I1 Position */ -#define LCD_PAL22_I1_Msk (0x01UL << LCD_PAL22_I1_Pos) /*!< LCD PAL22: I1 Mask */ - -// ---------------------------------------- LCD_PAL23 ------------------------------------------- -#define LCD_PAL23_R04_0_Pos 0 /*!< LCD PAL23: R04_0 Position */ -#define LCD_PAL23_R04_0_Msk (0x1fUL << LCD_PAL23_R04_0_Pos) /*!< LCD PAL23: R04_0 Mask */ -#define LCD_PAL23_G04_0_Pos 5 /*!< LCD PAL23: G04_0 Position */ -#define LCD_PAL23_G04_0_Msk (0x1fUL << LCD_PAL23_G04_0_Pos) /*!< LCD PAL23: G04_0 Mask */ -#define LCD_PAL23_B04_0_Pos 10 /*!< LCD PAL23: B04_0 Position */ -#define LCD_PAL23_B04_0_Msk (0x1fUL << LCD_PAL23_B04_0_Pos) /*!< LCD PAL23: B04_0 Mask */ -#define LCD_PAL23_I0_Pos 15 /*!< LCD PAL23: I0 Position */ -#define LCD_PAL23_I0_Msk (0x01UL << LCD_PAL23_I0_Pos) /*!< LCD PAL23: I0 Mask */ -#define LCD_PAL23_R14_0_Pos 16 /*!< LCD PAL23: R14_0 Position */ -#define LCD_PAL23_R14_0_Msk (0x1fUL << LCD_PAL23_R14_0_Pos) /*!< LCD PAL23: R14_0 Mask */ -#define LCD_PAL23_G14_0_Pos 21 /*!< LCD PAL23: G14_0 Position */ -#define LCD_PAL23_G14_0_Msk (0x1fUL << LCD_PAL23_G14_0_Pos) /*!< LCD PAL23: G14_0 Mask */ -#define LCD_PAL23_B14_0_Pos 26 /*!< LCD PAL23: B14_0 Position */ -#define LCD_PAL23_B14_0_Msk (0x1fUL << LCD_PAL23_B14_0_Pos) /*!< LCD PAL23: B14_0 Mask */ -#define LCD_PAL23_I1_Pos 31 /*!< LCD PAL23: I1 Position */ -#define LCD_PAL23_I1_Msk (0x01UL << LCD_PAL23_I1_Pos) /*!< LCD PAL23: I1 Mask */ - -// ---------------------------------------- LCD_PAL24 ------------------------------------------- -#define LCD_PAL24_R04_0_Pos 0 /*!< LCD PAL24: R04_0 Position */ -#define LCD_PAL24_R04_0_Msk (0x1fUL << LCD_PAL24_R04_0_Pos) /*!< LCD PAL24: R04_0 Mask */ -#define LCD_PAL24_G04_0_Pos 5 /*!< LCD PAL24: G04_0 Position */ -#define LCD_PAL24_G04_0_Msk (0x1fUL << LCD_PAL24_G04_0_Pos) /*!< LCD PAL24: G04_0 Mask */ -#define LCD_PAL24_B04_0_Pos 10 /*!< LCD PAL24: B04_0 Position */ -#define LCD_PAL24_B04_0_Msk (0x1fUL << LCD_PAL24_B04_0_Pos) /*!< LCD PAL24: B04_0 Mask */ -#define LCD_PAL24_I0_Pos 15 /*!< LCD PAL24: I0 Position */ -#define LCD_PAL24_I0_Msk (0x01UL << LCD_PAL24_I0_Pos) /*!< LCD PAL24: I0 Mask */ -#define LCD_PAL24_R14_0_Pos 16 /*!< LCD PAL24: R14_0 Position */ -#define LCD_PAL24_R14_0_Msk (0x1fUL << LCD_PAL24_R14_0_Pos) /*!< LCD PAL24: R14_0 Mask */ -#define LCD_PAL24_G14_0_Pos 21 /*!< LCD PAL24: G14_0 Position */ -#define LCD_PAL24_G14_0_Msk (0x1fUL << LCD_PAL24_G14_0_Pos) /*!< LCD PAL24: G14_0 Mask */ -#define LCD_PAL24_B14_0_Pos 26 /*!< LCD PAL24: B14_0 Position */ -#define LCD_PAL24_B14_0_Msk (0x1fUL << LCD_PAL24_B14_0_Pos) /*!< LCD PAL24: B14_0 Mask */ -#define LCD_PAL24_I1_Pos 31 /*!< LCD PAL24: I1 Position */ -#define LCD_PAL24_I1_Msk (0x01UL << LCD_PAL24_I1_Pos) /*!< LCD PAL24: I1 Mask */ - -// ---------------------------------------- LCD_PAL25 ------------------------------------------- -#define LCD_PAL25_R04_0_Pos 0 /*!< LCD PAL25: R04_0 Position */ -#define LCD_PAL25_R04_0_Msk (0x1fUL << LCD_PAL25_R04_0_Pos) /*!< LCD PAL25: R04_0 Mask */ -#define LCD_PAL25_G04_0_Pos 5 /*!< LCD PAL25: G04_0 Position */ -#define LCD_PAL25_G04_0_Msk (0x1fUL << LCD_PAL25_G04_0_Pos) /*!< LCD PAL25: G04_0 Mask */ -#define LCD_PAL25_B04_0_Pos 10 /*!< LCD PAL25: B04_0 Position */ -#define LCD_PAL25_B04_0_Msk (0x1fUL << LCD_PAL25_B04_0_Pos) /*!< LCD PAL25: B04_0 Mask */ -#define LCD_PAL25_I0_Pos 15 /*!< LCD PAL25: I0 Position */ -#define LCD_PAL25_I0_Msk (0x01UL << LCD_PAL25_I0_Pos) /*!< LCD PAL25: I0 Mask */ -#define LCD_PAL25_R14_0_Pos 16 /*!< LCD PAL25: R14_0 Position */ -#define LCD_PAL25_R14_0_Msk (0x1fUL << LCD_PAL25_R14_0_Pos) /*!< LCD PAL25: R14_0 Mask */ -#define LCD_PAL25_G14_0_Pos 21 /*!< LCD PAL25: G14_0 Position */ -#define LCD_PAL25_G14_0_Msk (0x1fUL << LCD_PAL25_G14_0_Pos) /*!< LCD PAL25: G14_0 Mask */ -#define LCD_PAL25_B14_0_Pos 26 /*!< LCD PAL25: B14_0 Position */ -#define LCD_PAL25_B14_0_Msk (0x1fUL << LCD_PAL25_B14_0_Pos) /*!< LCD PAL25: B14_0 Mask */ -#define LCD_PAL25_I1_Pos 31 /*!< LCD PAL25: I1 Position */ -#define LCD_PAL25_I1_Msk (0x01UL << LCD_PAL25_I1_Pos) /*!< LCD PAL25: I1 Mask */ - -// ---------------------------------------- LCD_PAL26 ------------------------------------------- -#define LCD_PAL26_R04_0_Pos 0 /*!< LCD PAL26: R04_0 Position */ -#define LCD_PAL26_R04_0_Msk (0x1fUL << LCD_PAL26_R04_0_Pos) /*!< LCD PAL26: R04_0 Mask */ -#define LCD_PAL26_G04_0_Pos 5 /*!< LCD PAL26: G04_0 Position */ -#define LCD_PAL26_G04_0_Msk (0x1fUL << LCD_PAL26_G04_0_Pos) /*!< LCD PAL26: G04_0 Mask */ -#define LCD_PAL26_B04_0_Pos 10 /*!< LCD PAL26: B04_0 Position */ -#define LCD_PAL26_B04_0_Msk (0x1fUL << LCD_PAL26_B04_0_Pos) /*!< LCD PAL26: B04_0 Mask */ -#define LCD_PAL26_I0_Pos 15 /*!< LCD PAL26: I0 Position */ -#define LCD_PAL26_I0_Msk (0x01UL << LCD_PAL26_I0_Pos) /*!< LCD PAL26: I0 Mask */ -#define LCD_PAL26_R14_0_Pos 16 /*!< LCD PAL26: R14_0 Position */ -#define LCD_PAL26_R14_0_Msk (0x1fUL << LCD_PAL26_R14_0_Pos) /*!< LCD PAL26: R14_0 Mask */ -#define LCD_PAL26_G14_0_Pos 21 /*!< LCD PAL26: G14_0 Position */ -#define LCD_PAL26_G14_0_Msk (0x1fUL << LCD_PAL26_G14_0_Pos) /*!< LCD PAL26: G14_0 Mask */ -#define LCD_PAL26_B14_0_Pos 26 /*!< LCD PAL26: B14_0 Position */ -#define LCD_PAL26_B14_0_Msk (0x1fUL << LCD_PAL26_B14_0_Pos) /*!< LCD PAL26: B14_0 Mask */ -#define LCD_PAL26_I1_Pos 31 /*!< LCD PAL26: I1 Position */ -#define LCD_PAL26_I1_Msk (0x01UL << LCD_PAL26_I1_Pos) /*!< LCD PAL26: I1 Mask */ - -// ---------------------------------------- LCD_PAL27 ------------------------------------------- -#define LCD_PAL27_R04_0_Pos 0 /*!< LCD PAL27: R04_0 Position */ -#define LCD_PAL27_R04_0_Msk (0x1fUL << LCD_PAL27_R04_0_Pos) /*!< LCD PAL27: R04_0 Mask */ -#define LCD_PAL27_G04_0_Pos 5 /*!< LCD PAL27: G04_0 Position */ -#define LCD_PAL27_G04_0_Msk (0x1fUL << LCD_PAL27_G04_0_Pos) /*!< LCD PAL27: G04_0 Mask */ -#define LCD_PAL27_B04_0_Pos 10 /*!< LCD PAL27: B04_0 Position */ -#define LCD_PAL27_B04_0_Msk (0x1fUL << LCD_PAL27_B04_0_Pos) /*!< LCD PAL27: B04_0 Mask */ -#define LCD_PAL27_I0_Pos 15 /*!< LCD PAL27: I0 Position */ -#define LCD_PAL27_I0_Msk (0x01UL << LCD_PAL27_I0_Pos) /*!< LCD PAL27: I0 Mask */ -#define LCD_PAL27_R14_0_Pos 16 /*!< LCD PAL27: R14_0 Position */ -#define LCD_PAL27_R14_0_Msk (0x1fUL << LCD_PAL27_R14_0_Pos) /*!< LCD PAL27: R14_0 Mask */ -#define LCD_PAL27_G14_0_Pos 21 /*!< LCD PAL27: G14_0 Position */ -#define LCD_PAL27_G14_0_Msk (0x1fUL << LCD_PAL27_G14_0_Pos) /*!< LCD PAL27: G14_0 Mask */ -#define LCD_PAL27_B14_0_Pos 26 /*!< LCD PAL27: B14_0 Position */ -#define LCD_PAL27_B14_0_Msk (0x1fUL << LCD_PAL27_B14_0_Pos) /*!< LCD PAL27: B14_0 Mask */ -#define LCD_PAL27_I1_Pos 31 /*!< LCD PAL27: I1 Position */ -#define LCD_PAL27_I1_Msk (0x01UL << LCD_PAL27_I1_Pos) /*!< LCD PAL27: I1 Mask */ - -// ---------------------------------------- LCD_PAL28 ------------------------------------------- -#define LCD_PAL28_R04_0_Pos 0 /*!< LCD PAL28: R04_0 Position */ -#define LCD_PAL28_R04_0_Msk (0x1fUL << LCD_PAL28_R04_0_Pos) /*!< LCD PAL28: R04_0 Mask */ -#define LCD_PAL28_G04_0_Pos 5 /*!< LCD PAL28: G04_0 Position */ -#define LCD_PAL28_G04_0_Msk (0x1fUL << LCD_PAL28_G04_0_Pos) /*!< LCD PAL28: G04_0 Mask */ -#define LCD_PAL28_B04_0_Pos 10 /*!< LCD PAL28: B04_0 Position */ -#define LCD_PAL28_B04_0_Msk (0x1fUL << LCD_PAL28_B04_0_Pos) /*!< LCD PAL28: B04_0 Mask */ -#define LCD_PAL28_I0_Pos 15 /*!< LCD PAL28: I0 Position */ -#define LCD_PAL28_I0_Msk (0x01UL << LCD_PAL28_I0_Pos) /*!< LCD PAL28: I0 Mask */ -#define LCD_PAL28_R14_0_Pos 16 /*!< LCD PAL28: R14_0 Position */ -#define LCD_PAL28_R14_0_Msk (0x1fUL << LCD_PAL28_R14_0_Pos) /*!< LCD PAL28: R14_0 Mask */ -#define LCD_PAL28_G14_0_Pos 21 /*!< LCD PAL28: G14_0 Position */ -#define LCD_PAL28_G14_0_Msk (0x1fUL << LCD_PAL28_G14_0_Pos) /*!< LCD PAL28: G14_0 Mask */ -#define LCD_PAL28_B14_0_Pos 26 /*!< LCD PAL28: B14_0 Position */ -#define LCD_PAL28_B14_0_Msk (0x1fUL << LCD_PAL28_B14_0_Pos) /*!< LCD PAL28: B14_0 Mask */ -#define LCD_PAL28_I1_Pos 31 /*!< LCD PAL28: I1 Position */ -#define LCD_PAL28_I1_Msk (0x01UL << LCD_PAL28_I1_Pos) /*!< LCD PAL28: I1 Mask */ - -// ---------------------------------------- LCD_PAL29 ------------------------------------------- -#define LCD_PAL29_R04_0_Pos 0 /*!< LCD PAL29: R04_0 Position */ -#define LCD_PAL29_R04_0_Msk (0x1fUL << LCD_PAL29_R04_0_Pos) /*!< LCD PAL29: R04_0 Mask */ -#define LCD_PAL29_G04_0_Pos 5 /*!< LCD PAL29: G04_0 Position */ -#define LCD_PAL29_G04_0_Msk (0x1fUL << LCD_PAL29_G04_0_Pos) /*!< LCD PAL29: G04_0 Mask */ -#define LCD_PAL29_B04_0_Pos 10 /*!< LCD PAL29: B04_0 Position */ -#define LCD_PAL29_B04_0_Msk (0x1fUL << LCD_PAL29_B04_0_Pos) /*!< LCD PAL29: B04_0 Mask */ -#define LCD_PAL29_I0_Pos 15 /*!< LCD PAL29: I0 Position */ -#define LCD_PAL29_I0_Msk (0x01UL << LCD_PAL29_I0_Pos) /*!< LCD PAL29: I0 Mask */ -#define LCD_PAL29_R14_0_Pos 16 /*!< LCD PAL29: R14_0 Position */ -#define LCD_PAL29_R14_0_Msk (0x1fUL << LCD_PAL29_R14_0_Pos) /*!< LCD PAL29: R14_0 Mask */ -#define LCD_PAL29_G14_0_Pos 21 /*!< LCD PAL29: G14_0 Position */ -#define LCD_PAL29_G14_0_Msk (0x1fUL << LCD_PAL29_G14_0_Pos) /*!< LCD PAL29: G14_0 Mask */ -#define LCD_PAL29_B14_0_Pos 26 /*!< LCD PAL29: B14_0 Position */ -#define LCD_PAL29_B14_0_Msk (0x1fUL << LCD_PAL29_B14_0_Pos) /*!< LCD PAL29: B14_0 Mask */ -#define LCD_PAL29_I1_Pos 31 /*!< LCD PAL29: I1 Position */ -#define LCD_PAL29_I1_Msk (0x01UL << LCD_PAL29_I1_Pos) /*!< LCD PAL29: I1 Mask */ - -// ---------------------------------------- LCD_PAL30 ------------------------------------------- -#define LCD_PAL30_R04_0_Pos 0 /*!< LCD PAL30: R04_0 Position */ -#define LCD_PAL30_R04_0_Msk (0x1fUL << LCD_PAL30_R04_0_Pos) /*!< LCD PAL30: R04_0 Mask */ -#define LCD_PAL30_G04_0_Pos 5 /*!< LCD PAL30: G04_0 Position */ -#define LCD_PAL30_G04_0_Msk (0x1fUL << LCD_PAL30_G04_0_Pos) /*!< LCD PAL30: G04_0 Mask */ -#define LCD_PAL30_B04_0_Pos 10 /*!< LCD PAL30: B04_0 Position */ -#define LCD_PAL30_B04_0_Msk (0x1fUL << LCD_PAL30_B04_0_Pos) /*!< LCD PAL30: B04_0 Mask */ -#define LCD_PAL30_I0_Pos 15 /*!< LCD PAL30: I0 Position */ -#define LCD_PAL30_I0_Msk (0x01UL << LCD_PAL30_I0_Pos) /*!< LCD PAL30: I0 Mask */ -#define LCD_PAL30_R14_0_Pos 16 /*!< LCD PAL30: R14_0 Position */ -#define LCD_PAL30_R14_0_Msk (0x1fUL << LCD_PAL30_R14_0_Pos) /*!< LCD PAL30: R14_0 Mask */ -#define LCD_PAL30_G14_0_Pos 21 /*!< LCD PAL30: G14_0 Position */ -#define LCD_PAL30_G14_0_Msk (0x1fUL << LCD_PAL30_G14_0_Pos) /*!< LCD PAL30: G14_0 Mask */ -#define LCD_PAL30_B14_0_Pos 26 /*!< LCD PAL30: B14_0 Position */ -#define LCD_PAL30_B14_0_Msk (0x1fUL << LCD_PAL30_B14_0_Pos) /*!< LCD PAL30: B14_0 Mask */ -#define LCD_PAL30_I1_Pos 31 /*!< LCD PAL30: I1 Position */ -#define LCD_PAL30_I1_Msk (0x01UL << LCD_PAL30_I1_Pos) /*!< LCD PAL30: I1 Mask */ - -// ---------------------------------------- LCD_PAL31 ------------------------------------------- -#define LCD_PAL31_R04_0_Pos 0 /*!< LCD PAL31: R04_0 Position */ -#define LCD_PAL31_R04_0_Msk (0x1fUL << LCD_PAL31_R04_0_Pos) /*!< LCD PAL31: R04_0 Mask */ -#define LCD_PAL31_G04_0_Pos 5 /*!< LCD PAL31: G04_0 Position */ -#define LCD_PAL31_G04_0_Msk (0x1fUL << LCD_PAL31_G04_0_Pos) /*!< LCD PAL31: G04_0 Mask */ -#define LCD_PAL31_B04_0_Pos 10 /*!< LCD PAL31: B04_0 Position */ -#define LCD_PAL31_B04_0_Msk (0x1fUL << LCD_PAL31_B04_0_Pos) /*!< LCD PAL31: B04_0 Mask */ -#define LCD_PAL31_I0_Pos 15 /*!< LCD PAL31: I0 Position */ -#define LCD_PAL31_I0_Msk (0x01UL << LCD_PAL31_I0_Pos) /*!< LCD PAL31: I0 Mask */ -#define LCD_PAL31_R14_0_Pos 16 /*!< LCD PAL31: R14_0 Position */ -#define LCD_PAL31_R14_0_Msk (0x1fUL << LCD_PAL31_R14_0_Pos) /*!< LCD PAL31: R14_0 Mask */ -#define LCD_PAL31_G14_0_Pos 21 /*!< LCD PAL31: G14_0 Position */ -#define LCD_PAL31_G14_0_Msk (0x1fUL << LCD_PAL31_G14_0_Pos) /*!< LCD PAL31: G14_0 Mask */ -#define LCD_PAL31_B14_0_Pos 26 /*!< LCD PAL31: B14_0 Position */ -#define LCD_PAL31_B14_0_Msk (0x1fUL << LCD_PAL31_B14_0_Pos) /*!< LCD PAL31: B14_0 Mask */ -#define LCD_PAL31_I1_Pos 31 /*!< LCD PAL31: I1 Position */ -#define LCD_PAL31_I1_Msk (0x01UL << LCD_PAL31_I1_Pos) /*!< LCD PAL31: I1 Mask */ - -// ---------------------------------------- LCD_PAL32 ------------------------------------------- -#define LCD_PAL32_R04_0_Pos 0 /*!< LCD PAL32: R04_0 Position */ -#define LCD_PAL32_R04_0_Msk (0x1fUL << LCD_PAL32_R04_0_Pos) /*!< LCD PAL32: R04_0 Mask */ -#define LCD_PAL32_G04_0_Pos 5 /*!< LCD PAL32: G04_0 Position */ -#define LCD_PAL32_G04_0_Msk (0x1fUL << LCD_PAL32_G04_0_Pos) /*!< LCD PAL32: G04_0 Mask */ -#define LCD_PAL32_B04_0_Pos 10 /*!< LCD PAL32: B04_0 Position */ -#define LCD_PAL32_B04_0_Msk (0x1fUL << LCD_PAL32_B04_0_Pos) /*!< LCD PAL32: B04_0 Mask */ -#define LCD_PAL32_I0_Pos 15 /*!< LCD PAL32: I0 Position */ -#define LCD_PAL32_I0_Msk (0x01UL << LCD_PAL32_I0_Pos) /*!< LCD PAL32: I0 Mask */ -#define LCD_PAL32_R14_0_Pos 16 /*!< LCD PAL32: R14_0 Position */ -#define LCD_PAL32_R14_0_Msk (0x1fUL << LCD_PAL32_R14_0_Pos) /*!< LCD PAL32: R14_0 Mask */ -#define LCD_PAL32_G14_0_Pos 21 /*!< LCD PAL32: G14_0 Position */ -#define LCD_PAL32_G14_0_Msk (0x1fUL << LCD_PAL32_G14_0_Pos) /*!< LCD PAL32: G14_0 Mask */ -#define LCD_PAL32_B14_0_Pos 26 /*!< LCD PAL32: B14_0 Position */ -#define LCD_PAL32_B14_0_Msk (0x1fUL << LCD_PAL32_B14_0_Pos) /*!< LCD PAL32: B14_0 Mask */ -#define LCD_PAL32_I1_Pos 31 /*!< LCD PAL32: I1 Position */ -#define LCD_PAL32_I1_Msk (0x01UL << LCD_PAL32_I1_Pos) /*!< LCD PAL32: I1 Mask */ - -// ---------------------------------------- LCD_PAL33 ------------------------------------------- -#define LCD_PAL33_R04_0_Pos 0 /*!< LCD PAL33: R04_0 Position */ -#define LCD_PAL33_R04_0_Msk (0x1fUL << LCD_PAL33_R04_0_Pos) /*!< LCD PAL33: R04_0 Mask */ -#define LCD_PAL33_G04_0_Pos 5 /*!< LCD PAL33: G04_0 Position */ -#define LCD_PAL33_G04_0_Msk (0x1fUL << LCD_PAL33_G04_0_Pos) /*!< LCD PAL33: G04_0 Mask */ -#define LCD_PAL33_B04_0_Pos 10 /*!< LCD PAL33: B04_0 Position */ -#define LCD_PAL33_B04_0_Msk (0x1fUL << LCD_PAL33_B04_0_Pos) /*!< LCD PAL33: B04_0 Mask */ -#define LCD_PAL33_I0_Pos 15 /*!< LCD PAL33: I0 Position */ -#define LCD_PAL33_I0_Msk (0x01UL << LCD_PAL33_I0_Pos) /*!< LCD PAL33: I0 Mask */ -#define LCD_PAL33_R14_0_Pos 16 /*!< LCD PAL33: R14_0 Position */ -#define LCD_PAL33_R14_0_Msk (0x1fUL << LCD_PAL33_R14_0_Pos) /*!< LCD PAL33: R14_0 Mask */ -#define LCD_PAL33_G14_0_Pos 21 /*!< LCD PAL33: G14_0 Position */ -#define LCD_PAL33_G14_0_Msk (0x1fUL << LCD_PAL33_G14_0_Pos) /*!< LCD PAL33: G14_0 Mask */ -#define LCD_PAL33_B14_0_Pos 26 /*!< LCD PAL33: B14_0 Position */ -#define LCD_PAL33_B14_0_Msk (0x1fUL << LCD_PAL33_B14_0_Pos) /*!< LCD PAL33: B14_0 Mask */ -#define LCD_PAL33_I1_Pos 31 /*!< LCD PAL33: I1 Position */ -#define LCD_PAL33_I1_Msk (0x01UL << LCD_PAL33_I1_Pos) /*!< LCD PAL33: I1 Mask */ - -// ---------------------------------------- LCD_PAL34 ------------------------------------------- -#define LCD_PAL34_R04_0_Pos 0 /*!< LCD PAL34: R04_0 Position */ -#define LCD_PAL34_R04_0_Msk (0x1fUL << LCD_PAL34_R04_0_Pos) /*!< LCD PAL34: R04_0 Mask */ -#define LCD_PAL34_G04_0_Pos 5 /*!< LCD PAL34: G04_0 Position */ -#define LCD_PAL34_G04_0_Msk (0x1fUL << LCD_PAL34_G04_0_Pos) /*!< LCD PAL34: G04_0 Mask */ -#define LCD_PAL34_B04_0_Pos 10 /*!< LCD PAL34: B04_0 Position */ -#define LCD_PAL34_B04_0_Msk (0x1fUL << LCD_PAL34_B04_0_Pos) /*!< LCD PAL34: B04_0 Mask */ -#define LCD_PAL34_I0_Pos 15 /*!< LCD PAL34: I0 Position */ -#define LCD_PAL34_I0_Msk (0x01UL << LCD_PAL34_I0_Pos) /*!< LCD PAL34: I0 Mask */ -#define LCD_PAL34_R14_0_Pos 16 /*!< LCD PAL34: R14_0 Position */ -#define LCD_PAL34_R14_0_Msk (0x1fUL << LCD_PAL34_R14_0_Pos) /*!< LCD PAL34: R14_0 Mask */ -#define LCD_PAL34_G14_0_Pos 21 /*!< LCD PAL34: G14_0 Position */ -#define LCD_PAL34_G14_0_Msk (0x1fUL << LCD_PAL34_G14_0_Pos) /*!< LCD PAL34: G14_0 Mask */ -#define LCD_PAL34_B14_0_Pos 26 /*!< LCD PAL34: B14_0 Position */ -#define LCD_PAL34_B14_0_Msk (0x1fUL << LCD_PAL34_B14_0_Pos) /*!< LCD PAL34: B14_0 Mask */ -#define LCD_PAL34_I1_Pos 31 /*!< LCD PAL34: I1 Position */ -#define LCD_PAL34_I1_Msk (0x01UL << LCD_PAL34_I1_Pos) /*!< LCD PAL34: I1 Mask */ - -// ---------------------------------------- LCD_PAL35 ------------------------------------------- -#define LCD_PAL35_R04_0_Pos 0 /*!< LCD PAL35: R04_0 Position */ -#define LCD_PAL35_R04_0_Msk (0x1fUL << LCD_PAL35_R04_0_Pos) /*!< LCD PAL35: R04_0 Mask */ -#define LCD_PAL35_G04_0_Pos 5 /*!< LCD PAL35: G04_0 Position */ -#define LCD_PAL35_G04_0_Msk (0x1fUL << LCD_PAL35_G04_0_Pos) /*!< LCD PAL35: G04_0 Mask */ -#define LCD_PAL35_B04_0_Pos 10 /*!< LCD PAL35: B04_0 Position */ -#define LCD_PAL35_B04_0_Msk (0x1fUL << LCD_PAL35_B04_0_Pos) /*!< LCD PAL35: B04_0 Mask */ -#define LCD_PAL35_I0_Pos 15 /*!< LCD PAL35: I0 Position */ -#define LCD_PAL35_I0_Msk (0x01UL << LCD_PAL35_I0_Pos) /*!< LCD PAL35: I0 Mask */ -#define LCD_PAL35_R14_0_Pos 16 /*!< LCD PAL35: R14_0 Position */ -#define LCD_PAL35_R14_0_Msk (0x1fUL << LCD_PAL35_R14_0_Pos) /*!< LCD PAL35: R14_0 Mask */ -#define LCD_PAL35_G14_0_Pos 21 /*!< LCD PAL35: G14_0 Position */ -#define LCD_PAL35_G14_0_Msk (0x1fUL << LCD_PAL35_G14_0_Pos) /*!< LCD PAL35: G14_0 Mask */ -#define LCD_PAL35_B14_0_Pos 26 /*!< LCD PAL35: B14_0 Position */ -#define LCD_PAL35_B14_0_Msk (0x1fUL << LCD_PAL35_B14_0_Pos) /*!< LCD PAL35: B14_0 Mask */ -#define LCD_PAL35_I1_Pos 31 /*!< LCD PAL35: I1 Position */ -#define LCD_PAL35_I1_Msk (0x01UL << LCD_PAL35_I1_Pos) /*!< LCD PAL35: I1 Mask */ - -// ---------------------------------------- LCD_PAL36 ------------------------------------------- -#define LCD_PAL36_R04_0_Pos 0 /*!< LCD PAL36: R04_0 Position */ -#define LCD_PAL36_R04_0_Msk (0x1fUL << LCD_PAL36_R04_0_Pos) /*!< LCD PAL36: R04_0 Mask */ -#define LCD_PAL36_G04_0_Pos 5 /*!< LCD PAL36: G04_0 Position */ -#define LCD_PAL36_G04_0_Msk (0x1fUL << LCD_PAL36_G04_0_Pos) /*!< LCD PAL36: G04_0 Mask */ -#define LCD_PAL36_B04_0_Pos 10 /*!< LCD PAL36: B04_0 Position */ -#define LCD_PAL36_B04_0_Msk (0x1fUL << LCD_PAL36_B04_0_Pos) /*!< LCD PAL36: B04_0 Mask */ -#define LCD_PAL36_I0_Pos 15 /*!< LCD PAL36: I0 Position */ -#define LCD_PAL36_I0_Msk (0x01UL << LCD_PAL36_I0_Pos) /*!< LCD PAL36: I0 Mask */ -#define LCD_PAL36_R14_0_Pos 16 /*!< LCD PAL36: R14_0 Position */ -#define LCD_PAL36_R14_0_Msk (0x1fUL << LCD_PAL36_R14_0_Pos) /*!< LCD PAL36: R14_0 Mask */ -#define LCD_PAL36_G14_0_Pos 21 /*!< LCD PAL36: G14_0 Position */ -#define LCD_PAL36_G14_0_Msk (0x1fUL << LCD_PAL36_G14_0_Pos) /*!< LCD PAL36: G14_0 Mask */ -#define LCD_PAL36_B14_0_Pos 26 /*!< LCD PAL36: B14_0 Position */ -#define LCD_PAL36_B14_0_Msk (0x1fUL << LCD_PAL36_B14_0_Pos) /*!< LCD PAL36: B14_0 Mask */ -#define LCD_PAL36_I1_Pos 31 /*!< LCD PAL36: I1 Position */ -#define LCD_PAL36_I1_Msk (0x01UL << LCD_PAL36_I1_Pos) /*!< LCD PAL36: I1 Mask */ - -// ---------------------------------------- LCD_PAL37 ------------------------------------------- -#define LCD_PAL37_R04_0_Pos 0 /*!< LCD PAL37: R04_0 Position */ -#define LCD_PAL37_R04_0_Msk (0x1fUL << LCD_PAL37_R04_0_Pos) /*!< LCD PAL37: R04_0 Mask */ -#define LCD_PAL37_G04_0_Pos 5 /*!< LCD PAL37: G04_0 Position */ -#define LCD_PAL37_G04_0_Msk (0x1fUL << LCD_PAL37_G04_0_Pos) /*!< LCD PAL37: G04_0 Mask */ -#define LCD_PAL37_B04_0_Pos 10 /*!< LCD PAL37: B04_0 Position */ -#define LCD_PAL37_B04_0_Msk (0x1fUL << LCD_PAL37_B04_0_Pos) /*!< LCD PAL37: B04_0 Mask */ -#define LCD_PAL37_I0_Pos 15 /*!< LCD PAL37: I0 Position */ -#define LCD_PAL37_I0_Msk (0x01UL << LCD_PAL37_I0_Pos) /*!< LCD PAL37: I0 Mask */ -#define LCD_PAL37_R14_0_Pos 16 /*!< LCD PAL37: R14_0 Position */ -#define LCD_PAL37_R14_0_Msk (0x1fUL << LCD_PAL37_R14_0_Pos) /*!< LCD PAL37: R14_0 Mask */ -#define LCD_PAL37_G14_0_Pos 21 /*!< LCD PAL37: G14_0 Position */ -#define LCD_PAL37_G14_0_Msk (0x1fUL << LCD_PAL37_G14_0_Pos) /*!< LCD PAL37: G14_0 Mask */ -#define LCD_PAL37_B14_0_Pos 26 /*!< LCD PAL37: B14_0 Position */ -#define LCD_PAL37_B14_0_Msk (0x1fUL << LCD_PAL37_B14_0_Pos) /*!< LCD PAL37: B14_0 Mask */ -#define LCD_PAL37_I1_Pos 31 /*!< LCD PAL37: I1 Position */ -#define LCD_PAL37_I1_Msk (0x01UL << LCD_PAL37_I1_Pos) /*!< LCD PAL37: I1 Mask */ - -// ---------------------------------------- LCD_PAL38 ------------------------------------------- -#define LCD_PAL38_R04_0_Pos 0 /*!< LCD PAL38: R04_0 Position */ -#define LCD_PAL38_R04_0_Msk (0x1fUL << LCD_PAL38_R04_0_Pos) /*!< LCD PAL38: R04_0 Mask */ -#define LCD_PAL38_G04_0_Pos 5 /*!< LCD PAL38: G04_0 Position */ -#define LCD_PAL38_G04_0_Msk (0x1fUL << LCD_PAL38_G04_0_Pos) /*!< LCD PAL38: G04_0 Mask */ -#define LCD_PAL38_B04_0_Pos 10 /*!< LCD PAL38: B04_0 Position */ -#define LCD_PAL38_B04_0_Msk (0x1fUL << LCD_PAL38_B04_0_Pos) /*!< LCD PAL38: B04_0 Mask */ -#define LCD_PAL38_I0_Pos 15 /*!< LCD PAL38: I0 Position */ -#define LCD_PAL38_I0_Msk (0x01UL << LCD_PAL38_I0_Pos) /*!< LCD PAL38: I0 Mask */ -#define LCD_PAL38_R14_0_Pos 16 /*!< LCD PAL38: R14_0 Position */ -#define LCD_PAL38_R14_0_Msk (0x1fUL << LCD_PAL38_R14_0_Pos) /*!< LCD PAL38: R14_0 Mask */ -#define LCD_PAL38_G14_0_Pos 21 /*!< LCD PAL38: G14_0 Position */ -#define LCD_PAL38_G14_0_Msk (0x1fUL << LCD_PAL38_G14_0_Pos) /*!< LCD PAL38: G14_0 Mask */ -#define LCD_PAL38_B14_0_Pos 26 /*!< LCD PAL38: B14_0 Position */ -#define LCD_PAL38_B14_0_Msk (0x1fUL << LCD_PAL38_B14_0_Pos) /*!< LCD PAL38: B14_0 Mask */ -#define LCD_PAL38_I1_Pos 31 /*!< LCD PAL38: I1 Position */ -#define LCD_PAL38_I1_Msk (0x01UL << LCD_PAL38_I1_Pos) /*!< LCD PAL38: I1 Mask */ - -// ---------------------------------------- LCD_PAL39 ------------------------------------------- -#define LCD_PAL39_R04_0_Pos 0 /*!< LCD PAL39: R04_0 Position */ -#define LCD_PAL39_R04_0_Msk (0x1fUL << LCD_PAL39_R04_0_Pos) /*!< LCD PAL39: R04_0 Mask */ -#define LCD_PAL39_G04_0_Pos 5 /*!< LCD PAL39: G04_0 Position */ -#define LCD_PAL39_G04_0_Msk (0x1fUL << LCD_PAL39_G04_0_Pos) /*!< LCD PAL39: G04_0 Mask */ -#define LCD_PAL39_B04_0_Pos 10 /*!< LCD PAL39: B04_0 Position */ -#define LCD_PAL39_B04_0_Msk (0x1fUL << LCD_PAL39_B04_0_Pos) /*!< LCD PAL39: B04_0 Mask */ -#define LCD_PAL39_I0_Pos 15 /*!< LCD PAL39: I0 Position */ -#define LCD_PAL39_I0_Msk (0x01UL << LCD_PAL39_I0_Pos) /*!< LCD PAL39: I0 Mask */ -#define LCD_PAL39_R14_0_Pos 16 /*!< LCD PAL39: R14_0 Position */ -#define LCD_PAL39_R14_0_Msk (0x1fUL << LCD_PAL39_R14_0_Pos) /*!< LCD PAL39: R14_0 Mask */ -#define LCD_PAL39_G14_0_Pos 21 /*!< LCD PAL39: G14_0 Position */ -#define LCD_PAL39_G14_0_Msk (0x1fUL << LCD_PAL39_G14_0_Pos) /*!< LCD PAL39: G14_0 Mask */ -#define LCD_PAL39_B14_0_Pos 26 /*!< LCD PAL39: B14_0 Position */ -#define LCD_PAL39_B14_0_Msk (0x1fUL << LCD_PAL39_B14_0_Pos) /*!< LCD PAL39: B14_0 Mask */ -#define LCD_PAL39_I1_Pos 31 /*!< LCD PAL39: I1 Position */ -#define LCD_PAL39_I1_Msk (0x01UL << LCD_PAL39_I1_Pos) /*!< LCD PAL39: I1 Mask */ - -// ---------------------------------------- LCD_PAL40 ------------------------------------------- -#define LCD_PAL40_R04_0_Pos 0 /*!< LCD PAL40: R04_0 Position */ -#define LCD_PAL40_R04_0_Msk (0x1fUL << LCD_PAL40_R04_0_Pos) /*!< LCD PAL40: R04_0 Mask */ -#define LCD_PAL40_G04_0_Pos 5 /*!< LCD PAL40: G04_0 Position */ -#define LCD_PAL40_G04_0_Msk (0x1fUL << LCD_PAL40_G04_0_Pos) /*!< LCD PAL40: G04_0 Mask */ -#define LCD_PAL40_B04_0_Pos 10 /*!< LCD PAL40: B04_0 Position */ -#define LCD_PAL40_B04_0_Msk (0x1fUL << LCD_PAL40_B04_0_Pos) /*!< LCD PAL40: B04_0 Mask */ -#define LCD_PAL40_I0_Pos 15 /*!< LCD PAL40: I0 Position */ -#define LCD_PAL40_I0_Msk (0x01UL << LCD_PAL40_I0_Pos) /*!< LCD PAL40: I0 Mask */ -#define LCD_PAL40_R14_0_Pos 16 /*!< LCD PAL40: R14_0 Position */ -#define LCD_PAL40_R14_0_Msk (0x1fUL << LCD_PAL40_R14_0_Pos) /*!< LCD PAL40: R14_0 Mask */ -#define LCD_PAL40_G14_0_Pos 21 /*!< LCD PAL40: G14_0 Position */ -#define LCD_PAL40_G14_0_Msk (0x1fUL << LCD_PAL40_G14_0_Pos) /*!< LCD PAL40: G14_0 Mask */ -#define LCD_PAL40_B14_0_Pos 26 /*!< LCD PAL40: B14_0 Position */ -#define LCD_PAL40_B14_0_Msk (0x1fUL << LCD_PAL40_B14_0_Pos) /*!< LCD PAL40: B14_0 Mask */ -#define LCD_PAL40_I1_Pos 31 /*!< LCD PAL40: I1 Position */ -#define LCD_PAL40_I1_Msk (0x01UL << LCD_PAL40_I1_Pos) /*!< LCD PAL40: I1 Mask */ - -// ---------------------------------------- LCD_PAL41 ------------------------------------------- -#define LCD_PAL41_R04_0_Pos 0 /*!< LCD PAL41: R04_0 Position */ -#define LCD_PAL41_R04_0_Msk (0x1fUL << LCD_PAL41_R04_0_Pos) /*!< LCD PAL41: R04_0 Mask */ -#define LCD_PAL41_G04_0_Pos 5 /*!< LCD PAL41: G04_0 Position */ -#define LCD_PAL41_G04_0_Msk (0x1fUL << LCD_PAL41_G04_0_Pos) /*!< LCD PAL41: G04_0 Mask */ -#define LCD_PAL41_B04_0_Pos 10 /*!< LCD PAL41: B04_0 Position */ -#define LCD_PAL41_B04_0_Msk (0x1fUL << LCD_PAL41_B04_0_Pos) /*!< LCD PAL41: B04_0 Mask */ -#define LCD_PAL41_I0_Pos 15 /*!< LCD PAL41: I0 Position */ -#define LCD_PAL41_I0_Msk (0x01UL << LCD_PAL41_I0_Pos) /*!< LCD PAL41: I0 Mask */ -#define LCD_PAL41_R14_0_Pos 16 /*!< LCD PAL41: R14_0 Position */ -#define LCD_PAL41_R14_0_Msk (0x1fUL << LCD_PAL41_R14_0_Pos) /*!< LCD PAL41: R14_0 Mask */ -#define LCD_PAL41_G14_0_Pos 21 /*!< LCD PAL41: G14_0 Position */ -#define LCD_PAL41_G14_0_Msk (0x1fUL << LCD_PAL41_G14_0_Pos) /*!< LCD PAL41: G14_0 Mask */ -#define LCD_PAL41_B14_0_Pos 26 /*!< LCD PAL41: B14_0 Position */ -#define LCD_PAL41_B14_0_Msk (0x1fUL << LCD_PAL41_B14_0_Pos) /*!< LCD PAL41: B14_0 Mask */ -#define LCD_PAL41_I1_Pos 31 /*!< LCD PAL41: I1 Position */ -#define LCD_PAL41_I1_Msk (0x01UL << LCD_PAL41_I1_Pos) /*!< LCD PAL41: I1 Mask */ - -// ---------------------------------------- LCD_PAL42 ------------------------------------------- -#define LCD_PAL42_R04_0_Pos 0 /*!< LCD PAL42: R04_0 Position */ -#define LCD_PAL42_R04_0_Msk (0x1fUL << LCD_PAL42_R04_0_Pos) /*!< LCD PAL42: R04_0 Mask */ -#define LCD_PAL42_G04_0_Pos 5 /*!< LCD PAL42: G04_0 Position */ -#define LCD_PAL42_G04_0_Msk (0x1fUL << LCD_PAL42_G04_0_Pos) /*!< LCD PAL42: G04_0 Mask */ -#define LCD_PAL42_B04_0_Pos 10 /*!< LCD PAL42: B04_0 Position */ -#define LCD_PAL42_B04_0_Msk (0x1fUL << LCD_PAL42_B04_0_Pos) /*!< LCD PAL42: B04_0 Mask */ -#define LCD_PAL42_I0_Pos 15 /*!< LCD PAL42: I0 Position */ -#define LCD_PAL42_I0_Msk (0x01UL << LCD_PAL42_I0_Pos) /*!< LCD PAL42: I0 Mask */ -#define LCD_PAL42_R14_0_Pos 16 /*!< LCD PAL42: R14_0 Position */ -#define LCD_PAL42_R14_0_Msk (0x1fUL << LCD_PAL42_R14_0_Pos) /*!< LCD PAL42: R14_0 Mask */ -#define LCD_PAL42_G14_0_Pos 21 /*!< LCD PAL42: G14_0 Position */ -#define LCD_PAL42_G14_0_Msk (0x1fUL << LCD_PAL42_G14_0_Pos) /*!< LCD PAL42: G14_0 Mask */ -#define LCD_PAL42_B14_0_Pos 26 /*!< LCD PAL42: B14_0 Position */ -#define LCD_PAL42_B14_0_Msk (0x1fUL << LCD_PAL42_B14_0_Pos) /*!< LCD PAL42: B14_0 Mask */ -#define LCD_PAL42_I1_Pos 31 /*!< LCD PAL42: I1 Position */ -#define LCD_PAL42_I1_Msk (0x01UL << LCD_PAL42_I1_Pos) /*!< LCD PAL42: I1 Mask */ - -// ---------------------------------------- LCD_PAL43 ------------------------------------------- -#define LCD_PAL43_R04_0_Pos 0 /*!< LCD PAL43: R04_0 Position */ -#define LCD_PAL43_R04_0_Msk (0x1fUL << LCD_PAL43_R04_0_Pos) /*!< LCD PAL43: R04_0 Mask */ -#define LCD_PAL43_G04_0_Pos 5 /*!< LCD PAL43: G04_0 Position */ -#define LCD_PAL43_G04_0_Msk (0x1fUL << LCD_PAL43_G04_0_Pos) /*!< LCD PAL43: G04_0 Mask */ -#define LCD_PAL43_B04_0_Pos 10 /*!< LCD PAL43: B04_0 Position */ -#define LCD_PAL43_B04_0_Msk (0x1fUL << LCD_PAL43_B04_0_Pos) /*!< LCD PAL43: B04_0 Mask */ -#define LCD_PAL43_I0_Pos 15 /*!< LCD PAL43: I0 Position */ -#define LCD_PAL43_I0_Msk (0x01UL << LCD_PAL43_I0_Pos) /*!< LCD PAL43: I0 Mask */ -#define LCD_PAL43_R14_0_Pos 16 /*!< LCD PAL43: R14_0 Position */ -#define LCD_PAL43_R14_0_Msk (0x1fUL << LCD_PAL43_R14_0_Pos) /*!< LCD PAL43: R14_0 Mask */ -#define LCD_PAL43_G14_0_Pos 21 /*!< LCD PAL43: G14_0 Position */ -#define LCD_PAL43_G14_0_Msk (0x1fUL << LCD_PAL43_G14_0_Pos) /*!< LCD PAL43: G14_0 Mask */ -#define LCD_PAL43_B14_0_Pos 26 /*!< LCD PAL43: B14_0 Position */ -#define LCD_PAL43_B14_0_Msk (0x1fUL << LCD_PAL43_B14_0_Pos) /*!< LCD PAL43: B14_0 Mask */ -#define LCD_PAL43_I1_Pos 31 /*!< LCD PAL43: I1 Position */ -#define LCD_PAL43_I1_Msk (0x01UL << LCD_PAL43_I1_Pos) /*!< LCD PAL43: I1 Mask */ - -// ---------------------------------------- LCD_PAL44 ------------------------------------------- -#define LCD_PAL44_R04_0_Pos 0 /*!< LCD PAL44: R04_0 Position */ -#define LCD_PAL44_R04_0_Msk (0x1fUL << LCD_PAL44_R04_0_Pos) /*!< LCD PAL44: R04_0 Mask */ -#define LCD_PAL44_G04_0_Pos 5 /*!< LCD PAL44: G04_0 Position */ -#define LCD_PAL44_G04_0_Msk (0x1fUL << LCD_PAL44_G04_0_Pos) /*!< LCD PAL44: G04_0 Mask */ -#define LCD_PAL44_B04_0_Pos 10 /*!< LCD PAL44: B04_0 Position */ -#define LCD_PAL44_B04_0_Msk (0x1fUL << LCD_PAL44_B04_0_Pos) /*!< LCD PAL44: B04_0 Mask */ -#define LCD_PAL44_I0_Pos 15 /*!< LCD PAL44: I0 Position */ -#define LCD_PAL44_I0_Msk (0x01UL << LCD_PAL44_I0_Pos) /*!< LCD PAL44: I0 Mask */ -#define LCD_PAL44_R14_0_Pos 16 /*!< LCD PAL44: R14_0 Position */ -#define LCD_PAL44_R14_0_Msk (0x1fUL << LCD_PAL44_R14_0_Pos) /*!< LCD PAL44: R14_0 Mask */ -#define LCD_PAL44_G14_0_Pos 21 /*!< LCD PAL44: G14_0 Position */ -#define LCD_PAL44_G14_0_Msk (0x1fUL << LCD_PAL44_G14_0_Pos) /*!< LCD PAL44: G14_0 Mask */ -#define LCD_PAL44_B14_0_Pos 26 /*!< LCD PAL44: B14_0 Position */ -#define LCD_PAL44_B14_0_Msk (0x1fUL << LCD_PAL44_B14_0_Pos) /*!< LCD PAL44: B14_0 Mask */ -#define LCD_PAL44_I1_Pos 31 /*!< LCD PAL44: I1 Position */ -#define LCD_PAL44_I1_Msk (0x01UL << LCD_PAL44_I1_Pos) /*!< LCD PAL44: I1 Mask */ - -// ---------------------------------------- LCD_PAL45 ------------------------------------------- -#define LCD_PAL45_R04_0_Pos 0 /*!< LCD PAL45: R04_0 Position */ -#define LCD_PAL45_R04_0_Msk (0x1fUL << LCD_PAL45_R04_0_Pos) /*!< LCD PAL45: R04_0 Mask */ -#define LCD_PAL45_G04_0_Pos 5 /*!< LCD PAL45: G04_0 Position */ -#define LCD_PAL45_G04_0_Msk (0x1fUL << LCD_PAL45_G04_0_Pos) /*!< LCD PAL45: G04_0 Mask */ -#define LCD_PAL45_B04_0_Pos 10 /*!< LCD PAL45: B04_0 Position */ -#define LCD_PAL45_B04_0_Msk (0x1fUL << LCD_PAL45_B04_0_Pos) /*!< LCD PAL45: B04_0 Mask */ -#define LCD_PAL45_I0_Pos 15 /*!< LCD PAL45: I0 Position */ -#define LCD_PAL45_I0_Msk (0x01UL << LCD_PAL45_I0_Pos) /*!< LCD PAL45: I0 Mask */ -#define LCD_PAL45_R14_0_Pos 16 /*!< LCD PAL45: R14_0 Position */ -#define LCD_PAL45_R14_0_Msk (0x1fUL << LCD_PAL45_R14_0_Pos) /*!< LCD PAL45: R14_0 Mask */ -#define LCD_PAL45_G14_0_Pos 21 /*!< LCD PAL45: G14_0 Position */ -#define LCD_PAL45_G14_0_Msk (0x1fUL << LCD_PAL45_G14_0_Pos) /*!< LCD PAL45: G14_0 Mask */ -#define LCD_PAL45_B14_0_Pos 26 /*!< LCD PAL45: B14_0 Position */ -#define LCD_PAL45_B14_0_Msk (0x1fUL << LCD_PAL45_B14_0_Pos) /*!< LCD PAL45: B14_0 Mask */ -#define LCD_PAL45_I1_Pos 31 /*!< LCD PAL45: I1 Position */ -#define LCD_PAL45_I1_Msk (0x01UL << LCD_PAL45_I1_Pos) /*!< LCD PAL45: I1 Mask */ - -// ---------------------------------------- LCD_PAL46 ------------------------------------------- -#define LCD_PAL46_R04_0_Pos 0 /*!< LCD PAL46: R04_0 Position */ -#define LCD_PAL46_R04_0_Msk (0x1fUL << LCD_PAL46_R04_0_Pos) /*!< LCD PAL46: R04_0 Mask */ -#define LCD_PAL46_G04_0_Pos 5 /*!< LCD PAL46: G04_0 Position */ -#define LCD_PAL46_G04_0_Msk (0x1fUL << LCD_PAL46_G04_0_Pos) /*!< LCD PAL46: G04_0 Mask */ -#define LCD_PAL46_B04_0_Pos 10 /*!< LCD PAL46: B04_0 Position */ -#define LCD_PAL46_B04_0_Msk (0x1fUL << LCD_PAL46_B04_0_Pos) /*!< LCD PAL46: B04_0 Mask */ -#define LCD_PAL46_I0_Pos 15 /*!< LCD PAL46: I0 Position */ -#define LCD_PAL46_I0_Msk (0x01UL << LCD_PAL46_I0_Pos) /*!< LCD PAL46: I0 Mask */ -#define LCD_PAL46_R14_0_Pos 16 /*!< LCD PAL46: R14_0 Position */ -#define LCD_PAL46_R14_0_Msk (0x1fUL << LCD_PAL46_R14_0_Pos) /*!< LCD PAL46: R14_0 Mask */ -#define LCD_PAL46_G14_0_Pos 21 /*!< LCD PAL46: G14_0 Position */ -#define LCD_PAL46_G14_0_Msk (0x1fUL << LCD_PAL46_G14_0_Pos) /*!< LCD PAL46: G14_0 Mask */ -#define LCD_PAL46_B14_0_Pos 26 /*!< LCD PAL46: B14_0 Position */ -#define LCD_PAL46_B14_0_Msk (0x1fUL << LCD_PAL46_B14_0_Pos) /*!< LCD PAL46: B14_0 Mask */ -#define LCD_PAL46_I1_Pos 31 /*!< LCD PAL46: I1 Position */ -#define LCD_PAL46_I1_Msk (0x01UL << LCD_PAL46_I1_Pos) /*!< LCD PAL46: I1 Mask */ - -// ---------------------------------------- LCD_PAL47 ------------------------------------------- -#define LCD_PAL47_R04_0_Pos 0 /*!< LCD PAL47: R04_0 Position */ -#define LCD_PAL47_R04_0_Msk (0x1fUL << LCD_PAL47_R04_0_Pos) /*!< LCD PAL47: R04_0 Mask */ -#define LCD_PAL47_G04_0_Pos 5 /*!< LCD PAL47: G04_0 Position */ -#define LCD_PAL47_G04_0_Msk (0x1fUL << LCD_PAL47_G04_0_Pos) /*!< LCD PAL47: G04_0 Mask */ -#define LCD_PAL47_B04_0_Pos 10 /*!< LCD PAL47: B04_0 Position */ -#define LCD_PAL47_B04_0_Msk (0x1fUL << LCD_PAL47_B04_0_Pos) /*!< LCD PAL47: B04_0 Mask */ -#define LCD_PAL47_I0_Pos 15 /*!< LCD PAL47: I0 Position */ -#define LCD_PAL47_I0_Msk (0x01UL << LCD_PAL47_I0_Pos) /*!< LCD PAL47: I0 Mask */ -#define LCD_PAL47_R14_0_Pos 16 /*!< LCD PAL47: R14_0 Position */ -#define LCD_PAL47_R14_0_Msk (0x1fUL << LCD_PAL47_R14_0_Pos) /*!< LCD PAL47: R14_0 Mask */ -#define LCD_PAL47_G14_0_Pos 21 /*!< LCD PAL47: G14_0 Position */ -#define LCD_PAL47_G14_0_Msk (0x1fUL << LCD_PAL47_G14_0_Pos) /*!< LCD PAL47: G14_0 Mask */ -#define LCD_PAL47_B14_0_Pos 26 /*!< LCD PAL47: B14_0 Position */ -#define LCD_PAL47_B14_0_Msk (0x1fUL << LCD_PAL47_B14_0_Pos) /*!< LCD PAL47: B14_0 Mask */ -#define LCD_PAL47_I1_Pos 31 /*!< LCD PAL47: I1 Position */ -#define LCD_PAL47_I1_Msk (0x01UL << LCD_PAL47_I1_Pos) /*!< LCD PAL47: I1 Mask */ - -// ---------------------------------------- LCD_PAL48 ------------------------------------------- -#define LCD_PAL48_R04_0_Pos 0 /*!< LCD PAL48: R04_0 Position */ -#define LCD_PAL48_R04_0_Msk (0x1fUL << LCD_PAL48_R04_0_Pos) /*!< LCD PAL48: R04_0 Mask */ -#define LCD_PAL48_G04_0_Pos 5 /*!< LCD PAL48: G04_0 Position */ -#define LCD_PAL48_G04_0_Msk (0x1fUL << LCD_PAL48_G04_0_Pos) /*!< LCD PAL48: G04_0 Mask */ -#define LCD_PAL48_B04_0_Pos 10 /*!< LCD PAL48: B04_0 Position */ -#define LCD_PAL48_B04_0_Msk (0x1fUL << LCD_PAL48_B04_0_Pos) /*!< LCD PAL48: B04_0 Mask */ -#define LCD_PAL48_I0_Pos 15 /*!< LCD PAL48: I0 Position */ -#define LCD_PAL48_I0_Msk (0x01UL << LCD_PAL48_I0_Pos) /*!< LCD PAL48: I0 Mask */ -#define LCD_PAL48_R14_0_Pos 16 /*!< LCD PAL48: R14_0 Position */ -#define LCD_PAL48_R14_0_Msk (0x1fUL << LCD_PAL48_R14_0_Pos) /*!< LCD PAL48: R14_0 Mask */ -#define LCD_PAL48_G14_0_Pos 21 /*!< LCD PAL48: G14_0 Position */ -#define LCD_PAL48_G14_0_Msk (0x1fUL << LCD_PAL48_G14_0_Pos) /*!< LCD PAL48: G14_0 Mask */ -#define LCD_PAL48_B14_0_Pos 26 /*!< LCD PAL48: B14_0 Position */ -#define LCD_PAL48_B14_0_Msk (0x1fUL << LCD_PAL48_B14_0_Pos) /*!< LCD PAL48: B14_0 Mask */ -#define LCD_PAL48_I1_Pos 31 /*!< LCD PAL48: I1 Position */ -#define LCD_PAL48_I1_Msk (0x01UL << LCD_PAL48_I1_Pos) /*!< LCD PAL48: I1 Mask */ - -// ---------------------------------------- LCD_PAL49 ------------------------------------------- -#define LCD_PAL49_R04_0_Pos 0 /*!< LCD PAL49: R04_0 Position */ -#define LCD_PAL49_R04_0_Msk (0x1fUL << LCD_PAL49_R04_0_Pos) /*!< LCD PAL49: R04_0 Mask */ -#define LCD_PAL49_G04_0_Pos 5 /*!< LCD PAL49: G04_0 Position */ -#define LCD_PAL49_G04_0_Msk (0x1fUL << LCD_PAL49_G04_0_Pos) /*!< LCD PAL49: G04_0 Mask */ -#define LCD_PAL49_B04_0_Pos 10 /*!< LCD PAL49: B04_0 Position */ -#define LCD_PAL49_B04_0_Msk (0x1fUL << LCD_PAL49_B04_0_Pos) /*!< LCD PAL49: B04_0 Mask */ -#define LCD_PAL49_I0_Pos 15 /*!< LCD PAL49: I0 Position */ -#define LCD_PAL49_I0_Msk (0x01UL << LCD_PAL49_I0_Pos) /*!< LCD PAL49: I0 Mask */ -#define LCD_PAL49_R14_0_Pos 16 /*!< LCD PAL49: R14_0 Position */ -#define LCD_PAL49_R14_0_Msk (0x1fUL << LCD_PAL49_R14_0_Pos) /*!< LCD PAL49: R14_0 Mask */ -#define LCD_PAL49_G14_0_Pos 21 /*!< LCD PAL49: G14_0 Position */ -#define LCD_PAL49_G14_0_Msk (0x1fUL << LCD_PAL49_G14_0_Pos) /*!< LCD PAL49: G14_0 Mask */ -#define LCD_PAL49_B14_0_Pos 26 /*!< LCD PAL49: B14_0 Position */ -#define LCD_PAL49_B14_0_Msk (0x1fUL << LCD_PAL49_B14_0_Pos) /*!< LCD PAL49: B14_0 Mask */ -#define LCD_PAL49_I1_Pos 31 /*!< LCD PAL49: I1 Position */ -#define LCD_PAL49_I1_Msk (0x01UL << LCD_PAL49_I1_Pos) /*!< LCD PAL49: I1 Mask */ - -// ---------------------------------------- LCD_PAL50 ------------------------------------------- -#define LCD_PAL50_R04_0_Pos 0 /*!< LCD PAL50: R04_0 Position */ -#define LCD_PAL50_R04_0_Msk (0x1fUL << LCD_PAL50_R04_0_Pos) /*!< LCD PAL50: R04_0 Mask */ -#define LCD_PAL50_G04_0_Pos 5 /*!< LCD PAL50: G04_0 Position */ -#define LCD_PAL50_G04_0_Msk (0x1fUL << LCD_PAL50_G04_0_Pos) /*!< LCD PAL50: G04_0 Mask */ -#define LCD_PAL50_B04_0_Pos 10 /*!< LCD PAL50: B04_0 Position */ -#define LCD_PAL50_B04_0_Msk (0x1fUL << LCD_PAL50_B04_0_Pos) /*!< LCD PAL50: B04_0 Mask */ -#define LCD_PAL50_I0_Pos 15 /*!< LCD PAL50: I0 Position */ -#define LCD_PAL50_I0_Msk (0x01UL << LCD_PAL50_I0_Pos) /*!< LCD PAL50: I0 Mask */ -#define LCD_PAL50_R14_0_Pos 16 /*!< LCD PAL50: R14_0 Position */ -#define LCD_PAL50_R14_0_Msk (0x1fUL << LCD_PAL50_R14_0_Pos) /*!< LCD PAL50: R14_0 Mask */ -#define LCD_PAL50_G14_0_Pos 21 /*!< LCD PAL50: G14_0 Position */ -#define LCD_PAL50_G14_0_Msk (0x1fUL << LCD_PAL50_G14_0_Pos) /*!< LCD PAL50: G14_0 Mask */ -#define LCD_PAL50_B14_0_Pos 26 /*!< LCD PAL50: B14_0 Position */ -#define LCD_PAL50_B14_0_Msk (0x1fUL << LCD_PAL50_B14_0_Pos) /*!< LCD PAL50: B14_0 Mask */ -#define LCD_PAL50_I1_Pos 31 /*!< LCD PAL50: I1 Position */ -#define LCD_PAL50_I1_Msk (0x01UL << LCD_PAL50_I1_Pos) /*!< LCD PAL50: I1 Mask */ - -// ---------------------------------------- LCD_PAL51 ------------------------------------------- -#define LCD_PAL51_R04_0_Pos 0 /*!< LCD PAL51: R04_0 Position */ -#define LCD_PAL51_R04_0_Msk (0x1fUL << LCD_PAL51_R04_0_Pos) /*!< LCD PAL51: R04_0 Mask */ -#define LCD_PAL51_G04_0_Pos 5 /*!< LCD PAL51: G04_0 Position */ -#define LCD_PAL51_G04_0_Msk (0x1fUL << LCD_PAL51_G04_0_Pos) /*!< LCD PAL51: G04_0 Mask */ -#define LCD_PAL51_B04_0_Pos 10 /*!< LCD PAL51: B04_0 Position */ -#define LCD_PAL51_B04_0_Msk (0x1fUL << LCD_PAL51_B04_0_Pos) /*!< LCD PAL51: B04_0 Mask */ -#define LCD_PAL51_I0_Pos 15 /*!< LCD PAL51: I0 Position */ -#define LCD_PAL51_I0_Msk (0x01UL << LCD_PAL51_I0_Pos) /*!< LCD PAL51: I0 Mask */ -#define LCD_PAL51_R14_0_Pos 16 /*!< LCD PAL51: R14_0 Position */ -#define LCD_PAL51_R14_0_Msk (0x1fUL << LCD_PAL51_R14_0_Pos) /*!< LCD PAL51: R14_0 Mask */ -#define LCD_PAL51_G14_0_Pos 21 /*!< LCD PAL51: G14_0 Position */ -#define LCD_PAL51_G14_0_Msk (0x1fUL << LCD_PAL51_G14_0_Pos) /*!< LCD PAL51: G14_0 Mask */ -#define LCD_PAL51_B14_0_Pos 26 /*!< LCD PAL51: B14_0 Position */ -#define LCD_PAL51_B14_0_Msk (0x1fUL << LCD_PAL51_B14_0_Pos) /*!< LCD PAL51: B14_0 Mask */ -#define LCD_PAL51_I1_Pos 31 /*!< LCD PAL51: I1 Position */ -#define LCD_PAL51_I1_Msk (0x01UL << LCD_PAL51_I1_Pos) /*!< LCD PAL51: I1 Mask */ - -// ---------------------------------------- LCD_PAL52 ------------------------------------------- -#define LCD_PAL52_R04_0_Pos 0 /*!< LCD PAL52: R04_0 Position */ -#define LCD_PAL52_R04_0_Msk (0x1fUL << LCD_PAL52_R04_0_Pos) /*!< LCD PAL52: R04_0 Mask */ -#define LCD_PAL52_G04_0_Pos 5 /*!< LCD PAL52: G04_0 Position */ -#define LCD_PAL52_G04_0_Msk (0x1fUL << LCD_PAL52_G04_0_Pos) /*!< LCD PAL52: G04_0 Mask */ -#define LCD_PAL52_B04_0_Pos 10 /*!< LCD PAL52: B04_0 Position */ -#define LCD_PAL52_B04_0_Msk (0x1fUL << LCD_PAL52_B04_0_Pos) /*!< LCD PAL52: B04_0 Mask */ -#define LCD_PAL52_I0_Pos 15 /*!< LCD PAL52: I0 Position */ -#define LCD_PAL52_I0_Msk (0x01UL << LCD_PAL52_I0_Pos) /*!< LCD PAL52: I0 Mask */ -#define LCD_PAL52_R14_0_Pos 16 /*!< LCD PAL52: R14_0 Position */ -#define LCD_PAL52_R14_0_Msk (0x1fUL << LCD_PAL52_R14_0_Pos) /*!< LCD PAL52: R14_0 Mask */ -#define LCD_PAL52_G14_0_Pos 21 /*!< LCD PAL52: G14_0 Position */ -#define LCD_PAL52_G14_0_Msk (0x1fUL << LCD_PAL52_G14_0_Pos) /*!< LCD PAL52: G14_0 Mask */ -#define LCD_PAL52_B14_0_Pos 26 /*!< LCD PAL52: B14_0 Position */ -#define LCD_PAL52_B14_0_Msk (0x1fUL << LCD_PAL52_B14_0_Pos) /*!< LCD PAL52: B14_0 Mask */ -#define LCD_PAL52_I1_Pos 31 /*!< LCD PAL52: I1 Position */ -#define LCD_PAL52_I1_Msk (0x01UL << LCD_PAL52_I1_Pos) /*!< LCD PAL52: I1 Mask */ - -// ---------------------------------------- LCD_PAL53 ------------------------------------------- -#define LCD_PAL53_R04_0_Pos 0 /*!< LCD PAL53: R04_0 Position */ -#define LCD_PAL53_R04_0_Msk (0x1fUL << LCD_PAL53_R04_0_Pos) /*!< LCD PAL53: R04_0 Mask */ -#define LCD_PAL53_G04_0_Pos 5 /*!< LCD PAL53: G04_0 Position */ -#define LCD_PAL53_G04_0_Msk (0x1fUL << LCD_PAL53_G04_0_Pos) /*!< LCD PAL53: G04_0 Mask */ -#define LCD_PAL53_B04_0_Pos 10 /*!< LCD PAL53: B04_0 Position */ -#define LCD_PAL53_B04_0_Msk (0x1fUL << LCD_PAL53_B04_0_Pos) /*!< LCD PAL53: B04_0 Mask */ -#define LCD_PAL53_I0_Pos 15 /*!< LCD PAL53: I0 Position */ -#define LCD_PAL53_I0_Msk (0x01UL << LCD_PAL53_I0_Pos) /*!< LCD PAL53: I0 Mask */ -#define LCD_PAL53_R14_0_Pos 16 /*!< LCD PAL53: R14_0 Position */ -#define LCD_PAL53_R14_0_Msk (0x1fUL << LCD_PAL53_R14_0_Pos) /*!< LCD PAL53: R14_0 Mask */ -#define LCD_PAL53_G14_0_Pos 21 /*!< LCD PAL53: G14_0 Position */ -#define LCD_PAL53_G14_0_Msk (0x1fUL << LCD_PAL53_G14_0_Pos) /*!< LCD PAL53: G14_0 Mask */ -#define LCD_PAL53_B14_0_Pos 26 /*!< LCD PAL53: B14_0 Position */ -#define LCD_PAL53_B14_0_Msk (0x1fUL << LCD_PAL53_B14_0_Pos) /*!< LCD PAL53: B14_0 Mask */ -#define LCD_PAL53_I1_Pos 31 /*!< LCD PAL53: I1 Position */ -#define LCD_PAL53_I1_Msk (0x01UL << LCD_PAL53_I1_Pos) /*!< LCD PAL53: I1 Mask */ - -// ---------------------------------------- LCD_PAL54 ------------------------------------------- -#define LCD_PAL54_R04_0_Pos 0 /*!< LCD PAL54: R04_0 Position */ -#define LCD_PAL54_R04_0_Msk (0x1fUL << LCD_PAL54_R04_0_Pos) /*!< LCD PAL54: R04_0 Mask */ -#define LCD_PAL54_G04_0_Pos 5 /*!< LCD PAL54: G04_0 Position */ -#define LCD_PAL54_G04_0_Msk (0x1fUL << LCD_PAL54_G04_0_Pos) /*!< LCD PAL54: G04_0 Mask */ -#define LCD_PAL54_B04_0_Pos 10 /*!< LCD PAL54: B04_0 Position */ -#define LCD_PAL54_B04_0_Msk (0x1fUL << LCD_PAL54_B04_0_Pos) /*!< LCD PAL54: B04_0 Mask */ -#define LCD_PAL54_I0_Pos 15 /*!< LCD PAL54: I0 Position */ -#define LCD_PAL54_I0_Msk (0x01UL << LCD_PAL54_I0_Pos) /*!< LCD PAL54: I0 Mask */ -#define LCD_PAL54_R14_0_Pos 16 /*!< LCD PAL54: R14_0 Position */ -#define LCD_PAL54_R14_0_Msk (0x1fUL << LCD_PAL54_R14_0_Pos) /*!< LCD PAL54: R14_0 Mask */ -#define LCD_PAL54_G14_0_Pos 21 /*!< LCD PAL54: G14_0 Position */ -#define LCD_PAL54_G14_0_Msk (0x1fUL << LCD_PAL54_G14_0_Pos) /*!< LCD PAL54: G14_0 Mask */ -#define LCD_PAL54_B14_0_Pos 26 /*!< LCD PAL54: B14_0 Position */ -#define LCD_PAL54_B14_0_Msk (0x1fUL << LCD_PAL54_B14_0_Pos) /*!< LCD PAL54: B14_0 Mask */ -#define LCD_PAL54_I1_Pos 31 /*!< LCD PAL54: I1 Position */ -#define LCD_PAL54_I1_Msk (0x01UL << LCD_PAL54_I1_Pos) /*!< LCD PAL54: I1 Mask */ - -// ---------------------------------------- LCD_PAL55 ------------------------------------------- -#define LCD_PAL55_R04_0_Pos 0 /*!< LCD PAL55: R04_0 Position */ -#define LCD_PAL55_R04_0_Msk (0x1fUL << LCD_PAL55_R04_0_Pos) /*!< LCD PAL55: R04_0 Mask */ -#define LCD_PAL55_G04_0_Pos 5 /*!< LCD PAL55: G04_0 Position */ -#define LCD_PAL55_G04_0_Msk (0x1fUL << LCD_PAL55_G04_0_Pos) /*!< LCD PAL55: G04_0 Mask */ -#define LCD_PAL55_B04_0_Pos 10 /*!< LCD PAL55: B04_0 Position */ -#define LCD_PAL55_B04_0_Msk (0x1fUL << LCD_PAL55_B04_0_Pos) /*!< LCD PAL55: B04_0 Mask */ -#define LCD_PAL55_I0_Pos 15 /*!< LCD PAL55: I0 Position */ -#define LCD_PAL55_I0_Msk (0x01UL << LCD_PAL55_I0_Pos) /*!< LCD PAL55: I0 Mask */ -#define LCD_PAL55_R14_0_Pos 16 /*!< LCD PAL55: R14_0 Position */ -#define LCD_PAL55_R14_0_Msk (0x1fUL << LCD_PAL55_R14_0_Pos) /*!< LCD PAL55: R14_0 Mask */ -#define LCD_PAL55_G14_0_Pos 21 /*!< LCD PAL55: G14_0 Position */ -#define LCD_PAL55_G14_0_Msk (0x1fUL << LCD_PAL55_G14_0_Pos) /*!< LCD PAL55: G14_0 Mask */ -#define LCD_PAL55_B14_0_Pos 26 /*!< LCD PAL55: B14_0 Position */ -#define LCD_PAL55_B14_0_Msk (0x1fUL << LCD_PAL55_B14_0_Pos) /*!< LCD PAL55: B14_0 Mask */ -#define LCD_PAL55_I1_Pos 31 /*!< LCD PAL55: I1 Position */ -#define LCD_PAL55_I1_Msk (0x01UL << LCD_PAL55_I1_Pos) /*!< LCD PAL55: I1 Mask */ - -// ---------------------------------------- LCD_PAL56 ------------------------------------------- -#define LCD_PAL56_R04_0_Pos 0 /*!< LCD PAL56: R04_0 Position */ -#define LCD_PAL56_R04_0_Msk (0x1fUL << LCD_PAL56_R04_0_Pos) /*!< LCD PAL56: R04_0 Mask */ -#define LCD_PAL56_G04_0_Pos 5 /*!< LCD PAL56: G04_0 Position */ -#define LCD_PAL56_G04_0_Msk (0x1fUL << LCD_PAL56_G04_0_Pos) /*!< LCD PAL56: G04_0 Mask */ -#define LCD_PAL56_B04_0_Pos 10 /*!< LCD PAL56: B04_0 Position */ -#define LCD_PAL56_B04_0_Msk (0x1fUL << LCD_PAL56_B04_0_Pos) /*!< LCD PAL56: B04_0 Mask */ -#define LCD_PAL56_I0_Pos 15 /*!< LCD PAL56: I0 Position */ -#define LCD_PAL56_I0_Msk (0x01UL << LCD_PAL56_I0_Pos) /*!< LCD PAL56: I0 Mask */ -#define LCD_PAL56_R14_0_Pos 16 /*!< LCD PAL56: R14_0 Position */ -#define LCD_PAL56_R14_0_Msk (0x1fUL << LCD_PAL56_R14_0_Pos) /*!< LCD PAL56: R14_0 Mask */ -#define LCD_PAL56_G14_0_Pos 21 /*!< LCD PAL56: G14_0 Position */ -#define LCD_PAL56_G14_0_Msk (0x1fUL << LCD_PAL56_G14_0_Pos) /*!< LCD PAL56: G14_0 Mask */ -#define LCD_PAL56_B14_0_Pos 26 /*!< LCD PAL56: B14_0 Position */ -#define LCD_PAL56_B14_0_Msk (0x1fUL << LCD_PAL56_B14_0_Pos) /*!< LCD PAL56: B14_0 Mask */ -#define LCD_PAL56_I1_Pos 31 /*!< LCD PAL56: I1 Position */ -#define LCD_PAL56_I1_Msk (0x01UL << LCD_PAL56_I1_Pos) /*!< LCD PAL56: I1 Mask */ - -// ---------------------------------------- LCD_PAL57 ------------------------------------------- -#define LCD_PAL57_R04_0_Pos 0 /*!< LCD PAL57: R04_0 Position */ -#define LCD_PAL57_R04_0_Msk (0x1fUL << LCD_PAL57_R04_0_Pos) /*!< LCD PAL57: R04_0 Mask */ -#define LCD_PAL57_G04_0_Pos 5 /*!< LCD PAL57: G04_0 Position */ -#define LCD_PAL57_G04_0_Msk (0x1fUL << LCD_PAL57_G04_0_Pos) /*!< LCD PAL57: G04_0 Mask */ -#define LCD_PAL57_B04_0_Pos 10 /*!< LCD PAL57: B04_0 Position */ -#define LCD_PAL57_B04_0_Msk (0x1fUL << LCD_PAL57_B04_0_Pos) /*!< LCD PAL57: B04_0 Mask */ -#define LCD_PAL57_I0_Pos 15 /*!< LCD PAL57: I0 Position */ -#define LCD_PAL57_I0_Msk (0x01UL << LCD_PAL57_I0_Pos) /*!< LCD PAL57: I0 Mask */ -#define LCD_PAL57_R14_0_Pos 16 /*!< LCD PAL57: R14_0 Position */ -#define LCD_PAL57_R14_0_Msk (0x1fUL << LCD_PAL57_R14_0_Pos) /*!< LCD PAL57: R14_0 Mask */ -#define LCD_PAL57_G14_0_Pos 21 /*!< LCD PAL57: G14_0 Position */ -#define LCD_PAL57_G14_0_Msk (0x1fUL << LCD_PAL57_G14_0_Pos) /*!< LCD PAL57: G14_0 Mask */ -#define LCD_PAL57_B14_0_Pos 26 /*!< LCD PAL57: B14_0 Position */ -#define LCD_PAL57_B14_0_Msk (0x1fUL << LCD_PAL57_B14_0_Pos) /*!< LCD PAL57: B14_0 Mask */ -#define LCD_PAL57_I1_Pos 31 /*!< LCD PAL57: I1 Position */ -#define LCD_PAL57_I1_Msk (0x01UL << LCD_PAL57_I1_Pos) /*!< LCD PAL57: I1 Mask */ - -// ---------------------------------------- LCD_PAL58 ------------------------------------------- -#define LCD_PAL58_R04_0_Pos 0 /*!< LCD PAL58: R04_0 Position */ -#define LCD_PAL58_R04_0_Msk (0x1fUL << LCD_PAL58_R04_0_Pos) /*!< LCD PAL58: R04_0 Mask */ -#define LCD_PAL58_G04_0_Pos 5 /*!< LCD PAL58: G04_0 Position */ -#define LCD_PAL58_G04_0_Msk (0x1fUL << LCD_PAL58_G04_0_Pos) /*!< LCD PAL58: G04_0 Mask */ -#define LCD_PAL58_B04_0_Pos 10 /*!< LCD PAL58: B04_0 Position */ -#define LCD_PAL58_B04_0_Msk (0x1fUL << LCD_PAL58_B04_0_Pos) /*!< LCD PAL58: B04_0 Mask */ -#define LCD_PAL58_I0_Pos 15 /*!< LCD PAL58: I0 Position */ -#define LCD_PAL58_I0_Msk (0x01UL << LCD_PAL58_I0_Pos) /*!< LCD PAL58: I0 Mask */ -#define LCD_PAL58_R14_0_Pos 16 /*!< LCD PAL58: R14_0 Position */ -#define LCD_PAL58_R14_0_Msk (0x1fUL << LCD_PAL58_R14_0_Pos) /*!< LCD PAL58: R14_0 Mask */ -#define LCD_PAL58_G14_0_Pos 21 /*!< LCD PAL58: G14_0 Position */ -#define LCD_PAL58_G14_0_Msk (0x1fUL << LCD_PAL58_G14_0_Pos) /*!< LCD PAL58: G14_0 Mask */ -#define LCD_PAL58_B14_0_Pos 26 /*!< LCD PAL58: B14_0 Position */ -#define LCD_PAL58_B14_0_Msk (0x1fUL << LCD_PAL58_B14_0_Pos) /*!< LCD PAL58: B14_0 Mask */ -#define LCD_PAL58_I1_Pos 31 /*!< LCD PAL58: I1 Position */ -#define LCD_PAL58_I1_Msk (0x01UL << LCD_PAL58_I1_Pos) /*!< LCD PAL58: I1 Mask */ - -// ---------------------------------------- LCD_PAL59 ------------------------------------------- -#define LCD_PAL59_R04_0_Pos 0 /*!< LCD PAL59: R04_0 Position */ -#define LCD_PAL59_R04_0_Msk (0x1fUL << LCD_PAL59_R04_0_Pos) /*!< LCD PAL59: R04_0 Mask */ -#define LCD_PAL59_G04_0_Pos 5 /*!< LCD PAL59: G04_0 Position */ -#define LCD_PAL59_G04_0_Msk (0x1fUL << LCD_PAL59_G04_0_Pos) /*!< LCD PAL59: G04_0 Mask */ -#define LCD_PAL59_B04_0_Pos 10 /*!< LCD PAL59: B04_0 Position */ -#define LCD_PAL59_B04_0_Msk (0x1fUL << LCD_PAL59_B04_0_Pos) /*!< LCD PAL59: B04_0 Mask */ -#define LCD_PAL59_I0_Pos 15 /*!< LCD PAL59: I0 Position */ -#define LCD_PAL59_I0_Msk (0x01UL << LCD_PAL59_I0_Pos) /*!< LCD PAL59: I0 Mask */ -#define LCD_PAL59_R14_0_Pos 16 /*!< LCD PAL59: R14_0 Position */ -#define LCD_PAL59_R14_0_Msk (0x1fUL << LCD_PAL59_R14_0_Pos) /*!< LCD PAL59: R14_0 Mask */ -#define LCD_PAL59_G14_0_Pos 21 /*!< LCD PAL59: G14_0 Position */ -#define LCD_PAL59_G14_0_Msk (0x1fUL << LCD_PAL59_G14_0_Pos) /*!< LCD PAL59: G14_0 Mask */ -#define LCD_PAL59_B14_0_Pos 26 /*!< LCD PAL59: B14_0 Position */ -#define LCD_PAL59_B14_0_Msk (0x1fUL << LCD_PAL59_B14_0_Pos) /*!< LCD PAL59: B14_0 Mask */ -#define LCD_PAL59_I1_Pos 31 /*!< LCD PAL59: I1 Position */ -#define LCD_PAL59_I1_Msk (0x01UL << LCD_PAL59_I1_Pos) /*!< LCD PAL59: I1 Mask */ - -// ---------------------------------------- LCD_PAL60 ------------------------------------------- -#define LCD_PAL60_R04_0_Pos 0 /*!< LCD PAL60: R04_0 Position */ -#define LCD_PAL60_R04_0_Msk (0x1fUL << LCD_PAL60_R04_0_Pos) /*!< LCD PAL60: R04_0 Mask */ -#define LCD_PAL60_G04_0_Pos 5 /*!< LCD PAL60: G04_0 Position */ -#define LCD_PAL60_G04_0_Msk (0x1fUL << LCD_PAL60_G04_0_Pos) /*!< LCD PAL60: G04_0 Mask */ -#define LCD_PAL60_B04_0_Pos 10 /*!< LCD PAL60: B04_0 Position */ -#define LCD_PAL60_B04_0_Msk (0x1fUL << LCD_PAL60_B04_0_Pos) /*!< LCD PAL60: B04_0 Mask */ -#define LCD_PAL60_I0_Pos 15 /*!< LCD PAL60: I0 Position */ -#define LCD_PAL60_I0_Msk (0x01UL << LCD_PAL60_I0_Pos) /*!< LCD PAL60: I0 Mask */ -#define LCD_PAL60_R14_0_Pos 16 /*!< LCD PAL60: R14_0 Position */ -#define LCD_PAL60_R14_0_Msk (0x1fUL << LCD_PAL60_R14_0_Pos) /*!< LCD PAL60: R14_0 Mask */ -#define LCD_PAL60_G14_0_Pos 21 /*!< LCD PAL60: G14_0 Position */ -#define LCD_PAL60_G14_0_Msk (0x1fUL << LCD_PAL60_G14_0_Pos) /*!< LCD PAL60: G14_0 Mask */ -#define LCD_PAL60_B14_0_Pos 26 /*!< LCD PAL60: B14_0 Position */ -#define LCD_PAL60_B14_0_Msk (0x1fUL << LCD_PAL60_B14_0_Pos) /*!< LCD PAL60: B14_0 Mask */ -#define LCD_PAL60_I1_Pos 31 /*!< LCD PAL60: I1 Position */ -#define LCD_PAL60_I1_Msk (0x01UL << LCD_PAL60_I1_Pos) /*!< LCD PAL60: I1 Mask */ - -// ---------------------------------------- LCD_PAL61 ------------------------------------------- -#define LCD_PAL61_R04_0_Pos 0 /*!< LCD PAL61: R04_0 Position */ -#define LCD_PAL61_R04_0_Msk (0x1fUL << LCD_PAL61_R04_0_Pos) /*!< LCD PAL61: R04_0 Mask */ -#define LCD_PAL61_G04_0_Pos 5 /*!< LCD PAL61: G04_0 Position */ -#define LCD_PAL61_G04_0_Msk (0x1fUL << LCD_PAL61_G04_0_Pos) /*!< LCD PAL61: G04_0 Mask */ -#define LCD_PAL61_B04_0_Pos 10 /*!< LCD PAL61: B04_0 Position */ -#define LCD_PAL61_B04_0_Msk (0x1fUL << LCD_PAL61_B04_0_Pos) /*!< LCD PAL61: B04_0 Mask */ -#define LCD_PAL61_I0_Pos 15 /*!< LCD PAL61: I0 Position */ -#define LCD_PAL61_I0_Msk (0x01UL << LCD_PAL61_I0_Pos) /*!< LCD PAL61: I0 Mask */ -#define LCD_PAL61_R14_0_Pos 16 /*!< LCD PAL61: R14_0 Position */ -#define LCD_PAL61_R14_0_Msk (0x1fUL << LCD_PAL61_R14_0_Pos) /*!< LCD PAL61: R14_0 Mask */ -#define LCD_PAL61_G14_0_Pos 21 /*!< LCD PAL61: G14_0 Position */ -#define LCD_PAL61_G14_0_Msk (0x1fUL << LCD_PAL61_G14_0_Pos) /*!< LCD PAL61: G14_0 Mask */ -#define LCD_PAL61_B14_0_Pos 26 /*!< LCD PAL61: B14_0 Position */ -#define LCD_PAL61_B14_0_Msk (0x1fUL << LCD_PAL61_B14_0_Pos) /*!< LCD PAL61: B14_0 Mask */ -#define LCD_PAL61_I1_Pos 31 /*!< LCD PAL61: I1 Position */ -#define LCD_PAL61_I1_Msk (0x01UL << LCD_PAL61_I1_Pos) /*!< LCD PAL61: I1 Mask */ - -// ---------------------------------------- LCD_PAL62 ------------------------------------------- -#define LCD_PAL62_R04_0_Pos 0 /*!< LCD PAL62: R04_0 Position */ -#define LCD_PAL62_R04_0_Msk (0x1fUL << LCD_PAL62_R04_0_Pos) /*!< LCD PAL62: R04_0 Mask */ -#define LCD_PAL62_G04_0_Pos 5 /*!< LCD PAL62: G04_0 Position */ -#define LCD_PAL62_G04_0_Msk (0x1fUL << LCD_PAL62_G04_0_Pos) /*!< LCD PAL62: G04_0 Mask */ -#define LCD_PAL62_B04_0_Pos 10 /*!< LCD PAL62: B04_0 Position */ -#define LCD_PAL62_B04_0_Msk (0x1fUL << LCD_PAL62_B04_0_Pos) /*!< LCD PAL62: B04_0 Mask */ -#define LCD_PAL62_I0_Pos 15 /*!< LCD PAL62: I0 Position */ -#define LCD_PAL62_I0_Msk (0x01UL << LCD_PAL62_I0_Pos) /*!< LCD PAL62: I0 Mask */ -#define LCD_PAL62_R14_0_Pos 16 /*!< LCD PAL62: R14_0 Position */ -#define LCD_PAL62_R14_0_Msk (0x1fUL << LCD_PAL62_R14_0_Pos) /*!< LCD PAL62: R14_0 Mask */ -#define LCD_PAL62_G14_0_Pos 21 /*!< LCD PAL62: G14_0 Position */ -#define LCD_PAL62_G14_0_Msk (0x1fUL << LCD_PAL62_G14_0_Pos) /*!< LCD PAL62: G14_0 Mask */ -#define LCD_PAL62_B14_0_Pos 26 /*!< LCD PAL62: B14_0 Position */ -#define LCD_PAL62_B14_0_Msk (0x1fUL << LCD_PAL62_B14_0_Pos) /*!< LCD PAL62: B14_0 Mask */ -#define LCD_PAL62_I1_Pos 31 /*!< LCD PAL62: I1 Position */ -#define LCD_PAL62_I1_Msk (0x01UL << LCD_PAL62_I1_Pos) /*!< LCD PAL62: I1 Mask */ - -// ---------------------------------------- LCD_PAL63 ------------------------------------------- -#define LCD_PAL63_R04_0_Pos 0 /*!< LCD PAL63: R04_0 Position */ -#define LCD_PAL63_R04_0_Msk (0x1fUL << LCD_PAL63_R04_0_Pos) /*!< LCD PAL63: R04_0 Mask */ -#define LCD_PAL63_G04_0_Pos 5 /*!< LCD PAL63: G04_0 Position */ -#define LCD_PAL63_G04_0_Msk (0x1fUL << LCD_PAL63_G04_0_Pos) /*!< LCD PAL63: G04_0 Mask */ -#define LCD_PAL63_B04_0_Pos 10 /*!< LCD PAL63: B04_0 Position */ -#define LCD_PAL63_B04_0_Msk (0x1fUL << LCD_PAL63_B04_0_Pos) /*!< LCD PAL63: B04_0 Mask */ -#define LCD_PAL63_I0_Pos 15 /*!< LCD PAL63: I0 Position */ -#define LCD_PAL63_I0_Msk (0x01UL << LCD_PAL63_I0_Pos) /*!< LCD PAL63: I0 Mask */ -#define LCD_PAL63_R14_0_Pos 16 /*!< LCD PAL63: R14_0 Position */ -#define LCD_PAL63_R14_0_Msk (0x1fUL << LCD_PAL63_R14_0_Pos) /*!< LCD PAL63: R14_0 Mask */ -#define LCD_PAL63_G14_0_Pos 21 /*!< LCD PAL63: G14_0 Position */ -#define LCD_PAL63_G14_0_Msk (0x1fUL << LCD_PAL63_G14_0_Pos) /*!< LCD PAL63: G14_0 Mask */ -#define LCD_PAL63_B14_0_Pos 26 /*!< LCD PAL63: B14_0 Position */ -#define LCD_PAL63_B14_0_Msk (0x1fUL << LCD_PAL63_B14_0_Pos) /*!< LCD PAL63: B14_0 Mask */ -#define LCD_PAL63_I1_Pos 31 /*!< LCD PAL63: I1 Position */ -#define LCD_PAL63_I1_Msk (0x01UL << LCD_PAL63_I1_Pos) /*!< LCD PAL63: I1 Mask */ - -// ---------------------------------------- LCD_PAL64 ------------------------------------------- -#define LCD_PAL64_R04_0_Pos 0 /*!< LCD PAL64: R04_0 Position */ -#define LCD_PAL64_R04_0_Msk (0x1fUL << LCD_PAL64_R04_0_Pos) /*!< LCD PAL64: R04_0 Mask */ -#define LCD_PAL64_G04_0_Pos 5 /*!< LCD PAL64: G04_0 Position */ -#define LCD_PAL64_G04_0_Msk (0x1fUL << LCD_PAL64_G04_0_Pos) /*!< LCD PAL64: G04_0 Mask */ -#define LCD_PAL64_B04_0_Pos 10 /*!< LCD PAL64: B04_0 Position */ -#define LCD_PAL64_B04_0_Msk (0x1fUL << LCD_PAL64_B04_0_Pos) /*!< LCD PAL64: B04_0 Mask */ -#define LCD_PAL64_I0_Pos 15 /*!< LCD PAL64: I0 Position */ -#define LCD_PAL64_I0_Msk (0x01UL << LCD_PAL64_I0_Pos) /*!< LCD PAL64: I0 Mask */ -#define LCD_PAL64_R14_0_Pos 16 /*!< LCD PAL64: R14_0 Position */ -#define LCD_PAL64_R14_0_Msk (0x1fUL << LCD_PAL64_R14_0_Pos) /*!< LCD PAL64: R14_0 Mask */ -#define LCD_PAL64_G14_0_Pos 21 /*!< LCD PAL64: G14_0 Position */ -#define LCD_PAL64_G14_0_Msk (0x1fUL << LCD_PAL64_G14_0_Pos) /*!< LCD PAL64: G14_0 Mask */ -#define LCD_PAL64_B14_0_Pos 26 /*!< LCD PAL64: B14_0 Position */ -#define LCD_PAL64_B14_0_Msk (0x1fUL << LCD_PAL64_B14_0_Pos) /*!< LCD PAL64: B14_0 Mask */ -#define LCD_PAL64_I1_Pos 31 /*!< LCD PAL64: I1 Position */ -#define LCD_PAL64_I1_Msk (0x01UL << LCD_PAL64_I1_Pos) /*!< LCD PAL64: I1 Mask */ - -// ---------------------------------------- LCD_PAL65 ------------------------------------------- -#define LCD_PAL65_R04_0_Pos 0 /*!< LCD PAL65: R04_0 Position */ -#define LCD_PAL65_R04_0_Msk (0x1fUL << LCD_PAL65_R04_0_Pos) /*!< LCD PAL65: R04_0 Mask */ -#define LCD_PAL65_G04_0_Pos 5 /*!< LCD PAL65: G04_0 Position */ -#define LCD_PAL65_G04_0_Msk (0x1fUL << LCD_PAL65_G04_0_Pos) /*!< LCD PAL65: G04_0 Mask */ -#define LCD_PAL65_B04_0_Pos 10 /*!< LCD PAL65: B04_0 Position */ -#define LCD_PAL65_B04_0_Msk (0x1fUL << LCD_PAL65_B04_0_Pos) /*!< LCD PAL65: B04_0 Mask */ -#define LCD_PAL65_I0_Pos 15 /*!< LCD PAL65: I0 Position */ -#define LCD_PAL65_I0_Msk (0x01UL << LCD_PAL65_I0_Pos) /*!< LCD PAL65: I0 Mask */ -#define LCD_PAL65_R14_0_Pos 16 /*!< LCD PAL65: R14_0 Position */ -#define LCD_PAL65_R14_0_Msk (0x1fUL << LCD_PAL65_R14_0_Pos) /*!< LCD PAL65: R14_0 Mask */ -#define LCD_PAL65_G14_0_Pos 21 /*!< LCD PAL65: G14_0 Position */ -#define LCD_PAL65_G14_0_Msk (0x1fUL << LCD_PAL65_G14_0_Pos) /*!< LCD PAL65: G14_0 Mask */ -#define LCD_PAL65_B14_0_Pos 26 /*!< LCD PAL65: B14_0 Position */ -#define LCD_PAL65_B14_0_Msk (0x1fUL << LCD_PAL65_B14_0_Pos) /*!< LCD PAL65: B14_0 Mask */ -#define LCD_PAL65_I1_Pos 31 /*!< LCD PAL65: I1 Position */ -#define LCD_PAL65_I1_Msk (0x01UL << LCD_PAL65_I1_Pos) /*!< LCD PAL65: I1 Mask */ - -// ---------------------------------------- LCD_PAL66 ------------------------------------------- -#define LCD_PAL66_R04_0_Pos 0 /*!< LCD PAL66: R04_0 Position */ -#define LCD_PAL66_R04_0_Msk (0x1fUL << LCD_PAL66_R04_0_Pos) /*!< LCD PAL66: R04_0 Mask */ -#define LCD_PAL66_G04_0_Pos 5 /*!< LCD PAL66: G04_0 Position */ -#define LCD_PAL66_G04_0_Msk (0x1fUL << LCD_PAL66_G04_0_Pos) /*!< LCD PAL66: G04_0 Mask */ -#define LCD_PAL66_B04_0_Pos 10 /*!< LCD PAL66: B04_0 Position */ -#define LCD_PAL66_B04_0_Msk (0x1fUL << LCD_PAL66_B04_0_Pos) /*!< LCD PAL66: B04_0 Mask */ -#define LCD_PAL66_I0_Pos 15 /*!< LCD PAL66: I0 Position */ -#define LCD_PAL66_I0_Msk (0x01UL << LCD_PAL66_I0_Pos) /*!< LCD PAL66: I0 Mask */ -#define LCD_PAL66_R14_0_Pos 16 /*!< LCD PAL66: R14_0 Position */ -#define LCD_PAL66_R14_0_Msk (0x1fUL << LCD_PAL66_R14_0_Pos) /*!< LCD PAL66: R14_0 Mask */ -#define LCD_PAL66_G14_0_Pos 21 /*!< LCD PAL66: G14_0 Position */ -#define LCD_PAL66_G14_0_Msk (0x1fUL << LCD_PAL66_G14_0_Pos) /*!< LCD PAL66: G14_0 Mask */ -#define LCD_PAL66_B14_0_Pos 26 /*!< LCD PAL66: B14_0 Position */ -#define LCD_PAL66_B14_0_Msk (0x1fUL << LCD_PAL66_B14_0_Pos) /*!< LCD PAL66: B14_0 Mask */ -#define LCD_PAL66_I1_Pos 31 /*!< LCD PAL66: I1 Position */ -#define LCD_PAL66_I1_Msk (0x01UL << LCD_PAL66_I1_Pos) /*!< LCD PAL66: I1 Mask */ - -// ---------------------------------------- LCD_PAL67 ------------------------------------------- -#define LCD_PAL67_R04_0_Pos 0 /*!< LCD PAL67: R04_0 Position */ -#define LCD_PAL67_R04_0_Msk (0x1fUL << LCD_PAL67_R04_0_Pos) /*!< LCD PAL67: R04_0 Mask */ -#define LCD_PAL67_G04_0_Pos 5 /*!< LCD PAL67: G04_0 Position */ -#define LCD_PAL67_G04_0_Msk (0x1fUL << LCD_PAL67_G04_0_Pos) /*!< LCD PAL67: G04_0 Mask */ -#define LCD_PAL67_B04_0_Pos 10 /*!< LCD PAL67: B04_0 Position */ -#define LCD_PAL67_B04_0_Msk (0x1fUL << LCD_PAL67_B04_0_Pos) /*!< LCD PAL67: B04_0 Mask */ -#define LCD_PAL67_I0_Pos 15 /*!< LCD PAL67: I0 Position */ -#define LCD_PAL67_I0_Msk (0x01UL << LCD_PAL67_I0_Pos) /*!< LCD PAL67: I0 Mask */ -#define LCD_PAL67_R14_0_Pos 16 /*!< LCD PAL67: R14_0 Position */ -#define LCD_PAL67_R14_0_Msk (0x1fUL << LCD_PAL67_R14_0_Pos) /*!< LCD PAL67: R14_0 Mask */ -#define LCD_PAL67_G14_0_Pos 21 /*!< LCD PAL67: G14_0 Position */ -#define LCD_PAL67_G14_0_Msk (0x1fUL << LCD_PAL67_G14_0_Pos) /*!< LCD PAL67: G14_0 Mask */ -#define LCD_PAL67_B14_0_Pos 26 /*!< LCD PAL67: B14_0 Position */ -#define LCD_PAL67_B14_0_Msk (0x1fUL << LCD_PAL67_B14_0_Pos) /*!< LCD PAL67: B14_0 Mask */ -#define LCD_PAL67_I1_Pos 31 /*!< LCD PAL67: I1 Position */ -#define LCD_PAL67_I1_Msk (0x01UL << LCD_PAL67_I1_Pos) /*!< LCD PAL67: I1 Mask */ - -// ---------------------------------------- LCD_PAL68 ------------------------------------------- -#define LCD_PAL68_R04_0_Pos 0 /*!< LCD PAL68: R04_0 Position */ -#define LCD_PAL68_R04_0_Msk (0x1fUL << LCD_PAL68_R04_0_Pos) /*!< LCD PAL68: R04_0 Mask */ -#define LCD_PAL68_G04_0_Pos 5 /*!< LCD PAL68: G04_0 Position */ -#define LCD_PAL68_G04_0_Msk (0x1fUL << LCD_PAL68_G04_0_Pos) /*!< LCD PAL68: G04_0 Mask */ -#define LCD_PAL68_B04_0_Pos 10 /*!< LCD PAL68: B04_0 Position */ -#define LCD_PAL68_B04_0_Msk (0x1fUL << LCD_PAL68_B04_0_Pos) /*!< LCD PAL68: B04_0 Mask */ -#define LCD_PAL68_I0_Pos 15 /*!< LCD PAL68: I0 Position */ -#define LCD_PAL68_I0_Msk (0x01UL << LCD_PAL68_I0_Pos) /*!< LCD PAL68: I0 Mask */ -#define LCD_PAL68_R14_0_Pos 16 /*!< LCD PAL68: R14_0 Position */ -#define LCD_PAL68_R14_0_Msk (0x1fUL << LCD_PAL68_R14_0_Pos) /*!< LCD PAL68: R14_0 Mask */ -#define LCD_PAL68_G14_0_Pos 21 /*!< LCD PAL68: G14_0 Position */ -#define LCD_PAL68_G14_0_Msk (0x1fUL << LCD_PAL68_G14_0_Pos) /*!< LCD PAL68: G14_0 Mask */ -#define LCD_PAL68_B14_0_Pos 26 /*!< LCD PAL68: B14_0 Position */ -#define LCD_PAL68_B14_0_Msk (0x1fUL << LCD_PAL68_B14_0_Pos) /*!< LCD PAL68: B14_0 Mask */ -#define LCD_PAL68_I1_Pos 31 /*!< LCD PAL68: I1 Position */ -#define LCD_PAL68_I1_Msk (0x01UL << LCD_PAL68_I1_Pos) /*!< LCD PAL68: I1 Mask */ - -// ---------------------------------------- LCD_PAL69 ------------------------------------------- -#define LCD_PAL69_R04_0_Pos 0 /*!< LCD PAL69: R04_0 Position */ -#define LCD_PAL69_R04_0_Msk (0x1fUL << LCD_PAL69_R04_0_Pos) /*!< LCD PAL69: R04_0 Mask */ -#define LCD_PAL69_G04_0_Pos 5 /*!< LCD PAL69: G04_0 Position */ -#define LCD_PAL69_G04_0_Msk (0x1fUL << LCD_PAL69_G04_0_Pos) /*!< LCD PAL69: G04_0 Mask */ -#define LCD_PAL69_B04_0_Pos 10 /*!< LCD PAL69: B04_0 Position */ -#define LCD_PAL69_B04_0_Msk (0x1fUL << LCD_PAL69_B04_0_Pos) /*!< LCD PAL69: B04_0 Mask */ -#define LCD_PAL69_I0_Pos 15 /*!< LCD PAL69: I0 Position */ -#define LCD_PAL69_I0_Msk (0x01UL << LCD_PAL69_I0_Pos) /*!< LCD PAL69: I0 Mask */ -#define LCD_PAL69_R14_0_Pos 16 /*!< LCD PAL69: R14_0 Position */ -#define LCD_PAL69_R14_0_Msk (0x1fUL << LCD_PAL69_R14_0_Pos) /*!< LCD PAL69: R14_0 Mask */ -#define LCD_PAL69_G14_0_Pos 21 /*!< LCD PAL69: G14_0 Position */ -#define LCD_PAL69_G14_0_Msk (0x1fUL << LCD_PAL69_G14_0_Pos) /*!< LCD PAL69: G14_0 Mask */ -#define LCD_PAL69_B14_0_Pos 26 /*!< LCD PAL69: B14_0 Position */ -#define LCD_PAL69_B14_0_Msk (0x1fUL << LCD_PAL69_B14_0_Pos) /*!< LCD PAL69: B14_0 Mask */ -#define LCD_PAL69_I1_Pos 31 /*!< LCD PAL69: I1 Position */ -#define LCD_PAL69_I1_Msk (0x01UL << LCD_PAL69_I1_Pos) /*!< LCD PAL69: I1 Mask */ - -// ---------------------------------------- LCD_PAL70 ------------------------------------------- -#define LCD_PAL70_R04_0_Pos 0 /*!< LCD PAL70: R04_0 Position */ -#define LCD_PAL70_R04_0_Msk (0x1fUL << LCD_PAL70_R04_0_Pos) /*!< LCD PAL70: R04_0 Mask */ -#define LCD_PAL70_G04_0_Pos 5 /*!< LCD PAL70: G04_0 Position */ -#define LCD_PAL70_G04_0_Msk (0x1fUL << LCD_PAL70_G04_0_Pos) /*!< LCD PAL70: G04_0 Mask */ -#define LCD_PAL70_B04_0_Pos 10 /*!< LCD PAL70: B04_0 Position */ -#define LCD_PAL70_B04_0_Msk (0x1fUL << LCD_PAL70_B04_0_Pos) /*!< LCD PAL70: B04_0 Mask */ -#define LCD_PAL70_I0_Pos 15 /*!< LCD PAL70: I0 Position */ -#define LCD_PAL70_I0_Msk (0x01UL << LCD_PAL70_I0_Pos) /*!< LCD PAL70: I0 Mask */ -#define LCD_PAL70_R14_0_Pos 16 /*!< LCD PAL70: R14_0 Position */ -#define LCD_PAL70_R14_0_Msk (0x1fUL << LCD_PAL70_R14_0_Pos) /*!< LCD PAL70: R14_0 Mask */ -#define LCD_PAL70_G14_0_Pos 21 /*!< LCD PAL70: G14_0 Position */ -#define LCD_PAL70_G14_0_Msk (0x1fUL << LCD_PAL70_G14_0_Pos) /*!< LCD PAL70: G14_0 Mask */ -#define LCD_PAL70_B14_0_Pos 26 /*!< LCD PAL70: B14_0 Position */ -#define LCD_PAL70_B14_0_Msk (0x1fUL << LCD_PAL70_B14_0_Pos) /*!< LCD PAL70: B14_0 Mask */ -#define LCD_PAL70_I1_Pos 31 /*!< LCD PAL70: I1 Position */ -#define LCD_PAL70_I1_Msk (0x01UL << LCD_PAL70_I1_Pos) /*!< LCD PAL70: I1 Mask */ - -// ---------------------------------------- LCD_PAL71 ------------------------------------------- -#define LCD_PAL71_R04_0_Pos 0 /*!< LCD PAL71: R04_0 Position */ -#define LCD_PAL71_R04_0_Msk (0x1fUL << LCD_PAL71_R04_0_Pos) /*!< LCD PAL71: R04_0 Mask */ -#define LCD_PAL71_G04_0_Pos 5 /*!< LCD PAL71: G04_0 Position */ -#define LCD_PAL71_G04_0_Msk (0x1fUL << LCD_PAL71_G04_0_Pos) /*!< LCD PAL71: G04_0 Mask */ -#define LCD_PAL71_B04_0_Pos 10 /*!< LCD PAL71: B04_0 Position */ -#define LCD_PAL71_B04_0_Msk (0x1fUL << LCD_PAL71_B04_0_Pos) /*!< LCD PAL71: B04_0 Mask */ -#define LCD_PAL71_I0_Pos 15 /*!< LCD PAL71: I0 Position */ -#define LCD_PAL71_I0_Msk (0x01UL << LCD_PAL71_I0_Pos) /*!< LCD PAL71: I0 Mask */ -#define LCD_PAL71_R14_0_Pos 16 /*!< LCD PAL71: R14_0 Position */ -#define LCD_PAL71_R14_0_Msk (0x1fUL << LCD_PAL71_R14_0_Pos) /*!< LCD PAL71: R14_0 Mask */ -#define LCD_PAL71_G14_0_Pos 21 /*!< LCD PAL71: G14_0 Position */ -#define LCD_PAL71_G14_0_Msk (0x1fUL << LCD_PAL71_G14_0_Pos) /*!< LCD PAL71: G14_0 Mask */ -#define LCD_PAL71_B14_0_Pos 26 /*!< LCD PAL71: B14_0 Position */ -#define LCD_PAL71_B14_0_Msk (0x1fUL << LCD_PAL71_B14_0_Pos) /*!< LCD PAL71: B14_0 Mask */ -#define LCD_PAL71_I1_Pos 31 /*!< LCD PAL71: I1 Position */ -#define LCD_PAL71_I1_Msk (0x01UL << LCD_PAL71_I1_Pos) /*!< LCD PAL71: I1 Mask */ - -// ---------------------------------------- LCD_PAL72 ------------------------------------------- -#define LCD_PAL72_R04_0_Pos 0 /*!< LCD PAL72: R04_0 Position */ -#define LCD_PAL72_R04_0_Msk (0x1fUL << LCD_PAL72_R04_0_Pos) /*!< LCD PAL72: R04_0 Mask */ -#define LCD_PAL72_G04_0_Pos 5 /*!< LCD PAL72: G04_0 Position */ -#define LCD_PAL72_G04_0_Msk (0x1fUL << LCD_PAL72_G04_0_Pos) /*!< LCD PAL72: G04_0 Mask */ -#define LCD_PAL72_B04_0_Pos 10 /*!< LCD PAL72: B04_0 Position */ -#define LCD_PAL72_B04_0_Msk (0x1fUL << LCD_PAL72_B04_0_Pos) /*!< LCD PAL72: B04_0 Mask */ -#define LCD_PAL72_I0_Pos 15 /*!< LCD PAL72: I0 Position */ -#define LCD_PAL72_I0_Msk (0x01UL << LCD_PAL72_I0_Pos) /*!< LCD PAL72: I0 Mask */ -#define LCD_PAL72_R14_0_Pos 16 /*!< LCD PAL72: R14_0 Position */ -#define LCD_PAL72_R14_0_Msk (0x1fUL << LCD_PAL72_R14_0_Pos) /*!< LCD PAL72: R14_0 Mask */ -#define LCD_PAL72_G14_0_Pos 21 /*!< LCD PAL72: G14_0 Position */ -#define LCD_PAL72_G14_0_Msk (0x1fUL << LCD_PAL72_G14_0_Pos) /*!< LCD PAL72: G14_0 Mask */ -#define LCD_PAL72_B14_0_Pos 26 /*!< LCD PAL72: B14_0 Position */ -#define LCD_PAL72_B14_0_Msk (0x1fUL << LCD_PAL72_B14_0_Pos) /*!< LCD PAL72: B14_0 Mask */ -#define LCD_PAL72_I1_Pos 31 /*!< LCD PAL72: I1 Position */ -#define LCD_PAL72_I1_Msk (0x01UL << LCD_PAL72_I1_Pos) /*!< LCD PAL72: I1 Mask */ - -// ---------------------------------------- LCD_PAL73 ------------------------------------------- -#define LCD_PAL73_R04_0_Pos 0 /*!< LCD PAL73: R04_0 Position */ -#define LCD_PAL73_R04_0_Msk (0x1fUL << LCD_PAL73_R04_0_Pos) /*!< LCD PAL73: R04_0 Mask */ -#define LCD_PAL73_G04_0_Pos 5 /*!< LCD PAL73: G04_0 Position */ -#define LCD_PAL73_G04_0_Msk (0x1fUL << LCD_PAL73_G04_0_Pos) /*!< LCD PAL73: G04_0 Mask */ -#define LCD_PAL73_B04_0_Pos 10 /*!< LCD PAL73: B04_0 Position */ -#define LCD_PAL73_B04_0_Msk (0x1fUL << LCD_PAL73_B04_0_Pos) /*!< LCD PAL73: B04_0 Mask */ -#define LCD_PAL73_I0_Pos 15 /*!< LCD PAL73: I0 Position */ -#define LCD_PAL73_I0_Msk (0x01UL << LCD_PAL73_I0_Pos) /*!< LCD PAL73: I0 Mask */ -#define LCD_PAL73_R14_0_Pos 16 /*!< LCD PAL73: R14_0 Position */ -#define LCD_PAL73_R14_0_Msk (0x1fUL << LCD_PAL73_R14_0_Pos) /*!< LCD PAL73: R14_0 Mask */ -#define LCD_PAL73_G14_0_Pos 21 /*!< LCD PAL73: G14_0 Position */ -#define LCD_PAL73_G14_0_Msk (0x1fUL << LCD_PAL73_G14_0_Pos) /*!< LCD PAL73: G14_0 Mask */ -#define LCD_PAL73_B14_0_Pos 26 /*!< LCD PAL73: B14_0 Position */ -#define LCD_PAL73_B14_0_Msk (0x1fUL << LCD_PAL73_B14_0_Pos) /*!< LCD PAL73: B14_0 Mask */ -#define LCD_PAL73_I1_Pos 31 /*!< LCD PAL73: I1 Position */ -#define LCD_PAL73_I1_Msk (0x01UL << LCD_PAL73_I1_Pos) /*!< LCD PAL73: I1 Mask */ - -// ---------------------------------------- LCD_PAL74 ------------------------------------------- -#define LCD_PAL74_R04_0_Pos 0 /*!< LCD PAL74: R04_0 Position */ -#define LCD_PAL74_R04_0_Msk (0x1fUL << LCD_PAL74_R04_0_Pos) /*!< LCD PAL74: R04_0 Mask */ -#define LCD_PAL74_G04_0_Pos 5 /*!< LCD PAL74: G04_0 Position */ -#define LCD_PAL74_G04_0_Msk (0x1fUL << LCD_PAL74_G04_0_Pos) /*!< LCD PAL74: G04_0 Mask */ -#define LCD_PAL74_B04_0_Pos 10 /*!< LCD PAL74: B04_0 Position */ -#define LCD_PAL74_B04_0_Msk (0x1fUL << LCD_PAL74_B04_0_Pos) /*!< LCD PAL74: B04_0 Mask */ -#define LCD_PAL74_I0_Pos 15 /*!< LCD PAL74: I0 Position */ -#define LCD_PAL74_I0_Msk (0x01UL << LCD_PAL74_I0_Pos) /*!< LCD PAL74: I0 Mask */ -#define LCD_PAL74_R14_0_Pos 16 /*!< LCD PAL74: R14_0 Position */ -#define LCD_PAL74_R14_0_Msk (0x1fUL << LCD_PAL74_R14_0_Pos) /*!< LCD PAL74: R14_0 Mask */ -#define LCD_PAL74_G14_0_Pos 21 /*!< LCD PAL74: G14_0 Position */ -#define LCD_PAL74_G14_0_Msk (0x1fUL << LCD_PAL74_G14_0_Pos) /*!< LCD PAL74: G14_0 Mask */ -#define LCD_PAL74_B14_0_Pos 26 /*!< LCD PAL74: B14_0 Position */ -#define LCD_PAL74_B14_0_Msk (0x1fUL << LCD_PAL74_B14_0_Pos) /*!< LCD PAL74: B14_0 Mask */ -#define LCD_PAL74_I1_Pos 31 /*!< LCD PAL74: I1 Position */ -#define LCD_PAL74_I1_Msk (0x01UL << LCD_PAL74_I1_Pos) /*!< LCD PAL74: I1 Mask */ - -// ---------------------------------------- LCD_PAL75 ------------------------------------------- -#define LCD_PAL75_R04_0_Pos 0 /*!< LCD PAL75: R04_0 Position */ -#define LCD_PAL75_R04_0_Msk (0x1fUL << LCD_PAL75_R04_0_Pos) /*!< LCD PAL75: R04_0 Mask */ -#define LCD_PAL75_G04_0_Pos 5 /*!< LCD PAL75: G04_0 Position */ -#define LCD_PAL75_G04_0_Msk (0x1fUL << LCD_PAL75_G04_0_Pos) /*!< LCD PAL75: G04_0 Mask */ -#define LCD_PAL75_B04_0_Pos 10 /*!< LCD PAL75: B04_0 Position */ -#define LCD_PAL75_B04_0_Msk (0x1fUL << LCD_PAL75_B04_0_Pos) /*!< LCD PAL75: B04_0 Mask */ -#define LCD_PAL75_I0_Pos 15 /*!< LCD PAL75: I0 Position */ -#define LCD_PAL75_I0_Msk (0x01UL << LCD_PAL75_I0_Pos) /*!< LCD PAL75: I0 Mask */ -#define LCD_PAL75_R14_0_Pos 16 /*!< LCD PAL75: R14_0 Position */ -#define LCD_PAL75_R14_0_Msk (0x1fUL << LCD_PAL75_R14_0_Pos) /*!< LCD PAL75: R14_0 Mask */ -#define LCD_PAL75_G14_0_Pos 21 /*!< LCD PAL75: G14_0 Position */ -#define LCD_PAL75_G14_0_Msk (0x1fUL << LCD_PAL75_G14_0_Pos) /*!< LCD PAL75: G14_0 Mask */ -#define LCD_PAL75_B14_0_Pos 26 /*!< LCD PAL75: B14_0 Position */ -#define LCD_PAL75_B14_0_Msk (0x1fUL << LCD_PAL75_B14_0_Pos) /*!< LCD PAL75: B14_0 Mask */ -#define LCD_PAL75_I1_Pos 31 /*!< LCD PAL75: I1 Position */ -#define LCD_PAL75_I1_Msk (0x01UL << LCD_PAL75_I1_Pos) /*!< LCD PAL75: I1 Mask */ - -// ---------------------------------------- LCD_PAL76 ------------------------------------------- -#define LCD_PAL76_R04_0_Pos 0 /*!< LCD PAL76: R04_0 Position */ -#define LCD_PAL76_R04_0_Msk (0x1fUL << LCD_PAL76_R04_0_Pos) /*!< LCD PAL76: R04_0 Mask */ -#define LCD_PAL76_G04_0_Pos 5 /*!< LCD PAL76: G04_0 Position */ -#define LCD_PAL76_G04_0_Msk (0x1fUL << LCD_PAL76_G04_0_Pos) /*!< LCD PAL76: G04_0 Mask */ -#define LCD_PAL76_B04_0_Pos 10 /*!< LCD PAL76: B04_0 Position */ -#define LCD_PAL76_B04_0_Msk (0x1fUL << LCD_PAL76_B04_0_Pos) /*!< LCD PAL76: B04_0 Mask */ -#define LCD_PAL76_I0_Pos 15 /*!< LCD PAL76: I0 Position */ -#define LCD_PAL76_I0_Msk (0x01UL << LCD_PAL76_I0_Pos) /*!< LCD PAL76: I0 Mask */ -#define LCD_PAL76_R14_0_Pos 16 /*!< LCD PAL76: R14_0 Position */ -#define LCD_PAL76_R14_0_Msk (0x1fUL << LCD_PAL76_R14_0_Pos) /*!< LCD PAL76: R14_0 Mask */ -#define LCD_PAL76_G14_0_Pos 21 /*!< LCD PAL76: G14_0 Position */ -#define LCD_PAL76_G14_0_Msk (0x1fUL << LCD_PAL76_G14_0_Pos) /*!< LCD PAL76: G14_0 Mask */ -#define LCD_PAL76_B14_0_Pos 26 /*!< LCD PAL76: B14_0 Position */ -#define LCD_PAL76_B14_0_Msk (0x1fUL << LCD_PAL76_B14_0_Pos) /*!< LCD PAL76: B14_0 Mask */ -#define LCD_PAL76_I1_Pos 31 /*!< LCD PAL76: I1 Position */ -#define LCD_PAL76_I1_Msk (0x01UL << LCD_PAL76_I1_Pos) /*!< LCD PAL76: I1 Mask */ - -// ---------------------------------------- LCD_PAL77 ------------------------------------------- -#define LCD_PAL77_R04_0_Pos 0 /*!< LCD PAL77: R04_0 Position */ -#define LCD_PAL77_R04_0_Msk (0x1fUL << LCD_PAL77_R04_0_Pos) /*!< LCD PAL77: R04_0 Mask */ -#define LCD_PAL77_G04_0_Pos 5 /*!< LCD PAL77: G04_0 Position */ -#define LCD_PAL77_G04_0_Msk (0x1fUL << LCD_PAL77_G04_0_Pos) /*!< LCD PAL77: G04_0 Mask */ -#define LCD_PAL77_B04_0_Pos 10 /*!< LCD PAL77: B04_0 Position */ -#define LCD_PAL77_B04_0_Msk (0x1fUL << LCD_PAL77_B04_0_Pos) /*!< LCD PAL77: B04_0 Mask */ -#define LCD_PAL77_I0_Pos 15 /*!< LCD PAL77: I0 Position */ -#define LCD_PAL77_I0_Msk (0x01UL << LCD_PAL77_I0_Pos) /*!< LCD PAL77: I0 Mask */ -#define LCD_PAL77_R14_0_Pos 16 /*!< LCD PAL77: R14_0 Position */ -#define LCD_PAL77_R14_0_Msk (0x1fUL << LCD_PAL77_R14_0_Pos) /*!< LCD PAL77: R14_0 Mask */ -#define LCD_PAL77_G14_0_Pos 21 /*!< LCD PAL77: G14_0 Position */ -#define LCD_PAL77_G14_0_Msk (0x1fUL << LCD_PAL77_G14_0_Pos) /*!< LCD PAL77: G14_0 Mask */ -#define LCD_PAL77_B14_0_Pos 26 /*!< LCD PAL77: B14_0 Position */ -#define LCD_PAL77_B14_0_Msk (0x1fUL << LCD_PAL77_B14_0_Pos) /*!< LCD PAL77: B14_0 Mask */ -#define LCD_PAL77_I1_Pos 31 /*!< LCD PAL77: I1 Position */ -#define LCD_PAL77_I1_Msk (0x01UL << LCD_PAL77_I1_Pos) /*!< LCD PAL77: I1 Mask */ - -// ---------------------------------------- LCD_PAL78 ------------------------------------------- -#define LCD_PAL78_R04_0_Pos 0 /*!< LCD PAL78: R04_0 Position */ -#define LCD_PAL78_R04_0_Msk (0x1fUL << LCD_PAL78_R04_0_Pos) /*!< LCD PAL78: R04_0 Mask */ -#define LCD_PAL78_G04_0_Pos 5 /*!< LCD PAL78: G04_0 Position */ -#define LCD_PAL78_G04_0_Msk (0x1fUL << LCD_PAL78_G04_0_Pos) /*!< LCD PAL78: G04_0 Mask */ -#define LCD_PAL78_B04_0_Pos 10 /*!< LCD PAL78: B04_0 Position */ -#define LCD_PAL78_B04_0_Msk (0x1fUL << LCD_PAL78_B04_0_Pos) /*!< LCD PAL78: B04_0 Mask */ -#define LCD_PAL78_I0_Pos 15 /*!< LCD PAL78: I0 Position */ -#define LCD_PAL78_I0_Msk (0x01UL << LCD_PAL78_I0_Pos) /*!< LCD PAL78: I0 Mask */ -#define LCD_PAL78_R14_0_Pos 16 /*!< LCD PAL78: R14_0 Position */ -#define LCD_PAL78_R14_0_Msk (0x1fUL << LCD_PAL78_R14_0_Pos) /*!< LCD PAL78: R14_0 Mask */ -#define LCD_PAL78_G14_0_Pos 21 /*!< LCD PAL78: G14_0 Position */ -#define LCD_PAL78_G14_0_Msk (0x1fUL << LCD_PAL78_G14_0_Pos) /*!< LCD PAL78: G14_0 Mask */ -#define LCD_PAL78_B14_0_Pos 26 /*!< LCD PAL78: B14_0 Position */ -#define LCD_PAL78_B14_0_Msk (0x1fUL << LCD_PAL78_B14_0_Pos) /*!< LCD PAL78: B14_0 Mask */ -#define LCD_PAL78_I1_Pos 31 /*!< LCD PAL78: I1 Position */ -#define LCD_PAL78_I1_Msk (0x01UL << LCD_PAL78_I1_Pos) /*!< LCD PAL78: I1 Mask */ - -// ---------------------------------------- LCD_PAL79 ------------------------------------------- -#define LCD_PAL79_R04_0_Pos 0 /*!< LCD PAL79: R04_0 Position */ -#define LCD_PAL79_R04_0_Msk (0x1fUL << LCD_PAL79_R04_0_Pos) /*!< LCD PAL79: R04_0 Mask */ -#define LCD_PAL79_G04_0_Pos 5 /*!< LCD PAL79: G04_0 Position */ -#define LCD_PAL79_G04_0_Msk (0x1fUL << LCD_PAL79_G04_0_Pos) /*!< LCD PAL79: G04_0 Mask */ -#define LCD_PAL79_B04_0_Pos 10 /*!< LCD PAL79: B04_0 Position */ -#define LCD_PAL79_B04_0_Msk (0x1fUL << LCD_PAL79_B04_0_Pos) /*!< LCD PAL79: B04_0 Mask */ -#define LCD_PAL79_I0_Pos 15 /*!< LCD PAL79: I0 Position */ -#define LCD_PAL79_I0_Msk (0x01UL << LCD_PAL79_I0_Pos) /*!< LCD PAL79: I0 Mask */ -#define LCD_PAL79_R14_0_Pos 16 /*!< LCD PAL79: R14_0 Position */ -#define LCD_PAL79_R14_0_Msk (0x1fUL << LCD_PAL79_R14_0_Pos) /*!< LCD PAL79: R14_0 Mask */ -#define LCD_PAL79_G14_0_Pos 21 /*!< LCD PAL79: G14_0 Position */ -#define LCD_PAL79_G14_0_Msk (0x1fUL << LCD_PAL79_G14_0_Pos) /*!< LCD PAL79: G14_0 Mask */ -#define LCD_PAL79_B14_0_Pos 26 /*!< LCD PAL79: B14_0 Position */ -#define LCD_PAL79_B14_0_Msk (0x1fUL << LCD_PAL79_B14_0_Pos) /*!< LCD PAL79: B14_0 Mask */ -#define LCD_PAL79_I1_Pos 31 /*!< LCD PAL79: I1 Position */ -#define LCD_PAL79_I1_Msk (0x01UL << LCD_PAL79_I1_Pos) /*!< LCD PAL79: I1 Mask */ - -// ---------------------------------------- LCD_PAL80 ------------------------------------------- -#define LCD_PAL80_R04_0_Pos 0 /*!< LCD PAL80: R04_0 Position */ -#define LCD_PAL80_R04_0_Msk (0x1fUL << LCD_PAL80_R04_0_Pos) /*!< LCD PAL80: R04_0 Mask */ -#define LCD_PAL80_G04_0_Pos 5 /*!< LCD PAL80: G04_0 Position */ -#define LCD_PAL80_G04_0_Msk (0x1fUL << LCD_PAL80_G04_0_Pos) /*!< LCD PAL80: G04_0 Mask */ -#define LCD_PAL80_B04_0_Pos 10 /*!< LCD PAL80: B04_0 Position */ -#define LCD_PAL80_B04_0_Msk (0x1fUL << LCD_PAL80_B04_0_Pos) /*!< LCD PAL80: B04_0 Mask */ -#define LCD_PAL80_I0_Pos 15 /*!< LCD PAL80: I0 Position */ -#define LCD_PAL80_I0_Msk (0x01UL << LCD_PAL80_I0_Pos) /*!< LCD PAL80: I0 Mask */ -#define LCD_PAL80_R14_0_Pos 16 /*!< LCD PAL80: R14_0 Position */ -#define LCD_PAL80_R14_0_Msk (0x1fUL << LCD_PAL80_R14_0_Pos) /*!< LCD PAL80: R14_0 Mask */ -#define LCD_PAL80_G14_0_Pos 21 /*!< LCD PAL80: G14_0 Position */ -#define LCD_PAL80_G14_0_Msk (0x1fUL << LCD_PAL80_G14_0_Pos) /*!< LCD PAL80: G14_0 Mask */ -#define LCD_PAL80_B14_0_Pos 26 /*!< LCD PAL80: B14_0 Position */ -#define LCD_PAL80_B14_0_Msk (0x1fUL << LCD_PAL80_B14_0_Pos) /*!< LCD PAL80: B14_0 Mask */ -#define LCD_PAL80_I1_Pos 31 /*!< LCD PAL80: I1 Position */ -#define LCD_PAL80_I1_Msk (0x01UL << LCD_PAL80_I1_Pos) /*!< LCD PAL80: I1 Mask */ - -// ---------------------------------------- LCD_PAL81 ------------------------------------------- -#define LCD_PAL81_R04_0_Pos 0 /*!< LCD PAL81: R04_0 Position */ -#define LCD_PAL81_R04_0_Msk (0x1fUL << LCD_PAL81_R04_0_Pos) /*!< LCD PAL81: R04_0 Mask */ -#define LCD_PAL81_G04_0_Pos 5 /*!< LCD PAL81: G04_0 Position */ -#define LCD_PAL81_G04_0_Msk (0x1fUL << LCD_PAL81_G04_0_Pos) /*!< LCD PAL81: G04_0 Mask */ -#define LCD_PAL81_B04_0_Pos 10 /*!< LCD PAL81: B04_0 Position */ -#define LCD_PAL81_B04_0_Msk (0x1fUL << LCD_PAL81_B04_0_Pos) /*!< LCD PAL81: B04_0 Mask */ -#define LCD_PAL81_I0_Pos 15 /*!< LCD PAL81: I0 Position */ -#define LCD_PAL81_I0_Msk (0x01UL << LCD_PAL81_I0_Pos) /*!< LCD PAL81: I0 Mask */ -#define LCD_PAL81_R14_0_Pos 16 /*!< LCD PAL81: R14_0 Position */ -#define LCD_PAL81_R14_0_Msk (0x1fUL << LCD_PAL81_R14_0_Pos) /*!< LCD PAL81: R14_0 Mask */ -#define LCD_PAL81_G14_0_Pos 21 /*!< LCD PAL81: G14_0 Position */ -#define LCD_PAL81_G14_0_Msk (0x1fUL << LCD_PAL81_G14_0_Pos) /*!< LCD PAL81: G14_0 Mask */ -#define LCD_PAL81_B14_0_Pos 26 /*!< LCD PAL81: B14_0 Position */ -#define LCD_PAL81_B14_0_Msk (0x1fUL << LCD_PAL81_B14_0_Pos) /*!< LCD PAL81: B14_0 Mask */ -#define LCD_PAL81_I1_Pos 31 /*!< LCD PAL81: I1 Position */ -#define LCD_PAL81_I1_Msk (0x01UL << LCD_PAL81_I1_Pos) /*!< LCD PAL81: I1 Mask */ - -// ---------------------------------------- LCD_PAL82 ------------------------------------------- -#define LCD_PAL82_R04_0_Pos 0 /*!< LCD PAL82: R04_0 Position */ -#define LCD_PAL82_R04_0_Msk (0x1fUL << LCD_PAL82_R04_0_Pos) /*!< LCD PAL82: R04_0 Mask */ -#define LCD_PAL82_G04_0_Pos 5 /*!< LCD PAL82: G04_0 Position */ -#define LCD_PAL82_G04_0_Msk (0x1fUL << LCD_PAL82_G04_0_Pos) /*!< LCD PAL82: G04_0 Mask */ -#define LCD_PAL82_B04_0_Pos 10 /*!< LCD PAL82: B04_0 Position */ -#define LCD_PAL82_B04_0_Msk (0x1fUL << LCD_PAL82_B04_0_Pos) /*!< LCD PAL82: B04_0 Mask */ -#define LCD_PAL82_I0_Pos 15 /*!< LCD PAL82: I0 Position */ -#define LCD_PAL82_I0_Msk (0x01UL << LCD_PAL82_I0_Pos) /*!< LCD PAL82: I0 Mask */ -#define LCD_PAL82_R14_0_Pos 16 /*!< LCD PAL82: R14_0 Position */ -#define LCD_PAL82_R14_0_Msk (0x1fUL << LCD_PAL82_R14_0_Pos) /*!< LCD PAL82: R14_0 Mask */ -#define LCD_PAL82_G14_0_Pos 21 /*!< LCD PAL82: G14_0 Position */ -#define LCD_PAL82_G14_0_Msk (0x1fUL << LCD_PAL82_G14_0_Pos) /*!< LCD PAL82: G14_0 Mask */ -#define LCD_PAL82_B14_0_Pos 26 /*!< LCD PAL82: B14_0 Position */ -#define LCD_PAL82_B14_0_Msk (0x1fUL << LCD_PAL82_B14_0_Pos) /*!< LCD PAL82: B14_0 Mask */ -#define LCD_PAL82_I1_Pos 31 /*!< LCD PAL82: I1 Position */ -#define LCD_PAL82_I1_Msk (0x01UL << LCD_PAL82_I1_Pos) /*!< LCD PAL82: I1 Mask */ - -// ---------------------------------------- LCD_PAL83 ------------------------------------------- -#define LCD_PAL83_R04_0_Pos 0 /*!< LCD PAL83: R04_0 Position */ -#define LCD_PAL83_R04_0_Msk (0x1fUL << LCD_PAL83_R04_0_Pos) /*!< LCD PAL83: R04_0 Mask */ -#define LCD_PAL83_G04_0_Pos 5 /*!< LCD PAL83: G04_0 Position */ -#define LCD_PAL83_G04_0_Msk (0x1fUL << LCD_PAL83_G04_0_Pos) /*!< LCD PAL83: G04_0 Mask */ -#define LCD_PAL83_B04_0_Pos 10 /*!< LCD PAL83: B04_0 Position */ -#define LCD_PAL83_B04_0_Msk (0x1fUL << LCD_PAL83_B04_0_Pos) /*!< LCD PAL83: B04_0 Mask */ -#define LCD_PAL83_I0_Pos 15 /*!< LCD PAL83: I0 Position */ -#define LCD_PAL83_I0_Msk (0x01UL << LCD_PAL83_I0_Pos) /*!< LCD PAL83: I0 Mask */ -#define LCD_PAL83_R14_0_Pos 16 /*!< LCD PAL83: R14_0 Position */ -#define LCD_PAL83_R14_0_Msk (0x1fUL << LCD_PAL83_R14_0_Pos) /*!< LCD PAL83: R14_0 Mask */ -#define LCD_PAL83_G14_0_Pos 21 /*!< LCD PAL83: G14_0 Position */ -#define LCD_PAL83_G14_0_Msk (0x1fUL << LCD_PAL83_G14_0_Pos) /*!< LCD PAL83: G14_0 Mask */ -#define LCD_PAL83_B14_0_Pos 26 /*!< LCD PAL83: B14_0 Position */ -#define LCD_PAL83_B14_0_Msk (0x1fUL << LCD_PAL83_B14_0_Pos) /*!< LCD PAL83: B14_0 Mask */ -#define LCD_PAL83_I1_Pos 31 /*!< LCD PAL83: I1 Position */ -#define LCD_PAL83_I1_Msk (0x01UL << LCD_PAL83_I1_Pos) /*!< LCD PAL83: I1 Mask */ - -// ---------------------------------------- LCD_PAL84 ------------------------------------------- -#define LCD_PAL84_R04_0_Pos 0 /*!< LCD PAL84: R04_0 Position */ -#define LCD_PAL84_R04_0_Msk (0x1fUL << LCD_PAL84_R04_0_Pos) /*!< LCD PAL84: R04_0 Mask */ -#define LCD_PAL84_G04_0_Pos 5 /*!< LCD PAL84: G04_0 Position */ -#define LCD_PAL84_G04_0_Msk (0x1fUL << LCD_PAL84_G04_0_Pos) /*!< LCD PAL84: G04_0 Mask */ -#define LCD_PAL84_B04_0_Pos 10 /*!< LCD PAL84: B04_0 Position */ -#define LCD_PAL84_B04_0_Msk (0x1fUL << LCD_PAL84_B04_0_Pos) /*!< LCD PAL84: B04_0 Mask */ -#define LCD_PAL84_I0_Pos 15 /*!< LCD PAL84: I0 Position */ -#define LCD_PAL84_I0_Msk (0x01UL << LCD_PAL84_I0_Pos) /*!< LCD PAL84: I0 Mask */ -#define LCD_PAL84_R14_0_Pos 16 /*!< LCD PAL84: R14_0 Position */ -#define LCD_PAL84_R14_0_Msk (0x1fUL << LCD_PAL84_R14_0_Pos) /*!< LCD PAL84: R14_0 Mask */ -#define LCD_PAL84_G14_0_Pos 21 /*!< LCD PAL84: G14_0 Position */ -#define LCD_PAL84_G14_0_Msk (0x1fUL << LCD_PAL84_G14_0_Pos) /*!< LCD PAL84: G14_0 Mask */ -#define LCD_PAL84_B14_0_Pos 26 /*!< LCD PAL84: B14_0 Position */ -#define LCD_PAL84_B14_0_Msk (0x1fUL << LCD_PAL84_B14_0_Pos) /*!< LCD PAL84: B14_0 Mask */ -#define LCD_PAL84_I1_Pos 31 /*!< LCD PAL84: I1 Position */ -#define LCD_PAL84_I1_Msk (0x01UL << LCD_PAL84_I1_Pos) /*!< LCD PAL84: I1 Mask */ - -// ---------------------------------------- LCD_PAL85 ------------------------------------------- -#define LCD_PAL85_R04_0_Pos 0 /*!< LCD PAL85: R04_0 Position */ -#define LCD_PAL85_R04_0_Msk (0x1fUL << LCD_PAL85_R04_0_Pos) /*!< LCD PAL85: R04_0 Mask */ -#define LCD_PAL85_G04_0_Pos 5 /*!< LCD PAL85: G04_0 Position */ -#define LCD_PAL85_G04_0_Msk (0x1fUL << LCD_PAL85_G04_0_Pos) /*!< LCD PAL85: G04_0 Mask */ -#define LCD_PAL85_B04_0_Pos 10 /*!< LCD PAL85: B04_0 Position */ -#define LCD_PAL85_B04_0_Msk (0x1fUL << LCD_PAL85_B04_0_Pos) /*!< LCD PAL85: B04_0 Mask */ -#define LCD_PAL85_I0_Pos 15 /*!< LCD PAL85: I0 Position */ -#define LCD_PAL85_I0_Msk (0x01UL << LCD_PAL85_I0_Pos) /*!< LCD PAL85: I0 Mask */ -#define LCD_PAL85_R14_0_Pos 16 /*!< LCD PAL85: R14_0 Position */ -#define LCD_PAL85_R14_0_Msk (0x1fUL << LCD_PAL85_R14_0_Pos) /*!< LCD PAL85: R14_0 Mask */ -#define LCD_PAL85_G14_0_Pos 21 /*!< LCD PAL85: G14_0 Position */ -#define LCD_PAL85_G14_0_Msk (0x1fUL << LCD_PAL85_G14_0_Pos) /*!< LCD PAL85: G14_0 Mask */ -#define LCD_PAL85_B14_0_Pos 26 /*!< LCD PAL85: B14_0 Position */ -#define LCD_PAL85_B14_0_Msk (0x1fUL << LCD_PAL85_B14_0_Pos) /*!< LCD PAL85: B14_0 Mask */ -#define LCD_PAL85_I1_Pos 31 /*!< LCD PAL85: I1 Position */ -#define LCD_PAL85_I1_Msk (0x01UL << LCD_PAL85_I1_Pos) /*!< LCD PAL85: I1 Mask */ - -// ---------------------------------------- LCD_PAL86 ------------------------------------------- -#define LCD_PAL86_R04_0_Pos 0 /*!< LCD PAL86: R04_0 Position */ -#define LCD_PAL86_R04_0_Msk (0x1fUL << LCD_PAL86_R04_0_Pos) /*!< LCD PAL86: R04_0 Mask */ -#define LCD_PAL86_G04_0_Pos 5 /*!< LCD PAL86: G04_0 Position */ -#define LCD_PAL86_G04_0_Msk (0x1fUL << LCD_PAL86_G04_0_Pos) /*!< LCD PAL86: G04_0 Mask */ -#define LCD_PAL86_B04_0_Pos 10 /*!< LCD PAL86: B04_0 Position */ -#define LCD_PAL86_B04_0_Msk (0x1fUL << LCD_PAL86_B04_0_Pos) /*!< LCD PAL86: B04_0 Mask */ -#define LCD_PAL86_I0_Pos 15 /*!< LCD PAL86: I0 Position */ -#define LCD_PAL86_I0_Msk (0x01UL << LCD_PAL86_I0_Pos) /*!< LCD PAL86: I0 Mask */ -#define LCD_PAL86_R14_0_Pos 16 /*!< LCD PAL86: R14_0 Position */ -#define LCD_PAL86_R14_0_Msk (0x1fUL << LCD_PAL86_R14_0_Pos) /*!< LCD PAL86: R14_0 Mask */ -#define LCD_PAL86_G14_0_Pos 21 /*!< LCD PAL86: G14_0 Position */ -#define LCD_PAL86_G14_0_Msk (0x1fUL << LCD_PAL86_G14_0_Pos) /*!< LCD PAL86: G14_0 Mask */ -#define LCD_PAL86_B14_0_Pos 26 /*!< LCD PAL86: B14_0 Position */ -#define LCD_PAL86_B14_0_Msk (0x1fUL << LCD_PAL86_B14_0_Pos) /*!< LCD PAL86: B14_0 Mask */ -#define LCD_PAL86_I1_Pos 31 /*!< LCD PAL86: I1 Position */ -#define LCD_PAL86_I1_Msk (0x01UL << LCD_PAL86_I1_Pos) /*!< LCD PAL86: I1 Mask */ - -// ---------------------------------------- LCD_PAL87 ------------------------------------------- -#define LCD_PAL87_R04_0_Pos 0 /*!< LCD PAL87: R04_0 Position */ -#define LCD_PAL87_R04_0_Msk (0x1fUL << LCD_PAL87_R04_0_Pos) /*!< LCD PAL87: R04_0 Mask */ -#define LCD_PAL87_G04_0_Pos 5 /*!< LCD PAL87: G04_0 Position */ -#define LCD_PAL87_G04_0_Msk (0x1fUL << LCD_PAL87_G04_0_Pos) /*!< LCD PAL87: G04_0 Mask */ -#define LCD_PAL87_B04_0_Pos 10 /*!< LCD PAL87: B04_0 Position */ -#define LCD_PAL87_B04_0_Msk (0x1fUL << LCD_PAL87_B04_0_Pos) /*!< LCD PAL87: B04_0 Mask */ -#define LCD_PAL87_I0_Pos 15 /*!< LCD PAL87: I0 Position */ -#define LCD_PAL87_I0_Msk (0x01UL << LCD_PAL87_I0_Pos) /*!< LCD PAL87: I0 Mask */ -#define LCD_PAL87_R14_0_Pos 16 /*!< LCD PAL87: R14_0 Position */ -#define LCD_PAL87_R14_0_Msk (0x1fUL << LCD_PAL87_R14_0_Pos) /*!< LCD PAL87: R14_0 Mask */ -#define LCD_PAL87_G14_0_Pos 21 /*!< LCD PAL87: G14_0 Position */ -#define LCD_PAL87_G14_0_Msk (0x1fUL << LCD_PAL87_G14_0_Pos) /*!< LCD PAL87: G14_0 Mask */ -#define LCD_PAL87_B14_0_Pos 26 /*!< LCD PAL87: B14_0 Position */ -#define LCD_PAL87_B14_0_Msk (0x1fUL << LCD_PAL87_B14_0_Pos) /*!< LCD PAL87: B14_0 Mask */ -#define LCD_PAL87_I1_Pos 31 /*!< LCD PAL87: I1 Position */ -#define LCD_PAL87_I1_Msk (0x01UL << LCD_PAL87_I1_Pos) /*!< LCD PAL87: I1 Mask */ - -// ---------------------------------------- LCD_PAL88 ------------------------------------------- -#define LCD_PAL88_R04_0_Pos 0 /*!< LCD PAL88: R04_0 Position */ -#define LCD_PAL88_R04_0_Msk (0x1fUL << LCD_PAL88_R04_0_Pos) /*!< LCD PAL88: R04_0 Mask */ -#define LCD_PAL88_G04_0_Pos 5 /*!< LCD PAL88: G04_0 Position */ -#define LCD_PAL88_G04_0_Msk (0x1fUL << LCD_PAL88_G04_0_Pos) /*!< LCD PAL88: G04_0 Mask */ -#define LCD_PAL88_B04_0_Pos 10 /*!< LCD PAL88: B04_0 Position */ -#define LCD_PAL88_B04_0_Msk (0x1fUL << LCD_PAL88_B04_0_Pos) /*!< LCD PAL88: B04_0 Mask */ -#define LCD_PAL88_I0_Pos 15 /*!< LCD PAL88: I0 Position */ -#define LCD_PAL88_I0_Msk (0x01UL << LCD_PAL88_I0_Pos) /*!< LCD PAL88: I0 Mask */ -#define LCD_PAL88_R14_0_Pos 16 /*!< LCD PAL88: R14_0 Position */ -#define LCD_PAL88_R14_0_Msk (0x1fUL << LCD_PAL88_R14_0_Pos) /*!< LCD PAL88: R14_0 Mask */ -#define LCD_PAL88_G14_0_Pos 21 /*!< LCD PAL88: G14_0 Position */ -#define LCD_PAL88_G14_0_Msk (0x1fUL << LCD_PAL88_G14_0_Pos) /*!< LCD PAL88: G14_0 Mask */ -#define LCD_PAL88_B14_0_Pos 26 /*!< LCD PAL88: B14_0 Position */ -#define LCD_PAL88_B14_0_Msk (0x1fUL << LCD_PAL88_B14_0_Pos) /*!< LCD PAL88: B14_0 Mask */ -#define LCD_PAL88_I1_Pos 31 /*!< LCD PAL88: I1 Position */ -#define LCD_PAL88_I1_Msk (0x01UL << LCD_PAL88_I1_Pos) /*!< LCD PAL88: I1 Mask */ - -// ---------------------------------------- LCD_PAL89 ------------------------------------------- -#define LCD_PAL89_R04_0_Pos 0 /*!< LCD PAL89: R04_0 Position */ -#define LCD_PAL89_R04_0_Msk (0x1fUL << LCD_PAL89_R04_0_Pos) /*!< LCD PAL89: R04_0 Mask */ -#define LCD_PAL89_G04_0_Pos 5 /*!< LCD PAL89: G04_0 Position */ -#define LCD_PAL89_G04_0_Msk (0x1fUL << LCD_PAL89_G04_0_Pos) /*!< LCD PAL89: G04_0 Mask */ -#define LCD_PAL89_B04_0_Pos 10 /*!< LCD PAL89: B04_0 Position */ -#define LCD_PAL89_B04_0_Msk (0x1fUL << LCD_PAL89_B04_0_Pos) /*!< LCD PAL89: B04_0 Mask */ -#define LCD_PAL89_I0_Pos 15 /*!< LCD PAL89: I0 Position */ -#define LCD_PAL89_I0_Msk (0x01UL << LCD_PAL89_I0_Pos) /*!< LCD PAL89: I0 Mask */ -#define LCD_PAL89_R14_0_Pos 16 /*!< LCD PAL89: R14_0 Position */ -#define LCD_PAL89_R14_0_Msk (0x1fUL << LCD_PAL89_R14_0_Pos) /*!< LCD PAL89: R14_0 Mask */ -#define LCD_PAL89_G14_0_Pos 21 /*!< LCD PAL89: G14_0 Position */ -#define LCD_PAL89_G14_0_Msk (0x1fUL << LCD_PAL89_G14_0_Pos) /*!< LCD PAL89: G14_0 Mask */ -#define LCD_PAL89_B14_0_Pos 26 /*!< LCD PAL89: B14_0 Position */ -#define LCD_PAL89_B14_0_Msk (0x1fUL << LCD_PAL89_B14_0_Pos) /*!< LCD PAL89: B14_0 Mask */ -#define LCD_PAL89_I1_Pos 31 /*!< LCD PAL89: I1 Position */ -#define LCD_PAL89_I1_Msk (0x01UL << LCD_PAL89_I1_Pos) /*!< LCD PAL89: I1 Mask */ - -// ---------------------------------------- LCD_PAL90 ------------------------------------------- -#define LCD_PAL90_R04_0_Pos 0 /*!< LCD PAL90: R04_0 Position */ -#define LCD_PAL90_R04_0_Msk (0x1fUL << LCD_PAL90_R04_0_Pos) /*!< LCD PAL90: R04_0 Mask */ -#define LCD_PAL90_G04_0_Pos 5 /*!< LCD PAL90: G04_0 Position */ -#define LCD_PAL90_G04_0_Msk (0x1fUL << LCD_PAL90_G04_0_Pos) /*!< LCD PAL90: G04_0 Mask */ -#define LCD_PAL90_B04_0_Pos 10 /*!< LCD PAL90: B04_0 Position */ -#define LCD_PAL90_B04_0_Msk (0x1fUL << LCD_PAL90_B04_0_Pos) /*!< LCD PAL90: B04_0 Mask */ -#define LCD_PAL90_I0_Pos 15 /*!< LCD PAL90: I0 Position */ -#define LCD_PAL90_I0_Msk (0x01UL << LCD_PAL90_I0_Pos) /*!< LCD PAL90: I0 Mask */ -#define LCD_PAL90_R14_0_Pos 16 /*!< LCD PAL90: R14_0 Position */ -#define LCD_PAL90_R14_0_Msk (0x1fUL << LCD_PAL90_R14_0_Pos) /*!< LCD PAL90: R14_0 Mask */ -#define LCD_PAL90_G14_0_Pos 21 /*!< LCD PAL90: G14_0 Position */ -#define LCD_PAL90_G14_0_Msk (0x1fUL << LCD_PAL90_G14_0_Pos) /*!< LCD PAL90: G14_0 Mask */ -#define LCD_PAL90_B14_0_Pos 26 /*!< LCD PAL90: B14_0 Position */ -#define LCD_PAL90_B14_0_Msk (0x1fUL << LCD_PAL90_B14_0_Pos) /*!< LCD PAL90: B14_0 Mask */ -#define LCD_PAL90_I1_Pos 31 /*!< LCD PAL90: I1 Position */ -#define LCD_PAL90_I1_Msk (0x01UL << LCD_PAL90_I1_Pos) /*!< LCD PAL90: I1 Mask */ - -// ---------------------------------------- LCD_PAL91 ------------------------------------------- -#define LCD_PAL91_R04_0_Pos 0 /*!< LCD PAL91: R04_0 Position */ -#define LCD_PAL91_R04_0_Msk (0x1fUL << LCD_PAL91_R04_0_Pos) /*!< LCD PAL91: R04_0 Mask */ -#define LCD_PAL91_G04_0_Pos 5 /*!< LCD PAL91: G04_0 Position */ -#define LCD_PAL91_G04_0_Msk (0x1fUL << LCD_PAL91_G04_0_Pos) /*!< LCD PAL91: G04_0 Mask */ -#define LCD_PAL91_B04_0_Pos 10 /*!< LCD PAL91: B04_0 Position */ -#define LCD_PAL91_B04_0_Msk (0x1fUL << LCD_PAL91_B04_0_Pos) /*!< LCD PAL91: B04_0 Mask */ -#define LCD_PAL91_I0_Pos 15 /*!< LCD PAL91: I0 Position */ -#define LCD_PAL91_I0_Msk (0x01UL << LCD_PAL91_I0_Pos) /*!< LCD PAL91: I0 Mask */ -#define LCD_PAL91_R14_0_Pos 16 /*!< LCD PAL91: R14_0 Position */ -#define LCD_PAL91_R14_0_Msk (0x1fUL << LCD_PAL91_R14_0_Pos) /*!< LCD PAL91: R14_0 Mask */ -#define LCD_PAL91_G14_0_Pos 21 /*!< LCD PAL91: G14_0 Position */ -#define LCD_PAL91_G14_0_Msk (0x1fUL << LCD_PAL91_G14_0_Pos) /*!< LCD PAL91: G14_0 Mask */ -#define LCD_PAL91_B14_0_Pos 26 /*!< LCD PAL91: B14_0 Position */ -#define LCD_PAL91_B14_0_Msk (0x1fUL << LCD_PAL91_B14_0_Pos) /*!< LCD PAL91: B14_0 Mask */ -#define LCD_PAL91_I1_Pos 31 /*!< LCD PAL91: I1 Position */ -#define LCD_PAL91_I1_Msk (0x01UL << LCD_PAL91_I1_Pos) /*!< LCD PAL91: I1 Mask */ - -// ---------------------------------------- LCD_PAL92 ------------------------------------------- -#define LCD_PAL92_R04_0_Pos 0 /*!< LCD PAL92: R04_0 Position */ -#define LCD_PAL92_R04_0_Msk (0x1fUL << LCD_PAL92_R04_0_Pos) /*!< LCD PAL92: R04_0 Mask */ -#define LCD_PAL92_G04_0_Pos 5 /*!< LCD PAL92: G04_0 Position */ -#define LCD_PAL92_G04_0_Msk (0x1fUL << LCD_PAL92_G04_0_Pos) /*!< LCD PAL92: G04_0 Mask */ -#define LCD_PAL92_B04_0_Pos 10 /*!< LCD PAL92: B04_0 Position */ -#define LCD_PAL92_B04_0_Msk (0x1fUL << LCD_PAL92_B04_0_Pos) /*!< LCD PAL92: B04_0 Mask */ -#define LCD_PAL92_I0_Pos 15 /*!< LCD PAL92: I0 Position */ -#define LCD_PAL92_I0_Msk (0x01UL << LCD_PAL92_I0_Pos) /*!< LCD PAL92: I0 Mask */ -#define LCD_PAL92_R14_0_Pos 16 /*!< LCD PAL92: R14_0 Position */ -#define LCD_PAL92_R14_0_Msk (0x1fUL << LCD_PAL92_R14_0_Pos) /*!< LCD PAL92: R14_0 Mask */ -#define LCD_PAL92_G14_0_Pos 21 /*!< LCD PAL92: G14_0 Position */ -#define LCD_PAL92_G14_0_Msk (0x1fUL << LCD_PAL92_G14_0_Pos) /*!< LCD PAL92: G14_0 Mask */ -#define LCD_PAL92_B14_0_Pos 26 /*!< LCD PAL92: B14_0 Position */ -#define LCD_PAL92_B14_0_Msk (0x1fUL << LCD_PAL92_B14_0_Pos) /*!< LCD PAL92: B14_0 Mask */ -#define LCD_PAL92_I1_Pos 31 /*!< LCD PAL92: I1 Position */ -#define LCD_PAL92_I1_Msk (0x01UL << LCD_PAL92_I1_Pos) /*!< LCD PAL92: I1 Mask */ - -// ---------------------------------------- LCD_PAL93 ------------------------------------------- -#define LCD_PAL93_R04_0_Pos 0 /*!< LCD PAL93: R04_0 Position */ -#define LCD_PAL93_R04_0_Msk (0x1fUL << LCD_PAL93_R04_0_Pos) /*!< LCD PAL93: R04_0 Mask */ -#define LCD_PAL93_G04_0_Pos 5 /*!< LCD PAL93: G04_0 Position */ -#define LCD_PAL93_G04_0_Msk (0x1fUL << LCD_PAL93_G04_0_Pos) /*!< LCD PAL93: G04_0 Mask */ -#define LCD_PAL93_B04_0_Pos 10 /*!< LCD PAL93: B04_0 Position */ -#define LCD_PAL93_B04_0_Msk (0x1fUL << LCD_PAL93_B04_0_Pos) /*!< LCD PAL93: B04_0 Mask */ -#define LCD_PAL93_I0_Pos 15 /*!< LCD PAL93: I0 Position */ -#define LCD_PAL93_I0_Msk (0x01UL << LCD_PAL93_I0_Pos) /*!< LCD PAL93: I0 Mask */ -#define LCD_PAL93_R14_0_Pos 16 /*!< LCD PAL93: R14_0 Position */ -#define LCD_PAL93_R14_0_Msk (0x1fUL << LCD_PAL93_R14_0_Pos) /*!< LCD PAL93: R14_0 Mask */ -#define LCD_PAL93_G14_0_Pos 21 /*!< LCD PAL93: G14_0 Position */ -#define LCD_PAL93_G14_0_Msk (0x1fUL << LCD_PAL93_G14_0_Pos) /*!< LCD PAL93: G14_0 Mask */ -#define LCD_PAL93_B14_0_Pos 26 /*!< LCD PAL93: B14_0 Position */ -#define LCD_PAL93_B14_0_Msk (0x1fUL << LCD_PAL93_B14_0_Pos) /*!< LCD PAL93: B14_0 Mask */ -#define LCD_PAL93_I1_Pos 31 /*!< LCD PAL93: I1 Position */ -#define LCD_PAL93_I1_Msk (0x01UL << LCD_PAL93_I1_Pos) /*!< LCD PAL93: I1 Mask */ - -// ---------------------------------------- LCD_PAL94 ------------------------------------------- -#define LCD_PAL94_R04_0_Pos 0 /*!< LCD PAL94: R04_0 Position */ -#define LCD_PAL94_R04_0_Msk (0x1fUL << LCD_PAL94_R04_0_Pos) /*!< LCD PAL94: R04_0 Mask */ -#define LCD_PAL94_G04_0_Pos 5 /*!< LCD PAL94: G04_0 Position */ -#define LCD_PAL94_G04_0_Msk (0x1fUL << LCD_PAL94_G04_0_Pos) /*!< LCD PAL94: G04_0 Mask */ -#define LCD_PAL94_B04_0_Pos 10 /*!< LCD PAL94: B04_0 Position */ -#define LCD_PAL94_B04_0_Msk (0x1fUL << LCD_PAL94_B04_0_Pos) /*!< LCD PAL94: B04_0 Mask */ -#define LCD_PAL94_I0_Pos 15 /*!< LCD PAL94: I0 Position */ -#define LCD_PAL94_I0_Msk (0x01UL << LCD_PAL94_I0_Pos) /*!< LCD PAL94: I0 Mask */ -#define LCD_PAL94_R14_0_Pos 16 /*!< LCD PAL94: R14_0 Position */ -#define LCD_PAL94_R14_0_Msk (0x1fUL << LCD_PAL94_R14_0_Pos) /*!< LCD PAL94: R14_0 Mask */ -#define LCD_PAL94_G14_0_Pos 21 /*!< LCD PAL94: G14_0 Position */ -#define LCD_PAL94_G14_0_Msk (0x1fUL << LCD_PAL94_G14_0_Pos) /*!< LCD PAL94: G14_0 Mask */ -#define LCD_PAL94_B14_0_Pos 26 /*!< LCD PAL94: B14_0 Position */ -#define LCD_PAL94_B14_0_Msk (0x1fUL << LCD_PAL94_B14_0_Pos) /*!< LCD PAL94: B14_0 Mask */ -#define LCD_PAL94_I1_Pos 31 /*!< LCD PAL94: I1 Position */ -#define LCD_PAL94_I1_Msk (0x01UL << LCD_PAL94_I1_Pos) /*!< LCD PAL94: I1 Mask */ - -// ---------------------------------------- LCD_PAL95 ------------------------------------------- -#define LCD_PAL95_R04_0_Pos 0 /*!< LCD PAL95: R04_0 Position */ -#define LCD_PAL95_R04_0_Msk (0x1fUL << LCD_PAL95_R04_0_Pos) /*!< LCD PAL95: R04_0 Mask */ -#define LCD_PAL95_G04_0_Pos 5 /*!< LCD PAL95: G04_0 Position */ -#define LCD_PAL95_G04_0_Msk (0x1fUL << LCD_PAL95_G04_0_Pos) /*!< LCD PAL95: G04_0 Mask */ -#define LCD_PAL95_B04_0_Pos 10 /*!< LCD PAL95: B04_0 Position */ -#define LCD_PAL95_B04_0_Msk (0x1fUL << LCD_PAL95_B04_0_Pos) /*!< LCD PAL95: B04_0 Mask */ -#define LCD_PAL95_I0_Pos 15 /*!< LCD PAL95: I0 Position */ -#define LCD_PAL95_I0_Msk (0x01UL << LCD_PAL95_I0_Pos) /*!< LCD PAL95: I0 Mask */ -#define LCD_PAL95_R14_0_Pos 16 /*!< LCD PAL95: R14_0 Position */ -#define LCD_PAL95_R14_0_Msk (0x1fUL << LCD_PAL95_R14_0_Pos) /*!< LCD PAL95: R14_0 Mask */ -#define LCD_PAL95_G14_0_Pos 21 /*!< LCD PAL95: G14_0 Position */ -#define LCD_PAL95_G14_0_Msk (0x1fUL << LCD_PAL95_G14_0_Pos) /*!< LCD PAL95: G14_0 Mask */ -#define LCD_PAL95_B14_0_Pos 26 /*!< LCD PAL95: B14_0 Position */ -#define LCD_PAL95_B14_0_Msk (0x1fUL << LCD_PAL95_B14_0_Pos) /*!< LCD PAL95: B14_0 Mask */ -#define LCD_PAL95_I1_Pos 31 /*!< LCD PAL95: I1 Position */ -#define LCD_PAL95_I1_Msk (0x01UL << LCD_PAL95_I1_Pos) /*!< LCD PAL95: I1 Mask */ - -// ---------------------------------------- LCD_PAL96 ------------------------------------------- -#define LCD_PAL96_R04_0_Pos 0 /*!< LCD PAL96: R04_0 Position */ -#define LCD_PAL96_R04_0_Msk (0x1fUL << LCD_PAL96_R04_0_Pos) /*!< LCD PAL96: R04_0 Mask */ -#define LCD_PAL96_G04_0_Pos 5 /*!< LCD PAL96: G04_0 Position */ -#define LCD_PAL96_G04_0_Msk (0x1fUL << LCD_PAL96_G04_0_Pos) /*!< LCD PAL96: G04_0 Mask */ -#define LCD_PAL96_B04_0_Pos 10 /*!< LCD PAL96: B04_0 Position */ -#define LCD_PAL96_B04_0_Msk (0x1fUL << LCD_PAL96_B04_0_Pos) /*!< LCD PAL96: B04_0 Mask */ -#define LCD_PAL96_I0_Pos 15 /*!< LCD PAL96: I0 Position */ -#define LCD_PAL96_I0_Msk (0x01UL << LCD_PAL96_I0_Pos) /*!< LCD PAL96: I0 Mask */ -#define LCD_PAL96_R14_0_Pos 16 /*!< LCD PAL96: R14_0 Position */ -#define LCD_PAL96_R14_0_Msk (0x1fUL << LCD_PAL96_R14_0_Pos) /*!< LCD PAL96: R14_0 Mask */ -#define LCD_PAL96_G14_0_Pos 21 /*!< LCD PAL96: G14_0 Position */ -#define LCD_PAL96_G14_0_Msk (0x1fUL << LCD_PAL96_G14_0_Pos) /*!< LCD PAL96: G14_0 Mask */ -#define LCD_PAL96_B14_0_Pos 26 /*!< LCD PAL96: B14_0 Position */ -#define LCD_PAL96_B14_0_Msk (0x1fUL << LCD_PAL96_B14_0_Pos) /*!< LCD PAL96: B14_0 Mask */ -#define LCD_PAL96_I1_Pos 31 /*!< LCD PAL96: I1 Position */ -#define LCD_PAL96_I1_Msk (0x01UL << LCD_PAL96_I1_Pos) /*!< LCD PAL96: I1 Mask */ - -// ---------------------------------------- LCD_PAL97 ------------------------------------------- -#define LCD_PAL97_R04_0_Pos 0 /*!< LCD PAL97: R04_0 Position */ -#define LCD_PAL97_R04_0_Msk (0x1fUL << LCD_PAL97_R04_0_Pos) /*!< LCD PAL97: R04_0 Mask */ -#define LCD_PAL97_G04_0_Pos 5 /*!< LCD PAL97: G04_0 Position */ -#define LCD_PAL97_G04_0_Msk (0x1fUL << LCD_PAL97_G04_0_Pos) /*!< LCD PAL97: G04_0 Mask */ -#define LCD_PAL97_B04_0_Pos 10 /*!< LCD PAL97: B04_0 Position */ -#define LCD_PAL97_B04_0_Msk (0x1fUL << LCD_PAL97_B04_0_Pos) /*!< LCD PAL97: B04_0 Mask */ -#define LCD_PAL97_I0_Pos 15 /*!< LCD PAL97: I0 Position */ -#define LCD_PAL97_I0_Msk (0x01UL << LCD_PAL97_I0_Pos) /*!< LCD PAL97: I0 Mask */ -#define LCD_PAL97_R14_0_Pos 16 /*!< LCD PAL97: R14_0 Position */ -#define LCD_PAL97_R14_0_Msk (0x1fUL << LCD_PAL97_R14_0_Pos) /*!< LCD PAL97: R14_0 Mask */ -#define LCD_PAL97_G14_0_Pos 21 /*!< LCD PAL97: G14_0 Position */ -#define LCD_PAL97_G14_0_Msk (0x1fUL << LCD_PAL97_G14_0_Pos) /*!< LCD PAL97: G14_0 Mask */ -#define LCD_PAL97_B14_0_Pos 26 /*!< LCD PAL97: B14_0 Position */ -#define LCD_PAL97_B14_0_Msk (0x1fUL << LCD_PAL97_B14_0_Pos) /*!< LCD PAL97: B14_0 Mask */ -#define LCD_PAL97_I1_Pos 31 /*!< LCD PAL97: I1 Position */ -#define LCD_PAL97_I1_Msk (0x01UL << LCD_PAL97_I1_Pos) /*!< LCD PAL97: I1 Mask */ - -// ---------------------------------------- LCD_PAL98 ------------------------------------------- -#define LCD_PAL98_R04_0_Pos 0 /*!< LCD PAL98: R04_0 Position */ -#define LCD_PAL98_R04_0_Msk (0x1fUL << LCD_PAL98_R04_0_Pos) /*!< LCD PAL98: R04_0 Mask */ -#define LCD_PAL98_G04_0_Pos 5 /*!< LCD PAL98: G04_0 Position */ -#define LCD_PAL98_G04_0_Msk (0x1fUL << LCD_PAL98_G04_0_Pos) /*!< LCD PAL98: G04_0 Mask */ -#define LCD_PAL98_B04_0_Pos 10 /*!< LCD PAL98: B04_0 Position */ -#define LCD_PAL98_B04_0_Msk (0x1fUL << LCD_PAL98_B04_0_Pos) /*!< LCD PAL98: B04_0 Mask */ -#define LCD_PAL98_I0_Pos 15 /*!< LCD PAL98: I0 Position */ -#define LCD_PAL98_I0_Msk (0x01UL << LCD_PAL98_I0_Pos) /*!< LCD PAL98: I0 Mask */ -#define LCD_PAL98_R14_0_Pos 16 /*!< LCD PAL98: R14_0 Position */ -#define LCD_PAL98_R14_0_Msk (0x1fUL << LCD_PAL98_R14_0_Pos) /*!< LCD PAL98: R14_0 Mask */ -#define LCD_PAL98_G14_0_Pos 21 /*!< LCD PAL98: G14_0 Position */ -#define LCD_PAL98_G14_0_Msk (0x1fUL << LCD_PAL98_G14_0_Pos) /*!< LCD PAL98: G14_0 Mask */ -#define LCD_PAL98_B14_0_Pos 26 /*!< LCD PAL98: B14_0 Position */ -#define LCD_PAL98_B14_0_Msk (0x1fUL << LCD_PAL98_B14_0_Pos) /*!< LCD PAL98: B14_0 Mask */ -#define LCD_PAL98_I1_Pos 31 /*!< LCD PAL98: I1 Position */ -#define LCD_PAL98_I1_Msk (0x01UL << LCD_PAL98_I1_Pos) /*!< LCD PAL98: I1 Mask */ - -// ---------------------------------------- LCD_PAL99 ------------------------------------------- -#define LCD_PAL99_R04_0_Pos 0 /*!< LCD PAL99: R04_0 Position */ -#define LCD_PAL99_R04_0_Msk (0x1fUL << LCD_PAL99_R04_0_Pos) /*!< LCD PAL99: R04_0 Mask */ -#define LCD_PAL99_G04_0_Pos 5 /*!< LCD PAL99: G04_0 Position */ -#define LCD_PAL99_G04_0_Msk (0x1fUL << LCD_PAL99_G04_0_Pos) /*!< LCD PAL99: G04_0 Mask */ -#define LCD_PAL99_B04_0_Pos 10 /*!< LCD PAL99: B04_0 Position */ -#define LCD_PAL99_B04_0_Msk (0x1fUL << LCD_PAL99_B04_0_Pos) /*!< LCD PAL99: B04_0 Mask */ -#define LCD_PAL99_I0_Pos 15 /*!< LCD PAL99: I0 Position */ -#define LCD_PAL99_I0_Msk (0x01UL << LCD_PAL99_I0_Pos) /*!< LCD PAL99: I0 Mask */ -#define LCD_PAL99_R14_0_Pos 16 /*!< LCD PAL99: R14_0 Position */ -#define LCD_PAL99_R14_0_Msk (0x1fUL << LCD_PAL99_R14_0_Pos) /*!< LCD PAL99: R14_0 Mask */ -#define LCD_PAL99_G14_0_Pos 21 /*!< LCD PAL99: G14_0 Position */ -#define LCD_PAL99_G14_0_Msk (0x1fUL << LCD_PAL99_G14_0_Pos) /*!< LCD PAL99: G14_0 Mask */ -#define LCD_PAL99_B14_0_Pos 26 /*!< LCD PAL99: B14_0 Position */ -#define LCD_PAL99_B14_0_Msk (0x1fUL << LCD_PAL99_B14_0_Pos) /*!< LCD PAL99: B14_0 Mask */ -#define LCD_PAL99_I1_Pos 31 /*!< LCD PAL99: I1 Position */ -#define LCD_PAL99_I1_Msk (0x01UL << LCD_PAL99_I1_Pos) /*!< LCD PAL99: I1 Mask */ - -// --------------------------------------- LCD_PAL100 ------------------------------------------- -#define LCD_PAL100_R04_0_Pos 0 /*!< LCD PAL100: R04_0 Position */ -#define LCD_PAL100_R04_0_Msk (0x1fUL << LCD_PAL100_R04_0_Pos) /*!< LCD PAL100: R04_0 Mask */ -#define LCD_PAL100_G04_0_Pos 5 /*!< LCD PAL100: G04_0 Position */ -#define LCD_PAL100_G04_0_Msk (0x1fUL << LCD_PAL100_G04_0_Pos) /*!< LCD PAL100: G04_0 Mask */ -#define LCD_PAL100_B04_0_Pos 10 /*!< LCD PAL100: B04_0 Position */ -#define LCD_PAL100_B04_0_Msk (0x1fUL << LCD_PAL100_B04_0_Pos) /*!< LCD PAL100: B04_0 Mask */ -#define LCD_PAL100_I0_Pos 15 /*!< LCD PAL100: I0 Position */ -#define LCD_PAL100_I0_Msk (0x01UL << LCD_PAL100_I0_Pos) /*!< LCD PAL100: I0 Mask */ -#define LCD_PAL100_R14_0_Pos 16 /*!< LCD PAL100: R14_0 Position */ -#define LCD_PAL100_R14_0_Msk (0x1fUL << LCD_PAL100_R14_0_Pos) /*!< LCD PAL100: R14_0 Mask */ -#define LCD_PAL100_G14_0_Pos 21 /*!< LCD PAL100: G14_0 Position */ -#define LCD_PAL100_G14_0_Msk (0x1fUL << LCD_PAL100_G14_0_Pos) /*!< LCD PAL100: G14_0 Mask */ -#define LCD_PAL100_B14_0_Pos 26 /*!< LCD PAL100: B14_0 Position */ -#define LCD_PAL100_B14_0_Msk (0x1fUL << LCD_PAL100_B14_0_Pos) /*!< LCD PAL100: B14_0 Mask */ -#define LCD_PAL100_I1_Pos 31 /*!< LCD PAL100: I1 Position */ -#define LCD_PAL100_I1_Msk (0x01UL << LCD_PAL100_I1_Pos) /*!< LCD PAL100: I1 Mask */ - -// --------------------------------------- LCD_PAL101 ------------------------------------------- -#define LCD_PAL101_R04_0_Pos 0 /*!< LCD PAL101: R04_0 Position */ -#define LCD_PAL101_R04_0_Msk (0x1fUL << LCD_PAL101_R04_0_Pos) /*!< LCD PAL101: R04_0 Mask */ -#define LCD_PAL101_G04_0_Pos 5 /*!< LCD PAL101: G04_0 Position */ -#define LCD_PAL101_G04_0_Msk (0x1fUL << LCD_PAL101_G04_0_Pos) /*!< LCD PAL101: G04_0 Mask */ -#define LCD_PAL101_B04_0_Pos 10 /*!< LCD PAL101: B04_0 Position */ -#define LCD_PAL101_B04_0_Msk (0x1fUL << LCD_PAL101_B04_0_Pos) /*!< LCD PAL101: B04_0 Mask */ -#define LCD_PAL101_I0_Pos 15 /*!< LCD PAL101: I0 Position */ -#define LCD_PAL101_I0_Msk (0x01UL << LCD_PAL101_I0_Pos) /*!< LCD PAL101: I0 Mask */ -#define LCD_PAL101_R14_0_Pos 16 /*!< LCD PAL101: R14_0 Position */ -#define LCD_PAL101_R14_0_Msk (0x1fUL << LCD_PAL101_R14_0_Pos) /*!< LCD PAL101: R14_0 Mask */ -#define LCD_PAL101_G14_0_Pos 21 /*!< LCD PAL101: G14_0 Position */ -#define LCD_PAL101_G14_0_Msk (0x1fUL << LCD_PAL101_G14_0_Pos) /*!< LCD PAL101: G14_0 Mask */ -#define LCD_PAL101_B14_0_Pos 26 /*!< LCD PAL101: B14_0 Position */ -#define LCD_PAL101_B14_0_Msk (0x1fUL << LCD_PAL101_B14_0_Pos) /*!< LCD PAL101: B14_0 Mask */ -#define LCD_PAL101_I1_Pos 31 /*!< LCD PAL101: I1 Position */ -#define LCD_PAL101_I1_Msk (0x01UL << LCD_PAL101_I1_Pos) /*!< LCD PAL101: I1 Mask */ - -// --------------------------------------- LCD_PAL102 ------------------------------------------- -#define LCD_PAL102_R04_0_Pos 0 /*!< LCD PAL102: R04_0 Position */ -#define LCD_PAL102_R04_0_Msk (0x1fUL << LCD_PAL102_R04_0_Pos) /*!< LCD PAL102: R04_0 Mask */ -#define LCD_PAL102_G04_0_Pos 5 /*!< LCD PAL102: G04_0 Position */ -#define LCD_PAL102_G04_0_Msk (0x1fUL << LCD_PAL102_G04_0_Pos) /*!< LCD PAL102: G04_0 Mask */ -#define LCD_PAL102_B04_0_Pos 10 /*!< LCD PAL102: B04_0 Position */ -#define LCD_PAL102_B04_0_Msk (0x1fUL << LCD_PAL102_B04_0_Pos) /*!< LCD PAL102: B04_0 Mask */ -#define LCD_PAL102_I0_Pos 15 /*!< LCD PAL102: I0 Position */ -#define LCD_PAL102_I0_Msk (0x01UL << LCD_PAL102_I0_Pos) /*!< LCD PAL102: I0 Mask */ -#define LCD_PAL102_R14_0_Pos 16 /*!< LCD PAL102: R14_0 Position */ -#define LCD_PAL102_R14_0_Msk (0x1fUL << LCD_PAL102_R14_0_Pos) /*!< LCD PAL102: R14_0 Mask */ -#define LCD_PAL102_G14_0_Pos 21 /*!< LCD PAL102: G14_0 Position */ -#define LCD_PAL102_G14_0_Msk (0x1fUL << LCD_PAL102_G14_0_Pos) /*!< LCD PAL102: G14_0 Mask */ -#define LCD_PAL102_B14_0_Pos 26 /*!< LCD PAL102: B14_0 Position */ -#define LCD_PAL102_B14_0_Msk (0x1fUL << LCD_PAL102_B14_0_Pos) /*!< LCD PAL102: B14_0 Mask */ -#define LCD_PAL102_I1_Pos 31 /*!< LCD PAL102: I1 Position */ -#define LCD_PAL102_I1_Msk (0x01UL << LCD_PAL102_I1_Pos) /*!< LCD PAL102: I1 Mask */ - -// --------------------------------------- LCD_PAL103 ------------------------------------------- -#define LCD_PAL103_R04_0_Pos 0 /*!< LCD PAL103: R04_0 Position */ -#define LCD_PAL103_R04_0_Msk (0x1fUL << LCD_PAL103_R04_0_Pos) /*!< LCD PAL103: R04_0 Mask */ -#define LCD_PAL103_G04_0_Pos 5 /*!< LCD PAL103: G04_0 Position */ -#define LCD_PAL103_G04_0_Msk (0x1fUL << LCD_PAL103_G04_0_Pos) /*!< LCD PAL103: G04_0 Mask */ -#define LCD_PAL103_B04_0_Pos 10 /*!< LCD PAL103: B04_0 Position */ -#define LCD_PAL103_B04_0_Msk (0x1fUL << LCD_PAL103_B04_0_Pos) /*!< LCD PAL103: B04_0 Mask */ -#define LCD_PAL103_I0_Pos 15 /*!< LCD PAL103: I0 Position */ -#define LCD_PAL103_I0_Msk (0x01UL << LCD_PAL103_I0_Pos) /*!< LCD PAL103: I0 Mask */ -#define LCD_PAL103_R14_0_Pos 16 /*!< LCD PAL103: R14_0 Position */ -#define LCD_PAL103_R14_0_Msk (0x1fUL << LCD_PAL103_R14_0_Pos) /*!< LCD PAL103: R14_0 Mask */ -#define LCD_PAL103_G14_0_Pos 21 /*!< LCD PAL103: G14_0 Position */ -#define LCD_PAL103_G14_0_Msk (0x1fUL << LCD_PAL103_G14_0_Pos) /*!< LCD PAL103: G14_0 Mask */ -#define LCD_PAL103_B14_0_Pos 26 /*!< LCD PAL103: B14_0 Position */ -#define LCD_PAL103_B14_0_Msk (0x1fUL << LCD_PAL103_B14_0_Pos) /*!< LCD PAL103: B14_0 Mask */ -#define LCD_PAL103_I1_Pos 31 /*!< LCD PAL103: I1 Position */ -#define LCD_PAL103_I1_Msk (0x01UL << LCD_PAL103_I1_Pos) /*!< LCD PAL103: I1 Mask */ - -// --------------------------------------- LCD_PAL104 ------------------------------------------- -#define LCD_PAL104_R04_0_Pos 0 /*!< LCD PAL104: R04_0 Position */ -#define LCD_PAL104_R04_0_Msk (0x1fUL << LCD_PAL104_R04_0_Pos) /*!< LCD PAL104: R04_0 Mask */ -#define LCD_PAL104_G04_0_Pos 5 /*!< LCD PAL104: G04_0 Position */ -#define LCD_PAL104_G04_0_Msk (0x1fUL << LCD_PAL104_G04_0_Pos) /*!< LCD PAL104: G04_0 Mask */ -#define LCD_PAL104_B04_0_Pos 10 /*!< LCD PAL104: B04_0 Position */ -#define LCD_PAL104_B04_0_Msk (0x1fUL << LCD_PAL104_B04_0_Pos) /*!< LCD PAL104: B04_0 Mask */ -#define LCD_PAL104_I0_Pos 15 /*!< LCD PAL104: I0 Position */ -#define LCD_PAL104_I0_Msk (0x01UL << LCD_PAL104_I0_Pos) /*!< LCD PAL104: I0 Mask */ -#define LCD_PAL104_R14_0_Pos 16 /*!< LCD PAL104: R14_0 Position */ -#define LCD_PAL104_R14_0_Msk (0x1fUL << LCD_PAL104_R14_0_Pos) /*!< LCD PAL104: R14_0 Mask */ -#define LCD_PAL104_G14_0_Pos 21 /*!< LCD PAL104: G14_0 Position */ -#define LCD_PAL104_G14_0_Msk (0x1fUL << LCD_PAL104_G14_0_Pos) /*!< LCD PAL104: G14_0 Mask */ -#define LCD_PAL104_B14_0_Pos 26 /*!< LCD PAL104: B14_0 Position */ -#define LCD_PAL104_B14_0_Msk (0x1fUL << LCD_PAL104_B14_0_Pos) /*!< LCD PAL104: B14_0 Mask */ -#define LCD_PAL104_I1_Pos 31 /*!< LCD PAL104: I1 Position */ -#define LCD_PAL104_I1_Msk (0x01UL << LCD_PAL104_I1_Pos) /*!< LCD PAL104: I1 Mask */ - -// --------------------------------------- LCD_PAL105 ------------------------------------------- -#define LCD_PAL105_R04_0_Pos 0 /*!< LCD PAL105: R04_0 Position */ -#define LCD_PAL105_R04_0_Msk (0x1fUL << LCD_PAL105_R04_0_Pos) /*!< LCD PAL105: R04_0 Mask */ -#define LCD_PAL105_G04_0_Pos 5 /*!< LCD PAL105: G04_0 Position */ -#define LCD_PAL105_G04_0_Msk (0x1fUL << LCD_PAL105_G04_0_Pos) /*!< LCD PAL105: G04_0 Mask */ -#define LCD_PAL105_B04_0_Pos 10 /*!< LCD PAL105: B04_0 Position */ -#define LCD_PAL105_B04_0_Msk (0x1fUL << LCD_PAL105_B04_0_Pos) /*!< LCD PAL105: B04_0 Mask */ -#define LCD_PAL105_I0_Pos 15 /*!< LCD PAL105: I0 Position */ -#define LCD_PAL105_I0_Msk (0x01UL << LCD_PAL105_I0_Pos) /*!< LCD PAL105: I0 Mask */ -#define LCD_PAL105_R14_0_Pos 16 /*!< LCD PAL105: R14_0 Position */ -#define LCD_PAL105_R14_0_Msk (0x1fUL << LCD_PAL105_R14_0_Pos) /*!< LCD PAL105: R14_0 Mask */ -#define LCD_PAL105_G14_0_Pos 21 /*!< LCD PAL105: G14_0 Position */ -#define LCD_PAL105_G14_0_Msk (0x1fUL << LCD_PAL105_G14_0_Pos) /*!< LCD PAL105: G14_0 Mask */ -#define LCD_PAL105_B14_0_Pos 26 /*!< LCD PAL105: B14_0 Position */ -#define LCD_PAL105_B14_0_Msk (0x1fUL << LCD_PAL105_B14_0_Pos) /*!< LCD PAL105: B14_0 Mask */ -#define LCD_PAL105_I1_Pos 31 /*!< LCD PAL105: I1 Position */ -#define LCD_PAL105_I1_Msk (0x01UL << LCD_PAL105_I1_Pos) /*!< LCD PAL105: I1 Mask */ - -// --------------------------------------- LCD_PAL106 ------------------------------------------- -#define LCD_PAL106_R04_0_Pos 0 /*!< LCD PAL106: R04_0 Position */ -#define LCD_PAL106_R04_0_Msk (0x1fUL << LCD_PAL106_R04_0_Pos) /*!< LCD PAL106: R04_0 Mask */ -#define LCD_PAL106_G04_0_Pos 5 /*!< LCD PAL106: G04_0 Position */ -#define LCD_PAL106_G04_0_Msk (0x1fUL << LCD_PAL106_G04_0_Pos) /*!< LCD PAL106: G04_0 Mask */ -#define LCD_PAL106_B04_0_Pos 10 /*!< LCD PAL106: B04_0 Position */ -#define LCD_PAL106_B04_0_Msk (0x1fUL << LCD_PAL106_B04_0_Pos) /*!< LCD PAL106: B04_0 Mask */ -#define LCD_PAL106_I0_Pos 15 /*!< LCD PAL106: I0 Position */ -#define LCD_PAL106_I0_Msk (0x01UL << LCD_PAL106_I0_Pos) /*!< LCD PAL106: I0 Mask */ -#define LCD_PAL106_R14_0_Pos 16 /*!< LCD PAL106: R14_0 Position */ -#define LCD_PAL106_R14_0_Msk (0x1fUL << LCD_PAL106_R14_0_Pos) /*!< LCD PAL106: R14_0 Mask */ -#define LCD_PAL106_G14_0_Pos 21 /*!< LCD PAL106: G14_0 Position */ -#define LCD_PAL106_G14_0_Msk (0x1fUL << LCD_PAL106_G14_0_Pos) /*!< LCD PAL106: G14_0 Mask */ -#define LCD_PAL106_B14_0_Pos 26 /*!< LCD PAL106: B14_0 Position */ -#define LCD_PAL106_B14_0_Msk (0x1fUL << LCD_PAL106_B14_0_Pos) /*!< LCD PAL106: B14_0 Mask */ -#define LCD_PAL106_I1_Pos 31 /*!< LCD PAL106: I1 Position */ -#define LCD_PAL106_I1_Msk (0x01UL << LCD_PAL106_I1_Pos) /*!< LCD PAL106: I1 Mask */ - -// --------------------------------------- LCD_PAL107 ------------------------------------------- -#define LCD_PAL107_R04_0_Pos 0 /*!< LCD PAL107: R04_0 Position */ -#define LCD_PAL107_R04_0_Msk (0x1fUL << LCD_PAL107_R04_0_Pos) /*!< LCD PAL107: R04_0 Mask */ -#define LCD_PAL107_G04_0_Pos 5 /*!< LCD PAL107: G04_0 Position */ -#define LCD_PAL107_G04_0_Msk (0x1fUL << LCD_PAL107_G04_0_Pos) /*!< LCD PAL107: G04_0 Mask */ -#define LCD_PAL107_B04_0_Pos 10 /*!< LCD PAL107: B04_0 Position */ -#define LCD_PAL107_B04_0_Msk (0x1fUL << LCD_PAL107_B04_0_Pos) /*!< LCD PAL107: B04_0 Mask */ -#define LCD_PAL107_I0_Pos 15 /*!< LCD PAL107: I0 Position */ -#define LCD_PAL107_I0_Msk (0x01UL << LCD_PAL107_I0_Pos) /*!< LCD PAL107: I0 Mask */ -#define LCD_PAL107_R14_0_Pos 16 /*!< LCD PAL107: R14_0 Position */ -#define LCD_PAL107_R14_0_Msk (0x1fUL << LCD_PAL107_R14_0_Pos) /*!< LCD PAL107: R14_0 Mask */ -#define LCD_PAL107_G14_0_Pos 21 /*!< LCD PAL107: G14_0 Position */ -#define LCD_PAL107_G14_0_Msk (0x1fUL << LCD_PAL107_G14_0_Pos) /*!< LCD PAL107: G14_0 Mask */ -#define LCD_PAL107_B14_0_Pos 26 /*!< LCD PAL107: B14_0 Position */ -#define LCD_PAL107_B14_0_Msk (0x1fUL << LCD_PAL107_B14_0_Pos) /*!< LCD PAL107: B14_0 Mask */ -#define LCD_PAL107_I1_Pos 31 /*!< LCD PAL107: I1 Position */ -#define LCD_PAL107_I1_Msk (0x01UL << LCD_PAL107_I1_Pos) /*!< LCD PAL107: I1 Mask */ - -// --------------------------------------- LCD_PAL108 ------------------------------------------- -#define LCD_PAL108_R04_0_Pos 0 /*!< LCD PAL108: R04_0 Position */ -#define LCD_PAL108_R04_0_Msk (0x1fUL << LCD_PAL108_R04_0_Pos) /*!< LCD PAL108: R04_0 Mask */ -#define LCD_PAL108_G04_0_Pos 5 /*!< LCD PAL108: G04_0 Position */ -#define LCD_PAL108_G04_0_Msk (0x1fUL << LCD_PAL108_G04_0_Pos) /*!< LCD PAL108: G04_0 Mask */ -#define LCD_PAL108_B04_0_Pos 10 /*!< LCD PAL108: B04_0 Position */ -#define LCD_PAL108_B04_0_Msk (0x1fUL << LCD_PAL108_B04_0_Pos) /*!< LCD PAL108: B04_0 Mask */ -#define LCD_PAL108_I0_Pos 15 /*!< LCD PAL108: I0 Position */ -#define LCD_PAL108_I0_Msk (0x01UL << LCD_PAL108_I0_Pos) /*!< LCD PAL108: I0 Mask */ -#define LCD_PAL108_R14_0_Pos 16 /*!< LCD PAL108: R14_0 Position */ -#define LCD_PAL108_R14_0_Msk (0x1fUL << LCD_PAL108_R14_0_Pos) /*!< LCD PAL108: R14_0 Mask */ -#define LCD_PAL108_G14_0_Pos 21 /*!< LCD PAL108: G14_0 Position */ -#define LCD_PAL108_G14_0_Msk (0x1fUL << LCD_PAL108_G14_0_Pos) /*!< LCD PAL108: G14_0 Mask */ -#define LCD_PAL108_B14_0_Pos 26 /*!< LCD PAL108: B14_0 Position */ -#define LCD_PAL108_B14_0_Msk (0x1fUL << LCD_PAL108_B14_0_Pos) /*!< LCD PAL108: B14_0 Mask */ -#define LCD_PAL108_I1_Pos 31 /*!< LCD PAL108: I1 Position */ -#define LCD_PAL108_I1_Msk (0x01UL << LCD_PAL108_I1_Pos) /*!< LCD PAL108: I1 Mask */ - -// --------------------------------------- LCD_PAL109 ------------------------------------------- -#define LCD_PAL109_R04_0_Pos 0 /*!< LCD PAL109: R04_0 Position */ -#define LCD_PAL109_R04_0_Msk (0x1fUL << LCD_PAL109_R04_0_Pos) /*!< LCD PAL109: R04_0 Mask */ -#define LCD_PAL109_G04_0_Pos 5 /*!< LCD PAL109: G04_0 Position */ -#define LCD_PAL109_G04_0_Msk (0x1fUL << LCD_PAL109_G04_0_Pos) /*!< LCD PAL109: G04_0 Mask */ -#define LCD_PAL109_B04_0_Pos 10 /*!< LCD PAL109: B04_0 Position */ -#define LCD_PAL109_B04_0_Msk (0x1fUL << LCD_PAL109_B04_0_Pos) /*!< LCD PAL109: B04_0 Mask */ -#define LCD_PAL109_I0_Pos 15 /*!< LCD PAL109: I0 Position */ -#define LCD_PAL109_I0_Msk (0x01UL << LCD_PAL109_I0_Pos) /*!< LCD PAL109: I0 Mask */ -#define LCD_PAL109_R14_0_Pos 16 /*!< LCD PAL109: R14_0 Position */ -#define LCD_PAL109_R14_0_Msk (0x1fUL << LCD_PAL109_R14_0_Pos) /*!< LCD PAL109: R14_0 Mask */ -#define LCD_PAL109_G14_0_Pos 21 /*!< LCD PAL109: G14_0 Position */ -#define LCD_PAL109_G14_0_Msk (0x1fUL << LCD_PAL109_G14_0_Pos) /*!< LCD PAL109: G14_0 Mask */ -#define LCD_PAL109_B14_0_Pos 26 /*!< LCD PAL109: B14_0 Position */ -#define LCD_PAL109_B14_0_Msk (0x1fUL << LCD_PAL109_B14_0_Pos) /*!< LCD PAL109: B14_0 Mask */ -#define LCD_PAL109_I1_Pos 31 /*!< LCD PAL109: I1 Position */ -#define LCD_PAL109_I1_Msk (0x01UL << LCD_PAL109_I1_Pos) /*!< LCD PAL109: I1 Mask */ - -// --------------------------------------- LCD_PAL110 ------------------------------------------- -#define LCD_PAL110_R04_0_Pos 0 /*!< LCD PAL110: R04_0 Position */ -#define LCD_PAL110_R04_0_Msk (0x1fUL << LCD_PAL110_R04_0_Pos) /*!< LCD PAL110: R04_0 Mask */ -#define LCD_PAL110_G04_0_Pos 5 /*!< LCD PAL110: G04_0 Position */ -#define LCD_PAL110_G04_0_Msk (0x1fUL << LCD_PAL110_G04_0_Pos) /*!< LCD PAL110: G04_0 Mask */ -#define LCD_PAL110_B04_0_Pos 10 /*!< LCD PAL110: B04_0 Position */ -#define LCD_PAL110_B04_0_Msk (0x1fUL << LCD_PAL110_B04_0_Pos) /*!< LCD PAL110: B04_0 Mask */ -#define LCD_PAL110_I0_Pos 15 /*!< LCD PAL110: I0 Position */ -#define LCD_PAL110_I0_Msk (0x01UL << LCD_PAL110_I0_Pos) /*!< LCD PAL110: I0 Mask */ -#define LCD_PAL110_R14_0_Pos 16 /*!< LCD PAL110: R14_0 Position */ -#define LCD_PAL110_R14_0_Msk (0x1fUL << LCD_PAL110_R14_0_Pos) /*!< LCD PAL110: R14_0 Mask */ -#define LCD_PAL110_G14_0_Pos 21 /*!< LCD PAL110: G14_0 Position */ -#define LCD_PAL110_G14_0_Msk (0x1fUL << LCD_PAL110_G14_0_Pos) /*!< LCD PAL110: G14_0 Mask */ -#define LCD_PAL110_B14_0_Pos 26 /*!< LCD PAL110: B14_0 Position */ -#define LCD_PAL110_B14_0_Msk (0x1fUL << LCD_PAL110_B14_0_Pos) /*!< LCD PAL110: B14_0 Mask */ -#define LCD_PAL110_I1_Pos 31 /*!< LCD PAL110: I1 Position */ -#define LCD_PAL110_I1_Msk (0x01UL << LCD_PAL110_I1_Pos) /*!< LCD PAL110: I1 Mask */ - -// --------------------------------------- LCD_PAL111 ------------------------------------------- -#define LCD_PAL111_R04_0_Pos 0 /*!< LCD PAL111: R04_0 Position */ -#define LCD_PAL111_R04_0_Msk (0x1fUL << LCD_PAL111_R04_0_Pos) /*!< LCD PAL111: R04_0 Mask */ -#define LCD_PAL111_G04_0_Pos 5 /*!< LCD PAL111: G04_0 Position */ -#define LCD_PAL111_G04_0_Msk (0x1fUL << LCD_PAL111_G04_0_Pos) /*!< LCD PAL111: G04_0 Mask */ -#define LCD_PAL111_B04_0_Pos 10 /*!< LCD PAL111: B04_0 Position */ -#define LCD_PAL111_B04_0_Msk (0x1fUL << LCD_PAL111_B04_0_Pos) /*!< LCD PAL111: B04_0 Mask */ -#define LCD_PAL111_I0_Pos 15 /*!< LCD PAL111: I0 Position */ -#define LCD_PAL111_I0_Msk (0x01UL << LCD_PAL111_I0_Pos) /*!< LCD PAL111: I0 Mask */ -#define LCD_PAL111_R14_0_Pos 16 /*!< LCD PAL111: R14_0 Position */ -#define LCD_PAL111_R14_0_Msk (0x1fUL << LCD_PAL111_R14_0_Pos) /*!< LCD PAL111: R14_0 Mask */ -#define LCD_PAL111_G14_0_Pos 21 /*!< LCD PAL111: G14_0 Position */ -#define LCD_PAL111_G14_0_Msk (0x1fUL << LCD_PAL111_G14_0_Pos) /*!< LCD PAL111: G14_0 Mask */ -#define LCD_PAL111_B14_0_Pos 26 /*!< LCD PAL111: B14_0 Position */ -#define LCD_PAL111_B14_0_Msk (0x1fUL << LCD_PAL111_B14_0_Pos) /*!< LCD PAL111: B14_0 Mask */ -#define LCD_PAL111_I1_Pos 31 /*!< LCD PAL111: I1 Position */ -#define LCD_PAL111_I1_Msk (0x01UL << LCD_PAL111_I1_Pos) /*!< LCD PAL111: I1 Mask */ - -// --------------------------------------- LCD_PAL112 ------------------------------------------- -#define LCD_PAL112_R04_0_Pos 0 /*!< LCD PAL112: R04_0 Position */ -#define LCD_PAL112_R04_0_Msk (0x1fUL << LCD_PAL112_R04_0_Pos) /*!< LCD PAL112: R04_0 Mask */ -#define LCD_PAL112_G04_0_Pos 5 /*!< LCD PAL112: G04_0 Position */ -#define LCD_PAL112_G04_0_Msk (0x1fUL << LCD_PAL112_G04_0_Pos) /*!< LCD PAL112: G04_0 Mask */ -#define LCD_PAL112_B04_0_Pos 10 /*!< LCD PAL112: B04_0 Position */ -#define LCD_PAL112_B04_0_Msk (0x1fUL << LCD_PAL112_B04_0_Pos) /*!< LCD PAL112: B04_0 Mask */ -#define LCD_PAL112_I0_Pos 15 /*!< LCD PAL112: I0 Position */ -#define LCD_PAL112_I0_Msk (0x01UL << LCD_PAL112_I0_Pos) /*!< LCD PAL112: I0 Mask */ -#define LCD_PAL112_R14_0_Pos 16 /*!< LCD PAL112: R14_0 Position */ -#define LCD_PAL112_R14_0_Msk (0x1fUL << LCD_PAL112_R14_0_Pos) /*!< LCD PAL112: R14_0 Mask */ -#define LCD_PAL112_G14_0_Pos 21 /*!< LCD PAL112: G14_0 Position */ -#define LCD_PAL112_G14_0_Msk (0x1fUL << LCD_PAL112_G14_0_Pos) /*!< LCD PAL112: G14_0 Mask */ -#define LCD_PAL112_B14_0_Pos 26 /*!< LCD PAL112: B14_0 Position */ -#define LCD_PAL112_B14_0_Msk (0x1fUL << LCD_PAL112_B14_0_Pos) /*!< LCD PAL112: B14_0 Mask */ -#define LCD_PAL112_I1_Pos 31 /*!< LCD PAL112: I1 Position */ -#define LCD_PAL112_I1_Msk (0x01UL << LCD_PAL112_I1_Pos) /*!< LCD PAL112: I1 Mask */ - -// --------------------------------------- LCD_PAL113 ------------------------------------------- -#define LCD_PAL113_R04_0_Pos 0 /*!< LCD PAL113: R04_0 Position */ -#define LCD_PAL113_R04_0_Msk (0x1fUL << LCD_PAL113_R04_0_Pos) /*!< LCD PAL113: R04_0 Mask */ -#define LCD_PAL113_G04_0_Pos 5 /*!< LCD PAL113: G04_0 Position */ -#define LCD_PAL113_G04_0_Msk (0x1fUL << LCD_PAL113_G04_0_Pos) /*!< LCD PAL113: G04_0 Mask */ -#define LCD_PAL113_B04_0_Pos 10 /*!< LCD PAL113: B04_0 Position */ -#define LCD_PAL113_B04_0_Msk (0x1fUL << LCD_PAL113_B04_0_Pos) /*!< LCD PAL113: B04_0 Mask */ -#define LCD_PAL113_I0_Pos 15 /*!< LCD PAL113: I0 Position */ -#define LCD_PAL113_I0_Msk (0x01UL << LCD_PAL113_I0_Pos) /*!< LCD PAL113: I0 Mask */ -#define LCD_PAL113_R14_0_Pos 16 /*!< LCD PAL113: R14_0 Position */ -#define LCD_PAL113_R14_0_Msk (0x1fUL << LCD_PAL113_R14_0_Pos) /*!< LCD PAL113: R14_0 Mask */ -#define LCD_PAL113_G14_0_Pos 21 /*!< LCD PAL113: G14_0 Position */ -#define LCD_PAL113_G14_0_Msk (0x1fUL << LCD_PAL113_G14_0_Pos) /*!< LCD PAL113: G14_0 Mask */ -#define LCD_PAL113_B14_0_Pos 26 /*!< LCD PAL113: B14_0 Position */ -#define LCD_PAL113_B14_0_Msk (0x1fUL << LCD_PAL113_B14_0_Pos) /*!< LCD PAL113: B14_0 Mask */ -#define LCD_PAL113_I1_Pos 31 /*!< LCD PAL113: I1 Position */ -#define LCD_PAL113_I1_Msk (0x01UL << LCD_PAL113_I1_Pos) /*!< LCD PAL113: I1 Mask */ - -// --------------------------------------- LCD_PAL114 ------------------------------------------- -#define LCD_PAL114_R04_0_Pos 0 /*!< LCD PAL114: R04_0 Position */ -#define LCD_PAL114_R04_0_Msk (0x1fUL << LCD_PAL114_R04_0_Pos) /*!< LCD PAL114: R04_0 Mask */ -#define LCD_PAL114_G04_0_Pos 5 /*!< LCD PAL114: G04_0 Position */ -#define LCD_PAL114_G04_0_Msk (0x1fUL << LCD_PAL114_G04_0_Pos) /*!< LCD PAL114: G04_0 Mask */ -#define LCD_PAL114_B04_0_Pos 10 /*!< LCD PAL114: B04_0 Position */ -#define LCD_PAL114_B04_0_Msk (0x1fUL << LCD_PAL114_B04_0_Pos) /*!< LCD PAL114: B04_0 Mask */ -#define LCD_PAL114_I0_Pos 15 /*!< LCD PAL114: I0 Position */ -#define LCD_PAL114_I0_Msk (0x01UL << LCD_PAL114_I0_Pos) /*!< LCD PAL114: I0 Mask */ -#define LCD_PAL114_R14_0_Pos 16 /*!< LCD PAL114: R14_0 Position */ -#define LCD_PAL114_R14_0_Msk (0x1fUL << LCD_PAL114_R14_0_Pos) /*!< LCD PAL114: R14_0 Mask */ -#define LCD_PAL114_G14_0_Pos 21 /*!< LCD PAL114: G14_0 Position */ -#define LCD_PAL114_G14_0_Msk (0x1fUL << LCD_PAL114_G14_0_Pos) /*!< LCD PAL114: G14_0 Mask */ -#define LCD_PAL114_B14_0_Pos 26 /*!< LCD PAL114: B14_0 Position */ -#define LCD_PAL114_B14_0_Msk (0x1fUL << LCD_PAL114_B14_0_Pos) /*!< LCD PAL114: B14_0 Mask */ -#define LCD_PAL114_I1_Pos 31 /*!< LCD PAL114: I1 Position */ -#define LCD_PAL114_I1_Msk (0x01UL << LCD_PAL114_I1_Pos) /*!< LCD PAL114: I1 Mask */ - -// --------------------------------------- LCD_PAL115 ------------------------------------------- -#define LCD_PAL115_R04_0_Pos 0 /*!< LCD PAL115: R04_0 Position */ -#define LCD_PAL115_R04_0_Msk (0x1fUL << LCD_PAL115_R04_0_Pos) /*!< LCD PAL115: R04_0 Mask */ -#define LCD_PAL115_G04_0_Pos 5 /*!< LCD PAL115: G04_0 Position */ -#define LCD_PAL115_G04_0_Msk (0x1fUL << LCD_PAL115_G04_0_Pos) /*!< LCD PAL115: G04_0 Mask */ -#define LCD_PAL115_B04_0_Pos 10 /*!< LCD PAL115: B04_0 Position */ -#define LCD_PAL115_B04_0_Msk (0x1fUL << LCD_PAL115_B04_0_Pos) /*!< LCD PAL115: B04_0 Mask */ -#define LCD_PAL115_I0_Pos 15 /*!< LCD PAL115: I0 Position */ -#define LCD_PAL115_I0_Msk (0x01UL << LCD_PAL115_I0_Pos) /*!< LCD PAL115: I0 Mask */ -#define LCD_PAL115_R14_0_Pos 16 /*!< LCD PAL115: R14_0 Position */ -#define LCD_PAL115_R14_0_Msk (0x1fUL << LCD_PAL115_R14_0_Pos) /*!< LCD PAL115: R14_0 Mask */ -#define LCD_PAL115_G14_0_Pos 21 /*!< LCD PAL115: G14_0 Position */ -#define LCD_PAL115_G14_0_Msk (0x1fUL << LCD_PAL115_G14_0_Pos) /*!< LCD PAL115: G14_0 Mask */ -#define LCD_PAL115_B14_0_Pos 26 /*!< LCD PAL115: B14_0 Position */ -#define LCD_PAL115_B14_0_Msk (0x1fUL << LCD_PAL115_B14_0_Pos) /*!< LCD PAL115: B14_0 Mask */ -#define LCD_PAL115_I1_Pos 31 /*!< LCD PAL115: I1 Position */ -#define LCD_PAL115_I1_Msk (0x01UL << LCD_PAL115_I1_Pos) /*!< LCD PAL115: I1 Mask */ - -// --------------------------------------- LCD_PAL116 ------------------------------------------- -#define LCD_PAL116_R04_0_Pos 0 /*!< LCD PAL116: R04_0 Position */ -#define LCD_PAL116_R04_0_Msk (0x1fUL << LCD_PAL116_R04_0_Pos) /*!< LCD PAL116: R04_0 Mask */ -#define LCD_PAL116_G04_0_Pos 5 /*!< LCD PAL116: G04_0 Position */ -#define LCD_PAL116_G04_0_Msk (0x1fUL << LCD_PAL116_G04_0_Pos) /*!< LCD PAL116: G04_0 Mask */ -#define LCD_PAL116_B04_0_Pos 10 /*!< LCD PAL116: B04_0 Position */ -#define LCD_PAL116_B04_0_Msk (0x1fUL << LCD_PAL116_B04_0_Pos) /*!< LCD PAL116: B04_0 Mask */ -#define LCD_PAL116_I0_Pos 15 /*!< LCD PAL116: I0 Position */ -#define LCD_PAL116_I0_Msk (0x01UL << LCD_PAL116_I0_Pos) /*!< LCD PAL116: I0 Mask */ -#define LCD_PAL116_R14_0_Pos 16 /*!< LCD PAL116: R14_0 Position */ -#define LCD_PAL116_R14_0_Msk (0x1fUL << LCD_PAL116_R14_0_Pos) /*!< LCD PAL116: R14_0 Mask */ -#define LCD_PAL116_G14_0_Pos 21 /*!< LCD PAL116: G14_0 Position */ -#define LCD_PAL116_G14_0_Msk (0x1fUL << LCD_PAL116_G14_0_Pos) /*!< LCD PAL116: G14_0 Mask */ -#define LCD_PAL116_B14_0_Pos 26 /*!< LCD PAL116: B14_0 Position */ -#define LCD_PAL116_B14_0_Msk (0x1fUL << LCD_PAL116_B14_0_Pos) /*!< LCD PAL116: B14_0 Mask */ -#define LCD_PAL116_I1_Pos 31 /*!< LCD PAL116: I1 Position */ -#define LCD_PAL116_I1_Msk (0x01UL << LCD_PAL116_I1_Pos) /*!< LCD PAL116: I1 Mask */ - -// --------------------------------------- LCD_PAL117 ------------------------------------------- -#define LCD_PAL117_R04_0_Pos 0 /*!< LCD PAL117: R04_0 Position */ -#define LCD_PAL117_R04_0_Msk (0x1fUL << LCD_PAL117_R04_0_Pos) /*!< LCD PAL117: R04_0 Mask */ -#define LCD_PAL117_G04_0_Pos 5 /*!< LCD PAL117: G04_0 Position */ -#define LCD_PAL117_G04_0_Msk (0x1fUL << LCD_PAL117_G04_0_Pos) /*!< LCD PAL117: G04_0 Mask */ -#define LCD_PAL117_B04_0_Pos 10 /*!< LCD PAL117: B04_0 Position */ -#define LCD_PAL117_B04_0_Msk (0x1fUL << LCD_PAL117_B04_0_Pos) /*!< LCD PAL117: B04_0 Mask */ -#define LCD_PAL117_I0_Pos 15 /*!< LCD PAL117: I0 Position */ -#define LCD_PAL117_I0_Msk (0x01UL << LCD_PAL117_I0_Pos) /*!< LCD PAL117: I0 Mask */ -#define LCD_PAL117_R14_0_Pos 16 /*!< LCD PAL117: R14_0 Position */ -#define LCD_PAL117_R14_0_Msk (0x1fUL << LCD_PAL117_R14_0_Pos) /*!< LCD PAL117: R14_0 Mask */ -#define LCD_PAL117_G14_0_Pos 21 /*!< LCD PAL117: G14_0 Position */ -#define LCD_PAL117_G14_0_Msk (0x1fUL << LCD_PAL117_G14_0_Pos) /*!< LCD PAL117: G14_0 Mask */ -#define LCD_PAL117_B14_0_Pos 26 /*!< LCD PAL117: B14_0 Position */ -#define LCD_PAL117_B14_0_Msk (0x1fUL << LCD_PAL117_B14_0_Pos) /*!< LCD PAL117: B14_0 Mask */ -#define LCD_PAL117_I1_Pos 31 /*!< LCD PAL117: I1 Position */ -#define LCD_PAL117_I1_Msk (0x01UL << LCD_PAL117_I1_Pos) /*!< LCD PAL117: I1 Mask */ - -// --------------------------------------- LCD_PAL118 ------------------------------------------- -#define LCD_PAL118_R04_0_Pos 0 /*!< LCD PAL118: R04_0 Position */ -#define LCD_PAL118_R04_0_Msk (0x1fUL << LCD_PAL118_R04_0_Pos) /*!< LCD PAL118: R04_0 Mask */ -#define LCD_PAL118_G04_0_Pos 5 /*!< LCD PAL118: G04_0 Position */ -#define LCD_PAL118_G04_0_Msk (0x1fUL << LCD_PAL118_G04_0_Pos) /*!< LCD PAL118: G04_0 Mask */ -#define LCD_PAL118_B04_0_Pos 10 /*!< LCD PAL118: B04_0 Position */ -#define LCD_PAL118_B04_0_Msk (0x1fUL << LCD_PAL118_B04_0_Pos) /*!< LCD PAL118: B04_0 Mask */ -#define LCD_PAL118_I0_Pos 15 /*!< LCD PAL118: I0 Position */ -#define LCD_PAL118_I0_Msk (0x01UL << LCD_PAL118_I0_Pos) /*!< LCD PAL118: I0 Mask */ -#define LCD_PAL118_R14_0_Pos 16 /*!< LCD PAL118: R14_0 Position */ -#define LCD_PAL118_R14_0_Msk (0x1fUL << LCD_PAL118_R14_0_Pos) /*!< LCD PAL118: R14_0 Mask */ -#define LCD_PAL118_G14_0_Pos 21 /*!< LCD PAL118: G14_0 Position */ -#define LCD_PAL118_G14_0_Msk (0x1fUL << LCD_PAL118_G14_0_Pos) /*!< LCD PAL118: G14_0 Mask */ -#define LCD_PAL118_B14_0_Pos 26 /*!< LCD PAL118: B14_0 Position */ -#define LCD_PAL118_B14_0_Msk (0x1fUL << LCD_PAL118_B14_0_Pos) /*!< LCD PAL118: B14_0 Mask */ -#define LCD_PAL118_I1_Pos 31 /*!< LCD PAL118: I1 Position */ -#define LCD_PAL118_I1_Msk (0x01UL << LCD_PAL118_I1_Pos) /*!< LCD PAL118: I1 Mask */ - -// --------------------------------------- LCD_PAL119 ------------------------------------------- -#define LCD_PAL119_R04_0_Pos 0 /*!< LCD PAL119: R04_0 Position */ -#define LCD_PAL119_R04_0_Msk (0x1fUL << LCD_PAL119_R04_0_Pos) /*!< LCD PAL119: R04_0 Mask */ -#define LCD_PAL119_G04_0_Pos 5 /*!< LCD PAL119: G04_0 Position */ -#define LCD_PAL119_G04_0_Msk (0x1fUL << LCD_PAL119_G04_0_Pos) /*!< LCD PAL119: G04_0 Mask */ -#define LCD_PAL119_B04_0_Pos 10 /*!< LCD PAL119: B04_0 Position */ -#define LCD_PAL119_B04_0_Msk (0x1fUL << LCD_PAL119_B04_0_Pos) /*!< LCD PAL119: B04_0 Mask */ -#define LCD_PAL119_I0_Pos 15 /*!< LCD PAL119: I0 Position */ -#define LCD_PAL119_I0_Msk (0x01UL << LCD_PAL119_I0_Pos) /*!< LCD PAL119: I0 Mask */ -#define LCD_PAL119_R14_0_Pos 16 /*!< LCD PAL119: R14_0 Position */ -#define LCD_PAL119_R14_0_Msk (0x1fUL << LCD_PAL119_R14_0_Pos) /*!< LCD PAL119: R14_0 Mask */ -#define LCD_PAL119_G14_0_Pos 21 /*!< LCD PAL119: G14_0 Position */ -#define LCD_PAL119_G14_0_Msk (0x1fUL << LCD_PAL119_G14_0_Pos) /*!< LCD PAL119: G14_0 Mask */ -#define LCD_PAL119_B14_0_Pos 26 /*!< LCD PAL119: B14_0 Position */ -#define LCD_PAL119_B14_0_Msk (0x1fUL << LCD_PAL119_B14_0_Pos) /*!< LCD PAL119: B14_0 Mask */ -#define LCD_PAL119_I1_Pos 31 /*!< LCD PAL119: I1 Position */ -#define LCD_PAL119_I1_Msk (0x01UL << LCD_PAL119_I1_Pos) /*!< LCD PAL119: I1 Mask */ - -// --------------------------------------- LCD_PAL120 ------------------------------------------- -#define LCD_PAL120_R04_0_Pos 0 /*!< LCD PAL120: R04_0 Position */ -#define LCD_PAL120_R04_0_Msk (0x1fUL << LCD_PAL120_R04_0_Pos) /*!< LCD PAL120: R04_0 Mask */ -#define LCD_PAL120_G04_0_Pos 5 /*!< LCD PAL120: G04_0 Position */ -#define LCD_PAL120_G04_0_Msk (0x1fUL << LCD_PAL120_G04_0_Pos) /*!< LCD PAL120: G04_0 Mask */ -#define LCD_PAL120_B04_0_Pos 10 /*!< LCD PAL120: B04_0 Position */ -#define LCD_PAL120_B04_0_Msk (0x1fUL << LCD_PAL120_B04_0_Pos) /*!< LCD PAL120: B04_0 Mask */ -#define LCD_PAL120_I0_Pos 15 /*!< LCD PAL120: I0 Position */ -#define LCD_PAL120_I0_Msk (0x01UL << LCD_PAL120_I0_Pos) /*!< LCD PAL120: I0 Mask */ -#define LCD_PAL120_R14_0_Pos 16 /*!< LCD PAL120: R14_0 Position */ -#define LCD_PAL120_R14_0_Msk (0x1fUL << LCD_PAL120_R14_0_Pos) /*!< LCD PAL120: R14_0 Mask */ -#define LCD_PAL120_G14_0_Pos 21 /*!< LCD PAL120: G14_0 Position */ -#define LCD_PAL120_G14_0_Msk (0x1fUL << LCD_PAL120_G14_0_Pos) /*!< LCD PAL120: G14_0 Mask */ -#define LCD_PAL120_B14_0_Pos 26 /*!< LCD PAL120: B14_0 Position */ -#define LCD_PAL120_B14_0_Msk (0x1fUL << LCD_PAL120_B14_0_Pos) /*!< LCD PAL120: B14_0 Mask */ -#define LCD_PAL120_I1_Pos 31 /*!< LCD PAL120: I1 Position */ -#define LCD_PAL120_I1_Msk (0x01UL << LCD_PAL120_I1_Pos) /*!< LCD PAL120: I1 Mask */ - -// --------------------------------------- LCD_PAL121 ------------------------------------------- -#define LCD_PAL121_R04_0_Pos 0 /*!< LCD PAL121: R04_0 Position */ -#define LCD_PAL121_R04_0_Msk (0x1fUL << LCD_PAL121_R04_0_Pos) /*!< LCD PAL121: R04_0 Mask */ -#define LCD_PAL121_G04_0_Pos 5 /*!< LCD PAL121: G04_0 Position */ -#define LCD_PAL121_G04_0_Msk (0x1fUL << LCD_PAL121_G04_0_Pos) /*!< LCD PAL121: G04_0 Mask */ -#define LCD_PAL121_B04_0_Pos 10 /*!< LCD PAL121: B04_0 Position */ -#define LCD_PAL121_B04_0_Msk (0x1fUL << LCD_PAL121_B04_0_Pos) /*!< LCD PAL121: B04_0 Mask */ -#define LCD_PAL121_I0_Pos 15 /*!< LCD PAL121: I0 Position */ -#define LCD_PAL121_I0_Msk (0x01UL << LCD_PAL121_I0_Pos) /*!< LCD PAL121: I0 Mask */ -#define LCD_PAL121_R14_0_Pos 16 /*!< LCD PAL121: R14_0 Position */ -#define LCD_PAL121_R14_0_Msk (0x1fUL << LCD_PAL121_R14_0_Pos) /*!< LCD PAL121: R14_0 Mask */ -#define LCD_PAL121_G14_0_Pos 21 /*!< LCD PAL121: G14_0 Position */ -#define LCD_PAL121_G14_0_Msk (0x1fUL << LCD_PAL121_G14_0_Pos) /*!< LCD PAL121: G14_0 Mask */ -#define LCD_PAL121_B14_0_Pos 26 /*!< LCD PAL121: B14_0 Position */ -#define LCD_PAL121_B14_0_Msk (0x1fUL << LCD_PAL121_B14_0_Pos) /*!< LCD PAL121: B14_0 Mask */ -#define LCD_PAL121_I1_Pos 31 /*!< LCD PAL121: I1 Position */ -#define LCD_PAL121_I1_Msk (0x01UL << LCD_PAL121_I1_Pos) /*!< LCD PAL121: I1 Mask */ - -// --------------------------------------- LCD_PAL122 ------------------------------------------- -#define LCD_PAL122_R04_0_Pos 0 /*!< LCD PAL122: R04_0 Position */ -#define LCD_PAL122_R04_0_Msk (0x1fUL << LCD_PAL122_R04_0_Pos) /*!< LCD PAL122: R04_0 Mask */ -#define LCD_PAL122_G04_0_Pos 5 /*!< LCD PAL122: G04_0 Position */ -#define LCD_PAL122_G04_0_Msk (0x1fUL << LCD_PAL122_G04_0_Pos) /*!< LCD PAL122: G04_0 Mask */ -#define LCD_PAL122_B04_0_Pos 10 /*!< LCD PAL122: B04_0 Position */ -#define LCD_PAL122_B04_0_Msk (0x1fUL << LCD_PAL122_B04_0_Pos) /*!< LCD PAL122: B04_0 Mask */ -#define LCD_PAL122_I0_Pos 15 /*!< LCD PAL122: I0 Position */ -#define LCD_PAL122_I0_Msk (0x01UL << LCD_PAL122_I0_Pos) /*!< LCD PAL122: I0 Mask */ -#define LCD_PAL122_R14_0_Pos 16 /*!< LCD PAL122: R14_0 Position */ -#define LCD_PAL122_R14_0_Msk (0x1fUL << LCD_PAL122_R14_0_Pos) /*!< LCD PAL122: R14_0 Mask */ -#define LCD_PAL122_G14_0_Pos 21 /*!< LCD PAL122: G14_0 Position */ -#define LCD_PAL122_G14_0_Msk (0x1fUL << LCD_PAL122_G14_0_Pos) /*!< LCD PAL122: G14_0 Mask */ -#define LCD_PAL122_B14_0_Pos 26 /*!< LCD PAL122: B14_0 Position */ -#define LCD_PAL122_B14_0_Msk (0x1fUL << LCD_PAL122_B14_0_Pos) /*!< LCD PAL122: B14_0 Mask */ -#define LCD_PAL122_I1_Pos 31 /*!< LCD PAL122: I1 Position */ -#define LCD_PAL122_I1_Msk (0x01UL << LCD_PAL122_I1_Pos) /*!< LCD PAL122: I1 Mask */ - -// --------------------------------------- LCD_PAL123 ------------------------------------------- -#define LCD_PAL123_R04_0_Pos 0 /*!< LCD PAL123: R04_0 Position */ -#define LCD_PAL123_R04_0_Msk (0x1fUL << LCD_PAL123_R04_0_Pos) /*!< LCD PAL123: R04_0 Mask */ -#define LCD_PAL123_G04_0_Pos 5 /*!< LCD PAL123: G04_0 Position */ -#define LCD_PAL123_G04_0_Msk (0x1fUL << LCD_PAL123_G04_0_Pos) /*!< LCD PAL123: G04_0 Mask */ -#define LCD_PAL123_B04_0_Pos 10 /*!< LCD PAL123: B04_0 Position */ -#define LCD_PAL123_B04_0_Msk (0x1fUL << LCD_PAL123_B04_0_Pos) /*!< LCD PAL123: B04_0 Mask */ -#define LCD_PAL123_I0_Pos 15 /*!< LCD PAL123: I0 Position */ -#define LCD_PAL123_I0_Msk (0x01UL << LCD_PAL123_I0_Pos) /*!< LCD PAL123: I0 Mask */ -#define LCD_PAL123_R14_0_Pos 16 /*!< LCD PAL123: R14_0 Position */ -#define LCD_PAL123_R14_0_Msk (0x1fUL << LCD_PAL123_R14_0_Pos) /*!< LCD PAL123: R14_0 Mask */ -#define LCD_PAL123_G14_0_Pos 21 /*!< LCD PAL123: G14_0 Position */ -#define LCD_PAL123_G14_0_Msk (0x1fUL << LCD_PAL123_G14_0_Pos) /*!< LCD PAL123: G14_0 Mask */ -#define LCD_PAL123_B14_0_Pos 26 /*!< LCD PAL123: B14_0 Position */ -#define LCD_PAL123_B14_0_Msk (0x1fUL << LCD_PAL123_B14_0_Pos) /*!< LCD PAL123: B14_0 Mask */ -#define LCD_PAL123_I1_Pos 31 /*!< LCD PAL123: I1 Position */ -#define LCD_PAL123_I1_Msk (0x01UL << LCD_PAL123_I1_Pos) /*!< LCD PAL123: I1 Mask */ - -// --------------------------------------- LCD_PAL124 ------------------------------------------- -#define LCD_PAL124_R04_0_Pos 0 /*!< LCD PAL124: R04_0 Position */ -#define LCD_PAL124_R04_0_Msk (0x1fUL << LCD_PAL124_R04_0_Pos) /*!< LCD PAL124: R04_0 Mask */ -#define LCD_PAL124_G04_0_Pos 5 /*!< LCD PAL124: G04_0 Position */ -#define LCD_PAL124_G04_0_Msk (0x1fUL << LCD_PAL124_G04_0_Pos) /*!< LCD PAL124: G04_0 Mask */ -#define LCD_PAL124_B04_0_Pos 10 /*!< LCD PAL124: B04_0 Position */ -#define LCD_PAL124_B04_0_Msk (0x1fUL << LCD_PAL124_B04_0_Pos) /*!< LCD PAL124: B04_0 Mask */ -#define LCD_PAL124_I0_Pos 15 /*!< LCD PAL124: I0 Position */ -#define LCD_PAL124_I0_Msk (0x01UL << LCD_PAL124_I0_Pos) /*!< LCD PAL124: I0 Mask */ -#define LCD_PAL124_R14_0_Pos 16 /*!< LCD PAL124: R14_0 Position */ -#define LCD_PAL124_R14_0_Msk (0x1fUL << LCD_PAL124_R14_0_Pos) /*!< LCD PAL124: R14_0 Mask */ -#define LCD_PAL124_G14_0_Pos 21 /*!< LCD PAL124: G14_0 Position */ -#define LCD_PAL124_G14_0_Msk (0x1fUL << LCD_PAL124_G14_0_Pos) /*!< LCD PAL124: G14_0 Mask */ -#define LCD_PAL124_B14_0_Pos 26 /*!< LCD PAL124: B14_0 Position */ -#define LCD_PAL124_B14_0_Msk (0x1fUL << LCD_PAL124_B14_0_Pos) /*!< LCD PAL124: B14_0 Mask */ -#define LCD_PAL124_I1_Pos 31 /*!< LCD PAL124: I1 Position */ -#define LCD_PAL124_I1_Msk (0x01UL << LCD_PAL124_I1_Pos) /*!< LCD PAL124: I1 Mask */ - -// --------------------------------------- LCD_PAL125 ------------------------------------------- -#define LCD_PAL125_R04_0_Pos 0 /*!< LCD PAL125: R04_0 Position */ -#define LCD_PAL125_R04_0_Msk (0x1fUL << LCD_PAL125_R04_0_Pos) /*!< LCD PAL125: R04_0 Mask */ -#define LCD_PAL125_G04_0_Pos 5 /*!< LCD PAL125: G04_0 Position */ -#define LCD_PAL125_G04_0_Msk (0x1fUL << LCD_PAL125_G04_0_Pos) /*!< LCD PAL125: G04_0 Mask */ -#define LCD_PAL125_B04_0_Pos 10 /*!< LCD PAL125: B04_0 Position */ -#define LCD_PAL125_B04_0_Msk (0x1fUL << LCD_PAL125_B04_0_Pos) /*!< LCD PAL125: B04_0 Mask */ -#define LCD_PAL125_I0_Pos 15 /*!< LCD PAL125: I0 Position */ -#define LCD_PAL125_I0_Msk (0x01UL << LCD_PAL125_I0_Pos) /*!< LCD PAL125: I0 Mask */ -#define LCD_PAL125_R14_0_Pos 16 /*!< LCD PAL125: R14_0 Position */ -#define LCD_PAL125_R14_0_Msk (0x1fUL << LCD_PAL125_R14_0_Pos) /*!< LCD PAL125: R14_0 Mask */ -#define LCD_PAL125_G14_0_Pos 21 /*!< LCD PAL125: G14_0 Position */ -#define LCD_PAL125_G14_0_Msk (0x1fUL << LCD_PAL125_G14_0_Pos) /*!< LCD PAL125: G14_0 Mask */ -#define LCD_PAL125_B14_0_Pos 26 /*!< LCD PAL125: B14_0 Position */ -#define LCD_PAL125_B14_0_Msk (0x1fUL << LCD_PAL125_B14_0_Pos) /*!< LCD PAL125: B14_0 Mask */ -#define LCD_PAL125_I1_Pos 31 /*!< LCD PAL125: I1 Position */ -#define LCD_PAL125_I1_Msk (0x01UL << LCD_PAL125_I1_Pos) /*!< LCD PAL125: I1 Mask */ - -// --------------------------------------- LCD_PAL126 ------------------------------------------- -#define LCD_PAL126_R04_0_Pos 0 /*!< LCD PAL126: R04_0 Position */ -#define LCD_PAL126_R04_0_Msk (0x1fUL << LCD_PAL126_R04_0_Pos) /*!< LCD PAL126: R04_0 Mask */ -#define LCD_PAL126_G04_0_Pos 5 /*!< LCD PAL126: G04_0 Position */ -#define LCD_PAL126_G04_0_Msk (0x1fUL << LCD_PAL126_G04_0_Pos) /*!< LCD PAL126: G04_0 Mask */ -#define LCD_PAL126_B04_0_Pos 10 /*!< LCD PAL126: B04_0 Position */ -#define LCD_PAL126_B04_0_Msk (0x1fUL << LCD_PAL126_B04_0_Pos) /*!< LCD PAL126: B04_0 Mask */ -#define LCD_PAL126_I0_Pos 15 /*!< LCD PAL126: I0 Position */ -#define LCD_PAL126_I0_Msk (0x01UL << LCD_PAL126_I0_Pos) /*!< LCD PAL126: I0 Mask */ -#define LCD_PAL126_R14_0_Pos 16 /*!< LCD PAL126: R14_0 Position */ -#define LCD_PAL126_R14_0_Msk (0x1fUL << LCD_PAL126_R14_0_Pos) /*!< LCD PAL126: R14_0 Mask */ -#define LCD_PAL126_G14_0_Pos 21 /*!< LCD PAL126: G14_0 Position */ -#define LCD_PAL126_G14_0_Msk (0x1fUL << LCD_PAL126_G14_0_Pos) /*!< LCD PAL126: G14_0 Mask */ -#define LCD_PAL126_B14_0_Pos 26 /*!< LCD PAL126: B14_0 Position */ -#define LCD_PAL126_B14_0_Msk (0x1fUL << LCD_PAL126_B14_0_Pos) /*!< LCD PAL126: B14_0 Mask */ -#define LCD_PAL126_I1_Pos 31 /*!< LCD PAL126: I1 Position */ -#define LCD_PAL126_I1_Msk (0x01UL << LCD_PAL126_I1_Pos) /*!< LCD PAL126: I1 Mask */ - -// --------------------------------------- LCD_PAL127 ------------------------------------------- -#define LCD_PAL127_R04_0_Pos 0 /*!< LCD PAL127: R04_0 Position */ -#define LCD_PAL127_R04_0_Msk (0x1fUL << LCD_PAL127_R04_0_Pos) /*!< LCD PAL127: R04_0 Mask */ -#define LCD_PAL127_G04_0_Pos 5 /*!< LCD PAL127: G04_0 Position */ -#define LCD_PAL127_G04_0_Msk (0x1fUL << LCD_PAL127_G04_0_Pos) /*!< LCD PAL127: G04_0 Mask */ -#define LCD_PAL127_B04_0_Pos 10 /*!< LCD PAL127: B04_0 Position */ -#define LCD_PAL127_B04_0_Msk (0x1fUL << LCD_PAL127_B04_0_Pos) /*!< LCD PAL127: B04_0 Mask */ -#define LCD_PAL127_I0_Pos 15 /*!< LCD PAL127: I0 Position */ -#define LCD_PAL127_I0_Msk (0x01UL << LCD_PAL127_I0_Pos) /*!< LCD PAL127: I0 Mask */ -#define LCD_PAL127_R14_0_Pos 16 /*!< LCD PAL127: R14_0 Position */ -#define LCD_PAL127_R14_0_Msk (0x1fUL << LCD_PAL127_R14_0_Pos) /*!< LCD PAL127: R14_0 Mask */ -#define LCD_PAL127_G14_0_Pos 21 /*!< LCD PAL127: G14_0 Position */ -#define LCD_PAL127_G14_0_Msk (0x1fUL << LCD_PAL127_G14_0_Pos) /*!< LCD PAL127: G14_0 Mask */ -#define LCD_PAL127_B14_0_Pos 26 /*!< LCD PAL127: B14_0 Position */ -#define LCD_PAL127_B14_0_Msk (0x1fUL << LCD_PAL127_B14_0_Pos) /*!< LCD PAL127: B14_0 Mask */ -#define LCD_PAL127_I1_Pos 31 /*!< LCD PAL127: I1 Position */ -#define LCD_PAL127_I1_Msk (0x01UL << LCD_PAL127_I1_Pos) /*!< LCD PAL127: I1 Mask */ - -// --------------------------------------- LCD_PAL128 ------------------------------------------- -#define LCD_PAL128_R04_0_Pos 0 /*!< LCD PAL128: R04_0 Position */ -#define LCD_PAL128_R04_0_Msk (0x1fUL << LCD_PAL128_R04_0_Pos) /*!< LCD PAL128: R04_0 Mask */ -#define LCD_PAL128_G04_0_Pos 5 /*!< LCD PAL128: G04_0 Position */ -#define LCD_PAL128_G04_0_Msk (0x1fUL << LCD_PAL128_G04_0_Pos) /*!< LCD PAL128: G04_0 Mask */ -#define LCD_PAL128_B04_0_Pos 10 /*!< LCD PAL128: B04_0 Position */ -#define LCD_PAL128_B04_0_Msk (0x1fUL << LCD_PAL128_B04_0_Pos) /*!< LCD PAL128: B04_0 Mask */ -#define LCD_PAL128_I0_Pos 15 /*!< LCD PAL128: I0 Position */ -#define LCD_PAL128_I0_Msk (0x01UL << LCD_PAL128_I0_Pos) /*!< LCD PAL128: I0 Mask */ -#define LCD_PAL128_R14_0_Pos 16 /*!< LCD PAL128: R14_0 Position */ -#define LCD_PAL128_R14_0_Msk (0x1fUL << LCD_PAL128_R14_0_Pos) /*!< LCD PAL128: R14_0 Mask */ -#define LCD_PAL128_G14_0_Pos 21 /*!< LCD PAL128: G14_0 Position */ -#define LCD_PAL128_G14_0_Msk (0x1fUL << LCD_PAL128_G14_0_Pos) /*!< LCD PAL128: G14_0 Mask */ -#define LCD_PAL128_B14_0_Pos 26 /*!< LCD PAL128: B14_0 Position */ -#define LCD_PAL128_B14_0_Msk (0x1fUL << LCD_PAL128_B14_0_Pos) /*!< LCD PAL128: B14_0 Mask */ -#define LCD_PAL128_I1_Pos 31 /*!< LCD PAL128: I1 Position */ -#define LCD_PAL128_I1_Msk (0x01UL << LCD_PAL128_I1_Pos) /*!< LCD PAL128: I1 Mask */ - -// --------------------------------------- LCD_PAL129 ------------------------------------------- -#define LCD_PAL129_R04_0_Pos 0 /*!< LCD PAL129: R04_0 Position */ -#define LCD_PAL129_R04_0_Msk (0x1fUL << LCD_PAL129_R04_0_Pos) /*!< LCD PAL129: R04_0 Mask */ -#define LCD_PAL129_G04_0_Pos 5 /*!< LCD PAL129: G04_0 Position */ -#define LCD_PAL129_G04_0_Msk (0x1fUL << LCD_PAL129_G04_0_Pos) /*!< LCD PAL129: G04_0 Mask */ -#define LCD_PAL129_B04_0_Pos 10 /*!< LCD PAL129: B04_0 Position */ -#define LCD_PAL129_B04_0_Msk (0x1fUL << LCD_PAL129_B04_0_Pos) /*!< LCD PAL129: B04_0 Mask */ -#define LCD_PAL129_I0_Pos 15 /*!< LCD PAL129: I0 Position */ -#define LCD_PAL129_I0_Msk (0x01UL << LCD_PAL129_I0_Pos) /*!< LCD PAL129: I0 Mask */ -#define LCD_PAL129_R14_0_Pos 16 /*!< LCD PAL129: R14_0 Position */ -#define LCD_PAL129_R14_0_Msk (0x1fUL << LCD_PAL129_R14_0_Pos) /*!< LCD PAL129: R14_0 Mask */ -#define LCD_PAL129_G14_0_Pos 21 /*!< LCD PAL129: G14_0 Position */ -#define LCD_PAL129_G14_0_Msk (0x1fUL << LCD_PAL129_G14_0_Pos) /*!< LCD PAL129: G14_0 Mask */ -#define LCD_PAL129_B14_0_Pos 26 /*!< LCD PAL129: B14_0 Position */ -#define LCD_PAL129_B14_0_Msk (0x1fUL << LCD_PAL129_B14_0_Pos) /*!< LCD PAL129: B14_0 Mask */ -#define LCD_PAL129_I1_Pos 31 /*!< LCD PAL129: I1 Position */ -#define LCD_PAL129_I1_Msk (0x01UL << LCD_PAL129_I1_Pos) /*!< LCD PAL129: I1 Mask */ - -// --------------------------------------- LCD_PAL130 ------------------------------------------- -#define LCD_PAL130_R04_0_Pos 0 /*!< LCD PAL130: R04_0 Position */ -#define LCD_PAL130_R04_0_Msk (0x1fUL << LCD_PAL130_R04_0_Pos) /*!< LCD PAL130: R04_0 Mask */ -#define LCD_PAL130_G04_0_Pos 5 /*!< LCD PAL130: G04_0 Position */ -#define LCD_PAL130_G04_0_Msk (0x1fUL << LCD_PAL130_G04_0_Pos) /*!< LCD PAL130: G04_0 Mask */ -#define LCD_PAL130_B04_0_Pos 10 /*!< LCD PAL130: B04_0 Position */ -#define LCD_PAL130_B04_0_Msk (0x1fUL << LCD_PAL130_B04_0_Pos) /*!< LCD PAL130: B04_0 Mask */ -#define LCD_PAL130_I0_Pos 15 /*!< LCD PAL130: I0 Position */ -#define LCD_PAL130_I0_Msk (0x01UL << LCD_PAL130_I0_Pos) /*!< LCD PAL130: I0 Mask */ -#define LCD_PAL130_R14_0_Pos 16 /*!< LCD PAL130: R14_0 Position */ -#define LCD_PAL130_R14_0_Msk (0x1fUL << LCD_PAL130_R14_0_Pos) /*!< LCD PAL130: R14_0 Mask */ -#define LCD_PAL130_G14_0_Pos 21 /*!< LCD PAL130: G14_0 Position */ -#define LCD_PAL130_G14_0_Msk (0x1fUL << LCD_PAL130_G14_0_Pos) /*!< LCD PAL130: G14_0 Mask */ -#define LCD_PAL130_B14_0_Pos 26 /*!< LCD PAL130: B14_0 Position */ -#define LCD_PAL130_B14_0_Msk (0x1fUL << LCD_PAL130_B14_0_Pos) /*!< LCD PAL130: B14_0 Mask */ -#define LCD_PAL130_I1_Pos 31 /*!< LCD PAL130: I1 Position */ -#define LCD_PAL130_I1_Msk (0x01UL << LCD_PAL130_I1_Pos) /*!< LCD PAL130: I1 Mask */ - -// --------------------------------------- LCD_PAL131 ------------------------------------------- -#define LCD_PAL131_R04_0_Pos 0 /*!< LCD PAL131: R04_0 Position */ -#define LCD_PAL131_R04_0_Msk (0x1fUL << LCD_PAL131_R04_0_Pos) /*!< LCD PAL131: R04_0 Mask */ -#define LCD_PAL131_G04_0_Pos 5 /*!< LCD PAL131: G04_0 Position */ -#define LCD_PAL131_G04_0_Msk (0x1fUL << LCD_PAL131_G04_0_Pos) /*!< LCD PAL131: G04_0 Mask */ -#define LCD_PAL131_B04_0_Pos 10 /*!< LCD PAL131: B04_0 Position */ -#define LCD_PAL131_B04_0_Msk (0x1fUL << LCD_PAL131_B04_0_Pos) /*!< LCD PAL131: B04_0 Mask */ -#define LCD_PAL131_I0_Pos 15 /*!< LCD PAL131: I0 Position */ -#define LCD_PAL131_I0_Msk (0x01UL << LCD_PAL131_I0_Pos) /*!< LCD PAL131: I0 Mask */ -#define LCD_PAL131_R14_0_Pos 16 /*!< LCD PAL131: R14_0 Position */ -#define LCD_PAL131_R14_0_Msk (0x1fUL << LCD_PAL131_R14_0_Pos) /*!< LCD PAL131: R14_0 Mask */ -#define LCD_PAL131_G14_0_Pos 21 /*!< LCD PAL131: G14_0 Position */ -#define LCD_PAL131_G14_0_Msk (0x1fUL << LCD_PAL131_G14_0_Pos) /*!< LCD PAL131: G14_0 Mask */ -#define LCD_PAL131_B14_0_Pos 26 /*!< LCD PAL131: B14_0 Position */ -#define LCD_PAL131_B14_0_Msk (0x1fUL << LCD_PAL131_B14_0_Pos) /*!< LCD PAL131: B14_0 Mask */ -#define LCD_PAL131_I1_Pos 31 /*!< LCD PAL131: I1 Position */ -#define LCD_PAL131_I1_Msk (0x01UL << LCD_PAL131_I1_Pos) /*!< LCD PAL131: I1 Mask */ - -// --------------------------------------- LCD_PAL132 ------------------------------------------- -#define LCD_PAL132_R04_0_Pos 0 /*!< LCD PAL132: R04_0 Position */ -#define LCD_PAL132_R04_0_Msk (0x1fUL << LCD_PAL132_R04_0_Pos) /*!< LCD PAL132: R04_0 Mask */ -#define LCD_PAL132_G04_0_Pos 5 /*!< LCD PAL132: G04_0 Position */ -#define LCD_PAL132_G04_0_Msk (0x1fUL << LCD_PAL132_G04_0_Pos) /*!< LCD PAL132: G04_0 Mask */ -#define LCD_PAL132_B04_0_Pos 10 /*!< LCD PAL132: B04_0 Position */ -#define LCD_PAL132_B04_0_Msk (0x1fUL << LCD_PAL132_B04_0_Pos) /*!< LCD PAL132: B04_0 Mask */ -#define LCD_PAL132_I0_Pos 15 /*!< LCD PAL132: I0 Position */ -#define LCD_PAL132_I0_Msk (0x01UL << LCD_PAL132_I0_Pos) /*!< LCD PAL132: I0 Mask */ -#define LCD_PAL132_R14_0_Pos 16 /*!< LCD PAL132: R14_0 Position */ -#define LCD_PAL132_R14_0_Msk (0x1fUL << LCD_PAL132_R14_0_Pos) /*!< LCD PAL132: R14_0 Mask */ -#define LCD_PAL132_G14_0_Pos 21 /*!< LCD PAL132: G14_0 Position */ -#define LCD_PAL132_G14_0_Msk (0x1fUL << LCD_PAL132_G14_0_Pos) /*!< LCD PAL132: G14_0 Mask */ -#define LCD_PAL132_B14_0_Pos 26 /*!< LCD PAL132: B14_0 Position */ -#define LCD_PAL132_B14_0_Msk (0x1fUL << LCD_PAL132_B14_0_Pos) /*!< LCD PAL132: B14_0 Mask */ -#define LCD_PAL132_I1_Pos 31 /*!< LCD PAL132: I1 Position */ -#define LCD_PAL132_I1_Msk (0x01UL << LCD_PAL132_I1_Pos) /*!< LCD PAL132: I1 Mask */ - -// --------------------------------------- LCD_PAL133 ------------------------------------------- -#define LCD_PAL133_R04_0_Pos 0 /*!< LCD PAL133: R04_0 Position */ -#define LCD_PAL133_R04_0_Msk (0x1fUL << LCD_PAL133_R04_0_Pos) /*!< LCD PAL133: R04_0 Mask */ -#define LCD_PAL133_G04_0_Pos 5 /*!< LCD PAL133: G04_0 Position */ -#define LCD_PAL133_G04_0_Msk (0x1fUL << LCD_PAL133_G04_0_Pos) /*!< LCD PAL133: G04_0 Mask */ -#define LCD_PAL133_B04_0_Pos 10 /*!< LCD PAL133: B04_0 Position */ -#define LCD_PAL133_B04_0_Msk (0x1fUL << LCD_PAL133_B04_0_Pos) /*!< LCD PAL133: B04_0 Mask */ -#define LCD_PAL133_I0_Pos 15 /*!< LCD PAL133: I0 Position */ -#define LCD_PAL133_I0_Msk (0x01UL << LCD_PAL133_I0_Pos) /*!< LCD PAL133: I0 Mask */ -#define LCD_PAL133_R14_0_Pos 16 /*!< LCD PAL133: R14_0 Position */ -#define LCD_PAL133_R14_0_Msk (0x1fUL << LCD_PAL133_R14_0_Pos) /*!< LCD PAL133: R14_0 Mask */ -#define LCD_PAL133_G14_0_Pos 21 /*!< LCD PAL133: G14_0 Position */ -#define LCD_PAL133_G14_0_Msk (0x1fUL << LCD_PAL133_G14_0_Pos) /*!< LCD PAL133: G14_0 Mask */ -#define LCD_PAL133_B14_0_Pos 26 /*!< LCD PAL133: B14_0 Position */ -#define LCD_PAL133_B14_0_Msk (0x1fUL << LCD_PAL133_B14_0_Pos) /*!< LCD PAL133: B14_0 Mask */ -#define LCD_PAL133_I1_Pos 31 /*!< LCD PAL133: I1 Position */ -#define LCD_PAL133_I1_Msk (0x01UL << LCD_PAL133_I1_Pos) /*!< LCD PAL133: I1 Mask */ - -// --------------------------------------- LCD_PAL134 ------------------------------------------- -#define LCD_PAL134_R04_0_Pos 0 /*!< LCD PAL134: R04_0 Position */ -#define LCD_PAL134_R04_0_Msk (0x1fUL << LCD_PAL134_R04_0_Pos) /*!< LCD PAL134: R04_0 Mask */ -#define LCD_PAL134_G04_0_Pos 5 /*!< LCD PAL134: G04_0 Position */ -#define LCD_PAL134_G04_0_Msk (0x1fUL << LCD_PAL134_G04_0_Pos) /*!< LCD PAL134: G04_0 Mask */ -#define LCD_PAL134_B04_0_Pos 10 /*!< LCD PAL134: B04_0 Position */ -#define LCD_PAL134_B04_0_Msk (0x1fUL << LCD_PAL134_B04_0_Pos) /*!< LCD PAL134: B04_0 Mask */ -#define LCD_PAL134_I0_Pos 15 /*!< LCD PAL134: I0 Position */ -#define LCD_PAL134_I0_Msk (0x01UL << LCD_PAL134_I0_Pos) /*!< LCD PAL134: I0 Mask */ -#define LCD_PAL134_R14_0_Pos 16 /*!< LCD PAL134: R14_0 Position */ -#define LCD_PAL134_R14_0_Msk (0x1fUL << LCD_PAL134_R14_0_Pos) /*!< LCD PAL134: R14_0 Mask */ -#define LCD_PAL134_G14_0_Pos 21 /*!< LCD PAL134: G14_0 Position */ -#define LCD_PAL134_G14_0_Msk (0x1fUL << LCD_PAL134_G14_0_Pos) /*!< LCD PAL134: G14_0 Mask */ -#define LCD_PAL134_B14_0_Pos 26 /*!< LCD PAL134: B14_0 Position */ -#define LCD_PAL134_B14_0_Msk (0x1fUL << LCD_PAL134_B14_0_Pos) /*!< LCD PAL134: B14_0 Mask */ -#define LCD_PAL134_I1_Pos 31 /*!< LCD PAL134: I1 Position */ -#define LCD_PAL134_I1_Msk (0x01UL << LCD_PAL134_I1_Pos) /*!< LCD PAL134: I1 Mask */ - -// --------------------------------------- LCD_PAL135 ------------------------------------------- -#define LCD_PAL135_R04_0_Pos 0 /*!< LCD PAL135: R04_0 Position */ -#define LCD_PAL135_R04_0_Msk (0x1fUL << LCD_PAL135_R04_0_Pos) /*!< LCD PAL135: R04_0 Mask */ -#define LCD_PAL135_G04_0_Pos 5 /*!< LCD PAL135: G04_0 Position */ -#define LCD_PAL135_G04_0_Msk (0x1fUL << LCD_PAL135_G04_0_Pos) /*!< LCD PAL135: G04_0 Mask */ -#define LCD_PAL135_B04_0_Pos 10 /*!< LCD PAL135: B04_0 Position */ -#define LCD_PAL135_B04_0_Msk (0x1fUL << LCD_PAL135_B04_0_Pos) /*!< LCD PAL135: B04_0 Mask */ -#define LCD_PAL135_I0_Pos 15 /*!< LCD PAL135: I0 Position */ -#define LCD_PAL135_I0_Msk (0x01UL << LCD_PAL135_I0_Pos) /*!< LCD PAL135: I0 Mask */ -#define LCD_PAL135_R14_0_Pos 16 /*!< LCD PAL135: R14_0 Position */ -#define LCD_PAL135_R14_0_Msk (0x1fUL << LCD_PAL135_R14_0_Pos) /*!< LCD PAL135: R14_0 Mask */ -#define LCD_PAL135_G14_0_Pos 21 /*!< LCD PAL135: G14_0 Position */ -#define LCD_PAL135_G14_0_Msk (0x1fUL << LCD_PAL135_G14_0_Pos) /*!< LCD PAL135: G14_0 Mask */ -#define LCD_PAL135_B14_0_Pos 26 /*!< LCD PAL135: B14_0 Position */ -#define LCD_PAL135_B14_0_Msk (0x1fUL << LCD_PAL135_B14_0_Pos) /*!< LCD PAL135: B14_0 Mask */ -#define LCD_PAL135_I1_Pos 31 /*!< LCD PAL135: I1 Position */ -#define LCD_PAL135_I1_Msk (0x01UL << LCD_PAL135_I1_Pos) /*!< LCD PAL135: I1 Mask */ - -// --------------------------------------- LCD_PAL136 ------------------------------------------- -#define LCD_PAL136_R04_0_Pos 0 /*!< LCD PAL136: R04_0 Position */ -#define LCD_PAL136_R04_0_Msk (0x1fUL << LCD_PAL136_R04_0_Pos) /*!< LCD PAL136: R04_0 Mask */ -#define LCD_PAL136_G04_0_Pos 5 /*!< LCD PAL136: G04_0 Position */ -#define LCD_PAL136_G04_0_Msk (0x1fUL << LCD_PAL136_G04_0_Pos) /*!< LCD PAL136: G04_0 Mask */ -#define LCD_PAL136_B04_0_Pos 10 /*!< LCD PAL136: B04_0 Position */ -#define LCD_PAL136_B04_0_Msk (0x1fUL << LCD_PAL136_B04_0_Pos) /*!< LCD PAL136: B04_0 Mask */ -#define LCD_PAL136_I0_Pos 15 /*!< LCD PAL136: I0 Position */ -#define LCD_PAL136_I0_Msk (0x01UL << LCD_PAL136_I0_Pos) /*!< LCD PAL136: I0 Mask */ -#define LCD_PAL136_R14_0_Pos 16 /*!< LCD PAL136: R14_0 Position */ -#define LCD_PAL136_R14_0_Msk (0x1fUL << LCD_PAL136_R14_0_Pos) /*!< LCD PAL136: R14_0 Mask */ -#define LCD_PAL136_G14_0_Pos 21 /*!< LCD PAL136: G14_0 Position */ -#define LCD_PAL136_G14_0_Msk (0x1fUL << LCD_PAL136_G14_0_Pos) /*!< LCD PAL136: G14_0 Mask */ -#define LCD_PAL136_B14_0_Pos 26 /*!< LCD PAL136: B14_0 Position */ -#define LCD_PAL136_B14_0_Msk (0x1fUL << LCD_PAL136_B14_0_Pos) /*!< LCD PAL136: B14_0 Mask */ -#define LCD_PAL136_I1_Pos 31 /*!< LCD PAL136: I1 Position */ -#define LCD_PAL136_I1_Msk (0x01UL << LCD_PAL136_I1_Pos) /*!< LCD PAL136: I1 Mask */ - -// --------------------------------------- LCD_PAL137 ------------------------------------------- -#define LCD_PAL137_R04_0_Pos 0 /*!< LCD PAL137: R04_0 Position */ -#define LCD_PAL137_R04_0_Msk (0x1fUL << LCD_PAL137_R04_0_Pos) /*!< LCD PAL137: R04_0 Mask */ -#define LCD_PAL137_G04_0_Pos 5 /*!< LCD PAL137: G04_0 Position */ -#define LCD_PAL137_G04_0_Msk (0x1fUL << LCD_PAL137_G04_0_Pos) /*!< LCD PAL137: G04_0 Mask */ -#define LCD_PAL137_B04_0_Pos 10 /*!< LCD PAL137: B04_0 Position */ -#define LCD_PAL137_B04_0_Msk (0x1fUL << LCD_PAL137_B04_0_Pos) /*!< LCD PAL137: B04_0 Mask */ -#define LCD_PAL137_I0_Pos 15 /*!< LCD PAL137: I0 Position */ -#define LCD_PAL137_I0_Msk (0x01UL << LCD_PAL137_I0_Pos) /*!< LCD PAL137: I0 Mask */ -#define LCD_PAL137_R14_0_Pos 16 /*!< LCD PAL137: R14_0 Position */ -#define LCD_PAL137_R14_0_Msk (0x1fUL << LCD_PAL137_R14_0_Pos) /*!< LCD PAL137: R14_0 Mask */ -#define LCD_PAL137_G14_0_Pos 21 /*!< LCD PAL137: G14_0 Position */ -#define LCD_PAL137_G14_0_Msk (0x1fUL << LCD_PAL137_G14_0_Pos) /*!< LCD PAL137: G14_0 Mask */ -#define LCD_PAL137_B14_0_Pos 26 /*!< LCD PAL137: B14_0 Position */ -#define LCD_PAL137_B14_0_Msk (0x1fUL << LCD_PAL137_B14_0_Pos) /*!< LCD PAL137: B14_0 Mask */ -#define LCD_PAL137_I1_Pos 31 /*!< LCD PAL137: I1 Position */ -#define LCD_PAL137_I1_Msk (0x01UL << LCD_PAL137_I1_Pos) /*!< LCD PAL137: I1 Mask */ - -// --------------------------------------- LCD_PAL138 ------------------------------------------- -#define LCD_PAL138_R04_0_Pos 0 /*!< LCD PAL138: R04_0 Position */ -#define LCD_PAL138_R04_0_Msk (0x1fUL << LCD_PAL138_R04_0_Pos) /*!< LCD PAL138: R04_0 Mask */ -#define LCD_PAL138_G04_0_Pos 5 /*!< LCD PAL138: G04_0 Position */ -#define LCD_PAL138_G04_0_Msk (0x1fUL << LCD_PAL138_G04_0_Pos) /*!< LCD PAL138: G04_0 Mask */ -#define LCD_PAL138_B04_0_Pos 10 /*!< LCD PAL138: B04_0 Position */ -#define LCD_PAL138_B04_0_Msk (0x1fUL << LCD_PAL138_B04_0_Pos) /*!< LCD PAL138: B04_0 Mask */ -#define LCD_PAL138_I0_Pos 15 /*!< LCD PAL138: I0 Position */ -#define LCD_PAL138_I0_Msk (0x01UL << LCD_PAL138_I0_Pos) /*!< LCD PAL138: I0 Mask */ -#define LCD_PAL138_R14_0_Pos 16 /*!< LCD PAL138: R14_0 Position */ -#define LCD_PAL138_R14_0_Msk (0x1fUL << LCD_PAL138_R14_0_Pos) /*!< LCD PAL138: R14_0 Mask */ -#define LCD_PAL138_G14_0_Pos 21 /*!< LCD PAL138: G14_0 Position */ -#define LCD_PAL138_G14_0_Msk (0x1fUL << LCD_PAL138_G14_0_Pos) /*!< LCD PAL138: G14_0 Mask */ -#define LCD_PAL138_B14_0_Pos 26 /*!< LCD PAL138: B14_0 Position */ -#define LCD_PAL138_B14_0_Msk (0x1fUL << LCD_PAL138_B14_0_Pos) /*!< LCD PAL138: B14_0 Mask */ -#define LCD_PAL138_I1_Pos 31 /*!< LCD PAL138: I1 Position */ -#define LCD_PAL138_I1_Msk (0x01UL << LCD_PAL138_I1_Pos) /*!< LCD PAL138: I1 Mask */ - -// --------------------------------------- LCD_PAL139 ------------------------------------------- -#define LCD_PAL139_R04_0_Pos 0 /*!< LCD PAL139: R04_0 Position */ -#define LCD_PAL139_R04_0_Msk (0x1fUL << LCD_PAL139_R04_0_Pos) /*!< LCD PAL139: R04_0 Mask */ -#define LCD_PAL139_G04_0_Pos 5 /*!< LCD PAL139: G04_0 Position */ -#define LCD_PAL139_G04_0_Msk (0x1fUL << LCD_PAL139_G04_0_Pos) /*!< LCD PAL139: G04_0 Mask */ -#define LCD_PAL139_B04_0_Pos 10 /*!< LCD PAL139: B04_0 Position */ -#define LCD_PAL139_B04_0_Msk (0x1fUL << LCD_PAL139_B04_0_Pos) /*!< LCD PAL139: B04_0 Mask */ -#define LCD_PAL139_I0_Pos 15 /*!< LCD PAL139: I0 Position */ -#define LCD_PAL139_I0_Msk (0x01UL << LCD_PAL139_I0_Pos) /*!< LCD PAL139: I0 Mask */ -#define LCD_PAL139_R14_0_Pos 16 /*!< LCD PAL139: R14_0 Position */ -#define LCD_PAL139_R14_0_Msk (0x1fUL << LCD_PAL139_R14_0_Pos) /*!< LCD PAL139: R14_0 Mask */ -#define LCD_PAL139_G14_0_Pos 21 /*!< LCD PAL139: G14_0 Position */ -#define LCD_PAL139_G14_0_Msk (0x1fUL << LCD_PAL139_G14_0_Pos) /*!< LCD PAL139: G14_0 Mask */ -#define LCD_PAL139_B14_0_Pos 26 /*!< LCD PAL139: B14_0 Position */ -#define LCD_PAL139_B14_0_Msk (0x1fUL << LCD_PAL139_B14_0_Pos) /*!< LCD PAL139: B14_0 Mask */ -#define LCD_PAL139_I1_Pos 31 /*!< LCD PAL139: I1 Position */ -#define LCD_PAL139_I1_Msk (0x01UL << LCD_PAL139_I1_Pos) /*!< LCD PAL139: I1 Mask */ - -// --------------------------------------- LCD_PAL140 ------------------------------------------- -#define LCD_PAL140_R04_0_Pos 0 /*!< LCD PAL140: R04_0 Position */ -#define LCD_PAL140_R04_0_Msk (0x1fUL << LCD_PAL140_R04_0_Pos) /*!< LCD PAL140: R04_0 Mask */ -#define LCD_PAL140_G04_0_Pos 5 /*!< LCD PAL140: G04_0 Position */ -#define LCD_PAL140_G04_0_Msk (0x1fUL << LCD_PAL140_G04_0_Pos) /*!< LCD PAL140: G04_0 Mask */ -#define LCD_PAL140_B04_0_Pos 10 /*!< LCD PAL140: B04_0 Position */ -#define LCD_PAL140_B04_0_Msk (0x1fUL << LCD_PAL140_B04_0_Pos) /*!< LCD PAL140: B04_0 Mask */ -#define LCD_PAL140_I0_Pos 15 /*!< LCD PAL140: I0 Position */ -#define LCD_PAL140_I0_Msk (0x01UL << LCD_PAL140_I0_Pos) /*!< LCD PAL140: I0 Mask */ -#define LCD_PAL140_R14_0_Pos 16 /*!< LCD PAL140: R14_0 Position */ -#define LCD_PAL140_R14_0_Msk (0x1fUL << LCD_PAL140_R14_0_Pos) /*!< LCD PAL140: R14_0 Mask */ -#define LCD_PAL140_G14_0_Pos 21 /*!< LCD PAL140: G14_0 Position */ -#define LCD_PAL140_G14_0_Msk (0x1fUL << LCD_PAL140_G14_0_Pos) /*!< LCD PAL140: G14_0 Mask */ -#define LCD_PAL140_B14_0_Pos 26 /*!< LCD PAL140: B14_0 Position */ -#define LCD_PAL140_B14_0_Msk (0x1fUL << LCD_PAL140_B14_0_Pos) /*!< LCD PAL140: B14_0 Mask */ -#define LCD_PAL140_I1_Pos 31 /*!< LCD PAL140: I1 Position */ -#define LCD_PAL140_I1_Msk (0x01UL << LCD_PAL140_I1_Pos) /*!< LCD PAL140: I1 Mask */ - -// --------------------------------------- LCD_PAL141 ------------------------------------------- -#define LCD_PAL141_R04_0_Pos 0 /*!< LCD PAL141: R04_0 Position */ -#define LCD_PAL141_R04_0_Msk (0x1fUL << LCD_PAL141_R04_0_Pos) /*!< LCD PAL141: R04_0 Mask */ -#define LCD_PAL141_G04_0_Pos 5 /*!< LCD PAL141: G04_0 Position */ -#define LCD_PAL141_G04_0_Msk (0x1fUL << LCD_PAL141_G04_0_Pos) /*!< LCD PAL141: G04_0 Mask */ -#define LCD_PAL141_B04_0_Pos 10 /*!< LCD PAL141: B04_0 Position */ -#define LCD_PAL141_B04_0_Msk (0x1fUL << LCD_PAL141_B04_0_Pos) /*!< LCD PAL141: B04_0 Mask */ -#define LCD_PAL141_I0_Pos 15 /*!< LCD PAL141: I0 Position */ -#define LCD_PAL141_I0_Msk (0x01UL << LCD_PAL141_I0_Pos) /*!< LCD PAL141: I0 Mask */ -#define LCD_PAL141_R14_0_Pos 16 /*!< LCD PAL141: R14_0 Position */ -#define LCD_PAL141_R14_0_Msk (0x1fUL << LCD_PAL141_R14_0_Pos) /*!< LCD PAL141: R14_0 Mask */ -#define LCD_PAL141_G14_0_Pos 21 /*!< LCD PAL141: G14_0 Position */ -#define LCD_PAL141_G14_0_Msk (0x1fUL << LCD_PAL141_G14_0_Pos) /*!< LCD PAL141: G14_0 Mask */ -#define LCD_PAL141_B14_0_Pos 26 /*!< LCD PAL141: B14_0 Position */ -#define LCD_PAL141_B14_0_Msk (0x1fUL << LCD_PAL141_B14_0_Pos) /*!< LCD PAL141: B14_0 Mask */ -#define LCD_PAL141_I1_Pos 31 /*!< LCD PAL141: I1 Position */ -#define LCD_PAL141_I1_Msk (0x01UL << LCD_PAL141_I1_Pos) /*!< LCD PAL141: I1 Mask */ - -// --------------------------------------- LCD_PAL142 ------------------------------------------- -#define LCD_PAL142_R04_0_Pos 0 /*!< LCD PAL142: R04_0 Position */ -#define LCD_PAL142_R04_0_Msk (0x1fUL << LCD_PAL142_R04_0_Pos) /*!< LCD PAL142: R04_0 Mask */ -#define LCD_PAL142_G04_0_Pos 5 /*!< LCD PAL142: G04_0 Position */ -#define LCD_PAL142_G04_0_Msk (0x1fUL << LCD_PAL142_G04_0_Pos) /*!< LCD PAL142: G04_0 Mask */ -#define LCD_PAL142_B04_0_Pos 10 /*!< LCD PAL142: B04_0 Position */ -#define LCD_PAL142_B04_0_Msk (0x1fUL << LCD_PAL142_B04_0_Pos) /*!< LCD PAL142: B04_0 Mask */ -#define LCD_PAL142_I0_Pos 15 /*!< LCD PAL142: I0 Position */ -#define LCD_PAL142_I0_Msk (0x01UL << LCD_PAL142_I0_Pos) /*!< LCD PAL142: I0 Mask */ -#define LCD_PAL142_R14_0_Pos 16 /*!< LCD PAL142: R14_0 Position */ -#define LCD_PAL142_R14_0_Msk (0x1fUL << LCD_PAL142_R14_0_Pos) /*!< LCD PAL142: R14_0 Mask */ -#define LCD_PAL142_G14_0_Pos 21 /*!< LCD PAL142: G14_0 Position */ -#define LCD_PAL142_G14_0_Msk (0x1fUL << LCD_PAL142_G14_0_Pos) /*!< LCD PAL142: G14_0 Mask */ -#define LCD_PAL142_B14_0_Pos 26 /*!< LCD PAL142: B14_0 Position */ -#define LCD_PAL142_B14_0_Msk (0x1fUL << LCD_PAL142_B14_0_Pos) /*!< LCD PAL142: B14_0 Mask */ -#define LCD_PAL142_I1_Pos 31 /*!< LCD PAL142: I1 Position */ -#define LCD_PAL142_I1_Msk (0x01UL << LCD_PAL142_I1_Pos) /*!< LCD PAL142: I1 Mask */ - -// --------------------------------------- LCD_PAL143 ------------------------------------------- -#define LCD_PAL143_R04_0_Pos 0 /*!< LCD PAL143: R04_0 Position */ -#define LCD_PAL143_R04_0_Msk (0x1fUL << LCD_PAL143_R04_0_Pos) /*!< LCD PAL143: R04_0 Mask */ -#define LCD_PAL143_G04_0_Pos 5 /*!< LCD PAL143: G04_0 Position */ -#define LCD_PAL143_G04_0_Msk (0x1fUL << LCD_PAL143_G04_0_Pos) /*!< LCD PAL143: G04_0 Mask */ -#define LCD_PAL143_B04_0_Pos 10 /*!< LCD PAL143: B04_0 Position */ -#define LCD_PAL143_B04_0_Msk (0x1fUL << LCD_PAL143_B04_0_Pos) /*!< LCD PAL143: B04_0 Mask */ -#define LCD_PAL143_I0_Pos 15 /*!< LCD PAL143: I0 Position */ -#define LCD_PAL143_I0_Msk (0x01UL << LCD_PAL143_I0_Pos) /*!< LCD PAL143: I0 Mask */ -#define LCD_PAL143_R14_0_Pos 16 /*!< LCD PAL143: R14_0 Position */ -#define LCD_PAL143_R14_0_Msk (0x1fUL << LCD_PAL143_R14_0_Pos) /*!< LCD PAL143: R14_0 Mask */ -#define LCD_PAL143_G14_0_Pos 21 /*!< LCD PAL143: G14_0 Position */ -#define LCD_PAL143_G14_0_Msk (0x1fUL << LCD_PAL143_G14_0_Pos) /*!< LCD PAL143: G14_0 Mask */ -#define LCD_PAL143_B14_0_Pos 26 /*!< LCD PAL143: B14_0 Position */ -#define LCD_PAL143_B14_0_Msk (0x1fUL << LCD_PAL143_B14_0_Pos) /*!< LCD PAL143: B14_0 Mask */ -#define LCD_PAL143_I1_Pos 31 /*!< LCD PAL143: I1 Position */ -#define LCD_PAL143_I1_Msk (0x01UL << LCD_PAL143_I1_Pos) /*!< LCD PAL143: I1 Mask */ - -// --------------------------------------- LCD_PAL144 ------------------------------------------- -#define LCD_PAL144_R04_0_Pos 0 /*!< LCD PAL144: R04_0 Position */ -#define LCD_PAL144_R04_0_Msk (0x1fUL << LCD_PAL144_R04_0_Pos) /*!< LCD PAL144: R04_0 Mask */ -#define LCD_PAL144_G04_0_Pos 5 /*!< LCD PAL144: G04_0 Position */ -#define LCD_PAL144_G04_0_Msk (0x1fUL << LCD_PAL144_G04_0_Pos) /*!< LCD PAL144: G04_0 Mask */ -#define LCD_PAL144_B04_0_Pos 10 /*!< LCD PAL144: B04_0 Position */ -#define LCD_PAL144_B04_0_Msk (0x1fUL << LCD_PAL144_B04_0_Pos) /*!< LCD PAL144: B04_0 Mask */ -#define LCD_PAL144_I0_Pos 15 /*!< LCD PAL144: I0 Position */ -#define LCD_PAL144_I0_Msk (0x01UL << LCD_PAL144_I0_Pos) /*!< LCD PAL144: I0 Mask */ -#define LCD_PAL144_R14_0_Pos 16 /*!< LCD PAL144: R14_0 Position */ -#define LCD_PAL144_R14_0_Msk (0x1fUL << LCD_PAL144_R14_0_Pos) /*!< LCD PAL144: R14_0 Mask */ -#define LCD_PAL144_G14_0_Pos 21 /*!< LCD PAL144: G14_0 Position */ -#define LCD_PAL144_G14_0_Msk (0x1fUL << LCD_PAL144_G14_0_Pos) /*!< LCD PAL144: G14_0 Mask */ -#define LCD_PAL144_B14_0_Pos 26 /*!< LCD PAL144: B14_0 Position */ -#define LCD_PAL144_B14_0_Msk (0x1fUL << LCD_PAL144_B14_0_Pos) /*!< LCD PAL144: B14_0 Mask */ -#define LCD_PAL144_I1_Pos 31 /*!< LCD PAL144: I1 Position */ -#define LCD_PAL144_I1_Msk (0x01UL << LCD_PAL144_I1_Pos) /*!< LCD PAL144: I1 Mask */ - -// --------------------------------------- LCD_PAL145 ------------------------------------------- -#define LCD_PAL145_R04_0_Pos 0 /*!< LCD PAL145: R04_0 Position */ -#define LCD_PAL145_R04_0_Msk (0x1fUL << LCD_PAL145_R04_0_Pos) /*!< LCD PAL145: R04_0 Mask */ -#define LCD_PAL145_G04_0_Pos 5 /*!< LCD PAL145: G04_0 Position */ -#define LCD_PAL145_G04_0_Msk (0x1fUL << LCD_PAL145_G04_0_Pos) /*!< LCD PAL145: G04_0 Mask */ -#define LCD_PAL145_B04_0_Pos 10 /*!< LCD PAL145: B04_0 Position */ -#define LCD_PAL145_B04_0_Msk (0x1fUL << LCD_PAL145_B04_0_Pos) /*!< LCD PAL145: B04_0 Mask */ -#define LCD_PAL145_I0_Pos 15 /*!< LCD PAL145: I0 Position */ -#define LCD_PAL145_I0_Msk (0x01UL << LCD_PAL145_I0_Pos) /*!< LCD PAL145: I0 Mask */ -#define LCD_PAL145_R14_0_Pos 16 /*!< LCD PAL145: R14_0 Position */ -#define LCD_PAL145_R14_0_Msk (0x1fUL << LCD_PAL145_R14_0_Pos) /*!< LCD PAL145: R14_0 Mask */ -#define LCD_PAL145_G14_0_Pos 21 /*!< LCD PAL145: G14_0 Position */ -#define LCD_PAL145_G14_0_Msk (0x1fUL << LCD_PAL145_G14_0_Pos) /*!< LCD PAL145: G14_0 Mask */ -#define LCD_PAL145_B14_0_Pos 26 /*!< LCD PAL145: B14_0 Position */ -#define LCD_PAL145_B14_0_Msk (0x1fUL << LCD_PAL145_B14_0_Pos) /*!< LCD PAL145: B14_0 Mask */ -#define LCD_PAL145_I1_Pos 31 /*!< LCD PAL145: I1 Position */ -#define LCD_PAL145_I1_Msk (0x01UL << LCD_PAL145_I1_Pos) /*!< LCD PAL145: I1 Mask */ - -// --------------------------------------- LCD_PAL146 ------------------------------------------- -#define LCD_PAL146_R04_0_Pos 0 /*!< LCD PAL146: R04_0 Position */ -#define LCD_PAL146_R04_0_Msk (0x1fUL << LCD_PAL146_R04_0_Pos) /*!< LCD PAL146: R04_0 Mask */ -#define LCD_PAL146_G04_0_Pos 5 /*!< LCD PAL146: G04_0 Position */ -#define LCD_PAL146_G04_0_Msk (0x1fUL << LCD_PAL146_G04_0_Pos) /*!< LCD PAL146: G04_0 Mask */ -#define LCD_PAL146_B04_0_Pos 10 /*!< LCD PAL146: B04_0 Position */ -#define LCD_PAL146_B04_0_Msk (0x1fUL << LCD_PAL146_B04_0_Pos) /*!< LCD PAL146: B04_0 Mask */ -#define LCD_PAL146_I0_Pos 15 /*!< LCD PAL146: I0 Position */ -#define LCD_PAL146_I0_Msk (0x01UL << LCD_PAL146_I0_Pos) /*!< LCD PAL146: I0 Mask */ -#define LCD_PAL146_R14_0_Pos 16 /*!< LCD PAL146: R14_0 Position */ -#define LCD_PAL146_R14_0_Msk (0x1fUL << LCD_PAL146_R14_0_Pos) /*!< LCD PAL146: R14_0 Mask */ -#define LCD_PAL146_G14_0_Pos 21 /*!< LCD PAL146: G14_0 Position */ -#define LCD_PAL146_G14_0_Msk (0x1fUL << LCD_PAL146_G14_0_Pos) /*!< LCD PAL146: G14_0 Mask */ -#define LCD_PAL146_B14_0_Pos 26 /*!< LCD PAL146: B14_0 Position */ -#define LCD_PAL146_B14_0_Msk (0x1fUL << LCD_PAL146_B14_0_Pos) /*!< LCD PAL146: B14_0 Mask */ -#define LCD_PAL146_I1_Pos 31 /*!< LCD PAL146: I1 Position */ -#define LCD_PAL146_I1_Msk (0x01UL << LCD_PAL146_I1_Pos) /*!< LCD PAL146: I1 Mask */ - -// --------------------------------------- LCD_PAL147 ------------------------------------------- -#define LCD_PAL147_R04_0_Pos 0 /*!< LCD PAL147: R04_0 Position */ -#define LCD_PAL147_R04_0_Msk (0x1fUL << LCD_PAL147_R04_0_Pos) /*!< LCD PAL147: R04_0 Mask */ -#define LCD_PAL147_G04_0_Pos 5 /*!< LCD PAL147: G04_0 Position */ -#define LCD_PAL147_G04_0_Msk (0x1fUL << LCD_PAL147_G04_0_Pos) /*!< LCD PAL147: G04_0 Mask */ -#define LCD_PAL147_B04_0_Pos 10 /*!< LCD PAL147: B04_0 Position */ -#define LCD_PAL147_B04_0_Msk (0x1fUL << LCD_PAL147_B04_0_Pos) /*!< LCD PAL147: B04_0 Mask */ -#define LCD_PAL147_I0_Pos 15 /*!< LCD PAL147: I0 Position */ -#define LCD_PAL147_I0_Msk (0x01UL << LCD_PAL147_I0_Pos) /*!< LCD PAL147: I0 Mask */ -#define LCD_PAL147_R14_0_Pos 16 /*!< LCD PAL147: R14_0 Position */ -#define LCD_PAL147_R14_0_Msk (0x1fUL << LCD_PAL147_R14_0_Pos) /*!< LCD PAL147: R14_0 Mask */ -#define LCD_PAL147_G14_0_Pos 21 /*!< LCD PAL147: G14_0 Position */ -#define LCD_PAL147_G14_0_Msk (0x1fUL << LCD_PAL147_G14_0_Pos) /*!< LCD PAL147: G14_0 Mask */ -#define LCD_PAL147_B14_0_Pos 26 /*!< LCD PAL147: B14_0 Position */ -#define LCD_PAL147_B14_0_Msk (0x1fUL << LCD_PAL147_B14_0_Pos) /*!< LCD PAL147: B14_0 Mask */ -#define LCD_PAL147_I1_Pos 31 /*!< LCD PAL147: I1 Position */ -#define LCD_PAL147_I1_Msk (0x01UL << LCD_PAL147_I1_Pos) /*!< LCD PAL147: I1 Mask */ - -// --------------------------------------- LCD_PAL148 ------------------------------------------- -#define LCD_PAL148_R04_0_Pos 0 /*!< LCD PAL148: R04_0 Position */ -#define LCD_PAL148_R04_0_Msk (0x1fUL << LCD_PAL148_R04_0_Pos) /*!< LCD PAL148: R04_0 Mask */ -#define LCD_PAL148_G04_0_Pos 5 /*!< LCD PAL148: G04_0 Position */ -#define LCD_PAL148_G04_0_Msk (0x1fUL << LCD_PAL148_G04_0_Pos) /*!< LCD PAL148: G04_0 Mask */ -#define LCD_PAL148_B04_0_Pos 10 /*!< LCD PAL148: B04_0 Position */ -#define LCD_PAL148_B04_0_Msk (0x1fUL << LCD_PAL148_B04_0_Pos) /*!< LCD PAL148: B04_0 Mask */ -#define LCD_PAL148_I0_Pos 15 /*!< LCD PAL148: I0 Position */ -#define LCD_PAL148_I0_Msk (0x01UL << LCD_PAL148_I0_Pos) /*!< LCD PAL148: I0 Mask */ -#define LCD_PAL148_R14_0_Pos 16 /*!< LCD PAL148: R14_0 Position */ -#define LCD_PAL148_R14_0_Msk (0x1fUL << LCD_PAL148_R14_0_Pos) /*!< LCD PAL148: R14_0 Mask */ -#define LCD_PAL148_G14_0_Pos 21 /*!< LCD PAL148: G14_0 Position */ -#define LCD_PAL148_G14_0_Msk (0x1fUL << LCD_PAL148_G14_0_Pos) /*!< LCD PAL148: G14_0 Mask */ -#define LCD_PAL148_B14_0_Pos 26 /*!< LCD PAL148: B14_0 Position */ -#define LCD_PAL148_B14_0_Msk (0x1fUL << LCD_PAL148_B14_0_Pos) /*!< LCD PAL148: B14_0 Mask */ -#define LCD_PAL148_I1_Pos 31 /*!< LCD PAL148: I1 Position */ -#define LCD_PAL148_I1_Msk (0x01UL << LCD_PAL148_I1_Pos) /*!< LCD PAL148: I1 Mask */ - -// --------------------------------------- LCD_PAL149 ------------------------------------------- -#define LCD_PAL149_R04_0_Pos 0 /*!< LCD PAL149: R04_0 Position */ -#define LCD_PAL149_R04_0_Msk (0x1fUL << LCD_PAL149_R04_0_Pos) /*!< LCD PAL149: R04_0 Mask */ -#define LCD_PAL149_G04_0_Pos 5 /*!< LCD PAL149: G04_0 Position */ -#define LCD_PAL149_G04_0_Msk (0x1fUL << LCD_PAL149_G04_0_Pos) /*!< LCD PAL149: G04_0 Mask */ -#define LCD_PAL149_B04_0_Pos 10 /*!< LCD PAL149: B04_0 Position */ -#define LCD_PAL149_B04_0_Msk (0x1fUL << LCD_PAL149_B04_0_Pos) /*!< LCD PAL149: B04_0 Mask */ -#define LCD_PAL149_I0_Pos 15 /*!< LCD PAL149: I0 Position */ -#define LCD_PAL149_I0_Msk (0x01UL << LCD_PAL149_I0_Pos) /*!< LCD PAL149: I0 Mask */ -#define LCD_PAL149_R14_0_Pos 16 /*!< LCD PAL149: R14_0 Position */ -#define LCD_PAL149_R14_0_Msk (0x1fUL << LCD_PAL149_R14_0_Pos) /*!< LCD PAL149: R14_0 Mask */ -#define LCD_PAL149_G14_0_Pos 21 /*!< LCD PAL149: G14_0 Position */ -#define LCD_PAL149_G14_0_Msk (0x1fUL << LCD_PAL149_G14_0_Pos) /*!< LCD PAL149: G14_0 Mask */ -#define LCD_PAL149_B14_0_Pos 26 /*!< LCD PAL149: B14_0 Position */ -#define LCD_PAL149_B14_0_Msk (0x1fUL << LCD_PAL149_B14_0_Pos) /*!< LCD PAL149: B14_0 Mask */ -#define LCD_PAL149_I1_Pos 31 /*!< LCD PAL149: I1 Position */ -#define LCD_PAL149_I1_Msk (0x01UL << LCD_PAL149_I1_Pos) /*!< LCD PAL149: I1 Mask */ - -// --------------------------------------- LCD_PAL150 ------------------------------------------- -#define LCD_PAL150_R04_0_Pos 0 /*!< LCD PAL150: R04_0 Position */ -#define LCD_PAL150_R04_0_Msk (0x1fUL << LCD_PAL150_R04_0_Pos) /*!< LCD PAL150: R04_0 Mask */ -#define LCD_PAL150_G04_0_Pos 5 /*!< LCD PAL150: G04_0 Position */ -#define LCD_PAL150_G04_0_Msk (0x1fUL << LCD_PAL150_G04_0_Pos) /*!< LCD PAL150: G04_0 Mask */ -#define LCD_PAL150_B04_0_Pos 10 /*!< LCD PAL150: B04_0 Position */ -#define LCD_PAL150_B04_0_Msk (0x1fUL << LCD_PAL150_B04_0_Pos) /*!< LCD PAL150: B04_0 Mask */ -#define LCD_PAL150_I0_Pos 15 /*!< LCD PAL150: I0 Position */ -#define LCD_PAL150_I0_Msk (0x01UL << LCD_PAL150_I0_Pos) /*!< LCD PAL150: I0 Mask */ -#define LCD_PAL150_R14_0_Pos 16 /*!< LCD PAL150: R14_0 Position */ -#define LCD_PAL150_R14_0_Msk (0x1fUL << LCD_PAL150_R14_0_Pos) /*!< LCD PAL150: R14_0 Mask */ -#define LCD_PAL150_G14_0_Pos 21 /*!< LCD PAL150: G14_0 Position */ -#define LCD_PAL150_G14_0_Msk (0x1fUL << LCD_PAL150_G14_0_Pos) /*!< LCD PAL150: G14_0 Mask */ -#define LCD_PAL150_B14_0_Pos 26 /*!< LCD PAL150: B14_0 Position */ -#define LCD_PAL150_B14_0_Msk (0x1fUL << LCD_PAL150_B14_0_Pos) /*!< LCD PAL150: B14_0 Mask */ -#define LCD_PAL150_I1_Pos 31 /*!< LCD PAL150: I1 Position */ -#define LCD_PAL150_I1_Msk (0x01UL << LCD_PAL150_I1_Pos) /*!< LCD PAL150: I1 Mask */ - -// --------------------------------------- LCD_PAL151 ------------------------------------------- -#define LCD_PAL151_R04_0_Pos 0 /*!< LCD PAL151: R04_0 Position */ -#define LCD_PAL151_R04_0_Msk (0x1fUL << LCD_PAL151_R04_0_Pos) /*!< LCD PAL151: R04_0 Mask */ -#define LCD_PAL151_G04_0_Pos 5 /*!< LCD PAL151: G04_0 Position */ -#define LCD_PAL151_G04_0_Msk (0x1fUL << LCD_PAL151_G04_0_Pos) /*!< LCD PAL151: G04_0 Mask */ -#define LCD_PAL151_B04_0_Pos 10 /*!< LCD PAL151: B04_0 Position */ -#define LCD_PAL151_B04_0_Msk (0x1fUL << LCD_PAL151_B04_0_Pos) /*!< LCD PAL151: B04_0 Mask */ -#define LCD_PAL151_I0_Pos 15 /*!< LCD PAL151: I0 Position */ -#define LCD_PAL151_I0_Msk (0x01UL << LCD_PAL151_I0_Pos) /*!< LCD PAL151: I0 Mask */ -#define LCD_PAL151_R14_0_Pos 16 /*!< LCD PAL151: R14_0 Position */ -#define LCD_PAL151_R14_0_Msk (0x1fUL << LCD_PAL151_R14_0_Pos) /*!< LCD PAL151: R14_0 Mask */ -#define LCD_PAL151_G14_0_Pos 21 /*!< LCD PAL151: G14_0 Position */ -#define LCD_PAL151_G14_0_Msk (0x1fUL << LCD_PAL151_G14_0_Pos) /*!< LCD PAL151: G14_0 Mask */ -#define LCD_PAL151_B14_0_Pos 26 /*!< LCD PAL151: B14_0 Position */ -#define LCD_PAL151_B14_0_Msk (0x1fUL << LCD_PAL151_B14_0_Pos) /*!< LCD PAL151: B14_0 Mask */ -#define LCD_PAL151_I1_Pos 31 /*!< LCD PAL151: I1 Position */ -#define LCD_PAL151_I1_Msk (0x01UL << LCD_PAL151_I1_Pos) /*!< LCD PAL151: I1 Mask */ - -// --------------------------------------- LCD_PAL152 ------------------------------------------- -#define LCD_PAL152_R04_0_Pos 0 /*!< LCD PAL152: R04_0 Position */ -#define LCD_PAL152_R04_0_Msk (0x1fUL << LCD_PAL152_R04_0_Pos) /*!< LCD PAL152: R04_0 Mask */ -#define LCD_PAL152_G04_0_Pos 5 /*!< LCD PAL152: G04_0 Position */ -#define LCD_PAL152_G04_0_Msk (0x1fUL << LCD_PAL152_G04_0_Pos) /*!< LCD PAL152: G04_0 Mask */ -#define LCD_PAL152_B04_0_Pos 10 /*!< LCD PAL152: B04_0 Position */ -#define LCD_PAL152_B04_0_Msk (0x1fUL << LCD_PAL152_B04_0_Pos) /*!< LCD PAL152: B04_0 Mask */ -#define LCD_PAL152_I0_Pos 15 /*!< LCD PAL152: I0 Position */ -#define LCD_PAL152_I0_Msk (0x01UL << LCD_PAL152_I0_Pos) /*!< LCD PAL152: I0 Mask */ -#define LCD_PAL152_R14_0_Pos 16 /*!< LCD PAL152: R14_0 Position */ -#define LCD_PAL152_R14_0_Msk (0x1fUL << LCD_PAL152_R14_0_Pos) /*!< LCD PAL152: R14_0 Mask */ -#define LCD_PAL152_G14_0_Pos 21 /*!< LCD PAL152: G14_0 Position */ -#define LCD_PAL152_G14_0_Msk (0x1fUL << LCD_PAL152_G14_0_Pos) /*!< LCD PAL152: G14_0 Mask */ -#define LCD_PAL152_B14_0_Pos 26 /*!< LCD PAL152: B14_0 Position */ -#define LCD_PAL152_B14_0_Msk (0x1fUL << LCD_PAL152_B14_0_Pos) /*!< LCD PAL152: B14_0 Mask */ -#define LCD_PAL152_I1_Pos 31 /*!< LCD PAL152: I1 Position */ -#define LCD_PAL152_I1_Msk (0x01UL << LCD_PAL152_I1_Pos) /*!< LCD PAL152: I1 Mask */ - -// --------------------------------------- LCD_PAL153 ------------------------------------------- -#define LCD_PAL153_R04_0_Pos 0 /*!< LCD PAL153: R04_0 Position */ -#define LCD_PAL153_R04_0_Msk (0x1fUL << LCD_PAL153_R04_0_Pos) /*!< LCD PAL153: R04_0 Mask */ -#define LCD_PAL153_G04_0_Pos 5 /*!< LCD PAL153: G04_0 Position */ -#define LCD_PAL153_G04_0_Msk (0x1fUL << LCD_PAL153_G04_0_Pos) /*!< LCD PAL153: G04_0 Mask */ -#define LCD_PAL153_B04_0_Pos 10 /*!< LCD PAL153: B04_0 Position */ -#define LCD_PAL153_B04_0_Msk (0x1fUL << LCD_PAL153_B04_0_Pos) /*!< LCD PAL153: B04_0 Mask */ -#define LCD_PAL153_I0_Pos 15 /*!< LCD PAL153: I0 Position */ -#define LCD_PAL153_I0_Msk (0x01UL << LCD_PAL153_I0_Pos) /*!< LCD PAL153: I0 Mask */ -#define LCD_PAL153_R14_0_Pos 16 /*!< LCD PAL153: R14_0 Position */ -#define LCD_PAL153_R14_0_Msk (0x1fUL << LCD_PAL153_R14_0_Pos) /*!< LCD PAL153: R14_0 Mask */ -#define LCD_PAL153_G14_0_Pos 21 /*!< LCD PAL153: G14_0 Position */ -#define LCD_PAL153_G14_0_Msk (0x1fUL << LCD_PAL153_G14_0_Pos) /*!< LCD PAL153: G14_0 Mask */ -#define LCD_PAL153_B14_0_Pos 26 /*!< LCD PAL153: B14_0 Position */ -#define LCD_PAL153_B14_0_Msk (0x1fUL << LCD_PAL153_B14_0_Pos) /*!< LCD PAL153: B14_0 Mask */ -#define LCD_PAL153_I1_Pos 31 /*!< LCD PAL153: I1 Position */ -#define LCD_PAL153_I1_Msk (0x01UL << LCD_PAL153_I1_Pos) /*!< LCD PAL153: I1 Mask */ - -// --------------------------------------- LCD_PAL154 ------------------------------------------- -#define LCD_PAL154_R04_0_Pos 0 /*!< LCD PAL154: R04_0 Position */ -#define LCD_PAL154_R04_0_Msk (0x1fUL << LCD_PAL154_R04_0_Pos) /*!< LCD PAL154: R04_0 Mask */ -#define LCD_PAL154_G04_0_Pos 5 /*!< LCD PAL154: G04_0 Position */ -#define LCD_PAL154_G04_0_Msk (0x1fUL << LCD_PAL154_G04_0_Pos) /*!< LCD PAL154: G04_0 Mask */ -#define LCD_PAL154_B04_0_Pos 10 /*!< LCD PAL154: B04_0 Position */ -#define LCD_PAL154_B04_0_Msk (0x1fUL << LCD_PAL154_B04_0_Pos) /*!< LCD PAL154: B04_0 Mask */ -#define LCD_PAL154_I0_Pos 15 /*!< LCD PAL154: I0 Position */ -#define LCD_PAL154_I0_Msk (0x01UL << LCD_PAL154_I0_Pos) /*!< LCD PAL154: I0 Mask */ -#define LCD_PAL154_R14_0_Pos 16 /*!< LCD PAL154: R14_0 Position */ -#define LCD_PAL154_R14_0_Msk (0x1fUL << LCD_PAL154_R14_0_Pos) /*!< LCD PAL154: R14_0 Mask */ -#define LCD_PAL154_G14_0_Pos 21 /*!< LCD PAL154: G14_0 Position */ -#define LCD_PAL154_G14_0_Msk (0x1fUL << LCD_PAL154_G14_0_Pos) /*!< LCD PAL154: G14_0 Mask */ -#define LCD_PAL154_B14_0_Pos 26 /*!< LCD PAL154: B14_0 Position */ -#define LCD_PAL154_B14_0_Msk (0x1fUL << LCD_PAL154_B14_0_Pos) /*!< LCD PAL154: B14_0 Mask */ -#define LCD_PAL154_I1_Pos 31 /*!< LCD PAL154: I1 Position */ -#define LCD_PAL154_I1_Msk (0x01UL << LCD_PAL154_I1_Pos) /*!< LCD PAL154: I1 Mask */ - -// --------------------------------------- LCD_PAL155 ------------------------------------------- -#define LCD_PAL155_R04_0_Pos 0 /*!< LCD PAL155: R04_0 Position */ -#define LCD_PAL155_R04_0_Msk (0x1fUL << LCD_PAL155_R04_0_Pos) /*!< LCD PAL155: R04_0 Mask */ -#define LCD_PAL155_G04_0_Pos 5 /*!< LCD PAL155: G04_0 Position */ -#define LCD_PAL155_G04_0_Msk (0x1fUL << LCD_PAL155_G04_0_Pos) /*!< LCD PAL155: G04_0 Mask */ -#define LCD_PAL155_B04_0_Pos 10 /*!< LCD PAL155: B04_0 Position */ -#define LCD_PAL155_B04_0_Msk (0x1fUL << LCD_PAL155_B04_0_Pos) /*!< LCD PAL155: B04_0 Mask */ -#define LCD_PAL155_I0_Pos 15 /*!< LCD PAL155: I0 Position */ -#define LCD_PAL155_I0_Msk (0x01UL << LCD_PAL155_I0_Pos) /*!< LCD PAL155: I0 Mask */ -#define LCD_PAL155_R14_0_Pos 16 /*!< LCD PAL155: R14_0 Position */ -#define LCD_PAL155_R14_0_Msk (0x1fUL << LCD_PAL155_R14_0_Pos) /*!< LCD PAL155: R14_0 Mask */ -#define LCD_PAL155_G14_0_Pos 21 /*!< LCD PAL155: G14_0 Position */ -#define LCD_PAL155_G14_0_Msk (0x1fUL << LCD_PAL155_G14_0_Pos) /*!< LCD PAL155: G14_0 Mask */ -#define LCD_PAL155_B14_0_Pos 26 /*!< LCD PAL155: B14_0 Position */ -#define LCD_PAL155_B14_0_Msk (0x1fUL << LCD_PAL155_B14_0_Pos) /*!< LCD PAL155: B14_0 Mask */ -#define LCD_PAL155_I1_Pos 31 /*!< LCD PAL155: I1 Position */ -#define LCD_PAL155_I1_Msk (0x01UL << LCD_PAL155_I1_Pos) /*!< LCD PAL155: I1 Mask */ - -// --------------------------------------- LCD_PAL156 ------------------------------------------- -#define LCD_PAL156_R04_0_Pos 0 /*!< LCD PAL156: R04_0 Position */ -#define LCD_PAL156_R04_0_Msk (0x1fUL << LCD_PAL156_R04_0_Pos) /*!< LCD PAL156: R04_0 Mask */ -#define LCD_PAL156_G04_0_Pos 5 /*!< LCD PAL156: G04_0 Position */ -#define LCD_PAL156_G04_0_Msk (0x1fUL << LCD_PAL156_G04_0_Pos) /*!< LCD PAL156: G04_0 Mask */ -#define LCD_PAL156_B04_0_Pos 10 /*!< LCD PAL156: B04_0 Position */ -#define LCD_PAL156_B04_0_Msk (0x1fUL << LCD_PAL156_B04_0_Pos) /*!< LCD PAL156: B04_0 Mask */ -#define LCD_PAL156_I0_Pos 15 /*!< LCD PAL156: I0 Position */ -#define LCD_PAL156_I0_Msk (0x01UL << LCD_PAL156_I0_Pos) /*!< LCD PAL156: I0 Mask */ -#define LCD_PAL156_R14_0_Pos 16 /*!< LCD PAL156: R14_0 Position */ -#define LCD_PAL156_R14_0_Msk (0x1fUL << LCD_PAL156_R14_0_Pos) /*!< LCD PAL156: R14_0 Mask */ -#define LCD_PAL156_G14_0_Pos 21 /*!< LCD PAL156: G14_0 Position */ -#define LCD_PAL156_G14_0_Msk (0x1fUL << LCD_PAL156_G14_0_Pos) /*!< LCD PAL156: G14_0 Mask */ -#define LCD_PAL156_B14_0_Pos 26 /*!< LCD PAL156: B14_0 Position */ -#define LCD_PAL156_B14_0_Msk (0x1fUL << LCD_PAL156_B14_0_Pos) /*!< LCD PAL156: B14_0 Mask */ -#define LCD_PAL156_I1_Pos 31 /*!< LCD PAL156: I1 Position */ -#define LCD_PAL156_I1_Msk (0x01UL << LCD_PAL156_I1_Pos) /*!< LCD PAL156: I1 Mask */ - -// --------------------------------------- LCD_PAL157 ------------------------------------------- -#define LCD_PAL157_R04_0_Pos 0 /*!< LCD PAL157: R04_0 Position */ -#define LCD_PAL157_R04_0_Msk (0x1fUL << LCD_PAL157_R04_0_Pos) /*!< LCD PAL157: R04_0 Mask */ -#define LCD_PAL157_G04_0_Pos 5 /*!< LCD PAL157: G04_0 Position */ -#define LCD_PAL157_G04_0_Msk (0x1fUL << LCD_PAL157_G04_0_Pos) /*!< LCD PAL157: G04_0 Mask */ -#define LCD_PAL157_B04_0_Pos 10 /*!< LCD PAL157: B04_0 Position */ -#define LCD_PAL157_B04_0_Msk (0x1fUL << LCD_PAL157_B04_0_Pos) /*!< LCD PAL157: B04_0 Mask */ -#define LCD_PAL157_I0_Pos 15 /*!< LCD PAL157: I0 Position */ -#define LCD_PAL157_I0_Msk (0x01UL << LCD_PAL157_I0_Pos) /*!< LCD PAL157: I0 Mask */ -#define LCD_PAL157_R14_0_Pos 16 /*!< LCD PAL157: R14_0 Position */ -#define LCD_PAL157_R14_0_Msk (0x1fUL << LCD_PAL157_R14_0_Pos) /*!< LCD PAL157: R14_0 Mask */ -#define LCD_PAL157_G14_0_Pos 21 /*!< LCD PAL157: G14_0 Position */ -#define LCD_PAL157_G14_0_Msk (0x1fUL << LCD_PAL157_G14_0_Pos) /*!< LCD PAL157: G14_0 Mask */ -#define LCD_PAL157_B14_0_Pos 26 /*!< LCD PAL157: B14_0 Position */ -#define LCD_PAL157_B14_0_Msk (0x1fUL << LCD_PAL157_B14_0_Pos) /*!< LCD PAL157: B14_0 Mask */ -#define LCD_PAL157_I1_Pos 31 /*!< LCD PAL157: I1 Position */ -#define LCD_PAL157_I1_Msk (0x01UL << LCD_PAL157_I1_Pos) /*!< LCD PAL157: I1 Mask */ - -// --------------------------------------- LCD_PAL158 ------------------------------------------- -#define LCD_PAL158_R04_0_Pos 0 /*!< LCD PAL158: R04_0 Position */ -#define LCD_PAL158_R04_0_Msk (0x1fUL << LCD_PAL158_R04_0_Pos) /*!< LCD PAL158: R04_0 Mask */ -#define LCD_PAL158_G04_0_Pos 5 /*!< LCD PAL158: G04_0 Position */ -#define LCD_PAL158_G04_0_Msk (0x1fUL << LCD_PAL158_G04_0_Pos) /*!< LCD PAL158: G04_0 Mask */ -#define LCD_PAL158_B04_0_Pos 10 /*!< LCD PAL158: B04_0 Position */ -#define LCD_PAL158_B04_0_Msk (0x1fUL << LCD_PAL158_B04_0_Pos) /*!< LCD PAL158: B04_0 Mask */ -#define LCD_PAL158_I0_Pos 15 /*!< LCD PAL158: I0 Position */ -#define LCD_PAL158_I0_Msk (0x01UL << LCD_PAL158_I0_Pos) /*!< LCD PAL158: I0 Mask */ -#define LCD_PAL158_R14_0_Pos 16 /*!< LCD PAL158: R14_0 Position */ -#define LCD_PAL158_R14_0_Msk (0x1fUL << LCD_PAL158_R14_0_Pos) /*!< LCD PAL158: R14_0 Mask */ -#define LCD_PAL158_G14_0_Pos 21 /*!< LCD PAL158: G14_0 Position */ -#define LCD_PAL158_G14_0_Msk (0x1fUL << LCD_PAL158_G14_0_Pos) /*!< LCD PAL158: G14_0 Mask */ -#define LCD_PAL158_B14_0_Pos 26 /*!< LCD PAL158: B14_0 Position */ -#define LCD_PAL158_B14_0_Msk (0x1fUL << LCD_PAL158_B14_0_Pos) /*!< LCD PAL158: B14_0 Mask */ -#define LCD_PAL158_I1_Pos 31 /*!< LCD PAL158: I1 Position */ -#define LCD_PAL158_I1_Msk (0x01UL << LCD_PAL158_I1_Pos) /*!< LCD PAL158: I1 Mask */ - -// --------------------------------------- LCD_PAL159 ------------------------------------------- -#define LCD_PAL159_R04_0_Pos 0 /*!< LCD PAL159: R04_0 Position */ -#define LCD_PAL159_R04_0_Msk (0x1fUL << LCD_PAL159_R04_0_Pos) /*!< LCD PAL159: R04_0 Mask */ -#define LCD_PAL159_G04_0_Pos 5 /*!< LCD PAL159: G04_0 Position */ -#define LCD_PAL159_G04_0_Msk (0x1fUL << LCD_PAL159_G04_0_Pos) /*!< LCD PAL159: G04_0 Mask */ -#define LCD_PAL159_B04_0_Pos 10 /*!< LCD PAL159: B04_0 Position */ -#define LCD_PAL159_B04_0_Msk (0x1fUL << LCD_PAL159_B04_0_Pos) /*!< LCD PAL159: B04_0 Mask */ -#define LCD_PAL159_I0_Pos 15 /*!< LCD PAL159: I0 Position */ -#define LCD_PAL159_I0_Msk (0x01UL << LCD_PAL159_I0_Pos) /*!< LCD PAL159: I0 Mask */ -#define LCD_PAL159_R14_0_Pos 16 /*!< LCD PAL159: R14_0 Position */ -#define LCD_PAL159_R14_0_Msk (0x1fUL << LCD_PAL159_R14_0_Pos) /*!< LCD PAL159: R14_0 Mask */ -#define LCD_PAL159_G14_0_Pos 21 /*!< LCD PAL159: G14_0 Position */ -#define LCD_PAL159_G14_0_Msk (0x1fUL << LCD_PAL159_G14_0_Pos) /*!< LCD PAL159: G14_0 Mask */ -#define LCD_PAL159_B14_0_Pos 26 /*!< LCD PAL159: B14_0 Position */ -#define LCD_PAL159_B14_0_Msk (0x1fUL << LCD_PAL159_B14_0_Pos) /*!< LCD PAL159: B14_0 Mask */ -#define LCD_PAL159_I1_Pos 31 /*!< LCD PAL159: I1 Position */ -#define LCD_PAL159_I1_Msk (0x01UL << LCD_PAL159_I1_Pos) /*!< LCD PAL159: I1 Mask */ - -// --------------------------------------- LCD_PAL160 ------------------------------------------- -#define LCD_PAL160_R04_0_Pos 0 /*!< LCD PAL160: R04_0 Position */ -#define LCD_PAL160_R04_0_Msk (0x1fUL << LCD_PAL160_R04_0_Pos) /*!< LCD PAL160: R04_0 Mask */ -#define LCD_PAL160_G04_0_Pos 5 /*!< LCD PAL160: G04_0 Position */ -#define LCD_PAL160_G04_0_Msk (0x1fUL << LCD_PAL160_G04_0_Pos) /*!< LCD PAL160: G04_0 Mask */ -#define LCD_PAL160_B04_0_Pos 10 /*!< LCD PAL160: B04_0 Position */ -#define LCD_PAL160_B04_0_Msk (0x1fUL << LCD_PAL160_B04_0_Pos) /*!< LCD PAL160: B04_0 Mask */ -#define LCD_PAL160_I0_Pos 15 /*!< LCD PAL160: I0 Position */ -#define LCD_PAL160_I0_Msk (0x01UL << LCD_PAL160_I0_Pos) /*!< LCD PAL160: I0 Mask */ -#define LCD_PAL160_R14_0_Pos 16 /*!< LCD PAL160: R14_0 Position */ -#define LCD_PAL160_R14_0_Msk (0x1fUL << LCD_PAL160_R14_0_Pos) /*!< LCD PAL160: R14_0 Mask */ -#define LCD_PAL160_G14_0_Pos 21 /*!< LCD PAL160: G14_0 Position */ -#define LCD_PAL160_G14_0_Msk (0x1fUL << LCD_PAL160_G14_0_Pos) /*!< LCD PAL160: G14_0 Mask */ -#define LCD_PAL160_B14_0_Pos 26 /*!< LCD PAL160: B14_0 Position */ -#define LCD_PAL160_B14_0_Msk (0x1fUL << LCD_PAL160_B14_0_Pos) /*!< LCD PAL160: B14_0 Mask */ -#define LCD_PAL160_I1_Pos 31 /*!< LCD PAL160: I1 Position */ -#define LCD_PAL160_I1_Msk (0x01UL << LCD_PAL160_I1_Pos) /*!< LCD PAL160: I1 Mask */ - -// --------------------------------------- LCD_PAL161 ------------------------------------------- -#define LCD_PAL161_R04_0_Pos 0 /*!< LCD PAL161: R04_0 Position */ -#define LCD_PAL161_R04_0_Msk (0x1fUL << LCD_PAL161_R04_0_Pos) /*!< LCD PAL161: R04_0 Mask */ -#define LCD_PAL161_G04_0_Pos 5 /*!< LCD PAL161: G04_0 Position */ -#define LCD_PAL161_G04_0_Msk (0x1fUL << LCD_PAL161_G04_0_Pos) /*!< LCD PAL161: G04_0 Mask */ -#define LCD_PAL161_B04_0_Pos 10 /*!< LCD PAL161: B04_0 Position */ -#define LCD_PAL161_B04_0_Msk (0x1fUL << LCD_PAL161_B04_0_Pos) /*!< LCD PAL161: B04_0 Mask */ -#define LCD_PAL161_I0_Pos 15 /*!< LCD PAL161: I0 Position */ -#define LCD_PAL161_I0_Msk (0x01UL << LCD_PAL161_I0_Pos) /*!< LCD PAL161: I0 Mask */ -#define LCD_PAL161_R14_0_Pos 16 /*!< LCD PAL161: R14_0 Position */ -#define LCD_PAL161_R14_0_Msk (0x1fUL << LCD_PAL161_R14_0_Pos) /*!< LCD PAL161: R14_0 Mask */ -#define LCD_PAL161_G14_0_Pos 21 /*!< LCD PAL161: G14_0 Position */ -#define LCD_PAL161_G14_0_Msk (0x1fUL << LCD_PAL161_G14_0_Pos) /*!< LCD PAL161: G14_0 Mask */ -#define LCD_PAL161_B14_0_Pos 26 /*!< LCD PAL161: B14_0 Position */ -#define LCD_PAL161_B14_0_Msk (0x1fUL << LCD_PAL161_B14_0_Pos) /*!< LCD PAL161: B14_0 Mask */ -#define LCD_PAL161_I1_Pos 31 /*!< LCD PAL161: I1 Position */ -#define LCD_PAL161_I1_Msk (0x01UL << LCD_PAL161_I1_Pos) /*!< LCD PAL161: I1 Mask */ - -// --------------------------------------- LCD_PAL162 ------------------------------------------- -#define LCD_PAL162_R04_0_Pos 0 /*!< LCD PAL162: R04_0 Position */ -#define LCD_PAL162_R04_0_Msk (0x1fUL << LCD_PAL162_R04_0_Pos) /*!< LCD PAL162: R04_0 Mask */ -#define LCD_PAL162_G04_0_Pos 5 /*!< LCD PAL162: G04_0 Position */ -#define LCD_PAL162_G04_0_Msk (0x1fUL << LCD_PAL162_G04_0_Pos) /*!< LCD PAL162: G04_0 Mask */ -#define LCD_PAL162_B04_0_Pos 10 /*!< LCD PAL162: B04_0 Position */ -#define LCD_PAL162_B04_0_Msk (0x1fUL << LCD_PAL162_B04_0_Pos) /*!< LCD PAL162: B04_0 Mask */ -#define LCD_PAL162_I0_Pos 15 /*!< LCD PAL162: I0 Position */ -#define LCD_PAL162_I0_Msk (0x01UL << LCD_PAL162_I0_Pos) /*!< LCD PAL162: I0 Mask */ -#define LCD_PAL162_R14_0_Pos 16 /*!< LCD PAL162: R14_0 Position */ -#define LCD_PAL162_R14_0_Msk (0x1fUL << LCD_PAL162_R14_0_Pos) /*!< LCD PAL162: R14_0 Mask */ -#define LCD_PAL162_G14_0_Pos 21 /*!< LCD PAL162: G14_0 Position */ -#define LCD_PAL162_G14_0_Msk (0x1fUL << LCD_PAL162_G14_0_Pos) /*!< LCD PAL162: G14_0 Mask */ -#define LCD_PAL162_B14_0_Pos 26 /*!< LCD PAL162: B14_0 Position */ -#define LCD_PAL162_B14_0_Msk (0x1fUL << LCD_PAL162_B14_0_Pos) /*!< LCD PAL162: B14_0 Mask */ -#define LCD_PAL162_I1_Pos 31 /*!< LCD PAL162: I1 Position */ -#define LCD_PAL162_I1_Msk (0x01UL << LCD_PAL162_I1_Pos) /*!< LCD PAL162: I1 Mask */ - -// --------------------------------------- LCD_PAL163 ------------------------------------------- -#define LCD_PAL163_R04_0_Pos 0 /*!< LCD PAL163: R04_0 Position */ -#define LCD_PAL163_R04_0_Msk (0x1fUL << LCD_PAL163_R04_0_Pos) /*!< LCD PAL163: R04_0 Mask */ -#define LCD_PAL163_G04_0_Pos 5 /*!< LCD PAL163: G04_0 Position */ -#define LCD_PAL163_G04_0_Msk (0x1fUL << LCD_PAL163_G04_0_Pos) /*!< LCD PAL163: G04_0 Mask */ -#define LCD_PAL163_B04_0_Pos 10 /*!< LCD PAL163: B04_0 Position */ -#define LCD_PAL163_B04_0_Msk (0x1fUL << LCD_PAL163_B04_0_Pos) /*!< LCD PAL163: B04_0 Mask */ -#define LCD_PAL163_I0_Pos 15 /*!< LCD PAL163: I0 Position */ -#define LCD_PAL163_I0_Msk (0x01UL << LCD_PAL163_I0_Pos) /*!< LCD PAL163: I0 Mask */ -#define LCD_PAL163_R14_0_Pos 16 /*!< LCD PAL163: R14_0 Position */ -#define LCD_PAL163_R14_0_Msk (0x1fUL << LCD_PAL163_R14_0_Pos) /*!< LCD PAL163: R14_0 Mask */ -#define LCD_PAL163_G14_0_Pos 21 /*!< LCD PAL163: G14_0 Position */ -#define LCD_PAL163_G14_0_Msk (0x1fUL << LCD_PAL163_G14_0_Pos) /*!< LCD PAL163: G14_0 Mask */ -#define LCD_PAL163_B14_0_Pos 26 /*!< LCD PAL163: B14_0 Position */ -#define LCD_PAL163_B14_0_Msk (0x1fUL << LCD_PAL163_B14_0_Pos) /*!< LCD PAL163: B14_0 Mask */ -#define LCD_PAL163_I1_Pos 31 /*!< LCD PAL163: I1 Position */ -#define LCD_PAL163_I1_Msk (0x01UL << LCD_PAL163_I1_Pos) /*!< LCD PAL163: I1 Mask */ - -// --------------------------------------- LCD_PAL164 ------------------------------------------- -#define LCD_PAL164_R04_0_Pos 0 /*!< LCD PAL164: R04_0 Position */ -#define LCD_PAL164_R04_0_Msk (0x1fUL << LCD_PAL164_R04_0_Pos) /*!< LCD PAL164: R04_0 Mask */ -#define LCD_PAL164_G04_0_Pos 5 /*!< LCD PAL164: G04_0 Position */ -#define LCD_PAL164_G04_0_Msk (0x1fUL << LCD_PAL164_G04_0_Pos) /*!< LCD PAL164: G04_0 Mask */ -#define LCD_PAL164_B04_0_Pos 10 /*!< LCD PAL164: B04_0 Position */ -#define LCD_PAL164_B04_0_Msk (0x1fUL << LCD_PAL164_B04_0_Pos) /*!< LCD PAL164: B04_0 Mask */ -#define LCD_PAL164_I0_Pos 15 /*!< LCD PAL164: I0 Position */ -#define LCD_PAL164_I0_Msk (0x01UL << LCD_PAL164_I0_Pos) /*!< LCD PAL164: I0 Mask */ -#define LCD_PAL164_R14_0_Pos 16 /*!< LCD PAL164: R14_0 Position */ -#define LCD_PAL164_R14_0_Msk (0x1fUL << LCD_PAL164_R14_0_Pos) /*!< LCD PAL164: R14_0 Mask */ -#define LCD_PAL164_G14_0_Pos 21 /*!< LCD PAL164: G14_0 Position */ -#define LCD_PAL164_G14_0_Msk (0x1fUL << LCD_PAL164_G14_0_Pos) /*!< LCD PAL164: G14_0 Mask */ -#define LCD_PAL164_B14_0_Pos 26 /*!< LCD PAL164: B14_0 Position */ -#define LCD_PAL164_B14_0_Msk (0x1fUL << LCD_PAL164_B14_0_Pos) /*!< LCD PAL164: B14_0 Mask */ -#define LCD_PAL164_I1_Pos 31 /*!< LCD PAL164: I1 Position */ -#define LCD_PAL164_I1_Msk (0x01UL << LCD_PAL164_I1_Pos) /*!< LCD PAL164: I1 Mask */ - -// --------------------------------------- LCD_PAL165 ------------------------------------------- -#define LCD_PAL165_R04_0_Pos 0 /*!< LCD PAL165: R04_0 Position */ -#define LCD_PAL165_R04_0_Msk (0x1fUL << LCD_PAL165_R04_0_Pos) /*!< LCD PAL165: R04_0 Mask */ -#define LCD_PAL165_G04_0_Pos 5 /*!< LCD PAL165: G04_0 Position */ -#define LCD_PAL165_G04_0_Msk (0x1fUL << LCD_PAL165_G04_0_Pos) /*!< LCD PAL165: G04_0 Mask */ -#define LCD_PAL165_B04_0_Pos 10 /*!< LCD PAL165: B04_0 Position */ -#define LCD_PAL165_B04_0_Msk (0x1fUL << LCD_PAL165_B04_0_Pos) /*!< LCD PAL165: B04_0 Mask */ -#define LCD_PAL165_I0_Pos 15 /*!< LCD PAL165: I0 Position */ -#define LCD_PAL165_I0_Msk (0x01UL << LCD_PAL165_I0_Pos) /*!< LCD PAL165: I0 Mask */ -#define LCD_PAL165_R14_0_Pos 16 /*!< LCD PAL165: R14_0 Position */ -#define LCD_PAL165_R14_0_Msk (0x1fUL << LCD_PAL165_R14_0_Pos) /*!< LCD PAL165: R14_0 Mask */ -#define LCD_PAL165_G14_0_Pos 21 /*!< LCD PAL165: G14_0 Position */ -#define LCD_PAL165_G14_0_Msk (0x1fUL << LCD_PAL165_G14_0_Pos) /*!< LCD PAL165: G14_0 Mask */ -#define LCD_PAL165_B14_0_Pos 26 /*!< LCD PAL165: B14_0 Position */ -#define LCD_PAL165_B14_0_Msk (0x1fUL << LCD_PAL165_B14_0_Pos) /*!< LCD PAL165: B14_0 Mask */ -#define LCD_PAL165_I1_Pos 31 /*!< LCD PAL165: I1 Position */ -#define LCD_PAL165_I1_Msk (0x01UL << LCD_PAL165_I1_Pos) /*!< LCD PAL165: I1 Mask */ - -// --------------------------------------- LCD_PAL166 ------------------------------------------- -#define LCD_PAL166_R04_0_Pos 0 /*!< LCD PAL166: R04_0 Position */ -#define LCD_PAL166_R04_0_Msk (0x1fUL << LCD_PAL166_R04_0_Pos) /*!< LCD PAL166: R04_0 Mask */ -#define LCD_PAL166_G04_0_Pos 5 /*!< LCD PAL166: G04_0 Position */ -#define LCD_PAL166_G04_0_Msk (0x1fUL << LCD_PAL166_G04_0_Pos) /*!< LCD PAL166: G04_0 Mask */ -#define LCD_PAL166_B04_0_Pos 10 /*!< LCD PAL166: B04_0 Position */ -#define LCD_PAL166_B04_0_Msk (0x1fUL << LCD_PAL166_B04_0_Pos) /*!< LCD PAL166: B04_0 Mask */ -#define LCD_PAL166_I0_Pos 15 /*!< LCD PAL166: I0 Position */ -#define LCD_PAL166_I0_Msk (0x01UL << LCD_PAL166_I0_Pos) /*!< LCD PAL166: I0 Mask */ -#define LCD_PAL166_R14_0_Pos 16 /*!< LCD PAL166: R14_0 Position */ -#define LCD_PAL166_R14_0_Msk (0x1fUL << LCD_PAL166_R14_0_Pos) /*!< LCD PAL166: R14_0 Mask */ -#define LCD_PAL166_G14_0_Pos 21 /*!< LCD PAL166: G14_0 Position */ -#define LCD_PAL166_G14_0_Msk (0x1fUL << LCD_PAL166_G14_0_Pos) /*!< LCD PAL166: G14_0 Mask */ -#define LCD_PAL166_B14_0_Pos 26 /*!< LCD PAL166: B14_0 Position */ -#define LCD_PAL166_B14_0_Msk (0x1fUL << LCD_PAL166_B14_0_Pos) /*!< LCD PAL166: B14_0 Mask */ -#define LCD_PAL166_I1_Pos 31 /*!< LCD PAL166: I1 Position */ -#define LCD_PAL166_I1_Msk (0x01UL << LCD_PAL166_I1_Pos) /*!< LCD PAL166: I1 Mask */ - -// --------------------------------------- LCD_PAL167 ------------------------------------------- -#define LCD_PAL167_R04_0_Pos 0 /*!< LCD PAL167: R04_0 Position */ -#define LCD_PAL167_R04_0_Msk (0x1fUL << LCD_PAL167_R04_0_Pos) /*!< LCD PAL167: R04_0 Mask */ -#define LCD_PAL167_G04_0_Pos 5 /*!< LCD PAL167: G04_0 Position */ -#define LCD_PAL167_G04_0_Msk (0x1fUL << LCD_PAL167_G04_0_Pos) /*!< LCD PAL167: G04_0 Mask */ -#define LCD_PAL167_B04_0_Pos 10 /*!< LCD PAL167: B04_0 Position */ -#define LCD_PAL167_B04_0_Msk (0x1fUL << LCD_PAL167_B04_0_Pos) /*!< LCD PAL167: B04_0 Mask */ -#define LCD_PAL167_I0_Pos 15 /*!< LCD PAL167: I0 Position */ -#define LCD_PAL167_I0_Msk (0x01UL << LCD_PAL167_I0_Pos) /*!< LCD PAL167: I0 Mask */ -#define LCD_PAL167_R14_0_Pos 16 /*!< LCD PAL167: R14_0 Position */ -#define LCD_PAL167_R14_0_Msk (0x1fUL << LCD_PAL167_R14_0_Pos) /*!< LCD PAL167: R14_0 Mask */ -#define LCD_PAL167_G14_0_Pos 21 /*!< LCD PAL167: G14_0 Position */ -#define LCD_PAL167_G14_0_Msk (0x1fUL << LCD_PAL167_G14_0_Pos) /*!< LCD PAL167: G14_0 Mask */ -#define LCD_PAL167_B14_0_Pos 26 /*!< LCD PAL167: B14_0 Position */ -#define LCD_PAL167_B14_0_Msk (0x1fUL << LCD_PAL167_B14_0_Pos) /*!< LCD PAL167: B14_0 Mask */ -#define LCD_PAL167_I1_Pos 31 /*!< LCD PAL167: I1 Position */ -#define LCD_PAL167_I1_Msk (0x01UL << LCD_PAL167_I1_Pos) /*!< LCD PAL167: I1 Mask */ - -// --------------------------------------- LCD_PAL168 ------------------------------------------- -#define LCD_PAL168_R04_0_Pos 0 /*!< LCD PAL168: R04_0 Position */ -#define LCD_PAL168_R04_0_Msk (0x1fUL << LCD_PAL168_R04_0_Pos) /*!< LCD PAL168: R04_0 Mask */ -#define LCD_PAL168_G04_0_Pos 5 /*!< LCD PAL168: G04_0 Position */ -#define LCD_PAL168_G04_0_Msk (0x1fUL << LCD_PAL168_G04_0_Pos) /*!< LCD PAL168: G04_0 Mask */ -#define LCD_PAL168_B04_0_Pos 10 /*!< LCD PAL168: B04_0 Position */ -#define LCD_PAL168_B04_0_Msk (0x1fUL << LCD_PAL168_B04_0_Pos) /*!< LCD PAL168: B04_0 Mask */ -#define LCD_PAL168_I0_Pos 15 /*!< LCD PAL168: I0 Position */ -#define LCD_PAL168_I0_Msk (0x01UL << LCD_PAL168_I0_Pos) /*!< LCD PAL168: I0 Mask */ -#define LCD_PAL168_R14_0_Pos 16 /*!< LCD PAL168: R14_0 Position */ -#define LCD_PAL168_R14_0_Msk (0x1fUL << LCD_PAL168_R14_0_Pos) /*!< LCD PAL168: R14_0 Mask */ -#define LCD_PAL168_G14_0_Pos 21 /*!< LCD PAL168: G14_0 Position */ -#define LCD_PAL168_G14_0_Msk (0x1fUL << LCD_PAL168_G14_0_Pos) /*!< LCD PAL168: G14_0 Mask */ -#define LCD_PAL168_B14_0_Pos 26 /*!< LCD PAL168: B14_0 Position */ -#define LCD_PAL168_B14_0_Msk (0x1fUL << LCD_PAL168_B14_0_Pos) /*!< LCD PAL168: B14_0 Mask */ -#define LCD_PAL168_I1_Pos 31 /*!< LCD PAL168: I1 Position */ -#define LCD_PAL168_I1_Msk (0x01UL << LCD_PAL168_I1_Pos) /*!< LCD PAL168: I1 Mask */ - -// --------------------------------------- LCD_PAL169 ------------------------------------------- -#define LCD_PAL169_R04_0_Pos 0 /*!< LCD PAL169: R04_0 Position */ -#define LCD_PAL169_R04_0_Msk (0x1fUL << LCD_PAL169_R04_0_Pos) /*!< LCD PAL169: R04_0 Mask */ -#define LCD_PAL169_G04_0_Pos 5 /*!< LCD PAL169: G04_0 Position */ -#define LCD_PAL169_G04_0_Msk (0x1fUL << LCD_PAL169_G04_0_Pos) /*!< LCD PAL169: G04_0 Mask */ -#define LCD_PAL169_B04_0_Pos 10 /*!< LCD PAL169: B04_0 Position */ -#define LCD_PAL169_B04_0_Msk (0x1fUL << LCD_PAL169_B04_0_Pos) /*!< LCD PAL169: B04_0 Mask */ -#define LCD_PAL169_I0_Pos 15 /*!< LCD PAL169: I0 Position */ -#define LCD_PAL169_I0_Msk (0x01UL << LCD_PAL169_I0_Pos) /*!< LCD PAL169: I0 Mask */ -#define LCD_PAL169_R14_0_Pos 16 /*!< LCD PAL169: R14_0 Position */ -#define LCD_PAL169_R14_0_Msk (0x1fUL << LCD_PAL169_R14_0_Pos) /*!< LCD PAL169: R14_0 Mask */ -#define LCD_PAL169_G14_0_Pos 21 /*!< LCD PAL169: G14_0 Position */ -#define LCD_PAL169_G14_0_Msk (0x1fUL << LCD_PAL169_G14_0_Pos) /*!< LCD PAL169: G14_0 Mask */ -#define LCD_PAL169_B14_0_Pos 26 /*!< LCD PAL169: B14_0 Position */ -#define LCD_PAL169_B14_0_Msk (0x1fUL << LCD_PAL169_B14_0_Pos) /*!< LCD PAL169: B14_0 Mask */ -#define LCD_PAL169_I1_Pos 31 /*!< LCD PAL169: I1 Position */ -#define LCD_PAL169_I1_Msk (0x01UL << LCD_PAL169_I1_Pos) /*!< LCD PAL169: I1 Mask */ - -// --------------------------------------- LCD_PAL170 ------------------------------------------- -#define LCD_PAL170_R04_0_Pos 0 /*!< LCD PAL170: R04_0 Position */ -#define LCD_PAL170_R04_0_Msk (0x1fUL << LCD_PAL170_R04_0_Pos) /*!< LCD PAL170: R04_0 Mask */ -#define LCD_PAL170_G04_0_Pos 5 /*!< LCD PAL170: G04_0 Position */ -#define LCD_PAL170_G04_0_Msk (0x1fUL << LCD_PAL170_G04_0_Pos) /*!< LCD PAL170: G04_0 Mask */ -#define LCD_PAL170_B04_0_Pos 10 /*!< LCD PAL170: B04_0 Position */ -#define LCD_PAL170_B04_0_Msk (0x1fUL << LCD_PAL170_B04_0_Pos) /*!< LCD PAL170: B04_0 Mask */ -#define LCD_PAL170_I0_Pos 15 /*!< LCD PAL170: I0 Position */ -#define LCD_PAL170_I0_Msk (0x01UL << LCD_PAL170_I0_Pos) /*!< LCD PAL170: I0 Mask */ -#define LCD_PAL170_R14_0_Pos 16 /*!< LCD PAL170: R14_0 Position */ -#define LCD_PAL170_R14_0_Msk (0x1fUL << LCD_PAL170_R14_0_Pos) /*!< LCD PAL170: R14_0 Mask */ -#define LCD_PAL170_G14_0_Pos 21 /*!< LCD PAL170: G14_0 Position */ -#define LCD_PAL170_G14_0_Msk (0x1fUL << LCD_PAL170_G14_0_Pos) /*!< LCD PAL170: G14_0 Mask */ -#define LCD_PAL170_B14_0_Pos 26 /*!< LCD PAL170: B14_0 Position */ -#define LCD_PAL170_B14_0_Msk (0x1fUL << LCD_PAL170_B14_0_Pos) /*!< LCD PAL170: B14_0 Mask */ -#define LCD_PAL170_I1_Pos 31 /*!< LCD PAL170: I1 Position */ -#define LCD_PAL170_I1_Msk (0x01UL << LCD_PAL170_I1_Pos) /*!< LCD PAL170: I1 Mask */ - -// --------------------------------------- LCD_PAL171 ------------------------------------------- -#define LCD_PAL171_R04_0_Pos 0 /*!< LCD PAL171: R04_0 Position */ -#define LCD_PAL171_R04_0_Msk (0x1fUL << LCD_PAL171_R04_0_Pos) /*!< LCD PAL171: R04_0 Mask */ -#define LCD_PAL171_G04_0_Pos 5 /*!< LCD PAL171: G04_0 Position */ -#define LCD_PAL171_G04_0_Msk (0x1fUL << LCD_PAL171_G04_0_Pos) /*!< LCD PAL171: G04_0 Mask */ -#define LCD_PAL171_B04_0_Pos 10 /*!< LCD PAL171: B04_0 Position */ -#define LCD_PAL171_B04_0_Msk (0x1fUL << LCD_PAL171_B04_0_Pos) /*!< LCD PAL171: B04_0 Mask */ -#define LCD_PAL171_I0_Pos 15 /*!< LCD PAL171: I0 Position */ -#define LCD_PAL171_I0_Msk (0x01UL << LCD_PAL171_I0_Pos) /*!< LCD PAL171: I0 Mask */ -#define LCD_PAL171_R14_0_Pos 16 /*!< LCD PAL171: R14_0 Position */ -#define LCD_PAL171_R14_0_Msk (0x1fUL << LCD_PAL171_R14_0_Pos) /*!< LCD PAL171: R14_0 Mask */ -#define LCD_PAL171_G14_0_Pos 21 /*!< LCD PAL171: G14_0 Position */ -#define LCD_PAL171_G14_0_Msk (0x1fUL << LCD_PAL171_G14_0_Pos) /*!< LCD PAL171: G14_0 Mask */ -#define LCD_PAL171_B14_0_Pos 26 /*!< LCD PAL171: B14_0 Position */ -#define LCD_PAL171_B14_0_Msk (0x1fUL << LCD_PAL171_B14_0_Pos) /*!< LCD PAL171: B14_0 Mask */ -#define LCD_PAL171_I1_Pos 31 /*!< LCD PAL171: I1 Position */ -#define LCD_PAL171_I1_Msk (0x01UL << LCD_PAL171_I1_Pos) /*!< LCD PAL171: I1 Mask */ - -// --------------------------------------- LCD_PAL172 ------------------------------------------- -#define LCD_PAL172_R04_0_Pos 0 /*!< LCD PAL172: R04_0 Position */ -#define LCD_PAL172_R04_0_Msk (0x1fUL << LCD_PAL172_R04_0_Pos) /*!< LCD PAL172: R04_0 Mask */ -#define LCD_PAL172_G04_0_Pos 5 /*!< LCD PAL172: G04_0 Position */ -#define LCD_PAL172_G04_0_Msk (0x1fUL << LCD_PAL172_G04_0_Pos) /*!< LCD PAL172: G04_0 Mask */ -#define LCD_PAL172_B04_0_Pos 10 /*!< LCD PAL172: B04_0 Position */ -#define LCD_PAL172_B04_0_Msk (0x1fUL << LCD_PAL172_B04_0_Pos) /*!< LCD PAL172: B04_0 Mask */ -#define LCD_PAL172_I0_Pos 15 /*!< LCD PAL172: I0 Position */ -#define LCD_PAL172_I0_Msk (0x01UL << LCD_PAL172_I0_Pos) /*!< LCD PAL172: I0 Mask */ -#define LCD_PAL172_R14_0_Pos 16 /*!< LCD PAL172: R14_0 Position */ -#define LCD_PAL172_R14_0_Msk (0x1fUL << LCD_PAL172_R14_0_Pos) /*!< LCD PAL172: R14_0 Mask */ -#define LCD_PAL172_G14_0_Pos 21 /*!< LCD PAL172: G14_0 Position */ -#define LCD_PAL172_G14_0_Msk (0x1fUL << LCD_PAL172_G14_0_Pos) /*!< LCD PAL172: G14_0 Mask */ -#define LCD_PAL172_B14_0_Pos 26 /*!< LCD PAL172: B14_0 Position */ -#define LCD_PAL172_B14_0_Msk (0x1fUL << LCD_PAL172_B14_0_Pos) /*!< LCD PAL172: B14_0 Mask */ -#define LCD_PAL172_I1_Pos 31 /*!< LCD PAL172: I1 Position */ -#define LCD_PAL172_I1_Msk (0x01UL << LCD_PAL172_I1_Pos) /*!< LCD PAL172: I1 Mask */ - -// --------------------------------------- LCD_PAL173 ------------------------------------------- -#define LCD_PAL173_R04_0_Pos 0 /*!< LCD PAL173: R04_0 Position */ -#define LCD_PAL173_R04_0_Msk (0x1fUL << LCD_PAL173_R04_0_Pos) /*!< LCD PAL173: R04_0 Mask */ -#define LCD_PAL173_G04_0_Pos 5 /*!< LCD PAL173: G04_0 Position */ -#define LCD_PAL173_G04_0_Msk (0x1fUL << LCD_PAL173_G04_0_Pos) /*!< LCD PAL173: G04_0 Mask */ -#define LCD_PAL173_B04_0_Pos 10 /*!< LCD PAL173: B04_0 Position */ -#define LCD_PAL173_B04_0_Msk (0x1fUL << LCD_PAL173_B04_0_Pos) /*!< LCD PAL173: B04_0 Mask */ -#define LCD_PAL173_I0_Pos 15 /*!< LCD PAL173: I0 Position */ -#define LCD_PAL173_I0_Msk (0x01UL << LCD_PAL173_I0_Pos) /*!< LCD PAL173: I0 Mask */ -#define LCD_PAL173_R14_0_Pos 16 /*!< LCD PAL173: R14_0 Position */ -#define LCD_PAL173_R14_0_Msk (0x1fUL << LCD_PAL173_R14_0_Pos) /*!< LCD PAL173: R14_0 Mask */ -#define LCD_PAL173_G14_0_Pos 21 /*!< LCD PAL173: G14_0 Position */ -#define LCD_PAL173_G14_0_Msk (0x1fUL << LCD_PAL173_G14_0_Pos) /*!< LCD PAL173: G14_0 Mask */ -#define LCD_PAL173_B14_0_Pos 26 /*!< LCD PAL173: B14_0 Position */ -#define LCD_PAL173_B14_0_Msk (0x1fUL << LCD_PAL173_B14_0_Pos) /*!< LCD PAL173: B14_0 Mask */ -#define LCD_PAL173_I1_Pos 31 /*!< LCD PAL173: I1 Position */ -#define LCD_PAL173_I1_Msk (0x01UL << LCD_PAL173_I1_Pos) /*!< LCD PAL173: I1 Mask */ - -// --------------------------------------- LCD_PAL174 ------------------------------------------- -#define LCD_PAL174_R04_0_Pos 0 /*!< LCD PAL174: R04_0 Position */ -#define LCD_PAL174_R04_0_Msk (0x1fUL << LCD_PAL174_R04_0_Pos) /*!< LCD PAL174: R04_0 Mask */ -#define LCD_PAL174_G04_0_Pos 5 /*!< LCD PAL174: G04_0 Position */ -#define LCD_PAL174_G04_0_Msk (0x1fUL << LCD_PAL174_G04_0_Pos) /*!< LCD PAL174: G04_0 Mask */ -#define LCD_PAL174_B04_0_Pos 10 /*!< LCD PAL174: B04_0 Position */ -#define LCD_PAL174_B04_0_Msk (0x1fUL << LCD_PAL174_B04_0_Pos) /*!< LCD PAL174: B04_0 Mask */ -#define LCD_PAL174_I0_Pos 15 /*!< LCD PAL174: I0 Position */ -#define LCD_PAL174_I0_Msk (0x01UL << LCD_PAL174_I0_Pos) /*!< LCD PAL174: I0 Mask */ -#define LCD_PAL174_R14_0_Pos 16 /*!< LCD PAL174: R14_0 Position */ -#define LCD_PAL174_R14_0_Msk (0x1fUL << LCD_PAL174_R14_0_Pos) /*!< LCD PAL174: R14_0 Mask */ -#define LCD_PAL174_G14_0_Pos 21 /*!< LCD PAL174: G14_0 Position */ -#define LCD_PAL174_G14_0_Msk (0x1fUL << LCD_PAL174_G14_0_Pos) /*!< LCD PAL174: G14_0 Mask */ -#define LCD_PAL174_B14_0_Pos 26 /*!< LCD PAL174: B14_0 Position */ -#define LCD_PAL174_B14_0_Msk (0x1fUL << LCD_PAL174_B14_0_Pos) /*!< LCD PAL174: B14_0 Mask */ -#define LCD_PAL174_I1_Pos 31 /*!< LCD PAL174: I1 Position */ -#define LCD_PAL174_I1_Msk (0x01UL << LCD_PAL174_I1_Pos) /*!< LCD PAL174: I1 Mask */ - -// --------------------------------------- LCD_PAL175 ------------------------------------------- -#define LCD_PAL175_R04_0_Pos 0 /*!< LCD PAL175: R04_0 Position */ -#define LCD_PAL175_R04_0_Msk (0x1fUL << LCD_PAL175_R04_0_Pos) /*!< LCD PAL175: R04_0 Mask */ -#define LCD_PAL175_G04_0_Pos 5 /*!< LCD PAL175: G04_0 Position */ -#define LCD_PAL175_G04_0_Msk (0x1fUL << LCD_PAL175_G04_0_Pos) /*!< LCD PAL175: G04_0 Mask */ -#define LCD_PAL175_B04_0_Pos 10 /*!< LCD PAL175: B04_0 Position */ -#define LCD_PAL175_B04_0_Msk (0x1fUL << LCD_PAL175_B04_0_Pos) /*!< LCD PAL175: B04_0 Mask */ -#define LCD_PAL175_I0_Pos 15 /*!< LCD PAL175: I0 Position */ -#define LCD_PAL175_I0_Msk (0x01UL << LCD_PAL175_I0_Pos) /*!< LCD PAL175: I0 Mask */ -#define LCD_PAL175_R14_0_Pos 16 /*!< LCD PAL175: R14_0 Position */ -#define LCD_PAL175_R14_0_Msk (0x1fUL << LCD_PAL175_R14_0_Pos) /*!< LCD PAL175: R14_0 Mask */ -#define LCD_PAL175_G14_0_Pos 21 /*!< LCD PAL175: G14_0 Position */ -#define LCD_PAL175_G14_0_Msk (0x1fUL << LCD_PAL175_G14_0_Pos) /*!< LCD PAL175: G14_0 Mask */ -#define LCD_PAL175_B14_0_Pos 26 /*!< LCD PAL175: B14_0 Position */ -#define LCD_PAL175_B14_0_Msk (0x1fUL << LCD_PAL175_B14_0_Pos) /*!< LCD PAL175: B14_0 Mask */ -#define LCD_PAL175_I1_Pos 31 /*!< LCD PAL175: I1 Position */ -#define LCD_PAL175_I1_Msk (0x01UL << LCD_PAL175_I1_Pos) /*!< LCD PAL175: I1 Mask */ - -// --------------------------------------- LCD_PAL176 ------------------------------------------- -#define LCD_PAL176_R04_0_Pos 0 /*!< LCD PAL176: R04_0 Position */ -#define LCD_PAL176_R04_0_Msk (0x1fUL << LCD_PAL176_R04_0_Pos) /*!< LCD PAL176: R04_0 Mask */ -#define LCD_PAL176_G04_0_Pos 5 /*!< LCD PAL176: G04_0 Position */ -#define LCD_PAL176_G04_0_Msk (0x1fUL << LCD_PAL176_G04_0_Pos) /*!< LCD PAL176: G04_0 Mask */ -#define LCD_PAL176_B04_0_Pos 10 /*!< LCD PAL176: B04_0 Position */ -#define LCD_PAL176_B04_0_Msk (0x1fUL << LCD_PAL176_B04_0_Pos) /*!< LCD PAL176: B04_0 Mask */ -#define LCD_PAL176_I0_Pos 15 /*!< LCD PAL176: I0 Position */ -#define LCD_PAL176_I0_Msk (0x01UL << LCD_PAL176_I0_Pos) /*!< LCD PAL176: I0 Mask */ -#define LCD_PAL176_R14_0_Pos 16 /*!< LCD PAL176: R14_0 Position */ -#define LCD_PAL176_R14_0_Msk (0x1fUL << LCD_PAL176_R14_0_Pos) /*!< LCD PAL176: R14_0 Mask */ -#define LCD_PAL176_G14_0_Pos 21 /*!< LCD PAL176: G14_0 Position */ -#define LCD_PAL176_G14_0_Msk (0x1fUL << LCD_PAL176_G14_0_Pos) /*!< LCD PAL176: G14_0 Mask */ -#define LCD_PAL176_B14_0_Pos 26 /*!< LCD PAL176: B14_0 Position */ -#define LCD_PAL176_B14_0_Msk (0x1fUL << LCD_PAL176_B14_0_Pos) /*!< LCD PAL176: B14_0 Mask */ -#define LCD_PAL176_I1_Pos 31 /*!< LCD PAL176: I1 Position */ -#define LCD_PAL176_I1_Msk (0x01UL << LCD_PAL176_I1_Pos) /*!< LCD PAL176: I1 Mask */ - -// --------------------------------------- LCD_PAL177 ------------------------------------------- -#define LCD_PAL177_R04_0_Pos 0 /*!< LCD PAL177: R04_0 Position */ -#define LCD_PAL177_R04_0_Msk (0x1fUL << LCD_PAL177_R04_0_Pos) /*!< LCD PAL177: R04_0 Mask */ -#define LCD_PAL177_G04_0_Pos 5 /*!< LCD PAL177: G04_0 Position */ -#define LCD_PAL177_G04_0_Msk (0x1fUL << LCD_PAL177_G04_0_Pos) /*!< LCD PAL177: G04_0 Mask */ -#define LCD_PAL177_B04_0_Pos 10 /*!< LCD PAL177: B04_0 Position */ -#define LCD_PAL177_B04_0_Msk (0x1fUL << LCD_PAL177_B04_0_Pos) /*!< LCD PAL177: B04_0 Mask */ -#define LCD_PAL177_I0_Pos 15 /*!< LCD PAL177: I0 Position */ -#define LCD_PAL177_I0_Msk (0x01UL << LCD_PAL177_I0_Pos) /*!< LCD PAL177: I0 Mask */ -#define LCD_PAL177_R14_0_Pos 16 /*!< LCD PAL177: R14_0 Position */ -#define LCD_PAL177_R14_0_Msk (0x1fUL << LCD_PAL177_R14_0_Pos) /*!< LCD PAL177: R14_0 Mask */ -#define LCD_PAL177_G14_0_Pos 21 /*!< LCD PAL177: G14_0 Position */ -#define LCD_PAL177_G14_0_Msk (0x1fUL << LCD_PAL177_G14_0_Pos) /*!< LCD PAL177: G14_0 Mask */ -#define LCD_PAL177_B14_0_Pos 26 /*!< LCD PAL177: B14_0 Position */ -#define LCD_PAL177_B14_0_Msk (0x1fUL << LCD_PAL177_B14_0_Pos) /*!< LCD PAL177: B14_0 Mask */ -#define LCD_PAL177_I1_Pos 31 /*!< LCD PAL177: I1 Position */ -#define LCD_PAL177_I1_Msk (0x01UL << LCD_PAL177_I1_Pos) /*!< LCD PAL177: I1 Mask */ - -// --------------------------------------- LCD_PAL178 ------------------------------------------- -#define LCD_PAL178_R04_0_Pos 0 /*!< LCD PAL178: R04_0 Position */ -#define LCD_PAL178_R04_0_Msk (0x1fUL << LCD_PAL178_R04_0_Pos) /*!< LCD PAL178: R04_0 Mask */ -#define LCD_PAL178_G04_0_Pos 5 /*!< LCD PAL178: G04_0 Position */ -#define LCD_PAL178_G04_0_Msk (0x1fUL << LCD_PAL178_G04_0_Pos) /*!< LCD PAL178: G04_0 Mask */ -#define LCD_PAL178_B04_0_Pos 10 /*!< LCD PAL178: B04_0 Position */ -#define LCD_PAL178_B04_0_Msk (0x1fUL << LCD_PAL178_B04_0_Pos) /*!< LCD PAL178: B04_0 Mask */ -#define LCD_PAL178_I0_Pos 15 /*!< LCD PAL178: I0 Position */ -#define LCD_PAL178_I0_Msk (0x01UL << LCD_PAL178_I0_Pos) /*!< LCD PAL178: I0 Mask */ -#define LCD_PAL178_R14_0_Pos 16 /*!< LCD PAL178: R14_0 Position */ -#define LCD_PAL178_R14_0_Msk (0x1fUL << LCD_PAL178_R14_0_Pos) /*!< LCD PAL178: R14_0 Mask */ -#define LCD_PAL178_G14_0_Pos 21 /*!< LCD PAL178: G14_0 Position */ -#define LCD_PAL178_G14_0_Msk (0x1fUL << LCD_PAL178_G14_0_Pos) /*!< LCD PAL178: G14_0 Mask */ -#define LCD_PAL178_B14_0_Pos 26 /*!< LCD PAL178: B14_0 Position */ -#define LCD_PAL178_B14_0_Msk (0x1fUL << LCD_PAL178_B14_0_Pos) /*!< LCD PAL178: B14_0 Mask */ -#define LCD_PAL178_I1_Pos 31 /*!< LCD PAL178: I1 Position */ -#define LCD_PAL178_I1_Msk (0x01UL << LCD_PAL178_I1_Pos) /*!< LCD PAL178: I1 Mask */ - -// --------------------------------------- LCD_PAL179 ------------------------------------------- -#define LCD_PAL179_R04_0_Pos 0 /*!< LCD PAL179: R04_0 Position */ -#define LCD_PAL179_R04_0_Msk (0x1fUL << LCD_PAL179_R04_0_Pos) /*!< LCD PAL179: R04_0 Mask */ -#define LCD_PAL179_G04_0_Pos 5 /*!< LCD PAL179: G04_0 Position */ -#define LCD_PAL179_G04_0_Msk (0x1fUL << LCD_PAL179_G04_0_Pos) /*!< LCD PAL179: G04_0 Mask */ -#define LCD_PAL179_B04_0_Pos 10 /*!< LCD PAL179: B04_0 Position */ -#define LCD_PAL179_B04_0_Msk (0x1fUL << LCD_PAL179_B04_0_Pos) /*!< LCD PAL179: B04_0 Mask */ -#define LCD_PAL179_I0_Pos 15 /*!< LCD PAL179: I0 Position */ -#define LCD_PAL179_I0_Msk (0x01UL << LCD_PAL179_I0_Pos) /*!< LCD PAL179: I0 Mask */ -#define LCD_PAL179_R14_0_Pos 16 /*!< LCD PAL179: R14_0 Position */ -#define LCD_PAL179_R14_0_Msk (0x1fUL << LCD_PAL179_R14_0_Pos) /*!< LCD PAL179: R14_0 Mask */ -#define LCD_PAL179_G14_0_Pos 21 /*!< LCD PAL179: G14_0 Position */ -#define LCD_PAL179_G14_0_Msk (0x1fUL << LCD_PAL179_G14_0_Pos) /*!< LCD PAL179: G14_0 Mask */ -#define LCD_PAL179_B14_0_Pos 26 /*!< LCD PAL179: B14_0 Position */ -#define LCD_PAL179_B14_0_Msk (0x1fUL << LCD_PAL179_B14_0_Pos) /*!< LCD PAL179: B14_0 Mask */ -#define LCD_PAL179_I1_Pos 31 /*!< LCD PAL179: I1 Position */ -#define LCD_PAL179_I1_Msk (0x01UL << LCD_PAL179_I1_Pos) /*!< LCD PAL179: I1 Mask */ - -// --------------------------------------- LCD_PAL180 ------------------------------------------- -#define LCD_PAL180_R04_0_Pos 0 /*!< LCD PAL180: R04_0 Position */ -#define LCD_PAL180_R04_0_Msk (0x1fUL << LCD_PAL180_R04_0_Pos) /*!< LCD PAL180: R04_0 Mask */ -#define LCD_PAL180_G04_0_Pos 5 /*!< LCD PAL180: G04_0 Position */ -#define LCD_PAL180_G04_0_Msk (0x1fUL << LCD_PAL180_G04_0_Pos) /*!< LCD PAL180: G04_0 Mask */ -#define LCD_PAL180_B04_0_Pos 10 /*!< LCD PAL180: B04_0 Position */ -#define LCD_PAL180_B04_0_Msk (0x1fUL << LCD_PAL180_B04_0_Pos) /*!< LCD PAL180: B04_0 Mask */ -#define LCD_PAL180_I0_Pos 15 /*!< LCD PAL180: I0 Position */ -#define LCD_PAL180_I0_Msk (0x01UL << LCD_PAL180_I0_Pos) /*!< LCD PAL180: I0 Mask */ -#define LCD_PAL180_R14_0_Pos 16 /*!< LCD PAL180: R14_0 Position */ -#define LCD_PAL180_R14_0_Msk (0x1fUL << LCD_PAL180_R14_0_Pos) /*!< LCD PAL180: R14_0 Mask */ -#define LCD_PAL180_G14_0_Pos 21 /*!< LCD PAL180: G14_0 Position */ -#define LCD_PAL180_G14_0_Msk (0x1fUL << LCD_PAL180_G14_0_Pos) /*!< LCD PAL180: G14_0 Mask */ -#define LCD_PAL180_B14_0_Pos 26 /*!< LCD PAL180: B14_0 Position */ -#define LCD_PAL180_B14_0_Msk (0x1fUL << LCD_PAL180_B14_0_Pos) /*!< LCD PAL180: B14_0 Mask */ -#define LCD_PAL180_I1_Pos 31 /*!< LCD PAL180: I1 Position */ -#define LCD_PAL180_I1_Msk (0x01UL << LCD_PAL180_I1_Pos) /*!< LCD PAL180: I1 Mask */ - -// --------------------------------------- LCD_PAL181 ------------------------------------------- -#define LCD_PAL181_R04_0_Pos 0 /*!< LCD PAL181: R04_0 Position */ -#define LCD_PAL181_R04_0_Msk (0x1fUL << LCD_PAL181_R04_0_Pos) /*!< LCD PAL181: R04_0 Mask */ -#define LCD_PAL181_G04_0_Pos 5 /*!< LCD PAL181: G04_0 Position */ -#define LCD_PAL181_G04_0_Msk (0x1fUL << LCD_PAL181_G04_0_Pos) /*!< LCD PAL181: G04_0 Mask */ -#define LCD_PAL181_B04_0_Pos 10 /*!< LCD PAL181: B04_0 Position */ -#define LCD_PAL181_B04_0_Msk (0x1fUL << LCD_PAL181_B04_0_Pos) /*!< LCD PAL181: B04_0 Mask */ -#define LCD_PAL181_I0_Pos 15 /*!< LCD PAL181: I0 Position */ -#define LCD_PAL181_I0_Msk (0x01UL << LCD_PAL181_I0_Pos) /*!< LCD PAL181: I0 Mask */ -#define LCD_PAL181_R14_0_Pos 16 /*!< LCD PAL181: R14_0 Position */ -#define LCD_PAL181_R14_0_Msk (0x1fUL << LCD_PAL181_R14_0_Pos) /*!< LCD PAL181: R14_0 Mask */ -#define LCD_PAL181_G14_0_Pos 21 /*!< LCD PAL181: G14_0 Position */ -#define LCD_PAL181_G14_0_Msk (0x1fUL << LCD_PAL181_G14_0_Pos) /*!< LCD PAL181: G14_0 Mask */ -#define LCD_PAL181_B14_0_Pos 26 /*!< LCD PAL181: B14_0 Position */ -#define LCD_PAL181_B14_0_Msk (0x1fUL << LCD_PAL181_B14_0_Pos) /*!< LCD PAL181: B14_0 Mask */ -#define LCD_PAL181_I1_Pos 31 /*!< LCD PAL181: I1 Position */ -#define LCD_PAL181_I1_Msk (0x01UL << LCD_PAL181_I1_Pos) /*!< LCD PAL181: I1 Mask */ - -// --------------------------------------- LCD_PAL182 ------------------------------------------- -#define LCD_PAL182_R04_0_Pos 0 /*!< LCD PAL182: R04_0 Position */ -#define LCD_PAL182_R04_0_Msk (0x1fUL << LCD_PAL182_R04_0_Pos) /*!< LCD PAL182: R04_0 Mask */ -#define LCD_PAL182_G04_0_Pos 5 /*!< LCD PAL182: G04_0 Position */ -#define LCD_PAL182_G04_0_Msk (0x1fUL << LCD_PAL182_G04_0_Pos) /*!< LCD PAL182: G04_0 Mask */ -#define LCD_PAL182_B04_0_Pos 10 /*!< LCD PAL182: B04_0 Position */ -#define LCD_PAL182_B04_0_Msk (0x1fUL << LCD_PAL182_B04_0_Pos) /*!< LCD PAL182: B04_0 Mask */ -#define LCD_PAL182_I0_Pos 15 /*!< LCD PAL182: I0 Position */ -#define LCD_PAL182_I0_Msk (0x01UL << LCD_PAL182_I0_Pos) /*!< LCD PAL182: I0 Mask */ -#define LCD_PAL182_R14_0_Pos 16 /*!< LCD PAL182: R14_0 Position */ -#define LCD_PAL182_R14_0_Msk (0x1fUL << LCD_PAL182_R14_0_Pos) /*!< LCD PAL182: R14_0 Mask */ -#define LCD_PAL182_G14_0_Pos 21 /*!< LCD PAL182: G14_0 Position */ -#define LCD_PAL182_G14_0_Msk (0x1fUL << LCD_PAL182_G14_0_Pos) /*!< LCD PAL182: G14_0 Mask */ -#define LCD_PAL182_B14_0_Pos 26 /*!< LCD PAL182: B14_0 Position */ -#define LCD_PAL182_B14_0_Msk (0x1fUL << LCD_PAL182_B14_0_Pos) /*!< LCD PAL182: B14_0 Mask */ -#define LCD_PAL182_I1_Pos 31 /*!< LCD PAL182: I1 Position */ -#define LCD_PAL182_I1_Msk (0x01UL << LCD_PAL182_I1_Pos) /*!< LCD PAL182: I1 Mask */ - -// --------------------------------------- LCD_PAL183 ------------------------------------------- -#define LCD_PAL183_R04_0_Pos 0 /*!< LCD PAL183: R04_0 Position */ -#define LCD_PAL183_R04_0_Msk (0x1fUL << LCD_PAL183_R04_0_Pos) /*!< LCD PAL183: R04_0 Mask */ -#define LCD_PAL183_G04_0_Pos 5 /*!< LCD PAL183: G04_0 Position */ -#define LCD_PAL183_G04_0_Msk (0x1fUL << LCD_PAL183_G04_0_Pos) /*!< LCD PAL183: G04_0 Mask */ -#define LCD_PAL183_B04_0_Pos 10 /*!< LCD PAL183: B04_0 Position */ -#define LCD_PAL183_B04_0_Msk (0x1fUL << LCD_PAL183_B04_0_Pos) /*!< LCD PAL183: B04_0 Mask */ -#define LCD_PAL183_I0_Pos 15 /*!< LCD PAL183: I0 Position */ -#define LCD_PAL183_I0_Msk (0x01UL << LCD_PAL183_I0_Pos) /*!< LCD PAL183: I0 Mask */ -#define LCD_PAL183_R14_0_Pos 16 /*!< LCD PAL183: R14_0 Position */ -#define LCD_PAL183_R14_0_Msk (0x1fUL << LCD_PAL183_R14_0_Pos) /*!< LCD PAL183: R14_0 Mask */ -#define LCD_PAL183_G14_0_Pos 21 /*!< LCD PAL183: G14_0 Position */ -#define LCD_PAL183_G14_0_Msk (0x1fUL << LCD_PAL183_G14_0_Pos) /*!< LCD PAL183: G14_0 Mask */ -#define LCD_PAL183_B14_0_Pos 26 /*!< LCD PAL183: B14_0 Position */ -#define LCD_PAL183_B14_0_Msk (0x1fUL << LCD_PAL183_B14_0_Pos) /*!< LCD PAL183: B14_0 Mask */ -#define LCD_PAL183_I1_Pos 31 /*!< LCD PAL183: I1 Position */ -#define LCD_PAL183_I1_Msk (0x01UL << LCD_PAL183_I1_Pos) /*!< LCD PAL183: I1 Mask */ - -// --------------------------------------- LCD_PAL184 ------------------------------------------- -#define LCD_PAL184_R04_0_Pos 0 /*!< LCD PAL184: R04_0 Position */ -#define LCD_PAL184_R04_0_Msk (0x1fUL << LCD_PAL184_R04_0_Pos) /*!< LCD PAL184: R04_0 Mask */ -#define LCD_PAL184_G04_0_Pos 5 /*!< LCD PAL184: G04_0 Position */ -#define LCD_PAL184_G04_0_Msk (0x1fUL << LCD_PAL184_G04_0_Pos) /*!< LCD PAL184: G04_0 Mask */ -#define LCD_PAL184_B04_0_Pos 10 /*!< LCD PAL184: B04_0 Position */ -#define LCD_PAL184_B04_0_Msk (0x1fUL << LCD_PAL184_B04_0_Pos) /*!< LCD PAL184: B04_0 Mask */ -#define LCD_PAL184_I0_Pos 15 /*!< LCD PAL184: I0 Position */ -#define LCD_PAL184_I0_Msk (0x01UL << LCD_PAL184_I0_Pos) /*!< LCD PAL184: I0 Mask */ -#define LCD_PAL184_R14_0_Pos 16 /*!< LCD PAL184: R14_0 Position */ -#define LCD_PAL184_R14_0_Msk (0x1fUL << LCD_PAL184_R14_0_Pos) /*!< LCD PAL184: R14_0 Mask */ -#define LCD_PAL184_G14_0_Pos 21 /*!< LCD PAL184: G14_0 Position */ -#define LCD_PAL184_G14_0_Msk (0x1fUL << LCD_PAL184_G14_0_Pos) /*!< LCD PAL184: G14_0 Mask */ -#define LCD_PAL184_B14_0_Pos 26 /*!< LCD PAL184: B14_0 Position */ -#define LCD_PAL184_B14_0_Msk (0x1fUL << LCD_PAL184_B14_0_Pos) /*!< LCD PAL184: B14_0 Mask */ -#define LCD_PAL184_I1_Pos 31 /*!< LCD PAL184: I1 Position */ -#define LCD_PAL184_I1_Msk (0x01UL << LCD_PAL184_I1_Pos) /*!< LCD PAL184: I1 Mask */ - -// --------------------------------------- LCD_PAL185 ------------------------------------------- -#define LCD_PAL185_R04_0_Pos 0 /*!< LCD PAL185: R04_0 Position */ -#define LCD_PAL185_R04_0_Msk (0x1fUL << LCD_PAL185_R04_0_Pos) /*!< LCD PAL185: R04_0 Mask */ -#define LCD_PAL185_G04_0_Pos 5 /*!< LCD PAL185: G04_0 Position */ -#define LCD_PAL185_G04_0_Msk (0x1fUL << LCD_PAL185_G04_0_Pos) /*!< LCD PAL185: G04_0 Mask */ -#define LCD_PAL185_B04_0_Pos 10 /*!< LCD PAL185: B04_0 Position */ -#define LCD_PAL185_B04_0_Msk (0x1fUL << LCD_PAL185_B04_0_Pos) /*!< LCD PAL185: B04_0 Mask */ -#define LCD_PAL185_I0_Pos 15 /*!< LCD PAL185: I0 Position */ -#define LCD_PAL185_I0_Msk (0x01UL << LCD_PAL185_I0_Pos) /*!< LCD PAL185: I0 Mask */ -#define LCD_PAL185_R14_0_Pos 16 /*!< LCD PAL185: R14_0 Position */ -#define LCD_PAL185_R14_0_Msk (0x1fUL << LCD_PAL185_R14_0_Pos) /*!< LCD PAL185: R14_0 Mask */ -#define LCD_PAL185_G14_0_Pos 21 /*!< LCD PAL185: G14_0 Position */ -#define LCD_PAL185_G14_0_Msk (0x1fUL << LCD_PAL185_G14_0_Pos) /*!< LCD PAL185: G14_0 Mask */ -#define LCD_PAL185_B14_0_Pos 26 /*!< LCD PAL185: B14_0 Position */ -#define LCD_PAL185_B14_0_Msk (0x1fUL << LCD_PAL185_B14_0_Pos) /*!< LCD PAL185: B14_0 Mask */ -#define LCD_PAL185_I1_Pos 31 /*!< LCD PAL185: I1 Position */ -#define LCD_PAL185_I1_Msk (0x01UL << LCD_PAL185_I1_Pos) /*!< LCD PAL185: I1 Mask */ - -// --------------------------------------- LCD_PAL186 ------------------------------------------- -#define LCD_PAL186_R04_0_Pos 0 /*!< LCD PAL186: R04_0 Position */ -#define LCD_PAL186_R04_0_Msk (0x1fUL << LCD_PAL186_R04_0_Pos) /*!< LCD PAL186: R04_0 Mask */ -#define LCD_PAL186_G04_0_Pos 5 /*!< LCD PAL186: G04_0 Position */ -#define LCD_PAL186_G04_0_Msk (0x1fUL << LCD_PAL186_G04_0_Pos) /*!< LCD PAL186: G04_0 Mask */ -#define LCD_PAL186_B04_0_Pos 10 /*!< LCD PAL186: B04_0 Position */ -#define LCD_PAL186_B04_0_Msk (0x1fUL << LCD_PAL186_B04_0_Pos) /*!< LCD PAL186: B04_0 Mask */ -#define LCD_PAL186_I0_Pos 15 /*!< LCD PAL186: I0 Position */ -#define LCD_PAL186_I0_Msk (0x01UL << LCD_PAL186_I0_Pos) /*!< LCD PAL186: I0 Mask */ -#define LCD_PAL186_R14_0_Pos 16 /*!< LCD PAL186: R14_0 Position */ -#define LCD_PAL186_R14_0_Msk (0x1fUL << LCD_PAL186_R14_0_Pos) /*!< LCD PAL186: R14_0 Mask */ -#define LCD_PAL186_G14_0_Pos 21 /*!< LCD PAL186: G14_0 Position */ -#define LCD_PAL186_G14_0_Msk (0x1fUL << LCD_PAL186_G14_0_Pos) /*!< LCD PAL186: G14_0 Mask */ -#define LCD_PAL186_B14_0_Pos 26 /*!< LCD PAL186: B14_0 Position */ -#define LCD_PAL186_B14_0_Msk (0x1fUL << LCD_PAL186_B14_0_Pos) /*!< LCD PAL186: B14_0 Mask */ -#define LCD_PAL186_I1_Pos 31 /*!< LCD PAL186: I1 Position */ -#define LCD_PAL186_I1_Msk (0x01UL << LCD_PAL186_I1_Pos) /*!< LCD PAL186: I1 Mask */ - -// --------------------------------------- LCD_PAL187 ------------------------------------------- -#define LCD_PAL187_R04_0_Pos 0 /*!< LCD PAL187: R04_0 Position */ -#define LCD_PAL187_R04_0_Msk (0x1fUL << LCD_PAL187_R04_0_Pos) /*!< LCD PAL187: R04_0 Mask */ -#define LCD_PAL187_G04_0_Pos 5 /*!< LCD PAL187: G04_0 Position */ -#define LCD_PAL187_G04_0_Msk (0x1fUL << LCD_PAL187_G04_0_Pos) /*!< LCD PAL187: G04_0 Mask */ -#define LCD_PAL187_B04_0_Pos 10 /*!< LCD PAL187: B04_0 Position */ -#define LCD_PAL187_B04_0_Msk (0x1fUL << LCD_PAL187_B04_0_Pos) /*!< LCD PAL187: B04_0 Mask */ -#define LCD_PAL187_I0_Pos 15 /*!< LCD PAL187: I0 Position */ -#define LCD_PAL187_I0_Msk (0x01UL << LCD_PAL187_I0_Pos) /*!< LCD PAL187: I0 Mask */ -#define LCD_PAL187_R14_0_Pos 16 /*!< LCD PAL187: R14_0 Position */ -#define LCD_PAL187_R14_0_Msk (0x1fUL << LCD_PAL187_R14_0_Pos) /*!< LCD PAL187: R14_0 Mask */ -#define LCD_PAL187_G14_0_Pos 21 /*!< LCD PAL187: G14_0 Position */ -#define LCD_PAL187_G14_0_Msk (0x1fUL << LCD_PAL187_G14_0_Pos) /*!< LCD PAL187: G14_0 Mask */ -#define LCD_PAL187_B14_0_Pos 26 /*!< LCD PAL187: B14_0 Position */ -#define LCD_PAL187_B14_0_Msk (0x1fUL << LCD_PAL187_B14_0_Pos) /*!< LCD PAL187: B14_0 Mask */ -#define LCD_PAL187_I1_Pos 31 /*!< LCD PAL187: I1 Position */ -#define LCD_PAL187_I1_Msk (0x01UL << LCD_PAL187_I1_Pos) /*!< LCD PAL187: I1 Mask */ - -// --------------------------------------- LCD_PAL188 ------------------------------------------- -#define LCD_PAL188_R04_0_Pos 0 /*!< LCD PAL188: R04_0 Position */ -#define LCD_PAL188_R04_0_Msk (0x1fUL << LCD_PAL188_R04_0_Pos) /*!< LCD PAL188: R04_0 Mask */ -#define LCD_PAL188_G04_0_Pos 5 /*!< LCD PAL188: G04_0 Position */ -#define LCD_PAL188_G04_0_Msk (0x1fUL << LCD_PAL188_G04_0_Pos) /*!< LCD PAL188: G04_0 Mask */ -#define LCD_PAL188_B04_0_Pos 10 /*!< LCD PAL188: B04_0 Position */ -#define LCD_PAL188_B04_0_Msk (0x1fUL << LCD_PAL188_B04_0_Pos) /*!< LCD PAL188: B04_0 Mask */ -#define LCD_PAL188_I0_Pos 15 /*!< LCD PAL188: I0 Position */ -#define LCD_PAL188_I0_Msk (0x01UL << LCD_PAL188_I0_Pos) /*!< LCD PAL188: I0 Mask */ -#define LCD_PAL188_R14_0_Pos 16 /*!< LCD PAL188: R14_0 Position */ -#define LCD_PAL188_R14_0_Msk (0x1fUL << LCD_PAL188_R14_0_Pos) /*!< LCD PAL188: R14_0 Mask */ -#define LCD_PAL188_G14_0_Pos 21 /*!< LCD PAL188: G14_0 Position */ -#define LCD_PAL188_G14_0_Msk (0x1fUL << LCD_PAL188_G14_0_Pos) /*!< LCD PAL188: G14_0 Mask */ -#define LCD_PAL188_B14_0_Pos 26 /*!< LCD PAL188: B14_0 Position */ -#define LCD_PAL188_B14_0_Msk (0x1fUL << LCD_PAL188_B14_0_Pos) /*!< LCD PAL188: B14_0 Mask */ -#define LCD_PAL188_I1_Pos 31 /*!< LCD PAL188: I1 Position */ -#define LCD_PAL188_I1_Msk (0x01UL << LCD_PAL188_I1_Pos) /*!< LCD PAL188: I1 Mask */ - -// --------------------------------------- LCD_PAL189 ------------------------------------------- -#define LCD_PAL189_R04_0_Pos 0 /*!< LCD PAL189: R04_0 Position */ -#define LCD_PAL189_R04_0_Msk (0x1fUL << LCD_PAL189_R04_0_Pos) /*!< LCD PAL189: R04_0 Mask */ -#define LCD_PAL189_G04_0_Pos 5 /*!< LCD PAL189: G04_0 Position */ -#define LCD_PAL189_G04_0_Msk (0x1fUL << LCD_PAL189_G04_0_Pos) /*!< LCD PAL189: G04_0 Mask */ -#define LCD_PAL189_B04_0_Pos 10 /*!< LCD PAL189: B04_0 Position */ -#define LCD_PAL189_B04_0_Msk (0x1fUL << LCD_PAL189_B04_0_Pos) /*!< LCD PAL189: B04_0 Mask */ -#define LCD_PAL189_I0_Pos 15 /*!< LCD PAL189: I0 Position */ -#define LCD_PAL189_I0_Msk (0x01UL << LCD_PAL189_I0_Pos) /*!< LCD PAL189: I0 Mask */ -#define LCD_PAL189_R14_0_Pos 16 /*!< LCD PAL189: R14_0 Position */ -#define LCD_PAL189_R14_0_Msk (0x1fUL << LCD_PAL189_R14_0_Pos) /*!< LCD PAL189: R14_0 Mask */ -#define LCD_PAL189_G14_0_Pos 21 /*!< LCD PAL189: G14_0 Position */ -#define LCD_PAL189_G14_0_Msk (0x1fUL << LCD_PAL189_G14_0_Pos) /*!< LCD PAL189: G14_0 Mask */ -#define LCD_PAL189_B14_0_Pos 26 /*!< LCD PAL189: B14_0 Position */ -#define LCD_PAL189_B14_0_Msk (0x1fUL << LCD_PAL189_B14_0_Pos) /*!< LCD PAL189: B14_0 Mask */ -#define LCD_PAL189_I1_Pos 31 /*!< LCD PAL189: I1 Position */ -#define LCD_PAL189_I1_Msk (0x01UL << LCD_PAL189_I1_Pos) /*!< LCD PAL189: I1 Mask */ - -// --------------------------------------- LCD_PAL190 ------------------------------------------- -#define LCD_PAL190_R04_0_Pos 0 /*!< LCD PAL190: R04_0 Position */ -#define LCD_PAL190_R04_0_Msk (0x1fUL << LCD_PAL190_R04_0_Pos) /*!< LCD PAL190: R04_0 Mask */ -#define LCD_PAL190_G04_0_Pos 5 /*!< LCD PAL190: G04_0 Position */ -#define LCD_PAL190_G04_0_Msk (0x1fUL << LCD_PAL190_G04_0_Pos) /*!< LCD PAL190: G04_0 Mask */ -#define LCD_PAL190_B04_0_Pos 10 /*!< LCD PAL190: B04_0 Position */ -#define LCD_PAL190_B04_0_Msk (0x1fUL << LCD_PAL190_B04_0_Pos) /*!< LCD PAL190: B04_0 Mask */ -#define LCD_PAL190_I0_Pos 15 /*!< LCD PAL190: I0 Position */ -#define LCD_PAL190_I0_Msk (0x01UL << LCD_PAL190_I0_Pos) /*!< LCD PAL190: I0 Mask */ -#define LCD_PAL190_R14_0_Pos 16 /*!< LCD PAL190: R14_0 Position */ -#define LCD_PAL190_R14_0_Msk (0x1fUL << LCD_PAL190_R14_0_Pos) /*!< LCD PAL190: R14_0 Mask */ -#define LCD_PAL190_G14_0_Pos 21 /*!< LCD PAL190: G14_0 Position */ -#define LCD_PAL190_G14_0_Msk (0x1fUL << LCD_PAL190_G14_0_Pos) /*!< LCD PAL190: G14_0 Mask */ -#define LCD_PAL190_B14_0_Pos 26 /*!< LCD PAL190: B14_0 Position */ -#define LCD_PAL190_B14_0_Msk (0x1fUL << LCD_PAL190_B14_0_Pos) /*!< LCD PAL190: B14_0 Mask */ -#define LCD_PAL190_I1_Pos 31 /*!< LCD PAL190: I1 Position */ -#define LCD_PAL190_I1_Msk (0x01UL << LCD_PAL190_I1_Pos) /*!< LCD PAL190: I1 Mask */ - -// --------------------------------------- LCD_PAL191 ------------------------------------------- -#define LCD_PAL191_R04_0_Pos 0 /*!< LCD PAL191: R04_0 Position */ -#define LCD_PAL191_R04_0_Msk (0x1fUL << LCD_PAL191_R04_0_Pos) /*!< LCD PAL191: R04_0 Mask */ -#define LCD_PAL191_G04_0_Pos 5 /*!< LCD PAL191: G04_0 Position */ -#define LCD_PAL191_G04_0_Msk (0x1fUL << LCD_PAL191_G04_0_Pos) /*!< LCD PAL191: G04_0 Mask */ -#define LCD_PAL191_B04_0_Pos 10 /*!< LCD PAL191: B04_0 Position */ -#define LCD_PAL191_B04_0_Msk (0x1fUL << LCD_PAL191_B04_0_Pos) /*!< LCD PAL191: B04_0 Mask */ -#define LCD_PAL191_I0_Pos 15 /*!< LCD PAL191: I0 Position */ -#define LCD_PAL191_I0_Msk (0x01UL << LCD_PAL191_I0_Pos) /*!< LCD PAL191: I0 Mask */ -#define LCD_PAL191_R14_0_Pos 16 /*!< LCD PAL191: R14_0 Position */ -#define LCD_PAL191_R14_0_Msk (0x1fUL << LCD_PAL191_R14_0_Pos) /*!< LCD PAL191: R14_0 Mask */ -#define LCD_PAL191_G14_0_Pos 21 /*!< LCD PAL191: G14_0 Position */ -#define LCD_PAL191_G14_0_Msk (0x1fUL << LCD_PAL191_G14_0_Pos) /*!< LCD PAL191: G14_0 Mask */ -#define LCD_PAL191_B14_0_Pos 26 /*!< LCD PAL191: B14_0 Position */ -#define LCD_PAL191_B14_0_Msk (0x1fUL << LCD_PAL191_B14_0_Pos) /*!< LCD PAL191: B14_0 Mask */ -#define LCD_PAL191_I1_Pos 31 /*!< LCD PAL191: I1 Position */ -#define LCD_PAL191_I1_Msk (0x01UL << LCD_PAL191_I1_Pos) /*!< LCD PAL191: I1 Mask */ - -// --------------------------------------- LCD_PAL192 ------------------------------------------- -#define LCD_PAL192_R04_0_Pos 0 /*!< LCD PAL192: R04_0 Position */ -#define LCD_PAL192_R04_0_Msk (0x1fUL << LCD_PAL192_R04_0_Pos) /*!< LCD PAL192: R04_0 Mask */ -#define LCD_PAL192_G04_0_Pos 5 /*!< LCD PAL192: G04_0 Position */ -#define LCD_PAL192_G04_0_Msk (0x1fUL << LCD_PAL192_G04_0_Pos) /*!< LCD PAL192: G04_0 Mask */ -#define LCD_PAL192_B04_0_Pos 10 /*!< LCD PAL192: B04_0 Position */ -#define LCD_PAL192_B04_0_Msk (0x1fUL << LCD_PAL192_B04_0_Pos) /*!< LCD PAL192: B04_0 Mask */ -#define LCD_PAL192_I0_Pos 15 /*!< LCD PAL192: I0 Position */ -#define LCD_PAL192_I0_Msk (0x01UL << LCD_PAL192_I0_Pos) /*!< LCD PAL192: I0 Mask */ -#define LCD_PAL192_R14_0_Pos 16 /*!< LCD PAL192: R14_0 Position */ -#define LCD_PAL192_R14_0_Msk (0x1fUL << LCD_PAL192_R14_0_Pos) /*!< LCD PAL192: R14_0 Mask */ -#define LCD_PAL192_G14_0_Pos 21 /*!< LCD PAL192: G14_0 Position */ -#define LCD_PAL192_G14_0_Msk (0x1fUL << LCD_PAL192_G14_0_Pos) /*!< LCD PAL192: G14_0 Mask */ -#define LCD_PAL192_B14_0_Pos 26 /*!< LCD PAL192: B14_0 Position */ -#define LCD_PAL192_B14_0_Msk (0x1fUL << LCD_PAL192_B14_0_Pos) /*!< LCD PAL192: B14_0 Mask */ -#define LCD_PAL192_I1_Pos 31 /*!< LCD PAL192: I1 Position */ -#define LCD_PAL192_I1_Msk (0x01UL << LCD_PAL192_I1_Pos) /*!< LCD PAL192: I1 Mask */ - -// --------------------------------------- LCD_PAL193 ------------------------------------------- -#define LCD_PAL193_R04_0_Pos 0 /*!< LCD PAL193: R04_0 Position */ -#define LCD_PAL193_R04_0_Msk (0x1fUL << LCD_PAL193_R04_0_Pos) /*!< LCD PAL193: R04_0 Mask */ -#define LCD_PAL193_G04_0_Pos 5 /*!< LCD PAL193: G04_0 Position */ -#define LCD_PAL193_G04_0_Msk (0x1fUL << LCD_PAL193_G04_0_Pos) /*!< LCD PAL193: G04_0 Mask */ -#define LCD_PAL193_B04_0_Pos 10 /*!< LCD PAL193: B04_0 Position */ -#define LCD_PAL193_B04_0_Msk (0x1fUL << LCD_PAL193_B04_0_Pos) /*!< LCD PAL193: B04_0 Mask */ -#define LCD_PAL193_I0_Pos 15 /*!< LCD PAL193: I0 Position */ -#define LCD_PAL193_I0_Msk (0x01UL << LCD_PAL193_I0_Pos) /*!< LCD PAL193: I0 Mask */ -#define LCD_PAL193_R14_0_Pos 16 /*!< LCD PAL193: R14_0 Position */ -#define LCD_PAL193_R14_0_Msk (0x1fUL << LCD_PAL193_R14_0_Pos) /*!< LCD PAL193: R14_0 Mask */ -#define LCD_PAL193_G14_0_Pos 21 /*!< LCD PAL193: G14_0 Position */ -#define LCD_PAL193_G14_0_Msk (0x1fUL << LCD_PAL193_G14_0_Pos) /*!< LCD PAL193: G14_0 Mask */ -#define LCD_PAL193_B14_0_Pos 26 /*!< LCD PAL193: B14_0 Position */ -#define LCD_PAL193_B14_0_Msk (0x1fUL << LCD_PAL193_B14_0_Pos) /*!< LCD PAL193: B14_0 Mask */ -#define LCD_PAL193_I1_Pos 31 /*!< LCD PAL193: I1 Position */ -#define LCD_PAL193_I1_Msk (0x01UL << LCD_PAL193_I1_Pos) /*!< LCD PAL193: I1 Mask */ - -// --------------------------------------- LCD_PAL194 ------------------------------------------- -#define LCD_PAL194_R04_0_Pos 0 /*!< LCD PAL194: R04_0 Position */ -#define LCD_PAL194_R04_0_Msk (0x1fUL << LCD_PAL194_R04_0_Pos) /*!< LCD PAL194: R04_0 Mask */ -#define LCD_PAL194_G04_0_Pos 5 /*!< LCD PAL194: G04_0 Position */ -#define LCD_PAL194_G04_0_Msk (0x1fUL << LCD_PAL194_G04_0_Pos) /*!< LCD PAL194: G04_0 Mask */ -#define LCD_PAL194_B04_0_Pos 10 /*!< LCD PAL194: B04_0 Position */ -#define LCD_PAL194_B04_0_Msk (0x1fUL << LCD_PAL194_B04_0_Pos) /*!< LCD PAL194: B04_0 Mask */ -#define LCD_PAL194_I0_Pos 15 /*!< LCD PAL194: I0 Position */ -#define LCD_PAL194_I0_Msk (0x01UL << LCD_PAL194_I0_Pos) /*!< LCD PAL194: I0 Mask */ -#define LCD_PAL194_R14_0_Pos 16 /*!< LCD PAL194: R14_0 Position */ -#define LCD_PAL194_R14_0_Msk (0x1fUL << LCD_PAL194_R14_0_Pos) /*!< LCD PAL194: R14_0 Mask */ -#define LCD_PAL194_G14_0_Pos 21 /*!< LCD PAL194: G14_0 Position */ -#define LCD_PAL194_G14_0_Msk (0x1fUL << LCD_PAL194_G14_0_Pos) /*!< LCD PAL194: G14_0 Mask */ -#define LCD_PAL194_B14_0_Pos 26 /*!< LCD PAL194: B14_0 Position */ -#define LCD_PAL194_B14_0_Msk (0x1fUL << LCD_PAL194_B14_0_Pos) /*!< LCD PAL194: B14_0 Mask */ -#define LCD_PAL194_I1_Pos 31 /*!< LCD PAL194: I1 Position */ -#define LCD_PAL194_I1_Msk (0x01UL << LCD_PAL194_I1_Pos) /*!< LCD PAL194: I1 Mask */ - -// --------------------------------------- LCD_PAL195 ------------------------------------------- -#define LCD_PAL195_R04_0_Pos 0 /*!< LCD PAL195: R04_0 Position */ -#define LCD_PAL195_R04_0_Msk (0x1fUL << LCD_PAL195_R04_0_Pos) /*!< LCD PAL195: R04_0 Mask */ -#define LCD_PAL195_G04_0_Pos 5 /*!< LCD PAL195: G04_0 Position */ -#define LCD_PAL195_G04_0_Msk (0x1fUL << LCD_PAL195_G04_0_Pos) /*!< LCD PAL195: G04_0 Mask */ -#define LCD_PAL195_B04_0_Pos 10 /*!< LCD PAL195: B04_0 Position */ -#define LCD_PAL195_B04_0_Msk (0x1fUL << LCD_PAL195_B04_0_Pos) /*!< LCD PAL195: B04_0 Mask */ -#define LCD_PAL195_I0_Pos 15 /*!< LCD PAL195: I0 Position */ -#define LCD_PAL195_I0_Msk (0x01UL << LCD_PAL195_I0_Pos) /*!< LCD PAL195: I0 Mask */ -#define LCD_PAL195_R14_0_Pos 16 /*!< LCD PAL195: R14_0 Position */ -#define LCD_PAL195_R14_0_Msk (0x1fUL << LCD_PAL195_R14_0_Pos) /*!< LCD PAL195: R14_0 Mask */ -#define LCD_PAL195_G14_0_Pos 21 /*!< LCD PAL195: G14_0 Position */ -#define LCD_PAL195_G14_0_Msk (0x1fUL << LCD_PAL195_G14_0_Pos) /*!< LCD PAL195: G14_0 Mask */ -#define LCD_PAL195_B14_0_Pos 26 /*!< LCD PAL195: B14_0 Position */ -#define LCD_PAL195_B14_0_Msk (0x1fUL << LCD_PAL195_B14_0_Pos) /*!< LCD PAL195: B14_0 Mask */ -#define LCD_PAL195_I1_Pos 31 /*!< LCD PAL195: I1 Position */ -#define LCD_PAL195_I1_Msk (0x01UL << LCD_PAL195_I1_Pos) /*!< LCD PAL195: I1 Mask */ - -// --------------------------------------- LCD_PAL196 ------------------------------------------- -#define LCD_PAL196_R04_0_Pos 0 /*!< LCD PAL196: R04_0 Position */ -#define LCD_PAL196_R04_0_Msk (0x1fUL << LCD_PAL196_R04_0_Pos) /*!< LCD PAL196: R04_0 Mask */ -#define LCD_PAL196_G04_0_Pos 5 /*!< LCD PAL196: G04_0 Position */ -#define LCD_PAL196_G04_0_Msk (0x1fUL << LCD_PAL196_G04_0_Pos) /*!< LCD PAL196: G04_0 Mask */ -#define LCD_PAL196_B04_0_Pos 10 /*!< LCD PAL196: B04_0 Position */ -#define LCD_PAL196_B04_0_Msk (0x1fUL << LCD_PAL196_B04_0_Pos) /*!< LCD PAL196: B04_0 Mask */ -#define LCD_PAL196_I0_Pos 15 /*!< LCD PAL196: I0 Position */ -#define LCD_PAL196_I0_Msk (0x01UL << LCD_PAL196_I0_Pos) /*!< LCD PAL196: I0 Mask */ -#define LCD_PAL196_R14_0_Pos 16 /*!< LCD PAL196: R14_0 Position */ -#define LCD_PAL196_R14_0_Msk (0x1fUL << LCD_PAL196_R14_0_Pos) /*!< LCD PAL196: R14_0 Mask */ -#define LCD_PAL196_G14_0_Pos 21 /*!< LCD PAL196: G14_0 Position */ -#define LCD_PAL196_G14_0_Msk (0x1fUL << LCD_PAL196_G14_0_Pos) /*!< LCD PAL196: G14_0 Mask */ -#define LCD_PAL196_B14_0_Pos 26 /*!< LCD PAL196: B14_0 Position */ -#define LCD_PAL196_B14_0_Msk (0x1fUL << LCD_PAL196_B14_0_Pos) /*!< LCD PAL196: B14_0 Mask */ -#define LCD_PAL196_I1_Pos 31 /*!< LCD PAL196: I1 Position */ -#define LCD_PAL196_I1_Msk (0x01UL << LCD_PAL196_I1_Pos) /*!< LCD PAL196: I1 Mask */ - -// --------------------------------------- LCD_PAL197 ------------------------------------------- -#define LCD_PAL197_R04_0_Pos 0 /*!< LCD PAL197: R04_0 Position */ -#define LCD_PAL197_R04_0_Msk (0x1fUL << LCD_PAL197_R04_0_Pos) /*!< LCD PAL197: R04_0 Mask */ -#define LCD_PAL197_G04_0_Pos 5 /*!< LCD PAL197: G04_0 Position */ -#define LCD_PAL197_G04_0_Msk (0x1fUL << LCD_PAL197_G04_0_Pos) /*!< LCD PAL197: G04_0 Mask */ -#define LCD_PAL197_B04_0_Pos 10 /*!< LCD PAL197: B04_0 Position */ -#define LCD_PAL197_B04_0_Msk (0x1fUL << LCD_PAL197_B04_0_Pos) /*!< LCD PAL197: B04_0 Mask */ -#define LCD_PAL197_I0_Pos 15 /*!< LCD PAL197: I0 Position */ -#define LCD_PAL197_I0_Msk (0x01UL << LCD_PAL197_I0_Pos) /*!< LCD PAL197: I0 Mask */ -#define LCD_PAL197_R14_0_Pos 16 /*!< LCD PAL197: R14_0 Position */ -#define LCD_PAL197_R14_0_Msk (0x1fUL << LCD_PAL197_R14_0_Pos) /*!< LCD PAL197: R14_0 Mask */ -#define LCD_PAL197_G14_0_Pos 21 /*!< LCD PAL197: G14_0 Position */ -#define LCD_PAL197_G14_0_Msk (0x1fUL << LCD_PAL197_G14_0_Pos) /*!< LCD PAL197: G14_0 Mask */ -#define LCD_PAL197_B14_0_Pos 26 /*!< LCD PAL197: B14_0 Position */ -#define LCD_PAL197_B14_0_Msk (0x1fUL << LCD_PAL197_B14_0_Pos) /*!< LCD PAL197: B14_0 Mask */ -#define LCD_PAL197_I1_Pos 31 /*!< LCD PAL197: I1 Position */ -#define LCD_PAL197_I1_Msk (0x01UL << LCD_PAL197_I1_Pos) /*!< LCD PAL197: I1 Mask */ - -// --------------------------------------- LCD_PAL198 ------------------------------------------- -#define LCD_PAL198_R04_0_Pos 0 /*!< LCD PAL198: R04_0 Position */ -#define LCD_PAL198_R04_0_Msk (0x1fUL << LCD_PAL198_R04_0_Pos) /*!< LCD PAL198: R04_0 Mask */ -#define LCD_PAL198_G04_0_Pos 5 /*!< LCD PAL198: G04_0 Position */ -#define LCD_PAL198_G04_0_Msk (0x1fUL << LCD_PAL198_G04_0_Pos) /*!< LCD PAL198: G04_0 Mask */ -#define LCD_PAL198_B04_0_Pos 10 /*!< LCD PAL198: B04_0 Position */ -#define LCD_PAL198_B04_0_Msk (0x1fUL << LCD_PAL198_B04_0_Pos) /*!< LCD PAL198: B04_0 Mask */ -#define LCD_PAL198_I0_Pos 15 /*!< LCD PAL198: I0 Position */ -#define LCD_PAL198_I0_Msk (0x01UL << LCD_PAL198_I0_Pos) /*!< LCD PAL198: I0 Mask */ -#define LCD_PAL198_R14_0_Pos 16 /*!< LCD PAL198: R14_0 Position */ -#define LCD_PAL198_R14_0_Msk (0x1fUL << LCD_PAL198_R14_0_Pos) /*!< LCD PAL198: R14_0 Mask */ -#define LCD_PAL198_G14_0_Pos 21 /*!< LCD PAL198: G14_0 Position */ -#define LCD_PAL198_G14_0_Msk (0x1fUL << LCD_PAL198_G14_0_Pos) /*!< LCD PAL198: G14_0 Mask */ -#define LCD_PAL198_B14_0_Pos 26 /*!< LCD PAL198: B14_0 Position */ -#define LCD_PAL198_B14_0_Msk (0x1fUL << LCD_PAL198_B14_0_Pos) /*!< LCD PAL198: B14_0 Mask */ -#define LCD_PAL198_I1_Pos 31 /*!< LCD PAL198: I1 Position */ -#define LCD_PAL198_I1_Msk (0x01UL << LCD_PAL198_I1_Pos) /*!< LCD PAL198: I1 Mask */ - -// --------------------------------------- LCD_PAL199 ------------------------------------------- -#define LCD_PAL199_R04_0_Pos 0 /*!< LCD PAL199: R04_0 Position */ -#define LCD_PAL199_R04_0_Msk (0x1fUL << LCD_PAL199_R04_0_Pos) /*!< LCD PAL199: R04_0 Mask */ -#define LCD_PAL199_G04_0_Pos 5 /*!< LCD PAL199: G04_0 Position */ -#define LCD_PAL199_G04_0_Msk (0x1fUL << LCD_PAL199_G04_0_Pos) /*!< LCD PAL199: G04_0 Mask */ -#define LCD_PAL199_B04_0_Pos 10 /*!< LCD PAL199: B04_0 Position */ -#define LCD_PAL199_B04_0_Msk (0x1fUL << LCD_PAL199_B04_0_Pos) /*!< LCD PAL199: B04_0 Mask */ -#define LCD_PAL199_I0_Pos 15 /*!< LCD PAL199: I0 Position */ -#define LCD_PAL199_I0_Msk (0x01UL << LCD_PAL199_I0_Pos) /*!< LCD PAL199: I0 Mask */ -#define LCD_PAL199_R14_0_Pos 16 /*!< LCD PAL199: R14_0 Position */ -#define LCD_PAL199_R14_0_Msk (0x1fUL << LCD_PAL199_R14_0_Pos) /*!< LCD PAL199: R14_0 Mask */ -#define LCD_PAL199_G14_0_Pos 21 /*!< LCD PAL199: G14_0 Position */ -#define LCD_PAL199_G14_0_Msk (0x1fUL << LCD_PAL199_G14_0_Pos) /*!< LCD PAL199: G14_0 Mask */ -#define LCD_PAL199_B14_0_Pos 26 /*!< LCD PAL199: B14_0 Position */ -#define LCD_PAL199_B14_0_Msk (0x1fUL << LCD_PAL199_B14_0_Pos) /*!< LCD PAL199: B14_0 Mask */ -#define LCD_PAL199_I1_Pos 31 /*!< LCD PAL199: I1 Position */ -#define LCD_PAL199_I1_Msk (0x01UL << LCD_PAL199_I1_Pos) /*!< LCD PAL199: I1 Mask */ - -// --------------------------------------- LCD_PAL200 ------------------------------------------- -#define LCD_PAL200_R04_0_Pos 0 /*!< LCD PAL200: R04_0 Position */ -#define LCD_PAL200_R04_0_Msk (0x1fUL << LCD_PAL200_R04_0_Pos) /*!< LCD PAL200: R04_0 Mask */ -#define LCD_PAL200_G04_0_Pos 5 /*!< LCD PAL200: G04_0 Position */ -#define LCD_PAL200_G04_0_Msk (0x1fUL << LCD_PAL200_G04_0_Pos) /*!< LCD PAL200: G04_0 Mask */ -#define LCD_PAL200_B04_0_Pos 10 /*!< LCD PAL200: B04_0 Position */ -#define LCD_PAL200_B04_0_Msk (0x1fUL << LCD_PAL200_B04_0_Pos) /*!< LCD PAL200: B04_0 Mask */ -#define LCD_PAL200_I0_Pos 15 /*!< LCD PAL200: I0 Position */ -#define LCD_PAL200_I0_Msk (0x01UL << LCD_PAL200_I0_Pos) /*!< LCD PAL200: I0 Mask */ -#define LCD_PAL200_R14_0_Pos 16 /*!< LCD PAL200: R14_0 Position */ -#define LCD_PAL200_R14_0_Msk (0x1fUL << LCD_PAL200_R14_0_Pos) /*!< LCD PAL200: R14_0 Mask */ -#define LCD_PAL200_G14_0_Pos 21 /*!< LCD PAL200: G14_0 Position */ -#define LCD_PAL200_G14_0_Msk (0x1fUL << LCD_PAL200_G14_0_Pos) /*!< LCD PAL200: G14_0 Mask */ -#define LCD_PAL200_B14_0_Pos 26 /*!< LCD PAL200: B14_0 Position */ -#define LCD_PAL200_B14_0_Msk (0x1fUL << LCD_PAL200_B14_0_Pos) /*!< LCD PAL200: B14_0 Mask */ -#define LCD_PAL200_I1_Pos 31 /*!< LCD PAL200: I1 Position */ -#define LCD_PAL200_I1_Msk (0x01UL << LCD_PAL200_I1_Pos) /*!< LCD PAL200: I1 Mask */ - -// --------------------------------------- LCD_PAL201 ------------------------------------------- -#define LCD_PAL201_R04_0_Pos 0 /*!< LCD PAL201: R04_0 Position */ -#define LCD_PAL201_R04_0_Msk (0x1fUL << LCD_PAL201_R04_0_Pos) /*!< LCD PAL201: R04_0 Mask */ -#define LCD_PAL201_G04_0_Pos 5 /*!< LCD PAL201: G04_0 Position */ -#define LCD_PAL201_G04_0_Msk (0x1fUL << LCD_PAL201_G04_0_Pos) /*!< LCD PAL201: G04_0 Mask */ -#define LCD_PAL201_B04_0_Pos 10 /*!< LCD PAL201: B04_0 Position */ -#define LCD_PAL201_B04_0_Msk (0x1fUL << LCD_PAL201_B04_0_Pos) /*!< LCD PAL201: B04_0 Mask */ -#define LCD_PAL201_I0_Pos 15 /*!< LCD PAL201: I0 Position */ -#define LCD_PAL201_I0_Msk (0x01UL << LCD_PAL201_I0_Pos) /*!< LCD PAL201: I0 Mask */ -#define LCD_PAL201_R14_0_Pos 16 /*!< LCD PAL201: R14_0 Position */ -#define LCD_PAL201_R14_0_Msk (0x1fUL << LCD_PAL201_R14_0_Pos) /*!< LCD PAL201: R14_0 Mask */ -#define LCD_PAL201_G14_0_Pos 21 /*!< LCD PAL201: G14_0 Position */ -#define LCD_PAL201_G14_0_Msk (0x1fUL << LCD_PAL201_G14_0_Pos) /*!< LCD PAL201: G14_0 Mask */ -#define LCD_PAL201_B14_0_Pos 26 /*!< LCD PAL201: B14_0 Position */ -#define LCD_PAL201_B14_0_Msk (0x1fUL << LCD_PAL201_B14_0_Pos) /*!< LCD PAL201: B14_0 Mask */ -#define LCD_PAL201_I1_Pos 31 /*!< LCD PAL201: I1 Position */ -#define LCD_PAL201_I1_Msk (0x01UL << LCD_PAL201_I1_Pos) /*!< LCD PAL201: I1 Mask */ - -// --------------------------------------- LCD_PAL202 ------------------------------------------- -#define LCD_PAL202_R04_0_Pos 0 /*!< LCD PAL202: R04_0 Position */ -#define LCD_PAL202_R04_0_Msk (0x1fUL << LCD_PAL202_R04_0_Pos) /*!< LCD PAL202: R04_0 Mask */ -#define LCD_PAL202_G04_0_Pos 5 /*!< LCD PAL202: G04_0 Position */ -#define LCD_PAL202_G04_0_Msk (0x1fUL << LCD_PAL202_G04_0_Pos) /*!< LCD PAL202: G04_0 Mask */ -#define LCD_PAL202_B04_0_Pos 10 /*!< LCD PAL202: B04_0 Position */ -#define LCD_PAL202_B04_0_Msk (0x1fUL << LCD_PAL202_B04_0_Pos) /*!< LCD PAL202: B04_0 Mask */ -#define LCD_PAL202_I0_Pos 15 /*!< LCD PAL202: I0 Position */ -#define LCD_PAL202_I0_Msk (0x01UL << LCD_PAL202_I0_Pos) /*!< LCD PAL202: I0 Mask */ -#define LCD_PAL202_R14_0_Pos 16 /*!< LCD PAL202: R14_0 Position */ -#define LCD_PAL202_R14_0_Msk (0x1fUL << LCD_PAL202_R14_0_Pos) /*!< LCD PAL202: R14_0 Mask */ -#define LCD_PAL202_G14_0_Pos 21 /*!< LCD PAL202: G14_0 Position */ -#define LCD_PAL202_G14_0_Msk (0x1fUL << LCD_PAL202_G14_0_Pos) /*!< LCD PAL202: G14_0 Mask */ -#define LCD_PAL202_B14_0_Pos 26 /*!< LCD PAL202: B14_0 Position */ -#define LCD_PAL202_B14_0_Msk (0x1fUL << LCD_PAL202_B14_0_Pos) /*!< LCD PAL202: B14_0 Mask */ -#define LCD_PAL202_I1_Pos 31 /*!< LCD PAL202: I1 Position */ -#define LCD_PAL202_I1_Msk (0x01UL << LCD_PAL202_I1_Pos) /*!< LCD PAL202: I1 Mask */ - -// --------------------------------------- LCD_PAL203 ------------------------------------------- -#define LCD_PAL203_R04_0_Pos 0 /*!< LCD PAL203: R04_0 Position */ -#define LCD_PAL203_R04_0_Msk (0x1fUL << LCD_PAL203_R04_0_Pos) /*!< LCD PAL203: R04_0 Mask */ -#define LCD_PAL203_G04_0_Pos 5 /*!< LCD PAL203: G04_0 Position */ -#define LCD_PAL203_G04_0_Msk (0x1fUL << LCD_PAL203_G04_0_Pos) /*!< LCD PAL203: G04_0 Mask */ -#define LCD_PAL203_B04_0_Pos 10 /*!< LCD PAL203: B04_0 Position */ -#define LCD_PAL203_B04_0_Msk (0x1fUL << LCD_PAL203_B04_0_Pos) /*!< LCD PAL203: B04_0 Mask */ -#define LCD_PAL203_I0_Pos 15 /*!< LCD PAL203: I0 Position */ -#define LCD_PAL203_I0_Msk (0x01UL << LCD_PAL203_I0_Pos) /*!< LCD PAL203: I0 Mask */ -#define LCD_PAL203_R14_0_Pos 16 /*!< LCD PAL203: R14_0 Position */ -#define LCD_PAL203_R14_0_Msk (0x1fUL << LCD_PAL203_R14_0_Pos) /*!< LCD PAL203: R14_0 Mask */ -#define LCD_PAL203_G14_0_Pos 21 /*!< LCD PAL203: G14_0 Position */ -#define LCD_PAL203_G14_0_Msk (0x1fUL << LCD_PAL203_G14_0_Pos) /*!< LCD PAL203: G14_0 Mask */ -#define LCD_PAL203_B14_0_Pos 26 /*!< LCD PAL203: B14_0 Position */ -#define LCD_PAL203_B14_0_Msk (0x1fUL << LCD_PAL203_B14_0_Pos) /*!< LCD PAL203: B14_0 Mask */ -#define LCD_PAL203_I1_Pos 31 /*!< LCD PAL203: I1 Position */ -#define LCD_PAL203_I1_Msk (0x01UL << LCD_PAL203_I1_Pos) /*!< LCD PAL203: I1 Mask */ - -// --------------------------------------- LCD_PAL204 ------------------------------------------- -#define LCD_PAL204_R04_0_Pos 0 /*!< LCD PAL204: R04_0 Position */ -#define LCD_PAL204_R04_0_Msk (0x1fUL << LCD_PAL204_R04_0_Pos) /*!< LCD PAL204: R04_0 Mask */ -#define LCD_PAL204_G04_0_Pos 5 /*!< LCD PAL204: G04_0 Position */ -#define LCD_PAL204_G04_0_Msk (0x1fUL << LCD_PAL204_G04_0_Pos) /*!< LCD PAL204: G04_0 Mask */ -#define LCD_PAL204_B04_0_Pos 10 /*!< LCD PAL204: B04_0 Position */ -#define LCD_PAL204_B04_0_Msk (0x1fUL << LCD_PAL204_B04_0_Pos) /*!< LCD PAL204: B04_0 Mask */ -#define LCD_PAL204_I0_Pos 15 /*!< LCD PAL204: I0 Position */ -#define LCD_PAL204_I0_Msk (0x01UL << LCD_PAL204_I0_Pos) /*!< LCD PAL204: I0 Mask */ -#define LCD_PAL204_R14_0_Pos 16 /*!< LCD PAL204: R14_0 Position */ -#define LCD_PAL204_R14_0_Msk (0x1fUL << LCD_PAL204_R14_0_Pos) /*!< LCD PAL204: R14_0 Mask */ -#define LCD_PAL204_G14_0_Pos 21 /*!< LCD PAL204: G14_0 Position */ -#define LCD_PAL204_G14_0_Msk (0x1fUL << LCD_PAL204_G14_0_Pos) /*!< LCD PAL204: G14_0 Mask */ -#define LCD_PAL204_B14_0_Pos 26 /*!< LCD PAL204: B14_0 Position */ -#define LCD_PAL204_B14_0_Msk (0x1fUL << LCD_PAL204_B14_0_Pos) /*!< LCD PAL204: B14_0 Mask */ -#define LCD_PAL204_I1_Pos 31 /*!< LCD PAL204: I1 Position */ -#define LCD_PAL204_I1_Msk (0x01UL << LCD_PAL204_I1_Pos) /*!< LCD PAL204: I1 Mask */ - -// --------------------------------------- LCD_PAL205 ------------------------------------------- -#define LCD_PAL205_R04_0_Pos 0 /*!< LCD PAL205: R04_0 Position */ -#define LCD_PAL205_R04_0_Msk (0x1fUL << LCD_PAL205_R04_0_Pos) /*!< LCD PAL205: R04_0 Mask */ -#define LCD_PAL205_G04_0_Pos 5 /*!< LCD PAL205: G04_0 Position */ -#define LCD_PAL205_G04_0_Msk (0x1fUL << LCD_PAL205_G04_0_Pos) /*!< LCD PAL205: G04_0 Mask */ -#define LCD_PAL205_B04_0_Pos 10 /*!< LCD PAL205: B04_0 Position */ -#define LCD_PAL205_B04_0_Msk (0x1fUL << LCD_PAL205_B04_0_Pos) /*!< LCD PAL205: B04_0 Mask */ -#define LCD_PAL205_I0_Pos 15 /*!< LCD PAL205: I0 Position */ -#define LCD_PAL205_I0_Msk (0x01UL << LCD_PAL205_I0_Pos) /*!< LCD PAL205: I0 Mask */ -#define LCD_PAL205_R14_0_Pos 16 /*!< LCD PAL205: R14_0 Position */ -#define LCD_PAL205_R14_0_Msk (0x1fUL << LCD_PAL205_R14_0_Pos) /*!< LCD PAL205: R14_0 Mask */ -#define LCD_PAL205_G14_0_Pos 21 /*!< LCD PAL205: G14_0 Position */ -#define LCD_PAL205_G14_0_Msk (0x1fUL << LCD_PAL205_G14_0_Pos) /*!< LCD PAL205: G14_0 Mask */ -#define LCD_PAL205_B14_0_Pos 26 /*!< LCD PAL205: B14_0 Position */ -#define LCD_PAL205_B14_0_Msk (0x1fUL << LCD_PAL205_B14_0_Pos) /*!< LCD PAL205: B14_0 Mask */ -#define LCD_PAL205_I1_Pos 31 /*!< LCD PAL205: I1 Position */ -#define LCD_PAL205_I1_Msk (0x01UL << LCD_PAL205_I1_Pos) /*!< LCD PAL205: I1 Mask */ - -// --------------------------------------- LCD_PAL206 ------------------------------------------- -#define LCD_PAL206_R04_0_Pos 0 /*!< LCD PAL206: R04_0 Position */ -#define LCD_PAL206_R04_0_Msk (0x1fUL << LCD_PAL206_R04_0_Pos) /*!< LCD PAL206: R04_0 Mask */ -#define LCD_PAL206_G04_0_Pos 5 /*!< LCD PAL206: G04_0 Position */ -#define LCD_PAL206_G04_0_Msk (0x1fUL << LCD_PAL206_G04_0_Pos) /*!< LCD PAL206: G04_0 Mask */ -#define LCD_PAL206_B04_0_Pos 10 /*!< LCD PAL206: B04_0 Position */ -#define LCD_PAL206_B04_0_Msk (0x1fUL << LCD_PAL206_B04_0_Pos) /*!< LCD PAL206: B04_0 Mask */ -#define LCD_PAL206_I0_Pos 15 /*!< LCD PAL206: I0 Position */ -#define LCD_PAL206_I0_Msk (0x01UL << LCD_PAL206_I0_Pos) /*!< LCD PAL206: I0 Mask */ -#define LCD_PAL206_R14_0_Pos 16 /*!< LCD PAL206: R14_0 Position */ -#define LCD_PAL206_R14_0_Msk (0x1fUL << LCD_PAL206_R14_0_Pos) /*!< LCD PAL206: R14_0 Mask */ -#define LCD_PAL206_G14_0_Pos 21 /*!< LCD PAL206: G14_0 Position */ -#define LCD_PAL206_G14_0_Msk (0x1fUL << LCD_PAL206_G14_0_Pos) /*!< LCD PAL206: G14_0 Mask */ -#define LCD_PAL206_B14_0_Pos 26 /*!< LCD PAL206: B14_0 Position */ -#define LCD_PAL206_B14_0_Msk (0x1fUL << LCD_PAL206_B14_0_Pos) /*!< LCD PAL206: B14_0 Mask */ -#define LCD_PAL206_I1_Pos 31 /*!< LCD PAL206: I1 Position */ -#define LCD_PAL206_I1_Msk (0x01UL << LCD_PAL206_I1_Pos) /*!< LCD PAL206: I1 Mask */ - -// --------------------------------------- LCD_PAL207 ------------------------------------------- -#define LCD_PAL207_R04_0_Pos 0 /*!< LCD PAL207: R04_0 Position */ -#define LCD_PAL207_R04_0_Msk (0x1fUL << LCD_PAL207_R04_0_Pos) /*!< LCD PAL207: R04_0 Mask */ -#define LCD_PAL207_G04_0_Pos 5 /*!< LCD PAL207: G04_0 Position */ -#define LCD_PAL207_G04_0_Msk (0x1fUL << LCD_PAL207_G04_0_Pos) /*!< LCD PAL207: G04_0 Mask */ -#define LCD_PAL207_B04_0_Pos 10 /*!< LCD PAL207: B04_0 Position */ -#define LCD_PAL207_B04_0_Msk (0x1fUL << LCD_PAL207_B04_0_Pos) /*!< LCD PAL207: B04_0 Mask */ -#define LCD_PAL207_I0_Pos 15 /*!< LCD PAL207: I0 Position */ -#define LCD_PAL207_I0_Msk (0x01UL << LCD_PAL207_I0_Pos) /*!< LCD PAL207: I0 Mask */ -#define LCD_PAL207_R14_0_Pos 16 /*!< LCD PAL207: R14_0 Position */ -#define LCD_PAL207_R14_0_Msk (0x1fUL << LCD_PAL207_R14_0_Pos) /*!< LCD PAL207: R14_0 Mask */ -#define LCD_PAL207_G14_0_Pos 21 /*!< LCD PAL207: G14_0 Position */ -#define LCD_PAL207_G14_0_Msk (0x1fUL << LCD_PAL207_G14_0_Pos) /*!< LCD PAL207: G14_0 Mask */ -#define LCD_PAL207_B14_0_Pos 26 /*!< LCD PAL207: B14_0 Position */ -#define LCD_PAL207_B14_0_Msk (0x1fUL << LCD_PAL207_B14_0_Pos) /*!< LCD PAL207: B14_0 Mask */ -#define LCD_PAL207_I1_Pos 31 /*!< LCD PAL207: I1 Position */ -#define LCD_PAL207_I1_Msk (0x01UL << LCD_PAL207_I1_Pos) /*!< LCD PAL207: I1 Mask */ - -// --------------------------------------- LCD_PAL208 ------------------------------------------- -#define LCD_PAL208_R04_0_Pos 0 /*!< LCD PAL208: R04_0 Position */ -#define LCD_PAL208_R04_0_Msk (0x1fUL << LCD_PAL208_R04_0_Pos) /*!< LCD PAL208: R04_0 Mask */ -#define LCD_PAL208_G04_0_Pos 5 /*!< LCD PAL208: G04_0 Position */ -#define LCD_PAL208_G04_0_Msk (0x1fUL << LCD_PAL208_G04_0_Pos) /*!< LCD PAL208: G04_0 Mask */ -#define LCD_PAL208_B04_0_Pos 10 /*!< LCD PAL208: B04_0 Position */ -#define LCD_PAL208_B04_0_Msk (0x1fUL << LCD_PAL208_B04_0_Pos) /*!< LCD PAL208: B04_0 Mask */ -#define LCD_PAL208_I0_Pos 15 /*!< LCD PAL208: I0 Position */ -#define LCD_PAL208_I0_Msk (0x01UL << LCD_PAL208_I0_Pos) /*!< LCD PAL208: I0 Mask */ -#define LCD_PAL208_R14_0_Pos 16 /*!< LCD PAL208: R14_0 Position */ -#define LCD_PAL208_R14_0_Msk (0x1fUL << LCD_PAL208_R14_0_Pos) /*!< LCD PAL208: R14_0 Mask */ -#define LCD_PAL208_G14_0_Pos 21 /*!< LCD PAL208: G14_0 Position */ -#define LCD_PAL208_G14_0_Msk (0x1fUL << LCD_PAL208_G14_0_Pos) /*!< LCD PAL208: G14_0 Mask */ -#define LCD_PAL208_B14_0_Pos 26 /*!< LCD PAL208: B14_0 Position */ -#define LCD_PAL208_B14_0_Msk (0x1fUL << LCD_PAL208_B14_0_Pos) /*!< LCD PAL208: B14_0 Mask */ -#define LCD_PAL208_I1_Pos 31 /*!< LCD PAL208: I1 Position */ -#define LCD_PAL208_I1_Msk (0x01UL << LCD_PAL208_I1_Pos) /*!< LCD PAL208: I1 Mask */ - -// --------------------------------------- LCD_PAL209 ------------------------------------------- -#define LCD_PAL209_R04_0_Pos 0 /*!< LCD PAL209: R04_0 Position */ -#define LCD_PAL209_R04_0_Msk (0x1fUL << LCD_PAL209_R04_0_Pos) /*!< LCD PAL209: R04_0 Mask */ -#define LCD_PAL209_G04_0_Pos 5 /*!< LCD PAL209: G04_0 Position */ -#define LCD_PAL209_G04_0_Msk (0x1fUL << LCD_PAL209_G04_0_Pos) /*!< LCD PAL209: G04_0 Mask */ -#define LCD_PAL209_B04_0_Pos 10 /*!< LCD PAL209: B04_0 Position */ -#define LCD_PAL209_B04_0_Msk (0x1fUL << LCD_PAL209_B04_0_Pos) /*!< LCD PAL209: B04_0 Mask */ -#define LCD_PAL209_I0_Pos 15 /*!< LCD PAL209: I0 Position */ -#define LCD_PAL209_I0_Msk (0x01UL << LCD_PAL209_I0_Pos) /*!< LCD PAL209: I0 Mask */ -#define LCD_PAL209_R14_0_Pos 16 /*!< LCD PAL209: R14_0 Position */ -#define LCD_PAL209_R14_0_Msk (0x1fUL << LCD_PAL209_R14_0_Pos) /*!< LCD PAL209: R14_0 Mask */ -#define LCD_PAL209_G14_0_Pos 21 /*!< LCD PAL209: G14_0 Position */ -#define LCD_PAL209_G14_0_Msk (0x1fUL << LCD_PAL209_G14_0_Pos) /*!< LCD PAL209: G14_0 Mask */ -#define LCD_PAL209_B14_0_Pos 26 /*!< LCD PAL209: B14_0 Position */ -#define LCD_PAL209_B14_0_Msk (0x1fUL << LCD_PAL209_B14_0_Pos) /*!< LCD PAL209: B14_0 Mask */ -#define LCD_PAL209_I1_Pos 31 /*!< LCD PAL209: I1 Position */ -#define LCD_PAL209_I1_Msk (0x01UL << LCD_PAL209_I1_Pos) /*!< LCD PAL209: I1 Mask */ - -// --------------------------------------- LCD_PAL210 ------------------------------------------- -#define LCD_PAL210_R04_0_Pos 0 /*!< LCD PAL210: R04_0 Position */ -#define LCD_PAL210_R04_0_Msk (0x1fUL << LCD_PAL210_R04_0_Pos) /*!< LCD PAL210: R04_0 Mask */ -#define LCD_PAL210_G04_0_Pos 5 /*!< LCD PAL210: G04_0 Position */ -#define LCD_PAL210_G04_0_Msk (0x1fUL << LCD_PAL210_G04_0_Pos) /*!< LCD PAL210: G04_0 Mask */ -#define LCD_PAL210_B04_0_Pos 10 /*!< LCD PAL210: B04_0 Position */ -#define LCD_PAL210_B04_0_Msk (0x1fUL << LCD_PAL210_B04_0_Pos) /*!< LCD PAL210: B04_0 Mask */ -#define LCD_PAL210_I0_Pos 15 /*!< LCD PAL210: I0 Position */ -#define LCD_PAL210_I0_Msk (0x01UL << LCD_PAL210_I0_Pos) /*!< LCD PAL210: I0 Mask */ -#define LCD_PAL210_R14_0_Pos 16 /*!< LCD PAL210: R14_0 Position */ -#define LCD_PAL210_R14_0_Msk (0x1fUL << LCD_PAL210_R14_0_Pos) /*!< LCD PAL210: R14_0 Mask */ -#define LCD_PAL210_G14_0_Pos 21 /*!< LCD PAL210: G14_0 Position */ -#define LCD_PAL210_G14_0_Msk (0x1fUL << LCD_PAL210_G14_0_Pos) /*!< LCD PAL210: G14_0 Mask */ -#define LCD_PAL210_B14_0_Pos 26 /*!< LCD PAL210: B14_0 Position */ -#define LCD_PAL210_B14_0_Msk (0x1fUL << LCD_PAL210_B14_0_Pos) /*!< LCD PAL210: B14_0 Mask */ -#define LCD_PAL210_I1_Pos 31 /*!< LCD PAL210: I1 Position */ -#define LCD_PAL210_I1_Msk (0x01UL << LCD_PAL210_I1_Pos) /*!< LCD PAL210: I1 Mask */ - -// --------------------------------------- LCD_PAL211 ------------------------------------------- -#define LCD_PAL211_R04_0_Pos 0 /*!< LCD PAL211: R04_0 Position */ -#define LCD_PAL211_R04_0_Msk (0x1fUL << LCD_PAL211_R04_0_Pos) /*!< LCD PAL211: R04_0 Mask */ -#define LCD_PAL211_G04_0_Pos 5 /*!< LCD PAL211: G04_0 Position */ -#define LCD_PAL211_G04_0_Msk (0x1fUL << LCD_PAL211_G04_0_Pos) /*!< LCD PAL211: G04_0 Mask */ -#define LCD_PAL211_B04_0_Pos 10 /*!< LCD PAL211: B04_0 Position */ -#define LCD_PAL211_B04_0_Msk (0x1fUL << LCD_PAL211_B04_0_Pos) /*!< LCD PAL211: B04_0 Mask */ -#define LCD_PAL211_I0_Pos 15 /*!< LCD PAL211: I0 Position */ -#define LCD_PAL211_I0_Msk (0x01UL << LCD_PAL211_I0_Pos) /*!< LCD PAL211: I0 Mask */ -#define LCD_PAL211_R14_0_Pos 16 /*!< LCD PAL211: R14_0 Position */ -#define LCD_PAL211_R14_0_Msk (0x1fUL << LCD_PAL211_R14_0_Pos) /*!< LCD PAL211: R14_0 Mask */ -#define LCD_PAL211_G14_0_Pos 21 /*!< LCD PAL211: G14_0 Position */ -#define LCD_PAL211_G14_0_Msk (0x1fUL << LCD_PAL211_G14_0_Pos) /*!< LCD PAL211: G14_0 Mask */ -#define LCD_PAL211_B14_0_Pos 26 /*!< LCD PAL211: B14_0 Position */ -#define LCD_PAL211_B14_0_Msk (0x1fUL << LCD_PAL211_B14_0_Pos) /*!< LCD PAL211: B14_0 Mask */ -#define LCD_PAL211_I1_Pos 31 /*!< LCD PAL211: I1 Position */ -#define LCD_PAL211_I1_Msk (0x01UL << LCD_PAL211_I1_Pos) /*!< LCD PAL211: I1 Mask */ - -// --------------------------------------- LCD_PAL212 ------------------------------------------- -#define LCD_PAL212_R04_0_Pos 0 /*!< LCD PAL212: R04_0 Position */ -#define LCD_PAL212_R04_0_Msk (0x1fUL << LCD_PAL212_R04_0_Pos) /*!< LCD PAL212: R04_0 Mask */ -#define LCD_PAL212_G04_0_Pos 5 /*!< LCD PAL212: G04_0 Position */ -#define LCD_PAL212_G04_0_Msk (0x1fUL << LCD_PAL212_G04_0_Pos) /*!< LCD PAL212: G04_0 Mask */ -#define LCD_PAL212_B04_0_Pos 10 /*!< LCD PAL212: B04_0 Position */ -#define LCD_PAL212_B04_0_Msk (0x1fUL << LCD_PAL212_B04_0_Pos) /*!< LCD PAL212: B04_0 Mask */ -#define LCD_PAL212_I0_Pos 15 /*!< LCD PAL212: I0 Position */ -#define LCD_PAL212_I0_Msk (0x01UL << LCD_PAL212_I0_Pos) /*!< LCD PAL212: I0 Mask */ -#define LCD_PAL212_R14_0_Pos 16 /*!< LCD PAL212: R14_0 Position */ -#define LCD_PAL212_R14_0_Msk (0x1fUL << LCD_PAL212_R14_0_Pos) /*!< LCD PAL212: R14_0 Mask */ -#define LCD_PAL212_G14_0_Pos 21 /*!< LCD PAL212: G14_0 Position */ -#define LCD_PAL212_G14_0_Msk (0x1fUL << LCD_PAL212_G14_0_Pos) /*!< LCD PAL212: G14_0 Mask */ -#define LCD_PAL212_B14_0_Pos 26 /*!< LCD PAL212: B14_0 Position */ -#define LCD_PAL212_B14_0_Msk (0x1fUL << LCD_PAL212_B14_0_Pos) /*!< LCD PAL212: B14_0 Mask */ -#define LCD_PAL212_I1_Pos 31 /*!< LCD PAL212: I1 Position */ -#define LCD_PAL212_I1_Msk (0x01UL << LCD_PAL212_I1_Pos) /*!< LCD PAL212: I1 Mask */ - -// --------------------------------------- LCD_PAL213 ------------------------------------------- -#define LCD_PAL213_R04_0_Pos 0 /*!< LCD PAL213: R04_0 Position */ -#define LCD_PAL213_R04_0_Msk (0x1fUL << LCD_PAL213_R04_0_Pos) /*!< LCD PAL213: R04_0 Mask */ -#define LCD_PAL213_G04_0_Pos 5 /*!< LCD PAL213: G04_0 Position */ -#define LCD_PAL213_G04_0_Msk (0x1fUL << LCD_PAL213_G04_0_Pos) /*!< LCD PAL213: G04_0 Mask */ -#define LCD_PAL213_B04_0_Pos 10 /*!< LCD PAL213: B04_0 Position */ -#define LCD_PAL213_B04_0_Msk (0x1fUL << LCD_PAL213_B04_0_Pos) /*!< LCD PAL213: B04_0 Mask */ -#define LCD_PAL213_I0_Pos 15 /*!< LCD PAL213: I0 Position */ -#define LCD_PAL213_I0_Msk (0x01UL << LCD_PAL213_I0_Pos) /*!< LCD PAL213: I0 Mask */ -#define LCD_PAL213_R14_0_Pos 16 /*!< LCD PAL213: R14_0 Position */ -#define LCD_PAL213_R14_0_Msk (0x1fUL << LCD_PAL213_R14_0_Pos) /*!< LCD PAL213: R14_0 Mask */ -#define LCD_PAL213_G14_0_Pos 21 /*!< LCD PAL213: G14_0 Position */ -#define LCD_PAL213_G14_0_Msk (0x1fUL << LCD_PAL213_G14_0_Pos) /*!< LCD PAL213: G14_0 Mask */ -#define LCD_PAL213_B14_0_Pos 26 /*!< LCD PAL213: B14_0 Position */ -#define LCD_PAL213_B14_0_Msk (0x1fUL << LCD_PAL213_B14_0_Pos) /*!< LCD PAL213: B14_0 Mask */ -#define LCD_PAL213_I1_Pos 31 /*!< LCD PAL213: I1 Position */ -#define LCD_PAL213_I1_Msk (0x01UL << LCD_PAL213_I1_Pos) /*!< LCD PAL213: I1 Mask */ - -// --------------------------------------- LCD_PAL214 ------------------------------------------- -#define LCD_PAL214_R04_0_Pos 0 /*!< LCD PAL214: R04_0 Position */ -#define LCD_PAL214_R04_0_Msk (0x1fUL << LCD_PAL214_R04_0_Pos) /*!< LCD PAL214: R04_0 Mask */ -#define LCD_PAL214_G04_0_Pos 5 /*!< LCD PAL214: G04_0 Position */ -#define LCD_PAL214_G04_0_Msk (0x1fUL << LCD_PAL214_G04_0_Pos) /*!< LCD PAL214: G04_0 Mask */ -#define LCD_PAL214_B04_0_Pos 10 /*!< LCD PAL214: B04_0 Position */ -#define LCD_PAL214_B04_0_Msk (0x1fUL << LCD_PAL214_B04_0_Pos) /*!< LCD PAL214: B04_0 Mask */ -#define LCD_PAL214_I0_Pos 15 /*!< LCD PAL214: I0 Position */ -#define LCD_PAL214_I0_Msk (0x01UL << LCD_PAL214_I0_Pos) /*!< LCD PAL214: I0 Mask */ -#define LCD_PAL214_R14_0_Pos 16 /*!< LCD PAL214: R14_0 Position */ -#define LCD_PAL214_R14_0_Msk (0x1fUL << LCD_PAL214_R14_0_Pos) /*!< LCD PAL214: R14_0 Mask */ -#define LCD_PAL214_G14_0_Pos 21 /*!< LCD PAL214: G14_0 Position */ -#define LCD_PAL214_G14_0_Msk (0x1fUL << LCD_PAL214_G14_0_Pos) /*!< LCD PAL214: G14_0 Mask */ -#define LCD_PAL214_B14_0_Pos 26 /*!< LCD PAL214: B14_0 Position */ -#define LCD_PAL214_B14_0_Msk (0x1fUL << LCD_PAL214_B14_0_Pos) /*!< LCD PAL214: B14_0 Mask */ -#define LCD_PAL214_I1_Pos 31 /*!< LCD PAL214: I1 Position */ -#define LCD_PAL214_I1_Msk (0x01UL << LCD_PAL214_I1_Pos) /*!< LCD PAL214: I1 Mask */ - -// --------------------------------------- LCD_PAL215 ------------------------------------------- -#define LCD_PAL215_R04_0_Pos 0 /*!< LCD PAL215: R04_0 Position */ -#define LCD_PAL215_R04_0_Msk (0x1fUL << LCD_PAL215_R04_0_Pos) /*!< LCD PAL215: R04_0 Mask */ -#define LCD_PAL215_G04_0_Pos 5 /*!< LCD PAL215: G04_0 Position */ -#define LCD_PAL215_G04_0_Msk (0x1fUL << LCD_PAL215_G04_0_Pos) /*!< LCD PAL215: G04_0 Mask */ -#define LCD_PAL215_B04_0_Pos 10 /*!< LCD PAL215: B04_0 Position */ -#define LCD_PAL215_B04_0_Msk (0x1fUL << LCD_PAL215_B04_0_Pos) /*!< LCD PAL215: B04_0 Mask */ -#define LCD_PAL215_I0_Pos 15 /*!< LCD PAL215: I0 Position */ -#define LCD_PAL215_I0_Msk (0x01UL << LCD_PAL215_I0_Pos) /*!< LCD PAL215: I0 Mask */ -#define LCD_PAL215_R14_0_Pos 16 /*!< LCD PAL215: R14_0 Position */ -#define LCD_PAL215_R14_0_Msk (0x1fUL << LCD_PAL215_R14_0_Pos) /*!< LCD PAL215: R14_0 Mask */ -#define LCD_PAL215_G14_0_Pos 21 /*!< LCD PAL215: G14_0 Position */ -#define LCD_PAL215_G14_0_Msk (0x1fUL << LCD_PAL215_G14_0_Pos) /*!< LCD PAL215: G14_0 Mask */ -#define LCD_PAL215_B14_0_Pos 26 /*!< LCD PAL215: B14_0 Position */ -#define LCD_PAL215_B14_0_Msk (0x1fUL << LCD_PAL215_B14_0_Pos) /*!< LCD PAL215: B14_0 Mask */ -#define LCD_PAL215_I1_Pos 31 /*!< LCD PAL215: I1 Position */ -#define LCD_PAL215_I1_Msk (0x01UL << LCD_PAL215_I1_Pos) /*!< LCD PAL215: I1 Mask */ - -// --------------------------------------- LCD_PAL216 ------------------------------------------- -#define LCD_PAL216_R04_0_Pos 0 /*!< LCD PAL216: R04_0 Position */ -#define LCD_PAL216_R04_0_Msk (0x1fUL << LCD_PAL216_R04_0_Pos) /*!< LCD PAL216: R04_0 Mask */ -#define LCD_PAL216_G04_0_Pos 5 /*!< LCD PAL216: G04_0 Position */ -#define LCD_PAL216_G04_0_Msk (0x1fUL << LCD_PAL216_G04_0_Pos) /*!< LCD PAL216: G04_0 Mask */ -#define LCD_PAL216_B04_0_Pos 10 /*!< LCD PAL216: B04_0 Position */ -#define LCD_PAL216_B04_0_Msk (0x1fUL << LCD_PAL216_B04_0_Pos) /*!< LCD PAL216: B04_0 Mask */ -#define LCD_PAL216_I0_Pos 15 /*!< LCD PAL216: I0 Position */ -#define LCD_PAL216_I0_Msk (0x01UL << LCD_PAL216_I0_Pos) /*!< LCD PAL216: I0 Mask */ -#define LCD_PAL216_R14_0_Pos 16 /*!< LCD PAL216: R14_0 Position */ -#define LCD_PAL216_R14_0_Msk (0x1fUL << LCD_PAL216_R14_0_Pos) /*!< LCD PAL216: R14_0 Mask */ -#define LCD_PAL216_G14_0_Pos 21 /*!< LCD PAL216: G14_0 Position */ -#define LCD_PAL216_G14_0_Msk (0x1fUL << LCD_PAL216_G14_0_Pos) /*!< LCD PAL216: G14_0 Mask */ -#define LCD_PAL216_B14_0_Pos 26 /*!< LCD PAL216: B14_0 Position */ -#define LCD_PAL216_B14_0_Msk (0x1fUL << LCD_PAL216_B14_0_Pos) /*!< LCD PAL216: B14_0 Mask */ -#define LCD_PAL216_I1_Pos 31 /*!< LCD PAL216: I1 Position */ -#define LCD_PAL216_I1_Msk (0x01UL << LCD_PAL216_I1_Pos) /*!< LCD PAL216: I1 Mask */ - -// --------------------------------------- LCD_PAL217 ------------------------------------------- -#define LCD_PAL217_R04_0_Pos 0 /*!< LCD PAL217: R04_0 Position */ -#define LCD_PAL217_R04_0_Msk (0x1fUL << LCD_PAL217_R04_0_Pos) /*!< LCD PAL217: R04_0 Mask */ -#define LCD_PAL217_G04_0_Pos 5 /*!< LCD PAL217: G04_0 Position */ -#define LCD_PAL217_G04_0_Msk (0x1fUL << LCD_PAL217_G04_0_Pos) /*!< LCD PAL217: G04_0 Mask */ -#define LCD_PAL217_B04_0_Pos 10 /*!< LCD PAL217: B04_0 Position */ -#define LCD_PAL217_B04_0_Msk (0x1fUL << LCD_PAL217_B04_0_Pos) /*!< LCD PAL217: B04_0 Mask */ -#define LCD_PAL217_I0_Pos 15 /*!< LCD PAL217: I0 Position */ -#define LCD_PAL217_I0_Msk (0x01UL << LCD_PAL217_I0_Pos) /*!< LCD PAL217: I0 Mask */ -#define LCD_PAL217_R14_0_Pos 16 /*!< LCD PAL217: R14_0 Position */ -#define LCD_PAL217_R14_0_Msk (0x1fUL << LCD_PAL217_R14_0_Pos) /*!< LCD PAL217: R14_0 Mask */ -#define LCD_PAL217_G14_0_Pos 21 /*!< LCD PAL217: G14_0 Position */ -#define LCD_PAL217_G14_0_Msk (0x1fUL << LCD_PAL217_G14_0_Pos) /*!< LCD PAL217: G14_0 Mask */ -#define LCD_PAL217_B14_0_Pos 26 /*!< LCD PAL217: B14_0 Position */ -#define LCD_PAL217_B14_0_Msk (0x1fUL << LCD_PAL217_B14_0_Pos) /*!< LCD PAL217: B14_0 Mask */ -#define LCD_PAL217_I1_Pos 31 /*!< LCD PAL217: I1 Position */ -#define LCD_PAL217_I1_Msk (0x01UL << LCD_PAL217_I1_Pos) /*!< LCD PAL217: I1 Mask */ - -// --------------------------------------- LCD_PAL218 ------------------------------------------- -#define LCD_PAL218_R04_0_Pos 0 /*!< LCD PAL218: R04_0 Position */ -#define LCD_PAL218_R04_0_Msk (0x1fUL << LCD_PAL218_R04_0_Pos) /*!< LCD PAL218: R04_0 Mask */ -#define LCD_PAL218_G04_0_Pos 5 /*!< LCD PAL218: G04_0 Position */ -#define LCD_PAL218_G04_0_Msk (0x1fUL << LCD_PAL218_G04_0_Pos) /*!< LCD PAL218: G04_0 Mask */ -#define LCD_PAL218_B04_0_Pos 10 /*!< LCD PAL218: B04_0 Position */ -#define LCD_PAL218_B04_0_Msk (0x1fUL << LCD_PAL218_B04_0_Pos) /*!< LCD PAL218: B04_0 Mask */ -#define LCD_PAL218_I0_Pos 15 /*!< LCD PAL218: I0 Position */ -#define LCD_PAL218_I0_Msk (0x01UL << LCD_PAL218_I0_Pos) /*!< LCD PAL218: I0 Mask */ -#define LCD_PAL218_R14_0_Pos 16 /*!< LCD PAL218: R14_0 Position */ -#define LCD_PAL218_R14_0_Msk (0x1fUL << LCD_PAL218_R14_0_Pos) /*!< LCD PAL218: R14_0 Mask */ -#define LCD_PAL218_G14_0_Pos 21 /*!< LCD PAL218: G14_0 Position */ -#define LCD_PAL218_G14_0_Msk (0x1fUL << LCD_PAL218_G14_0_Pos) /*!< LCD PAL218: G14_0 Mask */ -#define LCD_PAL218_B14_0_Pos 26 /*!< LCD PAL218: B14_0 Position */ -#define LCD_PAL218_B14_0_Msk (0x1fUL << LCD_PAL218_B14_0_Pos) /*!< LCD PAL218: B14_0 Mask */ -#define LCD_PAL218_I1_Pos 31 /*!< LCD PAL218: I1 Position */ -#define LCD_PAL218_I1_Msk (0x01UL << LCD_PAL218_I1_Pos) /*!< LCD PAL218: I1 Mask */ - -// --------------------------------------- LCD_PAL219 ------------------------------------------- -#define LCD_PAL219_R04_0_Pos 0 /*!< LCD PAL219: R04_0 Position */ -#define LCD_PAL219_R04_0_Msk (0x1fUL << LCD_PAL219_R04_0_Pos) /*!< LCD PAL219: R04_0 Mask */ -#define LCD_PAL219_G04_0_Pos 5 /*!< LCD PAL219: G04_0 Position */ -#define LCD_PAL219_G04_0_Msk (0x1fUL << LCD_PAL219_G04_0_Pos) /*!< LCD PAL219: G04_0 Mask */ -#define LCD_PAL219_B04_0_Pos 10 /*!< LCD PAL219: B04_0 Position */ -#define LCD_PAL219_B04_0_Msk (0x1fUL << LCD_PAL219_B04_0_Pos) /*!< LCD PAL219: B04_0 Mask */ -#define LCD_PAL219_I0_Pos 15 /*!< LCD PAL219: I0 Position */ -#define LCD_PAL219_I0_Msk (0x01UL << LCD_PAL219_I0_Pos) /*!< LCD PAL219: I0 Mask */ -#define LCD_PAL219_R14_0_Pos 16 /*!< LCD PAL219: R14_0 Position */ -#define LCD_PAL219_R14_0_Msk (0x1fUL << LCD_PAL219_R14_0_Pos) /*!< LCD PAL219: R14_0 Mask */ -#define LCD_PAL219_G14_0_Pos 21 /*!< LCD PAL219: G14_0 Position */ -#define LCD_PAL219_G14_0_Msk (0x1fUL << LCD_PAL219_G14_0_Pos) /*!< LCD PAL219: G14_0 Mask */ -#define LCD_PAL219_B14_0_Pos 26 /*!< LCD PAL219: B14_0 Position */ -#define LCD_PAL219_B14_0_Msk (0x1fUL << LCD_PAL219_B14_0_Pos) /*!< LCD PAL219: B14_0 Mask */ -#define LCD_PAL219_I1_Pos 31 /*!< LCD PAL219: I1 Position */ -#define LCD_PAL219_I1_Msk (0x01UL << LCD_PAL219_I1_Pos) /*!< LCD PAL219: I1 Mask */ - -// --------------------------------------- LCD_PAL220 ------------------------------------------- -#define LCD_PAL220_R04_0_Pos 0 /*!< LCD PAL220: R04_0 Position */ -#define LCD_PAL220_R04_0_Msk (0x1fUL << LCD_PAL220_R04_0_Pos) /*!< LCD PAL220: R04_0 Mask */ -#define LCD_PAL220_G04_0_Pos 5 /*!< LCD PAL220: G04_0 Position */ -#define LCD_PAL220_G04_0_Msk (0x1fUL << LCD_PAL220_G04_0_Pos) /*!< LCD PAL220: G04_0 Mask */ -#define LCD_PAL220_B04_0_Pos 10 /*!< LCD PAL220: B04_0 Position */ -#define LCD_PAL220_B04_0_Msk (0x1fUL << LCD_PAL220_B04_0_Pos) /*!< LCD PAL220: B04_0 Mask */ -#define LCD_PAL220_I0_Pos 15 /*!< LCD PAL220: I0 Position */ -#define LCD_PAL220_I0_Msk (0x01UL << LCD_PAL220_I0_Pos) /*!< LCD PAL220: I0 Mask */ -#define LCD_PAL220_R14_0_Pos 16 /*!< LCD PAL220: R14_0 Position */ -#define LCD_PAL220_R14_0_Msk (0x1fUL << LCD_PAL220_R14_0_Pos) /*!< LCD PAL220: R14_0 Mask */ -#define LCD_PAL220_G14_0_Pos 21 /*!< LCD PAL220: G14_0 Position */ -#define LCD_PAL220_G14_0_Msk (0x1fUL << LCD_PAL220_G14_0_Pos) /*!< LCD PAL220: G14_0 Mask */ -#define LCD_PAL220_B14_0_Pos 26 /*!< LCD PAL220: B14_0 Position */ -#define LCD_PAL220_B14_0_Msk (0x1fUL << LCD_PAL220_B14_0_Pos) /*!< LCD PAL220: B14_0 Mask */ -#define LCD_PAL220_I1_Pos 31 /*!< LCD PAL220: I1 Position */ -#define LCD_PAL220_I1_Msk (0x01UL << LCD_PAL220_I1_Pos) /*!< LCD PAL220: I1 Mask */ - -// --------------------------------------- LCD_PAL221 ------------------------------------------- -#define LCD_PAL221_R04_0_Pos 0 /*!< LCD PAL221: R04_0 Position */ -#define LCD_PAL221_R04_0_Msk (0x1fUL << LCD_PAL221_R04_0_Pos) /*!< LCD PAL221: R04_0 Mask */ -#define LCD_PAL221_G04_0_Pos 5 /*!< LCD PAL221: G04_0 Position */ -#define LCD_PAL221_G04_0_Msk (0x1fUL << LCD_PAL221_G04_0_Pos) /*!< LCD PAL221: G04_0 Mask */ -#define LCD_PAL221_B04_0_Pos 10 /*!< LCD PAL221: B04_0 Position */ -#define LCD_PAL221_B04_0_Msk (0x1fUL << LCD_PAL221_B04_0_Pos) /*!< LCD PAL221: B04_0 Mask */ -#define LCD_PAL221_I0_Pos 15 /*!< LCD PAL221: I0 Position */ -#define LCD_PAL221_I0_Msk (0x01UL << LCD_PAL221_I0_Pos) /*!< LCD PAL221: I0 Mask */ -#define LCD_PAL221_R14_0_Pos 16 /*!< LCD PAL221: R14_0 Position */ -#define LCD_PAL221_R14_0_Msk (0x1fUL << LCD_PAL221_R14_0_Pos) /*!< LCD PAL221: R14_0 Mask */ -#define LCD_PAL221_G14_0_Pos 21 /*!< LCD PAL221: G14_0 Position */ -#define LCD_PAL221_G14_0_Msk (0x1fUL << LCD_PAL221_G14_0_Pos) /*!< LCD PAL221: G14_0 Mask */ -#define LCD_PAL221_B14_0_Pos 26 /*!< LCD PAL221: B14_0 Position */ -#define LCD_PAL221_B14_0_Msk (0x1fUL << LCD_PAL221_B14_0_Pos) /*!< LCD PAL221: B14_0 Mask */ -#define LCD_PAL221_I1_Pos 31 /*!< LCD PAL221: I1 Position */ -#define LCD_PAL221_I1_Msk (0x01UL << LCD_PAL221_I1_Pos) /*!< LCD PAL221: I1 Mask */ - -// --------------------------------------- LCD_PAL222 ------------------------------------------- -#define LCD_PAL222_R04_0_Pos 0 /*!< LCD PAL222: R04_0 Position */ -#define LCD_PAL222_R04_0_Msk (0x1fUL << LCD_PAL222_R04_0_Pos) /*!< LCD PAL222: R04_0 Mask */ -#define LCD_PAL222_G04_0_Pos 5 /*!< LCD PAL222: G04_0 Position */ -#define LCD_PAL222_G04_0_Msk (0x1fUL << LCD_PAL222_G04_0_Pos) /*!< LCD PAL222: G04_0 Mask */ -#define LCD_PAL222_B04_0_Pos 10 /*!< LCD PAL222: B04_0 Position */ -#define LCD_PAL222_B04_0_Msk (0x1fUL << LCD_PAL222_B04_0_Pos) /*!< LCD PAL222: B04_0 Mask */ -#define LCD_PAL222_I0_Pos 15 /*!< LCD PAL222: I0 Position */ -#define LCD_PAL222_I0_Msk (0x01UL << LCD_PAL222_I0_Pos) /*!< LCD PAL222: I0 Mask */ -#define LCD_PAL222_R14_0_Pos 16 /*!< LCD PAL222: R14_0 Position */ -#define LCD_PAL222_R14_0_Msk (0x1fUL << LCD_PAL222_R14_0_Pos) /*!< LCD PAL222: R14_0 Mask */ -#define LCD_PAL222_G14_0_Pos 21 /*!< LCD PAL222: G14_0 Position */ -#define LCD_PAL222_G14_0_Msk (0x1fUL << LCD_PAL222_G14_0_Pos) /*!< LCD PAL222: G14_0 Mask */ -#define LCD_PAL222_B14_0_Pos 26 /*!< LCD PAL222: B14_0 Position */ -#define LCD_PAL222_B14_0_Msk (0x1fUL << LCD_PAL222_B14_0_Pos) /*!< LCD PAL222: B14_0 Mask */ -#define LCD_PAL222_I1_Pos 31 /*!< LCD PAL222: I1 Position */ -#define LCD_PAL222_I1_Msk (0x01UL << LCD_PAL222_I1_Pos) /*!< LCD PAL222: I1 Mask */ - -// --------------------------------------- LCD_PAL223 ------------------------------------------- -#define LCD_PAL223_R04_0_Pos 0 /*!< LCD PAL223: R04_0 Position */ -#define LCD_PAL223_R04_0_Msk (0x1fUL << LCD_PAL223_R04_0_Pos) /*!< LCD PAL223: R04_0 Mask */ -#define LCD_PAL223_G04_0_Pos 5 /*!< LCD PAL223: G04_0 Position */ -#define LCD_PAL223_G04_0_Msk (0x1fUL << LCD_PAL223_G04_0_Pos) /*!< LCD PAL223: G04_0 Mask */ -#define LCD_PAL223_B04_0_Pos 10 /*!< LCD PAL223: B04_0 Position */ -#define LCD_PAL223_B04_0_Msk (0x1fUL << LCD_PAL223_B04_0_Pos) /*!< LCD PAL223: B04_0 Mask */ -#define LCD_PAL223_I0_Pos 15 /*!< LCD PAL223: I0 Position */ -#define LCD_PAL223_I0_Msk (0x01UL << LCD_PAL223_I0_Pos) /*!< LCD PAL223: I0 Mask */ -#define LCD_PAL223_R14_0_Pos 16 /*!< LCD PAL223: R14_0 Position */ -#define LCD_PAL223_R14_0_Msk (0x1fUL << LCD_PAL223_R14_0_Pos) /*!< LCD PAL223: R14_0 Mask */ -#define LCD_PAL223_G14_0_Pos 21 /*!< LCD PAL223: G14_0 Position */ -#define LCD_PAL223_G14_0_Msk (0x1fUL << LCD_PAL223_G14_0_Pos) /*!< LCD PAL223: G14_0 Mask */ -#define LCD_PAL223_B14_0_Pos 26 /*!< LCD PAL223: B14_0 Position */ -#define LCD_PAL223_B14_0_Msk (0x1fUL << LCD_PAL223_B14_0_Pos) /*!< LCD PAL223: B14_0 Mask */ -#define LCD_PAL223_I1_Pos 31 /*!< LCD PAL223: I1 Position */ -#define LCD_PAL223_I1_Msk (0x01UL << LCD_PAL223_I1_Pos) /*!< LCD PAL223: I1 Mask */ - -// --------------------------------------- LCD_PAL224 ------------------------------------------- -#define LCD_PAL224_R04_0_Pos 0 /*!< LCD PAL224: R04_0 Position */ -#define LCD_PAL224_R04_0_Msk (0x1fUL << LCD_PAL224_R04_0_Pos) /*!< LCD PAL224: R04_0 Mask */ -#define LCD_PAL224_G04_0_Pos 5 /*!< LCD PAL224: G04_0 Position */ -#define LCD_PAL224_G04_0_Msk (0x1fUL << LCD_PAL224_G04_0_Pos) /*!< LCD PAL224: G04_0 Mask */ -#define LCD_PAL224_B04_0_Pos 10 /*!< LCD PAL224: B04_0 Position */ -#define LCD_PAL224_B04_0_Msk (0x1fUL << LCD_PAL224_B04_0_Pos) /*!< LCD PAL224: B04_0 Mask */ -#define LCD_PAL224_I0_Pos 15 /*!< LCD PAL224: I0 Position */ -#define LCD_PAL224_I0_Msk (0x01UL << LCD_PAL224_I0_Pos) /*!< LCD PAL224: I0 Mask */ -#define LCD_PAL224_R14_0_Pos 16 /*!< LCD PAL224: R14_0 Position */ -#define LCD_PAL224_R14_0_Msk (0x1fUL << LCD_PAL224_R14_0_Pos) /*!< LCD PAL224: R14_0 Mask */ -#define LCD_PAL224_G14_0_Pos 21 /*!< LCD PAL224: G14_0 Position */ -#define LCD_PAL224_G14_0_Msk (0x1fUL << LCD_PAL224_G14_0_Pos) /*!< LCD PAL224: G14_0 Mask */ -#define LCD_PAL224_B14_0_Pos 26 /*!< LCD PAL224: B14_0 Position */ -#define LCD_PAL224_B14_0_Msk (0x1fUL << LCD_PAL224_B14_0_Pos) /*!< LCD PAL224: B14_0 Mask */ -#define LCD_PAL224_I1_Pos 31 /*!< LCD PAL224: I1 Position */ -#define LCD_PAL224_I1_Msk (0x01UL << LCD_PAL224_I1_Pos) /*!< LCD PAL224: I1 Mask */ - -// --------------------------------------- LCD_PAL225 ------------------------------------------- -#define LCD_PAL225_R04_0_Pos 0 /*!< LCD PAL225: R04_0 Position */ -#define LCD_PAL225_R04_0_Msk (0x1fUL << LCD_PAL225_R04_0_Pos) /*!< LCD PAL225: R04_0 Mask */ -#define LCD_PAL225_G04_0_Pos 5 /*!< LCD PAL225: G04_0 Position */ -#define LCD_PAL225_G04_0_Msk (0x1fUL << LCD_PAL225_G04_0_Pos) /*!< LCD PAL225: G04_0 Mask */ -#define LCD_PAL225_B04_0_Pos 10 /*!< LCD PAL225: B04_0 Position */ -#define LCD_PAL225_B04_0_Msk (0x1fUL << LCD_PAL225_B04_0_Pos) /*!< LCD PAL225: B04_0 Mask */ -#define LCD_PAL225_I0_Pos 15 /*!< LCD PAL225: I0 Position */ -#define LCD_PAL225_I0_Msk (0x01UL << LCD_PAL225_I0_Pos) /*!< LCD PAL225: I0 Mask */ -#define LCD_PAL225_R14_0_Pos 16 /*!< LCD PAL225: R14_0 Position */ -#define LCD_PAL225_R14_0_Msk (0x1fUL << LCD_PAL225_R14_0_Pos) /*!< LCD PAL225: R14_0 Mask */ -#define LCD_PAL225_G14_0_Pos 21 /*!< LCD PAL225: G14_0 Position */ -#define LCD_PAL225_G14_0_Msk (0x1fUL << LCD_PAL225_G14_0_Pos) /*!< LCD PAL225: G14_0 Mask */ -#define LCD_PAL225_B14_0_Pos 26 /*!< LCD PAL225: B14_0 Position */ -#define LCD_PAL225_B14_0_Msk (0x1fUL << LCD_PAL225_B14_0_Pos) /*!< LCD PAL225: B14_0 Mask */ -#define LCD_PAL225_I1_Pos 31 /*!< LCD PAL225: I1 Position */ -#define LCD_PAL225_I1_Msk (0x01UL << LCD_PAL225_I1_Pos) /*!< LCD PAL225: I1 Mask */ - -// --------------------------------------- LCD_PAL226 ------------------------------------------- -#define LCD_PAL226_R04_0_Pos 0 /*!< LCD PAL226: R04_0 Position */ -#define LCD_PAL226_R04_0_Msk (0x1fUL << LCD_PAL226_R04_0_Pos) /*!< LCD PAL226: R04_0 Mask */ -#define LCD_PAL226_G04_0_Pos 5 /*!< LCD PAL226: G04_0 Position */ -#define LCD_PAL226_G04_0_Msk (0x1fUL << LCD_PAL226_G04_0_Pos) /*!< LCD PAL226: G04_0 Mask */ -#define LCD_PAL226_B04_0_Pos 10 /*!< LCD PAL226: B04_0 Position */ -#define LCD_PAL226_B04_0_Msk (0x1fUL << LCD_PAL226_B04_0_Pos) /*!< LCD PAL226: B04_0 Mask */ -#define LCD_PAL226_I0_Pos 15 /*!< LCD PAL226: I0 Position */ -#define LCD_PAL226_I0_Msk (0x01UL << LCD_PAL226_I0_Pos) /*!< LCD PAL226: I0 Mask */ -#define LCD_PAL226_R14_0_Pos 16 /*!< LCD PAL226: R14_0 Position */ -#define LCD_PAL226_R14_0_Msk (0x1fUL << LCD_PAL226_R14_0_Pos) /*!< LCD PAL226: R14_0 Mask */ -#define LCD_PAL226_G14_0_Pos 21 /*!< LCD PAL226: G14_0 Position */ -#define LCD_PAL226_G14_0_Msk (0x1fUL << LCD_PAL226_G14_0_Pos) /*!< LCD PAL226: G14_0 Mask */ -#define LCD_PAL226_B14_0_Pos 26 /*!< LCD PAL226: B14_0 Position */ -#define LCD_PAL226_B14_0_Msk (0x1fUL << LCD_PAL226_B14_0_Pos) /*!< LCD PAL226: B14_0 Mask */ -#define LCD_PAL226_I1_Pos 31 /*!< LCD PAL226: I1 Position */ -#define LCD_PAL226_I1_Msk (0x01UL << LCD_PAL226_I1_Pos) /*!< LCD PAL226: I1 Mask */ - -// --------------------------------------- LCD_PAL227 ------------------------------------------- -#define LCD_PAL227_R04_0_Pos 0 /*!< LCD PAL227: R04_0 Position */ -#define LCD_PAL227_R04_0_Msk (0x1fUL << LCD_PAL227_R04_0_Pos) /*!< LCD PAL227: R04_0 Mask */ -#define LCD_PAL227_G04_0_Pos 5 /*!< LCD PAL227: G04_0 Position */ -#define LCD_PAL227_G04_0_Msk (0x1fUL << LCD_PAL227_G04_0_Pos) /*!< LCD PAL227: G04_0 Mask */ -#define LCD_PAL227_B04_0_Pos 10 /*!< LCD PAL227: B04_0 Position */ -#define LCD_PAL227_B04_0_Msk (0x1fUL << LCD_PAL227_B04_0_Pos) /*!< LCD PAL227: B04_0 Mask */ -#define LCD_PAL227_I0_Pos 15 /*!< LCD PAL227: I0 Position */ -#define LCD_PAL227_I0_Msk (0x01UL << LCD_PAL227_I0_Pos) /*!< LCD PAL227: I0 Mask */ -#define LCD_PAL227_R14_0_Pos 16 /*!< LCD PAL227: R14_0 Position */ -#define LCD_PAL227_R14_0_Msk (0x1fUL << LCD_PAL227_R14_0_Pos) /*!< LCD PAL227: R14_0 Mask */ -#define LCD_PAL227_G14_0_Pos 21 /*!< LCD PAL227: G14_0 Position */ -#define LCD_PAL227_G14_0_Msk (0x1fUL << LCD_PAL227_G14_0_Pos) /*!< LCD PAL227: G14_0 Mask */ -#define LCD_PAL227_B14_0_Pos 26 /*!< LCD PAL227: B14_0 Position */ -#define LCD_PAL227_B14_0_Msk (0x1fUL << LCD_PAL227_B14_0_Pos) /*!< LCD PAL227: B14_0 Mask */ -#define LCD_PAL227_I1_Pos 31 /*!< LCD PAL227: I1 Position */ -#define LCD_PAL227_I1_Msk (0x01UL << LCD_PAL227_I1_Pos) /*!< LCD PAL227: I1 Mask */ - -// --------------------------------------- LCD_PAL228 ------------------------------------------- -#define LCD_PAL228_R04_0_Pos 0 /*!< LCD PAL228: R04_0 Position */ -#define LCD_PAL228_R04_0_Msk (0x1fUL << LCD_PAL228_R04_0_Pos) /*!< LCD PAL228: R04_0 Mask */ -#define LCD_PAL228_G04_0_Pos 5 /*!< LCD PAL228: G04_0 Position */ -#define LCD_PAL228_G04_0_Msk (0x1fUL << LCD_PAL228_G04_0_Pos) /*!< LCD PAL228: G04_0 Mask */ -#define LCD_PAL228_B04_0_Pos 10 /*!< LCD PAL228: B04_0 Position */ -#define LCD_PAL228_B04_0_Msk (0x1fUL << LCD_PAL228_B04_0_Pos) /*!< LCD PAL228: B04_0 Mask */ -#define LCD_PAL228_I0_Pos 15 /*!< LCD PAL228: I0 Position */ -#define LCD_PAL228_I0_Msk (0x01UL << LCD_PAL228_I0_Pos) /*!< LCD PAL228: I0 Mask */ -#define LCD_PAL228_R14_0_Pos 16 /*!< LCD PAL228: R14_0 Position */ -#define LCD_PAL228_R14_0_Msk (0x1fUL << LCD_PAL228_R14_0_Pos) /*!< LCD PAL228: R14_0 Mask */ -#define LCD_PAL228_G14_0_Pos 21 /*!< LCD PAL228: G14_0 Position */ -#define LCD_PAL228_G14_0_Msk (0x1fUL << LCD_PAL228_G14_0_Pos) /*!< LCD PAL228: G14_0 Mask */ -#define LCD_PAL228_B14_0_Pos 26 /*!< LCD PAL228: B14_0 Position */ -#define LCD_PAL228_B14_0_Msk (0x1fUL << LCD_PAL228_B14_0_Pos) /*!< LCD PAL228: B14_0 Mask */ -#define LCD_PAL228_I1_Pos 31 /*!< LCD PAL228: I1 Position */ -#define LCD_PAL228_I1_Msk (0x01UL << LCD_PAL228_I1_Pos) /*!< LCD PAL228: I1 Mask */ - -// --------------------------------------- LCD_PAL229 ------------------------------------------- -#define LCD_PAL229_R04_0_Pos 0 /*!< LCD PAL229: R04_0 Position */ -#define LCD_PAL229_R04_0_Msk (0x1fUL << LCD_PAL229_R04_0_Pos) /*!< LCD PAL229: R04_0 Mask */ -#define LCD_PAL229_G04_0_Pos 5 /*!< LCD PAL229: G04_0 Position */ -#define LCD_PAL229_G04_0_Msk (0x1fUL << LCD_PAL229_G04_0_Pos) /*!< LCD PAL229: G04_0 Mask */ -#define LCD_PAL229_B04_0_Pos 10 /*!< LCD PAL229: B04_0 Position */ -#define LCD_PAL229_B04_0_Msk (0x1fUL << LCD_PAL229_B04_0_Pos) /*!< LCD PAL229: B04_0 Mask */ -#define LCD_PAL229_I0_Pos 15 /*!< LCD PAL229: I0 Position */ -#define LCD_PAL229_I0_Msk (0x01UL << LCD_PAL229_I0_Pos) /*!< LCD PAL229: I0 Mask */ -#define LCD_PAL229_R14_0_Pos 16 /*!< LCD PAL229: R14_0 Position */ -#define LCD_PAL229_R14_0_Msk (0x1fUL << LCD_PAL229_R14_0_Pos) /*!< LCD PAL229: R14_0 Mask */ -#define LCD_PAL229_G14_0_Pos 21 /*!< LCD PAL229: G14_0 Position */ -#define LCD_PAL229_G14_0_Msk (0x1fUL << LCD_PAL229_G14_0_Pos) /*!< LCD PAL229: G14_0 Mask */ -#define LCD_PAL229_B14_0_Pos 26 /*!< LCD PAL229: B14_0 Position */ -#define LCD_PAL229_B14_0_Msk (0x1fUL << LCD_PAL229_B14_0_Pos) /*!< LCD PAL229: B14_0 Mask */ -#define LCD_PAL229_I1_Pos 31 /*!< LCD PAL229: I1 Position */ -#define LCD_PAL229_I1_Msk (0x01UL << LCD_PAL229_I1_Pos) /*!< LCD PAL229: I1 Mask */ - -// --------------------------------------- LCD_PAL230 ------------------------------------------- -#define LCD_PAL230_R04_0_Pos 0 /*!< LCD PAL230: R04_0 Position */ -#define LCD_PAL230_R04_0_Msk (0x1fUL << LCD_PAL230_R04_0_Pos) /*!< LCD PAL230: R04_0 Mask */ -#define LCD_PAL230_G04_0_Pos 5 /*!< LCD PAL230: G04_0 Position */ -#define LCD_PAL230_G04_0_Msk (0x1fUL << LCD_PAL230_G04_0_Pos) /*!< LCD PAL230: G04_0 Mask */ -#define LCD_PAL230_B04_0_Pos 10 /*!< LCD PAL230: B04_0 Position */ -#define LCD_PAL230_B04_0_Msk (0x1fUL << LCD_PAL230_B04_0_Pos) /*!< LCD PAL230: B04_0 Mask */ -#define LCD_PAL230_I0_Pos 15 /*!< LCD PAL230: I0 Position */ -#define LCD_PAL230_I0_Msk (0x01UL << LCD_PAL230_I0_Pos) /*!< LCD PAL230: I0 Mask */ -#define LCD_PAL230_R14_0_Pos 16 /*!< LCD PAL230: R14_0 Position */ -#define LCD_PAL230_R14_0_Msk (0x1fUL << LCD_PAL230_R14_0_Pos) /*!< LCD PAL230: R14_0 Mask */ -#define LCD_PAL230_G14_0_Pos 21 /*!< LCD PAL230: G14_0 Position */ -#define LCD_PAL230_G14_0_Msk (0x1fUL << LCD_PAL230_G14_0_Pos) /*!< LCD PAL230: G14_0 Mask */ -#define LCD_PAL230_B14_0_Pos 26 /*!< LCD PAL230: B14_0 Position */ -#define LCD_PAL230_B14_0_Msk (0x1fUL << LCD_PAL230_B14_0_Pos) /*!< LCD PAL230: B14_0 Mask */ -#define LCD_PAL230_I1_Pos 31 /*!< LCD PAL230: I1 Position */ -#define LCD_PAL230_I1_Msk (0x01UL << LCD_PAL230_I1_Pos) /*!< LCD PAL230: I1 Mask */ - -// --------------------------------------- LCD_PAL231 ------------------------------------------- -#define LCD_PAL231_R04_0_Pos 0 /*!< LCD PAL231: R04_0 Position */ -#define LCD_PAL231_R04_0_Msk (0x1fUL << LCD_PAL231_R04_0_Pos) /*!< LCD PAL231: R04_0 Mask */ -#define LCD_PAL231_G04_0_Pos 5 /*!< LCD PAL231: G04_0 Position */ -#define LCD_PAL231_G04_0_Msk (0x1fUL << LCD_PAL231_G04_0_Pos) /*!< LCD PAL231: G04_0 Mask */ -#define LCD_PAL231_B04_0_Pos 10 /*!< LCD PAL231: B04_0 Position */ -#define LCD_PAL231_B04_0_Msk (0x1fUL << LCD_PAL231_B04_0_Pos) /*!< LCD PAL231: B04_0 Mask */ -#define LCD_PAL231_I0_Pos 15 /*!< LCD PAL231: I0 Position */ -#define LCD_PAL231_I0_Msk (0x01UL << LCD_PAL231_I0_Pos) /*!< LCD PAL231: I0 Mask */ -#define LCD_PAL231_R14_0_Pos 16 /*!< LCD PAL231: R14_0 Position */ -#define LCD_PAL231_R14_0_Msk (0x1fUL << LCD_PAL231_R14_0_Pos) /*!< LCD PAL231: R14_0 Mask */ -#define LCD_PAL231_G14_0_Pos 21 /*!< LCD PAL231: G14_0 Position */ -#define LCD_PAL231_G14_0_Msk (0x1fUL << LCD_PAL231_G14_0_Pos) /*!< LCD PAL231: G14_0 Mask */ -#define LCD_PAL231_B14_0_Pos 26 /*!< LCD PAL231: B14_0 Position */ -#define LCD_PAL231_B14_0_Msk (0x1fUL << LCD_PAL231_B14_0_Pos) /*!< LCD PAL231: B14_0 Mask */ -#define LCD_PAL231_I1_Pos 31 /*!< LCD PAL231: I1 Position */ -#define LCD_PAL231_I1_Msk (0x01UL << LCD_PAL231_I1_Pos) /*!< LCD PAL231: I1 Mask */ - -// --------------------------------------- LCD_PAL232 ------------------------------------------- -#define LCD_PAL232_R04_0_Pos 0 /*!< LCD PAL232: R04_0 Position */ -#define LCD_PAL232_R04_0_Msk (0x1fUL << LCD_PAL232_R04_0_Pos) /*!< LCD PAL232: R04_0 Mask */ -#define LCD_PAL232_G04_0_Pos 5 /*!< LCD PAL232: G04_0 Position */ -#define LCD_PAL232_G04_0_Msk (0x1fUL << LCD_PAL232_G04_0_Pos) /*!< LCD PAL232: G04_0 Mask */ -#define LCD_PAL232_B04_0_Pos 10 /*!< LCD PAL232: B04_0 Position */ -#define LCD_PAL232_B04_0_Msk (0x1fUL << LCD_PAL232_B04_0_Pos) /*!< LCD PAL232: B04_0 Mask */ -#define LCD_PAL232_I0_Pos 15 /*!< LCD PAL232: I0 Position */ -#define LCD_PAL232_I0_Msk (0x01UL << LCD_PAL232_I0_Pos) /*!< LCD PAL232: I0 Mask */ -#define LCD_PAL232_R14_0_Pos 16 /*!< LCD PAL232: R14_0 Position */ -#define LCD_PAL232_R14_0_Msk (0x1fUL << LCD_PAL232_R14_0_Pos) /*!< LCD PAL232: R14_0 Mask */ -#define LCD_PAL232_G14_0_Pos 21 /*!< LCD PAL232: G14_0 Position */ -#define LCD_PAL232_G14_0_Msk (0x1fUL << LCD_PAL232_G14_0_Pos) /*!< LCD PAL232: G14_0 Mask */ -#define LCD_PAL232_B14_0_Pos 26 /*!< LCD PAL232: B14_0 Position */ -#define LCD_PAL232_B14_0_Msk (0x1fUL << LCD_PAL232_B14_0_Pos) /*!< LCD PAL232: B14_0 Mask */ -#define LCD_PAL232_I1_Pos 31 /*!< LCD PAL232: I1 Position */ -#define LCD_PAL232_I1_Msk (0x01UL << LCD_PAL232_I1_Pos) /*!< LCD PAL232: I1 Mask */ - -// --------------------------------------- LCD_PAL233 ------------------------------------------- -#define LCD_PAL233_R04_0_Pos 0 /*!< LCD PAL233: R04_0 Position */ -#define LCD_PAL233_R04_0_Msk (0x1fUL << LCD_PAL233_R04_0_Pos) /*!< LCD PAL233: R04_0 Mask */ -#define LCD_PAL233_G04_0_Pos 5 /*!< LCD PAL233: G04_0 Position */ -#define LCD_PAL233_G04_0_Msk (0x1fUL << LCD_PAL233_G04_0_Pos) /*!< LCD PAL233: G04_0 Mask */ -#define LCD_PAL233_B04_0_Pos 10 /*!< LCD PAL233: B04_0 Position */ -#define LCD_PAL233_B04_0_Msk (0x1fUL << LCD_PAL233_B04_0_Pos) /*!< LCD PAL233: B04_0 Mask */ -#define LCD_PAL233_I0_Pos 15 /*!< LCD PAL233: I0 Position */ -#define LCD_PAL233_I0_Msk (0x01UL << LCD_PAL233_I0_Pos) /*!< LCD PAL233: I0 Mask */ -#define LCD_PAL233_R14_0_Pos 16 /*!< LCD PAL233: R14_0 Position */ -#define LCD_PAL233_R14_0_Msk (0x1fUL << LCD_PAL233_R14_0_Pos) /*!< LCD PAL233: R14_0 Mask */ -#define LCD_PAL233_G14_0_Pos 21 /*!< LCD PAL233: G14_0 Position */ -#define LCD_PAL233_G14_0_Msk (0x1fUL << LCD_PAL233_G14_0_Pos) /*!< LCD PAL233: G14_0 Mask */ -#define LCD_PAL233_B14_0_Pos 26 /*!< LCD PAL233: B14_0 Position */ -#define LCD_PAL233_B14_0_Msk (0x1fUL << LCD_PAL233_B14_0_Pos) /*!< LCD PAL233: B14_0 Mask */ -#define LCD_PAL233_I1_Pos 31 /*!< LCD PAL233: I1 Position */ -#define LCD_PAL233_I1_Msk (0x01UL << LCD_PAL233_I1_Pos) /*!< LCD PAL233: I1 Mask */ - -// --------------------------------------- LCD_PAL234 ------------------------------------------- -#define LCD_PAL234_R04_0_Pos 0 /*!< LCD PAL234: R04_0 Position */ -#define LCD_PAL234_R04_0_Msk (0x1fUL << LCD_PAL234_R04_0_Pos) /*!< LCD PAL234: R04_0 Mask */ -#define LCD_PAL234_G04_0_Pos 5 /*!< LCD PAL234: G04_0 Position */ -#define LCD_PAL234_G04_0_Msk (0x1fUL << LCD_PAL234_G04_0_Pos) /*!< LCD PAL234: G04_0 Mask */ -#define LCD_PAL234_B04_0_Pos 10 /*!< LCD PAL234: B04_0 Position */ -#define LCD_PAL234_B04_0_Msk (0x1fUL << LCD_PAL234_B04_0_Pos) /*!< LCD PAL234: B04_0 Mask */ -#define LCD_PAL234_I0_Pos 15 /*!< LCD PAL234: I0 Position */ -#define LCD_PAL234_I0_Msk (0x01UL << LCD_PAL234_I0_Pos) /*!< LCD PAL234: I0 Mask */ -#define LCD_PAL234_R14_0_Pos 16 /*!< LCD PAL234: R14_0 Position */ -#define LCD_PAL234_R14_0_Msk (0x1fUL << LCD_PAL234_R14_0_Pos) /*!< LCD PAL234: R14_0 Mask */ -#define LCD_PAL234_G14_0_Pos 21 /*!< LCD PAL234: G14_0 Position */ -#define LCD_PAL234_G14_0_Msk (0x1fUL << LCD_PAL234_G14_0_Pos) /*!< LCD PAL234: G14_0 Mask */ -#define LCD_PAL234_B14_0_Pos 26 /*!< LCD PAL234: B14_0 Position */ -#define LCD_PAL234_B14_0_Msk (0x1fUL << LCD_PAL234_B14_0_Pos) /*!< LCD PAL234: B14_0 Mask */ -#define LCD_PAL234_I1_Pos 31 /*!< LCD PAL234: I1 Position */ -#define LCD_PAL234_I1_Msk (0x01UL << LCD_PAL234_I1_Pos) /*!< LCD PAL234: I1 Mask */ - -// --------------------------------------- LCD_PAL235 ------------------------------------------- -#define LCD_PAL235_R04_0_Pos 0 /*!< LCD PAL235: R04_0 Position */ -#define LCD_PAL235_R04_0_Msk (0x1fUL << LCD_PAL235_R04_0_Pos) /*!< LCD PAL235: R04_0 Mask */ -#define LCD_PAL235_G04_0_Pos 5 /*!< LCD PAL235: G04_0 Position */ -#define LCD_PAL235_G04_0_Msk (0x1fUL << LCD_PAL235_G04_0_Pos) /*!< LCD PAL235: G04_0 Mask */ -#define LCD_PAL235_B04_0_Pos 10 /*!< LCD PAL235: B04_0 Position */ -#define LCD_PAL235_B04_0_Msk (0x1fUL << LCD_PAL235_B04_0_Pos) /*!< LCD PAL235: B04_0 Mask */ -#define LCD_PAL235_I0_Pos 15 /*!< LCD PAL235: I0 Position */ -#define LCD_PAL235_I0_Msk (0x01UL << LCD_PAL235_I0_Pos) /*!< LCD PAL235: I0 Mask */ -#define LCD_PAL235_R14_0_Pos 16 /*!< LCD PAL235: R14_0 Position */ -#define LCD_PAL235_R14_0_Msk (0x1fUL << LCD_PAL235_R14_0_Pos) /*!< LCD PAL235: R14_0 Mask */ -#define LCD_PAL235_G14_0_Pos 21 /*!< LCD PAL235: G14_0 Position */ -#define LCD_PAL235_G14_0_Msk (0x1fUL << LCD_PAL235_G14_0_Pos) /*!< LCD PAL235: G14_0 Mask */ -#define LCD_PAL235_B14_0_Pos 26 /*!< LCD PAL235: B14_0 Position */ -#define LCD_PAL235_B14_0_Msk (0x1fUL << LCD_PAL235_B14_0_Pos) /*!< LCD PAL235: B14_0 Mask */ -#define LCD_PAL235_I1_Pos 31 /*!< LCD PAL235: I1 Position */ -#define LCD_PAL235_I1_Msk (0x01UL << LCD_PAL235_I1_Pos) /*!< LCD PAL235: I1 Mask */ - -// --------------------------------------- LCD_PAL236 ------------------------------------------- -#define LCD_PAL236_R04_0_Pos 0 /*!< LCD PAL236: R04_0 Position */ -#define LCD_PAL236_R04_0_Msk (0x1fUL << LCD_PAL236_R04_0_Pos) /*!< LCD PAL236: R04_0 Mask */ -#define LCD_PAL236_G04_0_Pos 5 /*!< LCD PAL236: G04_0 Position */ -#define LCD_PAL236_G04_0_Msk (0x1fUL << LCD_PAL236_G04_0_Pos) /*!< LCD PAL236: G04_0 Mask */ -#define LCD_PAL236_B04_0_Pos 10 /*!< LCD PAL236: B04_0 Position */ -#define LCD_PAL236_B04_0_Msk (0x1fUL << LCD_PAL236_B04_0_Pos) /*!< LCD PAL236: B04_0 Mask */ -#define LCD_PAL236_I0_Pos 15 /*!< LCD PAL236: I0 Position */ -#define LCD_PAL236_I0_Msk (0x01UL << LCD_PAL236_I0_Pos) /*!< LCD PAL236: I0 Mask */ -#define LCD_PAL236_R14_0_Pos 16 /*!< LCD PAL236: R14_0 Position */ -#define LCD_PAL236_R14_0_Msk (0x1fUL << LCD_PAL236_R14_0_Pos) /*!< LCD PAL236: R14_0 Mask */ -#define LCD_PAL236_G14_0_Pos 21 /*!< LCD PAL236: G14_0 Position */ -#define LCD_PAL236_G14_0_Msk (0x1fUL << LCD_PAL236_G14_0_Pos) /*!< LCD PAL236: G14_0 Mask */ -#define LCD_PAL236_B14_0_Pos 26 /*!< LCD PAL236: B14_0 Position */ -#define LCD_PAL236_B14_0_Msk (0x1fUL << LCD_PAL236_B14_0_Pos) /*!< LCD PAL236: B14_0 Mask */ -#define LCD_PAL236_I1_Pos 31 /*!< LCD PAL236: I1 Position */ -#define LCD_PAL236_I1_Msk (0x01UL << LCD_PAL236_I1_Pos) /*!< LCD PAL236: I1 Mask */ - -// --------------------------------------- LCD_PAL237 ------------------------------------------- -#define LCD_PAL237_R04_0_Pos 0 /*!< LCD PAL237: R04_0 Position */ -#define LCD_PAL237_R04_0_Msk (0x1fUL << LCD_PAL237_R04_0_Pos) /*!< LCD PAL237: R04_0 Mask */ -#define LCD_PAL237_G04_0_Pos 5 /*!< LCD PAL237: G04_0 Position */ -#define LCD_PAL237_G04_0_Msk (0x1fUL << LCD_PAL237_G04_0_Pos) /*!< LCD PAL237: G04_0 Mask */ -#define LCD_PAL237_B04_0_Pos 10 /*!< LCD PAL237: B04_0 Position */ -#define LCD_PAL237_B04_0_Msk (0x1fUL << LCD_PAL237_B04_0_Pos) /*!< LCD PAL237: B04_0 Mask */ -#define LCD_PAL237_I0_Pos 15 /*!< LCD PAL237: I0 Position */ -#define LCD_PAL237_I0_Msk (0x01UL << LCD_PAL237_I0_Pos) /*!< LCD PAL237: I0 Mask */ -#define LCD_PAL237_R14_0_Pos 16 /*!< LCD PAL237: R14_0 Position */ -#define LCD_PAL237_R14_0_Msk (0x1fUL << LCD_PAL237_R14_0_Pos) /*!< LCD PAL237: R14_0 Mask */ -#define LCD_PAL237_G14_0_Pos 21 /*!< LCD PAL237: G14_0 Position */ -#define LCD_PAL237_G14_0_Msk (0x1fUL << LCD_PAL237_G14_0_Pos) /*!< LCD PAL237: G14_0 Mask */ -#define LCD_PAL237_B14_0_Pos 26 /*!< LCD PAL237: B14_0 Position */ -#define LCD_PAL237_B14_0_Msk (0x1fUL << LCD_PAL237_B14_0_Pos) /*!< LCD PAL237: B14_0 Mask */ -#define LCD_PAL237_I1_Pos 31 /*!< LCD PAL237: I1 Position */ -#define LCD_PAL237_I1_Msk (0x01UL << LCD_PAL237_I1_Pos) /*!< LCD PAL237: I1 Mask */ - -// --------------------------------------- LCD_PAL238 ------------------------------------------- -#define LCD_PAL238_R04_0_Pos 0 /*!< LCD PAL238: R04_0 Position */ -#define LCD_PAL238_R04_0_Msk (0x1fUL << LCD_PAL238_R04_0_Pos) /*!< LCD PAL238: R04_0 Mask */ -#define LCD_PAL238_G04_0_Pos 5 /*!< LCD PAL238: G04_0 Position */ -#define LCD_PAL238_G04_0_Msk (0x1fUL << LCD_PAL238_G04_0_Pos) /*!< LCD PAL238: G04_0 Mask */ -#define LCD_PAL238_B04_0_Pos 10 /*!< LCD PAL238: B04_0 Position */ -#define LCD_PAL238_B04_0_Msk (0x1fUL << LCD_PAL238_B04_0_Pos) /*!< LCD PAL238: B04_0 Mask */ -#define LCD_PAL238_I0_Pos 15 /*!< LCD PAL238: I0 Position */ -#define LCD_PAL238_I0_Msk (0x01UL << LCD_PAL238_I0_Pos) /*!< LCD PAL238: I0 Mask */ -#define LCD_PAL238_R14_0_Pos 16 /*!< LCD PAL238: R14_0 Position */ -#define LCD_PAL238_R14_0_Msk (0x1fUL << LCD_PAL238_R14_0_Pos) /*!< LCD PAL238: R14_0 Mask */ -#define LCD_PAL238_G14_0_Pos 21 /*!< LCD PAL238: G14_0 Position */ -#define LCD_PAL238_G14_0_Msk (0x1fUL << LCD_PAL238_G14_0_Pos) /*!< LCD PAL238: G14_0 Mask */ -#define LCD_PAL238_B14_0_Pos 26 /*!< LCD PAL238: B14_0 Position */ -#define LCD_PAL238_B14_0_Msk (0x1fUL << LCD_PAL238_B14_0_Pos) /*!< LCD PAL238: B14_0 Mask */ -#define LCD_PAL238_I1_Pos 31 /*!< LCD PAL238: I1 Position */ -#define LCD_PAL238_I1_Msk (0x01UL << LCD_PAL238_I1_Pos) /*!< LCD PAL238: I1 Mask */ - -// --------------------------------------- LCD_PAL239 ------------------------------------------- -#define LCD_PAL239_R04_0_Pos 0 /*!< LCD PAL239: R04_0 Position */ -#define LCD_PAL239_R04_0_Msk (0x1fUL << LCD_PAL239_R04_0_Pos) /*!< LCD PAL239: R04_0 Mask */ -#define LCD_PAL239_G04_0_Pos 5 /*!< LCD PAL239: G04_0 Position */ -#define LCD_PAL239_G04_0_Msk (0x1fUL << LCD_PAL239_G04_0_Pos) /*!< LCD PAL239: G04_0 Mask */ -#define LCD_PAL239_B04_0_Pos 10 /*!< LCD PAL239: B04_0 Position */ -#define LCD_PAL239_B04_0_Msk (0x1fUL << LCD_PAL239_B04_0_Pos) /*!< LCD PAL239: B04_0 Mask */ -#define LCD_PAL239_I0_Pos 15 /*!< LCD PAL239: I0 Position */ -#define LCD_PAL239_I0_Msk (0x01UL << LCD_PAL239_I0_Pos) /*!< LCD PAL239: I0 Mask */ -#define LCD_PAL239_R14_0_Pos 16 /*!< LCD PAL239: R14_0 Position */ -#define LCD_PAL239_R14_0_Msk (0x1fUL << LCD_PAL239_R14_0_Pos) /*!< LCD PAL239: R14_0 Mask */ -#define LCD_PAL239_G14_0_Pos 21 /*!< LCD PAL239: G14_0 Position */ -#define LCD_PAL239_G14_0_Msk (0x1fUL << LCD_PAL239_G14_0_Pos) /*!< LCD PAL239: G14_0 Mask */ -#define LCD_PAL239_B14_0_Pos 26 /*!< LCD PAL239: B14_0 Position */ -#define LCD_PAL239_B14_0_Msk (0x1fUL << LCD_PAL239_B14_0_Pos) /*!< LCD PAL239: B14_0 Mask */ -#define LCD_PAL239_I1_Pos 31 /*!< LCD PAL239: I1 Position */ -#define LCD_PAL239_I1_Msk (0x01UL << LCD_PAL239_I1_Pos) /*!< LCD PAL239: I1 Mask */ - -// --------------------------------------- LCD_PAL240 ------------------------------------------- -#define LCD_PAL240_R04_0_Pos 0 /*!< LCD PAL240: R04_0 Position */ -#define LCD_PAL240_R04_0_Msk (0x1fUL << LCD_PAL240_R04_0_Pos) /*!< LCD PAL240: R04_0 Mask */ -#define LCD_PAL240_G04_0_Pos 5 /*!< LCD PAL240: G04_0 Position */ -#define LCD_PAL240_G04_0_Msk (0x1fUL << LCD_PAL240_G04_0_Pos) /*!< LCD PAL240: G04_0 Mask */ -#define LCD_PAL240_B04_0_Pos 10 /*!< LCD PAL240: B04_0 Position */ -#define LCD_PAL240_B04_0_Msk (0x1fUL << LCD_PAL240_B04_0_Pos) /*!< LCD PAL240: B04_0 Mask */ -#define LCD_PAL240_I0_Pos 15 /*!< LCD PAL240: I0 Position */ -#define LCD_PAL240_I0_Msk (0x01UL << LCD_PAL240_I0_Pos) /*!< LCD PAL240: I0 Mask */ -#define LCD_PAL240_R14_0_Pos 16 /*!< LCD PAL240: R14_0 Position */ -#define LCD_PAL240_R14_0_Msk (0x1fUL << LCD_PAL240_R14_0_Pos) /*!< LCD PAL240: R14_0 Mask */ -#define LCD_PAL240_G14_0_Pos 21 /*!< LCD PAL240: G14_0 Position */ -#define LCD_PAL240_G14_0_Msk (0x1fUL << LCD_PAL240_G14_0_Pos) /*!< LCD PAL240: G14_0 Mask */ -#define LCD_PAL240_B14_0_Pos 26 /*!< LCD PAL240: B14_0 Position */ -#define LCD_PAL240_B14_0_Msk (0x1fUL << LCD_PAL240_B14_0_Pos) /*!< LCD PAL240: B14_0 Mask */ -#define LCD_PAL240_I1_Pos 31 /*!< LCD PAL240: I1 Position */ -#define LCD_PAL240_I1_Msk (0x01UL << LCD_PAL240_I1_Pos) /*!< LCD PAL240: I1 Mask */ - -// --------------------------------------- LCD_PAL241 ------------------------------------------- -#define LCD_PAL241_R04_0_Pos 0 /*!< LCD PAL241: R04_0 Position */ -#define LCD_PAL241_R04_0_Msk (0x1fUL << LCD_PAL241_R04_0_Pos) /*!< LCD PAL241: R04_0 Mask */ -#define LCD_PAL241_G04_0_Pos 5 /*!< LCD PAL241: G04_0 Position */ -#define LCD_PAL241_G04_0_Msk (0x1fUL << LCD_PAL241_G04_0_Pos) /*!< LCD PAL241: G04_0 Mask */ -#define LCD_PAL241_B04_0_Pos 10 /*!< LCD PAL241: B04_0 Position */ -#define LCD_PAL241_B04_0_Msk (0x1fUL << LCD_PAL241_B04_0_Pos) /*!< LCD PAL241: B04_0 Mask */ -#define LCD_PAL241_I0_Pos 15 /*!< LCD PAL241: I0 Position */ -#define LCD_PAL241_I0_Msk (0x01UL << LCD_PAL241_I0_Pos) /*!< LCD PAL241: I0 Mask */ -#define LCD_PAL241_R14_0_Pos 16 /*!< LCD PAL241: R14_0 Position */ -#define LCD_PAL241_R14_0_Msk (0x1fUL << LCD_PAL241_R14_0_Pos) /*!< LCD PAL241: R14_0 Mask */ -#define LCD_PAL241_G14_0_Pos 21 /*!< LCD PAL241: G14_0 Position */ -#define LCD_PAL241_G14_0_Msk (0x1fUL << LCD_PAL241_G14_0_Pos) /*!< LCD PAL241: G14_0 Mask */ -#define LCD_PAL241_B14_0_Pos 26 /*!< LCD PAL241: B14_0 Position */ -#define LCD_PAL241_B14_0_Msk (0x1fUL << LCD_PAL241_B14_0_Pos) /*!< LCD PAL241: B14_0 Mask */ -#define LCD_PAL241_I1_Pos 31 /*!< LCD PAL241: I1 Position */ -#define LCD_PAL241_I1_Msk (0x01UL << LCD_PAL241_I1_Pos) /*!< LCD PAL241: I1 Mask */ - -// --------------------------------------- LCD_PAL242 ------------------------------------------- -#define LCD_PAL242_R04_0_Pos 0 /*!< LCD PAL242: R04_0 Position */ -#define LCD_PAL242_R04_0_Msk (0x1fUL << LCD_PAL242_R04_0_Pos) /*!< LCD PAL242: R04_0 Mask */ -#define LCD_PAL242_G04_0_Pos 5 /*!< LCD PAL242: G04_0 Position */ -#define LCD_PAL242_G04_0_Msk (0x1fUL << LCD_PAL242_G04_0_Pos) /*!< LCD PAL242: G04_0 Mask */ -#define LCD_PAL242_B04_0_Pos 10 /*!< LCD PAL242: B04_0 Position */ -#define LCD_PAL242_B04_0_Msk (0x1fUL << LCD_PAL242_B04_0_Pos) /*!< LCD PAL242: B04_0 Mask */ -#define LCD_PAL242_I0_Pos 15 /*!< LCD PAL242: I0 Position */ -#define LCD_PAL242_I0_Msk (0x01UL << LCD_PAL242_I0_Pos) /*!< LCD PAL242: I0 Mask */ -#define LCD_PAL242_R14_0_Pos 16 /*!< LCD PAL242: R14_0 Position */ -#define LCD_PAL242_R14_0_Msk (0x1fUL << LCD_PAL242_R14_0_Pos) /*!< LCD PAL242: R14_0 Mask */ -#define LCD_PAL242_G14_0_Pos 21 /*!< LCD PAL242: G14_0 Position */ -#define LCD_PAL242_G14_0_Msk (0x1fUL << LCD_PAL242_G14_0_Pos) /*!< LCD PAL242: G14_0 Mask */ -#define LCD_PAL242_B14_0_Pos 26 /*!< LCD PAL242: B14_0 Position */ -#define LCD_PAL242_B14_0_Msk (0x1fUL << LCD_PAL242_B14_0_Pos) /*!< LCD PAL242: B14_0 Mask */ -#define LCD_PAL242_I1_Pos 31 /*!< LCD PAL242: I1 Position */ -#define LCD_PAL242_I1_Msk (0x01UL << LCD_PAL242_I1_Pos) /*!< LCD PAL242: I1 Mask */ - -// --------------------------------------- LCD_PAL243 ------------------------------------------- -#define LCD_PAL243_R04_0_Pos 0 /*!< LCD PAL243: R04_0 Position */ -#define LCD_PAL243_R04_0_Msk (0x1fUL << LCD_PAL243_R04_0_Pos) /*!< LCD PAL243: R04_0 Mask */ -#define LCD_PAL243_G04_0_Pos 5 /*!< LCD PAL243: G04_0 Position */ -#define LCD_PAL243_G04_0_Msk (0x1fUL << LCD_PAL243_G04_0_Pos) /*!< LCD PAL243: G04_0 Mask */ -#define LCD_PAL243_B04_0_Pos 10 /*!< LCD PAL243: B04_0 Position */ -#define LCD_PAL243_B04_0_Msk (0x1fUL << LCD_PAL243_B04_0_Pos) /*!< LCD PAL243: B04_0 Mask */ -#define LCD_PAL243_I0_Pos 15 /*!< LCD PAL243: I0 Position */ -#define LCD_PAL243_I0_Msk (0x01UL << LCD_PAL243_I0_Pos) /*!< LCD PAL243: I0 Mask */ -#define LCD_PAL243_R14_0_Pos 16 /*!< LCD PAL243: R14_0 Position */ -#define LCD_PAL243_R14_0_Msk (0x1fUL << LCD_PAL243_R14_0_Pos) /*!< LCD PAL243: R14_0 Mask */ -#define LCD_PAL243_G14_0_Pos 21 /*!< LCD PAL243: G14_0 Position */ -#define LCD_PAL243_G14_0_Msk (0x1fUL << LCD_PAL243_G14_0_Pos) /*!< LCD PAL243: G14_0 Mask */ -#define LCD_PAL243_B14_0_Pos 26 /*!< LCD PAL243: B14_0 Position */ -#define LCD_PAL243_B14_0_Msk (0x1fUL << LCD_PAL243_B14_0_Pos) /*!< LCD PAL243: B14_0 Mask */ -#define LCD_PAL243_I1_Pos 31 /*!< LCD PAL243: I1 Position */ -#define LCD_PAL243_I1_Msk (0x01UL << LCD_PAL243_I1_Pos) /*!< LCD PAL243: I1 Mask */ - -// --------------------------------------- LCD_PAL244 ------------------------------------------- -#define LCD_PAL244_R04_0_Pos 0 /*!< LCD PAL244: R04_0 Position */ -#define LCD_PAL244_R04_0_Msk (0x1fUL << LCD_PAL244_R04_0_Pos) /*!< LCD PAL244: R04_0 Mask */ -#define LCD_PAL244_G04_0_Pos 5 /*!< LCD PAL244: G04_0 Position */ -#define LCD_PAL244_G04_0_Msk (0x1fUL << LCD_PAL244_G04_0_Pos) /*!< LCD PAL244: G04_0 Mask */ -#define LCD_PAL244_B04_0_Pos 10 /*!< LCD PAL244: B04_0 Position */ -#define LCD_PAL244_B04_0_Msk (0x1fUL << LCD_PAL244_B04_0_Pos) /*!< LCD PAL244: B04_0 Mask */ -#define LCD_PAL244_I0_Pos 15 /*!< LCD PAL244: I0 Position */ -#define LCD_PAL244_I0_Msk (0x01UL << LCD_PAL244_I0_Pos) /*!< LCD PAL244: I0 Mask */ -#define LCD_PAL244_R14_0_Pos 16 /*!< LCD PAL244: R14_0 Position */ -#define LCD_PAL244_R14_0_Msk (0x1fUL << LCD_PAL244_R14_0_Pos) /*!< LCD PAL244: R14_0 Mask */ -#define LCD_PAL244_G14_0_Pos 21 /*!< LCD PAL244: G14_0 Position */ -#define LCD_PAL244_G14_0_Msk (0x1fUL << LCD_PAL244_G14_0_Pos) /*!< LCD PAL244: G14_0 Mask */ -#define LCD_PAL244_B14_0_Pos 26 /*!< LCD PAL244: B14_0 Position */ -#define LCD_PAL244_B14_0_Msk (0x1fUL << LCD_PAL244_B14_0_Pos) /*!< LCD PAL244: B14_0 Mask */ -#define LCD_PAL244_I1_Pos 31 /*!< LCD PAL244: I1 Position */ -#define LCD_PAL244_I1_Msk (0x01UL << LCD_PAL244_I1_Pos) /*!< LCD PAL244: I1 Mask */ - -// --------------------------------------- LCD_PAL245 ------------------------------------------- -#define LCD_PAL245_R04_0_Pos 0 /*!< LCD PAL245: R04_0 Position */ -#define LCD_PAL245_R04_0_Msk (0x1fUL << LCD_PAL245_R04_0_Pos) /*!< LCD PAL245: R04_0 Mask */ -#define LCD_PAL245_G04_0_Pos 5 /*!< LCD PAL245: G04_0 Position */ -#define LCD_PAL245_G04_0_Msk (0x1fUL << LCD_PAL245_G04_0_Pos) /*!< LCD PAL245: G04_0 Mask */ -#define LCD_PAL245_B04_0_Pos 10 /*!< LCD PAL245: B04_0 Position */ -#define LCD_PAL245_B04_0_Msk (0x1fUL << LCD_PAL245_B04_0_Pos) /*!< LCD PAL245: B04_0 Mask */ -#define LCD_PAL245_I0_Pos 15 /*!< LCD PAL245: I0 Position */ -#define LCD_PAL245_I0_Msk (0x01UL << LCD_PAL245_I0_Pos) /*!< LCD PAL245: I0 Mask */ -#define LCD_PAL245_R14_0_Pos 16 /*!< LCD PAL245: R14_0 Position */ -#define LCD_PAL245_R14_0_Msk (0x1fUL << LCD_PAL245_R14_0_Pos) /*!< LCD PAL245: R14_0 Mask */ -#define LCD_PAL245_G14_0_Pos 21 /*!< LCD PAL245: G14_0 Position */ -#define LCD_PAL245_G14_0_Msk (0x1fUL << LCD_PAL245_G14_0_Pos) /*!< LCD PAL245: G14_0 Mask */ -#define LCD_PAL245_B14_0_Pos 26 /*!< LCD PAL245: B14_0 Position */ -#define LCD_PAL245_B14_0_Msk (0x1fUL << LCD_PAL245_B14_0_Pos) /*!< LCD PAL245: B14_0 Mask */ -#define LCD_PAL245_I1_Pos 31 /*!< LCD PAL245: I1 Position */ -#define LCD_PAL245_I1_Msk (0x01UL << LCD_PAL245_I1_Pos) /*!< LCD PAL245: I1 Mask */ - -// --------------------------------------- LCD_PAL246 ------------------------------------------- -#define LCD_PAL246_R04_0_Pos 0 /*!< LCD PAL246: R04_0 Position */ -#define LCD_PAL246_R04_0_Msk (0x1fUL << LCD_PAL246_R04_0_Pos) /*!< LCD PAL246: R04_0 Mask */ -#define LCD_PAL246_G04_0_Pos 5 /*!< LCD PAL246: G04_0 Position */ -#define LCD_PAL246_G04_0_Msk (0x1fUL << LCD_PAL246_G04_0_Pos) /*!< LCD PAL246: G04_0 Mask */ -#define LCD_PAL246_B04_0_Pos 10 /*!< LCD PAL246: B04_0 Position */ -#define LCD_PAL246_B04_0_Msk (0x1fUL << LCD_PAL246_B04_0_Pos) /*!< LCD PAL246: B04_0 Mask */ -#define LCD_PAL246_I0_Pos 15 /*!< LCD PAL246: I0 Position */ -#define LCD_PAL246_I0_Msk (0x01UL << LCD_PAL246_I0_Pos) /*!< LCD PAL246: I0 Mask */ -#define LCD_PAL246_R14_0_Pos 16 /*!< LCD PAL246: R14_0 Position */ -#define LCD_PAL246_R14_0_Msk (0x1fUL << LCD_PAL246_R14_0_Pos) /*!< LCD PAL246: R14_0 Mask */ -#define LCD_PAL246_G14_0_Pos 21 /*!< LCD PAL246: G14_0 Position */ -#define LCD_PAL246_G14_0_Msk (0x1fUL << LCD_PAL246_G14_0_Pos) /*!< LCD PAL246: G14_0 Mask */ -#define LCD_PAL246_B14_0_Pos 26 /*!< LCD PAL246: B14_0 Position */ -#define LCD_PAL246_B14_0_Msk (0x1fUL << LCD_PAL246_B14_0_Pos) /*!< LCD PAL246: B14_0 Mask */ -#define LCD_PAL246_I1_Pos 31 /*!< LCD PAL246: I1 Position */ -#define LCD_PAL246_I1_Msk (0x01UL << LCD_PAL246_I1_Pos) /*!< LCD PAL246: I1 Mask */ - -// --------------------------------------- LCD_PAL247 ------------------------------------------- -#define LCD_PAL247_R04_0_Pos 0 /*!< LCD PAL247: R04_0 Position */ -#define LCD_PAL247_R04_0_Msk (0x1fUL << LCD_PAL247_R04_0_Pos) /*!< LCD PAL247: R04_0 Mask */ -#define LCD_PAL247_G04_0_Pos 5 /*!< LCD PAL247: G04_0 Position */ -#define LCD_PAL247_G04_0_Msk (0x1fUL << LCD_PAL247_G04_0_Pos) /*!< LCD PAL247: G04_0 Mask */ -#define LCD_PAL247_B04_0_Pos 10 /*!< LCD PAL247: B04_0 Position */ -#define LCD_PAL247_B04_0_Msk (0x1fUL << LCD_PAL247_B04_0_Pos) /*!< LCD PAL247: B04_0 Mask */ -#define LCD_PAL247_I0_Pos 15 /*!< LCD PAL247: I0 Position */ -#define LCD_PAL247_I0_Msk (0x01UL << LCD_PAL247_I0_Pos) /*!< LCD PAL247: I0 Mask */ -#define LCD_PAL247_R14_0_Pos 16 /*!< LCD PAL247: R14_0 Position */ -#define LCD_PAL247_R14_0_Msk (0x1fUL << LCD_PAL247_R14_0_Pos) /*!< LCD PAL247: R14_0 Mask */ -#define LCD_PAL247_G14_0_Pos 21 /*!< LCD PAL247: G14_0 Position */ -#define LCD_PAL247_G14_0_Msk (0x1fUL << LCD_PAL247_G14_0_Pos) /*!< LCD PAL247: G14_0 Mask */ -#define LCD_PAL247_B14_0_Pos 26 /*!< LCD PAL247: B14_0 Position */ -#define LCD_PAL247_B14_0_Msk (0x1fUL << LCD_PAL247_B14_0_Pos) /*!< LCD PAL247: B14_0 Mask */ -#define LCD_PAL247_I1_Pos 31 /*!< LCD PAL247: I1 Position */ -#define LCD_PAL247_I1_Msk (0x01UL << LCD_PAL247_I1_Pos) /*!< LCD PAL247: I1 Mask */ - -// --------------------------------------- LCD_PAL248 ------------------------------------------- -#define LCD_PAL248_R04_0_Pos 0 /*!< LCD PAL248: R04_0 Position */ -#define LCD_PAL248_R04_0_Msk (0x1fUL << LCD_PAL248_R04_0_Pos) /*!< LCD PAL248: R04_0 Mask */ -#define LCD_PAL248_G04_0_Pos 5 /*!< LCD PAL248: G04_0 Position */ -#define LCD_PAL248_G04_0_Msk (0x1fUL << LCD_PAL248_G04_0_Pos) /*!< LCD PAL248: G04_0 Mask */ -#define LCD_PAL248_B04_0_Pos 10 /*!< LCD PAL248: B04_0 Position */ -#define LCD_PAL248_B04_0_Msk (0x1fUL << LCD_PAL248_B04_0_Pos) /*!< LCD PAL248: B04_0 Mask */ -#define LCD_PAL248_I0_Pos 15 /*!< LCD PAL248: I0 Position */ -#define LCD_PAL248_I0_Msk (0x01UL << LCD_PAL248_I0_Pos) /*!< LCD PAL248: I0 Mask */ -#define LCD_PAL248_R14_0_Pos 16 /*!< LCD PAL248: R14_0 Position */ -#define LCD_PAL248_R14_0_Msk (0x1fUL << LCD_PAL248_R14_0_Pos) /*!< LCD PAL248: R14_0 Mask */ -#define LCD_PAL248_G14_0_Pos 21 /*!< LCD PAL248: G14_0 Position */ -#define LCD_PAL248_G14_0_Msk (0x1fUL << LCD_PAL248_G14_0_Pos) /*!< LCD PAL248: G14_0 Mask */ -#define LCD_PAL248_B14_0_Pos 26 /*!< LCD PAL248: B14_0 Position */ -#define LCD_PAL248_B14_0_Msk (0x1fUL << LCD_PAL248_B14_0_Pos) /*!< LCD PAL248: B14_0 Mask */ -#define LCD_PAL248_I1_Pos 31 /*!< LCD PAL248: I1 Position */ -#define LCD_PAL248_I1_Msk (0x01UL << LCD_PAL248_I1_Pos) /*!< LCD PAL248: I1 Mask */ - -// --------------------------------------- LCD_PAL249 ------------------------------------------- -#define LCD_PAL249_R04_0_Pos 0 /*!< LCD PAL249: R04_0 Position */ -#define LCD_PAL249_R04_0_Msk (0x1fUL << LCD_PAL249_R04_0_Pos) /*!< LCD PAL249: R04_0 Mask */ -#define LCD_PAL249_G04_0_Pos 5 /*!< LCD PAL249: G04_0 Position */ -#define LCD_PAL249_G04_0_Msk (0x1fUL << LCD_PAL249_G04_0_Pos) /*!< LCD PAL249: G04_0 Mask */ -#define LCD_PAL249_B04_0_Pos 10 /*!< LCD PAL249: B04_0 Position */ -#define LCD_PAL249_B04_0_Msk (0x1fUL << LCD_PAL249_B04_0_Pos) /*!< LCD PAL249: B04_0 Mask */ -#define LCD_PAL249_I0_Pos 15 /*!< LCD PAL249: I0 Position */ -#define LCD_PAL249_I0_Msk (0x01UL << LCD_PAL249_I0_Pos) /*!< LCD PAL249: I0 Mask */ -#define LCD_PAL249_R14_0_Pos 16 /*!< LCD PAL249: R14_0 Position */ -#define LCD_PAL249_R14_0_Msk (0x1fUL << LCD_PAL249_R14_0_Pos) /*!< LCD PAL249: R14_0 Mask */ -#define LCD_PAL249_G14_0_Pos 21 /*!< LCD PAL249: G14_0 Position */ -#define LCD_PAL249_G14_0_Msk (0x1fUL << LCD_PAL249_G14_0_Pos) /*!< LCD PAL249: G14_0 Mask */ -#define LCD_PAL249_B14_0_Pos 26 /*!< LCD PAL249: B14_0 Position */ -#define LCD_PAL249_B14_0_Msk (0x1fUL << LCD_PAL249_B14_0_Pos) /*!< LCD PAL249: B14_0 Mask */ -#define LCD_PAL249_I1_Pos 31 /*!< LCD PAL249: I1 Position */ -#define LCD_PAL249_I1_Msk (0x01UL << LCD_PAL249_I1_Pos) /*!< LCD PAL249: I1 Mask */ - -// --------------------------------------- LCD_PAL250 ------------------------------------------- -#define LCD_PAL250_R04_0_Pos 0 /*!< LCD PAL250: R04_0 Position */ -#define LCD_PAL250_R04_0_Msk (0x1fUL << LCD_PAL250_R04_0_Pos) /*!< LCD PAL250: R04_0 Mask */ -#define LCD_PAL250_G04_0_Pos 5 /*!< LCD PAL250: G04_0 Position */ -#define LCD_PAL250_G04_0_Msk (0x1fUL << LCD_PAL250_G04_0_Pos) /*!< LCD PAL250: G04_0 Mask */ -#define LCD_PAL250_B04_0_Pos 10 /*!< LCD PAL250: B04_0 Position */ -#define LCD_PAL250_B04_0_Msk (0x1fUL << LCD_PAL250_B04_0_Pos) /*!< LCD PAL250: B04_0 Mask */ -#define LCD_PAL250_I0_Pos 15 /*!< LCD PAL250: I0 Position */ -#define LCD_PAL250_I0_Msk (0x01UL << LCD_PAL250_I0_Pos) /*!< LCD PAL250: I0 Mask */ -#define LCD_PAL250_R14_0_Pos 16 /*!< LCD PAL250: R14_0 Position */ -#define LCD_PAL250_R14_0_Msk (0x1fUL << LCD_PAL250_R14_0_Pos) /*!< LCD PAL250: R14_0 Mask */ -#define LCD_PAL250_G14_0_Pos 21 /*!< LCD PAL250: G14_0 Position */ -#define LCD_PAL250_G14_0_Msk (0x1fUL << LCD_PAL250_G14_0_Pos) /*!< LCD PAL250: G14_0 Mask */ -#define LCD_PAL250_B14_0_Pos 26 /*!< LCD PAL250: B14_0 Position */ -#define LCD_PAL250_B14_0_Msk (0x1fUL << LCD_PAL250_B14_0_Pos) /*!< LCD PAL250: B14_0 Mask */ -#define LCD_PAL250_I1_Pos 31 /*!< LCD PAL250: I1 Position */ -#define LCD_PAL250_I1_Msk (0x01UL << LCD_PAL250_I1_Pos) /*!< LCD PAL250: I1 Mask */ - -// --------------------------------------- LCD_PAL251 ------------------------------------------- -#define LCD_PAL251_R04_0_Pos 0 /*!< LCD PAL251: R04_0 Position */ -#define LCD_PAL251_R04_0_Msk (0x1fUL << LCD_PAL251_R04_0_Pos) /*!< LCD PAL251: R04_0 Mask */ -#define LCD_PAL251_G04_0_Pos 5 /*!< LCD PAL251: G04_0 Position */ -#define LCD_PAL251_G04_0_Msk (0x1fUL << LCD_PAL251_G04_0_Pos) /*!< LCD PAL251: G04_0 Mask */ -#define LCD_PAL251_B04_0_Pos 10 /*!< LCD PAL251: B04_0 Position */ -#define LCD_PAL251_B04_0_Msk (0x1fUL << LCD_PAL251_B04_0_Pos) /*!< LCD PAL251: B04_0 Mask */ -#define LCD_PAL251_I0_Pos 15 /*!< LCD PAL251: I0 Position */ -#define LCD_PAL251_I0_Msk (0x01UL << LCD_PAL251_I0_Pos) /*!< LCD PAL251: I0 Mask */ -#define LCD_PAL251_R14_0_Pos 16 /*!< LCD PAL251: R14_0 Position */ -#define LCD_PAL251_R14_0_Msk (0x1fUL << LCD_PAL251_R14_0_Pos) /*!< LCD PAL251: R14_0 Mask */ -#define LCD_PAL251_G14_0_Pos 21 /*!< LCD PAL251: G14_0 Position */ -#define LCD_PAL251_G14_0_Msk (0x1fUL << LCD_PAL251_G14_0_Pos) /*!< LCD PAL251: G14_0 Mask */ -#define LCD_PAL251_B14_0_Pos 26 /*!< LCD PAL251: B14_0 Position */ -#define LCD_PAL251_B14_0_Msk (0x1fUL << LCD_PAL251_B14_0_Pos) /*!< LCD PAL251: B14_0 Mask */ -#define LCD_PAL251_I1_Pos 31 /*!< LCD PAL251: I1 Position */ -#define LCD_PAL251_I1_Msk (0x01UL << LCD_PAL251_I1_Pos) /*!< LCD PAL251: I1 Mask */ - -// --------------------------------------- LCD_PAL252 ------------------------------------------- -#define LCD_PAL252_R04_0_Pos 0 /*!< LCD PAL252: R04_0 Position */ -#define LCD_PAL252_R04_0_Msk (0x1fUL << LCD_PAL252_R04_0_Pos) /*!< LCD PAL252: R04_0 Mask */ -#define LCD_PAL252_G04_0_Pos 5 /*!< LCD PAL252: G04_0 Position */ -#define LCD_PAL252_G04_0_Msk (0x1fUL << LCD_PAL252_G04_0_Pos) /*!< LCD PAL252: G04_0 Mask */ -#define LCD_PAL252_B04_0_Pos 10 /*!< LCD PAL252: B04_0 Position */ -#define LCD_PAL252_B04_0_Msk (0x1fUL << LCD_PAL252_B04_0_Pos) /*!< LCD PAL252: B04_0 Mask */ -#define LCD_PAL252_I0_Pos 15 /*!< LCD PAL252: I0 Position */ -#define LCD_PAL252_I0_Msk (0x01UL << LCD_PAL252_I0_Pos) /*!< LCD PAL252: I0 Mask */ -#define LCD_PAL252_R14_0_Pos 16 /*!< LCD PAL252: R14_0 Position */ -#define LCD_PAL252_R14_0_Msk (0x1fUL << LCD_PAL252_R14_0_Pos) /*!< LCD PAL252: R14_0 Mask */ -#define LCD_PAL252_G14_0_Pos 21 /*!< LCD PAL252: G14_0 Position */ -#define LCD_PAL252_G14_0_Msk (0x1fUL << LCD_PAL252_G14_0_Pos) /*!< LCD PAL252: G14_0 Mask */ -#define LCD_PAL252_B14_0_Pos 26 /*!< LCD PAL252: B14_0 Position */ -#define LCD_PAL252_B14_0_Msk (0x1fUL << LCD_PAL252_B14_0_Pos) /*!< LCD PAL252: B14_0 Mask */ -#define LCD_PAL252_I1_Pos 31 /*!< LCD PAL252: I1 Position */ -#define LCD_PAL252_I1_Msk (0x01UL << LCD_PAL252_I1_Pos) /*!< LCD PAL252: I1 Mask */ - -// --------------------------------------- LCD_PAL253 ------------------------------------------- -#define LCD_PAL253_R04_0_Pos 0 /*!< LCD PAL253: R04_0 Position */ -#define LCD_PAL253_R04_0_Msk (0x1fUL << LCD_PAL253_R04_0_Pos) /*!< LCD PAL253: R04_0 Mask */ -#define LCD_PAL253_G04_0_Pos 5 /*!< LCD PAL253: G04_0 Position */ -#define LCD_PAL253_G04_0_Msk (0x1fUL << LCD_PAL253_G04_0_Pos) /*!< LCD PAL253: G04_0 Mask */ -#define LCD_PAL253_B04_0_Pos 10 /*!< LCD PAL253: B04_0 Position */ -#define LCD_PAL253_B04_0_Msk (0x1fUL << LCD_PAL253_B04_0_Pos) /*!< LCD PAL253: B04_0 Mask */ -#define LCD_PAL253_I0_Pos 15 /*!< LCD PAL253: I0 Position */ -#define LCD_PAL253_I0_Msk (0x01UL << LCD_PAL253_I0_Pos) /*!< LCD PAL253: I0 Mask */ -#define LCD_PAL253_R14_0_Pos 16 /*!< LCD PAL253: R14_0 Position */ -#define LCD_PAL253_R14_0_Msk (0x1fUL << LCD_PAL253_R14_0_Pos) /*!< LCD PAL253: R14_0 Mask */ -#define LCD_PAL253_G14_0_Pos 21 /*!< LCD PAL253: G14_0 Position */ -#define LCD_PAL253_G14_0_Msk (0x1fUL << LCD_PAL253_G14_0_Pos) /*!< LCD PAL253: G14_0 Mask */ -#define LCD_PAL253_B14_0_Pos 26 /*!< LCD PAL253: B14_0 Position */ -#define LCD_PAL253_B14_0_Msk (0x1fUL << LCD_PAL253_B14_0_Pos) /*!< LCD PAL253: B14_0 Mask */ -#define LCD_PAL253_I1_Pos 31 /*!< LCD PAL253: I1 Position */ -#define LCD_PAL253_I1_Msk (0x01UL << LCD_PAL253_I1_Pos) /*!< LCD PAL253: I1 Mask */ - -// --------------------------------------- LCD_PAL254 ------------------------------------------- -#define LCD_PAL254_R04_0_Pos 0 /*!< LCD PAL254: R04_0 Position */ -#define LCD_PAL254_R04_0_Msk (0x1fUL << LCD_PAL254_R04_0_Pos) /*!< LCD PAL254: R04_0 Mask */ -#define LCD_PAL254_G04_0_Pos 5 /*!< LCD PAL254: G04_0 Position */ -#define LCD_PAL254_G04_0_Msk (0x1fUL << LCD_PAL254_G04_0_Pos) /*!< LCD PAL254: G04_0 Mask */ -#define LCD_PAL254_B04_0_Pos 10 /*!< LCD PAL254: B04_0 Position */ -#define LCD_PAL254_B04_0_Msk (0x1fUL << LCD_PAL254_B04_0_Pos) /*!< LCD PAL254: B04_0 Mask */ -#define LCD_PAL254_I0_Pos 15 /*!< LCD PAL254: I0 Position */ -#define LCD_PAL254_I0_Msk (0x01UL << LCD_PAL254_I0_Pos) /*!< LCD PAL254: I0 Mask */ -#define LCD_PAL254_R14_0_Pos 16 /*!< LCD PAL254: R14_0 Position */ -#define LCD_PAL254_R14_0_Msk (0x1fUL << LCD_PAL254_R14_0_Pos) /*!< LCD PAL254: R14_0 Mask */ -#define LCD_PAL254_G14_0_Pos 21 /*!< LCD PAL254: G14_0 Position */ -#define LCD_PAL254_G14_0_Msk (0x1fUL << LCD_PAL254_G14_0_Pos) /*!< LCD PAL254: G14_0 Mask */ -#define LCD_PAL254_B14_0_Pos 26 /*!< LCD PAL254: B14_0 Position */ -#define LCD_PAL254_B14_0_Msk (0x1fUL << LCD_PAL254_B14_0_Pos) /*!< LCD PAL254: B14_0 Mask */ -#define LCD_PAL254_I1_Pos 31 /*!< LCD PAL254: I1 Position */ -#define LCD_PAL254_I1_Msk (0x01UL << LCD_PAL254_I1_Pos) /*!< LCD PAL254: I1 Mask */ - -// --------------------------------------- LCD_PAL255 ------------------------------------------- -#define LCD_PAL255_R04_0_Pos 0 /*!< LCD PAL255: R04_0 Position */ -#define LCD_PAL255_R04_0_Msk (0x1fUL << LCD_PAL255_R04_0_Pos) /*!< LCD PAL255: R04_0 Mask */ -#define LCD_PAL255_G04_0_Pos 5 /*!< LCD PAL255: G04_0 Position */ -#define LCD_PAL255_G04_0_Msk (0x1fUL << LCD_PAL255_G04_0_Pos) /*!< LCD PAL255: G04_0 Mask */ -#define LCD_PAL255_B04_0_Pos 10 /*!< LCD PAL255: B04_0 Position */ -#define LCD_PAL255_B04_0_Msk (0x1fUL << LCD_PAL255_B04_0_Pos) /*!< LCD PAL255: B04_0 Mask */ -#define LCD_PAL255_I0_Pos 15 /*!< LCD PAL255: I0 Position */ -#define LCD_PAL255_I0_Msk (0x01UL << LCD_PAL255_I0_Pos) /*!< LCD PAL255: I0 Mask */ -#define LCD_PAL255_R14_0_Pos 16 /*!< LCD PAL255: R14_0 Position */ -#define LCD_PAL255_R14_0_Msk (0x1fUL << LCD_PAL255_R14_0_Pos) /*!< LCD PAL255: R14_0 Mask */ -#define LCD_PAL255_G14_0_Pos 21 /*!< LCD PAL255: G14_0 Position */ -#define LCD_PAL255_G14_0_Msk (0x1fUL << LCD_PAL255_G14_0_Pos) /*!< LCD PAL255: G14_0 Mask */ -#define LCD_PAL255_B14_0_Pos 26 /*!< LCD PAL255: B14_0 Position */ -#define LCD_PAL255_B14_0_Msk (0x1fUL << LCD_PAL255_B14_0_Pos) /*!< LCD PAL255: B14_0 Mask */ -#define LCD_PAL255_I1_Pos 31 /*!< LCD PAL255: I1 Position */ -#define LCD_PAL255_I1_Msk (0x01UL << LCD_PAL255_I1_Pos) /*!< LCD PAL255: I1 Mask */ - -// -------------------------------------- LCD_CRSR_IMG0 ----------------------------------------- -#define LCD_CRSR_IMG0_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG0: CRSR_IMG Position */ -#define LCD_CRSR_IMG0_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos) /*!< LCD CRSR_IMG0: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG1 ----------------------------------------- -#define LCD_CRSR_IMG1_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG1: CRSR_IMG Position */ -#define LCD_CRSR_IMG1_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos) /*!< LCD CRSR_IMG1: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG2 ----------------------------------------- -#define LCD_CRSR_IMG2_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG2: CRSR_IMG Position */ -#define LCD_CRSR_IMG2_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos) /*!< LCD CRSR_IMG2: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG3 ----------------------------------------- -#define LCD_CRSR_IMG3_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG3: CRSR_IMG Position */ -#define LCD_CRSR_IMG3_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos) /*!< LCD CRSR_IMG3: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG4 ----------------------------------------- -#define LCD_CRSR_IMG4_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG4: CRSR_IMG Position */ -#define LCD_CRSR_IMG4_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos) /*!< LCD CRSR_IMG4: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG5 ----------------------------------------- -#define LCD_CRSR_IMG5_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG5: CRSR_IMG Position */ -#define LCD_CRSR_IMG5_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos) /*!< LCD CRSR_IMG5: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG6 ----------------------------------------- -#define LCD_CRSR_IMG6_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG6: CRSR_IMG Position */ -#define LCD_CRSR_IMG6_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos) /*!< LCD CRSR_IMG6: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG7 ----------------------------------------- -#define LCD_CRSR_IMG7_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG7: CRSR_IMG Position */ -#define LCD_CRSR_IMG7_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos) /*!< LCD CRSR_IMG7: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG8 ----------------------------------------- -#define LCD_CRSR_IMG8_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG8: CRSR_IMG Position */ -#define LCD_CRSR_IMG8_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos) /*!< LCD CRSR_IMG8: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG9 ----------------------------------------- -#define LCD_CRSR_IMG9_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG9: CRSR_IMG Position */ -#define LCD_CRSR_IMG9_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos) /*!< LCD CRSR_IMG9: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG10 ----------------------------------------- -#define LCD_CRSR_IMG10_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG10: CRSR_IMG Position */ -#define LCD_CRSR_IMG10_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos) /*!< LCD CRSR_IMG10: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG11 ----------------------------------------- -#define LCD_CRSR_IMG11_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG11: CRSR_IMG Position */ -#define LCD_CRSR_IMG11_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos) /*!< LCD CRSR_IMG11: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG12 ----------------------------------------- -#define LCD_CRSR_IMG12_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG12: CRSR_IMG Position */ -#define LCD_CRSR_IMG12_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos) /*!< LCD CRSR_IMG12: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG13 ----------------------------------------- -#define LCD_CRSR_IMG13_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG13: CRSR_IMG Position */ -#define LCD_CRSR_IMG13_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos) /*!< LCD CRSR_IMG13: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG14 ----------------------------------------- -#define LCD_CRSR_IMG14_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG14: CRSR_IMG Position */ -#define LCD_CRSR_IMG14_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos) /*!< LCD CRSR_IMG14: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG15 ----------------------------------------- -#define LCD_CRSR_IMG15_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG15: CRSR_IMG Position */ -#define LCD_CRSR_IMG15_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos) /*!< LCD CRSR_IMG15: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG16 ----------------------------------------- -#define LCD_CRSR_IMG16_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG16: CRSR_IMG Position */ -#define LCD_CRSR_IMG16_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos) /*!< LCD CRSR_IMG16: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG17 ----------------------------------------- -#define LCD_CRSR_IMG17_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG17: CRSR_IMG Position */ -#define LCD_CRSR_IMG17_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos) /*!< LCD CRSR_IMG17: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG18 ----------------------------------------- -#define LCD_CRSR_IMG18_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG18: CRSR_IMG Position */ -#define LCD_CRSR_IMG18_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos) /*!< LCD CRSR_IMG18: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG19 ----------------------------------------- -#define LCD_CRSR_IMG19_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG19: CRSR_IMG Position */ -#define LCD_CRSR_IMG19_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos) /*!< LCD CRSR_IMG19: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG20 ----------------------------------------- -#define LCD_CRSR_IMG20_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG20: CRSR_IMG Position */ -#define LCD_CRSR_IMG20_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos) /*!< LCD CRSR_IMG20: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG21 ----------------------------------------- -#define LCD_CRSR_IMG21_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG21: CRSR_IMG Position */ -#define LCD_CRSR_IMG21_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos) /*!< LCD CRSR_IMG21: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG22 ----------------------------------------- -#define LCD_CRSR_IMG22_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG22: CRSR_IMG Position */ -#define LCD_CRSR_IMG22_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos) /*!< LCD CRSR_IMG22: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG23 ----------------------------------------- -#define LCD_CRSR_IMG23_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG23: CRSR_IMG Position */ -#define LCD_CRSR_IMG23_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos) /*!< LCD CRSR_IMG23: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG24 ----------------------------------------- -#define LCD_CRSR_IMG24_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG24: CRSR_IMG Position */ -#define LCD_CRSR_IMG24_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos) /*!< LCD CRSR_IMG24: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG25 ----------------------------------------- -#define LCD_CRSR_IMG25_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG25: CRSR_IMG Position */ -#define LCD_CRSR_IMG25_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos) /*!< LCD CRSR_IMG25: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG26 ----------------------------------------- -#define LCD_CRSR_IMG26_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG26: CRSR_IMG Position */ -#define LCD_CRSR_IMG26_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos) /*!< LCD CRSR_IMG26: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG27 ----------------------------------------- -#define LCD_CRSR_IMG27_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG27: CRSR_IMG Position */ -#define LCD_CRSR_IMG27_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos) /*!< LCD CRSR_IMG27: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG28 ----------------------------------------- -#define LCD_CRSR_IMG28_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG28: CRSR_IMG Position */ -#define LCD_CRSR_IMG28_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos) /*!< LCD CRSR_IMG28: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG29 ----------------------------------------- -#define LCD_CRSR_IMG29_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG29: CRSR_IMG Position */ -#define LCD_CRSR_IMG29_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos) /*!< LCD CRSR_IMG29: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG30 ----------------------------------------- -#define LCD_CRSR_IMG30_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG30: CRSR_IMG Position */ -#define LCD_CRSR_IMG30_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos) /*!< LCD CRSR_IMG30: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG31 ----------------------------------------- -#define LCD_CRSR_IMG31_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG31: CRSR_IMG Position */ -#define LCD_CRSR_IMG31_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos) /*!< LCD CRSR_IMG31: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG32 ----------------------------------------- -#define LCD_CRSR_IMG32_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG32: CRSR_IMG Position */ -#define LCD_CRSR_IMG32_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos) /*!< LCD CRSR_IMG32: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG33 ----------------------------------------- -#define LCD_CRSR_IMG33_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG33: CRSR_IMG Position */ -#define LCD_CRSR_IMG33_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos) /*!< LCD CRSR_IMG33: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG34 ----------------------------------------- -#define LCD_CRSR_IMG34_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG34: CRSR_IMG Position */ -#define LCD_CRSR_IMG34_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos) /*!< LCD CRSR_IMG34: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG35 ----------------------------------------- -#define LCD_CRSR_IMG35_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG35: CRSR_IMG Position */ -#define LCD_CRSR_IMG35_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos) /*!< LCD CRSR_IMG35: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG36 ----------------------------------------- -#define LCD_CRSR_IMG36_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG36: CRSR_IMG Position */ -#define LCD_CRSR_IMG36_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos) /*!< LCD CRSR_IMG36: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG37 ----------------------------------------- -#define LCD_CRSR_IMG37_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG37: CRSR_IMG Position */ -#define LCD_CRSR_IMG37_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos) /*!< LCD CRSR_IMG37: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG38 ----------------------------------------- -#define LCD_CRSR_IMG38_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG38: CRSR_IMG Position */ -#define LCD_CRSR_IMG38_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos) /*!< LCD CRSR_IMG38: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG39 ----------------------------------------- -#define LCD_CRSR_IMG39_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG39: CRSR_IMG Position */ -#define LCD_CRSR_IMG39_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos) /*!< LCD CRSR_IMG39: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG40 ----------------------------------------- -#define LCD_CRSR_IMG40_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG40: CRSR_IMG Position */ -#define LCD_CRSR_IMG40_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos) /*!< LCD CRSR_IMG40: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG41 ----------------------------------------- -#define LCD_CRSR_IMG41_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG41: CRSR_IMG Position */ -#define LCD_CRSR_IMG41_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos) /*!< LCD CRSR_IMG41: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG42 ----------------------------------------- -#define LCD_CRSR_IMG42_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG42: CRSR_IMG Position */ -#define LCD_CRSR_IMG42_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos) /*!< LCD CRSR_IMG42: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG43 ----------------------------------------- -#define LCD_CRSR_IMG43_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG43: CRSR_IMG Position */ -#define LCD_CRSR_IMG43_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos) /*!< LCD CRSR_IMG43: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG44 ----------------------------------------- -#define LCD_CRSR_IMG44_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG44: CRSR_IMG Position */ -#define LCD_CRSR_IMG44_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos) /*!< LCD CRSR_IMG44: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG45 ----------------------------------------- -#define LCD_CRSR_IMG45_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG45: CRSR_IMG Position */ -#define LCD_CRSR_IMG45_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos) /*!< LCD CRSR_IMG45: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG46 ----------------------------------------- -#define LCD_CRSR_IMG46_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG46: CRSR_IMG Position */ -#define LCD_CRSR_IMG46_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos) /*!< LCD CRSR_IMG46: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG47 ----------------------------------------- -#define LCD_CRSR_IMG47_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG47: CRSR_IMG Position */ -#define LCD_CRSR_IMG47_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos) /*!< LCD CRSR_IMG47: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG48 ----------------------------------------- -#define LCD_CRSR_IMG48_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG48: CRSR_IMG Position */ -#define LCD_CRSR_IMG48_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos) /*!< LCD CRSR_IMG48: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG49 ----------------------------------------- -#define LCD_CRSR_IMG49_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG49: CRSR_IMG Position */ -#define LCD_CRSR_IMG49_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos) /*!< LCD CRSR_IMG49: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG50 ----------------------------------------- -#define LCD_CRSR_IMG50_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG50: CRSR_IMG Position */ -#define LCD_CRSR_IMG50_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos) /*!< LCD CRSR_IMG50: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG51 ----------------------------------------- -#define LCD_CRSR_IMG51_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG51: CRSR_IMG Position */ -#define LCD_CRSR_IMG51_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos) /*!< LCD CRSR_IMG51: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG52 ----------------------------------------- -#define LCD_CRSR_IMG52_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG52: CRSR_IMG Position */ -#define LCD_CRSR_IMG52_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos) /*!< LCD CRSR_IMG52: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG53 ----------------------------------------- -#define LCD_CRSR_IMG53_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG53: CRSR_IMG Position */ -#define LCD_CRSR_IMG53_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos) /*!< LCD CRSR_IMG53: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG54 ----------------------------------------- -#define LCD_CRSR_IMG54_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG54: CRSR_IMG Position */ -#define LCD_CRSR_IMG54_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos) /*!< LCD CRSR_IMG54: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG55 ----------------------------------------- -#define LCD_CRSR_IMG55_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG55: CRSR_IMG Position */ -#define LCD_CRSR_IMG55_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos) /*!< LCD CRSR_IMG55: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG56 ----------------------------------------- -#define LCD_CRSR_IMG56_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG56: CRSR_IMG Position */ -#define LCD_CRSR_IMG56_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos) /*!< LCD CRSR_IMG56: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG57 ----------------------------------------- -#define LCD_CRSR_IMG57_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG57: CRSR_IMG Position */ -#define LCD_CRSR_IMG57_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos) /*!< LCD CRSR_IMG57: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG58 ----------------------------------------- -#define LCD_CRSR_IMG58_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG58: CRSR_IMG Position */ -#define LCD_CRSR_IMG58_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos) /*!< LCD CRSR_IMG58: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG59 ----------------------------------------- -#define LCD_CRSR_IMG59_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG59: CRSR_IMG Position */ -#define LCD_CRSR_IMG59_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos) /*!< LCD CRSR_IMG59: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG60 ----------------------------------------- -#define LCD_CRSR_IMG60_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG60: CRSR_IMG Position */ -#define LCD_CRSR_IMG60_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos) /*!< LCD CRSR_IMG60: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG61 ----------------------------------------- -#define LCD_CRSR_IMG61_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG61: CRSR_IMG Position */ -#define LCD_CRSR_IMG61_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos) /*!< LCD CRSR_IMG61: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG62 ----------------------------------------- -#define LCD_CRSR_IMG62_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG62: CRSR_IMG Position */ -#define LCD_CRSR_IMG62_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos) /*!< LCD CRSR_IMG62: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG63 ----------------------------------------- -#define LCD_CRSR_IMG63_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG63: CRSR_IMG Position */ -#define LCD_CRSR_IMG63_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos) /*!< LCD CRSR_IMG63: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG64 ----------------------------------------- -#define LCD_CRSR_IMG64_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG64: CRSR_IMG Position */ -#define LCD_CRSR_IMG64_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos) /*!< LCD CRSR_IMG64: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG65 ----------------------------------------- -#define LCD_CRSR_IMG65_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG65: CRSR_IMG Position */ -#define LCD_CRSR_IMG65_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos) /*!< LCD CRSR_IMG65: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG66 ----------------------------------------- -#define LCD_CRSR_IMG66_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG66: CRSR_IMG Position */ -#define LCD_CRSR_IMG66_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos) /*!< LCD CRSR_IMG66: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG67 ----------------------------------------- -#define LCD_CRSR_IMG67_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG67: CRSR_IMG Position */ -#define LCD_CRSR_IMG67_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos) /*!< LCD CRSR_IMG67: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG68 ----------------------------------------- -#define LCD_CRSR_IMG68_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG68: CRSR_IMG Position */ -#define LCD_CRSR_IMG68_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos) /*!< LCD CRSR_IMG68: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG69 ----------------------------------------- -#define LCD_CRSR_IMG69_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG69: CRSR_IMG Position */ -#define LCD_CRSR_IMG69_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos) /*!< LCD CRSR_IMG69: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG70 ----------------------------------------- -#define LCD_CRSR_IMG70_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG70: CRSR_IMG Position */ -#define LCD_CRSR_IMG70_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos) /*!< LCD CRSR_IMG70: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG71 ----------------------------------------- -#define LCD_CRSR_IMG71_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG71: CRSR_IMG Position */ -#define LCD_CRSR_IMG71_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos) /*!< LCD CRSR_IMG71: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG72 ----------------------------------------- -#define LCD_CRSR_IMG72_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG72: CRSR_IMG Position */ -#define LCD_CRSR_IMG72_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos) /*!< LCD CRSR_IMG72: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG73 ----------------------------------------- -#define LCD_CRSR_IMG73_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG73: CRSR_IMG Position */ -#define LCD_CRSR_IMG73_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos) /*!< LCD CRSR_IMG73: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG74 ----------------------------------------- -#define LCD_CRSR_IMG74_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG74: CRSR_IMG Position */ -#define LCD_CRSR_IMG74_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos) /*!< LCD CRSR_IMG74: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG75 ----------------------------------------- -#define LCD_CRSR_IMG75_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG75: CRSR_IMG Position */ -#define LCD_CRSR_IMG75_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos) /*!< LCD CRSR_IMG75: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG76 ----------------------------------------- -#define LCD_CRSR_IMG76_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG76: CRSR_IMG Position */ -#define LCD_CRSR_IMG76_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos) /*!< LCD CRSR_IMG76: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG77 ----------------------------------------- -#define LCD_CRSR_IMG77_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG77: CRSR_IMG Position */ -#define LCD_CRSR_IMG77_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos) /*!< LCD CRSR_IMG77: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG78 ----------------------------------------- -#define LCD_CRSR_IMG78_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG78: CRSR_IMG Position */ -#define LCD_CRSR_IMG78_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos) /*!< LCD CRSR_IMG78: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG79 ----------------------------------------- -#define LCD_CRSR_IMG79_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG79: CRSR_IMG Position */ -#define LCD_CRSR_IMG79_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos) /*!< LCD CRSR_IMG79: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG80 ----------------------------------------- -#define LCD_CRSR_IMG80_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG80: CRSR_IMG Position */ -#define LCD_CRSR_IMG80_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos) /*!< LCD CRSR_IMG80: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG81 ----------------------------------------- -#define LCD_CRSR_IMG81_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG81: CRSR_IMG Position */ -#define LCD_CRSR_IMG81_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos) /*!< LCD CRSR_IMG81: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG82 ----------------------------------------- -#define LCD_CRSR_IMG82_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG82: CRSR_IMG Position */ -#define LCD_CRSR_IMG82_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos) /*!< LCD CRSR_IMG82: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG83 ----------------------------------------- -#define LCD_CRSR_IMG83_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG83: CRSR_IMG Position */ -#define LCD_CRSR_IMG83_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos) /*!< LCD CRSR_IMG83: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG84 ----------------------------------------- -#define LCD_CRSR_IMG84_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG84: CRSR_IMG Position */ -#define LCD_CRSR_IMG84_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos) /*!< LCD CRSR_IMG84: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG85 ----------------------------------------- -#define LCD_CRSR_IMG85_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG85: CRSR_IMG Position */ -#define LCD_CRSR_IMG85_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos) /*!< LCD CRSR_IMG85: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG86 ----------------------------------------- -#define LCD_CRSR_IMG86_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG86: CRSR_IMG Position */ -#define LCD_CRSR_IMG86_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos) /*!< LCD CRSR_IMG86: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG87 ----------------------------------------- -#define LCD_CRSR_IMG87_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG87: CRSR_IMG Position */ -#define LCD_CRSR_IMG87_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos) /*!< LCD CRSR_IMG87: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG88 ----------------------------------------- -#define LCD_CRSR_IMG88_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG88: CRSR_IMG Position */ -#define LCD_CRSR_IMG88_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos) /*!< LCD CRSR_IMG88: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG89 ----------------------------------------- -#define LCD_CRSR_IMG89_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG89: CRSR_IMG Position */ -#define LCD_CRSR_IMG89_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos) /*!< LCD CRSR_IMG89: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG90 ----------------------------------------- -#define LCD_CRSR_IMG90_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG90: CRSR_IMG Position */ -#define LCD_CRSR_IMG90_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos) /*!< LCD CRSR_IMG90: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG91 ----------------------------------------- -#define LCD_CRSR_IMG91_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG91: CRSR_IMG Position */ -#define LCD_CRSR_IMG91_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos) /*!< LCD CRSR_IMG91: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG92 ----------------------------------------- -#define LCD_CRSR_IMG92_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG92: CRSR_IMG Position */ -#define LCD_CRSR_IMG92_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos) /*!< LCD CRSR_IMG92: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG93 ----------------------------------------- -#define LCD_CRSR_IMG93_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG93: CRSR_IMG Position */ -#define LCD_CRSR_IMG93_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos) /*!< LCD CRSR_IMG93: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG94 ----------------------------------------- -#define LCD_CRSR_IMG94_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG94: CRSR_IMG Position */ -#define LCD_CRSR_IMG94_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos) /*!< LCD CRSR_IMG94: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG95 ----------------------------------------- -#define LCD_CRSR_IMG95_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG95: CRSR_IMG Position */ -#define LCD_CRSR_IMG95_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos) /*!< LCD CRSR_IMG95: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG96 ----------------------------------------- -#define LCD_CRSR_IMG96_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG96: CRSR_IMG Position */ -#define LCD_CRSR_IMG96_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos) /*!< LCD CRSR_IMG96: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG97 ----------------------------------------- -#define LCD_CRSR_IMG97_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG97: CRSR_IMG Position */ -#define LCD_CRSR_IMG97_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos) /*!< LCD CRSR_IMG97: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG98 ----------------------------------------- -#define LCD_CRSR_IMG98_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG98: CRSR_IMG Position */ -#define LCD_CRSR_IMG98_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos) /*!< LCD CRSR_IMG98: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG99 ----------------------------------------- -#define LCD_CRSR_IMG99_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG99: CRSR_IMG Position */ -#define LCD_CRSR_IMG99_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos) /*!< LCD CRSR_IMG99: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG100 ---------------------------------------- -#define LCD_CRSR_IMG100_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG100: CRSR_IMG Position */ -#define LCD_CRSR_IMG100_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos) /*!< LCD CRSR_IMG100: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG101 ---------------------------------------- -#define LCD_CRSR_IMG101_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG101: CRSR_IMG Position */ -#define LCD_CRSR_IMG101_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos) /*!< LCD CRSR_IMG101: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG102 ---------------------------------------- -#define LCD_CRSR_IMG102_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG102: CRSR_IMG Position */ -#define LCD_CRSR_IMG102_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos) /*!< LCD CRSR_IMG102: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG103 ---------------------------------------- -#define LCD_CRSR_IMG103_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG103: CRSR_IMG Position */ -#define LCD_CRSR_IMG103_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos) /*!< LCD CRSR_IMG103: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG104 ---------------------------------------- -#define LCD_CRSR_IMG104_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG104: CRSR_IMG Position */ -#define LCD_CRSR_IMG104_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos) /*!< LCD CRSR_IMG104: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG105 ---------------------------------------- -#define LCD_CRSR_IMG105_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG105: CRSR_IMG Position */ -#define LCD_CRSR_IMG105_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos) /*!< LCD CRSR_IMG105: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG106 ---------------------------------------- -#define LCD_CRSR_IMG106_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG106: CRSR_IMG Position */ -#define LCD_CRSR_IMG106_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos) /*!< LCD CRSR_IMG106: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG107 ---------------------------------------- -#define LCD_CRSR_IMG107_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG107: CRSR_IMG Position */ -#define LCD_CRSR_IMG107_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos) /*!< LCD CRSR_IMG107: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG108 ---------------------------------------- -#define LCD_CRSR_IMG108_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG108: CRSR_IMG Position */ -#define LCD_CRSR_IMG108_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos) /*!< LCD CRSR_IMG108: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG109 ---------------------------------------- -#define LCD_CRSR_IMG109_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG109: CRSR_IMG Position */ -#define LCD_CRSR_IMG109_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos) /*!< LCD CRSR_IMG109: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG110 ---------------------------------------- -#define LCD_CRSR_IMG110_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG110: CRSR_IMG Position */ -#define LCD_CRSR_IMG110_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos) /*!< LCD CRSR_IMG110: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG111 ---------------------------------------- -#define LCD_CRSR_IMG111_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG111: CRSR_IMG Position */ -#define LCD_CRSR_IMG111_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos) /*!< LCD CRSR_IMG111: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG112 ---------------------------------------- -#define LCD_CRSR_IMG112_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG112: CRSR_IMG Position */ -#define LCD_CRSR_IMG112_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos) /*!< LCD CRSR_IMG112: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG113 ---------------------------------------- -#define LCD_CRSR_IMG113_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG113: CRSR_IMG Position */ -#define LCD_CRSR_IMG113_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos) /*!< LCD CRSR_IMG113: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG114 ---------------------------------------- -#define LCD_CRSR_IMG114_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG114: CRSR_IMG Position */ -#define LCD_CRSR_IMG114_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos) /*!< LCD CRSR_IMG114: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG115 ---------------------------------------- -#define LCD_CRSR_IMG115_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG115: CRSR_IMG Position */ -#define LCD_CRSR_IMG115_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos) /*!< LCD CRSR_IMG115: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG116 ---------------------------------------- -#define LCD_CRSR_IMG116_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG116: CRSR_IMG Position */ -#define LCD_CRSR_IMG116_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos) /*!< LCD CRSR_IMG116: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG117 ---------------------------------------- -#define LCD_CRSR_IMG117_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG117: CRSR_IMG Position */ -#define LCD_CRSR_IMG117_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos) /*!< LCD CRSR_IMG117: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG118 ---------------------------------------- -#define LCD_CRSR_IMG118_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG118: CRSR_IMG Position */ -#define LCD_CRSR_IMG118_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos) /*!< LCD CRSR_IMG118: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG119 ---------------------------------------- -#define LCD_CRSR_IMG119_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG119: CRSR_IMG Position */ -#define LCD_CRSR_IMG119_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos) /*!< LCD CRSR_IMG119: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG120 ---------------------------------------- -#define LCD_CRSR_IMG120_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG120: CRSR_IMG Position */ -#define LCD_CRSR_IMG120_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos) /*!< LCD CRSR_IMG120: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG121 ---------------------------------------- -#define LCD_CRSR_IMG121_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG121: CRSR_IMG Position */ -#define LCD_CRSR_IMG121_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos) /*!< LCD CRSR_IMG121: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG122 ---------------------------------------- -#define LCD_CRSR_IMG122_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG122: CRSR_IMG Position */ -#define LCD_CRSR_IMG122_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos) /*!< LCD CRSR_IMG122: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG123 ---------------------------------------- -#define LCD_CRSR_IMG123_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG123: CRSR_IMG Position */ -#define LCD_CRSR_IMG123_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos) /*!< LCD CRSR_IMG123: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG124 ---------------------------------------- -#define LCD_CRSR_IMG124_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG124: CRSR_IMG Position */ -#define LCD_CRSR_IMG124_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos) /*!< LCD CRSR_IMG124: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG125 ---------------------------------------- -#define LCD_CRSR_IMG125_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG125: CRSR_IMG Position */ -#define LCD_CRSR_IMG125_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos) /*!< LCD CRSR_IMG125: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG126 ---------------------------------------- -#define LCD_CRSR_IMG126_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG126: CRSR_IMG Position */ -#define LCD_CRSR_IMG126_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos) /*!< LCD CRSR_IMG126: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG127 ---------------------------------------- -#define LCD_CRSR_IMG127_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG127: CRSR_IMG Position */ -#define LCD_CRSR_IMG127_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos) /*!< LCD CRSR_IMG127: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG128 ---------------------------------------- -#define LCD_CRSR_IMG128_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG128: CRSR_IMG Position */ -#define LCD_CRSR_IMG128_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos) /*!< LCD CRSR_IMG128: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG129 ---------------------------------------- -#define LCD_CRSR_IMG129_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG129: CRSR_IMG Position */ -#define LCD_CRSR_IMG129_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos) /*!< LCD CRSR_IMG129: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG130 ---------------------------------------- -#define LCD_CRSR_IMG130_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG130: CRSR_IMG Position */ -#define LCD_CRSR_IMG130_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos) /*!< LCD CRSR_IMG130: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG131 ---------------------------------------- -#define LCD_CRSR_IMG131_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG131: CRSR_IMG Position */ -#define LCD_CRSR_IMG131_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos) /*!< LCD CRSR_IMG131: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG132 ---------------------------------------- -#define LCD_CRSR_IMG132_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG132: CRSR_IMG Position */ -#define LCD_CRSR_IMG132_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos) /*!< LCD CRSR_IMG132: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG133 ---------------------------------------- -#define LCD_CRSR_IMG133_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG133: CRSR_IMG Position */ -#define LCD_CRSR_IMG133_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos) /*!< LCD CRSR_IMG133: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG134 ---------------------------------------- -#define LCD_CRSR_IMG134_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG134: CRSR_IMG Position */ -#define LCD_CRSR_IMG134_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos) /*!< LCD CRSR_IMG134: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG135 ---------------------------------------- -#define LCD_CRSR_IMG135_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG135: CRSR_IMG Position */ -#define LCD_CRSR_IMG135_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos) /*!< LCD CRSR_IMG135: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG136 ---------------------------------------- -#define LCD_CRSR_IMG136_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG136: CRSR_IMG Position */ -#define LCD_CRSR_IMG136_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos) /*!< LCD CRSR_IMG136: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG137 ---------------------------------------- -#define LCD_CRSR_IMG137_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG137: CRSR_IMG Position */ -#define LCD_CRSR_IMG137_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos) /*!< LCD CRSR_IMG137: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG138 ---------------------------------------- -#define LCD_CRSR_IMG138_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG138: CRSR_IMG Position */ -#define LCD_CRSR_IMG138_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos) /*!< LCD CRSR_IMG138: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG139 ---------------------------------------- -#define LCD_CRSR_IMG139_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG139: CRSR_IMG Position */ -#define LCD_CRSR_IMG139_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos) /*!< LCD CRSR_IMG139: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG140 ---------------------------------------- -#define LCD_CRSR_IMG140_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG140: CRSR_IMG Position */ -#define LCD_CRSR_IMG140_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos) /*!< LCD CRSR_IMG140: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG141 ---------------------------------------- -#define LCD_CRSR_IMG141_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG141: CRSR_IMG Position */ -#define LCD_CRSR_IMG141_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos) /*!< LCD CRSR_IMG141: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG142 ---------------------------------------- -#define LCD_CRSR_IMG142_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG142: CRSR_IMG Position */ -#define LCD_CRSR_IMG142_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos) /*!< LCD CRSR_IMG142: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG143 ---------------------------------------- -#define LCD_CRSR_IMG143_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG143: CRSR_IMG Position */ -#define LCD_CRSR_IMG143_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos) /*!< LCD CRSR_IMG143: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG144 ---------------------------------------- -#define LCD_CRSR_IMG144_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG144: CRSR_IMG Position */ -#define LCD_CRSR_IMG144_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos) /*!< LCD CRSR_IMG144: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG145 ---------------------------------------- -#define LCD_CRSR_IMG145_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG145: CRSR_IMG Position */ -#define LCD_CRSR_IMG145_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos) /*!< LCD CRSR_IMG145: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG146 ---------------------------------------- -#define LCD_CRSR_IMG146_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG146: CRSR_IMG Position */ -#define LCD_CRSR_IMG146_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos) /*!< LCD CRSR_IMG146: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG147 ---------------------------------------- -#define LCD_CRSR_IMG147_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG147: CRSR_IMG Position */ -#define LCD_CRSR_IMG147_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos) /*!< LCD CRSR_IMG147: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG148 ---------------------------------------- -#define LCD_CRSR_IMG148_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG148: CRSR_IMG Position */ -#define LCD_CRSR_IMG148_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos) /*!< LCD CRSR_IMG148: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG149 ---------------------------------------- -#define LCD_CRSR_IMG149_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG149: CRSR_IMG Position */ -#define LCD_CRSR_IMG149_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos) /*!< LCD CRSR_IMG149: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG150 ---------------------------------------- -#define LCD_CRSR_IMG150_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG150: CRSR_IMG Position */ -#define LCD_CRSR_IMG150_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos) /*!< LCD CRSR_IMG150: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG151 ---------------------------------------- -#define LCD_CRSR_IMG151_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG151: CRSR_IMG Position */ -#define LCD_CRSR_IMG151_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos) /*!< LCD CRSR_IMG151: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG152 ---------------------------------------- -#define LCD_CRSR_IMG152_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG152: CRSR_IMG Position */ -#define LCD_CRSR_IMG152_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos) /*!< LCD CRSR_IMG152: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG153 ---------------------------------------- -#define LCD_CRSR_IMG153_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG153: CRSR_IMG Position */ -#define LCD_CRSR_IMG153_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos) /*!< LCD CRSR_IMG153: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG154 ---------------------------------------- -#define LCD_CRSR_IMG154_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG154: CRSR_IMG Position */ -#define LCD_CRSR_IMG154_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos) /*!< LCD CRSR_IMG154: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG155 ---------------------------------------- -#define LCD_CRSR_IMG155_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG155: CRSR_IMG Position */ -#define LCD_CRSR_IMG155_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos) /*!< LCD CRSR_IMG155: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG156 ---------------------------------------- -#define LCD_CRSR_IMG156_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG156: CRSR_IMG Position */ -#define LCD_CRSR_IMG156_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos) /*!< LCD CRSR_IMG156: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG157 ---------------------------------------- -#define LCD_CRSR_IMG157_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG157: CRSR_IMG Position */ -#define LCD_CRSR_IMG157_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos) /*!< LCD CRSR_IMG157: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG158 ---------------------------------------- -#define LCD_CRSR_IMG158_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG158: CRSR_IMG Position */ -#define LCD_CRSR_IMG158_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos) /*!< LCD CRSR_IMG158: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG159 ---------------------------------------- -#define LCD_CRSR_IMG159_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG159: CRSR_IMG Position */ -#define LCD_CRSR_IMG159_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos) /*!< LCD CRSR_IMG159: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG160 ---------------------------------------- -#define LCD_CRSR_IMG160_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG160: CRSR_IMG Position */ -#define LCD_CRSR_IMG160_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos) /*!< LCD CRSR_IMG160: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG161 ---------------------------------------- -#define LCD_CRSR_IMG161_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG161: CRSR_IMG Position */ -#define LCD_CRSR_IMG161_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos) /*!< LCD CRSR_IMG161: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG162 ---------------------------------------- -#define LCD_CRSR_IMG162_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG162: CRSR_IMG Position */ -#define LCD_CRSR_IMG162_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos) /*!< LCD CRSR_IMG162: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG163 ---------------------------------------- -#define LCD_CRSR_IMG163_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG163: CRSR_IMG Position */ -#define LCD_CRSR_IMG163_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos) /*!< LCD CRSR_IMG163: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG164 ---------------------------------------- -#define LCD_CRSR_IMG164_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG164: CRSR_IMG Position */ -#define LCD_CRSR_IMG164_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos) /*!< LCD CRSR_IMG164: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG165 ---------------------------------------- -#define LCD_CRSR_IMG165_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG165: CRSR_IMG Position */ -#define LCD_CRSR_IMG165_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos) /*!< LCD CRSR_IMG165: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG166 ---------------------------------------- -#define LCD_CRSR_IMG166_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG166: CRSR_IMG Position */ -#define LCD_CRSR_IMG166_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos) /*!< LCD CRSR_IMG166: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG167 ---------------------------------------- -#define LCD_CRSR_IMG167_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG167: CRSR_IMG Position */ -#define LCD_CRSR_IMG167_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos) /*!< LCD CRSR_IMG167: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG168 ---------------------------------------- -#define LCD_CRSR_IMG168_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG168: CRSR_IMG Position */ -#define LCD_CRSR_IMG168_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos) /*!< LCD CRSR_IMG168: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG169 ---------------------------------------- -#define LCD_CRSR_IMG169_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG169: CRSR_IMG Position */ -#define LCD_CRSR_IMG169_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos) /*!< LCD CRSR_IMG169: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG170 ---------------------------------------- -#define LCD_CRSR_IMG170_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG170: CRSR_IMG Position */ -#define LCD_CRSR_IMG170_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos) /*!< LCD CRSR_IMG170: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG171 ---------------------------------------- -#define LCD_CRSR_IMG171_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG171: CRSR_IMG Position */ -#define LCD_CRSR_IMG171_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos) /*!< LCD CRSR_IMG171: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG172 ---------------------------------------- -#define LCD_CRSR_IMG172_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG172: CRSR_IMG Position */ -#define LCD_CRSR_IMG172_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos) /*!< LCD CRSR_IMG172: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG173 ---------------------------------------- -#define LCD_CRSR_IMG173_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG173: CRSR_IMG Position */ -#define LCD_CRSR_IMG173_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos) /*!< LCD CRSR_IMG173: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG174 ---------------------------------------- -#define LCD_CRSR_IMG174_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG174: CRSR_IMG Position */ -#define LCD_CRSR_IMG174_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos) /*!< LCD CRSR_IMG174: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG175 ---------------------------------------- -#define LCD_CRSR_IMG175_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG175: CRSR_IMG Position */ -#define LCD_CRSR_IMG175_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos) /*!< LCD CRSR_IMG175: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG176 ---------------------------------------- -#define LCD_CRSR_IMG176_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG176: CRSR_IMG Position */ -#define LCD_CRSR_IMG176_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos) /*!< LCD CRSR_IMG176: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG177 ---------------------------------------- -#define LCD_CRSR_IMG177_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG177: CRSR_IMG Position */ -#define LCD_CRSR_IMG177_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos) /*!< LCD CRSR_IMG177: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG178 ---------------------------------------- -#define LCD_CRSR_IMG178_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG178: CRSR_IMG Position */ -#define LCD_CRSR_IMG178_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos) /*!< LCD CRSR_IMG178: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG179 ---------------------------------------- -#define LCD_CRSR_IMG179_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG179: CRSR_IMG Position */ -#define LCD_CRSR_IMG179_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos) /*!< LCD CRSR_IMG179: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG180 ---------------------------------------- -#define LCD_CRSR_IMG180_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG180: CRSR_IMG Position */ -#define LCD_CRSR_IMG180_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos) /*!< LCD CRSR_IMG180: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG181 ---------------------------------------- -#define LCD_CRSR_IMG181_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG181: CRSR_IMG Position */ -#define LCD_CRSR_IMG181_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos) /*!< LCD CRSR_IMG181: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG182 ---------------------------------------- -#define LCD_CRSR_IMG182_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG182: CRSR_IMG Position */ -#define LCD_CRSR_IMG182_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos) /*!< LCD CRSR_IMG182: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG183 ---------------------------------------- -#define LCD_CRSR_IMG183_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG183: CRSR_IMG Position */ -#define LCD_CRSR_IMG183_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos) /*!< LCD CRSR_IMG183: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG184 ---------------------------------------- -#define LCD_CRSR_IMG184_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG184: CRSR_IMG Position */ -#define LCD_CRSR_IMG184_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos) /*!< LCD CRSR_IMG184: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG185 ---------------------------------------- -#define LCD_CRSR_IMG185_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG185: CRSR_IMG Position */ -#define LCD_CRSR_IMG185_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos) /*!< LCD CRSR_IMG185: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG186 ---------------------------------------- -#define LCD_CRSR_IMG186_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG186: CRSR_IMG Position */ -#define LCD_CRSR_IMG186_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos) /*!< LCD CRSR_IMG186: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG187 ---------------------------------------- -#define LCD_CRSR_IMG187_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG187: CRSR_IMG Position */ -#define LCD_CRSR_IMG187_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos) /*!< LCD CRSR_IMG187: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG188 ---------------------------------------- -#define LCD_CRSR_IMG188_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG188: CRSR_IMG Position */ -#define LCD_CRSR_IMG188_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos) /*!< LCD CRSR_IMG188: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG189 ---------------------------------------- -#define LCD_CRSR_IMG189_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG189: CRSR_IMG Position */ -#define LCD_CRSR_IMG189_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos) /*!< LCD CRSR_IMG189: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG190 ---------------------------------------- -#define LCD_CRSR_IMG190_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG190: CRSR_IMG Position */ -#define LCD_CRSR_IMG190_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos) /*!< LCD CRSR_IMG190: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG191 ---------------------------------------- -#define LCD_CRSR_IMG191_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG191: CRSR_IMG Position */ -#define LCD_CRSR_IMG191_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos) /*!< LCD CRSR_IMG191: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG192 ---------------------------------------- -#define LCD_CRSR_IMG192_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG192: CRSR_IMG Position */ -#define LCD_CRSR_IMG192_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos) /*!< LCD CRSR_IMG192: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG193 ---------------------------------------- -#define LCD_CRSR_IMG193_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG193: CRSR_IMG Position */ -#define LCD_CRSR_IMG193_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos) /*!< LCD CRSR_IMG193: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG194 ---------------------------------------- -#define LCD_CRSR_IMG194_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG194: CRSR_IMG Position */ -#define LCD_CRSR_IMG194_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos) /*!< LCD CRSR_IMG194: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG195 ---------------------------------------- -#define LCD_CRSR_IMG195_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG195: CRSR_IMG Position */ -#define LCD_CRSR_IMG195_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos) /*!< LCD CRSR_IMG195: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG196 ---------------------------------------- -#define LCD_CRSR_IMG196_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG196: CRSR_IMG Position */ -#define LCD_CRSR_IMG196_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos) /*!< LCD CRSR_IMG196: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG197 ---------------------------------------- -#define LCD_CRSR_IMG197_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG197: CRSR_IMG Position */ -#define LCD_CRSR_IMG197_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos) /*!< LCD CRSR_IMG197: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG198 ---------------------------------------- -#define LCD_CRSR_IMG198_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG198: CRSR_IMG Position */ -#define LCD_CRSR_IMG198_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos) /*!< LCD CRSR_IMG198: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG199 ---------------------------------------- -#define LCD_CRSR_IMG199_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG199: CRSR_IMG Position */ -#define LCD_CRSR_IMG199_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos) /*!< LCD CRSR_IMG199: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG200 ---------------------------------------- -#define LCD_CRSR_IMG200_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG200: CRSR_IMG Position */ -#define LCD_CRSR_IMG200_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos) /*!< LCD CRSR_IMG200: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG201 ---------------------------------------- -#define LCD_CRSR_IMG201_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG201: CRSR_IMG Position */ -#define LCD_CRSR_IMG201_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos) /*!< LCD CRSR_IMG201: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG202 ---------------------------------------- -#define LCD_CRSR_IMG202_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG202: CRSR_IMG Position */ -#define LCD_CRSR_IMG202_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos) /*!< LCD CRSR_IMG202: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG203 ---------------------------------------- -#define LCD_CRSR_IMG203_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG203: CRSR_IMG Position */ -#define LCD_CRSR_IMG203_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos) /*!< LCD CRSR_IMG203: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG204 ---------------------------------------- -#define LCD_CRSR_IMG204_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG204: CRSR_IMG Position */ -#define LCD_CRSR_IMG204_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos) /*!< LCD CRSR_IMG204: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG205 ---------------------------------------- -#define LCD_CRSR_IMG205_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG205: CRSR_IMG Position */ -#define LCD_CRSR_IMG205_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos) /*!< LCD CRSR_IMG205: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG206 ---------------------------------------- -#define LCD_CRSR_IMG206_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG206: CRSR_IMG Position */ -#define LCD_CRSR_IMG206_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos) /*!< LCD CRSR_IMG206: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG207 ---------------------------------------- -#define LCD_CRSR_IMG207_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG207: CRSR_IMG Position */ -#define LCD_CRSR_IMG207_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos) /*!< LCD CRSR_IMG207: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG208 ---------------------------------------- -#define LCD_CRSR_IMG208_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG208: CRSR_IMG Position */ -#define LCD_CRSR_IMG208_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos) /*!< LCD CRSR_IMG208: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG209 ---------------------------------------- -#define LCD_CRSR_IMG209_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG209: CRSR_IMG Position */ -#define LCD_CRSR_IMG209_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos) /*!< LCD CRSR_IMG209: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG210 ---------------------------------------- -#define LCD_CRSR_IMG210_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG210: CRSR_IMG Position */ -#define LCD_CRSR_IMG210_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos) /*!< LCD CRSR_IMG210: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG211 ---------------------------------------- -#define LCD_CRSR_IMG211_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG211: CRSR_IMG Position */ -#define LCD_CRSR_IMG211_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos) /*!< LCD CRSR_IMG211: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG212 ---------------------------------------- -#define LCD_CRSR_IMG212_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG212: CRSR_IMG Position */ -#define LCD_CRSR_IMG212_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos) /*!< LCD CRSR_IMG212: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG213 ---------------------------------------- -#define LCD_CRSR_IMG213_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG213: CRSR_IMG Position */ -#define LCD_CRSR_IMG213_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos) /*!< LCD CRSR_IMG213: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG214 ---------------------------------------- -#define LCD_CRSR_IMG214_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG214: CRSR_IMG Position */ -#define LCD_CRSR_IMG214_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos) /*!< LCD CRSR_IMG214: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG215 ---------------------------------------- -#define LCD_CRSR_IMG215_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG215: CRSR_IMG Position */ -#define LCD_CRSR_IMG215_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos) /*!< LCD CRSR_IMG215: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG216 ---------------------------------------- -#define LCD_CRSR_IMG216_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG216: CRSR_IMG Position */ -#define LCD_CRSR_IMG216_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos) /*!< LCD CRSR_IMG216: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG217 ---------------------------------------- -#define LCD_CRSR_IMG217_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG217: CRSR_IMG Position */ -#define LCD_CRSR_IMG217_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos) /*!< LCD CRSR_IMG217: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG218 ---------------------------------------- -#define LCD_CRSR_IMG218_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG218: CRSR_IMG Position */ -#define LCD_CRSR_IMG218_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos) /*!< LCD CRSR_IMG218: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG219 ---------------------------------------- -#define LCD_CRSR_IMG219_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG219: CRSR_IMG Position */ -#define LCD_CRSR_IMG219_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos) /*!< LCD CRSR_IMG219: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG220 ---------------------------------------- -#define LCD_CRSR_IMG220_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG220: CRSR_IMG Position */ -#define LCD_CRSR_IMG220_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos) /*!< LCD CRSR_IMG220: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG221 ---------------------------------------- -#define LCD_CRSR_IMG221_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG221: CRSR_IMG Position */ -#define LCD_CRSR_IMG221_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos) /*!< LCD CRSR_IMG221: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG222 ---------------------------------------- -#define LCD_CRSR_IMG222_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG222: CRSR_IMG Position */ -#define LCD_CRSR_IMG222_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos) /*!< LCD CRSR_IMG222: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG223 ---------------------------------------- -#define LCD_CRSR_IMG223_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG223: CRSR_IMG Position */ -#define LCD_CRSR_IMG223_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos) /*!< LCD CRSR_IMG223: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG224 ---------------------------------------- -#define LCD_CRSR_IMG224_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG224: CRSR_IMG Position */ -#define LCD_CRSR_IMG224_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos) /*!< LCD CRSR_IMG224: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG225 ---------------------------------------- -#define LCD_CRSR_IMG225_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG225: CRSR_IMG Position */ -#define LCD_CRSR_IMG225_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos) /*!< LCD CRSR_IMG225: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG226 ---------------------------------------- -#define LCD_CRSR_IMG226_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG226: CRSR_IMG Position */ -#define LCD_CRSR_IMG226_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos) /*!< LCD CRSR_IMG226: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG227 ---------------------------------------- -#define LCD_CRSR_IMG227_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG227: CRSR_IMG Position */ -#define LCD_CRSR_IMG227_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos) /*!< LCD CRSR_IMG227: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG228 ---------------------------------------- -#define LCD_CRSR_IMG228_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG228: CRSR_IMG Position */ -#define LCD_CRSR_IMG228_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos) /*!< LCD CRSR_IMG228: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG229 ---------------------------------------- -#define LCD_CRSR_IMG229_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG229: CRSR_IMG Position */ -#define LCD_CRSR_IMG229_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos) /*!< LCD CRSR_IMG229: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG230 ---------------------------------------- -#define LCD_CRSR_IMG230_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG230: CRSR_IMG Position */ -#define LCD_CRSR_IMG230_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos) /*!< LCD CRSR_IMG230: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG231 ---------------------------------------- -#define LCD_CRSR_IMG231_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG231: CRSR_IMG Position */ -#define LCD_CRSR_IMG231_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos) /*!< LCD CRSR_IMG231: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG232 ---------------------------------------- -#define LCD_CRSR_IMG232_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG232: CRSR_IMG Position */ -#define LCD_CRSR_IMG232_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos) /*!< LCD CRSR_IMG232: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG233 ---------------------------------------- -#define LCD_CRSR_IMG233_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG233: CRSR_IMG Position */ -#define LCD_CRSR_IMG233_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos) /*!< LCD CRSR_IMG233: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG234 ---------------------------------------- -#define LCD_CRSR_IMG234_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG234: CRSR_IMG Position */ -#define LCD_CRSR_IMG234_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos) /*!< LCD CRSR_IMG234: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG235 ---------------------------------------- -#define LCD_CRSR_IMG235_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG235: CRSR_IMG Position */ -#define LCD_CRSR_IMG235_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos) /*!< LCD CRSR_IMG235: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG236 ---------------------------------------- -#define LCD_CRSR_IMG236_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG236: CRSR_IMG Position */ -#define LCD_CRSR_IMG236_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos) /*!< LCD CRSR_IMG236: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG237 ---------------------------------------- -#define LCD_CRSR_IMG237_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG237: CRSR_IMG Position */ -#define LCD_CRSR_IMG237_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos) /*!< LCD CRSR_IMG237: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG238 ---------------------------------------- -#define LCD_CRSR_IMG238_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG238: CRSR_IMG Position */ -#define LCD_CRSR_IMG238_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos) /*!< LCD CRSR_IMG238: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG239 ---------------------------------------- -#define LCD_CRSR_IMG239_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG239: CRSR_IMG Position */ -#define LCD_CRSR_IMG239_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos) /*!< LCD CRSR_IMG239: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG240 ---------------------------------------- -#define LCD_CRSR_IMG240_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG240: CRSR_IMG Position */ -#define LCD_CRSR_IMG240_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos) /*!< LCD CRSR_IMG240: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG241 ---------------------------------------- -#define LCD_CRSR_IMG241_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG241: CRSR_IMG Position */ -#define LCD_CRSR_IMG241_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos) /*!< LCD CRSR_IMG241: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG242 ---------------------------------------- -#define LCD_CRSR_IMG242_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG242: CRSR_IMG Position */ -#define LCD_CRSR_IMG242_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos) /*!< LCD CRSR_IMG242: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG243 ---------------------------------------- -#define LCD_CRSR_IMG243_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG243: CRSR_IMG Position */ -#define LCD_CRSR_IMG243_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos) /*!< LCD CRSR_IMG243: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG244 ---------------------------------------- -#define LCD_CRSR_IMG244_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG244: CRSR_IMG Position */ -#define LCD_CRSR_IMG244_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos) /*!< LCD CRSR_IMG244: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG245 ---------------------------------------- -#define LCD_CRSR_IMG245_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG245: CRSR_IMG Position */ -#define LCD_CRSR_IMG245_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos) /*!< LCD CRSR_IMG245: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG246 ---------------------------------------- -#define LCD_CRSR_IMG246_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG246: CRSR_IMG Position */ -#define LCD_CRSR_IMG246_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos) /*!< LCD CRSR_IMG246: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG247 ---------------------------------------- -#define LCD_CRSR_IMG247_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG247: CRSR_IMG Position */ -#define LCD_CRSR_IMG247_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos) /*!< LCD CRSR_IMG247: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG248 ---------------------------------------- -#define LCD_CRSR_IMG248_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG248: CRSR_IMG Position */ -#define LCD_CRSR_IMG248_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos) /*!< LCD CRSR_IMG248: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG249 ---------------------------------------- -#define LCD_CRSR_IMG249_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG249: CRSR_IMG Position */ -#define LCD_CRSR_IMG249_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos) /*!< LCD CRSR_IMG249: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG250 ---------------------------------------- -#define LCD_CRSR_IMG250_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG250: CRSR_IMG Position */ -#define LCD_CRSR_IMG250_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos) /*!< LCD CRSR_IMG250: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG251 ---------------------------------------- -#define LCD_CRSR_IMG251_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG251: CRSR_IMG Position */ -#define LCD_CRSR_IMG251_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos) /*!< LCD CRSR_IMG251: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG252 ---------------------------------------- -#define LCD_CRSR_IMG252_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG252: CRSR_IMG Position */ -#define LCD_CRSR_IMG252_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos) /*!< LCD CRSR_IMG252: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG253 ---------------------------------------- -#define LCD_CRSR_IMG253_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG253: CRSR_IMG Position */ -#define LCD_CRSR_IMG253_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos) /*!< LCD CRSR_IMG253: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG254 ---------------------------------------- -#define LCD_CRSR_IMG254_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG254: CRSR_IMG Position */ -#define LCD_CRSR_IMG254_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos) /*!< LCD CRSR_IMG254: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG255 ---------------------------------------- -#define LCD_CRSR_IMG255_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG255: CRSR_IMG Position */ -#define LCD_CRSR_IMG255_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos) /*!< LCD CRSR_IMG255: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_CTRL ----------------------------------------- -#define LCD_CRSR_CTRL_CrsrOn_Pos 0 /*!< LCD CRSR_CTRL: CrsrOn Position */ -#define LCD_CRSR_CTRL_CrsrOn_Msk (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos) /*!< LCD CRSR_CTRL: CrsrOn Mask */ -#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos 4 /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position */ -#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos) /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask */ - -// -------------------------------------- LCD_CRSR_CFG ------------------------------------------ -#define LCD_CRSR_CFG_CrsrSize_Pos 0 /*!< LCD CRSR_CFG: CrsrSize Position */ -#define LCD_CRSR_CFG_CrsrSize_Msk (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos) /*!< LCD CRSR_CFG: CrsrSize Mask */ -#define LCD_CRSR_CFG_FRAMESYNC_Pos 1 /*!< LCD CRSR_CFG: FRAMESYNC Position */ -#define LCD_CRSR_CFG_FRAMESYNC_Msk (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos) /*!< LCD CRSR_CFG: FRAMESYNC Mask */ - -// -------------------------------------- LCD_CRSR_PAL0 ----------------------------------------- -#define LCD_CRSR_PAL0_RED_Pos 0 /*!< LCD CRSR_PAL0: RED Position */ -#define LCD_CRSR_PAL0_RED_Msk (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos) /*!< LCD CRSR_PAL0: RED Mask */ -#define LCD_CRSR_PAL0_GREEN_Pos 8 /*!< LCD CRSR_PAL0: GREEN Position */ -#define LCD_CRSR_PAL0_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos) /*!< LCD CRSR_PAL0: GREEN Mask */ -#define LCD_CRSR_PAL0_BLUE_Pos 16 /*!< LCD CRSR_PAL0: BLUE Position */ -#define LCD_CRSR_PAL0_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos) /*!< LCD CRSR_PAL0: BLUE Mask */ - -// -------------------------------------- LCD_CRSR_PAL1 ----------------------------------------- -#define LCD_CRSR_PAL1_RED_Pos 0 /*!< LCD CRSR_PAL1: RED Position */ -#define LCD_CRSR_PAL1_RED_Msk (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos) /*!< LCD CRSR_PAL1: RED Mask */ -#define LCD_CRSR_PAL1_GREEN_Pos 8 /*!< LCD CRSR_PAL1: GREEN Position */ -#define LCD_CRSR_PAL1_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos) /*!< LCD CRSR_PAL1: GREEN Mask */ -#define LCD_CRSR_PAL1_BLUE_Pos 16 /*!< LCD CRSR_PAL1: BLUE Position */ -#define LCD_CRSR_PAL1_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos) /*!< LCD CRSR_PAL1: BLUE Mask */ - -// --------------------------------------- LCD_CRSR_XY ------------------------------------------ -#define LCD_CRSR_XY_CRSRX_Pos 0 /*!< LCD CRSR_XY: CRSRX Position */ -#define LCD_CRSR_XY_CRSRX_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos) /*!< LCD CRSR_XY: CRSRX Mask */ -#define LCD_CRSR_XY_CRSRY_Pos 16 /*!< LCD CRSR_XY: CRSRY Position */ -#define LCD_CRSR_XY_CRSRY_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos) /*!< LCD CRSR_XY: CRSRY Mask */ - -// -------------------------------------- LCD_CRSR_CLIP ----------------------------------------- -#define LCD_CRSR_CLIP_CRSRCLIPX_Pos 0 /*!< LCD CRSR_CLIP: CRSRCLIPX Position */ -#define LCD_CRSR_CLIP_CRSRCLIPX_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPX Mask */ -#define LCD_CRSR_CLIP_CRSRCLIPY_Pos 8 /*!< LCD CRSR_CLIP: CRSRCLIPY Position */ -#define LCD_CRSR_CLIP_CRSRCLIPY_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPY Mask */ - -// ------------------------------------- LCD_CRSR_INTMSK ---------------------------------------- -#define LCD_CRSR_INTMSK_CRSRIM_Pos 0 /*!< LCD CRSR_INTMSK: CRSRIM Position */ -#define LCD_CRSR_INTMSK_CRSRIM_Msk (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos) /*!< LCD CRSR_INTMSK: CRSRIM Mask */ - -// ------------------------------------- LCD_CRSR_INTCLR ---------------------------------------- -#define LCD_CRSR_INTCLR_CRSRIC_Pos 0 /*!< LCD CRSR_INTCLR: CRSRIC Position */ -#define LCD_CRSR_INTCLR_CRSRIC_Msk (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos) /*!< LCD CRSR_INTCLR: CRSRIC Mask */ - -// ------------------------------------- LCD_CRSR_INTRAW ---------------------------------------- -#define LCD_CRSR_INTRAW_CRSRRIS_Pos 0 /*!< LCD CRSR_INTRAW: CRSRRIS Position */ -#define LCD_CRSR_INTRAW_CRSRRIS_Msk (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos) /*!< LCD CRSR_INTRAW: CRSRRIS Mask */ - -// ------------------------------------ LCD_CRSR_INTSTAT ---------------------------------------- -#define LCD_CRSR_INTSTAT_CRSRMIS_Pos 0 /*!< LCD CRSR_INTSTAT: CRSRMIS Position */ -#define LCD_CRSR_INTSTAT_CRSRMIS_Msk (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos) /*!< LCD CRSR_INTSTAT: CRSRMIS Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- ETHERNET Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------- ETHERNET_MAC_CONFIG -------------------------------------- -#define ETHERNET_MAC_CONFIG_RE_Pos 2 /*!< ETHERNET MAC_CONFIG: RE Position */ -#define ETHERNET_MAC_CONFIG_RE_Msk (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos) /*!< ETHERNET MAC_CONFIG: RE Mask */ -#define ETHERNET_MAC_CONFIG_TE_Pos 3 /*!< ETHERNET MAC_CONFIG: TE Position */ -#define ETHERNET_MAC_CONFIG_TE_Msk (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos) /*!< ETHERNET MAC_CONFIG: TE Mask */ -#define ETHERNET_MAC_CONFIG_DF_Pos 4 /*!< ETHERNET MAC_CONFIG: DF Position */ -#define ETHERNET_MAC_CONFIG_DF_Msk (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos) /*!< ETHERNET MAC_CONFIG: DF Mask */ -#define ETHERNET_MAC_CONFIG_BL_Pos 5 /*!< ETHERNET MAC_CONFIG: BL Position */ -#define ETHERNET_MAC_CONFIG_BL_Msk (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos) /*!< ETHERNET MAC_CONFIG: BL Mask */ -#define ETHERNET_MAC_CONFIG_ACS_Pos 7 /*!< ETHERNET MAC_CONFIG: ACS Position */ -#define ETHERNET_MAC_CONFIG_ACS_Msk (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos) /*!< ETHERNET MAC_CONFIG: ACS Mask */ -#define ETHERNET_MAC_CONFIG_DR_Pos 9 /*!< ETHERNET MAC_CONFIG: DR Position */ -#define ETHERNET_MAC_CONFIG_DR_Msk (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos) /*!< ETHERNET MAC_CONFIG: DR Mask */ -#define ETHERNET_MAC_CONFIG_IPC_Pos 10 /*!< ETHERNET MAC_CONFIG: IPC Position */ -#define ETHERNET_MAC_CONFIG_IPC_Msk (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos) /*!< ETHERNET MAC_CONFIG: IPC Mask */ -#define ETHERNET_MAC_CONFIG_DM_Pos 11 /*!< ETHERNET MAC_CONFIG: DM Position */ -#define ETHERNET_MAC_CONFIG_DM_Msk (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos) /*!< ETHERNET MAC_CONFIG: DM Mask */ -#define ETHERNET_MAC_CONFIG_LM_Pos 12 /*!< ETHERNET MAC_CONFIG: LM Position */ -#define ETHERNET_MAC_CONFIG_LM_Msk (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos) /*!< ETHERNET MAC_CONFIG: LM Mask */ -#define ETHERNET_MAC_CONFIG_DO_Pos 13 /*!< ETHERNET MAC_CONFIG: DO Position */ -#define ETHERNET_MAC_CONFIG_DO_Msk (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos) /*!< ETHERNET MAC_CONFIG: DO Mask */ -#define ETHERNET_MAC_CONFIG_FES_Pos 14 /*!< ETHERNET MAC_CONFIG: FES Position */ -#define ETHERNET_MAC_CONFIG_FES_Msk (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos) /*!< ETHERNET MAC_CONFIG: FES Mask */ -#define ETHERNET_MAC_CONFIG_PS_Pos 15 /*!< ETHERNET MAC_CONFIG: PS Position */ -#define ETHERNET_MAC_CONFIG_PS_Msk (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos) /*!< ETHERNET MAC_CONFIG: PS Mask */ -#define ETHERNET_MAC_CONFIG_DCRS_Pos 16 /*!< ETHERNET MAC_CONFIG: DCRS Position */ -#define ETHERNET_MAC_CONFIG_DCRS_Msk (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos) /*!< ETHERNET MAC_CONFIG: DCRS Mask */ -#define ETHERNET_MAC_CONFIG_IFG_Pos 17 /*!< ETHERNET MAC_CONFIG: IFG Position */ -#define ETHERNET_MAC_CONFIG_IFG_Msk (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos) /*!< ETHERNET MAC_CONFIG: IFG Mask */ -#define ETHERNET_MAC_CONFIG_JE_Pos 20 /*!< ETHERNET MAC_CONFIG: JE Position */ -#define ETHERNET_MAC_CONFIG_JE_Msk (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos) /*!< ETHERNET MAC_CONFIG: JE Mask */ -#define ETHERNET_MAC_CONFIG_JD_Pos 22 /*!< ETHERNET MAC_CONFIG: JD Position */ -#define ETHERNET_MAC_CONFIG_JD_Msk (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos) /*!< ETHERNET MAC_CONFIG: JD Mask */ -#define ETHERNET_MAC_CONFIG_WD_Pos 23 /*!< ETHERNET MAC_CONFIG: WD Position */ -#define ETHERNET_MAC_CONFIG_WD_Msk (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos) /*!< ETHERNET MAC_CONFIG: WD Mask */ - -// -------------------------------- ETHERNET_MAC_FRAME_FILTER ----------------------------------- -#define ETHERNET_MAC_FRAME_FILTER_PR_Pos 0 /*!< ETHERNET MAC_FRAME_FILTER: PR Position */ -#define ETHERNET_MAC_FRAME_FILTER_PR_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PR Mask */ -#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos 3 /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */ -#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_PM_Pos 4 /*!< ETHERNET MAC_FRAME_FILTER: PM Position */ -#define ETHERNET_MAC_FRAME_FILTER_PM_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PM Mask */ -#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos 5 /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */ -#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos 6 /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */ -#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos 8 /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */ -#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos 9 /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */ -#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_RA_Pos 31 /*!< ETHERNET MAC_FRAME_FILTER: RA Position */ -#define ETHERNET_MAC_FRAME_FILTER_RA_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos) /*!< ETHERNET MAC_FRAME_FILTER: RA Mask */ - -// ------------------------------- ETHERNET_MAC_HASHTABLE_HIGH ---------------------------------- -#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos 0 /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */ -#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos) /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */ - -// ------------------------------- ETHERNET_MAC_HASHTABLE_LOW ----------------------------------- -#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos 0 /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */ -#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos) /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */ - -// ---------------------------------- ETHERNET_MAC_MII_ADDR ------------------------------------- -#define ETHERNET_MAC_MII_ADDR_GB_Pos 0 /*!< ETHERNET MAC_MII_ADDR: GB Position */ -#define ETHERNET_MAC_MII_ADDR_GB_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos) /*!< ETHERNET MAC_MII_ADDR: GB Mask */ -#define ETHERNET_MAC_MII_ADDR_W_Pos 1 /*!< ETHERNET MAC_MII_ADDR: W Position */ -#define ETHERNET_MAC_MII_ADDR_W_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos) /*!< ETHERNET MAC_MII_ADDR: W Mask */ -#define ETHERNET_MAC_MII_ADDR_CR_Pos 2 /*!< ETHERNET MAC_MII_ADDR: CR Position */ -#define ETHERNET_MAC_MII_ADDR_CR_Msk (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos) /*!< ETHERNET MAC_MII_ADDR: CR Mask */ -#define ETHERNET_MAC_MII_ADDR_GR_Pos 6 /*!< ETHERNET MAC_MII_ADDR: GR Position */ -#define ETHERNET_MAC_MII_ADDR_GR_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos) /*!< ETHERNET MAC_MII_ADDR: GR Mask */ -#define ETHERNET_MAC_MII_ADDR_PA_Pos 11 /*!< ETHERNET MAC_MII_ADDR: PA Position */ -#define ETHERNET_MAC_MII_ADDR_PA_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos) /*!< ETHERNET MAC_MII_ADDR: PA Mask */ - -// ---------------------------------- ETHERNET_MAC_MII_DATA ------------------------------------- -#define ETHERNET_MAC_MII_DATA_GD_Pos 0 /*!< ETHERNET MAC_MII_DATA: GD Position */ -#define ETHERNET_MAC_MII_DATA_GD_Msk (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos) /*!< ETHERNET MAC_MII_DATA: GD Mask */ - -// --------------------------------- ETHERNET_MAC_FLOW_CTRL ------------------------------------- -#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos 0 /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */ -#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos) /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask */ -#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos 1 /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */ -#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask */ -#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos 2 /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */ -#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask */ -#define ETHERNET_MAC_FLOW_CTRL_UP_Pos 3 /*!< ETHERNET MAC_FLOW_CTRL: UP Position */ -#define ETHERNET_MAC_FLOW_CTRL_UP_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos) /*!< ETHERNET MAC_FLOW_CTRL: UP Mask */ -#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos 4 /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */ -#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask */ -#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos 7 /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */ -#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos) /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask */ -#define ETHERNET_MAC_FLOW_CTRL_PT_Pos 16 /*!< ETHERNET MAC_FLOW_CTRL: PT Position */ -#define ETHERNET_MAC_FLOW_CTRL_PT_Msk (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PT Mask */ - -// ---------------------------------- ETHERNET_MAC_VLAN_TAG ------------------------------------- -#define ETHERNET_MAC_VLAN_TAG_VL_Pos 0 /*!< ETHERNET MAC_VLAN_TAG: VL Position */ -#define ETHERNET_MAC_VLAN_TAG_VL_Msk (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos) /*!< ETHERNET MAC_VLAN_TAG: VL Mask */ -#define ETHERNET_MAC_VLAN_TAG_ETV_Pos 16 /*!< ETHERNET MAC_VLAN_TAG: ETV Position */ -#define ETHERNET_MAC_VLAN_TAG_ETV_Msk (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos) /*!< ETHERNET MAC_VLAN_TAG: ETV Mask */ - -// ----------------------------------- ETHERNET_MAC_DEBUG --------------------------------------- -#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos 0 /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */ -#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */ -#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos 1 /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */ -#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos) /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask */ -#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos 4 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */ -#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */ -#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos 5 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */ -#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */ -#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos 8 /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */ -#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask */ -#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos 16 /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */ -#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */ -#define ETHERNET_MAC_DEBUG_TXSTAT_Pos 17 /*!< ETHERNET MAC_DEBUG: TXSTAT Position */ -#define ETHERNET_MAC_DEBUG_TXSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXSTAT Mask */ -#define ETHERNET_MAC_DEBUG_PAUSE_Pos 19 /*!< ETHERNET MAC_DEBUG: PAUSE Position */ -#define ETHERNET_MAC_DEBUG_PAUSE_Msk (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos) /*!< ETHERNET MAC_DEBUG: PAUSE Mask */ -#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos 20 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */ -#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */ -#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos 22 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */ -#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */ -#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos 24 /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */ -#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask */ -#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos 25 /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */ -#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */ - -// -------------------------------- ETHERNET_MAC_RWAKE_FRFLT ------------------------------------ -#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos 0 /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */ -#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos) /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */ - -// ------------------------------- ETHERNET_MAC_PMT_CTRL_STAT ----------------------------------- -#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos 0 /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos 1 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos 2 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos 5 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos 6 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos 9 /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos 31 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */ - -// --------------------------------- ETHERNET_MAC_INTR_MASK ------------------------------------- -#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos 3 /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */ -#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos) /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */ - -// --------------------------------- ETHERNET_MAC_ADDR0_HIGH ------------------------------------ -#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos 0 /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */ -#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */ -#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos 31 /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */ -#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask */ - -// --------------------------------- ETHERNET_MAC_ADDR0_LOW ------------------------------------- -#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos 0 /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */ -#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos) /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask */ - -// -------------------------------- ETHERNET_MAC_TIMESTP_CTRL ----------------------------------- -#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos 0 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos 1 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos 2 /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos 3 /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos 4 /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos 5 /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos 8 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos 9 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos 10 /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos 11 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos 12 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos 13 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos 14 /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos 15 /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos 16 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos 18 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */ - -// ---------------------------------- ETHERNET_DMA_BUS_MODE ------------------------------------- -#define ETHERNET_DMA_BUS_MODE_SWR_Pos 0 /*!< ETHERNET DMA_BUS_MODE: SWR Position */ -#define ETHERNET_DMA_BUS_MODE_SWR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos) /*!< ETHERNET DMA_BUS_MODE: SWR Mask */ -#define ETHERNET_DMA_BUS_MODE_DA_Pos 1 /*!< ETHERNET DMA_BUS_MODE: DA Position */ -#define ETHERNET_DMA_BUS_MODE_DA_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos) /*!< ETHERNET DMA_BUS_MODE: DA Mask */ -#define ETHERNET_DMA_BUS_MODE_DSL_Pos 2 /*!< ETHERNET DMA_BUS_MODE: DSL Position */ -#define ETHERNET_DMA_BUS_MODE_DSL_Msk (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos) /*!< ETHERNET DMA_BUS_MODE: DSL Mask */ -#define ETHERNET_DMA_BUS_MODE_ATDS_Pos 7 /*!< ETHERNET DMA_BUS_MODE: ATDS Position */ -#define ETHERNET_DMA_BUS_MODE_ATDS_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos) /*!< ETHERNET DMA_BUS_MODE: ATDS Mask */ -#define ETHERNET_DMA_BUS_MODE_PBL_Pos 8 /*!< ETHERNET DMA_BUS_MODE: PBL Position */ -#define ETHERNET_DMA_BUS_MODE_PBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL Mask */ -#define ETHERNET_DMA_BUS_MODE_PR_Pos 14 /*!< ETHERNET DMA_BUS_MODE: PR Position */ -#define ETHERNET_DMA_BUS_MODE_PR_Msk (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos) /*!< ETHERNET DMA_BUS_MODE: PR Mask */ -#define ETHERNET_DMA_BUS_MODE_FB_Pos 16 /*!< ETHERNET DMA_BUS_MODE: FB Position */ -#define ETHERNET_DMA_BUS_MODE_FB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos) /*!< ETHERNET DMA_BUS_MODE: FB Mask */ -#define ETHERNET_DMA_BUS_MODE_RPBL_Pos 17 /*!< ETHERNET DMA_BUS_MODE: RPBL Position */ -#define ETHERNET_DMA_BUS_MODE_RPBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos) /*!< ETHERNET DMA_BUS_MODE: RPBL Mask */ -#define ETHERNET_DMA_BUS_MODE_USP_Pos 23 /*!< ETHERNET DMA_BUS_MODE: USP Position */ -#define ETHERNET_DMA_BUS_MODE_USP_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos) /*!< ETHERNET DMA_BUS_MODE: USP Mask */ -#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos 24 /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */ -#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask */ -#define ETHERNET_DMA_BUS_MODE_AAL_Pos 25 /*!< ETHERNET DMA_BUS_MODE: AAL Position */ -#define ETHERNET_DMA_BUS_MODE_AAL_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos) /*!< ETHERNET DMA_BUS_MODE: AAL Mask */ -#define ETHERNET_DMA_BUS_MODE_MB_Pos 26 /*!< ETHERNET DMA_BUS_MODE: MB Position */ -#define ETHERNET_DMA_BUS_MODE_MB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos) /*!< ETHERNET DMA_BUS_MODE: MB Mask */ -#define ETHERNET_DMA_BUS_MODE_TXPR_Pos 27 /*!< ETHERNET DMA_BUS_MODE: TXPR Position */ -#define ETHERNET_DMA_BUS_MODE_TXPR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos) /*!< ETHERNET DMA_BUS_MODE: TXPR Mask */ - -// ----------------------------- ETHERNET_DMA_TRANS_POLL_DEMAND --------------------------------- -#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos 0 /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */ -#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos) /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */ - -// ------------------------------ ETHERNET_DMA_REC_POLL_DEMAND ---------------------------------- -#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos 0 /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */ -#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos) /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */ - -// -------------------------------- ETHERNET_DMA_REC_DES_ADDR ----------------------------------- -#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */ -#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */ - -// ------------------------------- ETHERNET_DMA_TRANS_DES_ADDR ---------------------------------- -#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */ -#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */ - -// ------------------------------------ ETHERNET_DMA_STAT --------------------------------------- -#define ETHERNET_DMA_STAT_TI_Pos 0 /*!< ETHERNET DMA_STAT: TI Position */ -#define ETHERNET_DMA_STAT_TI_Msk (0x01UL << ETHERNET_DMA_STAT_TI_Pos) /*!< ETHERNET DMA_STAT: TI Mask */ -#define ETHERNET_DMA_STAT_TPS_Pos 1 /*!< ETHERNET DMA_STAT: TPS Position */ -#define ETHERNET_DMA_STAT_TPS_Msk (0x01UL << ETHERNET_DMA_STAT_TPS_Pos) /*!< ETHERNET DMA_STAT: TPS Mask */ -#define ETHERNET_DMA_STAT_TU_Pos 2 /*!< ETHERNET DMA_STAT: TU Position */ -#define ETHERNET_DMA_STAT_TU_Msk (0x01UL << ETHERNET_DMA_STAT_TU_Pos) /*!< ETHERNET DMA_STAT: TU Mask */ -#define ETHERNET_DMA_STAT_TJT_Pos 3 /*!< ETHERNET DMA_STAT: TJT Position */ -#define ETHERNET_DMA_STAT_TJT_Msk (0x01UL << ETHERNET_DMA_STAT_TJT_Pos) /*!< ETHERNET DMA_STAT: TJT Mask */ -#define ETHERNET_DMA_STAT_OVF_Pos 4 /*!< ETHERNET DMA_STAT: OVF Position */ -#define ETHERNET_DMA_STAT_OVF_Msk (0x01UL << ETHERNET_DMA_STAT_OVF_Pos) /*!< ETHERNET DMA_STAT: OVF Mask */ -#define ETHERNET_DMA_STAT_UNF_Pos 5 /*!< ETHERNET DMA_STAT: UNF Position */ -#define ETHERNET_DMA_STAT_UNF_Msk (0x01UL << ETHERNET_DMA_STAT_UNF_Pos) /*!< ETHERNET DMA_STAT: UNF Mask */ -#define ETHERNET_DMA_STAT_RI_Pos 6 /*!< ETHERNET DMA_STAT: RI Position */ -#define ETHERNET_DMA_STAT_RI_Msk (0x01UL << ETHERNET_DMA_STAT_RI_Pos) /*!< ETHERNET DMA_STAT: RI Mask */ -#define ETHERNET_DMA_STAT_RU_Pos 7 /*!< ETHERNET DMA_STAT: RU Position */ -#define ETHERNET_DMA_STAT_RU_Msk (0x01UL << ETHERNET_DMA_STAT_RU_Pos) /*!< ETHERNET DMA_STAT: RU Mask */ -#define ETHERNET_DMA_STAT_RPS_Pos 8 /*!< ETHERNET DMA_STAT: RPS Position */ -#define ETHERNET_DMA_STAT_RPS_Msk (0x01UL << ETHERNET_DMA_STAT_RPS_Pos) /*!< ETHERNET DMA_STAT: RPS Mask */ -#define ETHERNET_DMA_STAT_RWT_Pos 9 /*!< ETHERNET DMA_STAT: RWT Position */ -#define ETHERNET_DMA_STAT_RWT_Msk (0x01UL << ETHERNET_DMA_STAT_RWT_Pos) /*!< ETHERNET DMA_STAT: RWT Mask */ -#define ETHERNET_DMA_STAT_ETI_Pos 10 /*!< ETHERNET DMA_STAT: ETI Position */ -#define ETHERNET_DMA_STAT_ETI_Msk (0x01UL << ETHERNET_DMA_STAT_ETI_Pos) /*!< ETHERNET DMA_STAT: ETI Mask */ -#define ETHERNET_DMA_STAT_FBI_Pos 13 /*!< ETHERNET DMA_STAT: FBI Position */ -#define ETHERNET_DMA_STAT_FBI_Msk (0x01UL << ETHERNET_DMA_STAT_FBI_Pos) /*!< ETHERNET DMA_STAT: FBI Mask */ -#define ETHERNET_DMA_STAT_ERI_Pos 14 /*!< ETHERNET DMA_STAT: ERI Position */ -#define ETHERNET_DMA_STAT_ERI_Msk (0x01UL << ETHERNET_DMA_STAT_ERI_Pos) /*!< ETHERNET DMA_STAT: ERI Mask */ -#define ETHERNET_DMA_STAT_AIE_Pos 15 /*!< ETHERNET DMA_STAT: AIE Position */ -#define ETHERNET_DMA_STAT_AIE_Msk (0x01UL << ETHERNET_DMA_STAT_AIE_Pos) /*!< ETHERNET DMA_STAT: AIE Mask */ -#define ETHERNET_DMA_STAT_NIS_Pos 16 /*!< ETHERNET DMA_STAT: NIS Position */ -#define ETHERNET_DMA_STAT_NIS_Msk (0x01UL << ETHERNET_DMA_STAT_NIS_Pos) /*!< ETHERNET DMA_STAT: NIS Mask */ - -// ---------------------------------- ETHERNET_DMA_OP_MODE -------------------------------------- -#define ETHERNET_DMA_OP_MODE_SR_Pos 1 /*!< ETHERNET DMA_OP_MODE: SR Position */ -#define ETHERNET_DMA_OP_MODE_SR_Msk (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos) /*!< ETHERNET DMA_OP_MODE: SR Mask */ -#define ETHERNET_DMA_OP_MODE_OSF_Pos 2 /*!< ETHERNET DMA_OP_MODE: OSF Position */ -#define ETHERNET_DMA_OP_MODE_OSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos) /*!< ETHERNET DMA_OP_MODE: OSF Mask */ -#define ETHERNET_DMA_OP_MODE_RTC_Pos 3 /*!< ETHERNET DMA_OP_MODE: RTC Position */ -#define ETHERNET_DMA_OP_MODE_RTC_Msk (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos) /*!< ETHERNET DMA_OP_MODE: RTC Mask */ -#define ETHERNET_DMA_OP_MODE_FUF_Pos 6 /*!< ETHERNET DMA_OP_MODE: FUF Position */ -#define ETHERNET_DMA_OP_MODE_FUF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos) /*!< ETHERNET DMA_OP_MODE: FUF Mask */ -#define ETHERNET_DMA_OP_MODE_FEF_Pos 7 /*!< ETHERNET DMA_OP_MODE: FEF Position */ -#define ETHERNET_DMA_OP_MODE_FEF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos) /*!< ETHERNET DMA_OP_MODE: FEF Mask */ -#define ETHERNET_DMA_OP_MODE_ST_Pos 13 /*!< ETHERNET DMA_OP_MODE: ST Position */ -#define ETHERNET_DMA_OP_MODE_ST_Msk (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos) /*!< ETHERNET DMA_OP_MODE: ST Mask */ -#define ETHERNET_DMA_OP_MODE_TTC_Pos 14 /*!< ETHERNET DMA_OP_MODE: TTC Position */ -#define ETHERNET_DMA_OP_MODE_TTC_Msk (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos) /*!< ETHERNET DMA_OP_MODE: TTC Mask */ -#define ETHERNET_DMA_OP_MODE_FTF_Pos 20 /*!< ETHERNET DMA_OP_MODE: FTF Position */ -#define ETHERNET_DMA_OP_MODE_FTF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos) /*!< ETHERNET DMA_OP_MODE: FTF Mask */ -#define ETHERNET_DMA_OP_MODE_TSF_Pos 21 /*!< ETHERNET DMA_OP_MODE: TSF Position */ -#define ETHERNET_DMA_OP_MODE_TSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos) /*!< ETHERNET DMA_OP_MODE: TSF Mask */ -#define ETHERNET_DMA_OP_MODE_DFF_Pos 24 /*!< ETHERNET DMA_OP_MODE: DFF Position */ -#define ETHERNET_DMA_OP_MODE_DFF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos) /*!< ETHERNET DMA_OP_MODE: DFF Mask */ -#define ETHERNET_DMA_OP_MODE_RSF_Pos 25 /*!< ETHERNET DMA_OP_MODE: RSF Position */ -#define ETHERNET_DMA_OP_MODE_RSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos) /*!< ETHERNET DMA_OP_MODE: RSF Mask */ -#define ETHERNET_DMA_OP_MODE_DT_Pos 26 /*!< ETHERNET DMA_OP_MODE: DT Position */ -#define ETHERNET_DMA_OP_MODE_DT_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos) /*!< ETHERNET DMA_OP_MODE: DT Mask */ - -// ----------------------------------- ETHERNET_DMA_INT_EN -------------------------------------- -#define ETHERNET_DMA_INT_EN_TIE_Pos 0 /*!< ETHERNET DMA_INT_EN: TIE Position */ -#define ETHERNET_DMA_INT_EN_TIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos) /*!< ETHERNET DMA_INT_EN: TIE Mask */ -#define ETHERNET_DMA_INT_EN_TSE_Pos 1 /*!< ETHERNET DMA_INT_EN: TSE Position */ -#define ETHERNET_DMA_INT_EN_TSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos) /*!< ETHERNET DMA_INT_EN: TSE Mask */ -#define ETHERNET_DMA_INT_EN_TUE_Pos 2 /*!< ETHERNET DMA_INT_EN: TUE Position */ -#define ETHERNET_DMA_INT_EN_TUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos) /*!< ETHERNET DMA_INT_EN: TUE Mask */ -#define ETHERNET_DMA_INT_EN_TJE_Pos 3 /*!< ETHERNET DMA_INT_EN: TJE Position */ -#define ETHERNET_DMA_INT_EN_TJE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos) /*!< ETHERNET DMA_INT_EN: TJE Mask */ -#define ETHERNET_DMA_INT_EN_OVE_Pos 4 /*!< ETHERNET DMA_INT_EN: OVE Position */ -#define ETHERNET_DMA_INT_EN_OVE_Msk (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos) /*!< ETHERNET DMA_INT_EN: OVE Mask */ -#define ETHERNET_DMA_INT_EN_UNE_Pos 5 /*!< ETHERNET DMA_INT_EN: UNE Position */ -#define ETHERNET_DMA_INT_EN_UNE_Msk (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos) /*!< ETHERNET DMA_INT_EN: UNE Mask */ -#define ETHERNET_DMA_INT_EN_RIE_Pos 6 /*!< ETHERNET DMA_INT_EN: RIE Position */ -#define ETHERNET_DMA_INT_EN_RIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos) /*!< ETHERNET DMA_INT_EN: RIE Mask */ -#define ETHERNET_DMA_INT_EN_RUE_Pos 7 /*!< ETHERNET DMA_INT_EN: RUE Position */ -#define ETHERNET_DMA_INT_EN_RUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos) /*!< ETHERNET DMA_INT_EN: RUE Mask */ -#define ETHERNET_DMA_INT_EN_RSE_Pos 8 /*!< ETHERNET DMA_INT_EN: RSE Position */ -#define ETHERNET_DMA_INT_EN_RSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos) /*!< ETHERNET DMA_INT_EN: RSE Mask */ -#define ETHERNET_DMA_INT_EN_RWE_Pos 9 /*!< ETHERNET DMA_INT_EN: RWE Position */ -#define ETHERNET_DMA_INT_EN_RWE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos) /*!< ETHERNET DMA_INT_EN: RWE Mask */ -#define ETHERNET_DMA_INT_EN_ETE_Pos 10 /*!< ETHERNET DMA_INT_EN: ETE Position */ -#define ETHERNET_DMA_INT_EN_ETE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos) /*!< ETHERNET DMA_INT_EN: ETE Mask */ -#define ETHERNET_DMA_INT_EN_FBE_Pos 13 /*!< ETHERNET DMA_INT_EN: FBE Position */ -#define ETHERNET_DMA_INT_EN_FBE_Msk (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos) /*!< ETHERNET DMA_INT_EN: FBE Mask */ -#define ETHERNET_DMA_INT_EN_ERE_Pos 14 /*!< ETHERNET DMA_INT_EN: ERE Position */ -#define ETHERNET_DMA_INT_EN_ERE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos) /*!< ETHERNET DMA_INT_EN: ERE Mask */ -#define ETHERNET_DMA_INT_EN_AIE_Pos 15 /*!< ETHERNET DMA_INT_EN: AIE Position */ -#define ETHERNET_DMA_INT_EN_AIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos) /*!< ETHERNET DMA_INT_EN: AIE Mask */ -#define ETHERNET_DMA_INT_EN_NIE_Pos 16 /*!< ETHERNET DMA_INT_EN: NIE Position */ -#define ETHERNET_DMA_INT_EN_NIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos) /*!< ETHERNET DMA_INT_EN: NIE Mask */ - -// --------------------------------- ETHERNET_DMA_MFRM_BUFOF ------------------------------------ -#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos 0 /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */ -#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask */ -#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos 16 /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */ -#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask */ -#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos 17 /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */ -#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask */ -#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos 28 /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */ -#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask */ - -// -------------------------------- ETHERNET_DMA_REC_INT_WDT ------------------------------------ -#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos 0 /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */ -#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos) /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */ - -// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_DES --------------------------------- -#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */ -#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */ - -// ------------------------------ ETHERNET_DMA_CURHOST_REC_DES ---------------------------------- -#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */ -#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos) /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */ - -// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_BUF --------------------------------- -#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */ -#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */ - -// ------------------------------ ETHERNET_DMA_CURHOST_REC_BUF ---------------------------------- -#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */ -#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos) /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- ATIMER Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------- ATIMER_DOWNCOUNTER --------------------------------------- -#define ATIMER_DOWNCOUNTER_CVAL_Pos 0 /*!< ATIMER DOWNCOUNTER: CVAL Position */ -#define ATIMER_DOWNCOUNTER_CVAL_Msk (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos) /*!< ATIMER DOWNCOUNTER: CVAL Mask */ - -// -------------------------------------- ATIMER_PRESET ----------------------------------------- -#define ATIMER_PRESET_PRESETVAL_Pos 0 /*!< ATIMER PRESET: PRESETVAL Position */ -#define ATIMER_PRESET_PRESETVAL_Msk (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos) /*!< ATIMER PRESET: PRESETVAL Mask */ - -// -------------------------------------- ATIMER_CLR_EN ----------------------------------------- -#define ATIMER_CLR_EN_CLR_EN_Pos 0 /*!< ATIMER CLR_EN: CLR_EN Position */ -#define ATIMER_CLR_EN_CLR_EN_Msk (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos) /*!< ATIMER CLR_EN: CLR_EN Mask */ - -// -------------------------------------- ATIMER_SET_EN ----------------------------------------- -#define ATIMER_SET_EN_SET_EN_Pos 0 /*!< ATIMER SET_EN: SET_EN Position */ -#define ATIMER_SET_EN_SET_EN_Msk (0x01UL << ATIMER_SET_EN_SET_EN_Pos) /*!< ATIMER SET_EN: SET_EN Mask */ - -// -------------------------------------- ATIMER_STATUS ----------------------------------------- -#define ATIMER_STATUS_STAT_Pos 0 /*!< ATIMER STATUS: STAT Position */ -#define ATIMER_STATUS_STAT_Msk (0x01UL << ATIMER_STATUS_STAT_Pos) /*!< ATIMER STATUS: STAT Mask */ - -// -------------------------------------- ATIMER_ENABLE ----------------------------------------- -#define ATIMER_ENABLE_EN_Pos 0 /*!< ATIMER ENABLE: EN Position */ -#define ATIMER_ENABLE_EN_Msk (0x01UL << ATIMER_ENABLE_EN_Pos) /*!< ATIMER ENABLE: EN Mask */ - -// ------------------------------------- ATIMER_CLR_STAT ---------------------------------------- -#define ATIMER_CLR_STAT_CSTAT_Pos 0 /*!< ATIMER CLR_STAT: CSTAT Position */ -#define ATIMER_CLR_STAT_CSTAT_Msk (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos) /*!< ATIMER CLR_STAT: CSTAT Mask */ - -// ------------------------------------- ATIMER_SET_STAT ---------------------------------------- -#define ATIMER_SET_STAT_SSTAT_Pos 0 /*!< ATIMER SET_STAT: SSTAT Position */ -#define ATIMER_SET_STAT_SSTAT_Msk (0x01UL << ATIMER_SET_STAT_SSTAT_Pos) /*!< ATIMER SET_STAT: SSTAT Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- REGFILE Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------ REGFILE_REGFILE0 ---------------------------------------- -#define REGFILE_REGFILE0_REGVAL_Pos 0 /*!< REGFILE REGFILE0: REGVAL Position */ -#define REGFILE_REGFILE0_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos) /*!< REGFILE REGFILE0: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE1 ---------------------------------------- -#define REGFILE_REGFILE1_REGVAL_Pos 0 /*!< REGFILE REGFILE1: REGVAL Position */ -#define REGFILE_REGFILE1_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos) /*!< REGFILE REGFILE1: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE2 ---------------------------------------- -#define REGFILE_REGFILE2_REGVAL_Pos 0 /*!< REGFILE REGFILE2: REGVAL Position */ -#define REGFILE_REGFILE2_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos) /*!< REGFILE REGFILE2: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE3 ---------------------------------------- -#define REGFILE_REGFILE3_REGVAL_Pos 0 /*!< REGFILE REGFILE3: REGVAL Position */ -#define REGFILE_REGFILE3_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos) /*!< REGFILE REGFILE3: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE4 ---------------------------------------- -#define REGFILE_REGFILE4_REGVAL_Pos 0 /*!< REGFILE REGFILE4: REGVAL Position */ -#define REGFILE_REGFILE4_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos) /*!< REGFILE REGFILE4: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE5 ---------------------------------------- -#define REGFILE_REGFILE5_REGVAL_Pos 0 /*!< REGFILE REGFILE5: REGVAL Position */ -#define REGFILE_REGFILE5_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos) /*!< REGFILE REGFILE5: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE6 ---------------------------------------- -#define REGFILE_REGFILE6_REGVAL_Pos 0 /*!< REGFILE REGFILE6: REGVAL Position */ -#define REGFILE_REGFILE6_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos) /*!< REGFILE REGFILE6: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE7 ---------------------------------------- -#define REGFILE_REGFILE7_REGVAL_Pos 0 /*!< REGFILE REGFILE7: REGVAL Position */ -#define REGFILE_REGFILE7_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos) /*!< REGFILE REGFILE7: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE8 ---------------------------------------- -#define REGFILE_REGFILE8_REGVAL_Pos 0 /*!< REGFILE REGFILE8: REGVAL Position */ -#define REGFILE_REGFILE8_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos) /*!< REGFILE REGFILE8: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE9 ---------------------------------------- -#define REGFILE_REGFILE9_REGVAL_Pos 0 /*!< REGFILE REGFILE9: REGVAL Position */ -#define REGFILE_REGFILE9_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos) /*!< REGFILE REGFILE9: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE10 --------------------------------------- -#define REGFILE_REGFILE10_REGVAL_Pos 0 /*!< REGFILE REGFILE10: REGVAL Position */ -#define REGFILE_REGFILE10_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos) /*!< REGFILE REGFILE10: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE11 --------------------------------------- -#define REGFILE_REGFILE11_REGVAL_Pos 0 /*!< REGFILE REGFILE11: REGVAL Position */ -#define REGFILE_REGFILE11_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos) /*!< REGFILE REGFILE11: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE12 --------------------------------------- -#define REGFILE_REGFILE12_REGVAL_Pos 0 /*!< REGFILE REGFILE12: REGVAL Position */ -#define REGFILE_REGFILE12_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos) /*!< REGFILE REGFILE12: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE13 --------------------------------------- -#define REGFILE_REGFILE13_REGVAL_Pos 0 /*!< REGFILE REGFILE13: REGVAL Position */ -#define REGFILE_REGFILE13_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos) /*!< REGFILE REGFILE13: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE14 --------------------------------------- -#define REGFILE_REGFILE14_REGVAL_Pos 0 /*!< REGFILE REGFILE14: REGVAL Position */ -#define REGFILE_REGFILE14_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos) /*!< REGFILE REGFILE14: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE15 --------------------------------------- -#define REGFILE_REGFILE15_REGVAL_Pos 0 /*!< REGFILE REGFILE15: REGVAL Position */ -#define REGFILE_REGFILE15_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos) /*!< REGFILE REGFILE15: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE16 --------------------------------------- -#define REGFILE_REGFILE16_REGVAL_Pos 0 /*!< REGFILE REGFILE16: REGVAL Position */ -#define REGFILE_REGFILE16_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos) /*!< REGFILE REGFILE16: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE17 --------------------------------------- -#define REGFILE_REGFILE17_REGVAL_Pos 0 /*!< REGFILE REGFILE17: REGVAL Position */ -#define REGFILE_REGFILE17_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos) /*!< REGFILE REGFILE17: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE18 --------------------------------------- -#define REGFILE_REGFILE18_REGVAL_Pos 0 /*!< REGFILE REGFILE18: REGVAL Position */ -#define REGFILE_REGFILE18_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos) /*!< REGFILE REGFILE18: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE19 --------------------------------------- -#define REGFILE_REGFILE19_REGVAL_Pos 0 /*!< REGFILE REGFILE19: REGVAL Position */ -#define REGFILE_REGFILE19_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos) /*!< REGFILE REGFILE19: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE20 --------------------------------------- -#define REGFILE_REGFILE20_REGVAL_Pos 0 /*!< REGFILE REGFILE20: REGVAL Position */ -#define REGFILE_REGFILE20_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos) /*!< REGFILE REGFILE20: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE21 --------------------------------------- -#define REGFILE_REGFILE21_REGVAL_Pos 0 /*!< REGFILE REGFILE21: REGVAL Position */ -#define REGFILE_REGFILE21_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos) /*!< REGFILE REGFILE21: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE22 --------------------------------------- -#define REGFILE_REGFILE22_REGVAL_Pos 0 /*!< REGFILE REGFILE22: REGVAL Position */ -#define REGFILE_REGFILE22_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos) /*!< REGFILE REGFILE22: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE23 --------------------------------------- -#define REGFILE_REGFILE23_REGVAL_Pos 0 /*!< REGFILE REGFILE23: REGVAL Position */ -#define REGFILE_REGFILE23_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos) /*!< REGFILE REGFILE23: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE24 --------------------------------------- -#define REGFILE_REGFILE24_REGVAL_Pos 0 /*!< REGFILE REGFILE24: REGVAL Position */ -#define REGFILE_REGFILE24_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos) /*!< REGFILE REGFILE24: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE25 --------------------------------------- -#define REGFILE_REGFILE25_REGVAL_Pos 0 /*!< REGFILE REGFILE25: REGVAL Position */ -#define REGFILE_REGFILE25_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos) /*!< REGFILE REGFILE25: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE26 --------------------------------------- -#define REGFILE_REGFILE26_REGVAL_Pos 0 /*!< REGFILE REGFILE26: REGVAL Position */ -#define REGFILE_REGFILE26_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos) /*!< REGFILE REGFILE26: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE27 --------------------------------------- -#define REGFILE_REGFILE27_REGVAL_Pos 0 /*!< REGFILE REGFILE27: REGVAL Position */ -#define REGFILE_REGFILE27_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos) /*!< REGFILE REGFILE27: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE28 --------------------------------------- -#define REGFILE_REGFILE28_REGVAL_Pos 0 /*!< REGFILE REGFILE28: REGVAL Position */ -#define REGFILE_REGFILE28_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos) /*!< REGFILE REGFILE28: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE29 --------------------------------------- -#define REGFILE_REGFILE29_REGVAL_Pos 0 /*!< REGFILE REGFILE29: REGVAL Position */ -#define REGFILE_REGFILE29_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos) /*!< REGFILE REGFILE29: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE30 --------------------------------------- -#define REGFILE_REGFILE30_REGVAL_Pos 0 /*!< REGFILE REGFILE30: REGVAL Position */ -#define REGFILE_REGFILE30_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos) /*!< REGFILE REGFILE30: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE31 --------------------------------------- -#define REGFILE_REGFILE31_REGVAL_Pos 0 /*!< REGFILE REGFILE31: REGVAL Position */ -#define REGFILE_REGFILE31_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos) /*!< REGFILE REGFILE31: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE32 --------------------------------------- -#define REGFILE_REGFILE32_REGVAL_Pos 0 /*!< REGFILE REGFILE32: REGVAL Position */ -#define REGFILE_REGFILE32_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos) /*!< REGFILE REGFILE32: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE33 --------------------------------------- -#define REGFILE_REGFILE33_REGVAL_Pos 0 /*!< REGFILE REGFILE33: REGVAL Position */ -#define REGFILE_REGFILE33_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos) /*!< REGFILE REGFILE33: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE34 --------------------------------------- -#define REGFILE_REGFILE34_REGVAL_Pos 0 /*!< REGFILE REGFILE34: REGVAL Position */ -#define REGFILE_REGFILE34_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos) /*!< REGFILE REGFILE34: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE35 --------------------------------------- -#define REGFILE_REGFILE35_REGVAL_Pos 0 /*!< REGFILE REGFILE35: REGVAL Position */ -#define REGFILE_REGFILE35_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos) /*!< REGFILE REGFILE35: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE36 --------------------------------------- -#define REGFILE_REGFILE36_REGVAL_Pos 0 /*!< REGFILE REGFILE36: REGVAL Position */ -#define REGFILE_REGFILE36_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos) /*!< REGFILE REGFILE36: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE37 --------------------------------------- -#define REGFILE_REGFILE37_REGVAL_Pos 0 /*!< REGFILE REGFILE37: REGVAL Position */ -#define REGFILE_REGFILE37_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos) /*!< REGFILE REGFILE37: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE38 --------------------------------------- -#define REGFILE_REGFILE38_REGVAL_Pos 0 /*!< REGFILE REGFILE38: REGVAL Position */ -#define REGFILE_REGFILE38_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos) /*!< REGFILE REGFILE38: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE39 --------------------------------------- -#define REGFILE_REGFILE39_REGVAL_Pos 0 /*!< REGFILE REGFILE39: REGVAL Position */ -#define REGFILE_REGFILE39_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos) /*!< REGFILE REGFILE39: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE40 --------------------------------------- -#define REGFILE_REGFILE40_REGVAL_Pos 0 /*!< REGFILE REGFILE40: REGVAL Position */ -#define REGFILE_REGFILE40_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos) /*!< REGFILE REGFILE40: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE41 --------------------------------------- -#define REGFILE_REGFILE41_REGVAL_Pos 0 /*!< REGFILE REGFILE41: REGVAL Position */ -#define REGFILE_REGFILE41_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos) /*!< REGFILE REGFILE41: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE42 --------------------------------------- -#define REGFILE_REGFILE42_REGVAL_Pos 0 /*!< REGFILE REGFILE42: REGVAL Position */ -#define REGFILE_REGFILE42_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos) /*!< REGFILE REGFILE42: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE43 --------------------------------------- -#define REGFILE_REGFILE43_REGVAL_Pos 0 /*!< REGFILE REGFILE43: REGVAL Position */ -#define REGFILE_REGFILE43_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos) /*!< REGFILE REGFILE43: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE44 --------------------------------------- -#define REGFILE_REGFILE44_REGVAL_Pos 0 /*!< REGFILE REGFILE44: REGVAL Position */ -#define REGFILE_REGFILE44_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos) /*!< REGFILE REGFILE44: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE45 --------------------------------------- -#define REGFILE_REGFILE45_REGVAL_Pos 0 /*!< REGFILE REGFILE45: REGVAL Position */ -#define REGFILE_REGFILE45_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos) /*!< REGFILE REGFILE45: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE46 --------------------------------------- -#define REGFILE_REGFILE46_REGVAL_Pos 0 /*!< REGFILE REGFILE46: REGVAL Position */ -#define REGFILE_REGFILE46_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos) /*!< REGFILE REGFILE46: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE47 --------------------------------------- -#define REGFILE_REGFILE47_REGVAL_Pos 0 /*!< REGFILE REGFILE47: REGVAL Position */ -#define REGFILE_REGFILE47_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos) /*!< REGFILE REGFILE47: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE48 --------------------------------------- -#define REGFILE_REGFILE48_REGVAL_Pos 0 /*!< REGFILE REGFILE48: REGVAL Position */ -#define REGFILE_REGFILE48_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos) /*!< REGFILE REGFILE48: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE49 --------------------------------------- -#define REGFILE_REGFILE49_REGVAL_Pos 0 /*!< REGFILE REGFILE49: REGVAL Position */ -#define REGFILE_REGFILE49_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos) /*!< REGFILE REGFILE49: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE50 --------------------------------------- -#define REGFILE_REGFILE50_REGVAL_Pos 0 /*!< REGFILE REGFILE50: REGVAL Position */ -#define REGFILE_REGFILE50_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos) /*!< REGFILE REGFILE50: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE51 --------------------------------------- -#define REGFILE_REGFILE51_REGVAL_Pos 0 /*!< REGFILE REGFILE51: REGVAL Position */ -#define REGFILE_REGFILE51_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos) /*!< REGFILE REGFILE51: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE52 --------------------------------------- -#define REGFILE_REGFILE52_REGVAL_Pos 0 /*!< REGFILE REGFILE52: REGVAL Position */ -#define REGFILE_REGFILE52_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos) /*!< REGFILE REGFILE52: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE53 --------------------------------------- -#define REGFILE_REGFILE53_REGVAL_Pos 0 /*!< REGFILE REGFILE53: REGVAL Position */ -#define REGFILE_REGFILE53_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos) /*!< REGFILE REGFILE53: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE54 --------------------------------------- -#define REGFILE_REGFILE54_REGVAL_Pos 0 /*!< REGFILE REGFILE54: REGVAL Position */ -#define REGFILE_REGFILE54_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos) /*!< REGFILE REGFILE54: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE55 --------------------------------------- -#define REGFILE_REGFILE55_REGVAL_Pos 0 /*!< REGFILE REGFILE55: REGVAL Position */ -#define REGFILE_REGFILE55_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos) /*!< REGFILE REGFILE55: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE56 --------------------------------------- -#define REGFILE_REGFILE56_REGVAL_Pos 0 /*!< REGFILE REGFILE56: REGVAL Position */ -#define REGFILE_REGFILE56_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos) /*!< REGFILE REGFILE56: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE57 --------------------------------------- -#define REGFILE_REGFILE57_REGVAL_Pos 0 /*!< REGFILE REGFILE57: REGVAL Position */ -#define REGFILE_REGFILE57_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos) /*!< REGFILE REGFILE57: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE58 --------------------------------------- -#define REGFILE_REGFILE58_REGVAL_Pos 0 /*!< REGFILE REGFILE58: REGVAL Position */ -#define REGFILE_REGFILE58_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos) /*!< REGFILE REGFILE58: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE59 --------------------------------------- -#define REGFILE_REGFILE59_REGVAL_Pos 0 /*!< REGFILE REGFILE59: REGVAL Position */ -#define REGFILE_REGFILE59_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos) /*!< REGFILE REGFILE59: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE60 --------------------------------------- -#define REGFILE_REGFILE60_REGVAL_Pos 0 /*!< REGFILE REGFILE60: REGVAL Position */ -#define REGFILE_REGFILE60_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos) /*!< REGFILE REGFILE60: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE61 --------------------------------------- -#define REGFILE_REGFILE61_REGVAL_Pos 0 /*!< REGFILE REGFILE61: REGVAL Position */ -#define REGFILE_REGFILE61_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos) /*!< REGFILE REGFILE61: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE62 --------------------------------------- -#define REGFILE_REGFILE62_REGVAL_Pos 0 /*!< REGFILE REGFILE62: REGVAL Position */ -#define REGFILE_REGFILE62_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos) /*!< REGFILE REGFILE62: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE63 --------------------------------------- -#define REGFILE_REGFILE63_REGVAL_Pos 0 /*!< REGFILE REGFILE63: REGVAL Position */ -#define REGFILE_REGFILE63_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos) /*!< REGFILE REGFILE63: REGVAL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- PMC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------- PMC_PD0_SLEEP0_HW_ENA ------------------------------------- -#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos 0 /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */ -#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos) /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */ - -// ----------------------------------- PMC_PD0_SLEEP0_MODE -------------------------------------- -#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos 0 /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */ -#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos) /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- CREG Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- CREG_IRCTRM ------------------------------------------ -#define CREG_IRCTRM_TRM_Pos 0 /*!< CREG IRCTRM: TRM Position */ -#define CREG_IRCTRM_TRM_Msk (0x00000fffUL << CREG_IRCTRM_TRM_Pos) /*!< CREG IRCTRM: TRM Mask */ - -// --------------------------------------- CREG_CREG0 ------------------------------------------- -#define CREG_CREG0_EN1KHZ_Pos 0 /*!< CREG CREG0: EN1KHZ Position */ -#define CREG_CREG0_EN1KHZ_Msk (0x01UL << CREG_CREG0_EN1KHZ_Pos) /*!< CREG CREG0: EN1KHZ Mask */ -#define CREG_CREG0_EN32KHZ_Pos 1 /*!< CREG CREG0: EN32KHZ Position */ -#define CREG_CREG0_EN32KHZ_Msk (0x01UL << CREG_CREG0_EN32KHZ_Pos) /*!< CREG CREG0: EN32KHZ Mask */ -#define CREG_CREG0_RESET32KHZ_Pos 2 /*!< CREG CREG0: RESET32KHZ Position */ -#define CREG_CREG0_RESET32KHZ_Msk (0x01UL << CREG_CREG0_RESET32KHZ_Pos) /*!< CREG CREG0: RESET32KHZ Mask */ -#define CREG_CREG0_32KHZPD_Pos 3 /*!< CREG CREG0: 32KHZPD Position */ -#define CREG_CREG0_32KHZPD_Msk (0x01UL << CREG_CREG0_32KHZPD_Pos) /*!< CREG CREG0: 32KHZPD Mask */ -#define CREG_CREG0_USB0PHY_Pos 5 /*!< CREG CREG0: USB0PHY Position */ -#define CREG_CREG0_USB0PHY_Msk (0x01UL << CREG_CREG0_USB0PHY_Pos) /*!< CREG CREG0: USB0PHY Mask */ -#define CREG_CREG0_ALARMCTRL_Pos 6 /*!< CREG CREG0: ALARMCTRL Position */ -#define CREG_CREG0_ALARMCTRL_Msk (0x03UL << CREG_CREG0_ALARMCTRL_Pos) /*!< CREG CREG0: ALARMCTRL Mask */ -#define CREG_CREG0_BODLVL1_Pos 8 /*!< CREG CREG0: BODLVL1 Position */ -#define CREG_CREG0_BODLVL1_Msk (0x03UL << CREG_CREG0_BODLVL1_Pos) /*!< CREG CREG0: BODLVL1 Mask */ -#define CREG_CREG0_BODLVL2_Pos 10 /*!< CREG CREG0: BODLVL2 Position */ -#define CREG_CREG0_BODLVL2_Msk (0x03UL << CREG_CREG0_BODLVL2_Pos) /*!< CREG CREG0: BODLVL2 Mask */ -#define CREG_CREG0_WAKEUP0CTRL_Pos 14 /*!< CREG CREG0: WAKEUP0CTRL Position */ -#define CREG_CREG0_WAKEUP0CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos) /*!< CREG CREG0: WAKEUP0CTRL Mask */ -#define CREG_CREG0_WAKEUP1CTRL_Pos 16 /*!< CREG CREG0: WAKEUP1CTRL Position */ -#define CREG_CREG0_WAKEUP1CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos) /*!< CREG CREG0: WAKEUP1CTRL Mask */ - -// --------------------------------------- CREG_PMUCON ------------------------------------------ -#define CREG_PMUCON_PWRCTRL_Pos 0 /*!< CREG PMUCON: PWRCTRL Position */ -#define CREG_PMUCON_PWRCTRL_Msk (0x000001ffUL << CREG_PMUCON_PWRCTRL_Pos) /*!< CREG PMUCON: PWRCTRL Mask */ -#define CREG_PMUCON_DYNAMICPWRCTRL_Pos 15 /*!< CREG PMUCON: DYNAMICPWRCTRL Position */ -#define CREG_PMUCON_DYNAMICPWRCTRL_Msk (0x01UL << CREG_PMUCON_DYNAMICPWRCTRL_Pos) /*!< CREG PMUCON: DYNAMICPWRCTRL Mask */ - -// -------------------------------------- CREG_M3MEMMAP ----------------------------------------- -#define CREG_M3MEMMAP_M3MAP_Pos 12 /*!< CREG M3MEMMAP: M3MAP Position */ -#define CREG_M3MEMMAP_M3MAP_Msk (0x000fffffUL << CREG_M3MEMMAP_M3MAP_Pos) /*!< CREG M3MEMMAP: M3MAP Mask */ - -// --------------------------------------- CREG_CREG5 ------------------------------------------- -#define CREG_CREG5_M3TAPSEL_Pos 6 /*!< CREG CREG5: M3TAPSEL Position */ -#define CREG_CREG5_M3TAPSEL_Msk (0x01UL << CREG_CREG5_M3TAPSEL_Pos) /*!< CREG CREG5: M3TAPSEL Mask */ - -// --------------------------------------- CREG_DMAMUX ------------------------------------------ -#define CREG_DMAMUX_DMAMUXCH0_Pos 0 /*!< CREG DMAMUX: DMAMUXCH0 Position */ -#define CREG_DMAMUX_DMAMUXCH0_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos) /*!< CREG DMAMUX: DMAMUXCH0 Mask */ -#define CREG_DMAMUX_DMAMUXCH1_Pos 2 /*!< CREG DMAMUX: DMAMUXCH1 Position */ -#define CREG_DMAMUX_DMAMUXCH1_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos) /*!< CREG DMAMUX: DMAMUXCH1 Mask */ -#define CREG_DMAMUX_DMAMUXCH2_Pos 4 /*!< CREG DMAMUX: DMAMUXCH2 Position */ -#define CREG_DMAMUX_DMAMUXCH2_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos) /*!< CREG DMAMUX: DMAMUXCH2 Mask */ -#define CREG_DMAMUX_DMAMUXCH3_Pos 6 /*!< CREG DMAMUX: DMAMUXCH3 Position */ -#define CREG_DMAMUX_DMAMUXCH3_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos) /*!< CREG DMAMUX: DMAMUXCH3 Mask */ -#define CREG_DMAMUX_DMAMUXCH4_Pos 8 /*!< CREG DMAMUX: DMAMUXCH4 Position */ -#define CREG_DMAMUX_DMAMUXCH4_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos) /*!< CREG DMAMUX: DMAMUXCH4 Mask */ -#define CREG_DMAMUX_DMAMUXCH5_Pos 10 /*!< CREG DMAMUX: DMAMUXCH5 Position */ -#define CREG_DMAMUX_DMAMUXCH5_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos) /*!< CREG DMAMUX: DMAMUXCH5 Mask */ -#define CREG_DMAMUX_DMAMUXCH6_Pos 12 /*!< CREG DMAMUX: DMAMUXCH6 Position */ -#define CREG_DMAMUX_DMAMUXCH6_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos) /*!< CREG DMAMUX: DMAMUXCH6 Mask */ -#define CREG_DMAMUX_DMAMUXCH7_Pos 14 /*!< CREG DMAMUX: DMAMUXCH7 Position */ -#define CREG_DMAMUX_DMAMUXCH7_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos) /*!< CREG DMAMUX: DMAMUXCH7 Mask */ -#define CREG_DMAMUX_DMAMUXCH8_Pos 16 /*!< CREG DMAMUX: DMAMUXCH8 Position */ -#define CREG_DMAMUX_DMAMUXCH8_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos) /*!< CREG DMAMUX: DMAMUXCH8 Mask */ -#define CREG_DMAMUX_DMAMUXCH9_Pos 18 /*!< CREG DMAMUX: DMAMUXCH9 Position */ -#define CREG_DMAMUX_DMAMUXCH9_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos) /*!< CREG DMAMUX: DMAMUXCH9 Mask */ -#define CREG_DMAMUX_DMAMUXCH10_Pos 20 /*!< CREG DMAMUX: DMAMUXCH10 Position */ -#define CREG_DMAMUX_DMAMUXCH10_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos) /*!< CREG DMAMUX: DMAMUXCH10 Mask */ -#define CREG_DMAMUX_DMAMUXCH11_Pos 22 /*!< CREG DMAMUX: DMAMUXCH11 Position */ -#define CREG_DMAMUX_DMAMUXCH11_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos) /*!< CREG DMAMUX: DMAMUXCH11 Mask */ -#define CREG_DMAMUX_DMAMUXCH12_Pos 24 /*!< CREG DMAMUX: DMAMUXCH12 Position */ -#define CREG_DMAMUX_DMAMUXCH12_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos) /*!< CREG DMAMUX: DMAMUXCH12 Mask */ -#define CREG_DMAMUX_DMAMUXCH13_Pos 26 /*!< CREG DMAMUX: DMAMUXCH13 Position */ -#define CREG_DMAMUX_DMAMUXCH13_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos) /*!< CREG DMAMUX: DMAMUXCH13 Mask */ -#define CREG_DMAMUX_DMAMUXCH14_Pos 28 /*!< CREG DMAMUX: DMAMUXCH14 Position */ -#define CREG_DMAMUX_DMAMUXCH14_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos) /*!< CREG DMAMUX: DMAMUXCH14 Mask */ -#define CREG_DMAMUX_DMAMUXCH15_Pos 30 /*!< CREG DMAMUX: DMAMUXCH15 Position */ -#define CREG_DMAMUX_DMAMUXCH15_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos) /*!< CREG DMAMUX: DMAMUXCH15 Mask */ - -// --------------------------------------- CREG_ETBCFG ------------------------------------------ -#define CREG_ETBCFG_ETB_Pos 0 /*!< CREG ETBCFG: ETB Position */ -#define CREG_ETBCFG_ETB_Msk (0x01UL << CREG_ETBCFG_ETB_Pos) /*!< CREG ETBCFG: ETB Mask */ - -// --------------------------------------- CREG_CREG6 ------------------------------------------- -#define CREG_CREG6_ETHMODE_Pos 0 /*!< CREG CREG6: ETHMODE Position */ -#define CREG_CREG6_ETHMODE_Msk (0x07UL << CREG_CREG6_ETHMODE_Pos) /*!< CREG CREG6: ETHMODE Mask */ -#define CREG_CREG6_TIMCTRL_Pos 4 /*!< CREG CREG6: TIMCTRL Position */ -#define CREG_CREG6_TIMCTRL_Msk (0x01UL << CREG_CREG6_TIMCTRL_Pos) /*!< CREG CREG6: TIMCTRL Mask */ -#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos 12 /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */ -#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */ -#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos 13 /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */ -#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */ -#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos 14 /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */ -#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */ -#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos 15 /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */ -#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */ -#define CREG_CREG6_EMC_CLK_SEL_Pos 16 /*!< CREG CREG6: EMC_CLK_SEL Position */ -#define CREG_CREG6_EMC_CLK_SEL_Msk (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos) /*!< CREG CREG6: EMC_CLK_SEL Mask */ - -// --------------------------------------- CREG_CHIPID ------------------------------------------ -#define CREG_CHIPID_ID_Pos 0 /*!< CREG CHIPID: ID Position */ -#define CREG_CHIPID_ID_Msk (0xffffffffUL << CREG_CHIPID_ID_Pos) /*!< CREG CHIPID: ID Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- EVENTROUTER Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------ EVENTROUTER_HILO ---------------------------------------- -#define EVENTROUTER_HILO_WAKEUP0_L_Pos 0 /*!< EVENTROUTER HILO: WAKEUP0_L Position */ -#define EVENTROUTER_HILO_WAKEUP0_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos) /*!< EVENTROUTER HILO: WAKEUP0_L Mask */ -#define EVENTROUTER_HILO_WAKEUP1_L_Pos 1 /*!< EVENTROUTER HILO: WAKEUP1_L Position */ -#define EVENTROUTER_HILO_WAKEUP1_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos) /*!< EVENTROUTER HILO: WAKEUP1_L Mask */ -#define EVENTROUTER_HILO_WAKEUP2_L_Pos 2 /*!< EVENTROUTER HILO: WAKEUP2_L Position */ -#define EVENTROUTER_HILO_WAKEUP2_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos) /*!< EVENTROUTER HILO: WAKEUP2_L Mask */ -#define EVENTROUTER_HILO_WAKEUP3_L_Pos 3 /*!< EVENTROUTER HILO: WAKEUP3_L Position */ -#define EVENTROUTER_HILO_WAKEUP3_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos) /*!< EVENTROUTER HILO: WAKEUP3_L Mask */ -#define EVENTROUTER_HILO_ATIMER_L_Pos 4 /*!< EVENTROUTER HILO: ATIMER_L Position */ -#define EVENTROUTER_HILO_ATIMER_L_Msk (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos) /*!< EVENTROUTER HILO: ATIMER_L Mask */ -#define EVENTROUTER_HILO_RTC_L_Pos 5 /*!< EVENTROUTER HILO: RTC_L Position */ -#define EVENTROUTER_HILO_RTC_L_Msk (0x01UL << EVENTROUTER_HILO_RTC_L_Pos) /*!< EVENTROUTER HILO: RTC_L Mask */ -#define EVENTROUTER_HILO_BOD_L_Pos 6 /*!< EVENTROUTER HILO: BOD_L Position */ -#define EVENTROUTER_HILO_BOD_L_Msk (0x01UL << EVENTROUTER_HILO_BOD_L_Pos) /*!< EVENTROUTER HILO: BOD_L Mask */ -#define EVENTROUTER_HILO_WWDT_L_Pos 7 /*!< EVENTROUTER HILO: WWDT_L Position */ -#define EVENTROUTER_HILO_WWDT_L_Msk (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos) /*!< EVENTROUTER HILO: WWDT_L Mask */ -#define EVENTROUTER_HILO_ETH_L_Pos 8 /*!< EVENTROUTER HILO: ETH_L Position */ -#define EVENTROUTER_HILO_ETH_L_Msk (0x01UL << EVENTROUTER_HILO_ETH_L_Pos) /*!< EVENTROUTER HILO: ETH_L Mask */ -#define EVENTROUTER_HILO_USB0_L_Pos 9 /*!< EVENTROUTER HILO: USB0_L Position */ -#define EVENTROUTER_HILO_USB0_L_Msk (0x01UL << EVENTROUTER_HILO_USB0_L_Pos) /*!< EVENTROUTER HILO: USB0_L Mask */ -#define EVENTROUTER_HILO_USB1_L_Pos 10 /*!< EVENTROUTER HILO: USB1_L Position */ -#define EVENTROUTER_HILO_USB1_L_Msk (0x01UL << EVENTROUTER_HILO_USB1_L_Pos) /*!< EVENTROUTER HILO: USB1_L Mask */ -#define EVENTROUTER_HILO_SDMMC_L_Pos 11 /*!< EVENTROUTER HILO: SDMMC_L Position */ -#define EVENTROUTER_HILO_SDMMC_L_Msk (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos) /*!< EVENTROUTER HILO: SDMMC_L Mask */ -#define EVENTROUTER_HILO_CAN_L_Pos 12 /*!< EVENTROUTER HILO: CAN_L Position */ -#define EVENTROUTER_HILO_CAN_L_Msk (0x01UL << EVENTROUTER_HILO_CAN_L_Pos) /*!< EVENTROUTER HILO: CAN_L Mask */ -#define EVENTROUTER_HILO_TIM2_L_Pos 13 /*!< EVENTROUTER HILO: TIM2_L Position */ -#define EVENTROUTER_HILO_TIM2_L_Msk (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos) /*!< EVENTROUTER HILO: TIM2_L Mask */ -#define EVENTROUTER_HILO_TIM6_L_Pos 14 /*!< EVENTROUTER HILO: TIM6_L Position */ -#define EVENTROUTER_HILO_TIM6_L_Msk (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos) /*!< EVENTROUTER HILO: TIM6_L Mask */ -#define EVENTROUTER_HILO_QEI_L_Pos 15 /*!< EVENTROUTER HILO: QEI_L Position */ -#define EVENTROUTER_HILO_QEI_L_Msk (0x01UL << EVENTROUTER_HILO_QEI_L_Pos) /*!< EVENTROUTER HILO: QEI_L Mask */ -#define EVENTROUTER_HILO_TIM14_L_Pos 16 /*!< EVENTROUTER HILO: TIM14_L Position */ -#define EVENTROUTER_HILO_TIM14_L_Msk (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos) /*!< EVENTROUTER HILO: TIM14_L Mask */ -#define EVENTROUTER_HILO_RESET_L_Pos 19 /*!< EVENTROUTER HILO: RESET_L Position */ -#define EVENTROUTER_HILO_RESET_L_Msk (0x01UL << EVENTROUTER_HILO_RESET_L_Pos) /*!< EVENTROUTER HILO: RESET_L Mask */ - -// ------------------------------------ EVENTROUTER_EDGE ---------------------------------------- -#define EVENTROUTER_EDGE_WAKEUP0_E_Pos 0 /*!< EVENTROUTER EDGE: WAKEUP0_E Position */ -#define EVENTROUTER_EDGE_WAKEUP0_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP0_E Mask */ -#define EVENTROUTER_EDGE_WAKEUP1_E_Pos 1 /*!< EVENTROUTER EDGE: WAKEUP1_E Position */ -#define EVENTROUTER_EDGE_WAKEUP1_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP1_E Mask */ -#define EVENTROUTER_EDGE_WAKEUP2_E_Pos 2 /*!< EVENTROUTER EDGE: WAKEUP2_E Position */ -#define EVENTROUTER_EDGE_WAKEUP2_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP2_E Mask */ -#define EVENTROUTER_EDGE_WAKEUP3_E_Pos 3 /*!< EVENTROUTER EDGE: WAKEUP3_E Position */ -#define EVENTROUTER_EDGE_WAKEUP3_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP3_E Mask */ -#define EVENTROUTER_EDGE_ATIMER_E_Pos 4 /*!< EVENTROUTER EDGE: ATIMER_E Position */ -#define EVENTROUTER_EDGE_ATIMER_E_Msk (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos) /*!< EVENTROUTER EDGE: ATIMER_E Mask */ -#define EVENTROUTER_EDGE_RTC_E_Pos 5 /*!< EVENTROUTER EDGE: RTC_E Position */ -#define EVENTROUTER_EDGE_RTC_E_Msk (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos) /*!< EVENTROUTER EDGE: RTC_E Mask */ -#define EVENTROUTER_EDGE_BOD_E_Pos 6 /*!< EVENTROUTER EDGE: BOD_E Position */ -#define EVENTROUTER_EDGE_BOD_E_Msk (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos) /*!< EVENTROUTER EDGE: BOD_E Mask */ -#define EVENTROUTER_EDGE_WWDT_E_Pos 7 /*!< EVENTROUTER EDGE: WWDT_E Position */ -#define EVENTROUTER_EDGE_WWDT_E_Msk (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos) /*!< EVENTROUTER EDGE: WWDT_E Mask */ -#define EVENTROUTER_EDGE_ETH_E_Pos 8 /*!< EVENTROUTER EDGE: ETH_E Position */ -#define EVENTROUTER_EDGE_ETH_E_Msk (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos) /*!< EVENTROUTER EDGE: ETH_E Mask */ -#define EVENTROUTER_EDGE_USB0_E_Pos 9 /*!< EVENTROUTER EDGE: USB0_E Position */ -#define EVENTROUTER_EDGE_USB0_E_Msk (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos) /*!< EVENTROUTER EDGE: USB0_E Mask */ -#define EVENTROUTER_EDGE_USB1_E_Pos 10 /*!< EVENTROUTER EDGE: USB1_E Position */ -#define EVENTROUTER_EDGE_USB1_E_Msk (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos) /*!< EVENTROUTER EDGE: USB1_E Mask */ -#define EVENTROUTER_EDGE_SDMMC_E_Pos 11 /*!< EVENTROUTER EDGE: SDMMC_E Position */ -#define EVENTROUTER_EDGE_SDMMC_E_Msk (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos) /*!< EVENTROUTER EDGE: SDMMC_E Mask */ -#define EVENTROUTER_EDGE_CAN_E_Pos 12 /*!< EVENTROUTER EDGE: CAN_E Position */ -#define EVENTROUTER_EDGE_CAN_E_Msk (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos) /*!< EVENTROUTER EDGE: CAN_E Mask */ -#define EVENTROUTER_EDGE_TIM2_E_Pos 13 /*!< EVENTROUTER EDGE: TIM2_E Position */ -#define EVENTROUTER_EDGE_TIM2_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos) /*!< EVENTROUTER EDGE: TIM2_E Mask */ -#define EVENTROUTER_EDGE_TIM6_E_Pos 14 /*!< EVENTROUTER EDGE: TIM6_E Position */ -#define EVENTROUTER_EDGE_TIM6_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos) /*!< EVENTROUTER EDGE: TIM6_E Mask */ -#define EVENTROUTER_EDGE_QEI_E_Pos 15 /*!< EVENTROUTER EDGE: QEI_E Position */ -#define EVENTROUTER_EDGE_QEI_E_Msk (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos) /*!< EVENTROUTER EDGE: QEI_E Mask */ -#define EVENTROUTER_EDGE_TIM14_E_Pos 16 /*!< EVENTROUTER EDGE: TIM14_E Position */ -#define EVENTROUTER_EDGE_TIM14_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos) /*!< EVENTROUTER EDGE: TIM14_E Mask */ -#define EVENTROUTER_EDGE_RESET_E_Pos 19 /*!< EVENTROUTER EDGE: RESET_E Position */ -#define EVENTROUTER_EDGE_RESET_E_Msk (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos) /*!< EVENTROUTER EDGE: RESET_E Mask */ - -// ----------------------------------- EVENTROUTER_CLR_EN --------------------------------------- -#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos 0 /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */ -#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */ -#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos 1 /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */ -#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */ -#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos 2 /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */ -#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */ -#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos 3 /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */ -#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */ -#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos 4 /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */ -#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */ -#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos 5 /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */ -#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask */ -#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos 6 /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */ -#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask */ -#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos 7 /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */ -#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */ -#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos 8 /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */ -#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask */ -#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos 9 /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */ -#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */ -#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos 10 /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */ -#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */ -#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos 11 /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */ -#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */ -#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos 12 /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */ -#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos) /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask */ -#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos 13 /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */ -#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */ -#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos 14 /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */ -#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */ -#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos 15 /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */ -#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos) /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask */ -#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos 16 /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */ -#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */ -#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos 19 /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */ -#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */ - -// ----------------------------------- EVENTROUTER_SET_EN --------------------------------------- -#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos 0 /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */ -#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */ -#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos 1 /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */ -#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */ -#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos 2 /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */ -#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */ -#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos 3 /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */ -#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */ -#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos 4 /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */ -#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos) /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */ -#define EVENTROUTER_SET_EN_RTC_SETEN_Pos 5 /*!< EVENTROUTER SET_EN: RTC_SETEN Position */ -#define EVENTROUTER_SET_EN_RTC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos) /*!< EVENTROUTER SET_EN: RTC_SETEN Mask */ -#define EVENTROUTER_SET_EN_BOD_SETEN_Pos 6 /*!< EVENTROUTER SET_EN: BOD_SETEN Position */ -#define EVENTROUTER_SET_EN_BOD_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos) /*!< EVENTROUTER SET_EN: BOD_SETEN Mask */ -#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos 7 /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */ -#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos) /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */ -#define EVENTROUTER_SET_EN_ETH_SETEN_Pos 8 /*!< EVENTROUTER SET_EN: ETH_SETEN Position */ -#define EVENTROUTER_SET_EN_ETH_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos) /*!< EVENTROUTER SET_EN: ETH_SETEN Mask */ -#define EVENTROUTER_SET_EN_USB0_SETEN_Pos 9 /*!< EVENTROUTER SET_EN: USB0_SETEN Position */ -#define EVENTROUTER_SET_EN_USB0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */ -#define EVENTROUTER_SET_EN_USB1_SETEN_Pos 10 /*!< EVENTROUTER SET_EN: USB1_SETEN Position */ -#define EVENTROUTER_SET_EN_USB1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */ -#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos 11 /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */ -#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos) /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */ -#define EVENTROUTER_SET_EN_CAN_SETEN_Pos 12 /*!< EVENTROUTER SET_EN: CAN_SETEN Position */ -#define EVENTROUTER_SET_EN_CAN_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos) /*!< EVENTROUTER SET_EN: CAN_SETEN Mask */ -#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos 13 /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */ -#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */ -#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos 14 /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */ -#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */ -#define EVENTROUTER_SET_EN_QEI_SETEN_Pos 15 /*!< EVENTROUTER SET_EN: QEI_SETEN Position */ -#define EVENTROUTER_SET_EN_QEI_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos) /*!< EVENTROUTER SET_EN: QEI_SETEN Mask */ -#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos 16 /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */ -#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */ -#define EVENTROUTER_SET_EN_RESET_SETEN_Pos 19 /*!< EVENTROUTER SET_EN: RESET_SETEN Position */ -#define EVENTROUTER_SET_EN_RESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */ - -// ----------------------------------- EVENTROUTER_STATUS --------------------------------------- -#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos 0 /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */ -#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */ -#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos 1 /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */ -#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */ -#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos 2 /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */ -#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */ -#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos 3 /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */ -#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */ -#define EVENTROUTER_STATUS_ATIMER_ST_Pos 4 /*!< EVENTROUTER STATUS: ATIMER_ST Position */ -#define EVENTROUTER_STATUS_ATIMER_ST_Msk (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos) /*!< EVENTROUTER STATUS: ATIMER_ST Mask */ -#define EVENTROUTER_STATUS_RTC_ST_Pos 5 /*!< EVENTROUTER STATUS: RTC_ST Position */ -#define EVENTROUTER_STATUS_RTC_ST_Msk (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos) /*!< EVENTROUTER STATUS: RTC_ST Mask */ -#define EVENTROUTER_STATUS_BOD_ST_Pos 6 /*!< EVENTROUTER STATUS: BOD_ST Position */ -#define EVENTROUTER_STATUS_BOD_ST_Msk (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos) /*!< EVENTROUTER STATUS: BOD_ST Mask */ -#define EVENTROUTER_STATUS_WWDT_ST_Pos 7 /*!< EVENTROUTER STATUS: WWDT_ST Position */ -#define EVENTROUTER_STATUS_WWDT_ST_Msk (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos) /*!< EVENTROUTER STATUS: WWDT_ST Mask */ -#define EVENTROUTER_STATUS_ETH_ST_Pos 8 /*!< EVENTROUTER STATUS: ETH_ST Position */ -#define EVENTROUTER_STATUS_ETH_ST_Msk (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos) /*!< EVENTROUTER STATUS: ETH_ST Mask */ -#define EVENTROUTER_STATUS_USB0_ST_Pos 9 /*!< EVENTROUTER STATUS: USB0_ST Position */ -#define EVENTROUTER_STATUS_USB0_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos) /*!< EVENTROUTER STATUS: USB0_ST Mask */ -#define EVENTROUTER_STATUS_USB1_ST_Pos 10 /*!< EVENTROUTER STATUS: USB1_ST Position */ -#define EVENTROUTER_STATUS_USB1_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos) /*!< EVENTROUTER STATUS: USB1_ST Mask */ -#define EVENTROUTER_STATUS_SDMMC_ST_Pos 11 /*!< EVENTROUTER STATUS: SDMMC_ST Position */ -#define EVENTROUTER_STATUS_SDMMC_ST_Msk (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos) /*!< EVENTROUTER STATUS: SDMMC_ST Mask */ -#define EVENTROUTER_STATUS_CAN_ST_Pos 12 /*!< EVENTROUTER STATUS: CAN_ST Position */ -#define EVENTROUTER_STATUS_CAN_ST_Msk (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos) /*!< EVENTROUTER STATUS: CAN_ST Mask */ -#define EVENTROUTER_STATUS_TIM2_ST_Pos 13 /*!< EVENTROUTER STATUS: TIM2_ST Position */ -#define EVENTROUTER_STATUS_TIM2_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos) /*!< EVENTROUTER STATUS: TIM2_ST Mask */ -#define EVENTROUTER_STATUS_TIM6_ST_Pos 14 /*!< EVENTROUTER STATUS: TIM6_ST Position */ -#define EVENTROUTER_STATUS_TIM6_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos) /*!< EVENTROUTER STATUS: TIM6_ST Mask */ -#define EVENTROUTER_STATUS_QEI_ST_Pos 15 /*!< EVENTROUTER STATUS: QEI_ST Position */ -#define EVENTROUTER_STATUS_QEI_ST_Msk (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos) /*!< EVENTROUTER STATUS: QEI_ST Mask */ -#define EVENTROUTER_STATUS_TIM14_ST_Pos 16 /*!< EVENTROUTER STATUS: TIM14_ST Position */ -#define EVENTROUTER_STATUS_TIM14_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos) /*!< EVENTROUTER STATUS: TIM14_ST Mask */ -#define EVENTROUTER_STATUS_RESET_ST_Pos 19 /*!< EVENTROUTER STATUS: RESET_ST Position */ -#define EVENTROUTER_STATUS_RESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos) /*!< EVENTROUTER STATUS: RESET_ST Mask */ - -// ----------------------------------- EVENTROUTER_ENABLE --------------------------------------- -#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos 0 /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */ -#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */ -#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos 1 /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */ -#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */ -#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos 2 /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */ -#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */ -#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos 3 /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */ -#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */ -#define EVENTROUTER_ENABLE_ATIMER_EN_Pos 4 /*!< EVENTROUTER ENABLE: ATIMER_EN Position */ -#define EVENTROUTER_ENABLE_ATIMER_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos) /*!< EVENTROUTER ENABLE: ATIMER_EN Mask */ -#define EVENTROUTER_ENABLE_RTC_EN_Pos 5 /*!< EVENTROUTER ENABLE: RTC_EN Position */ -#define EVENTROUTER_ENABLE_RTC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos) /*!< EVENTROUTER ENABLE: RTC_EN Mask */ -#define EVENTROUTER_ENABLE_BOD_EN_Pos 6 /*!< EVENTROUTER ENABLE: BOD_EN Position */ -#define EVENTROUTER_ENABLE_BOD_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos) /*!< EVENTROUTER ENABLE: BOD_EN Mask */ -#define EVENTROUTER_ENABLE_WWDT_EN_Pos 7 /*!< EVENTROUTER ENABLE: WWDT_EN Position */ -#define EVENTROUTER_ENABLE_WWDT_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos) /*!< EVENTROUTER ENABLE: WWDT_EN Mask */ -#define EVENTROUTER_ENABLE_ETH_EN_Pos 8 /*!< EVENTROUTER ENABLE: ETH_EN Position */ -#define EVENTROUTER_ENABLE_ETH_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos) /*!< EVENTROUTER ENABLE: ETH_EN Mask */ -#define EVENTROUTER_ENABLE_USB0_EN_Pos 9 /*!< EVENTROUTER ENABLE: USB0_EN Position */ -#define EVENTROUTER_ENABLE_USB0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos) /*!< EVENTROUTER ENABLE: USB0_EN Mask */ -#define EVENTROUTER_ENABLE_USB1_EN_Pos 10 /*!< EVENTROUTER ENABLE: USB1_EN Position */ -#define EVENTROUTER_ENABLE_USB1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos) /*!< EVENTROUTER ENABLE: USB1_EN Mask */ -#define EVENTROUTER_ENABLE_SDMMC_EN_Pos 11 /*!< EVENTROUTER ENABLE: SDMMC_EN Position */ -#define EVENTROUTER_ENABLE_SDMMC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos) /*!< EVENTROUTER ENABLE: SDMMC_EN Mask */ -#define EVENTROUTER_ENABLE_CAN_EN_Pos 12 /*!< EVENTROUTER ENABLE: CAN_EN Position */ -#define EVENTROUTER_ENABLE_CAN_EN_Msk (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos) /*!< EVENTROUTER ENABLE: CAN_EN Mask */ -#define EVENTROUTER_ENABLE_TIM2_EN_Pos 13 /*!< EVENTROUTER ENABLE: TIM2_EN Position */ -#define EVENTROUTER_ENABLE_TIM2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos) /*!< EVENTROUTER ENABLE: TIM2_EN Mask */ -#define EVENTROUTER_ENABLE_TIM6_EN_Pos 14 /*!< EVENTROUTER ENABLE: TIM6_EN Position */ -#define EVENTROUTER_ENABLE_TIM6_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos) /*!< EVENTROUTER ENABLE: TIM6_EN Mask */ -#define EVENTROUTER_ENABLE_QEI_EN_Pos 15 /*!< EVENTROUTER ENABLE: QEI_EN Position */ -#define EVENTROUTER_ENABLE_QEI_EN_Msk (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos) /*!< EVENTROUTER ENABLE: QEI_EN Mask */ -#define EVENTROUTER_ENABLE_TIM14_EN_Pos 16 /*!< EVENTROUTER ENABLE: TIM14_EN Position */ -#define EVENTROUTER_ENABLE_TIM14_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos) /*!< EVENTROUTER ENABLE: TIM14_EN Mask */ -#define EVENTROUTER_ENABLE_RESET_EN_Pos 19 /*!< EVENTROUTER ENABLE: RESET_EN Position */ -#define EVENTROUTER_ENABLE_RESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos) /*!< EVENTROUTER ENABLE: RESET_EN Mask */ - -// ---------------------------------- EVENTROUTER_CLR_STAT -------------------------------------- -#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos 0 /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos 1 /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos 2 /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos 3 /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos 4 /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */ -#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos 5 /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */ -#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos 6 /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */ -#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos 7 /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos 8 /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */ -#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos 9 /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */ -#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos 10 /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */ -#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos 11 /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */ -#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos 12 /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */ -#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos 13 /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */ -#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos 14 /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */ -#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos 15 /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */ -#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos 16 /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */ -#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos 19 /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */ -#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */ - -// ---------------------------------- EVENTROUTER_SET_STAT -------------------------------------- -#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos 0 /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */ -#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */ -#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos 1 /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */ -#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */ -#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos 2 /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */ -#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */ -#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos 3 /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */ -#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */ -#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos 4 /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */ -#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos) /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */ -#define EVENTROUTER_SET_STAT_RTC_SETST_Pos 5 /*!< EVENTROUTER SET_STAT: RTC_SETST Position */ -#define EVENTROUTER_SET_STAT_RTC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos) /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */ -#define EVENTROUTER_SET_STAT_BOD_SETST_Pos 6 /*!< EVENTROUTER SET_STAT: BOD_SETST Position */ -#define EVENTROUTER_SET_STAT_BOD_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos) /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */ -#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos 7 /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */ -#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos) /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */ -#define EVENTROUTER_SET_STAT_ETH_SETST_Pos 8 /*!< EVENTROUTER SET_STAT: ETH_SETST Position */ -#define EVENTROUTER_SET_STAT_ETH_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos) /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */ -#define EVENTROUTER_SET_STAT_USB0_SETST_Pos 9 /*!< EVENTROUTER SET_STAT: USB0_SETST Position */ -#define EVENTROUTER_SET_STAT_USB0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */ -#define EVENTROUTER_SET_STAT_USB1_SETST_Pos 10 /*!< EVENTROUTER SET_STAT: USB1_SETST Position */ -#define EVENTROUTER_SET_STAT_USB1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */ -#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos 11 /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */ -#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos) /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */ -#define EVENTROUTER_SET_STAT_CAN_SETST_Pos 12 /*!< EVENTROUTER SET_STAT: CAN_SETST Position */ -#define EVENTROUTER_SET_STAT_CAN_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos) /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */ -#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos 13 /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */ -#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */ -#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos 14 /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */ -#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */ -#define EVENTROUTER_SET_STAT_QEI_SETST_Pos 15 /*!< EVENTROUTER SET_STAT: QEI_SETST Position */ -#define EVENTROUTER_SET_STAT_QEI_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos) /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */ -#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos 16 /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */ -#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */ -#define EVENTROUTER_SET_STAT_RESET_SETST_Pos 19 /*!< EVENTROUTER SET_STAT: RESET_SETST Position */ -#define EVENTROUTER_SET_STAT_RESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- RTC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- RTC_ILR -------------------------------------------- -#define RTC_ILR_RTCCIF_Pos 0 /*!< RTC ILR: RTCCIF Position */ -#define RTC_ILR_RTCCIF_Msk (0x01UL << RTC_ILR_RTCCIF_Pos) /*!< RTC ILR: RTCCIF Mask */ -#define RTC_ILR_RTCALF_Pos 1 /*!< RTC ILR: RTCALF Position */ -#define RTC_ILR_RTCALF_Msk (0x01UL << RTC_ILR_RTCALF_Pos) /*!< RTC ILR: RTCALF Mask */ - -// ----------------------------------------- RTC_CCR -------------------------------------------- -#define RTC_CCR_CLKEN_Pos 0 /*!< RTC CCR: CLKEN Position */ -#define RTC_CCR_CLKEN_Msk (0x01UL << RTC_CCR_CLKEN_Pos) /*!< RTC CCR: CLKEN Mask */ -#define RTC_CCR_CTCRST_Pos 1 /*!< RTC CCR: CTCRST Position */ -#define RTC_CCR_CTCRST_Msk (0x01UL << RTC_CCR_CTCRST_Pos) /*!< RTC CCR: CTCRST Mask */ -#define RTC_CCR_CCALEN_Pos 4 /*!< RTC CCR: CCALEN Position */ -#define RTC_CCR_CCALEN_Msk (0x01UL << RTC_CCR_CCALEN_Pos) /*!< RTC CCR: CCALEN Mask */ - -// ---------------------------------------- RTC_CIIR -------------------------------------------- -#define RTC_CIIR_IMSEC_Pos 0 /*!< RTC CIIR: IMSEC Position */ -#define RTC_CIIR_IMSEC_Msk (0x01UL << RTC_CIIR_IMSEC_Pos) /*!< RTC CIIR: IMSEC Mask */ -#define RTC_CIIR_IMMIN_Pos 1 /*!< RTC CIIR: IMMIN Position */ -#define RTC_CIIR_IMMIN_Msk (0x01UL << RTC_CIIR_IMMIN_Pos) /*!< RTC CIIR: IMMIN Mask */ -#define RTC_CIIR_IMHOUR_Pos 2 /*!< RTC CIIR: IMHOUR Position */ -#define RTC_CIIR_IMHOUR_Msk (0x01UL << RTC_CIIR_IMHOUR_Pos) /*!< RTC CIIR: IMHOUR Mask */ -#define RTC_CIIR_IMDOM_Pos 3 /*!< RTC CIIR: IMDOM Position */ -#define RTC_CIIR_IMDOM_Msk (0x01UL << RTC_CIIR_IMDOM_Pos) /*!< RTC CIIR: IMDOM Mask */ -#define RTC_CIIR_IMDOW_Pos 4 /*!< RTC CIIR: IMDOW Position */ -#define RTC_CIIR_IMDOW_Msk (0x01UL << RTC_CIIR_IMDOW_Pos) /*!< RTC CIIR: IMDOW Mask */ -#define RTC_CIIR_IMDOY_Pos 5 /*!< RTC CIIR: IMDOY Position */ -#define RTC_CIIR_IMDOY_Msk (0x01UL << RTC_CIIR_IMDOY_Pos) /*!< RTC CIIR: IMDOY Mask */ -#define RTC_CIIR_IMMON_Pos 6 /*!< RTC CIIR: IMMON Position */ -#define RTC_CIIR_IMMON_Msk (0x01UL << RTC_CIIR_IMMON_Pos) /*!< RTC CIIR: IMMON Mask */ -#define RTC_CIIR_IMYEAR_Pos 7 /*!< RTC CIIR: IMYEAR Position */ -#define RTC_CIIR_IMYEAR_Msk (0x01UL << RTC_CIIR_IMYEAR_Pos) /*!< RTC CIIR: IMYEAR Mask */ - -// ----------------------------------------- RTC_AMR -------------------------------------------- -#define RTC_AMR_AMRSEC_Pos 0 /*!< RTC AMR: AMRSEC Position */ -#define RTC_AMR_AMRSEC_Msk (0x01UL << RTC_AMR_AMRSEC_Pos) /*!< RTC AMR: AMRSEC Mask */ -#define RTC_AMR_AMRMIN_Pos 1 /*!< RTC AMR: AMRMIN Position */ -#define RTC_AMR_AMRMIN_Msk (0x01UL << RTC_AMR_AMRMIN_Pos) /*!< RTC AMR: AMRMIN Mask */ -#define RTC_AMR_AMRHOUR_Pos 2 /*!< RTC AMR: AMRHOUR Position */ -#define RTC_AMR_AMRHOUR_Msk (0x01UL << RTC_AMR_AMRHOUR_Pos) /*!< RTC AMR: AMRHOUR Mask */ -#define RTC_AMR_AMRDOM_Pos 3 /*!< RTC AMR: AMRDOM Position */ -#define RTC_AMR_AMRDOM_Msk (0x01UL << RTC_AMR_AMRDOM_Pos) /*!< RTC AMR: AMRDOM Mask */ -#define RTC_AMR_AMRDOW_Pos 4 /*!< RTC AMR: AMRDOW Position */ -#define RTC_AMR_AMRDOW_Msk (0x01UL << RTC_AMR_AMRDOW_Pos) /*!< RTC AMR: AMRDOW Mask */ -#define RTC_AMR_AMRDOY_Pos 5 /*!< RTC AMR: AMRDOY Position */ -#define RTC_AMR_AMRDOY_Msk (0x01UL << RTC_AMR_AMRDOY_Pos) /*!< RTC AMR: AMRDOY Mask */ -#define RTC_AMR_AMRMON_Pos 6 /*!< RTC AMR: AMRMON Position */ -#define RTC_AMR_AMRMON_Msk (0x01UL << RTC_AMR_AMRMON_Pos) /*!< RTC AMR: AMRMON Mask */ -#define RTC_AMR_AMRYEAR_Pos 7 /*!< RTC AMR: AMRYEAR Position */ -#define RTC_AMR_AMRYEAR_Msk (0x01UL << RTC_AMR_AMRYEAR_Pos) /*!< RTC AMR: AMRYEAR Mask */ - -// --------------------------------------- RTC_CTIME0 ------------------------------------------- -#define RTC_CTIME0_SECONDS_Pos 0 /*!< RTC CTIME0: SECONDS Position */ -#define RTC_CTIME0_SECONDS_Msk (0x3fUL << RTC_CTIME0_SECONDS_Pos) /*!< RTC CTIME0: SECONDS Mask */ -#define RTC_CTIME0_MINUTES_Pos 8 /*!< RTC CTIME0: MINUTES Position */ -#define RTC_CTIME0_MINUTES_Msk (0x3fUL << RTC_CTIME0_MINUTES_Pos) /*!< RTC CTIME0: MINUTES Mask */ -#define RTC_CTIME0_HOURS_Pos 16 /*!< RTC CTIME0: HOURS Position */ -#define RTC_CTIME0_HOURS_Msk (0x1fUL << RTC_CTIME0_HOURS_Pos) /*!< RTC CTIME0: HOURS Mask */ -#define RTC_CTIME0_DOW_Pos 24 /*!< RTC CTIME0: DOW Position */ -#define RTC_CTIME0_DOW_Msk (0x07UL << RTC_CTIME0_DOW_Pos) /*!< RTC CTIME0: DOW Mask */ - -// --------------------------------------- RTC_CTIME1 ------------------------------------------- -#define RTC_CTIME1_DOM_Pos 0 /*!< RTC CTIME1: DOM Position */ -#define RTC_CTIME1_DOM_Msk (0x1fUL << RTC_CTIME1_DOM_Pos) /*!< RTC CTIME1: DOM Mask */ -#define RTC_CTIME1_MONTH_Pos 8 /*!< RTC CTIME1: MONTH Position */ -#define RTC_CTIME1_MONTH_Msk (0x0fUL << RTC_CTIME1_MONTH_Pos) /*!< RTC CTIME1: MONTH Mask */ -#define RTC_CTIME1_YEAR_Pos 16 /*!< RTC CTIME1: YEAR Position */ -#define RTC_CTIME1_YEAR_Msk (0x00000fffUL << RTC_CTIME1_YEAR_Pos) /*!< RTC CTIME1: YEAR Mask */ - -// --------------------------------------- RTC_CTIME2 ------------------------------------------- -#define RTC_CTIME2_DOY_Pos 0 /*!< RTC CTIME2: DOY Position */ -#define RTC_CTIME2_DOY_Msk (0x00000fffUL << RTC_CTIME2_DOY_Pos) /*!< RTC CTIME2: DOY Mask */ - -// ----------------------------------------- RTC_SEC -------------------------------------------- -#define RTC_SEC_SECONDS_Pos 0 /*!< RTC SEC: SECONDS Position */ -#define RTC_SEC_SECONDS_Msk (0x3fUL << RTC_SEC_SECONDS_Pos) /*!< RTC SEC: SECONDS Mask */ - -// ----------------------------------------- RTC_MIN -------------------------------------------- -#define RTC_MIN_MINUTES_Pos 0 /*!< RTC MIN: MINUTES Position */ -#define RTC_MIN_MINUTES_Msk (0x3fUL << RTC_MIN_MINUTES_Pos) /*!< RTC MIN: MINUTES Mask */ - -// ----------------------------------------- RTC_HRS -------------------------------------------- -#define RTC_HRS_HOURS_Pos 0 /*!< RTC HRS: HOURS Position */ -#define RTC_HRS_HOURS_Msk (0x1fUL << RTC_HRS_HOURS_Pos) /*!< RTC HRS: HOURS Mask */ - -// ----------------------------------------- RTC_DOM -------------------------------------------- -#define RTC_DOM_DOM_Pos 0 /*!< RTC DOM: DOM Position */ -#define RTC_DOM_DOM_Msk (0x1fUL << RTC_DOM_DOM_Pos) /*!< RTC DOM: DOM Mask */ - -// ----------------------------------------- RTC_DOW -------------------------------------------- -#define RTC_DOW_DOW_Pos 0 /*!< RTC DOW: DOW Position */ -#define RTC_DOW_DOW_Msk (0x07UL << RTC_DOW_DOW_Pos) /*!< RTC DOW: DOW Mask */ - -// ----------------------------------------- RTC_DOY -------------------------------------------- -#define RTC_DOY_DOY_Pos 0 /*!< RTC DOY: DOY Position */ -#define RTC_DOY_DOY_Msk (0x000001ffUL << RTC_DOY_DOY_Pos) /*!< RTC DOY: DOY Mask */ - -// ---------------------------------------- RTC_MONTH ------------------------------------------- -#define RTC_MONTH_MONTH_Pos 0 /*!< RTC MONTH: MONTH Position */ -#define RTC_MONTH_MONTH_Msk (0x0fUL << RTC_MONTH_MONTH_Pos) /*!< RTC MONTH: MONTH Mask */ - -// ---------------------------------------- RTC_YEAR -------------------------------------------- -#define RTC_YEAR_YEAR_Pos 0 /*!< RTC YEAR: YEAR Position */ -#define RTC_YEAR_YEAR_Msk (0x00000fffUL << RTC_YEAR_YEAR_Pos) /*!< RTC YEAR: YEAR Mask */ - -// ------------------------------------- RTC_CALIBRATION ---------------------------------------- -#define RTC_CALIBRATION_CALVAL_Pos 0 /*!< RTC CALIBRATION: CALVAL Position */ -#define RTC_CALIBRATION_CALVAL_Msk (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos) /*!< RTC CALIBRATION: CALVAL Mask */ -#define RTC_CALIBRATION_CALDIR_Pos 17 /*!< RTC CALIBRATION: CALDIR Position */ -#define RTC_CALIBRATION_CALDIR_Msk (0x01UL << RTC_CALIBRATION_CALDIR_Pos) /*!< RTC CALIBRATION: CALDIR Mask */ - -// ---------------------------------------- RTC_ASEC -------------------------------------------- -#define RTC_ASEC_SECONDS_Pos 0 /*!< RTC ASEC: SECONDS Position */ -#define RTC_ASEC_SECONDS_Msk (0x3fUL << RTC_ASEC_SECONDS_Pos) /*!< RTC ASEC: SECONDS Mask */ - -// ---------------------------------------- RTC_AMIN -------------------------------------------- -#define RTC_AMIN_MINUTES_Pos 0 /*!< RTC AMIN: MINUTES Position */ -#define RTC_AMIN_MINUTES_Msk (0x3fUL << RTC_AMIN_MINUTES_Pos) /*!< RTC AMIN: MINUTES Mask */ - -// ---------------------------------------- RTC_AHRS -------------------------------------------- -#define RTC_AHRS_HOURS_Pos 0 /*!< RTC AHRS: HOURS Position */ -#define RTC_AHRS_HOURS_Msk (0x1fUL << RTC_AHRS_HOURS_Pos) /*!< RTC AHRS: HOURS Mask */ - -// ---------------------------------------- RTC_ADOM -------------------------------------------- -#define RTC_ADOM_DOM_Pos 0 /*!< RTC ADOM: DOM Position */ -#define RTC_ADOM_DOM_Msk (0x1fUL << RTC_ADOM_DOM_Pos) /*!< RTC ADOM: DOM Mask */ - -// ---------------------------------------- RTC_ADOW -------------------------------------------- -#define RTC_ADOW_DOW_Pos 0 /*!< RTC ADOW: DOW Position */ -#define RTC_ADOW_DOW_Msk (0x07UL << RTC_ADOW_DOW_Pos) /*!< RTC ADOW: DOW Mask */ - -// ---------------------------------------- RTC_ADOY -------------------------------------------- -#define RTC_ADOY_DOY_Pos 0 /*!< RTC ADOY: DOY Position */ -#define RTC_ADOY_DOY_Msk (0x000001ffUL << RTC_ADOY_DOY_Pos) /*!< RTC ADOY: DOY Mask */ - -// ---------------------------------------- RTC_AMON -------------------------------------------- -#define RTC_AMON_MONTH_Pos 0 /*!< RTC AMON: MONTH Position */ -#define RTC_AMON_MONTH_Msk (0x0fUL << RTC_AMON_MONTH_Pos) /*!< RTC AMON: MONTH Mask */ - -// ---------------------------------------- RTC_AYRS -------------------------------------------- -#define RTC_AYRS_YEAR_Pos 0 /*!< RTC AYRS: YEAR Position */ -#define RTC_AYRS_YEAR_Msk (0x00000fffUL << RTC_AYRS_YEAR_Pos) /*!< RTC AYRS: YEAR Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- CGU Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// -------------------------------------- CGU_FREQ_MON ------------------------------------------ -#define CGU_FREQ_MON_RCNT_Pos 0 /*!< CGU FREQ_MON: RCNT Position */ -#define CGU_FREQ_MON_RCNT_Msk (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos) /*!< CGU FREQ_MON: RCNT Mask */ -#define CGU_FREQ_MON_FCNT_Pos 9 /*!< CGU FREQ_MON: FCNT Position */ -#define CGU_FREQ_MON_FCNT_Msk (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos) /*!< CGU FREQ_MON: FCNT Mask */ -#define CGU_FREQ_MON_MEAS_Pos 23 /*!< CGU FREQ_MON: MEAS Position */ -#define CGU_FREQ_MON_MEAS_Msk (0x01UL << CGU_FREQ_MON_MEAS_Pos) /*!< CGU FREQ_MON: MEAS Mask */ -#define CGU_FREQ_MON_CLK_SEL_Pos 24 /*!< CGU FREQ_MON: CLK_SEL Position */ -#define CGU_FREQ_MON_CLK_SEL_Msk (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos) /*!< CGU FREQ_MON: CLK_SEL Mask */ - -// ------------------------------------ CGU_XTAL_OSC_CTRL --------------------------------------- -#define CGU_XTAL_OSC_CTRL_ENABLE_Pos 0 /*!< CGU XTAL_OSC_CTRL: ENABLE Position */ -#define CGU_XTAL_OSC_CTRL_ENABLE_Msk (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos) /*!< CGU XTAL_OSC_CTRL: ENABLE Mask */ -#define CGU_XTAL_OSC_CTRL_BYPASS_Pos 1 /*!< CGU XTAL_OSC_CTRL: BYPASS Position */ -#define CGU_XTAL_OSC_CTRL_BYPASS_Msk (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos) /*!< CGU XTAL_OSC_CTRL: BYPASS Mask */ -#define CGU_XTAL_OSC_CTRL_HF_Pos 2 /*!< CGU XTAL_OSC_CTRL: HF Position */ -#define CGU_XTAL_OSC_CTRL_HF_Msk (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos) /*!< CGU XTAL_OSC_CTRL: HF Mask */ - -// ------------------------------------ CGU_PLL0USB_STAT ---------------------------------------- -#define CGU_PLL0USB_STAT_LOCK_Pos 0 /*!< CGU PLL0USB_STAT: LOCK Position */ -#define CGU_PLL0USB_STAT_LOCK_Msk (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos) /*!< CGU PLL0USB_STAT: LOCK Mask */ -#define CGU_PLL0USB_STAT_FR_Pos 1 /*!< CGU PLL0USB_STAT: FR Position */ -#define CGU_PLL0USB_STAT_FR_Msk (0x01UL << CGU_PLL0USB_STAT_FR_Pos) /*!< CGU PLL0USB_STAT: FR Mask */ - -// ------------------------------------ CGU_PLL0USB_CTRL ---------------------------------------- -#define CGU_PLL0USB_CTRL_PD_Pos 0 /*!< CGU PLL0USB_CTRL: PD Position */ -#define CGU_PLL0USB_CTRL_PD_Msk (0x01UL << CGU_PLL0USB_CTRL_PD_Pos) /*!< CGU PLL0USB_CTRL: PD Mask */ -#define CGU_PLL0USB_CTRL_BYPASS_Pos 1 /*!< CGU PLL0USB_CTRL: BYPASS Position */ -#define CGU_PLL0USB_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos) /*!< CGU PLL0USB_CTRL: BYPASS Mask */ -#define CGU_PLL0USB_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0USB_CTRL: DIRECTI Position */ -#define CGU_PLL0USB_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos) /*!< CGU PLL0USB_CTRL: DIRECTI Mask */ -#define CGU_PLL0USB_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0USB_CTRL: DIRECTO Position */ -#define CGU_PLL0USB_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos) /*!< CGU PLL0USB_CTRL: DIRECTO Mask */ -#define CGU_PLL0USB_CTRL_CLKEN_Pos 4 /*!< CGU PLL0USB_CTRL: CLKEN Position */ -#define CGU_PLL0USB_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos) /*!< CGU PLL0USB_CTRL: CLKEN Mask */ -#define CGU_PLL0USB_CTRL_FRM_Pos 6 /*!< CGU PLL0USB_CTRL: FRM Position */ -#define CGU_PLL0USB_CTRL_FRM_Msk (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos) /*!< CGU PLL0USB_CTRL: FRM Mask */ -#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */ -#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask */ -#define CGU_PLL0USB_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0USB_CTRL: CLK_SEL Position */ -#define CGU_PLL0USB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos) /*!< CGU PLL0USB_CTRL: CLK_SEL Mask */ - -// ------------------------------------ CGU_PLL0USB_MDIV ---------------------------------------- -#define CGU_PLL0USB_MDIV_MDEC_Pos 0 /*!< CGU PLL0USB_MDIV: MDEC Position */ -#define CGU_PLL0USB_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos) /*!< CGU PLL0USB_MDIV: MDEC Mask */ -#define CGU_PLL0USB_MDIV_SELP_Pos 17 /*!< CGU PLL0USB_MDIV: SELP Position */ -#define CGU_PLL0USB_MDIV_SELP_Msk (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos) /*!< CGU PLL0USB_MDIV: SELP Mask */ -#define CGU_PLL0USB_MDIV_SELI_Pos 22 /*!< CGU PLL0USB_MDIV: SELI Position */ -#define CGU_PLL0USB_MDIV_SELI_Msk (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos) /*!< CGU PLL0USB_MDIV: SELI Mask */ -#define CGU_PLL0USB_MDIV_SELR_Pos 28 /*!< CGU PLL0USB_MDIV: SELR Position */ -#define CGU_PLL0USB_MDIV_SELR_Msk (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos) /*!< CGU PLL0USB_MDIV: SELR Mask */ - -// ----------------------------------- CGU_PLL0USB_NP_DIV --------------------------------------- -#define CGU_PLL0USB_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0USB_NP_DIV: PDEC Position */ -#define CGU_PLL0USB_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos) /*!< CGU PLL0USB_NP_DIV: PDEC Mask */ -#define CGU_PLL0USB_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0USB_NP_DIV: NDEC Position */ -#define CGU_PLL0USB_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos) /*!< CGU PLL0USB_NP_DIV: NDEC Mask */ - -// ----------------------------------- CGU_PLL0AUDIO_STAT --------------------------------------- -#define CGU_PLL0AUDIO_STAT_LOCK_Pos 0 /*!< CGU PLL0AUDIO_STAT: LOCK Position */ -#define CGU_PLL0AUDIO_STAT_LOCK_Msk (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos) /*!< CGU PLL0AUDIO_STAT: LOCK Mask */ -#define CGU_PLL0AUDIO_STAT_FR_Pos 1 /*!< CGU PLL0AUDIO_STAT: FR Position */ -#define CGU_PLL0AUDIO_STAT_FR_Msk (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos) /*!< CGU PLL0AUDIO_STAT: FR Mask */ - -// ----------------------------------- CGU_PLL0AUDIO_CTRL --------------------------------------- -#define CGU_PLL0AUDIO_CTRL_PD_Pos 0 /*!< CGU PLL0AUDIO_CTRL: PD Position */ -#define CGU_PLL0AUDIO_CTRL_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: PD Mask */ -#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos 1 /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */ -#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos) /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask */ -#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */ -#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask */ -#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */ -#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask */ -#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos 4 /*!< CGU PLL0AUDIO_CTRL: CLKEN Position */ -#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos) /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask */ -#define CGU_PLL0AUDIO_CTRL_FRM_Pos 6 /*!< CGU PLL0AUDIO_CTRL: FRM Position */ -#define CGU_PLL0AUDIO_CTRL_FRM_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos) /*!< CGU PLL0AUDIO_CTRL: FRM Mask */ -#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */ -#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask */ -#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos 12 /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */ -#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos) /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */ -#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos 13 /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */ -#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos) /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask */ -#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos 14 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */ -#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask */ -#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */ -#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos) /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask */ - -// ----------------------------------- CGU_PLL0AUDIO_MDIV --------------------------------------- -#define CGU_PLL0AUDIO_MDIV_MDEC_Pos 0 /*!< CGU PLL0AUDIO_MDIV: MDEC Position */ -#define CGU_PLL0AUDIO_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos) /*!< CGU PLL0AUDIO_MDIV: MDEC Mask */ - -// ---------------------------------- CGU_PLL0AUDIO_NP_DIV -------------------------------------- -#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */ -#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask */ -#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */ -#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask */ - -// ----------------------------------- CGU_PLL0AUDIO_FRAC --------------------------------------- -#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos 0 /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */ -#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos) /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */ - -// -------------------------------------- CGU_PLL1_STAT ----------------------------------------- -#define CGU_PLL1_STAT_LOCK_Pos 0 /*!< CGU PLL1_STAT: LOCK Position */ -#define CGU_PLL1_STAT_LOCK_Msk (0x01UL << CGU_PLL1_STAT_LOCK_Pos) /*!< CGU PLL1_STAT: LOCK Mask */ - -// -------------------------------------- CGU_PLL1_CTRL ----------------------------------------- -#define CGU_PLL1_CTRL_PD_Pos 0 /*!< CGU PLL1_CTRL: PD Position */ -#define CGU_PLL1_CTRL_PD_Msk (0x01UL << CGU_PLL1_CTRL_PD_Pos) /*!< CGU PLL1_CTRL: PD Mask */ -#define CGU_PLL1_CTRL_BYPASS_Pos 1 /*!< CGU PLL1_CTRL: BYPASS Position */ -#define CGU_PLL1_CTRL_BYPASS_Msk (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos) /*!< CGU PLL1_CTRL: BYPASS Mask */ -#define CGU_PLL1_CTRL_FBSEL_Pos 6 /*!< CGU PLL1_CTRL: FBSEL Position */ -#define CGU_PLL1_CTRL_FBSEL_Msk (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos) /*!< CGU PLL1_CTRL: FBSEL Mask */ -#define CGU_PLL1_CTRL_DIRECT_Pos 7 /*!< CGU PLL1_CTRL: DIRECT Position */ -#define CGU_PLL1_CTRL_DIRECT_Msk (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos) /*!< CGU PLL1_CTRL: DIRECT Mask */ -#define CGU_PLL1_CTRL_PSEL_Pos 8 /*!< CGU PLL1_CTRL: PSEL Position */ -#define CGU_PLL1_CTRL_PSEL_Msk (0x03UL << CGU_PLL1_CTRL_PSEL_Pos) /*!< CGU PLL1_CTRL: PSEL Mask */ -#define CGU_PLL1_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL1_CTRL: AUTOBLOCK Position */ -#define CGU_PLL1_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL1_CTRL: AUTOBLOCK Mask */ -#define CGU_PLL1_CTRL_NSEL_Pos 12 /*!< CGU PLL1_CTRL: NSEL Position */ -#define CGU_PLL1_CTRL_NSEL_Msk (0x03UL << CGU_PLL1_CTRL_NSEL_Pos) /*!< CGU PLL1_CTRL: NSEL Mask */ -#define CGU_PLL1_CTRL_MSEL_Pos 16 /*!< CGU PLL1_CTRL: MSEL Position */ -#define CGU_PLL1_CTRL_MSEL_Msk (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos) /*!< CGU PLL1_CTRL: MSEL Mask */ -#define CGU_PLL1_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL1_CTRL: CLK_SEL Position */ -#define CGU_PLL1_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos) /*!< CGU PLL1_CTRL: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVA_CTRL ----------------------------------------- -#define CGU_IDIVA_CTRL_PD_Pos 0 /*!< CGU IDIVA_CTRL: PD Position */ -#define CGU_IDIVA_CTRL_PD_Msk (0x01UL << CGU_IDIVA_CTRL_PD_Pos) /*!< CGU IDIVA_CTRL: PD Mask */ -#define CGU_IDIVA_CTRL_IDIV_Pos 2 /*!< CGU IDIVA_CTRL: IDIV Position */ -#define CGU_IDIVA_CTRL_IDIV_Msk (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos) /*!< CGU IDIVA_CTRL: IDIV Mask */ -#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVA_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVA_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVA_CTRL: CLK_SEL Position */ -#define CGU_IDIVA_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos) /*!< CGU IDIVA_CTRL: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVB_CTRL ----------------------------------------- -#define CGU_IDIVB_CTRL_PD_Pos 0 /*!< CGU IDIVB_CTRL: PD Position */ -#define CGU_IDIVB_CTRL_PD_Msk (0x01UL << CGU_IDIVB_CTRL_PD_Pos) /*!< CGU IDIVB_CTRL: PD Mask */ -#define CGU_IDIVB_CTRL_IDIV_Pos 2 /*!< CGU IDIVB_CTRL: IDIV Position */ -#define CGU_IDIVB_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos) /*!< CGU IDIVB_CTRL: IDIV Mask */ -#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVB_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVB_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVB_CTRL: CLK_SEL Position */ -#define CGU_IDIVB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos) /*!< CGU IDIVB_CTRL: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVE_CTRL ----------------------------------------- -#define CGU_IDIVE_CTRL_PD_Pos 0 /*!< CGU IDIVE_CTRL: PD Position */ -#define CGU_IDIVE_CTRL_PD_Msk (0x01UL << CGU_IDIVE_CTRL_PD_Pos) /*!< CGU IDIVE_CTRL: PD Mask */ -#define CGU_IDIVE_CTRL_IDIV_Pos 2 /*!< CGU IDIVE_CTRL: IDIV Position */ -#define CGU_IDIVE_CTRL_IDIV_Msk (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos) /*!< CGU IDIVE_CTRL: IDIV Mask */ -#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVE_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVE_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVE_CTRL: CLK_SEL Position */ -#define CGU_IDIVE_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos) /*!< CGU IDIVE_CTRL: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SAFE_CLK --------------------------------------- -#define CGU_BASE_SAFE_CLK_PD_Pos 0 /*!< CGU BASE_SAFE_CLK: PD Position */ -#define CGU_BASE_SAFE_CLK_PD_Msk (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos) /*!< CGU BASE_SAFE_CLK: PD Mask */ -#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */ -#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos) /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_USB0_CLK --------------------------------------- -#define CGU_BASE_USB0_CLK_PD_Pos 0 /*!< CGU BASE_USB0_CLK: PD Position */ -#define CGU_BASE_USB0_CLK_PD_Msk (0x01UL << CGU_BASE_USB0_CLK_PD_Pos) /*!< CGU BASE_USB0_CLK: PD Mask */ -#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */ -#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_USB0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB0_CLK: CLK_SEL Position */ -#define CGU_BASE_USB0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB0_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_PERIPH_CLK -------------------------------------- -#define CGU_BASE_PERIPH_CLK_PD_Pos 0 /*!< CGU BASE_PERIPH_CLK: PD Position */ -#define CGU_BASE_PERIPH_CLK_PD_Msk (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos) /*!< CGU BASE_PERIPH_CLK: PD Mask */ -#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */ -#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */ -#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos) /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_USB1_CLK --------------------------------------- -#define CGU_BASE_USB1_CLK_PD_Pos 0 /*!< CGU BASE_USB1_CLK: PD Position */ -#define CGU_BASE_USB1_CLK_PD_Msk (0x01UL << CGU_BASE_USB1_CLK_PD_Pos) /*!< CGU BASE_USB1_CLK: PD Mask */ -#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_USB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB1_CLK: CLK_SEL Position */ -#define CGU_BASE_USB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB1_CLK: CLK_SEL Mask */ - -// ------------------------------------- CGU_BASE_M4_CLK ---------------------------------------- -#define CGU_BASE_M4_CLK_PD_Pos 0 /*!< CGU BASE_M4_CLK: PD Position */ -#define CGU_BASE_M4_CLK_PD_Msk (0x01UL << CGU_BASE_M4_CLK_PD_Pos) /*!< CGU BASE_M4_CLK: PD Mask */ -#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */ -#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_M4_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_M4_CLK: CLK_SEL Position */ -#define CGU_BASE_M4_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos) /*!< CGU BASE_M4_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_SPIFI_CLK --------------------------------------- -#define CGU_BASE_SPIFI_CLK_PD_Pos 0 /*!< CGU BASE_SPIFI_CLK: PD Position */ -#define CGU_BASE_SPIFI_CLK_PD_Msk (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos) /*!< CGU BASE_SPIFI_CLK: PD Mask */ -#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */ -#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SPI_CLK ---------------------------------------- -#define CGU_BASE_SPI_CLK_PD_Pos 0 /*!< CGU BASE_SPI_CLK: PD Position */ -#define CGU_BASE_SPI_CLK_PD_Msk (0x01UL << CGU_BASE_SPI_CLK_PD_Pos) /*!< CGU BASE_SPI_CLK: PD Mask */ -#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SPI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPI_CLK: CLK_SEL Position */ -#define CGU_BASE_SPI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPI_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_PHY_RX_CLK -------------------------------------- -#define CGU_BASE_PHY_RX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_RX_CLK: PD Position */ -#define CGU_BASE_PHY_RX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos) /*!< CGU BASE_PHY_RX_CLK: PD Mask */ -#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */ -#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */ -#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_PHY_TX_CLK -------------------------------------- -#define CGU_BASE_PHY_TX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_TX_CLK: PD Position */ -#define CGU_BASE_PHY_TX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos) /*!< CGU BASE_PHY_TX_CLK: PD Mask */ -#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */ -#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */ -#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_APB1_CLK --------------------------------------- -#define CGU_BASE_APB1_CLK_PD_Pos 0 /*!< CGU BASE_APB1_CLK: PD Position */ -#define CGU_BASE_APB1_CLK_PD_Msk (0x01UL << CGU_BASE_APB1_CLK_PD_Pos) /*!< CGU BASE_APB1_CLK: PD Mask */ -#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_APB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB1_CLK: CLK_SEL Position */ -#define CGU_BASE_APB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB1_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_APB3_CLK --------------------------------------- -#define CGU_BASE_APB3_CLK_PD_Pos 0 /*!< CGU BASE_APB3_CLK: PD Position */ -#define CGU_BASE_APB3_CLK_PD_Msk (0x01UL << CGU_BASE_APB3_CLK_PD_Pos) /*!< CGU BASE_APB3_CLK: PD Mask */ -#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */ -#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_APB3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB3_CLK: CLK_SEL Position */ -#define CGU_BASE_APB3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB3_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_LCD_CLK ---------------------------------------- -#define CGU_BASE_LCD_CLK_PD_Pos 0 /*!< CGU BASE_LCD_CLK: PD Position */ -#define CGU_BASE_LCD_CLK_PD_Msk (0x01UL << CGU_BASE_LCD_CLK_PD_Pos) /*!< CGU BASE_LCD_CLK: PD Mask */ -#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */ -#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_LCD_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_LCD_CLK: CLK_SEL Position */ -#define CGU_BASE_LCD_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos) /*!< CGU BASE_LCD_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SDIO_CLK --------------------------------------- -#define CGU_BASE_SDIO_CLK_PD_Pos 0 /*!< CGU BASE_SDIO_CLK: PD Position */ -#define CGU_BASE_SDIO_CLK_PD_Msk (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos) /*!< CGU BASE_SDIO_CLK: PD Mask */ -#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */ -#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos) /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SSP0_CLK --------------------------------------- -#define CGU_BASE_SSP0_CLK_PD_Pos 0 /*!< CGU BASE_SSP0_CLK: PD Position */ -#define CGU_BASE_SSP0_CLK_PD_Msk (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos) /*!< CGU BASE_SSP0_CLK: PD Mask */ -#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */ -#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SSP1_CLK --------------------------------------- -#define CGU_BASE_SSP1_CLK_PD_Pos 0 /*!< CGU BASE_SSP1_CLK: PD Position */ -#define CGU_BASE_SSP1_CLK_PD_Msk (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos) /*!< CGU BASE_SSP1_CLK: PD Mask */ -#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */ -#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_UART0_CLK --------------------------------------- -#define CGU_BASE_UART0_CLK_PD_Pos 0 /*!< CGU BASE_UART0_CLK: PD Position */ -#define CGU_BASE_UART0_CLK_PD_Msk (0x01UL << CGU_BASE_UART0_CLK_PD_Pos) /*!< CGU BASE_UART0_CLK: PD Mask */ -#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */ -#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_UART0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART0_CLK: CLK_SEL Position */ -#define CGU_BASE_UART0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART0_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_UART1_CLK --------------------------------------- -#define CGU_BASE_UART1_CLK_PD_Pos 0 /*!< CGU BASE_UART1_CLK: PD Position */ -#define CGU_BASE_UART1_CLK_PD_Msk (0x01UL << CGU_BASE_UART1_CLK_PD_Pos) /*!< CGU BASE_UART1_CLK: PD Mask */ -#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_UART1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART1_CLK: CLK_SEL Position */ -#define CGU_BASE_UART1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART1_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_UART2_CLK --------------------------------------- -#define CGU_BASE_UART2_CLK_PD_Pos 0 /*!< CGU BASE_UART2_CLK: PD Position */ -#define CGU_BASE_UART2_CLK_PD_Msk (0x01UL << CGU_BASE_UART2_CLK_PD_Pos) /*!< CGU BASE_UART2_CLK: PD Mask */ -#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */ -#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_UART2_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART2_CLK: CLK_SEL Position */ -#define CGU_BASE_UART2_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART2_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_UART3_CLK --------------------------------------- -#define CGU_BASE_UART3_CLK_PD_Pos 0 /*!< CGU BASE_UART3_CLK: PD Position */ -#define CGU_BASE_UART3_CLK_PD_Msk (0x01UL << CGU_BASE_UART3_CLK_PD_Pos) /*!< CGU BASE_UART3_CLK: PD Mask */ -#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */ -#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_UART3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART3_CLK: CLK_SEL Position */ -#define CGU_BASE_UART3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART3_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_OUT_CLK ---------------------------------------- -#define CGU_BASE_OUT_CLK_PD_Pos 0 /*!< CGU BASE_OUT_CLK: PD Position */ -#define CGU_BASE_OUT_CLK_PD_Msk (0x01UL << CGU_BASE_OUT_CLK_PD_Pos) /*!< CGU BASE_OUT_CLK: PD Mask */ -#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */ -#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_OUT_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_OUT_CLK: CLK_SEL Position */ -#define CGU_BASE_OUT_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos) /*!< CGU BASE_OUT_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_APLL_CLK --------------------------------------- -#define CGU_BASE_APLL_CLK_PD_Pos 0 /*!< CGU BASE_APLL_CLK: PD Position */ -#define CGU_BASE_APLL_CLK_PD_Msk (0x01UL << CGU_BASE_APLL_CLK_PD_Pos) /*!< CGU BASE_APLL_CLK: PD Mask */ -#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */ -#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_APLL_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APLL_CLK: CLK_SEL Position */ -#define CGU_BASE_APLL_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos) /*!< CGU BASE_APLL_CLK: CLK_SEL Mask */ - -// ---------------------------------- CGU_BASE_CGU_OUT0_CLK ------------------------------------- -#define CGU_BASE_CGU_OUT0_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT0_CLK: PD Position */ -#define CGU_BASE_CGU_OUT0_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT0_CLK: PD Mask */ -#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */ -#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */ -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */ - -// ---------------------------------- CGU_BASE_CGU_OUT1_CLK ------------------------------------- -#define CGU_BASE_CGU_OUT1_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT1_CLK: PD Position */ -#define CGU_BASE_CGU_OUT1_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT1_CLK: PD Mask */ -#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */ -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVC_CTRL ----------------------------------------- -#define CGU_IDIVC_CTRL_PD_Pos 0 /*!< CGU IDIVC_CTRL: PD Position */ -#define CGU_IDIVC_CTRL_PD_Msk (0x01UL << CGU_IDIVC_CTRL_PD_Pos) /*!< CGU IDIVC_CTRL: PD Mask */ -#define CGU_IDIVC_CTRL_IDIV_Pos 2 /*!< CGU IDIVC_CTRL: IDIV Position */ -#define CGU_IDIVC_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos) /*!< CGU IDIVC_CTRL: IDIV Mask */ -#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVC_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVC_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVC_CTRL: CLK_SEL Position */ -#define CGU_IDIVC_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos) /*!< CGU IDIVC_CTRL: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVD_CTRL ----------------------------------------- -#define CGU_IDIVD_CTRL_PD_Pos 0 /*!< CGU IDIVD_CTRL: PD Position */ -#define CGU_IDIVD_CTRL_PD_Msk (0x01UL << CGU_IDIVD_CTRL_PD_Pos) /*!< CGU IDIVD_CTRL: PD Mask */ -#define CGU_IDIVD_CTRL_IDIV_Pos 2 /*!< CGU IDIVD_CTRL: IDIV Position */ -#define CGU_IDIVD_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos) /*!< CGU IDIVD_CTRL: IDIV Mask */ -#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVD_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVD_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVD_CTRL: CLK_SEL Position */ -#define CGU_IDIVD_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos) /*!< CGU IDIVD_CTRL: CLK_SEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- CCU1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- CCU1_PM -------------------------------------------- -#define CCU1_PM_PD_Pos 0 /*!< CCU1 PM: PD Position */ -#define CCU1_PM_PD_Msk (0x01UL << CCU1_PM_PD_Pos) /*!< CCU1 PM: PD Mask */ - -// ------------------------------------- CCU1_BASE_STAT ----------------------------------------- -#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos 0 /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos 1 /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos 2 /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos 3 /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos 7 /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos 8 /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */ - -// ---------------------------------- CCU1_CLK_APB3_BUS_CFG ------------------------------------- -#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */ -#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask */ -#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */ -#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_BUS_STAT ------------------------------------- -#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */ -#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask */ -#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */ -#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_I2C1_CFG ------------------------------------- -#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */ -#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask */ -#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */ -#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_I2C1_STAT ------------------------------------ -#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */ -#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask */ -#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */ -#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_APB3_DAC_CFG ------------------------------------- -#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */ -#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask */ -#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */ -#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_DAC_STAT ------------------------------------- -#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */ -#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask */ -#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */ -#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_ADC0_CFG ------------------------------------- -#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */ -#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask */ -#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */ -#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_ADC0_STAT ------------------------------------ -#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */ -#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask */ -#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */ -#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_ADC1_CFG ------------------------------------- -#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */ -#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask */ -#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */ -#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_ADC1_STAT ------------------------------------ -#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */ -#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask */ -#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */ -#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_CAN0_CFG ------------------------------------- -#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */ -#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask */ -#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */ -#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_CAN0_STAT ------------------------------------ -#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */ -#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask */ -#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */ -#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_APB1_BUS_CFG ------------------------------------- -#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */ -#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask */ -#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */ -#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask */ -#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */ -#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_BUS_STAT ------------------------------------- -#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */ -#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask */ -#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */ -#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */ - -// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_CFG ---------------------------------- -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */ - -// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_STAT --------------------------------- -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_ABP1_I2C0_CFG ------------------------------------- -#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos 0 /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */ -#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask */ -#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */ -#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask */ -#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */ -#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_I2C0_STAT ------------------------------------ -#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */ -#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask */ -#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */ -#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_APB1_I2S_CFG ------------------------------------- -#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */ -#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask */ -#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */ -#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask */ -#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */ -#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_I2S_STAT ------------------------------------- -#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */ -#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask */ -#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */ -#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_CAN1_CFG ------------------------------------- -#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */ -#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask */ -#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */ -#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask */ -#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */ -#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_CAN1_STAT ------------------------------------ -#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */ -#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask */ -#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */ -#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_SPIFI_CFG --------------------------------------- -#define CCU1_CLK_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_CFG: RUN Position */ -#define CCU1_CLK_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_SPIFI_CFG: RUN Mask */ -#define CCU1_CLK_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_CFG: AUTO Position */ -#define CCU1_CLK_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask */ -#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */ -#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_SPIFI_STAT -------------------------------------- -#define CCU1_CLK_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_STAT: RUN Position */ -#define CCU1_CLK_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_SPIFI_STAT: RUN Mask */ -#define CCU1_CLK_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_STAT: AUTO Position */ -#define CCU1_CLK_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask */ -#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */ -#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M3_BUS_CFG -------------------------------------- -#define CCU1_CLK_M3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_BUS_CFG: RUN Position */ -#define CCU1_CLK_M3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_M3_BUS_CFG: RUN Mask */ -#define CCU1_CLK_M3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_BUS_CFG: AUTO Position */ -#define CCU1_CLK_M3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_BUS_CFG: AUTO Mask */ -#define CCU1_CLK_M3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_BUS_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_BUS_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_BUS_STAT -------------------------------------- -#define CCU1_CLK_M3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_BUS_STAT: RUN Position */ -#define CCU1_CLK_M3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_M3_BUS_STAT: RUN Mask */ -#define CCU1_CLK_M3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_BUS_STAT: AUTO Position */ -#define CCU1_CLK_M3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_BUS_STAT: AUTO Mask */ -#define CCU1_CLK_M3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_BUS_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_BUS_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SPIFI_CFG ------------------------------------- -#define CCU1_CLK_M3_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SPIFI_CFG: RUN Position */ -#define CCU1_CLK_M3_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: RUN Mask */ -#define CCU1_CLK_M3_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SPIFI_CFG: AUTO Position */ -#define CCU1_CLK_M3_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: AUTO Mask */ -#define CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SPIFI_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_SPIFI_STAT ------------------------------------- -#define CCU1_CLK_M3_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SPIFI_STAT: RUN Position */ -#define CCU1_CLK_M3_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: RUN Mask */ -#define CCU1_CLK_M3_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SPIFI_STAT: AUTO Position */ -#define CCU1_CLK_M3_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: AUTO Mask */ -#define CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SPIFI_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_GPIO_CFG -------------------------------------- -#define CCU1_CLK_M3_GPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_GPIO_CFG: RUN Position */ -#define CCU1_CLK_M3_GPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_RUN_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: RUN Mask */ -#define CCU1_CLK_M3_GPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_GPIO_CFG: AUTO Position */ -#define CCU1_CLK_M3_GPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: AUTO Mask */ -#define CCU1_CLK_M3_GPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_GPIO_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_GPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_GPIO_STAT ------------------------------------- -#define CCU1_CLK_M3_GPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_GPIO_STAT: RUN Position */ -#define CCU1_CLK_M3_GPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_RUN_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: RUN Mask */ -#define CCU1_CLK_M3_GPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_GPIO_STAT: AUTO Position */ -#define CCU1_CLK_M3_GPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: AUTO Mask */ -#define CCU1_CLK_M3_GPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_GPIO_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_GPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M3_LCD_CFG -------------------------------------- -#define CCU1_CLK_M3_LCD_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_LCD_CFG: RUN Position */ -#define CCU1_CLK_M3_LCD_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_RUN_Pos) /*!< CCU1 CLK_M3_LCD_CFG: RUN Mask */ -#define CCU1_CLK_M3_LCD_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_LCD_CFG: AUTO Position */ -#define CCU1_CLK_M3_LCD_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_LCD_CFG: AUTO Mask */ -#define CCU1_CLK_M3_LCD_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_LCD_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_LCD_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_LCD_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_LCD_STAT -------------------------------------- -#define CCU1_CLK_M3_LCD_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_LCD_STAT: RUN Position */ -#define CCU1_CLK_M3_LCD_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_RUN_Pos) /*!< CCU1 CLK_M3_LCD_STAT: RUN Mask */ -#define CCU1_CLK_M3_LCD_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_LCD_STAT: AUTO Position */ -#define CCU1_CLK_M3_LCD_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_LCD_STAT: AUTO Mask */ -#define CCU1_CLK_M3_LCD_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_LCD_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_LCD_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_LCD_STAT: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_M3_ETHERNET_CFG ------------------------------------ -#define CCU1_CLK_M3_ETHERNET_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_ETHERNET_CFG: RUN Position */ -#define CCU1_CLK_M3_ETHERNET_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_RUN_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: RUN Mask */ -#define CCU1_CLK_M3_ETHERNET_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_ETHERNET_CFG: AUTO Position */ -#define CCU1_CLK_M3_ETHERNET_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: AUTO Mask */ -#define CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_ETHERNET_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_M3_ETHERNET_STAT ----------------------------------- -#define CCU1_CLK_M3_ETHERNET_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_ETHERNET_STAT: RUN Position */ -#define CCU1_CLK_M3_ETHERNET_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_RUN_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: RUN Mask */ -#define CCU1_CLK_M3_ETHERNET_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_ETHERNET_STAT: AUTO Position */ -#define CCU1_CLK_M3_ETHERNET_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: AUTO Mask */ -#define CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_ETHERNET_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_USB0_CFG -------------------------------------- -#define CCU1_CLK_M3_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USB0_CFG: RUN Position */ -#define CCU1_CLK_M3_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USB0_CFG: RUN Mask */ -#define CCU1_CLK_M3_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB0_CFG: AUTO Position */ -#define CCU1_CLK_M3_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USB0_CFG: AUTO Mask */ -#define CCU1_CLK_M3_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB0_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB0_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_USB0_STAT ------------------------------------- -#define CCU1_CLK_M3_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USB0_STAT: RUN Position */ -#define CCU1_CLK_M3_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USB0_STAT: RUN Mask */ -#define CCU1_CLK_M3_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB0_STAT: AUTO Position */ -#define CCU1_CLK_M3_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USB0_STAT: AUTO Mask */ -#define CCU1_CLK_M3_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB0_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB0_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M3_EMC_CFG -------------------------------------- -#define CCU1_CLK_M3_EMC_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_EMC_CFG: RUN Position */ -#define CCU1_CLK_M3_EMC_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_RUN_Pos) /*!< CCU1 CLK_M3_EMC_CFG: RUN Mask */ -#define CCU1_CLK_M3_EMC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMC_CFG: AUTO Position */ -#define CCU1_CLK_M3_EMC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_EMC_CFG: AUTO Mask */ -#define CCU1_CLK_M3_EMC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMC_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_EMC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMC_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_EMC_STAT -------------------------------------- -#define CCU1_CLK_M3_EMC_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_EMC_STAT: RUN Position */ -#define CCU1_CLK_M3_EMC_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_RUN_Pos) /*!< CCU1 CLK_M3_EMC_STAT: RUN Mask */ -#define CCU1_CLK_M3_EMC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMC_STAT: AUTO Position */ -#define CCU1_CLK_M3_EMC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_EMC_STAT: AUTO Mask */ -#define CCU1_CLK_M3_EMC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMC_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_EMC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMC_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SDIO_CFG -------------------------------------- -#define CCU1_CLK_M3_SDIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SDIO_CFG: RUN Position */ -#define CCU1_CLK_M3_SDIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: RUN Mask */ -#define CCU1_CLK_M3_SDIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SDIO_CFG: AUTO Position */ -#define CCU1_CLK_M3_SDIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: AUTO Mask */ -#define CCU1_CLK_M3_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SDIO_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SDIO_STAT ------------------------------------- -#define CCU1_CLK_M3_SDIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SDIO_STAT: RUN Position */ -#define CCU1_CLK_M3_SDIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: RUN Mask */ -#define CCU1_CLK_M3_SDIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SDIO_STAT: AUTO Position */ -#define CCU1_CLK_M3_SDIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: AUTO Mask */ -#define CCU1_CLK_M3_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SDIO_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M3_DMA_CFG -------------------------------------- -#define CCU1_CLK_M3_DMA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_DMA_CFG: RUN Position */ -#define CCU1_CLK_M3_DMA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_RUN_Pos) /*!< CCU1 CLK_M3_DMA_CFG: RUN Mask */ -#define CCU1_CLK_M3_DMA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_DMA_CFG: AUTO Position */ -#define CCU1_CLK_M3_DMA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_DMA_CFG: AUTO Mask */ -#define CCU1_CLK_M3_DMA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_DMA_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_DMA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_DMA_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_DMA_STAT -------------------------------------- -#define CCU1_CLK_M3_DMA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_DMA_STAT: RUN Position */ -#define CCU1_CLK_M3_DMA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_RUN_Pos) /*!< CCU1 CLK_M3_DMA_STAT: RUN Mask */ -#define CCU1_CLK_M3_DMA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_DMA_STAT: AUTO Position */ -#define CCU1_CLK_M3_DMA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_DMA_STAT: AUTO Mask */ -#define CCU1_CLK_M3_DMA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_DMA_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_DMA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_DMA_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_M3CORE_CFG ------------------------------------- -#define CCU1_CLK_M3_M3CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_M3CORE_CFG: RUN Position */ -#define CCU1_CLK_M3_M3CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_RUN_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: RUN Mask */ -#define CCU1_CLK_M3_M3CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_M3CORE_CFG: AUTO Position */ -#define CCU1_CLK_M3_M3CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: AUTO Mask */ -#define CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_M3CORE_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_M3CORE_STAT ------------------------------------ -#define CCU1_CLK_M3_M3CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_M3CORE_STAT: RUN Position */ -#define CCU1_CLK_M3_M3CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_RUN_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: RUN Mask */ -#define CCU1_CLK_M3_M3CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_M3CORE_STAT: AUTO Position */ -#define CCU1_CLK_M3_M3CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: AUTO Mask */ -#define CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_M3CORE_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M3_SCT_CFG -------------------------------------- -#define CCU1_CLK_M3_SCT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SCT_CFG: RUN Position */ -#define CCU1_CLK_M3_SCT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SCT_CFG: RUN Mask */ -#define CCU1_CLK_M3_SCT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCT_CFG: AUTO Position */ -#define CCU1_CLK_M3_SCT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SCT_CFG: AUTO Mask */ -#define CCU1_CLK_M3_SCT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCT_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_SCT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCT_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SCT_STAT -------------------------------------- -#define CCU1_CLK_M3_SCT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SCT_STAT: RUN Position */ -#define CCU1_CLK_M3_SCT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SCT_STAT: RUN Mask */ -#define CCU1_CLK_M3_SCT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCT_STAT: AUTO Position */ -#define CCU1_CLK_M3_SCT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SCT_STAT: AUTO Mask */ -#define CCU1_CLK_M3_SCT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCT_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_SCT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCT_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_USB1_CFG -------------------------------------- -#define CCU1_CLK_M3_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USB1_CFG: RUN Position */ -#define CCU1_CLK_M3_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USB1_CFG: RUN Mask */ -#define CCU1_CLK_M3_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB1_CFG: AUTO Position */ -#define CCU1_CLK_M3_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USB1_CFG: AUTO Mask */ -#define CCU1_CLK_M3_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB1_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB1_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_USB1_STAT ------------------------------------- -#define CCU1_CLK_M3_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USB1_STAT: RUN Position */ -#define CCU1_CLK_M3_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USB1_STAT: RUN Mask */ -#define CCU1_CLK_M3_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB1_STAT: AUTO Position */ -#define CCU1_CLK_M3_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USB1_STAT: AUTO Mask */ -#define CCU1_CLK_M3_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB1_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB1_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_EMCDIV_CFG ------------------------------------- -#define CCU1_CLK_M3_EMCDIV_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_EMCDIV_CFG: RUN Position */ -#define CCU1_CLK_M3_EMCDIV_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_RUN_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: RUN Mask */ -#define CCU1_CLK_M3_EMCDIV_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMCDIV_CFG: AUTO Position */ -#define CCU1_CLK_M3_EMCDIV_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: AUTO Mask */ -#define CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMCDIV_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_EMCDIV_STAT ------------------------------------ -#define CCU1_CLK_M3_EMCDIV_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_EMCDIV_STAT: RUN Position */ -#define CCU1_CLK_M3_EMCDIV_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_RUN_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: RUN Mask */ -#define CCU1_CLK_M3_EMCDIV_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMCDIV_STAT: AUTO Position */ -#define CCU1_CLK_M3_EMCDIV_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: AUTO Mask */ -#define CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMCDIV_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_WWDT_CFG -------------------------------------- -#define CCU1_CLK_M3_WWDT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_WWDT_CFG: RUN Position */ -#define CCU1_CLK_M3_WWDT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_RUN_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: RUN Mask */ -#define CCU1_CLK_M3_WWDT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_WWDT_CFG: AUTO Position */ -#define CCU1_CLK_M3_WWDT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: AUTO Mask */ -#define CCU1_CLK_M3_WWDT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_WWDT_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_WWDT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_WWDT_STAT ------------------------------------- -#define CCU1_CLK_M3_WWDT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_WWDT_STAT: RUN Position */ -#define CCU1_CLK_M3_WWDT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_RUN_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: RUN Mask */ -#define CCU1_CLK_M3_WWDT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_WWDT_STAT: AUTO Position */ -#define CCU1_CLK_M3_WWDT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: AUTO Mask */ -#define CCU1_CLK_M3_WWDT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_WWDT_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_WWDT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_USART0_CFG ------------------------------------- -#define CCU1_CLK_M3_USART0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART0_CFG: RUN Position */ -#define CCU1_CLK_M3_USART0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART0_CFG: RUN Mask */ -#define CCU1_CLK_M3_USART0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART0_CFG: AUTO Position */ -#define CCU1_CLK_M3_USART0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART0_CFG: AUTO Mask */ -#define CCU1_CLK_M3_USART0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART0_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_USART0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_USART0_STAT ------------------------------------ -#define CCU1_CLK_M3_USART0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART0_STAT: RUN Position */ -#define CCU1_CLK_M3_USART0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART0_STAT: RUN Mask */ -#define CCU1_CLK_M3_USART0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART0_STAT: AUTO Position */ -#define CCU1_CLK_M3_USART0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART0_STAT: AUTO Mask */ -#define CCU1_CLK_M3_USART0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART0_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_USART0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART0_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_UART1_CFG ------------------------------------- -#define CCU1_CLK_M3_UART1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_UART1_CFG: RUN Position */ -#define CCU1_CLK_M3_UART1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_UART1_CFG: RUN Mask */ -#define CCU1_CLK_M3_UART1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_UART1_CFG: AUTO Position */ -#define CCU1_CLK_M3_UART1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_UART1_CFG: AUTO Mask */ -#define CCU1_CLK_M3_UART1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_UART1_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_UART1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_UART1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_UART1_STAT ------------------------------------- -#define CCU1_CLK_M3_UART1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_UART1_STAT: RUN Position */ -#define CCU1_CLK_M3_UART1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_UART1_STAT: RUN Mask */ -#define CCU1_CLK_M3_UART1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_UART1_STAT: AUTO Position */ -#define CCU1_CLK_M3_UART1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_UART1_STAT: AUTO Mask */ -#define CCU1_CLK_M3_UART1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_UART1_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_UART1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_UART1_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SSP0_CFG -------------------------------------- -#define CCU1_CLK_M3_SSP0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP0_CFG: RUN Position */ -#define CCU1_CLK_M3_SSP0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: RUN Mask */ -#define CCU1_CLK_M3_SSP0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP0_CFG: AUTO Position */ -#define CCU1_CLK_M3_SSP0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: AUTO Mask */ -#define CCU1_CLK_M3_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP0_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SSP0_STAT ------------------------------------- -#define CCU1_CLK_M3_SSP0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP0_STAT: RUN Position */ -#define CCU1_CLK_M3_SSP0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: RUN Mask */ -#define CCU1_CLK_M3_SSP0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP0_STAT: AUTO Position */ -#define CCU1_CLK_M3_SSP0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: AUTO Mask */ -#define CCU1_CLK_M3_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP0_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_TIMER0_CFG ------------------------------------- -#define CCU1_CLK_M3_TIMER0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER0_CFG: RUN Position */ -#define CCU1_CLK_M3_TIMER0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: RUN Mask */ -#define CCU1_CLK_M3_TIMER0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER0_CFG: AUTO Position */ -#define CCU1_CLK_M3_TIMER0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: AUTO Mask */ -#define CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER0_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_TIMER0_STAT ------------------------------------ -#define CCU1_CLK_M3_TIMER0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER0_STAT: RUN Position */ -#define CCU1_CLK_M3_TIMER0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: RUN Mask */ -#define CCU1_CLK_M3_TIMER0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER0_STAT: AUTO Position */ -#define CCU1_CLK_M3_TIMER0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: AUTO Mask */ -#define CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER0_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_TIMER1_CFG ------------------------------------- -#define CCU1_CLK_M3_TIMER1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER1_CFG: RUN Position */ -#define CCU1_CLK_M3_TIMER1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: RUN Mask */ -#define CCU1_CLK_M3_TIMER1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER1_CFG: AUTO Position */ -#define CCU1_CLK_M3_TIMER1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: AUTO Mask */ -#define CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER1_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_TIMER1_STAT ------------------------------------ -#define CCU1_CLK_M3_TIMER1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER1_STAT: RUN Position */ -#define CCU1_CLK_M3_TIMER1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: RUN Mask */ -#define CCU1_CLK_M3_TIMER1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER1_STAT: AUTO Position */ -#define CCU1_CLK_M3_TIMER1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: AUTO Mask */ -#define CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER1_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M3_SCU_CFG -------------------------------------- -#define CCU1_CLK_M3_SCU_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SCU_CFG: RUN Position */ -#define CCU1_CLK_M3_SCU_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SCU_CFG: RUN Mask */ -#define CCU1_CLK_M3_SCU_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCU_CFG: AUTO Position */ -#define CCU1_CLK_M3_SCU_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SCU_CFG: AUTO Mask */ -#define CCU1_CLK_M3_SCU_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCU_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_SCU_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCU_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SCU_STAT -------------------------------------- -#define CCU1_CLK_M3_SCU_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SCU_STAT: RUN Position */ -#define CCU1_CLK_M3_SCU_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SCU_STAT: RUN Mask */ -#define CCU1_CLK_M3_SCU_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCU_STAT: AUTO Position */ -#define CCU1_CLK_M3_SCU_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SCU_STAT: AUTO Mask */ -#define CCU1_CLK_M3_SCU_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCU_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_SCU_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCU_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_CREG_CFG -------------------------------------- -#define CCU1_CLK_M3_CREG_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_CREG_CFG: RUN Position */ -#define CCU1_CLK_M3_CREG_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_RUN_Pos) /*!< CCU1 CLK_M3_CREG_CFG: RUN Mask */ -#define CCU1_CLK_M3_CREG_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_CREG_CFG: AUTO Position */ -#define CCU1_CLK_M3_CREG_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_CREG_CFG: AUTO Mask */ -#define CCU1_CLK_M3_CREG_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_CREG_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_CREG_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_CREG_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_CREG_STAT ------------------------------------- -#define CCU1_CLK_M3_CREG_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_CREG_STAT: RUN Position */ -#define CCU1_CLK_M3_CREG_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_RUN_Pos) /*!< CCU1 CLK_M3_CREG_STAT: RUN Mask */ -#define CCU1_CLK_M3_CREG_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_CREG_STAT: AUTO Position */ -#define CCU1_CLK_M3_CREG_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_CREG_STAT: AUTO Mask */ -#define CCU1_CLK_M3_CREG_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_CREG_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_CREG_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_CREG_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_RITIMER_CFG ------------------------------------ -#define CCU1_CLK_M3_RITIMER_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_RITIMER_CFG: RUN Position */ -#define CCU1_CLK_M3_RITIMER_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_RUN_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: RUN Mask */ -#define CCU1_CLK_M3_RITIMER_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_RITIMER_CFG: AUTO Position */ -#define CCU1_CLK_M3_RITIMER_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: AUTO Mask */ -#define CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_RITIMER_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_M3_RITIMER_STAT ------------------------------------ -#define CCU1_CLK_M3_RITIMER_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_RITIMER_STAT: RUN Position */ -#define CCU1_CLK_M3_RITIMER_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_RUN_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: RUN Mask */ -#define CCU1_CLK_M3_RITIMER_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_RITIMER_STAT: AUTO Position */ -#define CCU1_CLK_M3_RITIMER_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: AUTO Mask */ -#define CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_RITIMER_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_USART2_CFG ------------------------------------- -#define CCU1_CLK_M3_USART2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART2_CFG: RUN Position */ -#define CCU1_CLK_M3_USART2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART2_CFG: RUN Mask */ -#define CCU1_CLK_M3_USART2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART2_CFG: AUTO Position */ -#define CCU1_CLK_M3_USART2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART2_CFG: AUTO Mask */ -#define CCU1_CLK_M3_USART2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART2_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_USART2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART2_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_USART2_STAT ------------------------------------ -#define CCU1_CLK_M3_USART2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART2_STAT: RUN Position */ -#define CCU1_CLK_M3_USART2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART2_STAT: RUN Mask */ -#define CCU1_CLK_M3_USART2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART2_STAT: AUTO Position */ -#define CCU1_CLK_M3_USART2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART2_STAT: AUTO Mask */ -#define CCU1_CLK_M3_USART2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART2_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_USART2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART2_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_USART3_CFG ------------------------------------- -#define CCU1_CLK_M3_USART3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART3_CFG: RUN Position */ -#define CCU1_CLK_M3_USART3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART3_CFG: RUN Mask */ -#define CCU1_CLK_M3_USART3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART3_CFG: AUTO Position */ -#define CCU1_CLK_M3_USART3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART3_CFG: AUTO Mask */ -#define CCU1_CLK_M3_USART3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART3_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_USART3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART3_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_USART3_STAT ------------------------------------ -#define CCU1_CLK_M3_USART3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART3_STAT: RUN Position */ -#define CCU1_CLK_M3_USART3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART3_STAT: RUN Mask */ -#define CCU1_CLK_M3_USART3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART3_STAT: AUTO Position */ -#define CCU1_CLK_M3_USART3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART3_STAT: AUTO Mask */ -#define CCU1_CLK_M3_USART3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART3_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_USART3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART3_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_TIMER2_CFG ------------------------------------- -#define CCU1_CLK_M3_TIMER2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER2_CFG: RUN Position */ -#define CCU1_CLK_M3_TIMER2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: RUN Mask */ -#define CCU1_CLK_M3_TIMER2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER2_CFG: AUTO Position */ -#define CCU1_CLK_M3_TIMER2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: AUTO Mask */ -#define CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER2_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_TIMER2_STAT ------------------------------------ -#define CCU1_CLK_M3_TIMER2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER2_STAT: RUN Position */ -#define CCU1_CLK_M3_TIMER2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: RUN Mask */ -#define CCU1_CLK_M3_TIMER2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER2_STAT: AUTO Position */ -#define CCU1_CLK_M3_TIMER2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: AUTO Mask */ -#define CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER2_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_TIMER3_CFG ------------------------------------- -#define CCU1_CLK_M3_TIMER3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER3_CFG: RUN Position */ -#define CCU1_CLK_M3_TIMER3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: RUN Mask */ -#define CCU1_CLK_M3_TIMER3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER3_CFG: AUTO Position */ -#define CCU1_CLK_M3_TIMER3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: AUTO Mask */ -#define CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER3_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M3_TIMER3_STAT ------------------------------------ -#define CCU1_CLK_M3_TIMER3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER3_STAT: RUN Position */ -#define CCU1_CLK_M3_TIMER3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: RUN Mask */ -#define CCU1_CLK_M3_TIMER3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER3_STAT: AUTO Position */ -#define CCU1_CLK_M3_TIMER3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: AUTO Mask */ -#define CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER3_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SSP1_CFG -------------------------------------- -#define CCU1_CLK_M3_SSP1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP1_CFG: RUN Position */ -#define CCU1_CLK_M3_SSP1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: RUN Mask */ -#define CCU1_CLK_M3_SSP1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP1_CFG: AUTO Position */ -#define CCU1_CLK_M3_SSP1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: AUTO Mask */ -#define CCU1_CLK_M3_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP1_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_SSP1_STAT ------------------------------------- -#define CCU1_CLK_M3_SSP1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP1_STAT: RUN Position */ -#define CCU1_CLK_M3_SSP1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: RUN Mask */ -#define CCU1_CLK_M3_SSP1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP1_STAT: AUTO Position */ -#define CCU1_CLK_M3_SSP1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: AUTO Mask */ -#define CCU1_CLK_M3_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP1_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M3_QEI_CFG -------------------------------------- -#define CCU1_CLK_M3_QEI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_QEI_CFG: RUN Position */ -#define CCU1_CLK_M3_QEI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_RUN_Pos) /*!< CCU1 CLK_M3_QEI_CFG: RUN Mask */ -#define CCU1_CLK_M3_QEI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_QEI_CFG: AUTO Position */ -#define CCU1_CLK_M3_QEI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_QEI_CFG: AUTO Mask */ -#define CCU1_CLK_M3_QEI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_QEI_CFG: WAKEUP Position */ -#define CCU1_CLK_M3_QEI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_QEI_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M3_QEI_STAT -------------------------------------- -#define CCU1_CLK_M3_QEI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_QEI_STAT: RUN Position */ -#define CCU1_CLK_M3_QEI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_RUN_Pos) /*!< CCU1 CLK_M3_QEI_STAT: RUN Mask */ -#define CCU1_CLK_M3_QEI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_QEI_STAT: AUTO Position */ -#define CCU1_CLK_M3_QEI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_QEI_STAT: AUTO Mask */ -#define CCU1_CLK_M3_QEI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_QEI_STAT: WAKEUP Position */ -#define CCU1_CLK_M3_QEI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_QEI_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_PERIPH_BUS_CFG ------------------------------------ -#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */ -#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask */ -#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */ -#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask */ -#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */ -#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_PERIPH_BUS_STAT ------------------------------------ -#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */ -#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask */ -#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */ -#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */ -#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */ -#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_PERIPH_CORE_CFG ------------------------------------ -#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */ -#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask */ -#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */ -#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */ -#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */ -#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_PERIPH_CORE_STAT ----------------------------------- -#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */ -#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */ -#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */ -#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */ -#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */ -#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */ - - -// ------------------------------------ CCU1_CLK_USB0_CFG --------------------------------------- -#define CCU1_CLK_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB0_CFG: RUN Position */ -#define CCU1_CLK_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_USB0_CFG: RUN Mask */ -#define CCU1_CLK_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB0_CFG: AUTO Position */ -#define CCU1_CLK_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_USB0_CFG: AUTO Mask */ -#define CCU1_CLK_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_CFG: WAKEUP Position */ -#define CCU1_CLK_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_USB0_STAT --------------------------------------- -#define CCU1_CLK_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB0_STAT: RUN Position */ -#define CCU1_CLK_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_USB0_STAT: RUN Mask */ -#define CCU1_CLK_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB0_STAT: AUTO Position */ -#define CCU1_CLK_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_USB0_STAT: AUTO Mask */ -#define CCU1_CLK_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */ -#define CCU1_CLK_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask */ - -// ------------------------------------ CCU1_CLK_USB1_CFG --------------------------------------- -#define CCU1_CLK_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB1_CFG: RUN Position */ -#define CCU1_CLK_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_USB1_CFG: RUN Mask */ -#define CCU1_CLK_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB1_CFG: AUTO Position */ -#define CCU1_CLK_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_USB1_CFG: AUTO Mask */ -#define CCU1_CLK_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_CFG: WAKEUP Position */ -#define CCU1_CLK_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_USB1_STAT --------------------------------------- -#define CCU1_CLK_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB1_STAT: RUN Position */ -#define CCU1_CLK_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_USB1_STAT: RUN Mask */ -#define CCU1_CLK_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB1_STAT: AUTO Position */ -#define CCU1_CLK_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_USB1_STAT: AUTO Mask */ -#define CCU1_CLK_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */ -#define CCU1_CLK_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask */ - -// ------------------------------------ CCU1_CLK_VADC_CFG --------------------------------------- -#define CCU1_CLK_VADC_CFG_RUN_Pos 0 /*!< CCU1 CLK_VADC_CFG: RUN Position */ -#define CCU1_CLK_VADC_CFG_RUN_Msk (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos) /*!< CCU1 CLK_VADC_CFG: RUN Mask */ -#define CCU1_CLK_VADC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_VADC_CFG: AUTO Position */ -#define CCU1_CLK_VADC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos) /*!< CCU1 CLK_VADC_CFG: AUTO Mask */ -#define CCU1_CLK_VADC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_CFG: WAKEUP Position */ -#define CCU1_CLK_VADC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_VADC_STAT --------------------------------------- -#define CCU1_CLK_VADC_STAT_RUN_Pos 0 /*!< CCU1 CLK_VADC_STAT: RUN Position */ -#define CCU1_CLK_VADC_STAT_RUN_Msk (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos) /*!< CCU1 CLK_VADC_STAT: RUN Mask */ -#define CCU1_CLK_VADC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_VADC_STAT: AUTO Position */ -#define CCU1_CLK_VADC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos) /*!< CCU1 CLK_VADC_STAT: AUTO Mask */ -#define CCU1_CLK_VADC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */ -#define CCU1_CLK_VADC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- CCU2 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- CCU2_PM -------------------------------------------- -#define CCU2_PM_PD_Pos 0 /*!< CCU2 PM: PD Position */ -#define CCU2_PM_PD_Msk (0x01UL << CCU2_PM_PD_Pos) /*!< CCU2 PM: PD Mask */ - -// ------------------------------------- CCU2_BASE_STAT ----------------------------------------- -#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos 1 /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */ -#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */ -#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos 2 /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */ -#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */ -#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos 3 /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */ -#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */ -#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos 4 /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */ -#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */ -#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos 5 /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */ -#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask */ -#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos 6 /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */ -#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask */ - -// ----------------------------------- CCU2_CLK_APLL3_CFG --------------------------------------- -#define CCU2_CLK_APLL3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APLL3_CFG: RUN Position */ -#define CCU2_CLK_APLL3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APLL3_CFG_RUN_Pos) /*!< CCU2 CLK_APLL3_CFG: RUN Mask */ -#define CCU2_CLK_APLL3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APLL3_CFG: AUTO Position */ -#define CCU2_CLK_APLL3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APLL3_CFG_AUTO_Pos) /*!< CCU2 CLK_APLL3_CFG: AUTO Mask */ -#define CCU2_CLK_APLL3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL3_CFG: WAKEUP Position */ -#define CCU2_CLK_APLL3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APLL3_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU2_CLK_APLL_STAT --------------------------------------- -#define CCU2_CLK_APLL_STAT_RUN_Pos 0 /*!< CCU2 CLK_APLL_STAT: RUN Position */ -#define CCU2_CLK_APLL_STAT_RUN_Msk (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos) /*!< CCU2 CLK_APLL_STAT: RUN Mask */ -#define CCU2_CLK_APLL_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APLL_STAT: AUTO Position */ -#define CCU2_CLK_APLL_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos) /*!< CCU2 CLK_APLL_STAT: AUTO Mask */ -#define CCU2_CLK_APLL_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */ -#define CCU2_CLK_APLL_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB2_USART3_CFG ------------------------------------ -#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */ -#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask */ -#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */ -#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */ -#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */ -#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB2_USART3_STAT ----------------------------------- -#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */ -#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */ -#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */ -#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */ -#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */ -#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB2_USART2_CFG ------------------------------------ -#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */ -#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask */ -#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */ -#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */ -#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */ -#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB2_USART2_STAT ----------------------------------- -#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */ -#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */ -#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */ -#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */ -#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */ -#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */ - -// ------------------------------- CCU2_CLK_APB0_UART1_BUS_CFG ---------------------------------- -#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB0_UART1_STAT ------------------------------------ -#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */ -#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask */ -#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */ -#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */ -#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */ -#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB0_USART0_CFG ------------------------------------ -#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */ -#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask */ -#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */ -#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */ -#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */ -#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB0_USART0_STAT ----------------------------------- -#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */ -#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */ -#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */ -#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */ -#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */ -#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */ - -// --------------------------------- CCU2_CLK_APB2_SSP1_CFG ------------------------------------- -#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */ -#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask */ -#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */ -#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask */ -#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */ -#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU2_CLK_APB2_SSP1_STAT ------------------------------------ -#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */ -#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask */ -#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */ -#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask */ -#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */ -#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */ - -// --------------------------------- CCU2_CLK_APB0_SSP0_CFG ------------------------------------- -#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */ -#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask */ -#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */ -#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask */ -#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */ -#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU2_CLK_APB0_SSP0_STAT ------------------------------------ -#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */ -#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask */ -#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */ -#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask */ -#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */ -#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */ - -// ------------------------------------ CCU2_CLK_SDIO_CFG --------------------------------------- -#define CCU2_CLK_SDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_SDIO_CFG: RUN Position */ -#define CCU2_CLK_SDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos) /*!< CCU2 CLK_SDIO_CFG: RUN Mask */ -#define CCU2_CLK_SDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_CFG: AUTO Position */ -#define CCU2_CLK_SDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_SDIO_CFG: AUTO Mask */ -#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position */ -#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU2_CLK_SDIO_STAT --------------------------------------- -#define CCU2_CLK_SDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_SDIO_STAT: RUN Position */ -#define CCU2_CLK_SDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos) /*!< CCU2 CLK_SDIO_STAT: RUN Mask */ -#define CCU2_CLK_SDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_STAT: AUTO Position */ -#define CCU2_CLK_SDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_SDIO_STAT: AUTO Mask */ -#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */ -#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- RGU Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- RGU_RESET_CTRL0 ---------------------------------------- -#define RGU_RESET_CTRL0_CORE_RST_Pos 0 /*!< RGU RESET_CTRL0: CORE_RST Position */ -#define RGU_RESET_CTRL0_CORE_RST_Msk (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos) /*!< RGU RESET_CTRL0: CORE_RST Mask */ -#define RGU_RESET_CTRL0_PERIPH_RST_Pos 1 /*!< RGU RESET_CTRL0: PERIPH_RST Position */ -#define RGU_RESET_CTRL0_PERIPH_RST_Msk (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos) /*!< RGU RESET_CTRL0: PERIPH_RST Mask */ -#define RGU_RESET_CTRL0_MASTER_RST_Pos 2 /*!< RGU RESET_CTRL0: MASTER_RST Position */ -#define RGU_RESET_CTRL0_MASTER_RST_Msk (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos) /*!< RGU RESET_CTRL0: MASTER_RST Mask */ -#define RGU_RESET_CTRL0_WWDT_RST_Pos 4 /*!< RGU RESET_CTRL0: WWDT_RST Position */ -#define RGU_RESET_CTRL0_WWDT_RST_Msk (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos) /*!< RGU RESET_CTRL0: WWDT_RST Mask */ -#define RGU_RESET_CTRL0_CREG_RST_Pos 5 /*!< RGU RESET_CTRL0: CREG_RST Position */ -#define RGU_RESET_CTRL0_CREG_RST_Msk (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos) /*!< RGU RESET_CTRL0: CREG_RST Mask */ -#define RGU_RESET_CTRL0_BUS_RST_Pos 8 /*!< RGU RESET_CTRL0: BUS_RST Position */ -#define RGU_RESET_CTRL0_BUS_RST_Msk (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos) /*!< RGU RESET_CTRL0: BUS_RST Mask */ -#define RGU_RESET_CTRL0_SCU_RST_Pos 9 /*!< RGU RESET_CTRL0: SCU_RST Position */ -#define RGU_RESET_CTRL0_SCU_RST_Msk (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos) /*!< RGU RESET_CTRL0: SCU_RST Mask */ -#define RGU_RESET_CTRL0_PINMUX_RST_Pos 10 /*!< RGU RESET_CTRL0: PINMUX_RST Position */ -#define RGU_RESET_CTRL0_PINMUX_RST_Msk (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos) /*!< RGU RESET_CTRL0: PINMUX_RST Mask */ -#define RGU_RESET_CTRL0_M3_RST_Pos 13 /*!< RGU RESET_CTRL0: M3_RST Position */ -#define RGU_RESET_CTRL0_M3_RST_Msk (0x01UL << RGU_RESET_CTRL0_M3_RST_Pos) /*!< RGU RESET_CTRL0: M3_RST Mask */ -#define RGU_RESET_CTRL0_LCD_RST_Pos 16 /*!< RGU RESET_CTRL0: LCD_RST Position */ -#define RGU_RESET_CTRL0_LCD_RST_Msk (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos) /*!< RGU RESET_CTRL0: LCD_RST Mask */ -#define RGU_RESET_CTRL0_USB0_RST_Pos 17 /*!< RGU RESET_CTRL0: USB0_RST Position */ -#define RGU_RESET_CTRL0_USB0_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos) /*!< RGU RESET_CTRL0: USB0_RST Mask */ -#define RGU_RESET_CTRL0_USB1_RST_Pos 18 /*!< RGU RESET_CTRL0: USB1_RST Position */ -#define RGU_RESET_CTRL0_USB1_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos) /*!< RGU RESET_CTRL0: USB1_RST Mask */ -#define RGU_RESET_CTRL0_DMA_RST_Pos 19 /*!< RGU RESET_CTRL0: DMA_RST Position */ -#define RGU_RESET_CTRL0_DMA_RST_Msk (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos) /*!< RGU RESET_CTRL0: DMA_RST Mask */ -#define RGU_RESET_CTRL0_SDIO_RST_Pos 20 /*!< RGU RESET_CTRL0: SDIO_RST Position */ -#define RGU_RESET_CTRL0_SDIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos) /*!< RGU RESET_CTRL0: SDIO_RST Mask */ -#define RGU_RESET_CTRL0_EMC_RST_Pos 21 /*!< RGU RESET_CTRL0: EMC_RST Position */ -#define RGU_RESET_CTRL0_EMC_RST_Msk (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos) /*!< RGU RESET_CTRL0: EMC_RST Mask */ -#define RGU_RESET_CTRL0_ETHERNET_RST_Pos 22 /*!< RGU RESET_CTRL0: ETHERNET_RST Position */ -#define RGU_RESET_CTRL0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos) /*!< RGU RESET_CTRL0: ETHERNET_RST Mask */ -#define RGU_RESET_CTRL0_GPIO_RST_Pos 28 /*!< RGU RESET_CTRL0: GPIO_RST Position */ -#define RGU_RESET_CTRL0_GPIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos) /*!< RGU RESET_CTRL0: GPIO_RST Mask */ - -// ------------------------------------- RGU_RESET_CTRL1 ---------------------------------------- -#define RGU_RESET_CTRL1_TIMER0_RST_Pos 0 /*!< RGU RESET_CTRL1: TIMER0_RST Position */ -#define RGU_RESET_CTRL1_TIMER0_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos) /*!< RGU RESET_CTRL1: TIMER0_RST Mask */ -#define RGU_RESET_CTRL1_TIMER1_RST_Pos 1 /*!< RGU RESET_CTRL1: TIMER1_RST Position */ -#define RGU_RESET_CTRL1_TIMER1_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos) /*!< RGU RESET_CTRL1: TIMER1_RST Mask */ -#define RGU_RESET_CTRL1_TIMER2_RST_Pos 2 /*!< RGU RESET_CTRL1: TIMER2_RST Position */ -#define RGU_RESET_CTRL1_TIMER2_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos) /*!< RGU RESET_CTRL1: TIMER2_RST Mask */ -#define RGU_RESET_CTRL1_TIMER3_RST_Pos 3 /*!< RGU RESET_CTRL1: TIMER3_RST Position */ -#define RGU_RESET_CTRL1_TIMER3_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos) /*!< RGU RESET_CTRL1: TIMER3_RST Mask */ -#define RGU_RESET_CTRL1_RITIMER_RST_Pos 4 /*!< RGU RESET_CTRL1: RITIMER_RST Position */ -#define RGU_RESET_CTRL1_RITIMER_RST_Msk (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos) /*!< RGU RESET_CTRL1: RITIMER_RST Mask */ -#define RGU_RESET_CTRL1_SCT_RST_Pos 5 /*!< RGU RESET_CTRL1: SCT_RST Position */ -#define RGU_RESET_CTRL1_SCT_RST_Msk (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos) /*!< RGU RESET_CTRL1: SCT_RST Mask */ -#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */ -#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */ -#define RGU_RESET_CTRL1_QEI_RST_Pos 7 /*!< RGU RESET_CTRL1: QEI_RST Position */ -#define RGU_RESET_CTRL1_QEI_RST_Msk (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos) /*!< RGU RESET_CTRL1: QEI_RST Mask */ -#define RGU_RESET_CTRL1_ADC0_RST_Pos 8 /*!< RGU RESET_CTRL1: ADC0_RST Position */ -#define RGU_RESET_CTRL1_ADC0_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos) /*!< RGU RESET_CTRL1: ADC0_RST Mask */ -#define RGU_RESET_CTRL1_ADC1_RST_Pos 9 /*!< RGU RESET_CTRL1: ADC1_RST Position */ -#define RGU_RESET_CTRL1_ADC1_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos) /*!< RGU RESET_CTRL1: ADC1_RST Mask */ -#define RGU_RESET_CTRL1_DAC_RST_Pos 10 /*!< RGU RESET_CTRL1: DAC_RST Position */ -#define RGU_RESET_CTRL1_DAC_RST_Msk (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos) /*!< RGU RESET_CTRL1: DAC_RST Mask */ -#define RGU_RESET_CTRL1_UART0_RST_Pos 12 /*!< RGU RESET_CTRL1: UART0_RST Position */ -#define RGU_RESET_CTRL1_UART0_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos) /*!< RGU RESET_CTRL1: UART0_RST Mask */ -#define RGU_RESET_CTRL1_UART1_RST_Pos 13 /*!< RGU RESET_CTRL1: UART1_RST Position */ -#define RGU_RESET_CTRL1_UART1_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos) /*!< RGU RESET_CTRL1: UART1_RST Mask */ -#define RGU_RESET_CTRL1_UART2_RST_Pos 14 /*!< RGU RESET_CTRL1: UART2_RST Position */ -#define RGU_RESET_CTRL1_UART2_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos) /*!< RGU RESET_CTRL1: UART2_RST Mask */ -#define RGU_RESET_CTRL1_UART3_RST_Pos 15 /*!< RGU RESET_CTRL1: UART3_RST Position */ -#define RGU_RESET_CTRL1_UART3_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos) /*!< RGU RESET_CTRL1: UART3_RST Mask */ -#define RGU_RESET_CTRL1_I2C0_RST_Pos 16 /*!< RGU RESET_CTRL1: I2C0_RST Position */ -#define RGU_RESET_CTRL1_I2C0_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos) /*!< RGU RESET_CTRL1: I2C0_RST Mask */ -#define RGU_RESET_CTRL1_I2C1_RST_Pos 17 /*!< RGU RESET_CTRL1: I2C1_RST Position */ -#define RGU_RESET_CTRL1_I2C1_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos) /*!< RGU RESET_CTRL1: I2C1_RST Mask */ -#define RGU_RESET_CTRL1_SSP0_RST_Pos 18 /*!< RGU RESET_CTRL1: SSP0_RST Position */ -#define RGU_RESET_CTRL1_SSP0_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos) /*!< RGU RESET_CTRL1: SSP0_RST Mask */ -#define RGU_RESET_CTRL1_SSP1_RST_Pos 19 /*!< RGU RESET_CTRL1: SSP1_RST Position */ -#define RGU_RESET_CTRL1_SSP1_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos) /*!< RGU RESET_CTRL1: SSP1_RST Mask */ -#define RGU_RESET_CTRL1_I2S_RST_Pos 20 /*!< RGU RESET_CTRL1: I2S_RST Position */ -#define RGU_RESET_CTRL1_I2S_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos) /*!< RGU RESET_CTRL1: I2S_RST Mask */ -#define RGU_RESET_CTRL1_SPIFI_RST_Pos 21 /*!< RGU RESET_CTRL1: SPIFI_RST Position */ -#define RGU_RESET_CTRL1_SPIFI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos) /*!< RGU RESET_CTRL1: SPIFI_RST Mask */ -#define RGU_RESET_CTRL1_CAN1_RST_Pos 22 /*!< RGU RESET_CTRL1: CAN1_RST Position */ -#define RGU_RESET_CTRL1_CAN1_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos) /*!< RGU RESET_CTRL1: CAN1_RST Mask */ -#define RGU_RESET_CTRL1_CAN0_RST_Pos 23 /*!< RGU RESET_CTRL1: CAN0_RST Position */ -#define RGU_RESET_CTRL1_CAN0_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos) /*!< RGU RESET_CTRL1: CAN0_RST Mask */ - -// ------------------------------------ RGU_RESET_STATUS0 --------------------------------------- -#define RGU_RESET_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_STATUS0: CORE_RST Position */ -#define RGU_RESET_STATUS0_CORE_RST_Msk (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos) /*!< RGU RESET_STATUS0: CORE_RST Mask */ -#define RGU_RESET_STATUS0_PERIPH_RST_Pos 2 /*!< RGU RESET_STATUS0: PERIPH_RST Position */ -#define RGU_RESET_STATUS0_PERIPH_RST_Msk (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_STATUS0: PERIPH_RST Mask */ -#define RGU_RESET_STATUS0_MASTER_RST_Pos 4 /*!< RGU RESET_STATUS0: MASTER_RST Position */ -#define RGU_RESET_STATUS0_MASTER_RST_Msk (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_STATUS0: MASTER_RST Mask */ -#define RGU_RESET_STATUS0_WWDT_RST_Pos 8 /*!< RGU RESET_STATUS0: WWDT_RST Position */ -#define RGU_RESET_STATUS0_WWDT_RST_Msk (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_STATUS0: WWDT_RST Mask */ -#define RGU_RESET_STATUS0_CREG_RST_Pos 10 /*!< RGU RESET_STATUS0: CREG_RST Position */ -#define RGU_RESET_STATUS0_CREG_RST_Msk (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos) /*!< RGU RESET_STATUS0: CREG_RST Mask */ -#define RGU_RESET_STATUS0_BUS_RST_Pos 16 /*!< RGU RESET_STATUS0: BUS_RST Position */ -#define RGU_RESET_STATUS0_BUS_RST_Msk (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos) /*!< RGU RESET_STATUS0: BUS_RST Mask */ -#define RGU_RESET_STATUS0_SCU_RST_Pos 18 /*!< RGU RESET_STATUS0: SCU_RST Position */ -#define RGU_RESET_STATUS0_SCU_RST_Msk (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos) /*!< RGU RESET_STATUS0: SCU_RST Mask */ -#define RGU_RESET_STATUS0_M3_RST_Pos 26 /*!< RGU RESET_STATUS0: M3_RST Position */ -#define RGU_RESET_STATUS0_M3_RST_Msk (0x03UL << RGU_RESET_STATUS0_M3_RST_Pos) /*!< RGU RESET_STATUS0: M3_RST Mask */ - -// ------------------------------------ RGU_RESET_STATUS1 --------------------------------------- -#define RGU_RESET_STATUS1_LCD_RST_Pos 0 /*!< RGU RESET_STATUS1: LCD_RST Position */ -#define RGU_RESET_STATUS1_LCD_RST_Msk (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos) /*!< RGU RESET_STATUS1: LCD_RST Mask */ -#define RGU_RESET_STATUS1_USB0_RST_Pos 2 /*!< RGU RESET_STATUS1: USB0_RST Position */ -#define RGU_RESET_STATUS1_USB0_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos) /*!< RGU RESET_STATUS1: USB0_RST Mask */ -#define RGU_RESET_STATUS1_USB1_RST_Pos 4 /*!< RGU RESET_STATUS1: USB1_RST Position */ -#define RGU_RESET_STATUS1_USB1_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos) /*!< RGU RESET_STATUS1: USB1_RST Mask */ -#define RGU_RESET_STATUS1_DMA_RST_Pos 6 /*!< RGU RESET_STATUS1: DMA_RST Position */ -#define RGU_RESET_STATUS1_DMA_RST_Msk (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos) /*!< RGU RESET_STATUS1: DMA_RST Mask */ -#define RGU_RESET_STATUS1_SDIO_RST_Pos 8 /*!< RGU RESET_STATUS1: SDIO_RST Position */ -#define RGU_RESET_STATUS1_SDIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos) /*!< RGU RESET_STATUS1: SDIO_RST Mask */ -#define RGU_RESET_STATUS1_EMC_RST_Pos 10 /*!< RGU RESET_STATUS1: EMC_RST Position */ -#define RGU_RESET_STATUS1_EMC_RST_Msk (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos) /*!< RGU RESET_STATUS1: EMC_RST Mask */ -#define RGU_RESET_STATUS1_ETHERNET_RST_Pos 12 /*!< RGU RESET_STATUS1: ETHERNET_RST Position */ -#define RGU_RESET_STATUS1_ETHERNET_RST_Msk (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos) /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */ -#define RGU_RESET_STATUS1_GPIO_RST_Pos 24 /*!< RGU RESET_STATUS1: GPIO_RST Position */ -#define RGU_RESET_STATUS1_GPIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos) /*!< RGU RESET_STATUS1: GPIO_RST Mask */ - -// ------------------------------------ RGU_RESET_STATUS2 --------------------------------------- -#define RGU_RESET_STATUS2_TIMER0_RST_Pos 0 /*!< RGU RESET_STATUS2: TIMER0_RST Position */ -#define RGU_RESET_STATUS2_TIMER0_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos) /*!< RGU RESET_STATUS2: TIMER0_RST Mask */ -#define RGU_RESET_STATUS2_TIMER1_RST_Pos 2 /*!< RGU RESET_STATUS2: TIMER1_RST Position */ -#define RGU_RESET_STATUS2_TIMER1_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos) /*!< RGU RESET_STATUS2: TIMER1_RST Mask */ -#define RGU_RESET_STATUS2_TIMER2_RST_Pos 4 /*!< RGU RESET_STATUS2: TIMER2_RST Position */ -#define RGU_RESET_STATUS2_TIMER2_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos) /*!< RGU RESET_STATUS2: TIMER2_RST Mask */ -#define RGU_RESET_STATUS2_TIMER3_RST_Pos 6 /*!< RGU RESET_STATUS2: TIMER3_RST Position */ -#define RGU_RESET_STATUS2_TIMER3_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos) /*!< RGU RESET_STATUS2: TIMER3_RST Mask */ -#define RGU_RESET_STATUS2_RITIMER_RST_Pos 8 /*!< RGU RESET_STATUS2: RITIMER_RST Position */ -#define RGU_RESET_STATUS2_RITIMER_RST_Msk (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos) /*!< RGU RESET_STATUS2: RITIMER_RST Mask */ -#define RGU_RESET_STATUS2_SCT_RST_Pos 10 /*!< RGU RESET_STATUS2: SCT_RST Position */ -#define RGU_RESET_STATUS2_SCT_RST_Msk (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos) /*!< RGU RESET_STATUS2: SCT_RST Mask */ -#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos 12 /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */ -#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos) /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */ -#define RGU_RESET_STATUS2_QEI_RST_Pos 14 /*!< RGU RESET_STATUS2: QEI_RST Position */ -#define RGU_RESET_STATUS2_QEI_RST_Msk (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos) /*!< RGU RESET_STATUS2: QEI_RST Mask */ -#define RGU_RESET_STATUS2_ADC0_RST_Pos 16 /*!< RGU RESET_STATUS2: ADC0_RST Position */ -#define RGU_RESET_STATUS2_ADC0_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos) /*!< RGU RESET_STATUS2: ADC0_RST Mask */ -#define RGU_RESET_STATUS2_ADC1_RST_Pos 18 /*!< RGU RESET_STATUS2: ADC1_RST Position */ -#define RGU_RESET_STATUS2_ADC1_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos) /*!< RGU RESET_STATUS2: ADC1_RST Mask */ -#define RGU_RESET_STATUS2_DAC_RST_Pos 20 /*!< RGU RESET_STATUS2: DAC_RST Position */ -#define RGU_RESET_STATUS2_DAC_RST_Msk (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos) /*!< RGU RESET_STATUS2: DAC_RST Mask */ -#define RGU_RESET_STATUS2_UART0_RST_Pos 24 /*!< RGU RESET_STATUS2: UART0_RST Position */ -#define RGU_RESET_STATUS2_UART0_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos) /*!< RGU RESET_STATUS2: UART0_RST Mask */ -#define RGU_RESET_STATUS2_UART1_RST_Pos 26 /*!< RGU RESET_STATUS2: UART1_RST Position */ -#define RGU_RESET_STATUS2_UART1_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos) /*!< RGU RESET_STATUS2: UART1_RST Mask */ -#define RGU_RESET_STATUS2_UART2_RST_Pos 28 /*!< RGU RESET_STATUS2: UART2_RST Position */ -#define RGU_RESET_STATUS2_UART2_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos) /*!< RGU RESET_STATUS2: UART2_RST Mask */ -#define RGU_RESET_STATUS2_UART3_RST_Pos 30 /*!< RGU RESET_STATUS2: UART3_RST Position */ -#define RGU_RESET_STATUS2_UART3_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos) /*!< RGU RESET_STATUS2: UART3_RST Mask */ - -// ------------------------------------ RGU_RESET_STATUS3 --------------------------------------- -#define RGU_RESET_STATUS3_I2C0_RST_Pos 0 /*!< RGU RESET_STATUS3: I2C0_RST Position */ -#define RGU_RESET_STATUS3_I2C0_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos) /*!< RGU RESET_STATUS3: I2C0_RST Mask */ -#define RGU_RESET_STATUS3_I2C1_RST_Pos 2 /*!< RGU RESET_STATUS3: I2C1_RST Position */ -#define RGU_RESET_STATUS3_I2C1_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos) /*!< RGU RESET_STATUS3: I2C1_RST Mask */ -#define RGU_RESET_STATUS3_SSP0_RST_Pos 4 /*!< RGU RESET_STATUS3: SSP0_RST Position */ -#define RGU_RESET_STATUS3_SSP0_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos) /*!< RGU RESET_STATUS3: SSP0_RST Mask */ -#define RGU_RESET_STATUS3_SSP1_RST_Pos 6 /*!< RGU RESET_STATUS3: SSP1_RST Position */ -#define RGU_RESET_STATUS3_SSP1_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos) /*!< RGU RESET_STATUS3: SSP1_RST Mask */ -#define RGU_RESET_STATUS3_I2S_RST_Pos 8 /*!< RGU RESET_STATUS3: I2S_RST Position */ -#define RGU_RESET_STATUS3_I2S_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos) /*!< RGU RESET_STATUS3: I2S_RST Mask */ -#define RGU_RESET_STATUS3_SPIFI_RST_Pos 10 /*!< RGU RESET_STATUS3: SPIFI_RST Position */ -#define RGU_RESET_STATUS3_SPIFI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos) /*!< RGU RESET_STATUS3: SPIFI_RST Mask */ -#define RGU_RESET_STATUS3_CAN1_RST_Pos 12 /*!< RGU RESET_STATUS3: CAN1_RST Position */ -#define RGU_RESET_STATUS3_CAN1_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos) /*!< RGU RESET_STATUS3: CAN1_RST Mask */ -#define RGU_RESET_STATUS3_CAN0_RST_Pos 14 /*!< RGU RESET_STATUS3: CAN0_RST Position */ -#define RGU_RESET_STATUS3_CAN0_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos) /*!< RGU RESET_STATUS3: CAN0_RST Mask */ - -// -------------------------------- RGU_RESET_ACTIVE_STATUS0 ------------------------------------ -#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */ - -// -------------------------------- RGU_RESET_ACTIVE_STATUS1 ------------------------------------ -#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos 3 /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos 7 /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos 14 /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos 15 /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos 23 /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT0 -------------------------------------- -#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos 0 /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */ -#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */ -#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos 4 /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */ -#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos) /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */ -#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos 5 /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */ -#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT1 -------------------------------------- -#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */ -#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT2 -------------------------------------- -#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT4 -------------------------------------- -#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */ -#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT5 -------------------------------------- -#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */ -#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT8 -------------------------------------- -#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT9 -------------------------------------- -#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT13 -------------------------------------- -#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT16 -------------------------------------- -#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT17 -------------------------------------- -#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT18 -------------------------------------- -#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT19 -------------------------------------- -#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT20 -------------------------------------- -#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT21 -------------------------------------- -#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT22 -------------------------------------- -#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT23 -------------------------------------- -#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT28 -------------------------------------- -#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT32 -------------------------------------- -#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT33 -------------------------------------- -#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT34 -------------------------------------- -#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT35 -------------------------------------- -#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT36 -------------------------------------- -#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT37 -------------------------------------- -#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT38 -------------------------------------- -#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT39 -------------------------------------- -#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT40 -------------------------------------- -#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT41 -------------------------------------- -#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT42 -------------------------------------- -#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT44 -------------------------------------- -#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT45 -------------------------------------- -#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT46 -------------------------------------- -#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT47 -------------------------------------- -#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT48 -------------------------------------- -#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT49 -------------------------------------- -#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT50 -------------------------------------- -#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT51 -------------------------------------- -#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT52 -------------------------------------- -#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT53 -------------------------------------- -#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT54 -------------------------------------- -#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT55 -------------------------------------- -#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- WWDT Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- WWDT_MOD -------------------------------------------- -#define WWDT_MOD_WDEN_Pos 0 /*!< WWDT MOD: WDEN Position */ -#define WWDT_MOD_WDEN_Msk (0x01UL << WWDT_MOD_WDEN_Pos) /*!< WWDT MOD: WDEN Mask */ -#define WWDT_MOD_WDRESET_Pos 1 /*!< WWDT MOD: WDRESET Position */ -#define WWDT_MOD_WDRESET_Msk (0x01UL << WWDT_MOD_WDRESET_Pos) /*!< WWDT MOD: WDRESET Mask */ -#define WWDT_MOD_WDTOF_Pos 2 /*!< WWDT MOD: WDTOF Position */ -#define WWDT_MOD_WDTOF_Msk (0x01UL << WWDT_MOD_WDTOF_Pos) /*!< WWDT MOD: WDTOF Mask */ -#define WWDT_MOD_WDINT_Pos 3 /*!< WWDT MOD: WDINT Position */ -#define WWDT_MOD_WDINT_Msk (0x01UL << WWDT_MOD_WDINT_Pos) /*!< WWDT MOD: WDINT Mask */ -#define WWDT_MOD_WDPROTECT_Pos 4 /*!< WWDT MOD: WDPROTECT Position */ -#define WWDT_MOD_WDPROTECT_Msk (0x01UL << WWDT_MOD_WDPROTECT_Pos) /*!< WWDT MOD: WDPROTECT Mask */ - -// ----------------------------------------- WWDT_TC -------------------------------------------- -#define WWDT_TC_WDTC_Pos 0 /*!< WWDT TC: WDTC Position */ -#define WWDT_TC_WDTC_Msk (0x00ffffffUL << WWDT_TC_WDTC_Pos) /*!< WWDT TC: WDTC Mask */ - -// ---------------------------------------- WWDT_FEED ------------------------------------------- -#define WWDT_FEED_Feed_Pos 0 /*!< WWDT FEED: Feed Position */ -#define WWDT_FEED_Feed_Msk (0x000000ffUL << WWDT_FEED_Feed_Pos) /*!< WWDT FEED: Feed Mask */ - -// ----------------------------------------- WWDT_TV -------------------------------------------- -#define WWDT_TV_Count_Pos 0 /*!< WWDT TV: Count Position */ -#define WWDT_TV_Count_Msk (0x00ffffffUL << WWDT_TV_Count_Pos) /*!< WWDT TV: Count Mask */ - -// -------------------------------------- WWDT_WARNINT ------------------------------------------ -#define WWDT_WARNINT_WDWARNINT_Pos 0 /*!< WWDT WARNINT: WDWARNINT Position */ -#define WWDT_WARNINT_WDWARNINT_Msk (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos) /*!< WWDT WARNINT: WDWARNINT Mask */ - -// --------------------------------------- WWDT_WINDOW ------------------------------------------ -#define WWDT_WINDOW_WDWINDOW_Pos 0 /*!< WWDT WINDOW: WDWINDOW Position */ -#define WWDT_WINDOW_WDWINDOW_Msk (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos) /*!< WWDT WINDOW: WDWINDOW Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USART0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- USART0_RBR ------------------------------------------- -#define USART0_RBR_RBR_Pos 0 /*!< USART0 RBR: RBR Position */ -#define USART0_RBR_RBR_Msk (0x000000ffUL << USART0_RBR_RBR_Pos) /*!< USART0 RBR: RBR Mask */ - -// --------------------------------------- USART0_THR ------------------------------------------- -#define USART0_THR_THR_Pos 0 /*!< USART0 THR: THR Position */ -#define USART0_THR_THR_Msk (0x000000ffUL << USART0_THR_THR_Pos) /*!< USART0 THR: THR Mask */ - -// --------------------------------------- USART0_DLL ------------------------------------------- -#define USART0_DLL_DLLSB_Pos 0 /*!< USART0 DLL: DLLSB Position */ -#define USART0_DLL_DLLSB_Msk (0x000000ffUL << USART0_DLL_DLLSB_Pos) /*!< USART0 DLL: DLLSB Mask */ - -// --------------------------------------- USART0_DLM ------------------------------------------- -#define USART0_DLM_DLMSB_Pos 0 /*!< USART0 DLM: DLMSB Position */ -#define USART0_DLM_DLMSB_Msk (0x000000ffUL << USART0_DLM_DLMSB_Pos) /*!< USART0 DLM: DLMSB Mask */ - -// --------------------------------------- USART0_IER ------------------------------------------- -#define USART0_IER_RBRIE_Pos 0 /*!< USART0 IER: RBRIE Position */ -#define USART0_IER_RBRIE_Msk (0x01UL << USART0_IER_RBRIE_Pos) /*!< USART0 IER: RBRIE Mask */ -#define USART0_IER_THREIE_Pos 1 /*!< USART0 IER: THREIE Position */ -#define USART0_IER_THREIE_Msk (0x01UL << USART0_IER_THREIE_Pos) /*!< USART0 IER: THREIE Mask */ -#define USART0_IER_RXIE_Pos 2 /*!< USART0 IER: RXIE Position */ -#define USART0_IER_RXIE_Msk (0x01UL << USART0_IER_RXIE_Pos) /*!< USART0 IER: RXIE Mask */ -#define USART0_IER_ABEOINTEN_Pos 8 /*!< USART0 IER: ABEOINTEN Position */ -#define USART0_IER_ABEOINTEN_Msk (0x01UL << USART0_IER_ABEOINTEN_Pos) /*!< USART0 IER: ABEOINTEN Mask */ -#define USART0_IER_ABTOINTEN_Pos 9 /*!< USART0 IER: ABTOINTEN Position */ -#define USART0_IER_ABTOINTEN_Msk (0x01UL << USART0_IER_ABTOINTEN_Pos) /*!< USART0 IER: ABTOINTEN Mask */ - -// --------------------------------------- USART0_IIR ------------------------------------------- -#define USART0_IIR_INTSTATUS_Pos 0 /*!< USART0 IIR: INTSTATUS Position */ -#define USART0_IIR_INTSTATUS_Msk (0x01UL << USART0_IIR_INTSTATUS_Pos) /*!< USART0 IIR: INTSTATUS Mask */ -#define USART0_IIR_INTID_Pos 1 /*!< USART0 IIR: INTID Position */ -#define USART0_IIR_INTID_Msk (0x07UL << USART0_IIR_INTID_Pos) /*!< USART0 IIR: INTID Mask */ -#define USART0_IIR_FIFOENABLE_Pos 6 /*!< USART0 IIR: FIFOENABLE Position */ -#define USART0_IIR_FIFOENABLE_Msk (0x03UL << USART0_IIR_FIFOENABLE_Pos) /*!< USART0 IIR: FIFOENABLE Mask */ -#define USART0_IIR_ABEOINT_Pos 8 /*!< USART0 IIR: ABEOINT Position */ -#define USART0_IIR_ABEOINT_Msk (0x01UL << USART0_IIR_ABEOINT_Pos) /*!< USART0 IIR: ABEOINT Mask */ -#define USART0_IIR_ABTOINT_Pos 9 /*!< USART0 IIR: ABTOINT Position */ -#define USART0_IIR_ABTOINT_Msk (0x01UL << USART0_IIR_ABTOINT_Pos) /*!< USART0 IIR: ABTOINT Mask */ - -// --------------------------------------- USART0_FCR ------------------------------------------- -#define USART0_FCR_FIFOEN_Pos 0 /*!< USART0 FCR: FIFOEN Position */ -#define USART0_FCR_FIFOEN_Msk (0x01UL << USART0_FCR_FIFOEN_Pos) /*!< USART0 FCR: FIFOEN Mask */ -#define USART0_FCR_RXFIFORES_Pos 1 /*!< USART0 FCR: RXFIFORES Position */ -#define USART0_FCR_RXFIFORES_Msk (0x01UL << USART0_FCR_RXFIFORES_Pos) /*!< USART0 FCR: RXFIFORES Mask */ -#define USART0_FCR_TXFIFORES_Pos 2 /*!< USART0 FCR: TXFIFORES Position */ -#define USART0_FCR_TXFIFORES_Msk (0x01UL << USART0_FCR_TXFIFORES_Pos) /*!< USART0 FCR: TXFIFORES Mask */ -#define USART0_FCR_DMAMODE_Pos 3 /*!< USART0 FCR: DMAMODE Position */ -#define USART0_FCR_DMAMODE_Msk (0x01UL << USART0_FCR_DMAMODE_Pos) /*!< USART0 FCR: DMAMODE Mask */ -#define USART0_FCR_RXTRIGLVL_Pos 6 /*!< USART0 FCR: RXTRIGLVL Position */ -#define USART0_FCR_RXTRIGLVL_Msk (0x03UL << USART0_FCR_RXTRIGLVL_Pos) /*!< USART0 FCR: RXTRIGLVL Mask */ - -// --------------------------------------- USART0_LCR ------------------------------------------- -#define USART0_LCR_WLS_Pos 0 /*!< USART0 LCR: WLS Position */ -#define USART0_LCR_WLS_Msk (0x03UL << USART0_LCR_WLS_Pos) /*!< USART0 LCR: WLS Mask */ -#define USART0_LCR_SBS_Pos 2 /*!< USART0 LCR: SBS Position */ -#define USART0_LCR_SBS_Msk (0x01UL << USART0_LCR_SBS_Pos) /*!< USART0 LCR: SBS Mask */ -#define USART0_LCR_PE_Pos 3 /*!< USART0 LCR: PE Position */ -#define USART0_LCR_PE_Msk (0x01UL << USART0_LCR_PE_Pos) /*!< USART0 LCR: PE Mask */ -#define USART0_LCR_PS_Pos 4 /*!< USART0 LCR: PS Position */ -#define USART0_LCR_PS_Msk (0x03UL << USART0_LCR_PS_Pos) /*!< USART0 LCR: PS Mask */ -#define USART0_LCR_BC_Pos 6 /*!< USART0 LCR: BC Position */ -#define USART0_LCR_BC_Msk (0x01UL << USART0_LCR_BC_Pos) /*!< USART0 LCR: BC Mask */ -#define USART0_LCR_DLAB_Pos 7 /*!< USART0 LCR: DLAB Position */ -#define USART0_LCR_DLAB_Msk (0x01UL << USART0_LCR_DLAB_Pos) /*!< USART0 LCR: DLAB Mask */ - -// --------------------------------------- USART0_LSR ------------------------------------------- -#define USART0_LSR_RDR_Pos 0 /*!< USART0 LSR: RDR Position */ -#define USART0_LSR_RDR_Msk (0x01UL << USART0_LSR_RDR_Pos) /*!< USART0 LSR: RDR Mask */ -#define USART0_LSR_OE_Pos 1 /*!< USART0 LSR: OE Position */ -#define USART0_LSR_OE_Msk (0x01UL << USART0_LSR_OE_Pos) /*!< USART0 LSR: OE Mask */ -#define USART0_LSR_PE_Pos 2 /*!< USART0 LSR: PE Position */ -#define USART0_LSR_PE_Msk (0x01UL << USART0_LSR_PE_Pos) /*!< USART0 LSR: PE Mask */ -#define USART0_LSR_FE_Pos 3 /*!< USART0 LSR: FE Position */ -#define USART0_LSR_FE_Msk (0x01UL << USART0_LSR_FE_Pos) /*!< USART0 LSR: FE Mask */ -#define USART0_LSR_BI_Pos 4 /*!< USART0 LSR: BI Position */ -#define USART0_LSR_BI_Msk (0x01UL << USART0_LSR_BI_Pos) /*!< USART0 LSR: BI Mask */ -#define USART0_LSR_THRE_Pos 5 /*!< USART0 LSR: THRE Position */ -#define USART0_LSR_THRE_Msk (0x01UL << USART0_LSR_THRE_Pos) /*!< USART0 LSR: THRE Mask */ -#define USART0_LSR_TEMT_Pos 6 /*!< USART0 LSR: TEMT Position */ -#define USART0_LSR_TEMT_Msk (0x01UL << USART0_LSR_TEMT_Pos) /*!< USART0 LSR: TEMT Mask */ -#define USART0_LSR_RXFE_Pos 7 /*!< USART0 LSR: RXFE Position */ -#define USART0_LSR_RXFE_Msk (0x01UL << USART0_LSR_RXFE_Pos) /*!< USART0 LSR: RXFE Mask */ -#define USART0_LSR_TXERR_Pos 8 /*!< USART0 LSR: TXERR Position */ -#define USART0_LSR_TXERR_Msk (0x01UL << USART0_LSR_TXERR_Pos) /*!< USART0 LSR: TXERR Mask */ - -// --------------------------------------- USART0_SCR ------------------------------------------- -#define USART0_SCR_PAD_Pos 0 /*!< USART0 SCR: PAD Position */ -#define USART0_SCR_PAD_Msk (0x000000ffUL << USART0_SCR_PAD_Pos) /*!< USART0 SCR: PAD Mask */ - -// --------------------------------------- USART0_ACR ------------------------------------------- -#define USART0_ACR_START_Pos 0 /*!< USART0 ACR: START Position */ -#define USART0_ACR_START_Msk (0x01UL << USART0_ACR_START_Pos) /*!< USART0 ACR: START Mask */ -#define USART0_ACR_MODE_Pos 1 /*!< USART0 ACR: MODE Position */ -#define USART0_ACR_MODE_Msk (0x01UL << USART0_ACR_MODE_Pos) /*!< USART0 ACR: MODE Mask */ -#define USART0_ACR_AUTORESTART_Pos 2 /*!< USART0 ACR: AUTORESTART Position */ -#define USART0_ACR_AUTORESTART_Msk (0x01UL << USART0_ACR_AUTORESTART_Pos) /*!< USART0 ACR: AUTORESTART Mask */ -#define USART0_ACR_ABEOINTCLR_Pos 8 /*!< USART0 ACR: ABEOINTCLR Position */ -#define USART0_ACR_ABEOINTCLR_Msk (0x01UL << USART0_ACR_ABEOINTCLR_Pos) /*!< USART0 ACR: ABEOINTCLR Mask */ -#define USART0_ACR_ABTOINTCLR_Pos 9 /*!< USART0 ACR: ABTOINTCLR Position */ -#define USART0_ACR_ABTOINTCLR_Msk (0x01UL << USART0_ACR_ABTOINTCLR_Pos) /*!< USART0 ACR: ABTOINTCLR Mask */ - -// --------------------------------------- USART0_ICR ------------------------------------------- -#define USART0_ICR_IRDAEN_Pos 0 /*!< USART0 ICR: IRDAEN Position */ -#define USART0_ICR_IRDAEN_Msk (0x01UL << USART0_ICR_IRDAEN_Pos) /*!< USART0 ICR: IRDAEN Mask */ -#define USART0_ICR_IRDAINV_Pos 1 /*!< USART0 ICR: IRDAINV Position */ -#define USART0_ICR_IRDAINV_Msk (0x01UL << USART0_ICR_IRDAINV_Pos) /*!< USART0 ICR: IRDAINV Mask */ -#define USART0_ICR_FIXPULSEEN_Pos 2 /*!< USART0 ICR: FIXPULSEEN Position */ -#define USART0_ICR_FIXPULSEEN_Msk (0x01UL << USART0_ICR_FIXPULSEEN_Pos) /*!< USART0 ICR: FIXPULSEEN Mask */ -#define USART0_ICR_PULSEDIV_Pos 3 /*!< USART0 ICR: PULSEDIV Position */ -#define USART0_ICR_PULSEDIV_Msk (0x07UL << USART0_ICR_PULSEDIV_Pos) /*!< USART0 ICR: PULSEDIV Mask */ - -// --------------------------------------- USART0_FDR ------------------------------------------- -#define USART0_FDR_DIVADDVAL_Pos 0 /*!< USART0 FDR: DIVADDVAL Position */ -#define USART0_FDR_DIVADDVAL_Msk (0x0fUL << USART0_FDR_DIVADDVAL_Pos) /*!< USART0 FDR: DIVADDVAL Mask */ -#define USART0_FDR_MULVAL_Pos 4 /*!< USART0 FDR: MULVAL Position */ -#define USART0_FDR_MULVAL_Msk (0x0fUL << USART0_FDR_MULVAL_Pos) /*!< USART0 FDR: MULVAL Mask */ - -// --------------------------------------- USART0_OSR ------------------------------------------- -#define USART0_OSR_OSFRAC_Pos 1 /*!< USART0 OSR: OSFRAC Position */ -#define USART0_OSR_OSFRAC_Msk (0x07UL << USART0_OSR_OSFRAC_Pos) /*!< USART0 OSR: OSFRAC Mask */ -#define USART0_OSR_OSINT_Pos 4 /*!< USART0 OSR: OSINT Position */ -#define USART0_OSR_OSINT_Msk (0x0fUL << USART0_OSR_OSINT_Pos) /*!< USART0 OSR: OSINT Mask */ -#define USART0_OSR_FDINT_Pos 8 /*!< USART0 OSR: FDINT Position */ -#define USART0_OSR_FDINT_Msk (0x7fUL << USART0_OSR_FDINT_Pos) /*!< USART0 OSR: FDINT Mask */ - -// --------------------------------------- USART0_HDEN ------------------------------------------ -#define USART0_HDEN_HDEN_Pos 0 /*!< USART0 HDEN: HDEN Position */ -#define USART0_HDEN_HDEN_Msk (0x01UL << USART0_HDEN_HDEN_Pos) /*!< USART0 HDEN: HDEN Mask */ - -// ------------------------------------- USART0_SCICTRL ----------------------------------------- -#define USART0_SCICTRL_SCIEN_Pos 0 /*!< USART0 SCICTRL: SCIEN Position */ -#define USART0_SCICTRL_SCIEN_Msk (0x01UL << USART0_SCICTRL_SCIEN_Pos) /*!< USART0 SCICTRL: SCIEN Mask */ -#define USART0_SCICTRL_NACKDIS_Pos 1 /*!< USART0 SCICTRL: NACKDIS Position */ -#define USART0_SCICTRL_NACKDIS_Msk (0x01UL << USART0_SCICTRL_NACKDIS_Pos) /*!< USART0 SCICTRL: NACKDIS Mask */ -#define USART0_SCICTRL_PROTSEL_Pos 2 /*!< USART0 SCICTRL: PROTSEL Position */ -#define USART0_SCICTRL_PROTSEL_Msk (0x01UL << USART0_SCICTRL_PROTSEL_Pos) /*!< USART0 SCICTRL: PROTSEL Mask */ -#define USART0_SCICTRL_TXRETRY_Pos 5 /*!< USART0 SCICTRL: TXRETRY Position */ -#define USART0_SCICTRL_TXRETRY_Msk (0x07UL << USART0_SCICTRL_TXRETRY_Pos) /*!< USART0 SCICTRL: TXRETRY Mask */ -#define USART0_SCICTRL_GUARDTIME_Pos 8 /*!< USART0 SCICTRL: GUARDTIME Position */ -#define USART0_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos) /*!< USART0 SCICTRL: GUARDTIME Mask */ - -// ------------------------------------ USART0_RS485CTRL ---------------------------------------- -#define USART0_RS485CTRL_NMMEN_Pos 0 /*!< USART0 RS485CTRL: NMMEN Position */ -#define USART0_RS485CTRL_NMMEN_Msk (0x01UL << USART0_RS485CTRL_NMMEN_Pos) /*!< USART0 RS485CTRL: NMMEN Mask */ -#define USART0_RS485CTRL_RXDIS_Pos 1 /*!< USART0 RS485CTRL: RXDIS Position */ -#define USART0_RS485CTRL_RXDIS_Msk (0x01UL << USART0_RS485CTRL_RXDIS_Pos) /*!< USART0 RS485CTRL: RXDIS Mask */ -#define USART0_RS485CTRL_AADEN_Pos 2 /*!< USART0 RS485CTRL: AADEN Position */ -#define USART0_RS485CTRL_AADEN_Msk (0x01UL << USART0_RS485CTRL_AADEN_Pos) /*!< USART0 RS485CTRL: AADEN Mask */ -#define USART0_RS485CTRL_DCTRL_Pos 4 /*!< USART0 RS485CTRL: DCTRL Position */ -#define USART0_RS485CTRL_DCTRL_Msk (0x01UL << USART0_RS485CTRL_DCTRL_Pos) /*!< USART0 RS485CTRL: DCTRL Mask */ -#define USART0_RS485CTRL_OINV_Pos 5 /*!< USART0 RS485CTRL: OINV Position */ -#define USART0_RS485CTRL_OINV_Msk (0x01UL << USART0_RS485CTRL_OINV_Pos) /*!< USART0 RS485CTRL: OINV Mask */ - -// ---------------------------------- USART0_RS485ADRMATCH -------------------------------------- -#define USART0_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART0 RS485ADRMATCH: ADRMATCH Position */ -#define USART0_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */ - -// ------------------------------------- USART0_RS485DLY ---------------------------------------- -#define USART0_RS485DLY_DLY_Pos 0 /*!< USART0 RS485DLY: DLY Position */ -#define USART0_RS485DLY_DLY_Msk (0x000000ffUL << USART0_RS485DLY_DLY_Pos) /*!< USART0 RS485DLY: DLY Mask */ - -// ------------------------------------- USART0_SYNCCTRL ---------------------------------------- -#define USART0_SYNCCTRL_SYNC_Pos 0 /*!< USART0 SYNCCTRL: SYNC Position */ -#define USART0_SYNCCTRL_SYNC_Msk (0x01UL << USART0_SYNCCTRL_SYNC_Pos) /*!< USART0 SYNCCTRL: SYNC Mask */ -#define USART0_SYNCCTRL_CSRC_Pos 1 /*!< USART0 SYNCCTRL: CSRC Position */ -#define USART0_SYNCCTRL_CSRC_Msk (0x01UL << USART0_SYNCCTRL_CSRC_Pos) /*!< USART0 SYNCCTRL: CSRC Mask */ -#define USART0_SYNCCTRL_FES_Pos 2 /*!< USART0 SYNCCTRL: FES Position */ -#define USART0_SYNCCTRL_FES_Msk (0x01UL << USART0_SYNCCTRL_FES_Pos) /*!< USART0 SYNCCTRL: FES Mask */ -#define USART0_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART0 SYNCCTRL: TSBYPASS Position */ -#define USART0_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos) /*!< USART0 SYNCCTRL: TSBYPASS Mask */ -#define USART0_SYNCCTRL_CSCEN_Pos 4 /*!< USART0 SYNCCTRL: CSCEN Position */ -#define USART0_SYNCCTRL_CSCEN_Msk (0x01UL << USART0_SYNCCTRL_CSCEN_Pos) /*!< USART0 SYNCCTRL: CSCEN Mask */ -#define USART0_SYNCCTRL_SSSDIS_Pos 5 /*!< USART0 SYNCCTRL: SSSDIS Position */ -#define USART0_SYNCCTRL_SSSDIS_Msk (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos) /*!< USART0 SYNCCTRL: SSSDIS Mask */ -#define USART0_SYNCCTRL_CCCLR_Pos 6 /*!< USART0 SYNCCTRL: CCCLR Position */ -#define USART0_SYNCCTRL_CCCLR_Msk (0x01UL << USART0_SYNCCTRL_CCCLR_Pos) /*!< USART0 SYNCCTRL: CCCLR Mask */ - -// --------------------------------------- USART0_TER ------------------------------------------- -#define USART0_TER_TXEN_Pos 0 /*!< USART0 TER: TXEN Position */ -#define USART0_TER_TXEN_Msk (0x01UL << USART0_TER_TXEN_Pos) /*!< USART0 TER: TXEN Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USART2 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- USART2_DLL ------------------------------------------- -#define USART2_DLL_DLLSB_Pos 0 /*!< USART2 DLL: DLLSB Position */ -#define USART2_DLL_DLLSB_Msk (0x000000ffUL << USART2_DLL_DLLSB_Pos) /*!< USART2 DLL: DLLSB Mask */ - -// --------------------------------------- USART2_THR ------------------------------------------- -#define USART2_THR_THR_Pos 0 /*!< USART2 THR: THR Position */ -#define USART2_THR_THR_Msk (0x000000ffUL << USART2_THR_THR_Pos) /*!< USART2 THR: THR Mask */ - -// --------------------------------------- USART2_RBR ------------------------------------------- -#define USART2_RBR_RBR_Pos 0 /*!< USART2 RBR: RBR Position */ -#define USART2_RBR_RBR_Msk (0x000000ffUL << USART2_RBR_RBR_Pos) /*!< USART2 RBR: RBR Mask */ - -// --------------------------------------- USART2_IER ------------------------------------------- -#define USART2_IER_RBRIE_Pos 0 /*!< USART2 IER: RBRIE Position */ -#define USART2_IER_RBRIE_Msk (0x01UL << USART2_IER_RBRIE_Pos) /*!< USART2 IER: RBRIE Mask */ -#define USART2_IER_THREIE_Pos 1 /*!< USART2 IER: THREIE Position */ -#define USART2_IER_THREIE_Msk (0x01UL << USART2_IER_THREIE_Pos) /*!< USART2 IER: THREIE Mask */ -#define USART2_IER_RXIE_Pos 2 /*!< USART2 IER: RXIE Position */ -#define USART2_IER_RXIE_Msk (0x01UL << USART2_IER_RXIE_Pos) /*!< USART2 IER: RXIE Mask */ -#define USART2_IER_ABEOINTEN_Pos 8 /*!< USART2 IER: ABEOINTEN Position */ -#define USART2_IER_ABEOINTEN_Msk (0x01UL << USART2_IER_ABEOINTEN_Pos) /*!< USART2 IER: ABEOINTEN Mask */ -#define USART2_IER_ABTOINTEN_Pos 9 /*!< USART2 IER: ABTOINTEN Position */ -#define USART2_IER_ABTOINTEN_Msk (0x01UL << USART2_IER_ABTOINTEN_Pos) /*!< USART2 IER: ABTOINTEN Mask */ - -// --------------------------------------- USART2_DLM ------------------------------------------- -#define USART2_DLM_DLMSB_Pos 0 /*!< USART2 DLM: DLMSB Position */ -#define USART2_DLM_DLMSB_Msk (0x000000ffUL << USART2_DLM_DLMSB_Pos) /*!< USART2 DLM: DLMSB Mask */ - -// --------------------------------------- USART2_FCR ------------------------------------------- -#define USART2_FCR_FIFOEN_Pos 0 /*!< USART2 FCR: FIFOEN Position */ -#define USART2_FCR_FIFOEN_Msk (0x01UL << USART2_FCR_FIFOEN_Pos) /*!< USART2 FCR: FIFOEN Mask */ -#define USART2_FCR_RXFIFORES_Pos 1 /*!< USART2 FCR: RXFIFORES Position */ -#define USART2_FCR_RXFIFORES_Msk (0x01UL << USART2_FCR_RXFIFORES_Pos) /*!< USART2 FCR: RXFIFORES Mask */ -#define USART2_FCR_TXFIFORES_Pos 2 /*!< USART2 FCR: TXFIFORES Position */ -#define USART2_FCR_TXFIFORES_Msk (0x01UL << USART2_FCR_TXFIFORES_Pos) /*!< USART2 FCR: TXFIFORES Mask */ -#define USART2_FCR_DMAMODE_Pos 3 /*!< USART2 FCR: DMAMODE Position */ -#define USART2_FCR_DMAMODE_Msk (0x01UL << USART2_FCR_DMAMODE_Pos) /*!< USART2 FCR: DMAMODE Mask */ -#define USART2_FCR_RXTRIGLVL_Pos 6 /*!< USART2 FCR: RXTRIGLVL Position */ -#define USART2_FCR_RXTRIGLVL_Msk (0x03UL << USART2_FCR_RXTRIGLVL_Pos) /*!< USART2 FCR: RXTRIGLVL Mask */ - -// --------------------------------------- USART2_IIR ------------------------------------------- -#define USART2_IIR_INTSTATUS_Pos 0 /*!< USART2 IIR: INTSTATUS Position */ -#define USART2_IIR_INTSTATUS_Msk (0x01UL << USART2_IIR_INTSTATUS_Pos) /*!< USART2 IIR: INTSTATUS Mask */ -#define USART2_IIR_INTID_Pos 1 /*!< USART2 IIR: INTID Position */ -#define USART2_IIR_INTID_Msk (0x07UL << USART2_IIR_INTID_Pos) /*!< USART2 IIR: INTID Mask */ -#define USART2_IIR_FIFOENABLE_Pos 6 /*!< USART2 IIR: FIFOENABLE Position */ -#define USART2_IIR_FIFOENABLE_Msk (0x03UL << USART2_IIR_FIFOENABLE_Pos) /*!< USART2 IIR: FIFOENABLE Mask */ -#define USART2_IIR_ABEOINT_Pos 8 /*!< USART2 IIR: ABEOINT Position */ -#define USART2_IIR_ABEOINT_Msk (0x01UL << USART2_IIR_ABEOINT_Pos) /*!< USART2 IIR: ABEOINT Mask */ -#define USART2_IIR_ABTOINT_Pos 9 /*!< USART2 IIR: ABTOINT Position */ -#define USART2_IIR_ABTOINT_Msk (0x01UL << USART2_IIR_ABTOINT_Pos) /*!< USART2 IIR: ABTOINT Mask */ - -// --------------------------------------- USART2_LCR ------------------------------------------- -#define USART2_LCR_WLS_Pos 0 /*!< USART2 LCR: WLS Position */ -#define USART2_LCR_WLS_Msk (0x03UL << USART2_LCR_WLS_Pos) /*!< USART2 LCR: WLS Mask */ -#define USART2_LCR_SBS_Pos 2 /*!< USART2 LCR: SBS Position */ -#define USART2_LCR_SBS_Msk (0x01UL << USART2_LCR_SBS_Pos) /*!< USART2 LCR: SBS Mask */ -#define USART2_LCR_PE_Pos 3 /*!< USART2 LCR: PE Position */ -#define USART2_LCR_PE_Msk (0x01UL << USART2_LCR_PE_Pos) /*!< USART2 LCR: PE Mask */ -#define USART2_LCR_PS_Pos 4 /*!< USART2 LCR: PS Position */ -#define USART2_LCR_PS_Msk (0x03UL << USART2_LCR_PS_Pos) /*!< USART2 LCR: PS Mask */ -#define USART2_LCR_BC_Pos 6 /*!< USART2 LCR: BC Position */ -#define USART2_LCR_BC_Msk (0x01UL << USART2_LCR_BC_Pos) /*!< USART2 LCR: BC Mask */ -#define USART2_LCR_DLAB_Pos 7 /*!< USART2 LCR: DLAB Position */ -#define USART2_LCR_DLAB_Msk (0x01UL << USART2_LCR_DLAB_Pos) /*!< USART2 LCR: DLAB Mask */ - -// --------------------------------------- USART2_LSR ------------------------------------------- -#define USART2_LSR_RDR_Pos 0 /*!< USART2 LSR: RDR Position */ -#define USART2_LSR_RDR_Msk (0x01UL << USART2_LSR_RDR_Pos) /*!< USART2 LSR: RDR Mask */ -#define USART2_LSR_OE_Pos 1 /*!< USART2 LSR: OE Position */ -#define USART2_LSR_OE_Msk (0x01UL << USART2_LSR_OE_Pos) /*!< USART2 LSR: OE Mask */ -#define USART2_LSR_PE_Pos 2 /*!< USART2 LSR: PE Position */ -#define USART2_LSR_PE_Msk (0x01UL << USART2_LSR_PE_Pos) /*!< USART2 LSR: PE Mask */ -#define USART2_LSR_FE_Pos 3 /*!< USART2 LSR: FE Position */ -#define USART2_LSR_FE_Msk (0x01UL << USART2_LSR_FE_Pos) /*!< USART2 LSR: FE Mask */ -#define USART2_LSR_BI_Pos 4 /*!< USART2 LSR: BI Position */ -#define USART2_LSR_BI_Msk (0x01UL << USART2_LSR_BI_Pos) /*!< USART2 LSR: BI Mask */ -#define USART2_LSR_THRE_Pos 5 /*!< USART2 LSR: THRE Position */ -#define USART2_LSR_THRE_Msk (0x01UL << USART2_LSR_THRE_Pos) /*!< USART2 LSR: THRE Mask */ -#define USART2_LSR_TEMT_Pos 6 /*!< USART2 LSR: TEMT Position */ -#define USART2_LSR_TEMT_Msk (0x01UL << USART2_LSR_TEMT_Pos) /*!< USART2 LSR: TEMT Mask */ -#define USART2_LSR_RXFE_Pos 7 /*!< USART2 LSR: RXFE Position */ -#define USART2_LSR_RXFE_Msk (0x01UL << USART2_LSR_RXFE_Pos) /*!< USART2 LSR: RXFE Mask */ -#define USART2_LSR_TXERR_Pos 8 /*!< USART2 LSR: TXERR Position */ -#define USART2_LSR_TXERR_Msk (0x01UL << USART2_LSR_TXERR_Pos) /*!< USART2 LSR: TXERR Mask */ - -// --------------------------------------- USART2_SCR ------------------------------------------- -#define USART2_SCR_PAD_Pos 0 /*!< USART2 SCR: PAD Position */ -#define USART2_SCR_PAD_Msk (0x000000ffUL << USART2_SCR_PAD_Pos) /*!< USART2 SCR: PAD Mask */ - -// --------------------------------------- USART2_ACR ------------------------------------------- -#define USART2_ACR_START_Pos 0 /*!< USART2 ACR: START Position */ -#define USART2_ACR_START_Msk (0x01UL << USART2_ACR_START_Pos) /*!< USART2 ACR: START Mask */ -#define USART2_ACR_MODE_Pos 1 /*!< USART2 ACR: MODE Position */ -#define USART2_ACR_MODE_Msk (0x01UL << USART2_ACR_MODE_Pos) /*!< USART2 ACR: MODE Mask */ -#define USART2_ACR_AUTORESTART_Pos 2 /*!< USART2 ACR: AUTORESTART Position */ -#define USART2_ACR_AUTORESTART_Msk (0x01UL << USART2_ACR_AUTORESTART_Pos) /*!< USART2 ACR: AUTORESTART Mask */ -#define USART2_ACR_ABEOINTCLR_Pos 8 /*!< USART2 ACR: ABEOINTCLR Position */ -#define USART2_ACR_ABEOINTCLR_Msk (0x01UL << USART2_ACR_ABEOINTCLR_Pos) /*!< USART2 ACR: ABEOINTCLR Mask */ -#define USART2_ACR_ABTOINTCLR_Pos 9 /*!< USART2 ACR: ABTOINTCLR Position */ -#define USART2_ACR_ABTOINTCLR_Msk (0x01UL << USART2_ACR_ABTOINTCLR_Pos) /*!< USART2 ACR: ABTOINTCLR Mask */ - -// --------------------------------------- USART2_ICR ------------------------------------------- -#define USART2_ICR_IRDAEN_Pos 0 /*!< USART2 ICR: IRDAEN Position */ -#define USART2_ICR_IRDAEN_Msk (0x01UL << USART2_ICR_IRDAEN_Pos) /*!< USART2 ICR: IRDAEN Mask */ -#define USART2_ICR_IRDAINV_Pos 1 /*!< USART2 ICR: IRDAINV Position */ -#define USART2_ICR_IRDAINV_Msk (0x01UL << USART2_ICR_IRDAINV_Pos) /*!< USART2 ICR: IRDAINV Mask */ -#define USART2_ICR_FIXPULSEEN_Pos 2 /*!< USART2 ICR: FIXPULSEEN Position */ -#define USART2_ICR_FIXPULSEEN_Msk (0x01UL << USART2_ICR_FIXPULSEEN_Pos) /*!< USART2 ICR: FIXPULSEEN Mask */ -#define USART2_ICR_PULSEDIV_Pos 3 /*!< USART2 ICR: PULSEDIV Position */ -#define USART2_ICR_PULSEDIV_Msk (0x07UL << USART2_ICR_PULSEDIV_Pos) /*!< USART2 ICR: PULSEDIV Mask */ - -// --------------------------------------- USART2_FDR ------------------------------------------- -#define USART2_FDR_DIVADDVAL_Pos 0 /*!< USART2 FDR: DIVADDVAL Position */ -#define USART2_FDR_DIVADDVAL_Msk (0x0fUL << USART2_FDR_DIVADDVAL_Pos) /*!< USART2 FDR: DIVADDVAL Mask */ -#define USART2_FDR_MULVAL_Pos 4 /*!< USART2 FDR: MULVAL Position */ -#define USART2_FDR_MULVAL_Msk (0x0fUL << USART2_FDR_MULVAL_Pos) /*!< USART2 FDR: MULVAL Mask */ - -// --------------------------------------- USART2_OSR ------------------------------------------- -#define USART2_OSR_OSFRAC_Pos 1 /*!< USART2 OSR: OSFRAC Position */ -#define USART2_OSR_OSFRAC_Msk (0x07UL << USART2_OSR_OSFRAC_Pos) /*!< USART2 OSR: OSFRAC Mask */ -#define USART2_OSR_OSINT_Pos 4 /*!< USART2 OSR: OSINT Position */ -#define USART2_OSR_OSINT_Msk (0x0fUL << USART2_OSR_OSINT_Pos) /*!< USART2 OSR: OSINT Mask */ -#define USART2_OSR_FDINT_Pos 8 /*!< USART2 OSR: FDINT Position */ -#define USART2_OSR_FDINT_Msk (0x7fUL << USART2_OSR_FDINT_Pos) /*!< USART2 OSR: FDINT Mask */ - -// --------------------------------------- USART2_HDEN ------------------------------------------ -#define USART2_HDEN_HDEN_Pos 0 /*!< USART2 HDEN: HDEN Position */ -#define USART2_HDEN_HDEN_Msk (0x01UL << USART2_HDEN_HDEN_Pos) /*!< USART2 HDEN: HDEN Mask */ - -// ------------------------------------- USART2_SCICTRL ----------------------------------------- -#define USART2_SCICTRL_SCIEN_Pos 0 /*!< USART2 SCICTRL: SCIEN Position */ -#define USART2_SCICTRL_SCIEN_Msk (0x01UL << USART2_SCICTRL_SCIEN_Pos) /*!< USART2 SCICTRL: SCIEN Mask */ -#define USART2_SCICTRL_NACKDIS_Pos 1 /*!< USART2 SCICTRL: NACKDIS Position */ -#define USART2_SCICTRL_NACKDIS_Msk (0x01UL << USART2_SCICTRL_NACKDIS_Pos) /*!< USART2 SCICTRL: NACKDIS Mask */ -#define USART2_SCICTRL_PROTSEL_Pos 2 /*!< USART2 SCICTRL: PROTSEL Position */ -#define USART2_SCICTRL_PROTSEL_Msk (0x01UL << USART2_SCICTRL_PROTSEL_Pos) /*!< USART2 SCICTRL: PROTSEL Mask */ -#define USART2_SCICTRL_TXRETRY_Pos 5 /*!< USART2 SCICTRL: TXRETRY Position */ -#define USART2_SCICTRL_TXRETRY_Msk (0x07UL << USART2_SCICTRL_TXRETRY_Pos) /*!< USART2 SCICTRL: TXRETRY Mask */ -#define USART2_SCICTRL_GUARDTIME_Pos 8 /*!< USART2 SCICTRL: GUARDTIME Position */ -#define USART2_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos) /*!< USART2 SCICTRL: GUARDTIME Mask */ - -// ------------------------------------ USART2_RS485CTRL ---------------------------------------- -#define USART2_RS485CTRL_NMMEN_Pos 0 /*!< USART2 RS485CTRL: NMMEN Position */ -#define USART2_RS485CTRL_NMMEN_Msk (0x01UL << USART2_RS485CTRL_NMMEN_Pos) /*!< USART2 RS485CTRL: NMMEN Mask */ -#define USART2_RS485CTRL_RXDIS_Pos 1 /*!< USART2 RS485CTRL: RXDIS Position */ -#define USART2_RS485CTRL_RXDIS_Msk (0x01UL << USART2_RS485CTRL_RXDIS_Pos) /*!< USART2 RS485CTRL: RXDIS Mask */ -#define USART2_RS485CTRL_AADEN_Pos 2 /*!< USART2 RS485CTRL: AADEN Position */ -#define USART2_RS485CTRL_AADEN_Msk (0x01UL << USART2_RS485CTRL_AADEN_Pos) /*!< USART2 RS485CTRL: AADEN Mask */ -#define USART2_RS485CTRL_DCTRL_Pos 4 /*!< USART2 RS485CTRL: DCTRL Position */ -#define USART2_RS485CTRL_DCTRL_Msk (0x01UL << USART2_RS485CTRL_DCTRL_Pos) /*!< USART2 RS485CTRL: DCTRL Mask */ -#define USART2_RS485CTRL_OINV_Pos 5 /*!< USART2 RS485CTRL: OINV Position */ -#define USART2_RS485CTRL_OINV_Msk (0x01UL << USART2_RS485CTRL_OINV_Pos) /*!< USART2 RS485CTRL: OINV Mask */ - -// ---------------------------------- USART2_RS485ADRMATCH -------------------------------------- -#define USART2_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART2 RS485ADRMATCH: ADRMATCH Position */ -#define USART2_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */ - -// ------------------------------------- USART2_RS485DLY ---------------------------------------- -#define USART2_RS485DLY_DLY_Pos 0 /*!< USART2 RS485DLY: DLY Position */ -#define USART2_RS485DLY_DLY_Msk (0x000000ffUL << USART2_RS485DLY_DLY_Pos) /*!< USART2 RS485DLY: DLY Mask */ - -// ------------------------------------- USART2_SYNCCTRL ---------------------------------------- -#define USART2_SYNCCTRL_SYNC_Pos 0 /*!< USART2 SYNCCTRL: SYNC Position */ -#define USART2_SYNCCTRL_SYNC_Msk (0x01UL << USART2_SYNCCTRL_SYNC_Pos) /*!< USART2 SYNCCTRL: SYNC Mask */ -#define USART2_SYNCCTRL_CSRC_Pos 1 /*!< USART2 SYNCCTRL: CSRC Position */ -#define USART2_SYNCCTRL_CSRC_Msk (0x01UL << USART2_SYNCCTRL_CSRC_Pos) /*!< USART2 SYNCCTRL: CSRC Mask */ -#define USART2_SYNCCTRL_FES_Pos 2 /*!< USART2 SYNCCTRL: FES Position */ -#define USART2_SYNCCTRL_FES_Msk (0x01UL << USART2_SYNCCTRL_FES_Pos) /*!< USART2 SYNCCTRL: FES Mask */ -#define USART2_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART2 SYNCCTRL: TSBYPASS Position */ -#define USART2_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos) /*!< USART2 SYNCCTRL: TSBYPASS Mask */ -#define USART2_SYNCCTRL_CSCEN_Pos 4 /*!< USART2 SYNCCTRL: CSCEN Position */ -#define USART2_SYNCCTRL_CSCEN_Msk (0x01UL << USART2_SYNCCTRL_CSCEN_Pos) /*!< USART2 SYNCCTRL: CSCEN Mask */ -#define USART2_SYNCCTRL_SSSDIS_Pos 5 /*!< USART2 SYNCCTRL: SSSDIS Position */ -#define USART2_SYNCCTRL_SSSDIS_Msk (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos) /*!< USART2 SYNCCTRL: SSSDIS Mask */ -#define USART2_SYNCCTRL_CCCLR_Pos 6 /*!< USART2 SYNCCTRL: CCCLR Position */ -#define USART2_SYNCCTRL_CCCLR_Msk (0x01UL << USART2_SYNCCTRL_CCCLR_Pos) /*!< USART2 SYNCCTRL: CCCLR Mask */ - -// --------------------------------------- USART2_TER ------------------------------------------- -#define USART2_TER_TXEN_Pos 0 /*!< USART2 TER: TXEN Position */ -#define USART2_TER_TXEN_Msk (0x01UL << USART2_TER_TXEN_Pos) /*!< USART2 TER: TXEN Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USART3 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- USART3_DLL ------------------------------------------- -#define USART3_DLL_DLLSB_Pos 0 /*!< USART3 DLL: DLLSB Position */ -#define USART3_DLL_DLLSB_Msk (0x000000ffUL << USART3_DLL_DLLSB_Pos) /*!< USART3 DLL: DLLSB Mask */ - -// --------------------------------------- USART3_THR ------------------------------------------- -#define USART3_THR_THR_Pos 0 /*!< USART3 THR: THR Position */ -#define USART3_THR_THR_Msk (0x000000ffUL << USART3_THR_THR_Pos) /*!< USART3 THR: THR Mask */ - -// --------------------------------------- USART3_RBR ------------------------------------------- -#define USART3_RBR_RBR_Pos 0 /*!< USART3 RBR: RBR Position */ -#define USART3_RBR_RBR_Msk (0x000000ffUL << USART3_RBR_RBR_Pos) /*!< USART3 RBR: RBR Mask */ - -// --------------------------------------- USART3_IER ------------------------------------------- -#define USART3_IER_RBRIE_Pos 0 /*!< USART3 IER: RBRIE Position */ -#define USART3_IER_RBRIE_Msk (0x01UL << USART3_IER_RBRIE_Pos) /*!< USART3 IER: RBRIE Mask */ -#define USART3_IER_THREIE_Pos 1 /*!< USART3 IER: THREIE Position */ -#define USART3_IER_THREIE_Msk (0x01UL << USART3_IER_THREIE_Pos) /*!< USART3 IER: THREIE Mask */ -#define USART3_IER_RXIE_Pos 2 /*!< USART3 IER: RXIE Position */ -#define USART3_IER_RXIE_Msk (0x01UL << USART3_IER_RXIE_Pos) /*!< USART3 IER: RXIE Mask */ -#define USART3_IER_ABEOINTEN_Pos 8 /*!< USART3 IER: ABEOINTEN Position */ -#define USART3_IER_ABEOINTEN_Msk (0x01UL << USART3_IER_ABEOINTEN_Pos) /*!< USART3 IER: ABEOINTEN Mask */ -#define USART3_IER_ABTOINTEN_Pos 9 /*!< USART3 IER: ABTOINTEN Position */ -#define USART3_IER_ABTOINTEN_Msk (0x01UL << USART3_IER_ABTOINTEN_Pos) /*!< USART3 IER: ABTOINTEN Mask */ - -// --------------------------------------- USART3_DLM ------------------------------------------- -#define USART3_DLM_DLMSB_Pos 0 /*!< USART3 DLM: DLMSB Position */ -#define USART3_DLM_DLMSB_Msk (0x000000ffUL << USART3_DLM_DLMSB_Pos) /*!< USART3 DLM: DLMSB Mask */ - -// --------------------------------------- USART3_FCR ------------------------------------------- -#define USART3_FCR_FIFOEN_Pos 0 /*!< USART3 FCR: FIFOEN Position */ -#define USART3_FCR_FIFOEN_Msk (0x01UL << USART3_FCR_FIFOEN_Pos) /*!< USART3 FCR: FIFOEN Mask */ -#define USART3_FCR_RXFIFORES_Pos 1 /*!< USART3 FCR: RXFIFORES Position */ -#define USART3_FCR_RXFIFORES_Msk (0x01UL << USART3_FCR_RXFIFORES_Pos) /*!< USART3 FCR: RXFIFORES Mask */ -#define USART3_FCR_TXFIFORES_Pos 2 /*!< USART3 FCR: TXFIFORES Position */ -#define USART3_FCR_TXFIFORES_Msk (0x01UL << USART3_FCR_TXFIFORES_Pos) /*!< USART3 FCR: TXFIFORES Mask */ -#define USART3_FCR_DMAMODE_Pos 3 /*!< USART3 FCR: DMAMODE Position */ -#define USART3_FCR_DMAMODE_Msk (0x01UL << USART3_FCR_DMAMODE_Pos) /*!< USART3 FCR: DMAMODE Mask */ -#define USART3_FCR_RXTRIGLVL_Pos 6 /*!< USART3 FCR: RXTRIGLVL Position */ -#define USART3_FCR_RXTRIGLVL_Msk (0x03UL << USART3_FCR_RXTRIGLVL_Pos) /*!< USART3 FCR: RXTRIGLVL Mask */ - -// --------------------------------------- USART3_IIR ------------------------------------------- -#define USART3_IIR_INTSTATUS_Pos 0 /*!< USART3 IIR: INTSTATUS Position */ -#define USART3_IIR_INTSTATUS_Msk (0x01UL << USART3_IIR_INTSTATUS_Pos) /*!< USART3 IIR: INTSTATUS Mask */ -#define USART3_IIR_INTID_Pos 1 /*!< USART3 IIR: INTID Position */ -#define USART3_IIR_INTID_Msk (0x07UL << USART3_IIR_INTID_Pos) /*!< USART3 IIR: INTID Mask */ -#define USART3_IIR_FIFOENABLE_Pos 6 /*!< USART3 IIR: FIFOENABLE Position */ -#define USART3_IIR_FIFOENABLE_Msk (0x03UL << USART3_IIR_FIFOENABLE_Pos) /*!< USART3 IIR: FIFOENABLE Mask */ -#define USART3_IIR_ABEOINT_Pos 8 /*!< USART3 IIR: ABEOINT Position */ -#define USART3_IIR_ABEOINT_Msk (0x01UL << USART3_IIR_ABEOINT_Pos) /*!< USART3 IIR: ABEOINT Mask */ -#define USART3_IIR_ABTOINT_Pos 9 /*!< USART3 IIR: ABTOINT Position */ -#define USART3_IIR_ABTOINT_Msk (0x01UL << USART3_IIR_ABTOINT_Pos) /*!< USART3 IIR: ABTOINT Mask */ - -// --------------------------------------- USART3_LCR ------------------------------------------- -#define USART3_LCR_WLS_Pos 0 /*!< USART3 LCR: WLS Position */ -#define USART3_LCR_WLS_Msk (0x03UL << USART3_LCR_WLS_Pos) /*!< USART3 LCR: WLS Mask */ -#define USART3_LCR_SBS_Pos 2 /*!< USART3 LCR: SBS Position */ -#define USART3_LCR_SBS_Msk (0x01UL << USART3_LCR_SBS_Pos) /*!< USART3 LCR: SBS Mask */ -#define USART3_LCR_PE_Pos 3 /*!< USART3 LCR: PE Position */ -#define USART3_LCR_PE_Msk (0x01UL << USART3_LCR_PE_Pos) /*!< USART3 LCR: PE Mask */ -#define USART3_LCR_PS_Pos 4 /*!< USART3 LCR: PS Position */ -#define USART3_LCR_PS_Msk (0x03UL << USART3_LCR_PS_Pos) /*!< USART3 LCR: PS Mask */ -#define USART3_LCR_BC_Pos 6 /*!< USART3 LCR: BC Position */ -#define USART3_LCR_BC_Msk (0x01UL << USART3_LCR_BC_Pos) /*!< USART3 LCR: BC Mask */ -#define USART3_LCR_DLAB_Pos 7 /*!< USART3 LCR: DLAB Position */ -#define USART3_LCR_DLAB_Msk (0x01UL << USART3_LCR_DLAB_Pos) /*!< USART3 LCR: DLAB Mask */ - -// --------------------------------------- USART3_LSR ------------------------------------------- -#define USART3_LSR_RDR_Pos 0 /*!< USART3 LSR: RDR Position */ -#define USART3_LSR_RDR_Msk (0x01UL << USART3_LSR_RDR_Pos) /*!< USART3 LSR: RDR Mask */ -#define USART3_LSR_OE_Pos 1 /*!< USART3 LSR: OE Position */ -#define USART3_LSR_OE_Msk (0x01UL << USART3_LSR_OE_Pos) /*!< USART3 LSR: OE Mask */ -#define USART3_LSR_PE_Pos 2 /*!< USART3 LSR: PE Position */ -#define USART3_LSR_PE_Msk (0x01UL << USART3_LSR_PE_Pos) /*!< USART3 LSR: PE Mask */ -#define USART3_LSR_FE_Pos 3 /*!< USART3 LSR: FE Position */ -#define USART3_LSR_FE_Msk (0x01UL << USART3_LSR_FE_Pos) /*!< USART3 LSR: FE Mask */ -#define USART3_LSR_BI_Pos 4 /*!< USART3 LSR: BI Position */ -#define USART3_LSR_BI_Msk (0x01UL << USART3_LSR_BI_Pos) /*!< USART3 LSR: BI Mask */ -#define USART3_LSR_THRE_Pos 5 /*!< USART3 LSR: THRE Position */ -#define USART3_LSR_THRE_Msk (0x01UL << USART3_LSR_THRE_Pos) /*!< USART3 LSR: THRE Mask */ -#define USART3_LSR_TEMT_Pos 6 /*!< USART3 LSR: TEMT Position */ -#define USART3_LSR_TEMT_Msk (0x01UL << USART3_LSR_TEMT_Pos) /*!< USART3 LSR: TEMT Mask */ -#define USART3_LSR_RXFE_Pos 7 /*!< USART3 LSR: RXFE Position */ -#define USART3_LSR_RXFE_Msk (0x01UL << USART3_LSR_RXFE_Pos) /*!< USART3 LSR: RXFE Mask */ -#define USART3_LSR_TXERR_Pos 8 /*!< USART3 LSR: TXERR Position */ -#define USART3_LSR_TXERR_Msk (0x01UL << USART3_LSR_TXERR_Pos) /*!< USART3 LSR: TXERR Mask */ - -// --------------------------------------- USART3_SCR ------------------------------------------- -#define USART3_SCR_PAD_Pos 0 /*!< USART3 SCR: PAD Position */ -#define USART3_SCR_PAD_Msk (0x000000ffUL << USART3_SCR_PAD_Pos) /*!< USART3 SCR: PAD Mask */ - -// --------------------------------------- USART3_ACR ------------------------------------------- -#define USART3_ACR_START_Pos 0 /*!< USART3 ACR: START Position */ -#define USART3_ACR_START_Msk (0x01UL << USART3_ACR_START_Pos) /*!< USART3 ACR: START Mask */ -#define USART3_ACR_MODE_Pos 1 /*!< USART3 ACR: MODE Position */ -#define USART3_ACR_MODE_Msk (0x01UL << USART3_ACR_MODE_Pos) /*!< USART3 ACR: MODE Mask */ -#define USART3_ACR_AUTORESTART_Pos 2 /*!< USART3 ACR: AUTORESTART Position */ -#define USART3_ACR_AUTORESTART_Msk (0x01UL << USART3_ACR_AUTORESTART_Pos) /*!< USART3 ACR: AUTORESTART Mask */ -#define USART3_ACR_ABEOINTCLR_Pos 8 /*!< USART3 ACR: ABEOINTCLR Position */ -#define USART3_ACR_ABEOINTCLR_Msk (0x01UL << USART3_ACR_ABEOINTCLR_Pos) /*!< USART3 ACR: ABEOINTCLR Mask */ -#define USART3_ACR_ABTOINTCLR_Pos 9 /*!< USART3 ACR: ABTOINTCLR Position */ -#define USART3_ACR_ABTOINTCLR_Msk (0x01UL << USART3_ACR_ABTOINTCLR_Pos) /*!< USART3 ACR: ABTOINTCLR Mask */ - -// --------------------------------------- USART3_ICR ------------------------------------------- -#define USART3_ICR_IRDAEN_Pos 0 /*!< USART3 ICR: IRDAEN Position */ -#define USART3_ICR_IRDAEN_Msk (0x01UL << USART3_ICR_IRDAEN_Pos) /*!< USART3 ICR: IRDAEN Mask */ -#define USART3_ICR_IRDAINV_Pos 1 /*!< USART3 ICR: IRDAINV Position */ -#define USART3_ICR_IRDAINV_Msk (0x01UL << USART3_ICR_IRDAINV_Pos) /*!< USART3 ICR: IRDAINV Mask */ -#define USART3_ICR_FIXPULSEEN_Pos 2 /*!< USART3 ICR: FIXPULSEEN Position */ -#define USART3_ICR_FIXPULSEEN_Msk (0x01UL << USART3_ICR_FIXPULSEEN_Pos) /*!< USART3 ICR: FIXPULSEEN Mask */ -#define USART3_ICR_PULSEDIV_Pos 3 /*!< USART3 ICR: PULSEDIV Position */ -#define USART3_ICR_PULSEDIV_Msk (0x07UL << USART3_ICR_PULSEDIV_Pos) /*!< USART3 ICR: PULSEDIV Mask */ - -// --------------------------------------- USART3_FDR ------------------------------------------- -#define USART3_FDR_DIVADDVAL_Pos 0 /*!< USART3 FDR: DIVADDVAL Position */ -#define USART3_FDR_DIVADDVAL_Msk (0x0fUL << USART3_FDR_DIVADDVAL_Pos) /*!< USART3 FDR: DIVADDVAL Mask */ -#define USART3_FDR_MULVAL_Pos 4 /*!< USART3 FDR: MULVAL Position */ -#define USART3_FDR_MULVAL_Msk (0x0fUL << USART3_FDR_MULVAL_Pos) /*!< USART3 FDR: MULVAL Mask */ - -// --------------------------------------- USART3_OSR ------------------------------------------- -#define USART3_OSR_OSFRAC_Pos 1 /*!< USART3 OSR: OSFRAC Position */ -#define USART3_OSR_OSFRAC_Msk (0x07UL << USART3_OSR_OSFRAC_Pos) /*!< USART3 OSR: OSFRAC Mask */ -#define USART3_OSR_OSINT_Pos 4 /*!< USART3 OSR: OSINT Position */ -#define USART3_OSR_OSINT_Msk (0x0fUL << USART3_OSR_OSINT_Pos) /*!< USART3 OSR: OSINT Mask */ -#define USART3_OSR_FDINT_Pos 8 /*!< USART3 OSR: FDINT Position */ -#define USART3_OSR_FDINT_Msk (0x7fUL << USART3_OSR_FDINT_Pos) /*!< USART3 OSR: FDINT Mask */ - -// --------------------------------------- USART3_HDEN ------------------------------------------ -#define USART3_HDEN_HDEN_Pos 0 /*!< USART3 HDEN: HDEN Position */ -#define USART3_HDEN_HDEN_Msk (0x01UL << USART3_HDEN_HDEN_Pos) /*!< USART3 HDEN: HDEN Mask */ - -// ------------------------------------- USART3_SCICTRL ----------------------------------------- -#define USART3_SCICTRL_SCIEN_Pos 0 /*!< USART3 SCICTRL: SCIEN Position */ -#define USART3_SCICTRL_SCIEN_Msk (0x01UL << USART3_SCICTRL_SCIEN_Pos) /*!< USART3 SCICTRL: SCIEN Mask */ -#define USART3_SCICTRL_NACKDIS_Pos 1 /*!< USART3 SCICTRL: NACKDIS Position */ -#define USART3_SCICTRL_NACKDIS_Msk (0x01UL << USART3_SCICTRL_NACKDIS_Pos) /*!< USART3 SCICTRL: NACKDIS Mask */ -#define USART3_SCICTRL_PROTSEL_Pos 2 /*!< USART3 SCICTRL: PROTSEL Position */ -#define USART3_SCICTRL_PROTSEL_Msk (0x01UL << USART3_SCICTRL_PROTSEL_Pos) /*!< USART3 SCICTRL: PROTSEL Mask */ -#define USART3_SCICTRL_TXRETRY_Pos 5 /*!< USART3 SCICTRL: TXRETRY Position */ -#define USART3_SCICTRL_TXRETRY_Msk (0x07UL << USART3_SCICTRL_TXRETRY_Pos) /*!< USART3 SCICTRL: TXRETRY Mask */ -#define USART3_SCICTRL_GUARDTIME_Pos 8 /*!< USART3 SCICTRL: GUARDTIME Position */ -#define USART3_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos) /*!< USART3 SCICTRL: GUARDTIME Mask */ - -// ------------------------------------ USART3_RS485CTRL ---------------------------------------- -#define USART3_RS485CTRL_NMMEN_Pos 0 /*!< USART3 RS485CTRL: NMMEN Position */ -#define USART3_RS485CTRL_NMMEN_Msk (0x01UL << USART3_RS485CTRL_NMMEN_Pos) /*!< USART3 RS485CTRL: NMMEN Mask */ -#define USART3_RS485CTRL_RXDIS_Pos 1 /*!< USART3 RS485CTRL: RXDIS Position */ -#define USART3_RS485CTRL_RXDIS_Msk (0x01UL << USART3_RS485CTRL_RXDIS_Pos) /*!< USART3 RS485CTRL: RXDIS Mask */ -#define USART3_RS485CTRL_AADEN_Pos 2 /*!< USART3 RS485CTRL: AADEN Position */ -#define USART3_RS485CTRL_AADEN_Msk (0x01UL << USART3_RS485CTRL_AADEN_Pos) /*!< USART3 RS485CTRL: AADEN Mask */ -#define USART3_RS485CTRL_DCTRL_Pos 4 /*!< USART3 RS485CTRL: DCTRL Position */ -#define USART3_RS485CTRL_DCTRL_Msk (0x01UL << USART3_RS485CTRL_DCTRL_Pos) /*!< USART3 RS485CTRL: DCTRL Mask */ -#define USART3_RS485CTRL_OINV_Pos 5 /*!< USART3 RS485CTRL: OINV Position */ -#define USART3_RS485CTRL_OINV_Msk (0x01UL << USART3_RS485CTRL_OINV_Pos) /*!< USART3 RS485CTRL: OINV Mask */ - -// ---------------------------------- USART3_RS485ADRMATCH -------------------------------------- -#define USART3_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART3 RS485ADRMATCH: ADRMATCH Position */ -#define USART3_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */ - -// ------------------------------------- USART3_RS485DLY ---------------------------------------- -#define USART3_RS485DLY_DLY_Pos 0 /*!< USART3 RS485DLY: DLY Position */ -#define USART3_RS485DLY_DLY_Msk (0x000000ffUL << USART3_RS485DLY_DLY_Pos) /*!< USART3 RS485DLY: DLY Mask */ - -// ------------------------------------- USART3_SYNCCTRL ---------------------------------------- -#define USART3_SYNCCTRL_SYNC_Pos 0 /*!< USART3 SYNCCTRL: SYNC Position */ -#define USART3_SYNCCTRL_SYNC_Msk (0x01UL << USART3_SYNCCTRL_SYNC_Pos) /*!< USART3 SYNCCTRL: SYNC Mask */ -#define USART3_SYNCCTRL_CSRC_Pos 1 /*!< USART3 SYNCCTRL: CSRC Position */ -#define USART3_SYNCCTRL_CSRC_Msk (0x01UL << USART3_SYNCCTRL_CSRC_Pos) /*!< USART3 SYNCCTRL: CSRC Mask */ -#define USART3_SYNCCTRL_FES_Pos 2 /*!< USART3 SYNCCTRL: FES Position */ -#define USART3_SYNCCTRL_FES_Msk (0x01UL << USART3_SYNCCTRL_FES_Pos) /*!< USART3 SYNCCTRL: FES Mask */ -#define USART3_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART3 SYNCCTRL: TSBYPASS Position */ -#define USART3_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos) /*!< USART3 SYNCCTRL: TSBYPASS Mask */ -#define USART3_SYNCCTRL_CSCEN_Pos 4 /*!< USART3 SYNCCTRL: CSCEN Position */ -#define USART3_SYNCCTRL_CSCEN_Msk (0x01UL << USART3_SYNCCTRL_CSCEN_Pos) /*!< USART3 SYNCCTRL: CSCEN Mask */ -#define USART3_SYNCCTRL_SSSDIS_Pos 5 /*!< USART3 SYNCCTRL: SSSDIS Position */ -#define USART3_SYNCCTRL_SSSDIS_Msk (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos) /*!< USART3 SYNCCTRL: SSSDIS Mask */ -#define USART3_SYNCCTRL_CCCLR_Pos 6 /*!< USART3 SYNCCTRL: CCCLR Position */ -#define USART3_SYNCCTRL_CCCLR_Msk (0x01UL << USART3_SYNCCTRL_CCCLR_Pos) /*!< USART3 SYNCCTRL: CCCLR Mask */ - -// --------------------------------------- USART3_TER ------------------------------------------- -#define USART3_TER_TXEN_Pos 0 /*!< USART3 TER: TXEN Position */ -#define USART3_TER_TXEN_Msk (0x01UL << USART3_TER_TXEN_Pos) /*!< USART3 TER: TXEN Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- UART1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- UART1_RBR ------------------------------------------- -#define UART1_RBR_RBR_Pos 0 /*!< UART1 RBR: RBR Position */ -#define UART1_RBR_RBR_Msk (0x000000ffUL << UART1_RBR_RBR_Pos) /*!< UART1 RBR: RBR Mask */ - -// ---------------------------------------- UART1_THR ------------------------------------------- -#define UART1_THR_THR_Pos 0 /*!< UART1 THR: THR Position */ -#define UART1_THR_THR_Msk (0x000000ffUL << UART1_THR_THR_Pos) /*!< UART1 THR: THR Mask */ - -// ---------------------------------------- UART1_DLL ------------------------------------------- -#define UART1_DLL_DLLSB_Pos 0 /*!< UART1 DLL: DLLSB Position */ -#define UART1_DLL_DLLSB_Msk (0x000000ffUL << UART1_DLL_DLLSB_Pos) /*!< UART1 DLL: DLLSB Mask */ - -// ---------------------------------------- UART1_DLM ------------------------------------------- -#define UART1_DLM_DLMSB_Pos 0 /*!< UART1 DLM: DLMSB Position */ -#define UART1_DLM_DLMSB_Msk (0x000000ffUL << UART1_DLM_DLMSB_Pos) /*!< UART1 DLM: DLMSB Mask */ - -// ---------------------------------------- UART1_IER ------------------------------------------- -#define UART1_IER_RBRIE_Pos 0 /*!< UART1 IER: RBRIE Position */ -#define UART1_IER_RBRIE_Msk (0x01UL << UART1_IER_RBRIE_Pos) /*!< UART1 IER: RBRIE Mask */ -#define UART1_IER_THREIE_Pos 1 /*!< UART1 IER: THREIE Position */ -#define UART1_IER_THREIE_Msk (0x01UL << UART1_IER_THREIE_Pos) /*!< UART1 IER: THREIE Mask */ -#define UART1_IER_RXIE_Pos 2 /*!< UART1 IER: RXIE Position */ -#define UART1_IER_RXIE_Msk (0x01UL << UART1_IER_RXIE_Pos) /*!< UART1 IER: RXIE Mask */ -#define UART1_IER_MSIE_Pos 3 /*!< UART1 IER: MSIE Position */ -#define UART1_IER_MSIE_Msk (0x01UL << UART1_IER_MSIE_Pos) /*!< UART1 IER: MSIE Mask */ -#define UART1_IER_CTSIE_Pos 7 /*!< UART1 IER: CTSIE Position */ -#define UART1_IER_CTSIE_Msk (0x01UL << UART1_IER_CTSIE_Pos) /*!< UART1 IER: CTSIE Mask */ -#define UART1_IER_ABEOIE_Pos 8 /*!< UART1 IER: ABEOIE Position */ -#define UART1_IER_ABEOIE_Msk (0x01UL << UART1_IER_ABEOIE_Pos) /*!< UART1 IER: ABEOIE Mask */ -#define UART1_IER_ABTOIE_Pos 9 /*!< UART1 IER: ABTOIE Position */ -#define UART1_IER_ABTOIE_Msk (0x01UL << UART1_IER_ABTOIE_Pos) /*!< UART1 IER: ABTOIE Mask */ - -// ---------------------------------------- UART1_IIR ------------------------------------------- -#define UART1_IIR_INTSTATUS_Pos 0 /*!< UART1 IIR: INTSTATUS Position */ -#define UART1_IIR_INTSTATUS_Msk (0x01UL << UART1_IIR_INTSTATUS_Pos) /*!< UART1 IIR: INTSTATUS Mask */ -#define UART1_IIR_INTID_Pos 1 /*!< UART1 IIR: INTID Position */ -#define UART1_IIR_INTID_Msk (0x07UL << UART1_IIR_INTID_Pos) /*!< UART1 IIR: INTID Mask */ -#define UART1_IIR_FIFOENABLE_Pos 6 /*!< UART1 IIR: FIFOENABLE Position */ -#define UART1_IIR_FIFOENABLE_Msk (0x03UL << UART1_IIR_FIFOENABLE_Pos) /*!< UART1 IIR: FIFOENABLE Mask */ -#define UART1_IIR_ABEOINT_Pos 8 /*!< UART1 IIR: ABEOINT Position */ -#define UART1_IIR_ABEOINT_Msk (0x01UL << UART1_IIR_ABEOINT_Pos) /*!< UART1 IIR: ABEOINT Mask */ -#define UART1_IIR_ABTOINT_Pos 9 /*!< UART1 IIR: ABTOINT Position */ -#define UART1_IIR_ABTOINT_Msk (0x01UL << UART1_IIR_ABTOINT_Pos) /*!< UART1 IIR: ABTOINT Mask */ - -// ---------------------------------------- UART1_FCR ------------------------------------------- -#define UART1_FCR_FIFOEN_Pos 0 /*!< UART1 FCR: FIFOEN Position */ -#define UART1_FCR_FIFOEN_Msk (0x01UL << UART1_FCR_FIFOEN_Pos) /*!< UART1 FCR: FIFOEN Mask */ -#define UART1_FCR_RXFIFORES_Pos 1 /*!< UART1 FCR: RXFIFORES Position */ -#define UART1_FCR_RXFIFORES_Msk (0x01UL << UART1_FCR_RXFIFORES_Pos) /*!< UART1 FCR: RXFIFORES Mask */ -#define UART1_FCR_TXFIFORES_Pos 2 /*!< UART1 FCR: TXFIFORES Position */ -#define UART1_FCR_TXFIFORES_Msk (0x01UL << UART1_FCR_TXFIFORES_Pos) /*!< UART1 FCR: TXFIFORES Mask */ -#define UART1_FCR_DMAMODE_Pos 3 /*!< UART1 FCR: DMAMODE Position */ -#define UART1_FCR_DMAMODE_Msk (0x01UL << UART1_FCR_DMAMODE_Pos) /*!< UART1 FCR: DMAMODE Mask */ -#define UART1_FCR_RXTRIGLVL_Pos 6 /*!< UART1 FCR: RXTRIGLVL Position */ -#define UART1_FCR_RXTRIGLVL_Msk (0x03UL << UART1_FCR_RXTRIGLVL_Pos) /*!< UART1 FCR: RXTRIGLVL Mask */ - -// ---------------------------------------- UART1_LCR ------------------------------------------- -#define UART1_LCR_WLS_Pos 0 /*!< UART1 LCR: WLS Position */ -#define UART1_LCR_WLS_Msk (0x03UL << UART1_LCR_WLS_Pos) /*!< UART1 LCR: WLS Mask */ -#define UART1_LCR_SBS_Pos 2 /*!< UART1 LCR: SBS Position */ -#define UART1_LCR_SBS_Msk (0x01UL << UART1_LCR_SBS_Pos) /*!< UART1 LCR: SBS Mask */ -#define UART1_LCR_PE_Pos 3 /*!< UART1 LCR: PE Position */ -#define UART1_LCR_PE_Msk (0x01UL << UART1_LCR_PE_Pos) /*!< UART1 LCR: PE Mask */ -#define UART1_LCR_PS_Pos 4 /*!< UART1 LCR: PS Position */ -#define UART1_LCR_PS_Msk (0x03UL << UART1_LCR_PS_Pos) /*!< UART1 LCR: PS Mask */ -#define UART1_LCR_BC_Pos 6 /*!< UART1 LCR: BC Position */ -#define UART1_LCR_BC_Msk (0x01UL << UART1_LCR_BC_Pos) /*!< UART1 LCR: BC Mask */ -#define UART1_LCR_DLAB_Pos 7 /*!< UART1 LCR: DLAB Position */ -#define UART1_LCR_DLAB_Msk (0x01UL << UART1_LCR_DLAB_Pos) /*!< UART1 LCR: DLAB Mask */ - -// ---------------------------------------- UART1_MCR ------------------------------------------- -#define UART1_MCR_DTRCTRL_Pos 0 /*!< UART1 MCR: DTRCTRL Position */ -#define UART1_MCR_DTRCTRL_Msk (0x01UL << UART1_MCR_DTRCTRL_Pos) /*!< UART1 MCR: DTRCTRL Mask */ -#define UART1_MCR_RTSCTRL_Pos 1 /*!< UART1 MCR: RTSCTRL Position */ -#define UART1_MCR_RTSCTRL_Msk (0x01UL << UART1_MCR_RTSCTRL_Pos) /*!< UART1 MCR: RTSCTRL Mask */ -#define UART1_MCR_LMS_Pos 4 /*!< UART1 MCR: LMS Position */ -#define UART1_MCR_LMS_Msk (0x01UL << UART1_MCR_LMS_Pos) /*!< UART1 MCR: LMS Mask */ -#define UART1_MCR_RTSEN_Pos 6 /*!< UART1 MCR: RTSEN Position */ -#define UART1_MCR_RTSEN_Msk (0x01UL << UART1_MCR_RTSEN_Pos) /*!< UART1 MCR: RTSEN Mask */ -#define UART1_MCR_CTSEN_Pos 7 /*!< UART1 MCR: CTSEN Position */ -#define UART1_MCR_CTSEN_Msk (0x01UL << UART1_MCR_CTSEN_Pos) /*!< UART1 MCR: CTSEN Mask */ - -// ---------------------------------------- UART1_LSR ------------------------------------------- -#define UART1_LSR_RDR_Pos 0 /*!< UART1 LSR: RDR Position */ -#define UART1_LSR_RDR_Msk (0x01UL << UART1_LSR_RDR_Pos) /*!< UART1 LSR: RDR Mask */ -#define UART1_LSR_OE_Pos 1 /*!< UART1 LSR: OE Position */ -#define UART1_LSR_OE_Msk (0x01UL << UART1_LSR_OE_Pos) /*!< UART1 LSR: OE Mask */ -#define UART1_LSR_PE_Pos 2 /*!< UART1 LSR: PE Position */ -#define UART1_LSR_PE_Msk (0x01UL << UART1_LSR_PE_Pos) /*!< UART1 LSR: PE Mask */ -#define UART1_LSR_FE_Pos 3 /*!< UART1 LSR: FE Position */ -#define UART1_LSR_FE_Msk (0x01UL << UART1_LSR_FE_Pos) /*!< UART1 LSR: FE Mask */ -#define UART1_LSR_BI_Pos 4 /*!< UART1 LSR: BI Position */ -#define UART1_LSR_BI_Msk (0x01UL << UART1_LSR_BI_Pos) /*!< UART1 LSR: BI Mask */ -#define UART1_LSR_THRE_Pos 5 /*!< UART1 LSR: THRE Position */ -#define UART1_LSR_THRE_Msk (0x01UL << UART1_LSR_THRE_Pos) /*!< UART1 LSR: THRE Mask */ -#define UART1_LSR_TEMT_Pos 6 /*!< UART1 LSR: TEMT Position */ -#define UART1_LSR_TEMT_Msk (0x01UL << UART1_LSR_TEMT_Pos) /*!< UART1 LSR: TEMT Mask */ -#define UART1_LSR_RXFE_Pos 7 /*!< UART1 LSR: RXFE Position */ -#define UART1_LSR_RXFE_Msk (0x01UL << UART1_LSR_RXFE_Pos) /*!< UART1 LSR: RXFE Mask */ - -// ---------------------------------------- UART1_MSR ------------------------------------------- -#define UART1_MSR_DCTS_Pos 0 /*!< UART1 MSR: DCTS Position */ -#define UART1_MSR_DCTS_Msk (0x01UL << UART1_MSR_DCTS_Pos) /*!< UART1 MSR: DCTS Mask */ -#define UART1_MSR_DDSR_Pos 1 /*!< UART1 MSR: DDSR Position */ -#define UART1_MSR_DDSR_Msk (0x01UL << UART1_MSR_DDSR_Pos) /*!< UART1 MSR: DDSR Mask */ -#define UART1_MSR_TERI_Pos 2 /*!< UART1 MSR: TERI Position */ -#define UART1_MSR_TERI_Msk (0x01UL << UART1_MSR_TERI_Pos) /*!< UART1 MSR: TERI Mask */ -#define UART1_MSR_DDCD_Pos 3 /*!< UART1 MSR: DDCD Position */ -#define UART1_MSR_DDCD_Msk (0x01UL << UART1_MSR_DDCD_Pos) /*!< UART1 MSR: DDCD Mask */ -#define UART1_MSR_CTS_Pos 4 /*!< UART1 MSR: CTS Position */ -#define UART1_MSR_CTS_Msk (0x01UL << UART1_MSR_CTS_Pos) /*!< UART1 MSR: CTS Mask */ -#define UART1_MSR_DSR_Pos 5 /*!< UART1 MSR: DSR Position */ -#define UART1_MSR_DSR_Msk (0x01UL << UART1_MSR_DSR_Pos) /*!< UART1 MSR: DSR Mask */ -#define UART1_MSR_RI_Pos 6 /*!< UART1 MSR: RI Position */ -#define UART1_MSR_RI_Msk (0x01UL << UART1_MSR_RI_Pos) /*!< UART1 MSR: RI Mask */ -#define UART1_MSR_DCD_Pos 7 /*!< UART1 MSR: DCD Position */ -#define UART1_MSR_DCD_Msk (0x01UL << UART1_MSR_DCD_Pos) /*!< UART1 MSR: DCD Mask */ - -// ---------------------------------------- UART1_SCR ------------------------------------------- -#define UART1_SCR_Pad_Pos 0 /*!< UART1 SCR: Pad Position */ -#define UART1_SCR_Pad_Msk (0x000000ffUL << UART1_SCR_Pad_Pos) /*!< UART1 SCR: Pad Mask */ - -// ---------------------------------------- UART1_ACR ------------------------------------------- -#define UART1_ACR_START_Pos 0 /*!< UART1 ACR: START Position */ -#define UART1_ACR_START_Msk (0x01UL << UART1_ACR_START_Pos) /*!< UART1 ACR: START Mask */ -#define UART1_ACR_MODE_Pos 1 /*!< UART1 ACR: MODE Position */ -#define UART1_ACR_MODE_Msk (0x01UL << UART1_ACR_MODE_Pos) /*!< UART1 ACR: MODE Mask */ -#define UART1_ACR_AUTORESTART_Pos 2 /*!< UART1 ACR: AUTORESTART Position */ -#define UART1_ACR_AUTORESTART_Msk (0x01UL << UART1_ACR_AUTORESTART_Pos) /*!< UART1 ACR: AUTORESTART Mask */ -#define UART1_ACR_ABEOINTCLR_Pos 8 /*!< UART1 ACR: ABEOINTCLR Position */ -#define UART1_ACR_ABEOINTCLR_Msk (0x01UL << UART1_ACR_ABEOINTCLR_Pos) /*!< UART1 ACR: ABEOINTCLR Mask */ -#define UART1_ACR_ABTOINTCLR_Pos 9 /*!< UART1 ACR: ABTOINTCLR Position */ -#define UART1_ACR_ABTOINTCLR_Msk (0x01UL << UART1_ACR_ABTOINTCLR_Pos) /*!< UART1 ACR: ABTOINTCLR Mask */ - -// ---------------------------------------- UART1_FDR ------------------------------------------- -#define UART1_FDR_DIVADDVAL_Pos 0 /*!< UART1 FDR: DIVADDVAL Position */ -#define UART1_FDR_DIVADDVAL_Msk (0x0fUL << UART1_FDR_DIVADDVAL_Pos) /*!< UART1 FDR: DIVADDVAL Mask */ -#define UART1_FDR_MULVAL_Pos 4 /*!< UART1 FDR: MULVAL Position */ -#define UART1_FDR_MULVAL_Msk (0x0fUL << UART1_FDR_MULVAL_Pos) /*!< UART1 FDR: MULVAL Mask */ - -// ---------------------------------------- UART1_TER ------------------------------------------- -#define UART1_TER_TXEN_Pos 7 /*!< UART1 TER: TXEN Position */ -#define UART1_TER_TXEN_Msk (0x01UL << UART1_TER_TXEN_Pos) /*!< UART1 TER: TXEN Mask */ - -// ------------------------------------- UART1_RS485CTRL ---------------------------------------- -#define UART1_RS485CTRL_NMMEN_Pos 0 /*!< UART1 RS485CTRL: NMMEN Position */ -#define UART1_RS485CTRL_NMMEN_Msk (0x01UL << UART1_RS485CTRL_NMMEN_Pos) /*!< UART1 RS485CTRL: NMMEN Mask */ -#define UART1_RS485CTRL_RXDIS_Pos 1 /*!< UART1 RS485CTRL: RXDIS Position */ -#define UART1_RS485CTRL_RXDIS_Msk (0x01UL << UART1_RS485CTRL_RXDIS_Pos) /*!< UART1 RS485CTRL: RXDIS Mask */ -#define UART1_RS485CTRL_AADEN_Pos 2 /*!< UART1 RS485CTRL: AADEN Position */ -#define UART1_RS485CTRL_AADEN_Msk (0x01UL << UART1_RS485CTRL_AADEN_Pos) /*!< UART1 RS485CTRL: AADEN Mask */ -#define UART1_RS485CTRL_SEL_Pos 3 /*!< UART1 RS485CTRL: SEL Position */ -#define UART1_RS485CTRL_SEL_Msk (0x01UL << UART1_RS485CTRL_SEL_Pos) /*!< UART1 RS485CTRL: SEL Mask */ -#define UART1_RS485CTRL_DCTRL_Pos 4 /*!< UART1 RS485CTRL: DCTRL Position */ -#define UART1_RS485CTRL_DCTRL_Msk (0x01UL << UART1_RS485CTRL_DCTRL_Pos) /*!< UART1 RS485CTRL: DCTRL Mask */ -#define UART1_RS485CTRL_OINV_Pos 5 /*!< UART1 RS485CTRL: OINV Position */ -#define UART1_RS485CTRL_OINV_Msk (0x01UL << UART1_RS485CTRL_OINV_Pos) /*!< UART1 RS485CTRL: OINV Mask */ - -// ----------------------------------- UART1_RS485ADRMATCH -------------------------------------- -#define UART1_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< UART1 RS485ADRMATCH: ADRMATCH Position */ -#define UART1_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos) /*!< UART1 RS485ADRMATCH: ADRMATCH Mask */ - -// ------------------------------------- UART1_RS485DLY ----------------------------------------- -#define UART1_RS485DLY_DLY_Pos 0 /*!< UART1 RS485DLY: DLY Position */ -#define UART1_RS485DLY_DLY_Msk (0x000000ffUL << UART1_RS485DLY_DLY_Pos) /*!< UART1 RS485DLY: DLY Mask */ - -// -------------------------------------- UART1_FIFOLVL ----------------------------------------- -#define UART1_FIFOLVL_RXFIFILVL_Pos 0 /*!< UART1 FIFOLVL: RXFIFILVL Position */ -#define UART1_FIFOLVL_RXFIFILVL_Msk (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos) /*!< UART1 FIFOLVL: RXFIFILVL Mask */ -#define UART1_FIFOLVL_TXFIFOLVL_Pos 8 /*!< UART1 FIFOLVL: TXFIFOLVL Position */ -#define UART1_FIFOLVL_TXFIFOLVL_Msk (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos) /*!< UART1 FIFOLVL: TXFIFOLVL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SSP0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- SSP0_CR0 -------------------------------------------- -#define SSP0_CR0_DSS_Pos 0 /*!< SSP0 CR0: DSS Position */ -#define SSP0_CR0_DSS_Msk (0x0fUL << SSP0_CR0_DSS_Pos) /*!< SSP0 CR0: DSS Mask */ -#define SSP0_CR0_FRF_Pos 4 /*!< SSP0 CR0: FRF Position */ -#define SSP0_CR0_FRF_Msk (0x03UL << SSP0_CR0_FRF_Pos) /*!< SSP0 CR0: FRF Mask */ -#define SSP0_CR0_CPOL_Pos 6 /*!< SSP0 CR0: CPOL Position */ -#define SSP0_CR0_CPOL_Msk (0x01UL << SSP0_CR0_CPOL_Pos) /*!< SSP0 CR0: CPOL Mask */ -#define SSP0_CR0_CPHA_Pos 7 /*!< SSP0 CR0: CPHA Position */ -#define SSP0_CR0_CPHA_Msk (0x01UL << SSP0_CR0_CPHA_Pos) /*!< SSP0 CR0: CPHA Mask */ -#define SSP0_CR0_SCR_Pos 8 /*!< SSP0 CR0: SCR Position */ -#define SSP0_CR0_SCR_Msk (0x000000ffUL << SSP0_CR0_SCR_Pos) /*!< SSP0 CR0: SCR Mask */ - -// ---------------------------------------- SSP0_CR1 -------------------------------------------- -#define SSP0_CR1_LBM_Pos 0 /*!< SSP0 CR1: LBM Position */ -#define SSP0_CR1_LBM_Msk (0x01UL << SSP0_CR1_LBM_Pos) /*!< SSP0 CR1: LBM Mask */ -#define SSP0_CR1_SSE_Pos 1 /*!< SSP0 CR1: SSE Position */ -#define SSP0_CR1_SSE_Msk (0x01UL << SSP0_CR1_SSE_Pos) /*!< SSP0 CR1: SSE Mask */ -#define SSP0_CR1_MS_Pos 2 /*!< SSP0 CR1: MS Position */ -#define SSP0_CR1_MS_Msk (0x01UL << SSP0_CR1_MS_Pos) /*!< SSP0 CR1: MS Mask */ -#define SSP0_CR1_SOD_Pos 3 /*!< SSP0 CR1: SOD Position */ -#define SSP0_CR1_SOD_Msk (0x01UL << SSP0_CR1_SOD_Pos) /*!< SSP0 CR1: SOD Mask */ - -// ----------------------------------------- SSP0_DR -------------------------------------------- -#define SSP0_DR_DATA_Pos 0 /*!< SSP0 DR: DATA Position */ -#define SSP0_DR_DATA_Msk (0x0000ffffUL << SSP0_DR_DATA_Pos) /*!< SSP0 DR: DATA Mask */ - -// ----------------------------------------- SSP0_SR -------------------------------------------- -#define SSP0_SR_TFE_Pos 0 /*!< SSP0 SR: TFE Position */ -#define SSP0_SR_TFE_Msk (0x01UL << SSP0_SR_TFE_Pos) /*!< SSP0 SR: TFE Mask */ -#define SSP0_SR_TNF_Pos 1 /*!< SSP0 SR: TNF Position */ -#define SSP0_SR_TNF_Msk (0x01UL << SSP0_SR_TNF_Pos) /*!< SSP0 SR: TNF Mask */ -#define SSP0_SR_RNE_Pos 2 /*!< SSP0 SR: RNE Position */ -#define SSP0_SR_RNE_Msk (0x01UL << SSP0_SR_RNE_Pos) /*!< SSP0 SR: RNE Mask */ -#define SSP0_SR_RFF_Pos 3 /*!< SSP0 SR: RFF Position */ -#define SSP0_SR_RFF_Msk (0x01UL << SSP0_SR_RFF_Pos) /*!< SSP0 SR: RFF Mask */ -#define SSP0_SR_BSY_Pos 4 /*!< SSP0 SR: BSY Position */ -#define SSP0_SR_BSY_Msk (0x01UL << SSP0_SR_BSY_Pos) /*!< SSP0 SR: BSY Mask */ - -// ---------------------------------------- SSP0_CPSR ------------------------------------------- -#define SSP0_CPSR_CPSDVSR_Pos 0 /*!< SSP0 CPSR: CPSDVSR Position */ -#define SSP0_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos) /*!< SSP0 CPSR: CPSDVSR Mask */ - -// ---------------------------------------- SSP0_IMSC ------------------------------------------- -#define SSP0_IMSC_RORIM_Pos 0 /*!< SSP0 IMSC: RORIM Position */ -#define SSP0_IMSC_RORIM_Msk (0x01UL << SSP0_IMSC_RORIM_Pos) /*!< SSP0 IMSC: RORIM Mask */ -#define SSP0_IMSC_RTIM_Pos 1 /*!< SSP0 IMSC: RTIM Position */ -#define SSP0_IMSC_RTIM_Msk (0x01UL << SSP0_IMSC_RTIM_Pos) /*!< SSP0 IMSC: RTIM Mask */ -#define SSP0_IMSC_RXIM_Pos 2 /*!< SSP0 IMSC: RXIM Position */ -#define SSP0_IMSC_RXIM_Msk (0x01UL << SSP0_IMSC_RXIM_Pos) /*!< SSP0 IMSC: RXIM Mask */ -#define SSP0_IMSC_TXIM_Pos 3 /*!< SSP0 IMSC: TXIM Position */ -#define SSP0_IMSC_TXIM_Msk (0x01UL << SSP0_IMSC_TXIM_Pos) /*!< SSP0 IMSC: TXIM Mask */ - -// ---------------------------------------- SSP0_RIS -------------------------------------------- -#define SSP0_RIS_RORRIS_Pos 0 /*!< SSP0 RIS: RORRIS Position */ -#define SSP0_RIS_RORRIS_Msk (0x01UL << SSP0_RIS_RORRIS_Pos) /*!< SSP0 RIS: RORRIS Mask */ -#define SSP0_RIS_RTRIS_Pos 1 /*!< SSP0 RIS: RTRIS Position */ -#define SSP0_RIS_RTRIS_Msk (0x01UL << SSP0_RIS_RTRIS_Pos) /*!< SSP0 RIS: RTRIS Mask */ -#define SSP0_RIS_RXRIS_Pos 2 /*!< SSP0 RIS: RXRIS Position */ -#define SSP0_RIS_RXRIS_Msk (0x01UL << SSP0_RIS_RXRIS_Pos) /*!< SSP0 RIS: RXRIS Mask */ -#define SSP0_RIS_TXRIS_Pos 3 /*!< SSP0 RIS: TXRIS Position */ -#define SSP0_RIS_TXRIS_Msk (0x01UL << SSP0_RIS_TXRIS_Pos) /*!< SSP0 RIS: TXRIS Mask */ - -// ---------------------------------------- SSP0_MIS -------------------------------------------- -#define SSP0_MIS_RORMIS_Pos 0 /*!< SSP0 MIS: RORMIS Position */ -#define SSP0_MIS_RORMIS_Msk (0x01UL << SSP0_MIS_RORMIS_Pos) /*!< SSP0 MIS: RORMIS Mask */ -#define SSP0_MIS_RTMIS_Pos 1 /*!< SSP0 MIS: RTMIS Position */ -#define SSP0_MIS_RTMIS_Msk (0x01UL << SSP0_MIS_RTMIS_Pos) /*!< SSP0 MIS: RTMIS Mask */ -#define SSP0_MIS_RXMIS_Pos 2 /*!< SSP0 MIS: RXMIS Position */ -#define SSP0_MIS_RXMIS_Msk (0x01UL << SSP0_MIS_RXMIS_Pos) /*!< SSP0 MIS: RXMIS Mask */ -#define SSP0_MIS_TXMIS_Pos 3 /*!< SSP0 MIS: TXMIS Position */ -#define SSP0_MIS_TXMIS_Msk (0x01UL << SSP0_MIS_TXMIS_Pos) /*!< SSP0 MIS: TXMIS Mask */ - -// ---------------------------------------- SSP0_ICR -------------------------------------------- -#define SSP0_ICR_RORIC_Pos 0 /*!< SSP0 ICR: RORIC Position */ -#define SSP0_ICR_RORIC_Msk (0x01UL << SSP0_ICR_RORIC_Pos) /*!< SSP0 ICR: RORIC Mask */ -#define SSP0_ICR_RTIC_Pos 1 /*!< SSP0 ICR: RTIC Position */ -#define SSP0_ICR_RTIC_Msk (0x01UL << SSP0_ICR_RTIC_Pos) /*!< SSP0 ICR: RTIC Mask */ - -// --------------------------------------- SSP0_DMACR ------------------------------------------- -#define SSP0_DMACR_RXDMAE_Pos 0 /*!< SSP0 DMACR: RXDMAE Position */ -#define SSP0_DMACR_RXDMAE_Msk (0x01UL << SSP0_DMACR_RXDMAE_Pos) /*!< SSP0 DMACR: RXDMAE Mask */ -#define SSP0_DMACR_TXDMAE_Pos 1 /*!< SSP0 DMACR: TXDMAE Position */ -#define SSP0_DMACR_TXDMAE_Msk (0x01UL << SSP0_DMACR_TXDMAE_Pos) /*!< SSP0 DMACR: TXDMAE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SSP1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- SSP1_CR0 -------------------------------------------- -#define SSP1_CR0_DSS_Pos 0 /*!< SSP1 CR0: DSS Position */ -#define SSP1_CR0_DSS_Msk (0x0fUL << SSP1_CR0_DSS_Pos) /*!< SSP1 CR0: DSS Mask */ -#define SSP1_CR0_FRF_Pos 4 /*!< SSP1 CR0: FRF Position */ -#define SSP1_CR0_FRF_Msk (0x03UL << SSP1_CR0_FRF_Pos) /*!< SSP1 CR0: FRF Mask */ -#define SSP1_CR0_CPOL_Pos 6 /*!< SSP1 CR0: CPOL Position */ -#define SSP1_CR0_CPOL_Msk (0x01UL << SSP1_CR0_CPOL_Pos) /*!< SSP1 CR0: CPOL Mask */ -#define SSP1_CR0_CPHA_Pos 7 /*!< SSP1 CR0: CPHA Position */ -#define SSP1_CR0_CPHA_Msk (0x01UL << SSP1_CR0_CPHA_Pos) /*!< SSP1 CR0: CPHA Mask */ -#define SSP1_CR0_SCR_Pos 8 /*!< SSP1 CR0: SCR Position */ -#define SSP1_CR0_SCR_Msk (0x000000ffUL << SSP1_CR0_SCR_Pos) /*!< SSP1 CR0: SCR Mask */ - -// ---------------------------------------- SSP1_CR1 -------------------------------------------- -#define SSP1_CR1_LBM_Pos 0 /*!< SSP1 CR1: LBM Position */ -#define SSP1_CR1_LBM_Msk (0x01UL << SSP1_CR1_LBM_Pos) /*!< SSP1 CR1: LBM Mask */ -#define SSP1_CR1_SSE_Pos 1 /*!< SSP1 CR1: SSE Position */ -#define SSP1_CR1_SSE_Msk (0x01UL << SSP1_CR1_SSE_Pos) /*!< SSP1 CR1: SSE Mask */ -#define SSP1_CR1_MS_Pos 2 /*!< SSP1 CR1: MS Position */ -#define SSP1_CR1_MS_Msk (0x01UL << SSP1_CR1_MS_Pos) /*!< SSP1 CR1: MS Mask */ -#define SSP1_CR1_SOD_Pos 3 /*!< SSP1 CR1: SOD Position */ -#define SSP1_CR1_SOD_Msk (0x01UL << SSP1_CR1_SOD_Pos) /*!< SSP1 CR1: SOD Mask */ - -// ----------------------------------------- SSP1_DR -------------------------------------------- -#define SSP1_DR_DATA_Pos 0 /*!< SSP1 DR: DATA Position */ -#define SSP1_DR_DATA_Msk (0x0000ffffUL << SSP1_DR_DATA_Pos) /*!< SSP1 DR: DATA Mask */ - -// ----------------------------------------- SSP1_SR -------------------------------------------- -#define SSP1_SR_TFE_Pos 0 /*!< SSP1 SR: TFE Position */ -#define SSP1_SR_TFE_Msk (0x01UL << SSP1_SR_TFE_Pos) /*!< SSP1 SR: TFE Mask */ -#define SSP1_SR_TNF_Pos 1 /*!< SSP1 SR: TNF Position */ -#define SSP1_SR_TNF_Msk (0x01UL << SSP1_SR_TNF_Pos) /*!< SSP1 SR: TNF Mask */ -#define SSP1_SR_RNE_Pos 2 /*!< SSP1 SR: RNE Position */ -#define SSP1_SR_RNE_Msk (0x01UL << SSP1_SR_RNE_Pos) /*!< SSP1 SR: RNE Mask */ -#define SSP1_SR_RFF_Pos 3 /*!< SSP1 SR: RFF Position */ -#define SSP1_SR_RFF_Msk (0x01UL << SSP1_SR_RFF_Pos) /*!< SSP1 SR: RFF Mask */ -#define SSP1_SR_BSY_Pos 4 /*!< SSP1 SR: BSY Position */ -#define SSP1_SR_BSY_Msk (0x01UL << SSP1_SR_BSY_Pos) /*!< SSP1 SR: BSY Mask */ - -// ---------------------------------------- SSP1_CPSR ------------------------------------------- -#define SSP1_CPSR_CPSDVSR_Pos 0 /*!< SSP1 CPSR: CPSDVSR Position */ -#define SSP1_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos) /*!< SSP1 CPSR: CPSDVSR Mask */ - -// ---------------------------------------- SSP1_IMSC ------------------------------------------- -#define SSP1_IMSC_RORIM_Pos 0 /*!< SSP1 IMSC: RORIM Position */ -#define SSP1_IMSC_RORIM_Msk (0x01UL << SSP1_IMSC_RORIM_Pos) /*!< SSP1 IMSC: RORIM Mask */ -#define SSP1_IMSC_RTIM_Pos 1 /*!< SSP1 IMSC: RTIM Position */ -#define SSP1_IMSC_RTIM_Msk (0x01UL << SSP1_IMSC_RTIM_Pos) /*!< SSP1 IMSC: RTIM Mask */ -#define SSP1_IMSC_RXIM_Pos 2 /*!< SSP1 IMSC: RXIM Position */ -#define SSP1_IMSC_RXIM_Msk (0x01UL << SSP1_IMSC_RXIM_Pos) /*!< SSP1 IMSC: RXIM Mask */ -#define SSP1_IMSC_TXIM_Pos 3 /*!< SSP1 IMSC: TXIM Position */ -#define SSP1_IMSC_TXIM_Msk (0x01UL << SSP1_IMSC_TXIM_Pos) /*!< SSP1 IMSC: TXIM Mask */ - -// ---------------------------------------- SSP1_RIS -------------------------------------------- -#define SSP1_RIS_RORRIS_Pos 0 /*!< SSP1 RIS: RORRIS Position */ -#define SSP1_RIS_RORRIS_Msk (0x01UL << SSP1_RIS_RORRIS_Pos) /*!< SSP1 RIS: RORRIS Mask */ -#define SSP1_RIS_RTRIS_Pos 1 /*!< SSP1 RIS: RTRIS Position */ -#define SSP1_RIS_RTRIS_Msk (0x01UL << SSP1_RIS_RTRIS_Pos) /*!< SSP1 RIS: RTRIS Mask */ -#define SSP1_RIS_RXRIS_Pos 2 /*!< SSP1 RIS: RXRIS Position */ -#define SSP1_RIS_RXRIS_Msk (0x01UL << SSP1_RIS_RXRIS_Pos) /*!< SSP1 RIS: RXRIS Mask */ -#define SSP1_RIS_TXRIS_Pos 3 /*!< SSP1 RIS: TXRIS Position */ -#define SSP1_RIS_TXRIS_Msk (0x01UL << SSP1_RIS_TXRIS_Pos) /*!< SSP1 RIS: TXRIS Mask */ - -// ---------------------------------------- SSP1_MIS -------------------------------------------- -#define SSP1_MIS_RORMIS_Pos 0 /*!< SSP1 MIS: RORMIS Position */ -#define SSP1_MIS_RORMIS_Msk (0x01UL << SSP1_MIS_RORMIS_Pos) /*!< SSP1 MIS: RORMIS Mask */ -#define SSP1_MIS_RTMIS_Pos 1 /*!< SSP1 MIS: RTMIS Position */ -#define SSP1_MIS_RTMIS_Msk (0x01UL << SSP1_MIS_RTMIS_Pos) /*!< SSP1 MIS: RTMIS Mask */ -#define SSP1_MIS_RXMIS_Pos 2 /*!< SSP1 MIS: RXMIS Position */ -#define SSP1_MIS_RXMIS_Msk (0x01UL << SSP1_MIS_RXMIS_Pos) /*!< SSP1 MIS: RXMIS Mask */ -#define SSP1_MIS_TXMIS_Pos 3 /*!< SSP1 MIS: TXMIS Position */ -#define SSP1_MIS_TXMIS_Msk (0x01UL << SSP1_MIS_TXMIS_Pos) /*!< SSP1 MIS: TXMIS Mask */ - -// ---------------------------------------- SSP1_ICR -------------------------------------------- -#define SSP1_ICR_RORIC_Pos 0 /*!< SSP1 ICR: RORIC Position */ -#define SSP1_ICR_RORIC_Msk (0x01UL << SSP1_ICR_RORIC_Pos) /*!< SSP1 ICR: RORIC Mask */ -#define SSP1_ICR_RTIC_Pos 1 /*!< SSP1 ICR: RTIC Position */ -#define SSP1_ICR_RTIC_Msk (0x01UL << SSP1_ICR_RTIC_Pos) /*!< SSP1 ICR: RTIC Mask */ - -// --------------------------------------- SSP1_DMACR ------------------------------------------- -#define SSP1_DMACR_RXDMAE_Pos 0 /*!< SSP1 DMACR: RXDMAE Position */ -#define SSP1_DMACR_RXDMAE_Msk (0x01UL << SSP1_DMACR_RXDMAE_Pos) /*!< SSP1 DMACR: RXDMAE Mask */ -#define SSP1_DMACR_TXDMAE_Pos 1 /*!< SSP1 DMACR: TXDMAE Position */ -#define SSP1_DMACR_TXDMAE_Msk (0x01UL << SSP1_DMACR_TXDMAE_Pos) /*!< SSP1 DMACR: TXDMAE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMER0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- TIMER0_IR ------------------------------------------- -#define TIMER0_IR_MR0INT_Pos 0 /*!< TIMER0 IR: MR0INT Position */ -#define TIMER0_IR_MR0INT_Msk (0x01UL << TIMER0_IR_MR0INT_Pos) /*!< TIMER0 IR: MR0INT Mask */ -#define TIMER0_IR_MR1INT_Pos 1 /*!< TIMER0 IR: MR1INT Position */ -#define TIMER0_IR_MR1INT_Msk (0x01UL << TIMER0_IR_MR1INT_Pos) /*!< TIMER0 IR: MR1INT Mask */ -#define TIMER0_IR_MR2INT_Pos 2 /*!< TIMER0 IR: MR2INT Position */ -#define TIMER0_IR_MR2INT_Msk (0x01UL << TIMER0_IR_MR2INT_Pos) /*!< TIMER0 IR: MR2INT Mask */ -#define TIMER0_IR_MR3INT_Pos 3 /*!< TIMER0 IR: MR3INT Position */ -#define TIMER0_IR_MR3INT_Msk (0x01UL << TIMER0_IR_MR3INT_Pos) /*!< TIMER0 IR: MR3INT Mask */ -#define TIMER0_IR_CR0INT_Pos 4 /*!< TIMER0 IR: CR0INT Position */ -#define TIMER0_IR_CR0INT_Msk (0x01UL << TIMER0_IR_CR0INT_Pos) /*!< TIMER0 IR: CR0INT Mask */ -#define TIMER0_IR_CR1INT_Pos 5 /*!< TIMER0 IR: CR1INT Position */ -#define TIMER0_IR_CR1INT_Msk (0x01UL << TIMER0_IR_CR1INT_Pos) /*!< TIMER0 IR: CR1INT Mask */ -#define TIMER0_IR_CR2INT_Pos 6 /*!< TIMER0 IR: CR2INT Position */ -#define TIMER0_IR_CR2INT_Msk (0x01UL << TIMER0_IR_CR2INT_Pos) /*!< TIMER0 IR: CR2INT Mask */ -#define TIMER0_IR_CR3INT_Pos 7 /*!< TIMER0 IR: CR3INT Position */ -#define TIMER0_IR_CR3INT_Msk (0x01UL << TIMER0_IR_CR3INT_Pos) /*!< TIMER0 IR: CR3INT Mask */ - -// --------------------------------------- TIMER0_TCR ------------------------------------------- -#define TIMER0_TCR_CEN_Pos 0 /*!< TIMER0 TCR: CEN Position */ -#define TIMER0_TCR_CEN_Msk (0x01UL << TIMER0_TCR_CEN_Pos) /*!< TIMER0 TCR: CEN Mask */ -#define TIMER0_TCR_CRST_Pos 1 /*!< TIMER0 TCR: CRST Position */ -#define TIMER0_TCR_CRST_Msk (0x01UL << TIMER0_TCR_CRST_Pos) /*!< TIMER0 TCR: CRST Mask */ - -// ---------------------------------------- TIMER0_TC ------------------------------------------- -#define TIMER0_TC_TC_Pos 0 /*!< TIMER0 TC: TC Position */ -#define TIMER0_TC_TC_Msk (0xffffffffUL << TIMER0_TC_TC_Pos) /*!< TIMER0 TC: TC Mask */ - -// ---------------------------------------- TIMER0_PR ------------------------------------------- -#define TIMER0_PR_PM_Pos 0 /*!< TIMER0 PR: PM Position */ -#define TIMER0_PR_PM_Msk (0xffffffffUL << TIMER0_PR_PM_Pos) /*!< TIMER0 PR: PM Mask */ - -// ---------------------------------------- TIMER0_PC ------------------------------------------- -#define TIMER0_PC_PC_Pos 0 /*!< TIMER0 PC: PC Position */ -#define TIMER0_PC_PC_Msk (0xffffffffUL << TIMER0_PC_PC_Pos) /*!< TIMER0 PC: PC Mask */ - -// --------------------------------------- TIMER0_MCR ------------------------------------------- -#define TIMER0_MCR_MR0I_Pos 0 /*!< TIMER0 MCR: MR0I Position */ -#define TIMER0_MCR_MR0I_Msk (0x01UL << TIMER0_MCR_MR0I_Pos) /*!< TIMER0 MCR: MR0I Mask */ -#define TIMER0_MCR_MR0R_Pos 1 /*!< TIMER0 MCR: MR0R Position */ -#define TIMER0_MCR_MR0R_Msk (0x01UL << TIMER0_MCR_MR0R_Pos) /*!< TIMER0 MCR: MR0R Mask */ -#define TIMER0_MCR_MR0S_Pos 2 /*!< TIMER0 MCR: MR0S Position */ -#define TIMER0_MCR_MR0S_Msk (0x01UL << TIMER0_MCR_MR0S_Pos) /*!< TIMER0 MCR: MR0S Mask */ -#define TIMER0_MCR_MR1I_Pos 3 /*!< TIMER0 MCR: MR1I Position */ -#define TIMER0_MCR_MR1I_Msk (0x01UL << TIMER0_MCR_MR1I_Pos) /*!< TIMER0 MCR: MR1I Mask */ -#define TIMER0_MCR_MR1R_Pos 4 /*!< TIMER0 MCR: MR1R Position */ -#define TIMER0_MCR_MR1R_Msk (0x01UL << TIMER0_MCR_MR1R_Pos) /*!< TIMER0 MCR: MR1R Mask */ -#define TIMER0_MCR_MR1S_Pos 5 /*!< TIMER0 MCR: MR1S Position */ -#define TIMER0_MCR_MR1S_Msk (0x01UL << TIMER0_MCR_MR1S_Pos) /*!< TIMER0 MCR: MR1S Mask */ -#define TIMER0_MCR_MR2I_Pos 6 /*!< TIMER0 MCR: MR2I Position */ -#define TIMER0_MCR_MR2I_Msk (0x01UL << TIMER0_MCR_MR2I_Pos) /*!< TIMER0 MCR: MR2I Mask */ -#define TIMER0_MCR_MR2R_Pos 7 /*!< TIMER0 MCR: MR2R Position */ -#define TIMER0_MCR_MR2R_Msk (0x01UL << TIMER0_MCR_MR2R_Pos) /*!< TIMER0 MCR: MR2R Mask */ -#define TIMER0_MCR_MR2S_Pos 8 /*!< TIMER0 MCR: MR2S Position */ -#define TIMER0_MCR_MR2S_Msk (0x01UL << TIMER0_MCR_MR2S_Pos) /*!< TIMER0 MCR: MR2S Mask */ -#define TIMER0_MCR_MR3I_Pos 9 /*!< TIMER0 MCR: MR3I Position */ -#define TIMER0_MCR_MR3I_Msk (0x01UL << TIMER0_MCR_MR3I_Pos) /*!< TIMER0 MCR: MR3I Mask */ -#define TIMER0_MCR_MR3R_Pos 10 /*!< TIMER0 MCR: MR3R Position */ -#define TIMER0_MCR_MR3R_Msk (0x01UL << TIMER0_MCR_MR3R_Pos) /*!< TIMER0 MCR: MR3R Mask */ -#define TIMER0_MCR_MR3S_Pos 11 /*!< TIMER0 MCR: MR3S Position */ -#define TIMER0_MCR_MR3S_Msk (0x01UL << TIMER0_MCR_MR3S_Pos) /*!< TIMER0 MCR: MR3S Mask */ - -// --------------------------------------- TIMER0_MR0 ------------------------------------------- -#define TIMER0_MR0_MATCH_Pos 0 /*!< TIMER0 MR0: MATCH Position */ -#define TIMER0_MR0_MATCH_Msk (0xffffffffUL << TIMER0_MR0_MATCH_Pos) /*!< TIMER0 MR0: MATCH Mask */ - -// --------------------------------------- TIMER0_MR1 ------------------------------------------- -#define TIMER0_MR1_MATCH_Pos 0 /*!< TIMER0 MR1: MATCH Position */ -#define TIMER0_MR1_MATCH_Msk (0xffffffffUL << TIMER0_MR1_MATCH_Pos) /*!< TIMER0 MR1: MATCH Mask */ - -// --------------------------------------- TIMER0_MR2 ------------------------------------------- -#define TIMER0_MR2_MATCH_Pos 0 /*!< TIMER0 MR2: MATCH Position */ -#define TIMER0_MR2_MATCH_Msk (0xffffffffUL << TIMER0_MR2_MATCH_Pos) /*!< TIMER0 MR2: MATCH Mask */ - -// --------------------------------------- TIMER0_MR3 ------------------------------------------- -#define TIMER0_MR3_MATCH_Pos 0 /*!< TIMER0 MR3: MATCH Position */ -#define TIMER0_MR3_MATCH_Msk (0xffffffffUL << TIMER0_MR3_MATCH_Pos) /*!< TIMER0 MR3: MATCH Mask */ - -// --------------------------------------- TIMER0_CCR ------------------------------------------- -#define TIMER0_CCR_CAP0RE_Pos 0 /*!< TIMER0 CCR: CAP0RE Position */ -#define TIMER0_CCR_CAP0RE_Msk (0x01UL << TIMER0_CCR_CAP0RE_Pos) /*!< TIMER0 CCR: CAP0RE Mask */ -#define TIMER0_CCR_CAP0FE_Pos 1 /*!< TIMER0 CCR: CAP0FE Position */ -#define TIMER0_CCR_CAP0FE_Msk (0x01UL << TIMER0_CCR_CAP0FE_Pos) /*!< TIMER0 CCR: CAP0FE Mask */ -#define TIMER0_CCR_CAP0I_Pos 2 /*!< TIMER0 CCR: CAP0I Position */ -#define TIMER0_CCR_CAP0I_Msk (0x01UL << TIMER0_CCR_CAP0I_Pos) /*!< TIMER0 CCR: CAP0I Mask */ -#define TIMER0_CCR_CAP1RE_Pos 3 /*!< TIMER0 CCR: CAP1RE Position */ -#define TIMER0_CCR_CAP1RE_Msk (0x01UL << TIMER0_CCR_CAP1RE_Pos) /*!< TIMER0 CCR: CAP1RE Mask */ -#define TIMER0_CCR_CAP1FE_Pos 4 /*!< TIMER0 CCR: CAP1FE Position */ -#define TIMER0_CCR_CAP1FE_Msk (0x01UL << TIMER0_CCR_CAP1FE_Pos) /*!< TIMER0 CCR: CAP1FE Mask */ -#define TIMER0_CCR_CAP1I_Pos 5 /*!< TIMER0 CCR: CAP1I Position */ -#define TIMER0_CCR_CAP1I_Msk (0x01UL << TIMER0_CCR_CAP1I_Pos) /*!< TIMER0 CCR: CAP1I Mask */ -#define TIMER0_CCR_CAP2RE_Pos 6 /*!< TIMER0 CCR: CAP2RE Position */ -#define TIMER0_CCR_CAP2RE_Msk (0x01UL << TIMER0_CCR_CAP2RE_Pos) /*!< TIMER0 CCR: CAP2RE Mask */ -#define TIMER0_CCR_CAP2FE_Pos 7 /*!< TIMER0 CCR: CAP2FE Position */ -#define TIMER0_CCR_CAP2FE_Msk (0x01UL << TIMER0_CCR_CAP2FE_Pos) /*!< TIMER0 CCR: CAP2FE Mask */ -#define TIMER0_CCR_CAP2I_Pos 8 /*!< TIMER0 CCR: CAP2I Position */ -#define TIMER0_CCR_CAP2I_Msk (0x01UL << TIMER0_CCR_CAP2I_Pos) /*!< TIMER0 CCR: CAP2I Mask */ -#define TIMER0_CCR_CAP3RE_Pos 9 /*!< TIMER0 CCR: CAP3RE Position */ -#define TIMER0_CCR_CAP3RE_Msk (0x01UL << TIMER0_CCR_CAP3RE_Pos) /*!< TIMER0 CCR: CAP3RE Mask */ -#define TIMER0_CCR_CAP3FE_Pos 10 /*!< TIMER0 CCR: CAP3FE Position */ -#define TIMER0_CCR_CAP3FE_Msk (0x01UL << TIMER0_CCR_CAP3FE_Pos) /*!< TIMER0 CCR: CAP3FE Mask */ -#define TIMER0_CCR_CAP3I_Pos 11 /*!< TIMER0 CCR: CAP3I Position */ -#define TIMER0_CCR_CAP3I_Msk (0x01UL << TIMER0_CCR_CAP3I_Pos) /*!< TIMER0 CCR: CAP3I Mask */ - -// --------------------------------------- TIMER0_CR0 ------------------------------------------- -#define TIMER0_CR0_CAP_Pos 0 /*!< TIMER0 CR0: CAP Position */ -#define TIMER0_CR0_CAP_Msk (0xffffffffUL << TIMER0_CR0_CAP_Pos) /*!< TIMER0 CR0: CAP Mask */ - -// --------------------------------------- TIMER0_CR1 ------------------------------------------- -#define TIMER0_CR1_CAP_Pos 0 /*!< TIMER0 CR1: CAP Position */ -#define TIMER0_CR1_CAP_Msk (0xffffffffUL << TIMER0_CR1_CAP_Pos) /*!< TIMER0 CR1: CAP Mask */ - -// --------------------------------------- TIMER0_CR2 ------------------------------------------- -#define TIMER0_CR2_CAP_Pos 0 /*!< TIMER0 CR2: CAP Position */ -#define TIMER0_CR2_CAP_Msk (0xffffffffUL << TIMER0_CR2_CAP_Pos) /*!< TIMER0 CR2: CAP Mask */ - -// --------------------------------------- TIMER0_CR3 ------------------------------------------- -#define TIMER0_CR3_CAP_Pos 0 /*!< TIMER0 CR3: CAP Position */ -#define TIMER0_CR3_CAP_Msk (0xffffffffUL << TIMER0_CR3_CAP_Pos) /*!< TIMER0 CR3: CAP Mask */ - -// --------------------------------------- TIMER0_EMR ------------------------------------------- -#define TIMER0_EMR_EM0_Pos 0 /*!< TIMER0 EMR: EM0 Position */ -#define TIMER0_EMR_EM0_Msk (0x01UL << TIMER0_EMR_EM0_Pos) /*!< TIMER0 EMR: EM0 Mask */ -#define TIMER0_EMR_EM1_Pos 1 /*!< TIMER0 EMR: EM1 Position */ -#define TIMER0_EMR_EM1_Msk (0x01UL << TIMER0_EMR_EM1_Pos) /*!< TIMER0 EMR: EM1 Mask */ -#define TIMER0_EMR_EM2_Pos 2 /*!< TIMER0 EMR: EM2 Position */ -#define TIMER0_EMR_EM2_Msk (0x01UL << TIMER0_EMR_EM2_Pos) /*!< TIMER0 EMR: EM2 Mask */ -#define TIMER0_EMR_EM3_Pos 3 /*!< TIMER0 EMR: EM3 Position */ -#define TIMER0_EMR_EM3_Msk (0x01UL << TIMER0_EMR_EM3_Pos) /*!< TIMER0 EMR: EM3 Mask */ -#define TIMER0_EMR_EMC0_Pos 4 /*!< TIMER0 EMR: EMC0 Position */ -#define TIMER0_EMR_EMC0_Msk (0x03UL << TIMER0_EMR_EMC0_Pos) /*!< TIMER0 EMR: EMC0 Mask */ -#define TIMER0_EMR_EMC1_Pos 6 /*!< TIMER0 EMR: EMC1 Position */ -#define TIMER0_EMR_EMC1_Msk (0x03UL << TIMER0_EMR_EMC1_Pos) /*!< TIMER0 EMR: EMC1 Mask */ -#define TIMER0_EMR_EMC2_Pos 8 /*!< TIMER0 EMR: EMC2 Position */ -#define TIMER0_EMR_EMC2_Msk (0x03UL << TIMER0_EMR_EMC2_Pos) /*!< TIMER0 EMR: EMC2 Mask */ -#define TIMER0_EMR_EMC3_Pos 10 /*!< TIMER0 EMR: EMC3 Position */ -#define TIMER0_EMR_EMC3_Msk (0x03UL << TIMER0_EMR_EMC3_Pos) /*!< TIMER0 EMR: EMC3 Mask */ - -// --------------------------------------- TIMER0_CTCR ------------------------------------------ -#define TIMER0_CTCR_CTMODE_Pos 0 /*!< TIMER0 CTCR: CTMODE Position */ -#define TIMER0_CTCR_CTMODE_Msk (0x03UL << TIMER0_CTCR_CTMODE_Pos) /*!< TIMER0 CTCR: CTMODE Mask */ -#define TIMER0_CTCR_CINSEL_Pos 2 /*!< TIMER0 CTCR: CINSEL Position */ -#define TIMER0_CTCR_CINSEL_Msk (0x03UL << TIMER0_CTCR_CINSEL_Pos) /*!< TIMER0 CTCR: CINSEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMER1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- TIMER1_IR ------------------------------------------- -#define TIMER1_IR_MR0INT_Pos 0 /*!< TIMER1 IR: MR0INT Position */ -#define TIMER1_IR_MR0INT_Msk (0x01UL << TIMER1_IR_MR0INT_Pos) /*!< TIMER1 IR: MR0INT Mask */ -#define TIMER1_IR_MR1INT_Pos 1 /*!< TIMER1 IR: MR1INT Position */ -#define TIMER1_IR_MR1INT_Msk (0x01UL << TIMER1_IR_MR1INT_Pos) /*!< TIMER1 IR: MR1INT Mask */ -#define TIMER1_IR_MR2INT_Pos 2 /*!< TIMER1 IR: MR2INT Position */ -#define TIMER1_IR_MR2INT_Msk (0x01UL << TIMER1_IR_MR2INT_Pos) /*!< TIMER1 IR: MR2INT Mask */ -#define TIMER1_IR_MR3INT_Pos 3 /*!< TIMER1 IR: MR3INT Position */ -#define TIMER1_IR_MR3INT_Msk (0x01UL << TIMER1_IR_MR3INT_Pos) /*!< TIMER1 IR: MR3INT Mask */ -#define TIMER1_IR_CR0INT_Pos 4 /*!< TIMER1 IR: CR0INT Position */ -#define TIMER1_IR_CR0INT_Msk (0x01UL << TIMER1_IR_CR0INT_Pos) /*!< TIMER1 IR: CR0INT Mask */ -#define TIMER1_IR_CR1INT_Pos 5 /*!< TIMER1 IR: CR1INT Position */ -#define TIMER1_IR_CR1INT_Msk (0x01UL << TIMER1_IR_CR1INT_Pos) /*!< TIMER1 IR: CR1INT Mask */ -#define TIMER1_IR_CR2INT_Pos 6 /*!< TIMER1 IR: CR2INT Position */ -#define TIMER1_IR_CR2INT_Msk (0x01UL << TIMER1_IR_CR2INT_Pos) /*!< TIMER1 IR: CR2INT Mask */ -#define TIMER1_IR_CR3INT_Pos 7 /*!< TIMER1 IR: CR3INT Position */ -#define TIMER1_IR_CR3INT_Msk (0x01UL << TIMER1_IR_CR3INT_Pos) /*!< TIMER1 IR: CR3INT Mask */ - -// --------------------------------------- TIMER1_TCR ------------------------------------------- -#define TIMER1_TCR_CEN_Pos 0 /*!< TIMER1 TCR: CEN Position */ -#define TIMER1_TCR_CEN_Msk (0x01UL << TIMER1_TCR_CEN_Pos) /*!< TIMER1 TCR: CEN Mask */ -#define TIMER1_TCR_CRST_Pos 1 /*!< TIMER1 TCR: CRST Position */ -#define TIMER1_TCR_CRST_Msk (0x01UL << TIMER1_TCR_CRST_Pos) /*!< TIMER1 TCR: CRST Mask */ - -// ---------------------------------------- TIMER1_TC ------------------------------------------- -#define TIMER1_TC_TC_Pos 0 /*!< TIMER1 TC: TC Position */ -#define TIMER1_TC_TC_Msk (0xffffffffUL << TIMER1_TC_TC_Pos) /*!< TIMER1 TC: TC Mask */ - -// ---------------------------------------- TIMER1_PR ------------------------------------------- -#define TIMER1_PR_PM_Pos 0 /*!< TIMER1 PR: PM Position */ -#define TIMER1_PR_PM_Msk (0xffffffffUL << TIMER1_PR_PM_Pos) /*!< TIMER1 PR: PM Mask */ - -// ---------------------------------------- TIMER1_PC ------------------------------------------- -#define TIMER1_PC_PC_Pos 0 /*!< TIMER1 PC: PC Position */ -#define TIMER1_PC_PC_Msk (0xffffffffUL << TIMER1_PC_PC_Pos) /*!< TIMER1 PC: PC Mask */ - -// --------------------------------------- TIMER1_MCR ------------------------------------------- -#define TIMER1_MCR_MR0I_Pos 0 /*!< TIMER1 MCR: MR0I Position */ -#define TIMER1_MCR_MR0I_Msk (0x01UL << TIMER1_MCR_MR0I_Pos) /*!< TIMER1 MCR: MR0I Mask */ -#define TIMER1_MCR_MR0R_Pos 1 /*!< TIMER1 MCR: MR0R Position */ -#define TIMER1_MCR_MR0R_Msk (0x01UL << TIMER1_MCR_MR0R_Pos) /*!< TIMER1 MCR: MR0R Mask */ -#define TIMER1_MCR_MR0S_Pos 2 /*!< TIMER1 MCR: MR0S Position */ -#define TIMER1_MCR_MR0S_Msk (0x01UL << TIMER1_MCR_MR0S_Pos) /*!< TIMER1 MCR: MR0S Mask */ -#define TIMER1_MCR_MR1I_Pos 3 /*!< TIMER1 MCR: MR1I Position */ -#define TIMER1_MCR_MR1I_Msk (0x01UL << TIMER1_MCR_MR1I_Pos) /*!< TIMER1 MCR: MR1I Mask */ -#define TIMER1_MCR_MR1R_Pos 4 /*!< TIMER1 MCR: MR1R Position */ -#define TIMER1_MCR_MR1R_Msk (0x01UL << TIMER1_MCR_MR1R_Pos) /*!< TIMER1 MCR: MR1R Mask */ -#define TIMER1_MCR_MR1S_Pos 5 /*!< TIMER1 MCR: MR1S Position */ -#define TIMER1_MCR_MR1S_Msk (0x01UL << TIMER1_MCR_MR1S_Pos) /*!< TIMER1 MCR: MR1S Mask */ -#define TIMER1_MCR_MR2I_Pos 6 /*!< TIMER1 MCR: MR2I Position */ -#define TIMER1_MCR_MR2I_Msk (0x01UL << TIMER1_MCR_MR2I_Pos) /*!< TIMER1 MCR: MR2I Mask */ -#define TIMER1_MCR_MR2R_Pos 7 /*!< TIMER1 MCR: MR2R Position */ -#define TIMER1_MCR_MR2R_Msk (0x01UL << TIMER1_MCR_MR2R_Pos) /*!< TIMER1 MCR: MR2R Mask */ -#define TIMER1_MCR_MR2S_Pos 8 /*!< TIMER1 MCR: MR2S Position */ -#define TIMER1_MCR_MR2S_Msk (0x01UL << TIMER1_MCR_MR2S_Pos) /*!< TIMER1 MCR: MR2S Mask */ -#define TIMER1_MCR_MR3I_Pos 9 /*!< TIMER1 MCR: MR3I Position */ -#define TIMER1_MCR_MR3I_Msk (0x01UL << TIMER1_MCR_MR3I_Pos) /*!< TIMER1 MCR: MR3I Mask */ -#define TIMER1_MCR_MR3R_Pos 10 /*!< TIMER1 MCR: MR3R Position */ -#define TIMER1_MCR_MR3R_Msk (0x01UL << TIMER1_MCR_MR3R_Pos) /*!< TIMER1 MCR: MR3R Mask */ -#define TIMER1_MCR_MR3S_Pos 11 /*!< TIMER1 MCR: MR3S Position */ -#define TIMER1_MCR_MR3S_Msk (0x01UL << TIMER1_MCR_MR3S_Pos) /*!< TIMER1 MCR: MR3S Mask */ - -// --------------------------------------- TIMER1_MR0 ------------------------------------------- -#define TIMER1_MR0_MATCH_Pos 0 /*!< TIMER1 MR0: MATCH Position */ -#define TIMER1_MR0_MATCH_Msk (0xffffffffUL << TIMER1_MR0_MATCH_Pos) /*!< TIMER1 MR0: MATCH Mask */ - -// --------------------------------------- TIMER1_MR1 ------------------------------------------- -#define TIMER1_MR1_MATCH_Pos 0 /*!< TIMER1 MR1: MATCH Position */ -#define TIMER1_MR1_MATCH_Msk (0xffffffffUL << TIMER1_MR1_MATCH_Pos) /*!< TIMER1 MR1: MATCH Mask */ - -// --------------------------------------- TIMER1_MR2 ------------------------------------------- -#define TIMER1_MR2_MATCH_Pos 0 /*!< TIMER1 MR2: MATCH Position */ -#define TIMER1_MR2_MATCH_Msk (0xffffffffUL << TIMER1_MR2_MATCH_Pos) /*!< TIMER1 MR2: MATCH Mask */ - -// --------------------------------------- TIMER1_MR3 ------------------------------------------- -#define TIMER1_MR3_MATCH_Pos 0 /*!< TIMER1 MR3: MATCH Position */ -#define TIMER1_MR3_MATCH_Msk (0xffffffffUL << TIMER1_MR3_MATCH_Pos) /*!< TIMER1 MR3: MATCH Mask */ - -// --------------------------------------- TIMER1_CCR ------------------------------------------- -#define TIMER1_CCR_CAP0RE_Pos 0 /*!< TIMER1 CCR: CAP0RE Position */ -#define TIMER1_CCR_CAP0RE_Msk (0x01UL << TIMER1_CCR_CAP0RE_Pos) /*!< TIMER1 CCR: CAP0RE Mask */ -#define TIMER1_CCR_CAP0FE_Pos 1 /*!< TIMER1 CCR: CAP0FE Position */ -#define TIMER1_CCR_CAP0FE_Msk (0x01UL << TIMER1_CCR_CAP0FE_Pos) /*!< TIMER1 CCR: CAP0FE Mask */ -#define TIMER1_CCR_CAP0I_Pos 2 /*!< TIMER1 CCR: CAP0I Position */ -#define TIMER1_CCR_CAP0I_Msk (0x01UL << TIMER1_CCR_CAP0I_Pos) /*!< TIMER1 CCR: CAP0I Mask */ -#define TIMER1_CCR_CAP1RE_Pos 3 /*!< TIMER1 CCR: CAP1RE Position */ -#define TIMER1_CCR_CAP1RE_Msk (0x01UL << TIMER1_CCR_CAP1RE_Pos) /*!< TIMER1 CCR: CAP1RE Mask */ -#define TIMER1_CCR_CAP1FE_Pos 4 /*!< TIMER1 CCR: CAP1FE Position */ -#define TIMER1_CCR_CAP1FE_Msk (0x01UL << TIMER1_CCR_CAP1FE_Pos) /*!< TIMER1 CCR: CAP1FE Mask */ -#define TIMER1_CCR_CAP1I_Pos 5 /*!< TIMER1 CCR: CAP1I Position */ -#define TIMER1_CCR_CAP1I_Msk (0x01UL << TIMER1_CCR_CAP1I_Pos) /*!< TIMER1 CCR: CAP1I Mask */ -#define TIMER1_CCR_CAP2RE_Pos 6 /*!< TIMER1 CCR: CAP2RE Position */ -#define TIMER1_CCR_CAP2RE_Msk (0x01UL << TIMER1_CCR_CAP2RE_Pos) /*!< TIMER1 CCR: CAP2RE Mask */ -#define TIMER1_CCR_CAP2FE_Pos 7 /*!< TIMER1 CCR: CAP2FE Position */ -#define TIMER1_CCR_CAP2FE_Msk (0x01UL << TIMER1_CCR_CAP2FE_Pos) /*!< TIMER1 CCR: CAP2FE Mask */ -#define TIMER1_CCR_CAP2I_Pos 8 /*!< TIMER1 CCR: CAP2I Position */ -#define TIMER1_CCR_CAP2I_Msk (0x01UL << TIMER1_CCR_CAP2I_Pos) /*!< TIMER1 CCR: CAP2I Mask */ -#define TIMER1_CCR_CAP3RE_Pos 9 /*!< TIMER1 CCR: CAP3RE Position */ -#define TIMER1_CCR_CAP3RE_Msk (0x01UL << TIMER1_CCR_CAP3RE_Pos) /*!< TIMER1 CCR: CAP3RE Mask */ -#define TIMER1_CCR_CAP3FE_Pos 10 /*!< TIMER1 CCR: CAP3FE Position */ -#define TIMER1_CCR_CAP3FE_Msk (0x01UL << TIMER1_CCR_CAP3FE_Pos) /*!< TIMER1 CCR: CAP3FE Mask */ -#define TIMER1_CCR_CAP3I_Pos 11 /*!< TIMER1 CCR: CAP3I Position */ -#define TIMER1_CCR_CAP3I_Msk (0x01UL << TIMER1_CCR_CAP3I_Pos) /*!< TIMER1 CCR: CAP3I Mask */ - -// --------------------------------------- TIMER1_CR0 ------------------------------------------- -#define TIMER1_CR0_CAP_Pos 0 /*!< TIMER1 CR0: CAP Position */ -#define TIMER1_CR0_CAP_Msk (0xffffffffUL << TIMER1_CR0_CAP_Pos) /*!< TIMER1 CR0: CAP Mask */ - -// --------------------------------------- TIMER1_CR1 ------------------------------------------- -#define TIMER1_CR1_CAP_Pos 0 /*!< TIMER1 CR1: CAP Position */ -#define TIMER1_CR1_CAP_Msk (0xffffffffUL << TIMER1_CR1_CAP_Pos) /*!< TIMER1 CR1: CAP Mask */ - -// --------------------------------------- TIMER1_CR2 ------------------------------------------- -#define TIMER1_CR2_CAP_Pos 0 /*!< TIMER1 CR2: CAP Position */ -#define TIMER1_CR2_CAP_Msk (0xffffffffUL << TIMER1_CR2_CAP_Pos) /*!< TIMER1 CR2: CAP Mask */ - -// --------------------------------------- TIMER1_CR3 ------------------------------------------- -#define TIMER1_CR3_CAP_Pos 0 /*!< TIMER1 CR3: CAP Position */ -#define TIMER1_CR3_CAP_Msk (0xffffffffUL << TIMER1_CR3_CAP_Pos) /*!< TIMER1 CR3: CAP Mask */ - -// --------------------------------------- TIMER1_EMR ------------------------------------------- -#define TIMER1_EMR_EM0_Pos 0 /*!< TIMER1 EMR: EM0 Position */ -#define TIMER1_EMR_EM0_Msk (0x01UL << TIMER1_EMR_EM0_Pos) /*!< TIMER1 EMR: EM0 Mask */ -#define TIMER1_EMR_EM1_Pos 1 /*!< TIMER1 EMR: EM1 Position */ -#define TIMER1_EMR_EM1_Msk (0x01UL << TIMER1_EMR_EM1_Pos) /*!< TIMER1 EMR: EM1 Mask */ -#define TIMER1_EMR_EM2_Pos 2 /*!< TIMER1 EMR: EM2 Position */ -#define TIMER1_EMR_EM2_Msk (0x01UL << TIMER1_EMR_EM2_Pos) /*!< TIMER1 EMR: EM2 Mask */ -#define TIMER1_EMR_EM3_Pos 3 /*!< TIMER1 EMR: EM3 Position */ -#define TIMER1_EMR_EM3_Msk (0x01UL << TIMER1_EMR_EM3_Pos) /*!< TIMER1 EMR: EM3 Mask */ -#define TIMER1_EMR_EMC0_Pos 4 /*!< TIMER1 EMR: EMC0 Position */ -#define TIMER1_EMR_EMC0_Msk (0x03UL << TIMER1_EMR_EMC0_Pos) /*!< TIMER1 EMR: EMC0 Mask */ -#define TIMER1_EMR_EMC1_Pos 6 /*!< TIMER1 EMR: EMC1 Position */ -#define TIMER1_EMR_EMC1_Msk (0x03UL << TIMER1_EMR_EMC1_Pos) /*!< TIMER1 EMR: EMC1 Mask */ -#define TIMER1_EMR_EMC2_Pos 8 /*!< TIMER1 EMR: EMC2 Position */ -#define TIMER1_EMR_EMC2_Msk (0x03UL << TIMER1_EMR_EMC2_Pos) /*!< TIMER1 EMR: EMC2 Mask */ -#define TIMER1_EMR_EMC3_Pos 10 /*!< TIMER1 EMR: EMC3 Position */ -#define TIMER1_EMR_EMC3_Msk (0x03UL << TIMER1_EMR_EMC3_Pos) /*!< TIMER1 EMR: EMC3 Mask */ - -// --------------------------------------- TIMER1_CTCR ------------------------------------------ -#define TIMER1_CTCR_CTMODE_Pos 0 /*!< TIMER1 CTCR: CTMODE Position */ -#define TIMER1_CTCR_CTMODE_Msk (0x03UL << TIMER1_CTCR_CTMODE_Pos) /*!< TIMER1 CTCR: CTMODE Mask */ -#define TIMER1_CTCR_CINSEL_Pos 2 /*!< TIMER1 CTCR: CINSEL Position */ -#define TIMER1_CTCR_CINSEL_Msk (0x03UL << TIMER1_CTCR_CINSEL_Pos) /*!< TIMER1 CTCR: CINSEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMER2 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- TIMER2_IR ------------------------------------------- -#define TIMER2_IR_MR0INT_Pos 0 /*!< TIMER2 IR: MR0INT Position */ -#define TIMER2_IR_MR0INT_Msk (0x01UL << TIMER2_IR_MR0INT_Pos) /*!< TIMER2 IR: MR0INT Mask */ -#define TIMER2_IR_MR1INT_Pos 1 /*!< TIMER2 IR: MR1INT Position */ -#define TIMER2_IR_MR1INT_Msk (0x01UL << TIMER2_IR_MR1INT_Pos) /*!< TIMER2 IR: MR1INT Mask */ -#define TIMER2_IR_MR2INT_Pos 2 /*!< TIMER2 IR: MR2INT Position */ -#define TIMER2_IR_MR2INT_Msk (0x01UL << TIMER2_IR_MR2INT_Pos) /*!< TIMER2 IR: MR2INT Mask */ -#define TIMER2_IR_MR3INT_Pos 3 /*!< TIMER2 IR: MR3INT Position */ -#define TIMER2_IR_MR3INT_Msk (0x01UL << TIMER2_IR_MR3INT_Pos) /*!< TIMER2 IR: MR3INT Mask */ -#define TIMER2_IR_CR0INT_Pos 4 /*!< TIMER2 IR: CR0INT Position */ -#define TIMER2_IR_CR0INT_Msk (0x01UL << TIMER2_IR_CR0INT_Pos) /*!< TIMER2 IR: CR0INT Mask */ -#define TIMER2_IR_CR1INT_Pos 5 /*!< TIMER2 IR: CR1INT Position */ -#define TIMER2_IR_CR1INT_Msk (0x01UL << TIMER2_IR_CR1INT_Pos) /*!< TIMER2 IR: CR1INT Mask */ -#define TIMER2_IR_CR2INT_Pos 6 /*!< TIMER2 IR: CR2INT Position */ -#define TIMER2_IR_CR2INT_Msk (0x01UL << TIMER2_IR_CR2INT_Pos) /*!< TIMER2 IR: CR2INT Mask */ -#define TIMER2_IR_CR3INT_Pos 7 /*!< TIMER2 IR: CR3INT Position */ -#define TIMER2_IR_CR3INT_Msk (0x01UL << TIMER2_IR_CR3INT_Pos) /*!< TIMER2 IR: CR3INT Mask */ - -// --------------------------------------- TIMER2_TCR ------------------------------------------- -#define TIMER2_TCR_CEN_Pos 0 /*!< TIMER2 TCR: CEN Position */ -#define TIMER2_TCR_CEN_Msk (0x01UL << TIMER2_TCR_CEN_Pos) /*!< TIMER2 TCR: CEN Mask */ -#define TIMER2_TCR_CRST_Pos 1 /*!< TIMER2 TCR: CRST Position */ -#define TIMER2_TCR_CRST_Msk (0x01UL << TIMER2_TCR_CRST_Pos) /*!< TIMER2 TCR: CRST Mask */ - -// ---------------------------------------- TIMER2_TC ------------------------------------------- -#define TIMER2_TC_TC_Pos 0 /*!< TIMER2 TC: TC Position */ -#define TIMER2_TC_TC_Msk (0xffffffffUL << TIMER2_TC_TC_Pos) /*!< TIMER2 TC: TC Mask */ - -// ---------------------------------------- TIMER2_PR ------------------------------------------- -#define TIMER2_PR_PM_Pos 0 /*!< TIMER2 PR: PM Position */ -#define TIMER2_PR_PM_Msk (0xffffffffUL << TIMER2_PR_PM_Pos) /*!< TIMER2 PR: PM Mask */ - -// ---------------------------------------- TIMER2_PC ------------------------------------------- -#define TIMER2_PC_PC_Pos 0 /*!< TIMER2 PC: PC Position */ -#define TIMER2_PC_PC_Msk (0xffffffffUL << TIMER2_PC_PC_Pos) /*!< TIMER2 PC: PC Mask */ - -// --------------------------------------- TIMER2_MCR ------------------------------------------- -#define TIMER2_MCR_MR0I_Pos 0 /*!< TIMER2 MCR: MR0I Position */ -#define TIMER2_MCR_MR0I_Msk (0x01UL << TIMER2_MCR_MR0I_Pos) /*!< TIMER2 MCR: MR0I Mask */ -#define TIMER2_MCR_MR0R_Pos 1 /*!< TIMER2 MCR: MR0R Position */ -#define TIMER2_MCR_MR0R_Msk (0x01UL << TIMER2_MCR_MR0R_Pos) /*!< TIMER2 MCR: MR0R Mask */ -#define TIMER2_MCR_MR0S_Pos 2 /*!< TIMER2 MCR: MR0S Position */ -#define TIMER2_MCR_MR0S_Msk (0x01UL << TIMER2_MCR_MR0S_Pos) /*!< TIMER2 MCR: MR0S Mask */ -#define TIMER2_MCR_MR1I_Pos 3 /*!< TIMER2 MCR: MR1I Position */ -#define TIMER2_MCR_MR1I_Msk (0x01UL << TIMER2_MCR_MR1I_Pos) /*!< TIMER2 MCR: MR1I Mask */ -#define TIMER2_MCR_MR1R_Pos 4 /*!< TIMER2 MCR: MR1R Position */ -#define TIMER2_MCR_MR1R_Msk (0x01UL << TIMER2_MCR_MR1R_Pos) /*!< TIMER2 MCR: MR1R Mask */ -#define TIMER2_MCR_MR1S_Pos 5 /*!< TIMER2 MCR: MR1S Position */ -#define TIMER2_MCR_MR1S_Msk (0x01UL << TIMER2_MCR_MR1S_Pos) /*!< TIMER2 MCR: MR1S Mask */ -#define TIMER2_MCR_MR2I_Pos 6 /*!< TIMER2 MCR: MR2I Position */ -#define TIMER2_MCR_MR2I_Msk (0x01UL << TIMER2_MCR_MR2I_Pos) /*!< TIMER2 MCR: MR2I Mask */ -#define TIMER2_MCR_MR2R_Pos 7 /*!< TIMER2 MCR: MR2R Position */ -#define TIMER2_MCR_MR2R_Msk (0x01UL << TIMER2_MCR_MR2R_Pos) /*!< TIMER2 MCR: MR2R Mask */ -#define TIMER2_MCR_MR2S_Pos 8 /*!< TIMER2 MCR: MR2S Position */ -#define TIMER2_MCR_MR2S_Msk (0x01UL << TIMER2_MCR_MR2S_Pos) /*!< TIMER2 MCR: MR2S Mask */ -#define TIMER2_MCR_MR3I_Pos 9 /*!< TIMER2 MCR: MR3I Position */ -#define TIMER2_MCR_MR3I_Msk (0x01UL << TIMER2_MCR_MR3I_Pos) /*!< TIMER2 MCR: MR3I Mask */ -#define TIMER2_MCR_MR3R_Pos 10 /*!< TIMER2 MCR: MR3R Position */ -#define TIMER2_MCR_MR3R_Msk (0x01UL << TIMER2_MCR_MR3R_Pos) /*!< TIMER2 MCR: MR3R Mask */ -#define TIMER2_MCR_MR3S_Pos 11 /*!< TIMER2 MCR: MR3S Position */ -#define TIMER2_MCR_MR3S_Msk (0x01UL << TIMER2_MCR_MR3S_Pos) /*!< TIMER2 MCR: MR3S Mask */ - -// --------------------------------------- TIMER2_MR0 ------------------------------------------- -#define TIMER2_MR0_MATCH_Pos 0 /*!< TIMER2 MR0: MATCH Position */ -#define TIMER2_MR0_MATCH_Msk (0xffffffffUL << TIMER2_MR0_MATCH_Pos) /*!< TIMER2 MR0: MATCH Mask */ - -// --------------------------------------- TIMER2_MR1 ------------------------------------------- -#define TIMER2_MR1_MATCH_Pos 0 /*!< TIMER2 MR1: MATCH Position */ -#define TIMER2_MR1_MATCH_Msk (0xffffffffUL << TIMER2_MR1_MATCH_Pos) /*!< TIMER2 MR1: MATCH Mask */ - -// --------------------------------------- TIMER2_MR2 ------------------------------------------- -#define TIMER2_MR2_MATCH_Pos 0 /*!< TIMER2 MR2: MATCH Position */ -#define TIMER2_MR2_MATCH_Msk (0xffffffffUL << TIMER2_MR2_MATCH_Pos) /*!< TIMER2 MR2: MATCH Mask */ - -// --------------------------------------- TIMER2_MR3 ------------------------------------------- -#define TIMER2_MR3_MATCH_Pos 0 /*!< TIMER2 MR3: MATCH Position */ -#define TIMER2_MR3_MATCH_Msk (0xffffffffUL << TIMER2_MR3_MATCH_Pos) /*!< TIMER2 MR3: MATCH Mask */ - -// --------------------------------------- TIMER2_CCR ------------------------------------------- -#define TIMER2_CCR_CAP0RE_Pos 0 /*!< TIMER2 CCR: CAP0RE Position */ -#define TIMER2_CCR_CAP0RE_Msk (0x01UL << TIMER2_CCR_CAP0RE_Pos) /*!< TIMER2 CCR: CAP0RE Mask */ -#define TIMER2_CCR_CAP0FE_Pos 1 /*!< TIMER2 CCR: CAP0FE Position */ -#define TIMER2_CCR_CAP0FE_Msk (0x01UL << TIMER2_CCR_CAP0FE_Pos) /*!< TIMER2 CCR: CAP0FE Mask */ -#define TIMER2_CCR_CAP0I_Pos 2 /*!< TIMER2 CCR: CAP0I Position */ -#define TIMER2_CCR_CAP0I_Msk (0x01UL << TIMER2_CCR_CAP0I_Pos) /*!< TIMER2 CCR: CAP0I Mask */ -#define TIMER2_CCR_CAP1RE_Pos 3 /*!< TIMER2 CCR: CAP1RE Position */ -#define TIMER2_CCR_CAP1RE_Msk (0x01UL << TIMER2_CCR_CAP1RE_Pos) /*!< TIMER2 CCR: CAP1RE Mask */ -#define TIMER2_CCR_CAP1FE_Pos 4 /*!< TIMER2 CCR: CAP1FE Position */ -#define TIMER2_CCR_CAP1FE_Msk (0x01UL << TIMER2_CCR_CAP1FE_Pos) /*!< TIMER2 CCR: CAP1FE Mask */ -#define TIMER2_CCR_CAP1I_Pos 5 /*!< TIMER2 CCR: CAP1I Position */ -#define TIMER2_CCR_CAP1I_Msk (0x01UL << TIMER2_CCR_CAP1I_Pos) /*!< TIMER2 CCR: CAP1I Mask */ -#define TIMER2_CCR_CAP2RE_Pos 6 /*!< TIMER2 CCR: CAP2RE Position */ -#define TIMER2_CCR_CAP2RE_Msk (0x01UL << TIMER2_CCR_CAP2RE_Pos) /*!< TIMER2 CCR: CAP2RE Mask */ -#define TIMER2_CCR_CAP2FE_Pos 7 /*!< TIMER2 CCR: CAP2FE Position */ -#define TIMER2_CCR_CAP2FE_Msk (0x01UL << TIMER2_CCR_CAP2FE_Pos) /*!< TIMER2 CCR: CAP2FE Mask */ -#define TIMER2_CCR_CAP2I_Pos 8 /*!< TIMER2 CCR: CAP2I Position */ -#define TIMER2_CCR_CAP2I_Msk (0x01UL << TIMER2_CCR_CAP2I_Pos) /*!< TIMER2 CCR: CAP2I Mask */ -#define TIMER2_CCR_CAP3RE_Pos 9 /*!< TIMER2 CCR: CAP3RE Position */ -#define TIMER2_CCR_CAP3RE_Msk (0x01UL << TIMER2_CCR_CAP3RE_Pos) /*!< TIMER2 CCR: CAP3RE Mask */ -#define TIMER2_CCR_CAP3FE_Pos 10 /*!< TIMER2 CCR: CAP3FE Position */ -#define TIMER2_CCR_CAP3FE_Msk (0x01UL << TIMER2_CCR_CAP3FE_Pos) /*!< TIMER2 CCR: CAP3FE Mask */ -#define TIMER2_CCR_CAP3I_Pos 11 /*!< TIMER2 CCR: CAP3I Position */ -#define TIMER2_CCR_CAP3I_Msk (0x01UL << TIMER2_CCR_CAP3I_Pos) /*!< TIMER2 CCR: CAP3I Mask */ - -// --------------------------------------- TIMER2_CR0 ------------------------------------------- -#define TIMER2_CR0_CAP_Pos 0 /*!< TIMER2 CR0: CAP Position */ -#define TIMER2_CR0_CAP_Msk (0xffffffffUL << TIMER2_CR0_CAP_Pos) /*!< TIMER2 CR0: CAP Mask */ - -// --------------------------------------- TIMER2_CR1 ------------------------------------------- -#define TIMER2_CR1_CAP_Pos 0 /*!< TIMER2 CR1: CAP Position */ -#define TIMER2_CR1_CAP_Msk (0xffffffffUL << TIMER2_CR1_CAP_Pos) /*!< TIMER2 CR1: CAP Mask */ - -// --------------------------------------- TIMER2_CR2 ------------------------------------------- -#define TIMER2_CR2_CAP_Pos 0 /*!< TIMER2 CR2: CAP Position */ -#define TIMER2_CR2_CAP_Msk (0xffffffffUL << TIMER2_CR2_CAP_Pos) /*!< TIMER2 CR2: CAP Mask */ - -// --------------------------------------- TIMER2_CR3 ------------------------------------------- -#define TIMER2_CR3_CAP_Pos 0 /*!< TIMER2 CR3: CAP Position */ -#define TIMER2_CR3_CAP_Msk (0xffffffffUL << TIMER2_CR3_CAP_Pos) /*!< TIMER2 CR3: CAP Mask */ - -// --------------------------------------- TIMER2_EMR ------------------------------------------- -#define TIMER2_EMR_EM0_Pos 0 /*!< TIMER2 EMR: EM0 Position */ -#define TIMER2_EMR_EM0_Msk (0x01UL << TIMER2_EMR_EM0_Pos) /*!< TIMER2 EMR: EM0 Mask */ -#define TIMER2_EMR_EM1_Pos 1 /*!< TIMER2 EMR: EM1 Position */ -#define TIMER2_EMR_EM1_Msk (0x01UL << TIMER2_EMR_EM1_Pos) /*!< TIMER2 EMR: EM1 Mask */ -#define TIMER2_EMR_EM2_Pos 2 /*!< TIMER2 EMR: EM2 Position */ -#define TIMER2_EMR_EM2_Msk (0x01UL << TIMER2_EMR_EM2_Pos) /*!< TIMER2 EMR: EM2 Mask */ -#define TIMER2_EMR_EM3_Pos 3 /*!< TIMER2 EMR: EM3 Position */ -#define TIMER2_EMR_EM3_Msk (0x01UL << TIMER2_EMR_EM3_Pos) /*!< TIMER2 EMR: EM3 Mask */ -#define TIMER2_EMR_EMC0_Pos 4 /*!< TIMER2 EMR: EMC0 Position */ -#define TIMER2_EMR_EMC0_Msk (0x03UL << TIMER2_EMR_EMC0_Pos) /*!< TIMER2 EMR: EMC0 Mask */ -#define TIMER2_EMR_EMC1_Pos 6 /*!< TIMER2 EMR: EMC1 Position */ -#define TIMER2_EMR_EMC1_Msk (0x03UL << TIMER2_EMR_EMC1_Pos) /*!< TIMER2 EMR: EMC1 Mask */ -#define TIMER2_EMR_EMC2_Pos 8 /*!< TIMER2 EMR: EMC2 Position */ -#define TIMER2_EMR_EMC2_Msk (0x03UL << TIMER2_EMR_EMC2_Pos) /*!< TIMER2 EMR: EMC2 Mask */ -#define TIMER2_EMR_EMC3_Pos 10 /*!< TIMER2 EMR: EMC3 Position */ -#define TIMER2_EMR_EMC3_Msk (0x03UL << TIMER2_EMR_EMC3_Pos) /*!< TIMER2 EMR: EMC3 Mask */ - -// --------------------------------------- TIMER2_CTCR ------------------------------------------ -#define TIMER2_CTCR_CTMODE_Pos 0 /*!< TIMER2 CTCR: CTMODE Position */ -#define TIMER2_CTCR_CTMODE_Msk (0x03UL << TIMER2_CTCR_CTMODE_Pos) /*!< TIMER2 CTCR: CTMODE Mask */ -#define TIMER2_CTCR_CINSEL_Pos 2 /*!< TIMER2 CTCR: CINSEL Position */ -#define TIMER2_CTCR_CINSEL_Msk (0x03UL << TIMER2_CTCR_CINSEL_Pos) /*!< TIMER2 CTCR: CINSEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMER3 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- TIMER3_IR ------------------------------------------- -#define TIMER3_IR_MR0INT_Pos 0 /*!< TIMER3 IR: MR0INT Position */ -#define TIMER3_IR_MR0INT_Msk (0x01UL << TIMER3_IR_MR0INT_Pos) /*!< TIMER3 IR: MR0INT Mask */ -#define TIMER3_IR_MR1INT_Pos 1 /*!< TIMER3 IR: MR1INT Position */ -#define TIMER3_IR_MR1INT_Msk (0x01UL << TIMER3_IR_MR1INT_Pos) /*!< TIMER3 IR: MR1INT Mask */ -#define TIMER3_IR_MR2INT_Pos 2 /*!< TIMER3 IR: MR2INT Position */ -#define TIMER3_IR_MR2INT_Msk (0x01UL << TIMER3_IR_MR2INT_Pos) /*!< TIMER3 IR: MR2INT Mask */ -#define TIMER3_IR_MR3INT_Pos 3 /*!< TIMER3 IR: MR3INT Position */ -#define TIMER3_IR_MR3INT_Msk (0x01UL << TIMER3_IR_MR3INT_Pos) /*!< TIMER3 IR: MR3INT Mask */ -#define TIMER3_IR_CR0INT_Pos 4 /*!< TIMER3 IR: CR0INT Position */ -#define TIMER3_IR_CR0INT_Msk (0x01UL << TIMER3_IR_CR0INT_Pos) /*!< TIMER3 IR: CR0INT Mask */ -#define TIMER3_IR_CR1INT_Pos 5 /*!< TIMER3 IR: CR1INT Position */ -#define TIMER3_IR_CR1INT_Msk (0x01UL << TIMER3_IR_CR1INT_Pos) /*!< TIMER3 IR: CR1INT Mask */ -#define TIMER3_IR_CR2INT_Pos 6 /*!< TIMER3 IR: CR2INT Position */ -#define TIMER3_IR_CR2INT_Msk (0x01UL << TIMER3_IR_CR2INT_Pos) /*!< TIMER3 IR: CR2INT Mask */ -#define TIMER3_IR_CR3INT_Pos 7 /*!< TIMER3 IR: CR3INT Position */ -#define TIMER3_IR_CR3INT_Msk (0x01UL << TIMER3_IR_CR3INT_Pos) /*!< TIMER3 IR: CR3INT Mask */ - -// --------------------------------------- TIMER3_TCR ------------------------------------------- -#define TIMER3_TCR_CEN_Pos 0 /*!< TIMER3 TCR: CEN Position */ -#define TIMER3_TCR_CEN_Msk (0x01UL << TIMER3_TCR_CEN_Pos) /*!< TIMER3 TCR: CEN Mask */ -#define TIMER3_TCR_CRST_Pos 1 /*!< TIMER3 TCR: CRST Position */ -#define TIMER3_TCR_CRST_Msk (0x01UL << TIMER3_TCR_CRST_Pos) /*!< TIMER3 TCR: CRST Mask */ - -// ---------------------------------------- TIMER3_TC ------------------------------------------- -#define TIMER3_TC_TC_Pos 0 /*!< TIMER3 TC: TC Position */ -#define TIMER3_TC_TC_Msk (0xffffffffUL << TIMER3_TC_TC_Pos) /*!< TIMER3 TC: TC Mask */ - -// ---------------------------------------- TIMER3_PR ------------------------------------------- -#define TIMER3_PR_PM_Pos 0 /*!< TIMER3 PR: PM Position */ -#define TIMER3_PR_PM_Msk (0xffffffffUL << TIMER3_PR_PM_Pos) /*!< TIMER3 PR: PM Mask */ - -// ---------------------------------------- TIMER3_PC ------------------------------------------- -#define TIMER3_PC_PC_Pos 0 /*!< TIMER3 PC: PC Position */ -#define TIMER3_PC_PC_Msk (0xffffffffUL << TIMER3_PC_PC_Pos) /*!< TIMER3 PC: PC Mask */ - -// --------------------------------------- TIMER3_MCR ------------------------------------------- -#define TIMER3_MCR_MR0I_Pos 0 /*!< TIMER3 MCR: MR0I Position */ -#define TIMER3_MCR_MR0I_Msk (0x01UL << TIMER3_MCR_MR0I_Pos) /*!< TIMER3 MCR: MR0I Mask */ -#define TIMER3_MCR_MR0R_Pos 1 /*!< TIMER3 MCR: MR0R Position */ -#define TIMER3_MCR_MR0R_Msk (0x01UL << TIMER3_MCR_MR0R_Pos) /*!< TIMER3 MCR: MR0R Mask */ -#define TIMER3_MCR_MR0S_Pos 2 /*!< TIMER3 MCR: MR0S Position */ -#define TIMER3_MCR_MR0S_Msk (0x01UL << TIMER3_MCR_MR0S_Pos) /*!< TIMER3 MCR: MR0S Mask */ -#define TIMER3_MCR_MR1I_Pos 3 /*!< TIMER3 MCR: MR1I Position */ -#define TIMER3_MCR_MR1I_Msk (0x01UL << TIMER3_MCR_MR1I_Pos) /*!< TIMER3 MCR: MR1I Mask */ -#define TIMER3_MCR_MR1R_Pos 4 /*!< TIMER3 MCR: MR1R Position */ -#define TIMER3_MCR_MR1R_Msk (0x01UL << TIMER3_MCR_MR1R_Pos) /*!< TIMER3 MCR: MR1R Mask */ -#define TIMER3_MCR_MR1S_Pos 5 /*!< TIMER3 MCR: MR1S Position */ -#define TIMER3_MCR_MR1S_Msk (0x01UL << TIMER3_MCR_MR1S_Pos) /*!< TIMER3 MCR: MR1S Mask */ -#define TIMER3_MCR_MR2I_Pos 6 /*!< TIMER3 MCR: MR2I Position */ -#define TIMER3_MCR_MR2I_Msk (0x01UL << TIMER3_MCR_MR2I_Pos) /*!< TIMER3 MCR: MR2I Mask */ -#define TIMER3_MCR_MR2R_Pos 7 /*!< TIMER3 MCR: MR2R Position */ -#define TIMER3_MCR_MR2R_Msk (0x01UL << TIMER3_MCR_MR2R_Pos) /*!< TIMER3 MCR: MR2R Mask */ -#define TIMER3_MCR_MR2S_Pos 8 /*!< TIMER3 MCR: MR2S Position */ -#define TIMER3_MCR_MR2S_Msk (0x01UL << TIMER3_MCR_MR2S_Pos) /*!< TIMER3 MCR: MR2S Mask */ -#define TIMER3_MCR_MR3I_Pos 9 /*!< TIMER3 MCR: MR3I Position */ -#define TIMER3_MCR_MR3I_Msk (0x01UL << TIMER3_MCR_MR3I_Pos) /*!< TIMER3 MCR: MR3I Mask */ -#define TIMER3_MCR_MR3R_Pos 10 /*!< TIMER3 MCR: MR3R Position */ -#define TIMER3_MCR_MR3R_Msk (0x01UL << TIMER3_MCR_MR3R_Pos) /*!< TIMER3 MCR: MR3R Mask */ -#define TIMER3_MCR_MR3S_Pos 11 /*!< TIMER3 MCR: MR3S Position */ -#define TIMER3_MCR_MR3S_Msk (0x01UL << TIMER3_MCR_MR3S_Pos) /*!< TIMER3 MCR: MR3S Mask */ - -// --------------------------------------- TIMER3_MR0 ------------------------------------------- -#define TIMER3_MR0_MATCH_Pos 0 /*!< TIMER3 MR0: MATCH Position */ -#define TIMER3_MR0_MATCH_Msk (0xffffffffUL << TIMER3_MR0_MATCH_Pos) /*!< TIMER3 MR0: MATCH Mask */ - -// --------------------------------------- TIMER3_MR1 ------------------------------------------- -#define TIMER3_MR1_MATCH_Pos 0 /*!< TIMER3 MR1: MATCH Position */ -#define TIMER3_MR1_MATCH_Msk (0xffffffffUL << TIMER3_MR1_MATCH_Pos) /*!< TIMER3 MR1: MATCH Mask */ - -// --------------------------------------- TIMER3_MR2 ------------------------------------------- -#define TIMER3_MR2_MATCH_Pos 0 /*!< TIMER3 MR2: MATCH Position */ -#define TIMER3_MR2_MATCH_Msk (0xffffffffUL << TIMER3_MR2_MATCH_Pos) /*!< TIMER3 MR2: MATCH Mask */ - -// --------------------------------------- TIMER3_MR3 ------------------------------------------- -#define TIMER3_MR3_MATCH_Pos 0 /*!< TIMER3 MR3: MATCH Position */ -#define TIMER3_MR3_MATCH_Msk (0xffffffffUL << TIMER3_MR3_MATCH_Pos) /*!< TIMER3 MR3: MATCH Mask */ - -// --------------------------------------- TIMER3_CCR ------------------------------------------- -#define TIMER3_CCR_CAP0RE_Pos 0 /*!< TIMER3 CCR: CAP0RE Position */ -#define TIMER3_CCR_CAP0RE_Msk (0x01UL << TIMER3_CCR_CAP0RE_Pos) /*!< TIMER3 CCR: CAP0RE Mask */ -#define TIMER3_CCR_CAP0FE_Pos 1 /*!< TIMER3 CCR: CAP0FE Position */ -#define TIMER3_CCR_CAP0FE_Msk (0x01UL << TIMER3_CCR_CAP0FE_Pos) /*!< TIMER3 CCR: CAP0FE Mask */ -#define TIMER3_CCR_CAP0I_Pos 2 /*!< TIMER3 CCR: CAP0I Position */ -#define TIMER3_CCR_CAP0I_Msk (0x01UL << TIMER3_CCR_CAP0I_Pos) /*!< TIMER3 CCR: CAP0I Mask */ -#define TIMER3_CCR_CAP1RE_Pos 3 /*!< TIMER3 CCR: CAP1RE Position */ -#define TIMER3_CCR_CAP1RE_Msk (0x01UL << TIMER3_CCR_CAP1RE_Pos) /*!< TIMER3 CCR: CAP1RE Mask */ -#define TIMER3_CCR_CAP1FE_Pos 4 /*!< TIMER3 CCR: CAP1FE Position */ -#define TIMER3_CCR_CAP1FE_Msk (0x01UL << TIMER3_CCR_CAP1FE_Pos) /*!< TIMER3 CCR: CAP1FE Mask */ -#define TIMER3_CCR_CAP1I_Pos 5 /*!< TIMER3 CCR: CAP1I Position */ -#define TIMER3_CCR_CAP1I_Msk (0x01UL << TIMER3_CCR_CAP1I_Pos) /*!< TIMER3 CCR: CAP1I Mask */ -#define TIMER3_CCR_CAP2RE_Pos 6 /*!< TIMER3 CCR: CAP2RE Position */ -#define TIMER3_CCR_CAP2RE_Msk (0x01UL << TIMER3_CCR_CAP2RE_Pos) /*!< TIMER3 CCR: CAP2RE Mask */ -#define TIMER3_CCR_CAP2FE_Pos 7 /*!< TIMER3 CCR: CAP2FE Position */ -#define TIMER3_CCR_CAP2FE_Msk (0x01UL << TIMER3_CCR_CAP2FE_Pos) /*!< TIMER3 CCR: CAP2FE Mask */ -#define TIMER3_CCR_CAP2I_Pos 8 /*!< TIMER3 CCR: CAP2I Position */ -#define TIMER3_CCR_CAP2I_Msk (0x01UL << TIMER3_CCR_CAP2I_Pos) /*!< TIMER3 CCR: CAP2I Mask */ -#define TIMER3_CCR_CAP3RE_Pos 9 /*!< TIMER3 CCR: CAP3RE Position */ -#define TIMER3_CCR_CAP3RE_Msk (0x01UL << TIMER3_CCR_CAP3RE_Pos) /*!< TIMER3 CCR: CAP3RE Mask */ -#define TIMER3_CCR_CAP3FE_Pos 10 /*!< TIMER3 CCR: CAP3FE Position */ -#define TIMER3_CCR_CAP3FE_Msk (0x01UL << TIMER3_CCR_CAP3FE_Pos) /*!< TIMER3 CCR: CAP3FE Mask */ -#define TIMER3_CCR_CAP3I_Pos 11 /*!< TIMER3 CCR: CAP3I Position */ -#define TIMER3_CCR_CAP3I_Msk (0x01UL << TIMER3_CCR_CAP3I_Pos) /*!< TIMER3 CCR: CAP3I Mask */ - -// --------------------------------------- TIMER3_CR0 ------------------------------------------- -#define TIMER3_CR0_CAP_Pos 0 /*!< TIMER3 CR0: CAP Position */ -#define TIMER3_CR0_CAP_Msk (0xffffffffUL << TIMER3_CR0_CAP_Pos) /*!< TIMER3 CR0: CAP Mask */ - -// --------------------------------------- TIMER3_CR1 ------------------------------------------- -#define TIMER3_CR1_CAP_Pos 0 /*!< TIMER3 CR1: CAP Position */ -#define TIMER3_CR1_CAP_Msk (0xffffffffUL << TIMER3_CR1_CAP_Pos) /*!< TIMER3 CR1: CAP Mask */ - -// --------------------------------------- TIMER3_CR2 ------------------------------------------- -#define TIMER3_CR2_CAP_Pos 0 /*!< TIMER3 CR2: CAP Position */ -#define TIMER3_CR2_CAP_Msk (0xffffffffUL << TIMER3_CR2_CAP_Pos) /*!< TIMER3 CR2: CAP Mask */ - -// --------------------------------------- TIMER3_CR3 ------------------------------------------- -#define TIMER3_CR3_CAP_Pos 0 /*!< TIMER3 CR3: CAP Position */ -#define TIMER3_CR3_CAP_Msk (0xffffffffUL << TIMER3_CR3_CAP_Pos) /*!< TIMER3 CR3: CAP Mask */ - -// --------------------------------------- TIMER3_EMR ------------------------------------------- -#define TIMER3_EMR_EM0_Pos 0 /*!< TIMER3 EMR: EM0 Position */ -#define TIMER3_EMR_EM0_Msk (0x01UL << TIMER3_EMR_EM0_Pos) /*!< TIMER3 EMR: EM0 Mask */ -#define TIMER3_EMR_EM1_Pos 1 /*!< TIMER3 EMR: EM1 Position */ -#define TIMER3_EMR_EM1_Msk (0x01UL << TIMER3_EMR_EM1_Pos) /*!< TIMER3 EMR: EM1 Mask */ -#define TIMER3_EMR_EM2_Pos 2 /*!< TIMER3 EMR: EM2 Position */ -#define TIMER3_EMR_EM2_Msk (0x01UL << TIMER3_EMR_EM2_Pos) /*!< TIMER3 EMR: EM2 Mask */ -#define TIMER3_EMR_EM3_Pos 3 /*!< TIMER3 EMR: EM3 Position */ -#define TIMER3_EMR_EM3_Msk (0x01UL << TIMER3_EMR_EM3_Pos) /*!< TIMER3 EMR: EM3 Mask */ -#define TIMER3_EMR_EMC0_Pos 4 /*!< TIMER3 EMR: EMC0 Position */ -#define TIMER3_EMR_EMC0_Msk (0x03UL << TIMER3_EMR_EMC0_Pos) /*!< TIMER3 EMR: EMC0 Mask */ -#define TIMER3_EMR_EMC1_Pos 6 /*!< TIMER3 EMR: EMC1 Position */ -#define TIMER3_EMR_EMC1_Msk (0x03UL << TIMER3_EMR_EMC1_Pos) /*!< TIMER3 EMR: EMC1 Mask */ -#define TIMER3_EMR_EMC2_Pos 8 /*!< TIMER3 EMR: EMC2 Position */ -#define TIMER3_EMR_EMC2_Msk (0x03UL << TIMER3_EMR_EMC2_Pos) /*!< TIMER3 EMR: EMC2 Mask */ -#define TIMER3_EMR_EMC3_Pos 10 /*!< TIMER3 EMR: EMC3 Position */ -#define TIMER3_EMR_EMC3_Msk (0x03UL << TIMER3_EMR_EMC3_Pos) /*!< TIMER3 EMR: EMC3 Mask */ - -// --------------------------------------- TIMER3_CTCR ------------------------------------------ -#define TIMER3_CTCR_CTMODE_Pos 0 /*!< TIMER3 CTCR: CTMODE Position */ -#define TIMER3_CTCR_CTMODE_Msk (0x03UL << TIMER3_CTCR_CTMODE_Pos) /*!< TIMER3 CTCR: CTMODE Mask */ -#define TIMER3_CTCR_CINSEL_Pos 2 /*!< TIMER3 CTCR: CINSEL Position */ -#define TIMER3_CTCR_CINSEL_Msk (0x03UL << TIMER3_CTCR_CINSEL_Pos) /*!< TIMER3 CTCR: CINSEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SCU Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- SCU_SFSP0_0 ------------------------------------------ -#define SCU_SFSP0_0_MODE_Pos 0 /*!< SCU SFSP0_0: MODE Position */ -#define SCU_SFSP0_0_MODE_Msk (0x07UL << SCU_SFSP0_0_MODE_Pos) /*!< SCU SFSP0_0: MODE Mask */ -#define SCU_SFSP0_0_EPD_Pos 3 /*!< SCU SFSP0_0: EPD Position */ -#define SCU_SFSP0_0_EPD_Msk (0x01UL << SCU_SFSP0_0_EPD_Pos) /*!< SCU SFSP0_0: EPD Mask */ -#define SCU_SFSP0_0_EPUN_Pos 4 /*!< SCU SFSP0_0: EPUN Position */ -#define SCU_SFSP0_0_EPUN_Msk (0x01UL << SCU_SFSP0_0_EPUN_Pos) /*!< SCU SFSP0_0: EPUN Mask */ -#define SCU_SFSP0_0_EHS_Pos 5 /*!< SCU SFSP0_0: EHS Position */ -#define SCU_SFSP0_0_EHS_Msk (0x01UL << SCU_SFSP0_0_EHS_Pos) /*!< SCU SFSP0_0: EHS Mask */ -#define SCU_SFSP0_0_EZI_Pos 6 /*!< SCU SFSP0_0: EZI Position */ -#define SCU_SFSP0_0_EZI_Msk (0x01UL << SCU_SFSP0_0_EZI_Pos) /*!< SCU SFSP0_0: EZI Mask */ - -// --------------------------------------- SCU_SFSP0_1 ------------------------------------------ -#define SCU_SFSP0_1_MODE_Pos 0 /*!< SCU SFSP0_1: MODE Position */ -#define SCU_SFSP0_1_MODE_Msk (0x07UL << SCU_SFSP0_1_MODE_Pos) /*!< SCU SFSP0_1: MODE Mask */ -#define SCU_SFSP0_1_EPD_Pos 3 /*!< SCU SFSP0_1: EPD Position */ -#define SCU_SFSP0_1_EPD_Msk (0x01UL << SCU_SFSP0_1_EPD_Pos) /*!< SCU SFSP0_1: EPD Mask */ -#define SCU_SFSP0_1_EPUN_Pos 4 /*!< SCU SFSP0_1: EPUN Position */ -#define SCU_SFSP0_1_EPUN_Msk (0x01UL << SCU_SFSP0_1_EPUN_Pos) /*!< SCU SFSP0_1: EPUN Mask */ -#define SCU_SFSP0_1_EHS_Pos 5 /*!< SCU SFSP0_1: EHS Position */ -#define SCU_SFSP0_1_EHS_Msk (0x01UL << SCU_SFSP0_1_EHS_Pos) /*!< SCU SFSP0_1: EHS Mask */ -#define SCU_SFSP0_1_EZI_Pos 6 /*!< SCU SFSP0_1: EZI Position */ -#define SCU_SFSP0_1_EZI_Msk (0x01UL << SCU_SFSP0_1_EZI_Pos) /*!< SCU SFSP0_1: EZI Mask */ - -// --------------------------------------- SCU_SFSP1_0 ------------------------------------------ -#define SCU_SFSP1_0_MODE_Pos 0 /*!< SCU SFSP1_0: MODE Position */ -#define SCU_SFSP1_0_MODE_Msk (0x07UL << SCU_SFSP1_0_MODE_Pos) /*!< SCU SFSP1_0: MODE Mask */ -#define SCU_SFSP1_0_EPD_Pos 3 /*!< SCU SFSP1_0: EPD Position */ -#define SCU_SFSP1_0_EPD_Msk (0x01UL << SCU_SFSP1_0_EPD_Pos) /*!< SCU SFSP1_0: EPD Mask */ -#define SCU_SFSP1_0_EPUN_Pos 4 /*!< SCU SFSP1_0: EPUN Position */ -#define SCU_SFSP1_0_EPUN_Msk (0x01UL << SCU_SFSP1_0_EPUN_Pos) /*!< SCU SFSP1_0: EPUN Mask */ -#define SCU_SFSP1_0_EHS_Pos 5 /*!< SCU SFSP1_0: EHS Position */ -#define SCU_SFSP1_0_EHS_Msk (0x01UL << SCU_SFSP1_0_EHS_Pos) /*!< SCU SFSP1_0: EHS Mask */ -#define SCU_SFSP1_0_EZI_Pos 6 /*!< SCU SFSP1_0: EZI Position */ -#define SCU_SFSP1_0_EZI_Msk (0x01UL << SCU_SFSP1_0_EZI_Pos) /*!< SCU SFSP1_0: EZI Mask */ -#define SCU_SFSP1_0_EHD_Pos 8 /*!< SCU SFSP1_0: EHD Position */ -#define SCU_SFSP1_0_EHD_Msk (0x03UL << SCU_SFSP1_0_EHD_Pos) /*!< SCU SFSP1_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_1 ------------------------------------------ -#define SCU_SFSP1_1_MODE_Pos 0 /*!< SCU SFSP1_1: MODE Position */ -#define SCU_SFSP1_1_MODE_Msk (0x07UL << SCU_SFSP1_1_MODE_Pos) /*!< SCU SFSP1_1: MODE Mask */ -#define SCU_SFSP1_1_EPD_Pos 3 /*!< SCU SFSP1_1: EPD Position */ -#define SCU_SFSP1_1_EPD_Msk (0x01UL << SCU_SFSP1_1_EPD_Pos) /*!< SCU SFSP1_1: EPD Mask */ -#define SCU_SFSP1_1_EPUN_Pos 4 /*!< SCU SFSP1_1: EPUN Position */ -#define SCU_SFSP1_1_EPUN_Msk (0x01UL << SCU_SFSP1_1_EPUN_Pos) /*!< SCU SFSP1_1: EPUN Mask */ -#define SCU_SFSP1_1_EHS_Pos 5 /*!< SCU SFSP1_1: EHS Position */ -#define SCU_SFSP1_1_EHS_Msk (0x01UL << SCU_SFSP1_1_EHS_Pos) /*!< SCU SFSP1_1: EHS Mask */ -#define SCU_SFSP1_1_EZI_Pos 6 /*!< SCU SFSP1_1: EZI Position */ -#define SCU_SFSP1_1_EZI_Msk (0x01UL << SCU_SFSP1_1_EZI_Pos) /*!< SCU SFSP1_1: EZI Mask */ -#define SCU_SFSP1_1_EHD_Pos 8 /*!< SCU SFSP1_1: EHD Position */ -#define SCU_SFSP1_1_EHD_Msk (0x03UL << SCU_SFSP1_1_EHD_Pos) /*!< SCU SFSP1_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_2 ------------------------------------------ -#define SCU_SFSP1_2_MODE_Pos 0 /*!< SCU SFSP1_2: MODE Position */ -#define SCU_SFSP1_2_MODE_Msk (0x07UL << SCU_SFSP1_2_MODE_Pos) /*!< SCU SFSP1_2: MODE Mask */ -#define SCU_SFSP1_2_EPD_Pos 3 /*!< SCU SFSP1_2: EPD Position */ -#define SCU_SFSP1_2_EPD_Msk (0x01UL << SCU_SFSP1_2_EPD_Pos) /*!< SCU SFSP1_2: EPD Mask */ -#define SCU_SFSP1_2_EPUN_Pos 4 /*!< SCU SFSP1_2: EPUN Position */ -#define SCU_SFSP1_2_EPUN_Msk (0x01UL << SCU_SFSP1_2_EPUN_Pos) /*!< SCU SFSP1_2: EPUN Mask */ -#define SCU_SFSP1_2_EHS_Pos 5 /*!< SCU SFSP1_2: EHS Position */ -#define SCU_SFSP1_2_EHS_Msk (0x01UL << SCU_SFSP1_2_EHS_Pos) /*!< SCU SFSP1_2: EHS Mask */ -#define SCU_SFSP1_2_EZI_Pos 6 /*!< SCU SFSP1_2: EZI Position */ -#define SCU_SFSP1_2_EZI_Msk (0x01UL << SCU_SFSP1_2_EZI_Pos) /*!< SCU SFSP1_2: EZI Mask */ -#define SCU_SFSP1_2_EHD_Pos 8 /*!< SCU SFSP1_2: EHD Position */ -#define SCU_SFSP1_2_EHD_Msk (0x03UL << SCU_SFSP1_2_EHD_Pos) /*!< SCU SFSP1_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_3 ------------------------------------------ -#define SCU_SFSP1_3_MODE_Pos 0 /*!< SCU SFSP1_3: MODE Position */ -#define SCU_SFSP1_3_MODE_Msk (0x07UL << SCU_SFSP1_3_MODE_Pos) /*!< SCU SFSP1_3: MODE Mask */ -#define SCU_SFSP1_3_EPD_Pos 3 /*!< SCU SFSP1_3: EPD Position */ -#define SCU_SFSP1_3_EPD_Msk (0x01UL << SCU_SFSP1_3_EPD_Pos) /*!< SCU SFSP1_3: EPD Mask */ -#define SCU_SFSP1_3_EPUN_Pos 4 /*!< SCU SFSP1_3: EPUN Position */ -#define SCU_SFSP1_3_EPUN_Msk (0x01UL << SCU_SFSP1_3_EPUN_Pos) /*!< SCU SFSP1_3: EPUN Mask */ -#define SCU_SFSP1_3_EHS_Pos 5 /*!< SCU SFSP1_3: EHS Position */ -#define SCU_SFSP1_3_EHS_Msk (0x01UL << SCU_SFSP1_3_EHS_Pos) /*!< SCU SFSP1_3: EHS Mask */ -#define SCU_SFSP1_3_EZI_Pos 6 /*!< SCU SFSP1_3: EZI Position */ -#define SCU_SFSP1_3_EZI_Msk (0x01UL << SCU_SFSP1_3_EZI_Pos) /*!< SCU SFSP1_3: EZI Mask */ -#define SCU_SFSP1_3_EHD_Pos 8 /*!< SCU SFSP1_3: EHD Position */ -#define SCU_SFSP1_3_EHD_Msk (0x03UL << SCU_SFSP1_3_EHD_Pos) /*!< SCU SFSP1_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_4 ------------------------------------------ -#define SCU_SFSP1_4_MODE_Pos 0 /*!< SCU SFSP1_4: MODE Position */ -#define SCU_SFSP1_4_MODE_Msk (0x07UL << SCU_SFSP1_4_MODE_Pos) /*!< SCU SFSP1_4: MODE Mask */ -#define SCU_SFSP1_4_EPD_Pos 3 /*!< SCU SFSP1_4: EPD Position */ -#define SCU_SFSP1_4_EPD_Msk (0x01UL << SCU_SFSP1_4_EPD_Pos) /*!< SCU SFSP1_4: EPD Mask */ -#define SCU_SFSP1_4_EPUN_Pos 4 /*!< SCU SFSP1_4: EPUN Position */ -#define SCU_SFSP1_4_EPUN_Msk (0x01UL << SCU_SFSP1_4_EPUN_Pos) /*!< SCU SFSP1_4: EPUN Mask */ -#define SCU_SFSP1_4_EHS_Pos 5 /*!< SCU SFSP1_4: EHS Position */ -#define SCU_SFSP1_4_EHS_Msk (0x01UL << SCU_SFSP1_4_EHS_Pos) /*!< SCU SFSP1_4: EHS Mask */ -#define SCU_SFSP1_4_EZI_Pos 6 /*!< SCU SFSP1_4: EZI Position */ -#define SCU_SFSP1_4_EZI_Msk (0x01UL << SCU_SFSP1_4_EZI_Pos) /*!< SCU SFSP1_4: EZI Mask */ -#define SCU_SFSP1_4_EHD_Pos 8 /*!< SCU SFSP1_4: EHD Position */ -#define SCU_SFSP1_4_EHD_Msk (0x03UL << SCU_SFSP1_4_EHD_Pos) /*!< SCU SFSP1_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_5 ------------------------------------------ -#define SCU_SFSP1_5_MODE_Pos 0 /*!< SCU SFSP1_5: MODE Position */ -#define SCU_SFSP1_5_MODE_Msk (0x07UL << SCU_SFSP1_5_MODE_Pos) /*!< SCU SFSP1_5: MODE Mask */ -#define SCU_SFSP1_5_EPD_Pos 3 /*!< SCU SFSP1_5: EPD Position */ -#define SCU_SFSP1_5_EPD_Msk (0x01UL << SCU_SFSP1_5_EPD_Pos) /*!< SCU SFSP1_5: EPD Mask */ -#define SCU_SFSP1_5_EPUN_Pos 4 /*!< SCU SFSP1_5: EPUN Position */ -#define SCU_SFSP1_5_EPUN_Msk (0x01UL << SCU_SFSP1_5_EPUN_Pos) /*!< SCU SFSP1_5: EPUN Mask */ -#define SCU_SFSP1_5_EHS_Pos 5 /*!< SCU SFSP1_5: EHS Position */ -#define SCU_SFSP1_5_EHS_Msk (0x01UL << SCU_SFSP1_5_EHS_Pos) /*!< SCU SFSP1_5: EHS Mask */ -#define SCU_SFSP1_5_EZI_Pos 6 /*!< SCU SFSP1_5: EZI Position */ -#define SCU_SFSP1_5_EZI_Msk (0x01UL << SCU_SFSP1_5_EZI_Pos) /*!< SCU SFSP1_5: EZI Mask */ -#define SCU_SFSP1_5_EHD_Pos 8 /*!< SCU SFSP1_5: EHD Position */ -#define SCU_SFSP1_5_EHD_Msk (0x03UL << SCU_SFSP1_5_EHD_Pos) /*!< SCU SFSP1_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_6 ------------------------------------------ -#define SCU_SFSP1_6_MODE_Pos 0 /*!< SCU SFSP1_6: MODE Position */ -#define SCU_SFSP1_6_MODE_Msk (0x07UL << SCU_SFSP1_6_MODE_Pos) /*!< SCU SFSP1_6: MODE Mask */ -#define SCU_SFSP1_6_EPD_Pos 3 /*!< SCU SFSP1_6: EPD Position */ -#define SCU_SFSP1_6_EPD_Msk (0x01UL << SCU_SFSP1_6_EPD_Pos) /*!< SCU SFSP1_6: EPD Mask */ -#define SCU_SFSP1_6_EPUN_Pos 4 /*!< SCU SFSP1_6: EPUN Position */ -#define SCU_SFSP1_6_EPUN_Msk (0x01UL << SCU_SFSP1_6_EPUN_Pos) /*!< SCU SFSP1_6: EPUN Mask */ -#define SCU_SFSP1_6_EHS_Pos 5 /*!< SCU SFSP1_6: EHS Position */ -#define SCU_SFSP1_6_EHS_Msk (0x01UL << SCU_SFSP1_6_EHS_Pos) /*!< SCU SFSP1_6: EHS Mask */ -#define SCU_SFSP1_6_EZI_Pos 6 /*!< SCU SFSP1_6: EZI Position */ -#define SCU_SFSP1_6_EZI_Msk (0x01UL << SCU_SFSP1_6_EZI_Pos) /*!< SCU SFSP1_6: EZI Mask */ -#define SCU_SFSP1_6_EHD_Pos 8 /*!< SCU SFSP1_6: EHD Position */ -#define SCU_SFSP1_6_EHD_Msk (0x03UL << SCU_SFSP1_6_EHD_Pos) /*!< SCU SFSP1_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_7 ------------------------------------------ -#define SCU_SFSP1_7_MODE_Pos 0 /*!< SCU SFSP1_7: MODE Position */ -#define SCU_SFSP1_7_MODE_Msk (0x07UL << SCU_SFSP1_7_MODE_Pos) /*!< SCU SFSP1_7: MODE Mask */ -#define SCU_SFSP1_7_EPD_Pos 3 /*!< SCU SFSP1_7: EPD Position */ -#define SCU_SFSP1_7_EPD_Msk (0x01UL << SCU_SFSP1_7_EPD_Pos) /*!< SCU SFSP1_7: EPD Mask */ -#define SCU_SFSP1_7_EPUN_Pos 4 /*!< SCU SFSP1_7: EPUN Position */ -#define SCU_SFSP1_7_EPUN_Msk (0x01UL << SCU_SFSP1_7_EPUN_Pos) /*!< SCU SFSP1_7: EPUN Mask */ -#define SCU_SFSP1_7_EHS_Pos 5 /*!< SCU SFSP1_7: EHS Position */ -#define SCU_SFSP1_7_EHS_Msk (0x01UL << SCU_SFSP1_7_EHS_Pos) /*!< SCU SFSP1_7: EHS Mask */ -#define SCU_SFSP1_7_EZI_Pos 6 /*!< SCU SFSP1_7: EZI Position */ -#define SCU_SFSP1_7_EZI_Msk (0x01UL << SCU_SFSP1_7_EZI_Pos) /*!< SCU SFSP1_7: EZI Mask */ -#define SCU_SFSP1_7_EHD_Pos 8 /*!< SCU SFSP1_7: EHD Position */ -#define SCU_SFSP1_7_EHD_Msk (0x03UL << SCU_SFSP1_7_EHD_Pos) /*!< SCU SFSP1_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_8 ------------------------------------------ -#define SCU_SFSP1_8_MODE_Pos 0 /*!< SCU SFSP1_8: MODE Position */ -#define SCU_SFSP1_8_MODE_Msk (0x07UL << SCU_SFSP1_8_MODE_Pos) /*!< SCU SFSP1_8: MODE Mask */ -#define SCU_SFSP1_8_EPD_Pos 3 /*!< SCU SFSP1_8: EPD Position */ -#define SCU_SFSP1_8_EPD_Msk (0x01UL << SCU_SFSP1_8_EPD_Pos) /*!< SCU SFSP1_8: EPD Mask */ -#define SCU_SFSP1_8_EPUN_Pos 4 /*!< SCU SFSP1_8: EPUN Position */ -#define SCU_SFSP1_8_EPUN_Msk (0x01UL << SCU_SFSP1_8_EPUN_Pos) /*!< SCU SFSP1_8: EPUN Mask */ -#define SCU_SFSP1_8_EHS_Pos 5 /*!< SCU SFSP1_8: EHS Position */ -#define SCU_SFSP1_8_EHS_Msk (0x01UL << SCU_SFSP1_8_EHS_Pos) /*!< SCU SFSP1_8: EHS Mask */ -#define SCU_SFSP1_8_EZI_Pos 6 /*!< SCU SFSP1_8: EZI Position */ -#define SCU_SFSP1_8_EZI_Msk (0x01UL << SCU_SFSP1_8_EZI_Pos) /*!< SCU SFSP1_8: EZI Mask */ -#define SCU_SFSP1_8_EHD_Pos 8 /*!< SCU SFSP1_8: EHD Position */ -#define SCU_SFSP1_8_EHD_Msk (0x03UL << SCU_SFSP1_8_EHD_Pos) /*!< SCU SFSP1_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_9 ------------------------------------------ -#define SCU_SFSP1_9_MODE_Pos 0 /*!< SCU SFSP1_9: MODE Position */ -#define SCU_SFSP1_9_MODE_Msk (0x07UL << SCU_SFSP1_9_MODE_Pos) /*!< SCU SFSP1_9: MODE Mask */ -#define SCU_SFSP1_9_EPD_Pos 3 /*!< SCU SFSP1_9: EPD Position */ -#define SCU_SFSP1_9_EPD_Msk (0x01UL << SCU_SFSP1_9_EPD_Pos) /*!< SCU SFSP1_9: EPD Mask */ -#define SCU_SFSP1_9_EPUN_Pos 4 /*!< SCU SFSP1_9: EPUN Position */ -#define SCU_SFSP1_9_EPUN_Msk (0x01UL << SCU_SFSP1_9_EPUN_Pos) /*!< SCU SFSP1_9: EPUN Mask */ -#define SCU_SFSP1_9_EHS_Pos 5 /*!< SCU SFSP1_9: EHS Position */ -#define SCU_SFSP1_9_EHS_Msk (0x01UL << SCU_SFSP1_9_EHS_Pos) /*!< SCU SFSP1_9: EHS Mask */ -#define SCU_SFSP1_9_EZI_Pos 6 /*!< SCU SFSP1_9: EZI Position */ -#define SCU_SFSP1_9_EZI_Msk (0x01UL << SCU_SFSP1_9_EZI_Pos) /*!< SCU SFSP1_9: EZI Mask */ -#define SCU_SFSP1_9_EHD_Pos 8 /*!< SCU SFSP1_9: EHD Position */ -#define SCU_SFSP1_9_EHD_Msk (0x03UL << SCU_SFSP1_9_EHD_Pos) /*!< SCU SFSP1_9: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_10 ------------------------------------------ -#define SCU_SFSP1_10_MODE_Pos 0 /*!< SCU SFSP1_10: MODE Position */ -#define SCU_SFSP1_10_MODE_Msk (0x07UL << SCU_SFSP1_10_MODE_Pos) /*!< SCU SFSP1_10: MODE Mask */ -#define SCU_SFSP1_10_EPD_Pos 3 /*!< SCU SFSP1_10: EPD Position */ -#define SCU_SFSP1_10_EPD_Msk (0x01UL << SCU_SFSP1_10_EPD_Pos) /*!< SCU SFSP1_10: EPD Mask */ -#define SCU_SFSP1_10_EPUN_Pos 4 /*!< SCU SFSP1_10: EPUN Position */ -#define SCU_SFSP1_10_EPUN_Msk (0x01UL << SCU_SFSP1_10_EPUN_Pos) /*!< SCU SFSP1_10: EPUN Mask */ -#define SCU_SFSP1_10_EHS_Pos 5 /*!< SCU SFSP1_10: EHS Position */ -#define SCU_SFSP1_10_EHS_Msk (0x01UL << SCU_SFSP1_10_EHS_Pos) /*!< SCU SFSP1_10: EHS Mask */ -#define SCU_SFSP1_10_EZI_Pos 6 /*!< SCU SFSP1_10: EZI Position */ -#define SCU_SFSP1_10_EZI_Msk (0x01UL << SCU_SFSP1_10_EZI_Pos) /*!< SCU SFSP1_10: EZI Mask */ -#define SCU_SFSP1_10_EHD_Pos 8 /*!< SCU SFSP1_10: EHD Position */ -#define SCU_SFSP1_10_EHD_Msk (0x03UL << SCU_SFSP1_10_EHD_Pos) /*!< SCU SFSP1_10: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_11 ------------------------------------------ -#define SCU_SFSP1_11_MODE_Pos 0 /*!< SCU SFSP1_11: MODE Position */ -#define SCU_SFSP1_11_MODE_Msk (0x07UL << SCU_SFSP1_11_MODE_Pos) /*!< SCU SFSP1_11: MODE Mask */ -#define SCU_SFSP1_11_EPD_Pos 3 /*!< SCU SFSP1_11: EPD Position */ -#define SCU_SFSP1_11_EPD_Msk (0x01UL << SCU_SFSP1_11_EPD_Pos) /*!< SCU SFSP1_11: EPD Mask */ -#define SCU_SFSP1_11_EPUN_Pos 4 /*!< SCU SFSP1_11: EPUN Position */ -#define SCU_SFSP1_11_EPUN_Msk (0x01UL << SCU_SFSP1_11_EPUN_Pos) /*!< SCU SFSP1_11: EPUN Mask */ -#define SCU_SFSP1_11_EHS_Pos 5 /*!< SCU SFSP1_11: EHS Position */ -#define SCU_SFSP1_11_EHS_Msk (0x01UL << SCU_SFSP1_11_EHS_Pos) /*!< SCU SFSP1_11: EHS Mask */ -#define SCU_SFSP1_11_EZI_Pos 6 /*!< SCU SFSP1_11: EZI Position */ -#define SCU_SFSP1_11_EZI_Msk (0x01UL << SCU_SFSP1_11_EZI_Pos) /*!< SCU SFSP1_11: EZI Mask */ -#define SCU_SFSP1_11_EHD_Pos 8 /*!< SCU SFSP1_11: EHD Position */ -#define SCU_SFSP1_11_EHD_Msk (0x03UL << SCU_SFSP1_11_EHD_Pos) /*!< SCU SFSP1_11: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_12 ------------------------------------------ -#define SCU_SFSP1_12_MODE_Pos 0 /*!< SCU SFSP1_12: MODE Position */ -#define SCU_SFSP1_12_MODE_Msk (0x07UL << SCU_SFSP1_12_MODE_Pos) /*!< SCU SFSP1_12: MODE Mask */ -#define SCU_SFSP1_12_EPD_Pos 3 /*!< SCU SFSP1_12: EPD Position */ -#define SCU_SFSP1_12_EPD_Msk (0x01UL << SCU_SFSP1_12_EPD_Pos) /*!< SCU SFSP1_12: EPD Mask */ -#define SCU_SFSP1_12_EPUN_Pos 4 /*!< SCU SFSP1_12: EPUN Position */ -#define SCU_SFSP1_12_EPUN_Msk (0x01UL << SCU_SFSP1_12_EPUN_Pos) /*!< SCU SFSP1_12: EPUN Mask */ -#define SCU_SFSP1_12_EHS_Pos 5 /*!< SCU SFSP1_12: EHS Position */ -#define SCU_SFSP1_12_EHS_Msk (0x01UL << SCU_SFSP1_12_EHS_Pos) /*!< SCU SFSP1_12: EHS Mask */ -#define SCU_SFSP1_12_EZI_Pos 6 /*!< SCU SFSP1_12: EZI Position */ -#define SCU_SFSP1_12_EZI_Msk (0x01UL << SCU_SFSP1_12_EZI_Pos) /*!< SCU SFSP1_12: EZI Mask */ -#define SCU_SFSP1_12_EHD_Pos 8 /*!< SCU SFSP1_12: EHD Position */ -#define SCU_SFSP1_12_EHD_Msk (0x03UL << SCU_SFSP1_12_EHD_Pos) /*!< SCU SFSP1_12: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_13 ------------------------------------------ -#define SCU_SFSP1_13_MODE_Pos 0 /*!< SCU SFSP1_13: MODE Position */ -#define SCU_SFSP1_13_MODE_Msk (0x07UL << SCU_SFSP1_13_MODE_Pos) /*!< SCU SFSP1_13: MODE Mask */ -#define SCU_SFSP1_13_EPD_Pos 3 /*!< SCU SFSP1_13: EPD Position */ -#define SCU_SFSP1_13_EPD_Msk (0x01UL << SCU_SFSP1_13_EPD_Pos) /*!< SCU SFSP1_13: EPD Mask */ -#define SCU_SFSP1_13_EPUN_Pos 4 /*!< SCU SFSP1_13: EPUN Position */ -#define SCU_SFSP1_13_EPUN_Msk (0x01UL << SCU_SFSP1_13_EPUN_Pos) /*!< SCU SFSP1_13: EPUN Mask */ -#define SCU_SFSP1_13_EHS_Pos 5 /*!< SCU SFSP1_13: EHS Position */ -#define SCU_SFSP1_13_EHS_Msk (0x01UL << SCU_SFSP1_13_EHS_Pos) /*!< SCU SFSP1_13: EHS Mask */ -#define SCU_SFSP1_13_EZI_Pos 6 /*!< SCU SFSP1_13: EZI Position */ -#define SCU_SFSP1_13_EZI_Msk (0x01UL << SCU_SFSP1_13_EZI_Pos) /*!< SCU SFSP1_13: EZI Mask */ -#define SCU_SFSP1_13_EHD_Pos 8 /*!< SCU SFSP1_13: EHD Position */ -#define SCU_SFSP1_13_EHD_Msk (0x03UL << SCU_SFSP1_13_EHD_Pos) /*!< SCU SFSP1_13: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_14 ------------------------------------------ -#define SCU_SFSP1_14_MODE_Pos 0 /*!< SCU SFSP1_14: MODE Position */ -#define SCU_SFSP1_14_MODE_Msk (0x07UL << SCU_SFSP1_14_MODE_Pos) /*!< SCU SFSP1_14: MODE Mask */ -#define SCU_SFSP1_14_EPD_Pos 3 /*!< SCU SFSP1_14: EPD Position */ -#define SCU_SFSP1_14_EPD_Msk (0x01UL << SCU_SFSP1_14_EPD_Pos) /*!< SCU SFSP1_14: EPD Mask */ -#define SCU_SFSP1_14_EPUN_Pos 4 /*!< SCU SFSP1_14: EPUN Position */ -#define SCU_SFSP1_14_EPUN_Msk (0x01UL << SCU_SFSP1_14_EPUN_Pos) /*!< SCU SFSP1_14: EPUN Mask */ -#define SCU_SFSP1_14_EHS_Pos 5 /*!< SCU SFSP1_14: EHS Position */ -#define SCU_SFSP1_14_EHS_Msk (0x01UL << SCU_SFSP1_14_EHS_Pos) /*!< SCU SFSP1_14: EHS Mask */ -#define SCU_SFSP1_14_EZI_Pos 6 /*!< SCU SFSP1_14: EZI Position */ -#define SCU_SFSP1_14_EZI_Msk (0x01UL << SCU_SFSP1_14_EZI_Pos) /*!< SCU SFSP1_14: EZI Mask */ -#define SCU_SFSP1_14_EHD_Pos 8 /*!< SCU SFSP1_14: EHD Position */ -#define SCU_SFSP1_14_EHD_Msk (0x03UL << SCU_SFSP1_14_EHD_Pos) /*!< SCU SFSP1_14: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_15 ------------------------------------------ -#define SCU_SFSP1_15_MODE_Pos 0 /*!< SCU SFSP1_15: MODE Position */ -#define SCU_SFSP1_15_MODE_Msk (0x07UL << SCU_SFSP1_15_MODE_Pos) /*!< SCU SFSP1_15: MODE Mask */ -#define SCU_SFSP1_15_EPD_Pos 3 /*!< SCU SFSP1_15: EPD Position */ -#define SCU_SFSP1_15_EPD_Msk (0x01UL << SCU_SFSP1_15_EPD_Pos) /*!< SCU SFSP1_15: EPD Mask */ -#define SCU_SFSP1_15_EPUN_Pos 4 /*!< SCU SFSP1_15: EPUN Position */ -#define SCU_SFSP1_15_EPUN_Msk (0x01UL << SCU_SFSP1_15_EPUN_Pos) /*!< SCU SFSP1_15: EPUN Mask */ -#define SCU_SFSP1_15_EHS_Pos 5 /*!< SCU SFSP1_15: EHS Position */ -#define SCU_SFSP1_15_EHS_Msk (0x01UL << SCU_SFSP1_15_EHS_Pos) /*!< SCU SFSP1_15: EHS Mask */ -#define SCU_SFSP1_15_EZI_Pos 6 /*!< SCU SFSP1_15: EZI Position */ -#define SCU_SFSP1_15_EZI_Msk (0x01UL << SCU_SFSP1_15_EZI_Pos) /*!< SCU SFSP1_15: EZI Mask */ -#define SCU_SFSP1_15_EHD_Pos 8 /*!< SCU SFSP1_15: EHD Position */ -#define SCU_SFSP1_15_EHD_Msk (0x03UL << SCU_SFSP1_15_EHD_Pos) /*!< SCU SFSP1_15: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_16 ------------------------------------------ -#define SCU_SFSP1_16_MODE_Pos 0 /*!< SCU SFSP1_16: MODE Position */ -#define SCU_SFSP1_16_MODE_Msk (0x07UL << SCU_SFSP1_16_MODE_Pos) /*!< SCU SFSP1_16: MODE Mask */ -#define SCU_SFSP1_16_EPD_Pos 3 /*!< SCU SFSP1_16: EPD Position */ -#define SCU_SFSP1_16_EPD_Msk (0x01UL << SCU_SFSP1_16_EPD_Pos) /*!< SCU SFSP1_16: EPD Mask */ -#define SCU_SFSP1_16_EPUN_Pos 4 /*!< SCU SFSP1_16: EPUN Position */ -#define SCU_SFSP1_16_EPUN_Msk (0x01UL << SCU_SFSP1_16_EPUN_Pos) /*!< SCU SFSP1_16: EPUN Mask */ -#define SCU_SFSP1_16_EHS_Pos 5 /*!< SCU SFSP1_16: EHS Position */ -#define SCU_SFSP1_16_EHS_Msk (0x01UL << SCU_SFSP1_16_EHS_Pos) /*!< SCU SFSP1_16: EHS Mask */ -#define SCU_SFSP1_16_EZI_Pos 6 /*!< SCU SFSP1_16: EZI Position */ -#define SCU_SFSP1_16_EZI_Msk (0x01UL << SCU_SFSP1_16_EZI_Pos) /*!< SCU SFSP1_16: EZI Mask */ -#define SCU_SFSP1_16_EHD_Pos 8 /*!< SCU SFSP1_16: EHD Position */ -#define SCU_SFSP1_16_EHD_Msk (0x03UL << SCU_SFSP1_16_EHD_Pos) /*!< SCU SFSP1_16: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_17 ------------------------------------------ -#define SCU_SFSP1_17_MODE_Pos 0 /*!< SCU SFSP1_17: MODE Position */ -#define SCU_SFSP1_17_MODE_Msk (0x07UL << SCU_SFSP1_17_MODE_Pos) /*!< SCU SFSP1_17: MODE Mask */ -#define SCU_SFSP1_17_EPD_Pos 3 /*!< SCU SFSP1_17: EPD Position */ -#define SCU_SFSP1_17_EPD_Msk (0x01UL << SCU_SFSP1_17_EPD_Pos) /*!< SCU SFSP1_17: EPD Mask */ -#define SCU_SFSP1_17_EPUN_Pos 4 /*!< SCU SFSP1_17: EPUN Position */ -#define SCU_SFSP1_17_EPUN_Msk (0x01UL << SCU_SFSP1_17_EPUN_Pos) /*!< SCU SFSP1_17: EPUN Mask */ -#define SCU_SFSP1_17_EHS_Pos 5 /*!< SCU SFSP1_17: EHS Position */ -#define SCU_SFSP1_17_EHS_Msk (0x01UL << SCU_SFSP1_17_EHS_Pos) /*!< SCU SFSP1_17: EHS Mask */ -#define SCU_SFSP1_17_EZI_Pos 6 /*!< SCU SFSP1_17: EZI Position */ -#define SCU_SFSP1_17_EZI_Msk (0x01UL << SCU_SFSP1_17_EZI_Pos) /*!< SCU SFSP1_17: EZI Mask */ -#define SCU_SFSP1_17_EHD_Pos 8 /*!< SCU SFSP1_17: EHD Position */ -#define SCU_SFSP1_17_EHD_Msk (0x03UL << SCU_SFSP1_17_EHD_Pos) /*!< SCU SFSP1_17: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_18 ------------------------------------------ -#define SCU_SFSP1_18_MODE_Pos 0 /*!< SCU SFSP1_18: MODE Position */ -#define SCU_SFSP1_18_MODE_Msk (0x07UL << SCU_SFSP1_18_MODE_Pos) /*!< SCU SFSP1_18: MODE Mask */ -#define SCU_SFSP1_18_EPD_Pos 3 /*!< SCU SFSP1_18: EPD Position */ -#define SCU_SFSP1_18_EPD_Msk (0x01UL << SCU_SFSP1_18_EPD_Pos) /*!< SCU SFSP1_18: EPD Mask */ -#define SCU_SFSP1_18_EPUN_Pos 4 /*!< SCU SFSP1_18: EPUN Position */ -#define SCU_SFSP1_18_EPUN_Msk (0x01UL << SCU_SFSP1_18_EPUN_Pos) /*!< SCU SFSP1_18: EPUN Mask */ -#define SCU_SFSP1_18_EHS_Pos 5 /*!< SCU SFSP1_18: EHS Position */ -#define SCU_SFSP1_18_EHS_Msk (0x01UL << SCU_SFSP1_18_EHS_Pos) /*!< SCU SFSP1_18: EHS Mask */ -#define SCU_SFSP1_18_EZI_Pos 6 /*!< SCU SFSP1_18: EZI Position */ -#define SCU_SFSP1_18_EZI_Msk (0x01UL << SCU_SFSP1_18_EZI_Pos) /*!< SCU SFSP1_18: EZI Mask */ -#define SCU_SFSP1_18_EHD_Pos 8 /*!< SCU SFSP1_18: EHD Position */ -#define SCU_SFSP1_18_EHD_Msk (0x03UL << SCU_SFSP1_18_EHD_Pos) /*!< SCU SFSP1_18: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_19 ------------------------------------------ -#define SCU_SFSP1_19_MODE_Pos 0 /*!< SCU SFSP1_19: MODE Position */ -#define SCU_SFSP1_19_MODE_Msk (0x07UL << SCU_SFSP1_19_MODE_Pos) /*!< SCU SFSP1_19: MODE Mask */ -#define SCU_SFSP1_19_EPD_Pos 3 /*!< SCU SFSP1_19: EPD Position */ -#define SCU_SFSP1_19_EPD_Msk (0x01UL << SCU_SFSP1_19_EPD_Pos) /*!< SCU SFSP1_19: EPD Mask */ -#define SCU_SFSP1_19_EPUN_Pos 4 /*!< SCU SFSP1_19: EPUN Position */ -#define SCU_SFSP1_19_EPUN_Msk (0x01UL << SCU_SFSP1_19_EPUN_Pos) /*!< SCU SFSP1_19: EPUN Mask */ -#define SCU_SFSP1_19_EHS_Pos 5 /*!< SCU SFSP1_19: EHS Position */ -#define SCU_SFSP1_19_EHS_Msk (0x01UL << SCU_SFSP1_19_EHS_Pos) /*!< SCU SFSP1_19: EHS Mask */ -#define SCU_SFSP1_19_EZI_Pos 6 /*!< SCU SFSP1_19: EZI Position */ -#define SCU_SFSP1_19_EZI_Msk (0x01UL << SCU_SFSP1_19_EZI_Pos) /*!< SCU SFSP1_19: EZI Mask */ -#define SCU_SFSP1_19_EHD_Pos 8 /*!< SCU SFSP1_19: EHD Position */ -#define SCU_SFSP1_19_EHD_Msk (0x03UL << SCU_SFSP1_19_EHD_Pos) /*!< SCU SFSP1_19: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_20 ------------------------------------------ -#define SCU_SFSP1_20_MODE_Pos 0 /*!< SCU SFSP1_20: MODE Position */ -#define SCU_SFSP1_20_MODE_Msk (0x07UL << SCU_SFSP1_20_MODE_Pos) /*!< SCU SFSP1_20: MODE Mask */ -#define SCU_SFSP1_20_EPD_Pos 3 /*!< SCU SFSP1_20: EPD Position */ -#define SCU_SFSP1_20_EPD_Msk (0x01UL << SCU_SFSP1_20_EPD_Pos) /*!< SCU SFSP1_20: EPD Mask */ -#define SCU_SFSP1_20_EPUN_Pos 4 /*!< SCU SFSP1_20: EPUN Position */ -#define SCU_SFSP1_20_EPUN_Msk (0x01UL << SCU_SFSP1_20_EPUN_Pos) /*!< SCU SFSP1_20: EPUN Mask */ -#define SCU_SFSP1_20_EHS_Pos 5 /*!< SCU SFSP1_20: EHS Position */ -#define SCU_SFSP1_20_EHS_Msk (0x01UL << SCU_SFSP1_20_EHS_Pos) /*!< SCU SFSP1_20: EHS Mask */ -#define SCU_SFSP1_20_EZI_Pos 6 /*!< SCU SFSP1_20: EZI Position */ -#define SCU_SFSP1_20_EZI_Msk (0x01UL << SCU_SFSP1_20_EZI_Pos) /*!< SCU SFSP1_20: EZI Mask */ -#define SCU_SFSP1_20_EHD_Pos 8 /*!< SCU SFSP1_20: EHD Position */ -#define SCU_SFSP1_20_EHD_Msk (0x03UL << SCU_SFSP1_20_EHD_Pos) /*!< SCU SFSP1_20: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_0 ------------------------------------------ -#define SCU_SFSP2_0_MODE_Pos 0 /*!< SCU SFSP2_0: MODE Position */ -#define SCU_SFSP2_0_MODE_Msk (0x07UL << SCU_SFSP2_0_MODE_Pos) /*!< SCU SFSP2_0: MODE Mask */ -#define SCU_SFSP2_0_EPD_Pos 3 /*!< SCU SFSP2_0: EPD Position */ -#define SCU_SFSP2_0_EPD_Msk (0x01UL << SCU_SFSP2_0_EPD_Pos) /*!< SCU SFSP2_0: EPD Mask */ -#define SCU_SFSP2_0_EPUN_Pos 4 /*!< SCU SFSP2_0: EPUN Position */ -#define SCU_SFSP2_0_EPUN_Msk (0x01UL << SCU_SFSP2_0_EPUN_Pos) /*!< SCU SFSP2_0: EPUN Mask */ -#define SCU_SFSP2_0_EHS_Pos 5 /*!< SCU SFSP2_0: EHS Position */ -#define SCU_SFSP2_0_EHS_Msk (0x01UL << SCU_SFSP2_0_EHS_Pos) /*!< SCU SFSP2_0: EHS Mask */ -#define SCU_SFSP2_0_EZI_Pos 6 /*!< SCU SFSP2_0: EZI Position */ -#define SCU_SFSP2_0_EZI_Msk (0x01UL << SCU_SFSP2_0_EZI_Pos) /*!< SCU SFSP2_0: EZI Mask */ -#define SCU_SFSP2_0_EHD_Pos 8 /*!< SCU SFSP2_0: EHD Position */ -#define SCU_SFSP2_0_EHD_Msk (0x03UL << SCU_SFSP2_0_EHD_Pos) /*!< SCU SFSP2_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_1 ------------------------------------------ -#define SCU_SFSP2_1_MODE_Pos 0 /*!< SCU SFSP2_1: MODE Position */ -#define SCU_SFSP2_1_MODE_Msk (0x07UL << SCU_SFSP2_1_MODE_Pos) /*!< SCU SFSP2_1: MODE Mask */ -#define SCU_SFSP2_1_EPD_Pos 3 /*!< SCU SFSP2_1: EPD Position */ -#define SCU_SFSP2_1_EPD_Msk (0x01UL << SCU_SFSP2_1_EPD_Pos) /*!< SCU SFSP2_1: EPD Mask */ -#define SCU_SFSP2_1_EPUN_Pos 4 /*!< SCU SFSP2_1: EPUN Position */ -#define SCU_SFSP2_1_EPUN_Msk (0x01UL << SCU_SFSP2_1_EPUN_Pos) /*!< SCU SFSP2_1: EPUN Mask */ -#define SCU_SFSP2_1_EHS_Pos 5 /*!< SCU SFSP2_1: EHS Position */ -#define SCU_SFSP2_1_EHS_Msk (0x01UL << SCU_SFSP2_1_EHS_Pos) /*!< SCU SFSP2_1: EHS Mask */ -#define SCU_SFSP2_1_EZI_Pos 6 /*!< SCU SFSP2_1: EZI Position */ -#define SCU_SFSP2_1_EZI_Msk (0x01UL << SCU_SFSP2_1_EZI_Pos) /*!< SCU SFSP2_1: EZI Mask */ -#define SCU_SFSP2_1_EHD_Pos 8 /*!< SCU SFSP2_1: EHD Position */ -#define SCU_SFSP2_1_EHD_Msk (0x03UL << SCU_SFSP2_1_EHD_Pos) /*!< SCU SFSP2_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_2 ------------------------------------------ -#define SCU_SFSP2_2_MODE_Pos 0 /*!< SCU SFSP2_2: MODE Position */ -#define SCU_SFSP2_2_MODE_Msk (0x07UL << SCU_SFSP2_2_MODE_Pos) /*!< SCU SFSP2_2: MODE Mask */ -#define SCU_SFSP2_2_EPD_Pos 3 /*!< SCU SFSP2_2: EPD Position */ -#define SCU_SFSP2_2_EPD_Msk (0x01UL << SCU_SFSP2_2_EPD_Pos) /*!< SCU SFSP2_2: EPD Mask */ -#define SCU_SFSP2_2_EPUN_Pos 4 /*!< SCU SFSP2_2: EPUN Position */ -#define SCU_SFSP2_2_EPUN_Msk (0x01UL << SCU_SFSP2_2_EPUN_Pos) /*!< SCU SFSP2_2: EPUN Mask */ -#define SCU_SFSP2_2_EHS_Pos 5 /*!< SCU SFSP2_2: EHS Position */ -#define SCU_SFSP2_2_EHS_Msk (0x01UL << SCU_SFSP2_2_EHS_Pos) /*!< SCU SFSP2_2: EHS Mask */ -#define SCU_SFSP2_2_EZI_Pos 6 /*!< SCU SFSP2_2: EZI Position */ -#define SCU_SFSP2_2_EZI_Msk (0x01UL << SCU_SFSP2_2_EZI_Pos) /*!< SCU SFSP2_2: EZI Mask */ -#define SCU_SFSP2_2_EHD_Pos 8 /*!< SCU SFSP2_2: EHD Position */ -#define SCU_SFSP2_2_EHD_Msk (0x03UL << SCU_SFSP2_2_EHD_Pos) /*!< SCU SFSP2_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_3 ------------------------------------------ -#define SCU_SFSP2_3_MODE_Pos 0 /*!< SCU SFSP2_3: MODE Position */ -#define SCU_SFSP2_3_MODE_Msk (0x07UL << SCU_SFSP2_3_MODE_Pos) /*!< SCU SFSP2_3: MODE Mask */ -#define SCU_SFSP2_3_EPD_Pos 3 /*!< SCU SFSP2_3: EPD Position */ -#define SCU_SFSP2_3_EPD_Msk (0x01UL << SCU_SFSP2_3_EPD_Pos) /*!< SCU SFSP2_3: EPD Mask */ -#define SCU_SFSP2_3_EPUN_Pos 4 /*!< SCU SFSP2_3: EPUN Position */ -#define SCU_SFSP2_3_EPUN_Msk (0x01UL << SCU_SFSP2_3_EPUN_Pos) /*!< SCU SFSP2_3: EPUN Mask */ -#define SCU_SFSP2_3_EHS_Pos 5 /*!< SCU SFSP2_3: EHS Position */ -#define SCU_SFSP2_3_EHS_Msk (0x01UL << SCU_SFSP2_3_EHS_Pos) /*!< SCU SFSP2_3: EHS Mask */ -#define SCU_SFSP2_3_EZI_Pos 6 /*!< SCU SFSP2_3: EZI Position */ -#define SCU_SFSP2_3_EZI_Msk (0x01UL << SCU_SFSP2_3_EZI_Pos) /*!< SCU SFSP2_3: EZI Mask */ -#define SCU_SFSP2_3_EHD_Pos 8 /*!< SCU SFSP2_3: EHD Position */ -#define SCU_SFSP2_3_EHD_Msk (0x03UL << SCU_SFSP2_3_EHD_Pos) /*!< SCU SFSP2_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_4 ------------------------------------------ -#define SCU_SFSP2_4_MODE_Pos 0 /*!< SCU SFSP2_4: MODE Position */ -#define SCU_SFSP2_4_MODE_Msk (0x07UL << SCU_SFSP2_4_MODE_Pos) /*!< SCU SFSP2_4: MODE Mask */ -#define SCU_SFSP2_4_EPD_Pos 3 /*!< SCU SFSP2_4: EPD Position */ -#define SCU_SFSP2_4_EPD_Msk (0x01UL << SCU_SFSP2_4_EPD_Pos) /*!< SCU SFSP2_4: EPD Mask */ -#define SCU_SFSP2_4_EPUN_Pos 4 /*!< SCU SFSP2_4: EPUN Position */ -#define SCU_SFSP2_4_EPUN_Msk (0x01UL << SCU_SFSP2_4_EPUN_Pos) /*!< SCU SFSP2_4: EPUN Mask */ -#define SCU_SFSP2_4_EHS_Pos 5 /*!< SCU SFSP2_4: EHS Position */ -#define SCU_SFSP2_4_EHS_Msk (0x01UL << SCU_SFSP2_4_EHS_Pos) /*!< SCU SFSP2_4: EHS Mask */ -#define SCU_SFSP2_4_EZI_Pos 6 /*!< SCU SFSP2_4: EZI Position */ -#define SCU_SFSP2_4_EZI_Msk (0x01UL << SCU_SFSP2_4_EZI_Pos) /*!< SCU SFSP2_4: EZI Mask */ -#define SCU_SFSP2_4_EHD_Pos 8 /*!< SCU SFSP2_4: EHD Position */ -#define SCU_SFSP2_4_EHD_Msk (0x03UL << SCU_SFSP2_4_EHD_Pos) /*!< SCU SFSP2_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_5 ------------------------------------------ -#define SCU_SFSP2_5_MODE_Pos 0 /*!< SCU SFSP2_5: MODE Position */ -#define SCU_SFSP2_5_MODE_Msk (0x07UL << SCU_SFSP2_5_MODE_Pos) /*!< SCU SFSP2_5: MODE Mask */ -#define SCU_SFSP2_5_EPD_Pos 3 /*!< SCU SFSP2_5: EPD Position */ -#define SCU_SFSP2_5_EPD_Msk (0x01UL << SCU_SFSP2_5_EPD_Pos) /*!< SCU SFSP2_5: EPD Mask */ -#define SCU_SFSP2_5_EPUN_Pos 4 /*!< SCU SFSP2_5: EPUN Position */ -#define SCU_SFSP2_5_EPUN_Msk (0x01UL << SCU_SFSP2_5_EPUN_Pos) /*!< SCU SFSP2_5: EPUN Mask */ -#define SCU_SFSP2_5_EHS_Pos 5 /*!< SCU SFSP2_5: EHS Position */ -#define SCU_SFSP2_5_EHS_Msk (0x01UL << SCU_SFSP2_5_EHS_Pos) /*!< SCU SFSP2_5: EHS Mask */ -#define SCU_SFSP2_5_EZI_Pos 6 /*!< SCU SFSP2_5: EZI Position */ -#define SCU_SFSP2_5_EZI_Msk (0x01UL << SCU_SFSP2_5_EZI_Pos) /*!< SCU SFSP2_5: EZI Mask */ -#define SCU_SFSP2_5_EHD_Pos 8 /*!< SCU SFSP2_5: EHD Position */ -#define SCU_SFSP2_5_EHD_Msk (0x03UL << SCU_SFSP2_5_EHD_Pos) /*!< SCU SFSP2_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_6 ------------------------------------------ -#define SCU_SFSP2_6_MODE_Pos 0 /*!< SCU SFSP2_6: MODE Position */ -#define SCU_SFSP2_6_MODE_Msk (0x07UL << SCU_SFSP2_6_MODE_Pos) /*!< SCU SFSP2_6: MODE Mask */ -#define SCU_SFSP2_6_EPD_Pos 3 /*!< SCU SFSP2_6: EPD Position */ -#define SCU_SFSP2_6_EPD_Msk (0x01UL << SCU_SFSP2_6_EPD_Pos) /*!< SCU SFSP2_6: EPD Mask */ -#define SCU_SFSP2_6_EPUN_Pos 4 /*!< SCU SFSP2_6: EPUN Position */ -#define SCU_SFSP2_6_EPUN_Msk (0x01UL << SCU_SFSP2_6_EPUN_Pos) /*!< SCU SFSP2_6: EPUN Mask */ -#define SCU_SFSP2_6_EHS_Pos 5 /*!< SCU SFSP2_6: EHS Position */ -#define SCU_SFSP2_6_EHS_Msk (0x01UL << SCU_SFSP2_6_EHS_Pos) /*!< SCU SFSP2_6: EHS Mask */ -#define SCU_SFSP2_6_EZI_Pos 6 /*!< SCU SFSP2_6: EZI Position */ -#define SCU_SFSP2_6_EZI_Msk (0x01UL << SCU_SFSP2_6_EZI_Pos) /*!< SCU SFSP2_6: EZI Mask */ -#define SCU_SFSP2_6_EHD_Pos 8 /*!< SCU SFSP2_6: EHD Position */ -#define SCU_SFSP2_6_EHD_Msk (0x03UL << SCU_SFSP2_6_EHD_Pos) /*!< SCU SFSP2_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_7 ------------------------------------------ -#define SCU_SFSP2_7_MODE_Pos 0 /*!< SCU SFSP2_7: MODE Position */ -#define SCU_SFSP2_7_MODE_Msk (0x07UL << SCU_SFSP2_7_MODE_Pos) /*!< SCU SFSP2_7: MODE Mask */ -#define SCU_SFSP2_7_EPD_Pos 3 /*!< SCU SFSP2_7: EPD Position */ -#define SCU_SFSP2_7_EPD_Msk (0x01UL << SCU_SFSP2_7_EPD_Pos) /*!< SCU SFSP2_7: EPD Mask */ -#define SCU_SFSP2_7_EPUN_Pos 4 /*!< SCU SFSP2_7: EPUN Position */ -#define SCU_SFSP2_7_EPUN_Msk (0x01UL << SCU_SFSP2_7_EPUN_Pos) /*!< SCU SFSP2_7: EPUN Mask */ -#define SCU_SFSP2_7_EHS_Pos 5 /*!< SCU SFSP2_7: EHS Position */ -#define SCU_SFSP2_7_EHS_Msk (0x01UL << SCU_SFSP2_7_EHS_Pos) /*!< SCU SFSP2_7: EHS Mask */ -#define SCU_SFSP2_7_EZI_Pos 6 /*!< SCU SFSP2_7: EZI Position */ -#define SCU_SFSP2_7_EZI_Msk (0x01UL << SCU_SFSP2_7_EZI_Pos) /*!< SCU SFSP2_7: EZI Mask */ -#define SCU_SFSP2_7_EHD_Pos 8 /*!< SCU SFSP2_7: EHD Position */ -#define SCU_SFSP2_7_EHD_Msk (0x03UL << SCU_SFSP2_7_EHD_Pos) /*!< SCU SFSP2_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_8 ------------------------------------------ -#define SCU_SFSP2_8_MODE_Pos 0 /*!< SCU SFSP2_8: MODE Position */ -#define SCU_SFSP2_8_MODE_Msk (0x07UL << SCU_SFSP2_8_MODE_Pos) /*!< SCU SFSP2_8: MODE Mask */ -#define SCU_SFSP2_8_EPD_Pos 3 /*!< SCU SFSP2_8: EPD Position */ -#define SCU_SFSP2_8_EPD_Msk (0x01UL << SCU_SFSP2_8_EPD_Pos) /*!< SCU SFSP2_8: EPD Mask */ -#define SCU_SFSP2_8_EPUN_Pos 4 /*!< SCU SFSP2_8: EPUN Position */ -#define SCU_SFSP2_8_EPUN_Msk (0x01UL << SCU_SFSP2_8_EPUN_Pos) /*!< SCU SFSP2_8: EPUN Mask */ -#define SCU_SFSP2_8_EHS_Pos 5 /*!< SCU SFSP2_8: EHS Position */ -#define SCU_SFSP2_8_EHS_Msk (0x01UL << SCU_SFSP2_8_EHS_Pos) /*!< SCU SFSP2_8: EHS Mask */ -#define SCU_SFSP2_8_EZI_Pos 6 /*!< SCU SFSP2_8: EZI Position */ -#define SCU_SFSP2_8_EZI_Msk (0x01UL << SCU_SFSP2_8_EZI_Pos) /*!< SCU SFSP2_8: EZI Mask */ -#define SCU_SFSP2_8_EHD_Pos 8 /*!< SCU SFSP2_8: EHD Position */ -#define SCU_SFSP2_8_EHD_Msk (0x03UL << SCU_SFSP2_8_EHD_Pos) /*!< SCU SFSP2_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_9 ------------------------------------------ -#define SCU_SFSP2_9_MODE_Pos 0 /*!< SCU SFSP2_9: MODE Position */ -#define SCU_SFSP2_9_MODE_Msk (0x07UL << SCU_SFSP2_9_MODE_Pos) /*!< SCU SFSP2_9: MODE Mask */ -#define SCU_SFSP2_9_EPD_Pos 3 /*!< SCU SFSP2_9: EPD Position */ -#define SCU_SFSP2_9_EPD_Msk (0x01UL << SCU_SFSP2_9_EPD_Pos) /*!< SCU SFSP2_9: EPD Mask */ -#define SCU_SFSP2_9_EPUN_Pos 4 /*!< SCU SFSP2_9: EPUN Position */ -#define SCU_SFSP2_9_EPUN_Msk (0x01UL << SCU_SFSP2_9_EPUN_Pos) /*!< SCU SFSP2_9: EPUN Mask */ -#define SCU_SFSP2_9_EHS_Pos 5 /*!< SCU SFSP2_9: EHS Position */ -#define SCU_SFSP2_9_EHS_Msk (0x01UL << SCU_SFSP2_9_EHS_Pos) /*!< SCU SFSP2_9: EHS Mask */ -#define SCU_SFSP2_9_EZI_Pos 6 /*!< SCU SFSP2_9: EZI Position */ -#define SCU_SFSP2_9_EZI_Msk (0x01UL << SCU_SFSP2_9_EZI_Pos) /*!< SCU SFSP2_9: EZI Mask */ -#define SCU_SFSP2_9_EHD_Pos 8 /*!< SCU SFSP2_9: EHD Position */ -#define SCU_SFSP2_9_EHD_Msk (0x03UL << SCU_SFSP2_9_EHD_Pos) /*!< SCU SFSP2_9: EHD Mask */ - -// -------------------------------------- SCU_SFSP2_10 ------------------------------------------ -#define SCU_SFSP2_10_MODE_Pos 0 /*!< SCU SFSP2_10: MODE Position */ -#define SCU_SFSP2_10_MODE_Msk (0x07UL << SCU_SFSP2_10_MODE_Pos) /*!< SCU SFSP2_10: MODE Mask */ -#define SCU_SFSP2_10_EPD_Pos 3 /*!< SCU SFSP2_10: EPD Position */ -#define SCU_SFSP2_10_EPD_Msk (0x01UL << SCU_SFSP2_10_EPD_Pos) /*!< SCU SFSP2_10: EPD Mask */ -#define SCU_SFSP2_10_EPUN_Pos 4 /*!< SCU SFSP2_10: EPUN Position */ -#define SCU_SFSP2_10_EPUN_Msk (0x01UL << SCU_SFSP2_10_EPUN_Pos) /*!< SCU SFSP2_10: EPUN Mask */ -#define SCU_SFSP2_10_EHS_Pos 5 /*!< SCU SFSP2_10: EHS Position */ -#define SCU_SFSP2_10_EHS_Msk (0x01UL << SCU_SFSP2_10_EHS_Pos) /*!< SCU SFSP2_10: EHS Mask */ -#define SCU_SFSP2_10_EZI_Pos 6 /*!< SCU SFSP2_10: EZI Position */ -#define SCU_SFSP2_10_EZI_Msk (0x01UL << SCU_SFSP2_10_EZI_Pos) /*!< SCU SFSP2_10: EZI Mask */ -#define SCU_SFSP2_10_EHD_Pos 8 /*!< SCU SFSP2_10: EHD Position */ -#define SCU_SFSP2_10_EHD_Msk (0x03UL << SCU_SFSP2_10_EHD_Pos) /*!< SCU SFSP2_10: EHD Mask */ - -// -------------------------------------- SCU_SFSP2_11 ------------------------------------------ -#define SCU_SFSP2_11_MODE_Pos 0 /*!< SCU SFSP2_11: MODE Position */ -#define SCU_SFSP2_11_MODE_Msk (0x07UL << SCU_SFSP2_11_MODE_Pos) /*!< SCU SFSP2_11: MODE Mask */ -#define SCU_SFSP2_11_EPD_Pos 3 /*!< SCU SFSP2_11: EPD Position */ -#define SCU_SFSP2_11_EPD_Msk (0x01UL << SCU_SFSP2_11_EPD_Pos) /*!< SCU SFSP2_11: EPD Mask */ -#define SCU_SFSP2_11_EPUN_Pos 4 /*!< SCU SFSP2_11: EPUN Position */ -#define SCU_SFSP2_11_EPUN_Msk (0x01UL << SCU_SFSP2_11_EPUN_Pos) /*!< SCU SFSP2_11: EPUN Mask */ -#define SCU_SFSP2_11_EHS_Pos 5 /*!< SCU SFSP2_11: EHS Position */ -#define SCU_SFSP2_11_EHS_Msk (0x01UL << SCU_SFSP2_11_EHS_Pos) /*!< SCU SFSP2_11: EHS Mask */ -#define SCU_SFSP2_11_EZI_Pos 6 /*!< SCU SFSP2_11: EZI Position */ -#define SCU_SFSP2_11_EZI_Msk (0x01UL << SCU_SFSP2_11_EZI_Pos) /*!< SCU SFSP2_11: EZI Mask */ -#define SCU_SFSP2_11_EHD_Pos 8 /*!< SCU SFSP2_11: EHD Position */ -#define SCU_SFSP2_11_EHD_Msk (0x03UL << SCU_SFSP2_11_EHD_Pos) /*!< SCU SFSP2_11: EHD Mask */ - -// -------------------------------------- SCU_SFSP2_12 ------------------------------------------ -#define SCU_SFSP2_12_MODE_Pos 0 /*!< SCU SFSP2_12: MODE Position */ -#define SCU_SFSP2_12_MODE_Msk (0x07UL << SCU_SFSP2_12_MODE_Pos) /*!< SCU SFSP2_12: MODE Mask */ -#define SCU_SFSP2_12_EPD_Pos 3 /*!< SCU SFSP2_12: EPD Position */ -#define SCU_SFSP2_12_EPD_Msk (0x01UL << SCU_SFSP2_12_EPD_Pos) /*!< SCU SFSP2_12: EPD Mask */ -#define SCU_SFSP2_12_EPUN_Pos 4 /*!< SCU SFSP2_12: EPUN Position */ -#define SCU_SFSP2_12_EPUN_Msk (0x01UL << SCU_SFSP2_12_EPUN_Pos) /*!< SCU SFSP2_12: EPUN Mask */ -#define SCU_SFSP2_12_EHS_Pos 5 /*!< SCU SFSP2_12: EHS Position */ -#define SCU_SFSP2_12_EHS_Msk (0x01UL << SCU_SFSP2_12_EHS_Pos) /*!< SCU SFSP2_12: EHS Mask */ -#define SCU_SFSP2_12_EZI_Pos 6 /*!< SCU SFSP2_12: EZI Position */ -#define SCU_SFSP2_12_EZI_Msk (0x01UL << SCU_SFSP2_12_EZI_Pos) /*!< SCU SFSP2_12: EZI Mask */ -#define SCU_SFSP2_12_EHD_Pos 8 /*!< SCU SFSP2_12: EHD Position */ -#define SCU_SFSP2_12_EHD_Msk (0x03UL << SCU_SFSP2_12_EHD_Pos) /*!< SCU SFSP2_12: EHD Mask */ - -// -------------------------------------- SCU_SFSP2_13 ------------------------------------------ -#define SCU_SFSP2_13_MODE_Pos 0 /*!< SCU SFSP2_13: MODE Position */ -#define SCU_SFSP2_13_MODE_Msk (0x07UL << SCU_SFSP2_13_MODE_Pos) /*!< SCU SFSP2_13: MODE Mask */ -#define SCU_SFSP2_13_EPD_Pos 3 /*!< SCU SFSP2_13: EPD Position */ -#define SCU_SFSP2_13_EPD_Msk (0x01UL << SCU_SFSP2_13_EPD_Pos) /*!< SCU SFSP2_13: EPD Mask */ -#define SCU_SFSP2_13_EPUN_Pos 4 /*!< SCU SFSP2_13: EPUN Position */ -#define SCU_SFSP2_13_EPUN_Msk (0x01UL << SCU_SFSP2_13_EPUN_Pos) /*!< SCU SFSP2_13: EPUN Mask */ -#define SCU_SFSP2_13_EHS_Pos 5 /*!< SCU SFSP2_13: EHS Position */ -#define SCU_SFSP2_13_EHS_Msk (0x01UL << SCU_SFSP2_13_EHS_Pos) /*!< SCU SFSP2_13: EHS Mask */ -#define SCU_SFSP2_13_EZI_Pos 6 /*!< SCU SFSP2_13: EZI Position */ -#define SCU_SFSP2_13_EZI_Msk (0x01UL << SCU_SFSP2_13_EZI_Pos) /*!< SCU SFSP2_13: EZI Mask */ -#define SCU_SFSP2_13_EHD_Pos 8 /*!< SCU SFSP2_13: EHD Position */ -#define SCU_SFSP2_13_EHD_Msk (0x03UL << SCU_SFSP2_13_EHD_Pos) /*!< SCU SFSP2_13: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_0 ------------------------------------------ -#define SCU_SFSP3_0_MODE_Pos 0 /*!< SCU SFSP3_0: MODE Position */ -#define SCU_SFSP3_0_MODE_Msk (0x07UL << SCU_SFSP3_0_MODE_Pos) /*!< SCU SFSP3_0: MODE Mask */ -#define SCU_SFSP3_0_EPD_Pos 3 /*!< SCU SFSP3_0: EPD Position */ -#define SCU_SFSP3_0_EPD_Msk (0x01UL << SCU_SFSP3_0_EPD_Pos) /*!< SCU SFSP3_0: EPD Mask */ -#define SCU_SFSP3_0_EPUN_Pos 4 /*!< SCU SFSP3_0: EPUN Position */ -#define SCU_SFSP3_0_EPUN_Msk (0x01UL << SCU_SFSP3_0_EPUN_Pos) /*!< SCU SFSP3_0: EPUN Mask */ -#define SCU_SFSP3_0_EHS_Pos 5 /*!< SCU SFSP3_0: EHS Position */ -#define SCU_SFSP3_0_EHS_Msk (0x01UL << SCU_SFSP3_0_EHS_Pos) /*!< SCU SFSP3_0: EHS Mask */ -#define SCU_SFSP3_0_EZI_Pos 6 /*!< SCU SFSP3_0: EZI Position */ -#define SCU_SFSP3_0_EZI_Msk (0x01UL << SCU_SFSP3_0_EZI_Pos) /*!< SCU SFSP3_0: EZI Mask */ -#define SCU_SFSP3_0_EHD_Pos 8 /*!< SCU SFSP3_0: EHD Position */ -#define SCU_SFSP3_0_EHD_Msk (0x03UL << SCU_SFSP3_0_EHD_Pos) /*!< SCU SFSP3_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_1 ------------------------------------------ -#define SCU_SFSP3_1_MODE_Pos 0 /*!< SCU SFSP3_1: MODE Position */ -#define SCU_SFSP3_1_MODE_Msk (0x07UL << SCU_SFSP3_1_MODE_Pos) /*!< SCU SFSP3_1: MODE Mask */ -#define SCU_SFSP3_1_EPD_Pos 3 /*!< SCU SFSP3_1: EPD Position */ -#define SCU_SFSP3_1_EPD_Msk (0x01UL << SCU_SFSP3_1_EPD_Pos) /*!< SCU SFSP3_1: EPD Mask */ -#define SCU_SFSP3_1_EPUN_Pos 4 /*!< SCU SFSP3_1: EPUN Position */ -#define SCU_SFSP3_1_EPUN_Msk (0x01UL << SCU_SFSP3_1_EPUN_Pos) /*!< SCU SFSP3_1: EPUN Mask */ -#define SCU_SFSP3_1_EHS_Pos 5 /*!< SCU SFSP3_1: EHS Position */ -#define SCU_SFSP3_1_EHS_Msk (0x01UL << SCU_SFSP3_1_EHS_Pos) /*!< SCU SFSP3_1: EHS Mask */ -#define SCU_SFSP3_1_EZI_Pos 6 /*!< SCU SFSP3_1: EZI Position */ -#define SCU_SFSP3_1_EZI_Msk (0x01UL << SCU_SFSP3_1_EZI_Pos) /*!< SCU SFSP3_1: EZI Mask */ -#define SCU_SFSP3_1_EHD_Pos 8 /*!< SCU SFSP3_1: EHD Position */ -#define SCU_SFSP3_1_EHD_Msk (0x03UL << SCU_SFSP3_1_EHD_Pos) /*!< SCU SFSP3_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_2 ------------------------------------------ -#define SCU_SFSP3_2_MODE_Pos 0 /*!< SCU SFSP3_2: MODE Position */ -#define SCU_SFSP3_2_MODE_Msk (0x07UL << SCU_SFSP3_2_MODE_Pos) /*!< SCU SFSP3_2: MODE Mask */ -#define SCU_SFSP3_2_EPD_Pos 3 /*!< SCU SFSP3_2: EPD Position */ -#define SCU_SFSP3_2_EPD_Msk (0x01UL << SCU_SFSP3_2_EPD_Pos) /*!< SCU SFSP3_2: EPD Mask */ -#define SCU_SFSP3_2_EPUN_Pos 4 /*!< SCU SFSP3_2: EPUN Position */ -#define SCU_SFSP3_2_EPUN_Msk (0x01UL << SCU_SFSP3_2_EPUN_Pos) /*!< SCU SFSP3_2: EPUN Mask */ -#define SCU_SFSP3_2_EHS_Pos 5 /*!< SCU SFSP3_2: EHS Position */ -#define SCU_SFSP3_2_EHS_Msk (0x01UL << SCU_SFSP3_2_EHS_Pos) /*!< SCU SFSP3_2: EHS Mask */ -#define SCU_SFSP3_2_EZI_Pos 6 /*!< SCU SFSP3_2: EZI Position */ -#define SCU_SFSP3_2_EZI_Msk (0x01UL << SCU_SFSP3_2_EZI_Pos) /*!< SCU SFSP3_2: EZI Mask */ -#define SCU_SFSP3_2_EHD_Pos 8 /*!< SCU SFSP3_2: EHD Position */ -#define SCU_SFSP3_2_EHD_Msk (0x03UL << SCU_SFSP3_2_EHD_Pos) /*!< SCU SFSP3_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_3 ------------------------------------------ -#define SCU_SFSP3_3_MODE_Pos 0 /*!< SCU SFSP3_3: MODE Position */ -#define SCU_SFSP3_3_MODE_Msk (0x07UL << SCU_SFSP3_3_MODE_Pos) /*!< SCU SFSP3_3: MODE Mask */ -#define SCU_SFSP3_3_EPD_Pos 3 /*!< SCU SFSP3_3: EPD Position */ -#define SCU_SFSP3_3_EPD_Msk (0x01UL << SCU_SFSP3_3_EPD_Pos) /*!< SCU SFSP3_3: EPD Mask */ -#define SCU_SFSP3_3_EPUN_Pos 4 /*!< SCU SFSP3_3: EPUN Position */ -#define SCU_SFSP3_3_EPUN_Msk (0x01UL << SCU_SFSP3_3_EPUN_Pos) /*!< SCU SFSP3_3: EPUN Mask */ -#define SCU_SFSP3_3_EHS_Pos 5 /*!< SCU SFSP3_3: EHS Position */ -#define SCU_SFSP3_3_EHS_Msk (0x01UL << SCU_SFSP3_3_EHS_Pos) /*!< SCU SFSP3_3: EHS Mask */ -#define SCU_SFSP3_3_EZI_Pos 6 /*!< SCU SFSP3_3: EZI Position */ -#define SCU_SFSP3_3_EZI_Msk (0x01UL << SCU_SFSP3_3_EZI_Pos) /*!< SCU SFSP3_3: EZI Mask */ -#define SCU_SFSP3_3_EHD_Pos 8 /*!< SCU SFSP3_3: EHD Position */ -#define SCU_SFSP3_3_EHD_Msk (0x03UL << SCU_SFSP3_3_EHD_Pos) /*!< SCU SFSP3_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_4 ------------------------------------------ -#define SCU_SFSP3_4_MODE_Pos 0 /*!< SCU SFSP3_4: MODE Position */ -#define SCU_SFSP3_4_MODE_Msk (0x07UL << SCU_SFSP3_4_MODE_Pos) /*!< SCU SFSP3_4: MODE Mask */ -#define SCU_SFSP3_4_EPD_Pos 3 /*!< SCU SFSP3_4: EPD Position */ -#define SCU_SFSP3_4_EPD_Msk (0x01UL << SCU_SFSP3_4_EPD_Pos) /*!< SCU SFSP3_4: EPD Mask */ -#define SCU_SFSP3_4_EPUN_Pos 4 /*!< SCU SFSP3_4: EPUN Position */ -#define SCU_SFSP3_4_EPUN_Msk (0x01UL << SCU_SFSP3_4_EPUN_Pos) /*!< SCU SFSP3_4: EPUN Mask */ -#define SCU_SFSP3_4_EHS_Pos 5 /*!< SCU SFSP3_4: EHS Position */ -#define SCU_SFSP3_4_EHS_Msk (0x01UL << SCU_SFSP3_4_EHS_Pos) /*!< SCU SFSP3_4: EHS Mask */ -#define SCU_SFSP3_4_EZI_Pos 6 /*!< SCU SFSP3_4: EZI Position */ -#define SCU_SFSP3_4_EZI_Msk (0x01UL << SCU_SFSP3_4_EZI_Pos) /*!< SCU SFSP3_4: EZI Mask */ -#define SCU_SFSP3_4_EHD_Pos 8 /*!< SCU SFSP3_4: EHD Position */ -#define SCU_SFSP3_4_EHD_Msk (0x03UL << SCU_SFSP3_4_EHD_Pos) /*!< SCU SFSP3_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_5 ------------------------------------------ -#define SCU_SFSP3_5_MODE_Pos 0 /*!< SCU SFSP3_5: MODE Position */ -#define SCU_SFSP3_5_MODE_Msk (0x07UL << SCU_SFSP3_5_MODE_Pos) /*!< SCU SFSP3_5: MODE Mask */ -#define SCU_SFSP3_5_EPD_Pos 3 /*!< SCU SFSP3_5: EPD Position */ -#define SCU_SFSP3_5_EPD_Msk (0x01UL << SCU_SFSP3_5_EPD_Pos) /*!< SCU SFSP3_5: EPD Mask */ -#define SCU_SFSP3_5_EPUN_Pos 4 /*!< SCU SFSP3_5: EPUN Position */ -#define SCU_SFSP3_5_EPUN_Msk (0x01UL << SCU_SFSP3_5_EPUN_Pos) /*!< SCU SFSP3_5: EPUN Mask */ -#define SCU_SFSP3_5_EHS_Pos 5 /*!< SCU SFSP3_5: EHS Position */ -#define SCU_SFSP3_5_EHS_Msk (0x01UL << SCU_SFSP3_5_EHS_Pos) /*!< SCU SFSP3_5: EHS Mask */ -#define SCU_SFSP3_5_EZI_Pos 6 /*!< SCU SFSP3_5: EZI Position */ -#define SCU_SFSP3_5_EZI_Msk (0x01UL << SCU_SFSP3_5_EZI_Pos) /*!< SCU SFSP3_5: EZI Mask */ -#define SCU_SFSP3_5_EHD_Pos 8 /*!< SCU SFSP3_5: EHD Position */ -#define SCU_SFSP3_5_EHD_Msk (0x03UL << SCU_SFSP3_5_EHD_Pos) /*!< SCU SFSP3_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_6 ------------------------------------------ -#define SCU_SFSP3_6_MODE_Pos 0 /*!< SCU SFSP3_6: MODE Position */ -#define SCU_SFSP3_6_MODE_Msk (0x07UL << SCU_SFSP3_6_MODE_Pos) /*!< SCU SFSP3_6: MODE Mask */ -#define SCU_SFSP3_6_EPD_Pos 3 /*!< SCU SFSP3_6: EPD Position */ -#define SCU_SFSP3_6_EPD_Msk (0x01UL << SCU_SFSP3_6_EPD_Pos) /*!< SCU SFSP3_6: EPD Mask */ -#define SCU_SFSP3_6_EPUN_Pos 4 /*!< SCU SFSP3_6: EPUN Position */ -#define SCU_SFSP3_6_EPUN_Msk (0x01UL << SCU_SFSP3_6_EPUN_Pos) /*!< SCU SFSP3_6: EPUN Mask */ -#define SCU_SFSP3_6_EHS_Pos 5 /*!< SCU SFSP3_6: EHS Position */ -#define SCU_SFSP3_6_EHS_Msk (0x01UL << SCU_SFSP3_6_EHS_Pos) /*!< SCU SFSP3_6: EHS Mask */ -#define SCU_SFSP3_6_EZI_Pos 6 /*!< SCU SFSP3_6: EZI Position */ -#define SCU_SFSP3_6_EZI_Msk (0x01UL << SCU_SFSP3_6_EZI_Pos) /*!< SCU SFSP3_6: EZI Mask */ -#define SCU_SFSP3_6_EHD_Pos 8 /*!< SCU SFSP3_6: EHD Position */ -#define SCU_SFSP3_6_EHD_Msk (0x03UL << SCU_SFSP3_6_EHD_Pos) /*!< SCU SFSP3_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_7 ------------------------------------------ -#define SCU_SFSP3_7_MODE_Pos 0 /*!< SCU SFSP3_7: MODE Position */ -#define SCU_SFSP3_7_MODE_Msk (0x07UL << SCU_SFSP3_7_MODE_Pos) /*!< SCU SFSP3_7: MODE Mask */ -#define SCU_SFSP3_7_EPD_Pos 3 /*!< SCU SFSP3_7: EPD Position */ -#define SCU_SFSP3_7_EPD_Msk (0x01UL << SCU_SFSP3_7_EPD_Pos) /*!< SCU SFSP3_7: EPD Mask */ -#define SCU_SFSP3_7_EPUN_Pos 4 /*!< SCU SFSP3_7: EPUN Position */ -#define SCU_SFSP3_7_EPUN_Msk (0x01UL << SCU_SFSP3_7_EPUN_Pos) /*!< SCU SFSP3_7: EPUN Mask */ -#define SCU_SFSP3_7_EHS_Pos 5 /*!< SCU SFSP3_7: EHS Position */ -#define SCU_SFSP3_7_EHS_Msk (0x01UL << SCU_SFSP3_7_EHS_Pos) /*!< SCU SFSP3_7: EHS Mask */ -#define SCU_SFSP3_7_EZI_Pos 6 /*!< SCU SFSP3_7: EZI Position */ -#define SCU_SFSP3_7_EZI_Msk (0x01UL << SCU_SFSP3_7_EZI_Pos) /*!< SCU SFSP3_7: EZI Mask */ -#define SCU_SFSP3_7_EHD_Pos 8 /*!< SCU SFSP3_7: EHD Position */ -#define SCU_SFSP3_7_EHD_Msk (0x03UL << SCU_SFSP3_7_EHD_Pos) /*!< SCU SFSP3_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_8 ------------------------------------------ -#define SCU_SFSP3_8_MODE_Pos 0 /*!< SCU SFSP3_8: MODE Position */ -#define SCU_SFSP3_8_MODE_Msk (0x07UL << SCU_SFSP3_8_MODE_Pos) /*!< SCU SFSP3_8: MODE Mask */ -#define SCU_SFSP3_8_EPD_Pos 3 /*!< SCU SFSP3_8: EPD Position */ -#define SCU_SFSP3_8_EPD_Msk (0x01UL << SCU_SFSP3_8_EPD_Pos) /*!< SCU SFSP3_8: EPD Mask */ -#define SCU_SFSP3_8_EPUN_Pos 4 /*!< SCU SFSP3_8: EPUN Position */ -#define SCU_SFSP3_8_EPUN_Msk (0x01UL << SCU_SFSP3_8_EPUN_Pos) /*!< SCU SFSP3_8: EPUN Mask */ -#define SCU_SFSP3_8_EHS_Pos 5 /*!< SCU SFSP3_8: EHS Position */ -#define SCU_SFSP3_8_EHS_Msk (0x01UL << SCU_SFSP3_8_EHS_Pos) /*!< SCU SFSP3_8: EHS Mask */ -#define SCU_SFSP3_8_EZI_Pos 6 /*!< SCU SFSP3_8: EZI Position */ -#define SCU_SFSP3_8_EZI_Msk (0x01UL << SCU_SFSP3_8_EZI_Pos) /*!< SCU SFSP3_8: EZI Mask */ -#define SCU_SFSP3_8_EHD_Pos 8 /*!< SCU SFSP3_8: EHD Position */ -#define SCU_SFSP3_8_EHD_Msk (0x03UL << SCU_SFSP3_8_EHD_Pos) /*!< SCU SFSP3_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_0 ------------------------------------------ -#define SCU_SFSP4_0_MODE_Pos 0 /*!< SCU SFSP4_0: MODE Position */ -#define SCU_SFSP4_0_MODE_Msk (0x07UL << SCU_SFSP4_0_MODE_Pos) /*!< SCU SFSP4_0: MODE Mask */ -#define SCU_SFSP4_0_EPD_Pos 3 /*!< SCU SFSP4_0: EPD Position */ -#define SCU_SFSP4_0_EPD_Msk (0x01UL << SCU_SFSP4_0_EPD_Pos) /*!< SCU SFSP4_0: EPD Mask */ -#define SCU_SFSP4_0_EPUN_Pos 4 /*!< SCU SFSP4_0: EPUN Position */ -#define SCU_SFSP4_0_EPUN_Msk (0x01UL << SCU_SFSP4_0_EPUN_Pos) /*!< SCU SFSP4_0: EPUN Mask */ -#define SCU_SFSP4_0_EHS_Pos 5 /*!< SCU SFSP4_0: EHS Position */ -#define SCU_SFSP4_0_EHS_Msk (0x01UL << SCU_SFSP4_0_EHS_Pos) /*!< SCU SFSP4_0: EHS Mask */ -#define SCU_SFSP4_0_EZI_Pos 6 /*!< SCU SFSP4_0: EZI Position */ -#define SCU_SFSP4_0_EZI_Msk (0x01UL << SCU_SFSP4_0_EZI_Pos) /*!< SCU SFSP4_0: EZI Mask */ -#define SCU_SFSP4_0_EHD_Pos 8 /*!< SCU SFSP4_0: EHD Position */ -#define SCU_SFSP4_0_EHD_Msk (0x03UL << SCU_SFSP4_0_EHD_Pos) /*!< SCU SFSP4_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_1 ------------------------------------------ -#define SCU_SFSP4_1_MODE_Pos 0 /*!< SCU SFSP4_1: MODE Position */ -#define SCU_SFSP4_1_MODE_Msk (0x07UL << SCU_SFSP4_1_MODE_Pos) /*!< SCU SFSP4_1: MODE Mask */ -#define SCU_SFSP4_1_EPD_Pos 3 /*!< SCU SFSP4_1: EPD Position */ -#define SCU_SFSP4_1_EPD_Msk (0x01UL << SCU_SFSP4_1_EPD_Pos) /*!< SCU SFSP4_1: EPD Mask */ -#define SCU_SFSP4_1_EPUN_Pos 4 /*!< SCU SFSP4_1: EPUN Position */ -#define SCU_SFSP4_1_EPUN_Msk (0x01UL << SCU_SFSP4_1_EPUN_Pos) /*!< SCU SFSP4_1: EPUN Mask */ -#define SCU_SFSP4_1_EHS_Pos 5 /*!< SCU SFSP4_1: EHS Position */ -#define SCU_SFSP4_1_EHS_Msk (0x01UL << SCU_SFSP4_1_EHS_Pos) /*!< SCU SFSP4_1: EHS Mask */ -#define SCU_SFSP4_1_EZI_Pos 6 /*!< SCU SFSP4_1: EZI Position */ -#define SCU_SFSP4_1_EZI_Msk (0x01UL << SCU_SFSP4_1_EZI_Pos) /*!< SCU SFSP4_1: EZI Mask */ -#define SCU_SFSP4_1_EHD_Pos 8 /*!< SCU SFSP4_1: EHD Position */ -#define SCU_SFSP4_1_EHD_Msk (0x03UL << SCU_SFSP4_1_EHD_Pos) /*!< SCU SFSP4_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_2 ------------------------------------------ -#define SCU_SFSP4_2_MODE_Pos 0 /*!< SCU SFSP4_2: MODE Position */ -#define SCU_SFSP4_2_MODE_Msk (0x07UL << SCU_SFSP4_2_MODE_Pos) /*!< SCU SFSP4_2: MODE Mask */ -#define SCU_SFSP4_2_EPD_Pos 3 /*!< SCU SFSP4_2: EPD Position */ -#define SCU_SFSP4_2_EPD_Msk (0x01UL << SCU_SFSP4_2_EPD_Pos) /*!< SCU SFSP4_2: EPD Mask */ -#define SCU_SFSP4_2_EPUN_Pos 4 /*!< SCU SFSP4_2: EPUN Position */ -#define SCU_SFSP4_2_EPUN_Msk (0x01UL << SCU_SFSP4_2_EPUN_Pos) /*!< SCU SFSP4_2: EPUN Mask */ -#define SCU_SFSP4_2_EHS_Pos 5 /*!< SCU SFSP4_2: EHS Position */ -#define SCU_SFSP4_2_EHS_Msk (0x01UL << SCU_SFSP4_2_EHS_Pos) /*!< SCU SFSP4_2: EHS Mask */ -#define SCU_SFSP4_2_EZI_Pos 6 /*!< SCU SFSP4_2: EZI Position */ -#define SCU_SFSP4_2_EZI_Msk (0x01UL << SCU_SFSP4_2_EZI_Pos) /*!< SCU SFSP4_2: EZI Mask */ -#define SCU_SFSP4_2_EHD_Pos 8 /*!< SCU SFSP4_2: EHD Position */ -#define SCU_SFSP4_2_EHD_Msk (0x03UL << SCU_SFSP4_2_EHD_Pos) /*!< SCU SFSP4_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_3 ------------------------------------------ -#define SCU_SFSP4_3_MODE_Pos 0 /*!< SCU SFSP4_3: MODE Position */ -#define SCU_SFSP4_3_MODE_Msk (0x07UL << SCU_SFSP4_3_MODE_Pos) /*!< SCU SFSP4_3: MODE Mask */ -#define SCU_SFSP4_3_EPD_Pos 3 /*!< SCU SFSP4_3: EPD Position */ -#define SCU_SFSP4_3_EPD_Msk (0x01UL << SCU_SFSP4_3_EPD_Pos) /*!< SCU SFSP4_3: EPD Mask */ -#define SCU_SFSP4_3_EPUN_Pos 4 /*!< SCU SFSP4_3: EPUN Position */ -#define SCU_SFSP4_3_EPUN_Msk (0x01UL << SCU_SFSP4_3_EPUN_Pos) /*!< SCU SFSP4_3: EPUN Mask */ -#define SCU_SFSP4_3_EHS_Pos 5 /*!< SCU SFSP4_3: EHS Position */ -#define SCU_SFSP4_3_EHS_Msk (0x01UL << SCU_SFSP4_3_EHS_Pos) /*!< SCU SFSP4_3: EHS Mask */ -#define SCU_SFSP4_3_EZI_Pos 6 /*!< SCU SFSP4_3: EZI Position */ -#define SCU_SFSP4_3_EZI_Msk (0x01UL << SCU_SFSP4_3_EZI_Pos) /*!< SCU SFSP4_3: EZI Mask */ -#define SCU_SFSP4_3_EHD_Pos 8 /*!< SCU SFSP4_3: EHD Position */ -#define SCU_SFSP4_3_EHD_Msk (0x03UL << SCU_SFSP4_3_EHD_Pos) /*!< SCU SFSP4_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_4 ------------------------------------------ -#define SCU_SFSP4_4_MODE_Pos 0 /*!< SCU SFSP4_4: MODE Position */ -#define SCU_SFSP4_4_MODE_Msk (0x07UL << SCU_SFSP4_4_MODE_Pos) /*!< SCU SFSP4_4: MODE Mask */ -#define SCU_SFSP4_4_EPD_Pos 3 /*!< SCU SFSP4_4: EPD Position */ -#define SCU_SFSP4_4_EPD_Msk (0x01UL << SCU_SFSP4_4_EPD_Pos) /*!< SCU SFSP4_4: EPD Mask */ -#define SCU_SFSP4_4_EPUN_Pos 4 /*!< SCU SFSP4_4: EPUN Position */ -#define SCU_SFSP4_4_EPUN_Msk (0x01UL << SCU_SFSP4_4_EPUN_Pos) /*!< SCU SFSP4_4: EPUN Mask */ -#define SCU_SFSP4_4_EHS_Pos 5 /*!< SCU SFSP4_4: EHS Position */ -#define SCU_SFSP4_4_EHS_Msk (0x01UL << SCU_SFSP4_4_EHS_Pos) /*!< SCU SFSP4_4: EHS Mask */ -#define SCU_SFSP4_4_EZI_Pos 6 /*!< SCU SFSP4_4: EZI Position */ -#define SCU_SFSP4_4_EZI_Msk (0x01UL << SCU_SFSP4_4_EZI_Pos) /*!< SCU SFSP4_4: EZI Mask */ -#define SCU_SFSP4_4_EHD_Pos 8 /*!< SCU SFSP4_4: EHD Position */ -#define SCU_SFSP4_4_EHD_Msk (0x03UL << SCU_SFSP4_4_EHD_Pos) /*!< SCU SFSP4_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_5 ------------------------------------------ -#define SCU_SFSP4_5_MODE_Pos 0 /*!< SCU SFSP4_5: MODE Position */ -#define SCU_SFSP4_5_MODE_Msk (0x07UL << SCU_SFSP4_5_MODE_Pos) /*!< SCU SFSP4_5: MODE Mask */ -#define SCU_SFSP4_5_EPD_Pos 3 /*!< SCU SFSP4_5: EPD Position */ -#define SCU_SFSP4_5_EPD_Msk (0x01UL << SCU_SFSP4_5_EPD_Pos) /*!< SCU SFSP4_5: EPD Mask */ -#define SCU_SFSP4_5_EPUN_Pos 4 /*!< SCU SFSP4_5: EPUN Position */ -#define SCU_SFSP4_5_EPUN_Msk (0x01UL << SCU_SFSP4_5_EPUN_Pos) /*!< SCU SFSP4_5: EPUN Mask */ -#define SCU_SFSP4_5_EHS_Pos 5 /*!< SCU SFSP4_5: EHS Position */ -#define SCU_SFSP4_5_EHS_Msk (0x01UL << SCU_SFSP4_5_EHS_Pos) /*!< SCU SFSP4_5: EHS Mask */ -#define SCU_SFSP4_5_EZI_Pos 6 /*!< SCU SFSP4_5: EZI Position */ -#define SCU_SFSP4_5_EZI_Msk (0x01UL << SCU_SFSP4_5_EZI_Pos) /*!< SCU SFSP4_5: EZI Mask */ -#define SCU_SFSP4_5_EHD_Pos 8 /*!< SCU SFSP4_5: EHD Position */ -#define SCU_SFSP4_5_EHD_Msk (0x03UL << SCU_SFSP4_5_EHD_Pos) /*!< SCU SFSP4_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_6 ------------------------------------------ -#define SCU_SFSP4_6_MODE_Pos 0 /*!< SCU SFSP4_6: MODE Position */ -#define SCU_SFSP4_6_MODE_Msk (0x07UL << SCU_SFSP4_6_MODE_Pos) /*!< SCU SFSP4_6: MODE Mask */ -#define SCU_SFSP4_6_EPD_Pos 3 /*!< SCU SFSP4_6: EPD Position */ -#define SCU_SFSP4_6_EPD_Msk (0x01UL << SCU_SFSP4_6_EPD_Pos) /*!< SCU SFSP4_6: EPD Mask */ -#define SCU_SFSP4_6_EPUN_Pos 4 /*!< SCU SFSP4_6: EPUN Position */ -#define SCU_SFSP4_6_EPUN_Msk (0x01UL << SCU_SFSP4_6_EPUN_Pos) /*!< SCU SFSP4_6: EPUN Mask */ -#define SCU_SFSP4_6_EHS_Pos 5 /*!< SCU SFSP4_6: EHS Position */ -#define SCU_SFSP4_6_EHS_Msk (0x01UL << SCU_SFSP4_6_EHS_Pos) /*!< SCU SFSP4_6: EHS Mask */ -#define SCU_SFSP4_6_EZI_Pos 6 /*!< SCU SFSP4_6: EZI Position */ -#define SCU_SFSP4_6_EZI_Msk (0x01UL << SCU_SFSP4_6_EZI_Pos) /*!< SCU SFSP4_6: EZI Mask */ -#define SCU_SFSP4_6_EHD_Pos 8 /*!< SCU SFSP4_6: EHD Position */ -#define SCU_SFSP4_6_EHD_Msk (0x03UL << SCU_SFSP4_6_EHD_Pos) /*!< SCU SFSP4_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_7 ------------------------------------------ -#define SCU_SFSP4_7_MODE_Pos 0 /*!< SCU SFSP4_7: MODE Position */ -#define SCU_SFSP4_7_MODE_Msk (0x07UL << SCU_SFSP4_7_MODE_Pos) /*!< SCU SFSP4_7: MODE Mask */ -#define SCU_SFSP4_7_EPD_Pos 3 /*!< SCU SFSP4_7: EPD Position */ -#define SCU_SFSP4_7_EPD_Msk (0x01UL << SCU_SFSP4_7_EPD_Pos) /*!< SCU SFSP4_7: EPD Mask */ -#define SCU_SFSP4_7_EPUN_Pos 4 /*!< SCU SFSP4_7: EPUN Position */ -#define SCU_SFSP4_7_EPUN_Msk (0x01UL << SCU_SFSP4_7_EPUN_Pos) /*!< SCU SFSP4_7: EPUN Mask */ -#define SCU_SFSP4_7_EHS_Pos 5 /*!< SCU SFSP4_7: EHS Position */ -#define SCU_SFSP4_7_EHS_Msk (0x01UL << SCU_SFSP4_7_EHS_Pos) /*!< SCU SFSP4_7: EHS Mask */ -#define SCU_SFSP4_7_EZI_Pos 6 /*!< SCU SFSP4_7: EZI Position */ -#define SCU_SFSP4_7_EZI_Msk (0x01UL << SCU_SFSP4_7_EZI_Pos) /*!< SCU SFSP4_7: EZI Mask */ -#define SCU_SFSP4_7_EHD_Pos 8 /*!< SCU SFSP4_7: EHD Position */ -#define SCU_SFSP4_7_EHD_Msk (0x03UL << SCU_SFSP4_7_EHD_Pos) /*!< SCU SFSP4_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_8 ------------------------------------------ -#define SCU_SFSP4_8_MODE_Pos 0 /*!< SCU SFSP4_8: MODE Position */ -#define SCU_SFSP4_8_MODE_Msk (0x07UL << SCU_SFSP4_8_MODE_Pos) /*!< SCU SFSP4_8: MODE Mask */ -#define SCU_SFSP4_8_EPD_Pos 3 /*!< SCU SFSP4_8: EPD Position */ -#define SCU_SFSP4_8_EPD_Msk (0x01UL << SCU_SFSP4_8_EPD_Pos) /*!< SCU SFSP4_8: EPD Mask */ -#define SCU_SFSP4_8_EPUN_Pos 4 /*!< SCU SFSP4_8: EPUN Position */ -#define SCU_SFSP4_8_EPUN_Msk (0x01UL << SCU_SFSP4_8_EPUN_Pos) /*!< SCU SFSP4_8: EPUN Mask */ -#define SCU_SFSP4_8_EHS_Pos 5 /*!< SCU SFSP4_8: EHS Position */ -#define SCU_SFSP4_8_EHS_Msk (0x01UL << SCU_SFSP4_8_EHS_Pos) /*!< SCU SFSP4_8: EHS Mask */ -#define SCU_SFSP4_8_EZI_Pos 6 /*!< SCU SFSP4_8: EZI Position */ -#define SCU_SFSP4_8_EZI_Msk (0x01UL << SCU_SFSP4_8_EZI_Pos) /*!< SCU SFSP4_8: EZI Mask */ -#define SCU_SFSP4_8_EHD_Pos 8 /*!< SCU SFSP4_8: EHD Position */ -#define SCU_SFSP4_8_EHD_Msk (0x03UL << SCU_SFSP4_8_EHD_Pos) /*!< SCU SFSP4_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_9 ------------------------------------------ -#define SCU_SFSP4_9_MODE_Pos 0 /*!< SCU SFSP4_9: MODE Position */ -#define SCU_SFSP4_9_MODE_Msk (0x07UL << SCU_SFSP4_9_MODE_Pos) /*!< SCU SFSP4_9: MODE Mask */ -#define SCU_SFSP4_9_EPD_Pos 3 /*!< SCU SFSP4_9: EPD Position */ -#define SCU_SFSP4_9_EPD_Msk (0x01UL << SCU_SFSP4_9_EPD_Pos) /*!< SCU SFSP4_9: EPD Mask */ -#define SCU_SFSP4_9_EPUN_Pos 4 /*!< SCU SFSP4_9: EPUN Position */ -#define SCU_SFSP4_9_EPUN_Msk (0x01UL << SCU_SFSP4_9_EPUN_Pos) /*!< SCU SFSP4_9: EPUN Mask */ -#define SCU_SFSP4_9_EHS_Pos 5 /*!< SCU SFSP4_9: EHS Position */ -#define SCU_SFSP4_9_EHS_Msk (0x01UL << SCU_SFSP4_9_EHS_Pos) /*!< SCU SFSP4_9: EHS Mask */ -#define SCU_SFSP4_9_EZI_Pos 6 /*!< SCU SFSP4_9: EZI Position */ -#define SCU_SFSP4_9_EZI_Msk (0x01UL << SCU_SFSP4_9_EZI_Pos) /*!< SCU SFSP4_9: EZI Mask */ -#define SCU_SFSP4_9_EHD_Pos 8 /*!< SCU SFSP4_9: EHD Position */ -#define SCU_SFSP4_9_EHD_Msk (0x03UL << SCU_SFSP4_9_EHD_Pos) /*!< SCU SFSP4_9: EHD Mask */ - -// -------------------------------------- SCU_SFSP4_10 ------------------------------------------ -#define SCU_SFSP4_10_MODE_Pos 0 /*!< SCU SFSP4_10: MODE Position */ -#define SCU_SFSP4_10_MODE_Msk (0x07UL << SCU_SFSP4_10_MODE_Pos) /*!< SCU SFSP4_10: MODE Mask */ -#define SCU_SFSP4_10_EPD_Pos 3 /*!< SCU SFSP4_10: EPD Position */ -#define SCU_SFSP4_10_EPD_Msk (0x01UL << SCU_SFSP4_10_EPD_Pos) /*!< SCU SFSP4_10: EPD Mask */ -#define SCU_SFSP4_10_EPUN_Pos 4 /*!< SCU SFSP4_10: EPUN Position */ -#define SCU_SFSP4_10_EPUN_Msk (0x01UL << SCU_SFSP4_10_EPUN_Pos) /*!< SCU SFSP4_10: EPUN Mask */ -#define SCU_SFSP4_10_EHS_Pos 5 /*!< SCU SFSP4_10: EHS Position */ -#define SCU_SFSP4_10_EHS_Msk (0x01UL << SCU_SFSP4_10_EHS_Pos) /*!< SCU SFSP4_10: EHS Mask */ -#define SCU_SFSP4_10_EZI_Pos 6 /*!< SCU SFSP4_10: EZI Position */ -#define SCU_SFSP4_10_EZI_Msk (0x01UL << SCU_SFSP4_10_EZI_Pos) /*!< SCU SFSP4_10: EZI Mask */ -#define SCU_SFSP4_10_EHD_Pos 8 /*!< SCU SFSP4_10: EHD Position */ -#define SCU_SFSP4_10_EHD_Msk (0x03UL << SCU_SFSP4_10_EHD_Pos) /*!< SCU SFSP4_10: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_0 ------------------------------------------ -#define SCU_SFSP5_0_MODE_Pos 0 /*!< SCU SFSP5_0: MODE Position */ -#define SCU_SFSP5_0_MODE_Msk (0x07UL << SCU_SFSP5_0_MODE_Pos) /*!< SCU SFSP5_0: MODE Mask */ -#define SCU_SFSP5_0_EPD_Pos 3 /*!< SCU SFSP5_0: EPD Position */ -#define SCU_SFSP5_0_EPD_Msk (0x01UL << SCU_SFSP5_0_EPD_Pos) /*!< SCU SFSP5_0: EPD Mask */ -#define SCU_SFSP5_0_EPUN_Pos 4 /*!< SCU SFSP5_0: EPUN Position */ -#define SCU_SFSP5_0_EPUN_Msk (0x01UL << SCU_SFSP5_0_EPUN_Pos) /*!< SCU SFSP5_0: EPUN Mask */ -#define SCU_SFSP5_0_EHS_Pos 5 /*!< SCU SFSP5_0: EHS Position */ -#define SCU_SFSP5_0_EHS_Msk (0x01UL << SCU_SFSP5_0_EHS_Pos) /*!< SCU SFSP5_0: EHS Mask */ -#define SCU_SFSP5_0_EZI_Pos 6 /*!< SCU SFSP5_0: EZI Position */ -#define SCU_SFSP5_0_EZI_Msk (0x01UL << SCU_SFSP5_0_EZI_Pos) /*!< SCU SFSP5_0: EZI Mask */ -#define SCU_SFSP5_0_EHD_Pos 8 /*!< SCU SFSP5_0: EHD Position */ -#define SCU_SFSP5_0_EHD_Msk (0x03UL << SCU_SFSP5_0_EHD_Pos) /*!< SCU SFSP5_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_1 ------------------------------------------ -#define SCU_SFSP5_1_MODE_Pos 0 /*!< SCU SFSP5_1: MODE Position */ -#define SCU_SFSP5_1_MODE_Msk (0x07UL << SCU_SFSP5_1_MODE_Pos) /*!< SCU SFSP5_1: MODE Mask */ -#define SCU_SFSP5_1_EPD_Pos 3 /*!< SCU SFSP5_1: EPD Position */ -#define SCU_SFSP5_1_EPD_Msk (0x01UL << SCU_SFSP5_1_EPD_Pos) /*!< SCU SFSP5_1: EPD Mask */ -#define SCU_SFSP5_1_EPUN_Pos 4 /*!< SCU SFSP5_1: EPUN Position */ -#define SCU_SFSP5_1_EPUN_Msk (0x01UL << SCU_SFSP5_1_EPUN_Pos) /*!< SCU SFSP5_1: EPUN Mask */ -#define SCU_SFSP5_1_EHS_Pos 5 /*!< SCU SFSP5_1: EHS Position */ -#define SCU_SFSP5_1_EHS_Msk (0x01UL << SCU_SFSP5_1_EHS_Pos) /*!< SCU SFSP5_1: EHS Mask */ -#define SCU_SFSP5_1_EZI_Pos 6 /*!< SCU SFSP5_1: EZI Position */ -#define SCU_SFSP5_1_EZI_Msk (0x01UL << SCU_SFSP5_1_EZI_Pos) /*!< SCU SFSP5_1: EZI Mask */ -#define SCU_SFSP5_1_EHD_Pos 8 /*!< SCU SFSP5_1: EHD Position */ -#define SCU_SFSP5_1_EHD_Msk (0x03UL << SCU_SFSP5_1_EHD_Pos) /*!< SCU SFSP5_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_2 ------------------------------------------ -#define SCU_SFSP5_2_MODE_Pos 0 /*!< SCU SFSP5_2: MODE Position */ -#define SCU_SFSP5_2_MODE_Msk (0x07UL << SCU_SFSP5_2_MODE_Pos) /*!< SCU SFSP5_2: MODE Mask */ -#define SCU_SFSP5_2_EPD_Pos 3 /*!< SCU SFSP5_2: EPD Position */ -#define SCU_SFSP5_2_EPD_Msk (0x01UL << SCU_SFSP5_2_EPD_Pos) /*!< SCU SFSP5_2: EPD Mask */ -#define SCU_SFSP5_2_EPUN_Pos 4 /*!< SCU SFSP5_2: EPUN Position */ -#define SCU_SFSP5_2_EPUN_Msk (0x01UL << SCU_SFSP5_2_EPUN_Pos) /*!< SCU SFSP5_2: EPUN Mask */ -#define SCU_SFSP5_2_EHS_Pos 5 /*!< SCU SFSP5_2: EHS Position */ -#define SCU_SFSP5_2_EHS_Msk (0x01UL << SCU_SFSP5_2_EHS_Pos) /*!< SCU SFSP5_2: EHS Mask */ -#define SCU_SFSP5_2_EZI_Pos 6 /*!< SCU SFSP5_2: EZI Position */ -#define SCU_SFSP5_2_EZI_Msk (0x01UL << SCU_SFSP5_2_EZI_Pos) /*!< SCU SFSP5_2: EZI Mask */ -#define SCU_SFSP5_2_EHD_Pos 8 /*!< SCU SFSP5_2: EHD Position */ -#define SCU_SFSP5_2_EHD_Msk (0x03UL << SCU_SFSP5_2_EHD_Pos) /*!< SCU SFSP5_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_3 ------------------------------------------ -#define SCU_SFSP5_3_MODE_Pos 0 /*!< SCU SFSP5_3: MODE Position */ -#define SCU_SFSP5_3_MODE_Msk (0x07UL << SCU_SFSP5_3_MODE_Pos) /*!< SCU SFSP5_3: MODE Mask */ -#define SCU_SFSP5_3_EPD_Pos 3 /*!< SCU SFSP5_3: EPD Position */ -#define SCU_SFSP5_3_EPD_Msk (0x01UL << SCU_SFSP5_3_EPD_Pos) /*!< SCU SFSP5_3: EPD Mask */ -#define SCU_SFSP5_3_EPUN_Pos 4 /*!< SCU SFSP5_3: EPUN Position */ -#define SCU_SFSP5_3_EPUN_Msk (0x01UL << SCU_SFSP5_3_EPUN_Pos) /*!< SCU SFSP5_3: EPUN Mask */ -#define SCU_SFSP5_3_EHS_Pos 5 /*!< SCU SFSP5_3: EHS Position */ -#define SCU_SFSP5_3_EHS_Msk (0x01UL << SCU_SFSP5_3_EHS_Pos) /*!< SCU SFSP5_3: EHS Mask */ -#define SCU_SFSP5_3_EZI_Pos 6 /*!< SCU SFSP5_3: EZI Position */ -#define SCU_SFSP5_3_EZI_Msk (0x01UL << SCU_SFSP5_3_EZI_Pos) /*!< SCU SFSP5_3: EZI Mask */ -#define SCU_SFSP5_3_EHD_Pos 8 /*!< SCU SFSP5_3: EHD Position */ -#define SCU_SFSP5_3_EHD_Msk (0x03UL << SCU_SFSP5_3_EHD_Pos) /*!< SCU SFSP5_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_4 ------------------------------------------ -#define SCU_SFSP5_4_MODE_Pos 0 /*!< SCU SFSP5_4: MODE Position */ -#define SCU_SFSP5_4_MODE_Msk (0x07UL << SCU_SFSP5_4_MODE_Pos) /*!< SCU SFSP5_4: MODE Mask */ -#define SCU_SFSP5_4_EPD_Pos 3 /*!< SCU SFSP5_4: EPD Position */ -#define SCU_SFSP5_4_EPD_Msk (0x01UL << SCU_SFSP5_4_EPD_Pos) /*!< SCU SFSP5_4: EPD Mask */ -#define SCU_SFSP5_4_EPUN_Pos 4 /*!< SCU SFSP5_4: EPUN Position */ -#define SCU_SFSP5_4_EPUN_Msk (0x01UL << SCU_SFSP5_4_EPUN_Pos) /*!< SCU SFSP5_4: EPUN Mask */ -#define SCU_SFSP5_4_EHS_Pos 5 /*!< SCU SFSP5_4: EHS Position */ -#define SCU_SFSP5_4_EHS_Msk (0x01UL << SCU_SFSP5_4_EHS_Pos) /*!< SCU SFSP5_4: EHS Mask */ -#define SCU_SFSP5_4_EZI_Pos 6 /*!< SCU SFSP5_4: EZI Position */ -#define SCU_SFSP5_4_EZI_Msk (0x01UL << SCU_SFSP5_4_EZI_Pos) /*!< SCU SFSP5_4: EZI Mask */ -#define SCU_SFSP5_4_EHD_Pos 8 /*!< SCU SFSP5_4: EHD Position */ -#define SCU_SFSP5_4_EHD_Msk (0x03UL << SCU_SFSP5_4_EHD_Pos) /*!< SCU SFSP5_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_5 ------------------------------------------ -#define SCU_SFSP5_5_MODE_Pos 0 /*!< SCU SFSP5_5: MODE Position */ -#define SCU_SFSP5_5_MODE_Msk (0x07UL << SCU_SFSP5_5_MODE_Pos) /*!< SCU SFSP5_5: MODE Mask */ -#define SCU_SFSP5_5_EPD_Pos 3 /*!< SCU SFSP5_5: EPD Position */ -#define SCU_SFSP5_5_EPD_Msk (0x01UL << SCU_SFSP5_5_EPD_Pos) /*!< SCU SFSP5_5: EPD Mask */ -#define SCU_SFSP5_5_EPUN_Pos 4 /*!< SCU SFSP5_5: EPUN Position */ -#define SCU_SFSP5_5_EPUN_Msk (0x01UL << SCU_SFSP5_5_EPUN_Pos) /*!< SCU SFSP5_5: EPUN Mask */ -#define SCU_SFSP5_5_EHS_Pos 5 /*!< SCU SFSP5_5: EHS Position */ -#define SCU_SFSP5_5_EHS_Msk (0x01UL << SCU_SFSP5_5_EHS_Pos) /*!< SCU SFSP5_5: EHS Mask */ -#define SCU_SFSP5_5_EZI_Pos 6 /*!< SCU SFSP5_5: EZI Position */ -#define SCU_SFSP5_5_EZI_Msk (0x01UL << SCU_SFSP5_5_EZI_Pos) /*!< SCU SFSP5_5: EZI Mask */ -#define SCU_SFSP5_5_EHD_Pos 8 /*!< SCU SFSP5_5: EHD Position */ -#define SCU_SFSP5_5_EHD_Msk (0x03UL << SCU_SFSP5_5_EHD_Pos) /*!< SCU SFSP5_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_6 ------------------------------------------ -#define SCU_SFSP5_6_MODE_Pos 0 /*!< SCU SFSP5_6: MODE Position */ -#define SCU_SFSP5_6_MODE_Msk (0x07UL << SCU_SFSP5_6_MODE_Pos) /*!< SCU SFSP5_6: MODE Mask */ -#define SCU_SFSP5_6_EPD_Pos 3 /*!< SCU SFSP5_6: EPD Position */ -#define SCU_SFSP5_6_EPD_Msk (0x01UL << SCU_SFSP5_6_EPD_Pos) /*!< SCU SFSP5_6: EPD Mask */ -#define SCU_SFSP5_6_EPUN_Pos 4 /*!< SCU SFSP5_6: EPUN Position */ -#define SCU_SFSP5_6_EPUN_Msk (0x01UL << SCU_SFSP5_6_EPUN_Pos) /*!< SCU SFSP5_6: EPUN Mask */ -#define SCU_SFSP5_6_EHS_Pos 5 /*!< SCU SFSP5_6: EHS Position */ -#define SCU_SFSP5_6_EHS_Msk (0x01UL << SCU_SFSP5_6_EHS_Pos) /*!< SCU SFSP5_6: EHS Mask */ -#define SCU_SFSP5_6_EZI_Pos 6 /*!< SCU SFSP5_6: EZI Position */ -#define SCU_SFSP5_6_EZI_Msk (0x01UL << SCU_SFSP5_6_EZI_Pos) /*!< SCU SFSP5_6: EZI Mask */ -#define SCU_SFSP5_6_EHD_Pos 8 /*!< SCU SFSP5_6: EHD Position */ -#define SCU_SFSP5_6_EHD_Msk (0x03UL << SCU_SFSP5_6_EHD_Pos) /*!< SCU SFSP5_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_7 ------------------------------------------ -#define SCU_SFSP5_7_MODE_Pos 0 /*!< SCU SFSP5_7: MODE Position */ -#define SCU_SFSP5_7_MODE_Msk (0x07UL << SCU_SFSP5_7_MODE_Pos) /*!< SCU SFSP5_7: MODE Mask */ -#define SCU_SFSP5_7_EPD_Pos 3 /*!< SCU SFSP5_7: EPD Position */ -#define SCU_SFSP5_7_EPD_Msk (0x01UL << SCU_SFSP5_7_EPD_Pos) /*!< SCU SFSP5_7: EPD Mask */ -#define SCU_SFSP5_7_EPUN_Pos 4 /*!< SCU SFSP5_7: EPUN Position */ -#define SCU_SFSP5_7_EPUN_Msk (0x01UL << SCU_SFSP5_7_EPUN_Pos) /*!< SCU SFSP5_7: EPUN Mask */ -#define SCU_SFSP5_7_EHS_Pos 5 /*!< SCU SFSP5_7: EHS Position */ -#define SCU_SFSP5_7_EHS_Msk (0x01UL << SCU_SFSP5_7_EHS_Pos) /*!< SCU SFSP5_7: EHS Mask */ -#define SCU_SFSP5_7_EZI_Pos 6 /*!< SCU SFSP5_7: EZI Position */ -#define SCU_SFSP5_7_EZI_Msk (0x01UL << SCU_SFSP5_7_EZI_Pos) /*!< SCU SFSP5_7: EZI Mask */ -#define SCU_SFSP5_7_EHD_Pos 8 /*!< SCU SFSP5_7: EHD Position */ -#define SCU_SFSP5_7_EHD_Msk (0x03UL << SCU_SFSP5_7_EHD_Pos) /*!< SCU SFSP5_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_0 ------------------------------------------ -#define SCU_SFSP6_0_MODE_Pos 0 /*!< SCU SFSP6_0: MODE Position */ -#define SCU_SFSP6_0_MODE_Msk (0x07UL << SCU_SFSP6_0_MODE_Pos) /*!< SCU SFSP6_0: MODE Mask */ -#define SCU_SFSP6_0_EPD_Pos 3 /*!< SCU SFSP6_0: EPD Position */ -#define SCU_SFSP6_0_EPD_Msk (0x01UL << SCU_SFSP6_0_EPD_Pos) /*!< SCU SFSP6_0: EPD Mask */ -#define SCU_SFSP6_0_EPUN_Pos 4 /*!< SCU SFSP6_0: EPUN Position */ -#define SCU_SFSP6_0_EPUN_Msk (0x01UL << SCU_SFSP6_0_EPUN_Pos) /*!< SCU SFSP6_0: EPUN Mask */ -#define SCU_SFSP6_0_EHS_Pos 5 /*!< SCU SFSP6_0: EHS Position */ -#define SCU_SFSP6_0_EHS_Msk (0x01UL << SCU_SFSP6_0_EHS_Pos) /*!< SCU SFSP6_0: EHS Mask */ -#define SCU_SFSP6_0_EZI_Pos 6 /*!< SCU SFSP6_0: EZI Position */ -#define SCU_SFSP6_0_EZI_Msk (0x01UL << SCU_SFSP6_0_EZI_Pos) /*!< SCU SFSP6_0: EZI Mask */ -#define SCU_SFSP6_0_EHD_Pos 8 /*!< SCU SFSP6_0: EHD Position */ -#define SCU_SFSP6_0_EHD_Msk (0x03UL << SCU_SFSP6_0_EHD_Pos) /*!< SCU SFSP6_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_1 ------------------------------------------ -#define SCU_SFSP6_1_MODE_Pos 0 /*!< SCU SFSP6_1: MODE Position */ -#define SCU_SFSP6_1_MODE_Msk (0x07UL << SCU_SFSP6_1_MODE_Pos) /*!< SCU SFSP6_1: MODE Mask */ -#define SCU_SFSP6_1_EPD_Pos 3 /*!< SCU SFSP6_1: EPD Position */ -#define SCU_SFSP6_1_EPD_Msk (0x01UL << SCU_SFSP6_1_EPD_Pos) /*!< SCU SFSP6_1: EPD Mask */ -#define SCU_SFSP6_1_EPUN_Pos 4 /*!< SCU SFSP6_1: EPUN Position */ -#define SCU_SFSP6_1_EPUN_Msk (0x01UL << SCU_SFSP6_1_EPUN_Pos) /*!< SCU SFSP6_1: EPUN Mask */ -#define SCU_SFSP6_1_EHS_Pos 5 /*!< SCU SFSP6_1: EHS Position */ -#define SCU_SFSP6_1_EHS_Msk (0x01UL << SCU_SFSP6_1_EHS_Pos) /*!< SCU SFSP6_1: EHS Mask */ -#define SCU_SFSP6_1_EZI_Pos 6 /*!< SCU SFSP6_1: EZI Position */ -#define SCU_SFSP6_1_EZI_Msk (0x01UL << SCU_SFSP6_1_EZI_Pos) /*!< SCU SFSP6_1: EZI Mask */ -#define SCU_SFSP6_1_EHD_Pos 8 /*!< SCU SFSP6_1: EHD Position */ -#define SCU_SFSP6_1_EHD_Msk (0x03UL << SCU_SFSP6_1_EHD_Pos) /*!< SCU SFSP6_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_2 ------------------------------------------ -#define SCU_SFSP6_2_MODE_Pos 0 /*!< SCU SFSP6_2: MODE Position */ -#define SCU_SFSP6_2_MODE_Msk (0x07UL << SCU_SFSP6_2_MODE_Pos) /*!< SCU SFSP6_2: MODE Mask */ -#define SCU_SFSP6_2_EPD_Pos 3 /*!< SCU SFSP6_2: EPD Position */ -#define SCU_SFSP6_2_EPD_Msk (0x01UL << SCU_SFSP6_2_EPD_Pos) /*!< SCU SFSP6_2: EPD Mask */ -#define SCU_SFSP6_2_EPUN_Pos 4 /*!< SCU SFSP6_2: EPUN Position */ -#define SCU_SFSP6_2_EPUN_Msk (0x01UL << SCU_SFSP6_2_EPUN_Pos) /*!< SCU SFSP6_2: EPUN Mask */ -#define SCU_SFSP6_2_EHS_Pos 5 /*!< SCU SFSP6_2: EHS Position */ -#define SCU_SFSP6_2_EHS_Msk (0x01UL << SCU_SFSP6_2_EHS_Pos) /*!< SCU SFSP6_2: EHS Mask */ -#define SCU_SFSP6_2_EZI_Pos 6 /*!< SCU SFSP6_2: EZI Position */ -#define SCU_SFSP6_2_EZI_Msk (0x01UL << SCU_SFSP6_2_EZI_Pos) /*!< SCU SFSP6_2: EZI Mask */ -#define SCU_SFSP6_2_EHD_Pos 8 /*!< SCU SFSP6_2: EHD Position */ -#define SCU_SFSP6_2_EHD_Msk (0x03UL << SCU_SFSP6_2_EHD_Pos) /*!< SCU SFSP6_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_3 ------------------------------------------ -#define SCU_SFSP6_3_MODE_Pos 0 /*!< SCU SFSP6_3: MODE Position */ -#define SCU_SFSP6_3_MODE_Msk (0x07UL << SCU_SFSP6_3_MODE_Pos) /*!< SCU SFSP6_3: MODE Mask */ -#define SCU_SFSP6_3_EPD_Pos 3 /*!< SCU SFSP6_3: EPD Position */ -#define SCU_SFSP6_3_EPD_Msk (0x01UL << SCU_SFSP6_3_EPD_Pos) /*!< SCU SFSP6_3: EPD Mask */ -#define SCU_SFSP6_3_EPUN_Pos 4 /*!< SCU SFSP6_3: EPUN Position */ -#define SCU_SFSP6_3_EPUN_Msk (0x01UL << SCU_SFSP6_3_EPUN_Pos) /*!< SCU SFSP6_3: EPUN Mask */ -#define SCU_SFSP6_3_EHS_Pos 5 /*!< SCU SFSP6_3: EHS Position */ -#define SCU_SFSP6_3_EHS_Msk (0x01UL << SCU_SFSP6_3_EHS_Pos) /*!< SCU SFSP6_3: EHS Mask */ -#define SCU_SFSP6_3_EZI_Pos 6 /*!< SCU SFSP6_3: EZI Position */ -#define SCU_SFSP6_3_EZI_Msk (0x01UL << SCU_SFSP6_3_EZI_Pos) /*!< SCU SFSP6_3: EZI Mask */ -#define SCU_SFSP6_3_EHD_Pos 8 /*!< SCU SFSP6_3: EHD Position */ -#define SCU_SFSP6_3_EHD_Msk (0x03UL << SCU_SFSP6_3_EHD_Pos) /*!< SCU SFSP6_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_4 ------------------------------------------ -#define SCU_SFSP6_4_MODE_Pos 0 /*!< SCU SFSP6_4: MODE Position */ -#define SCU_SFSP6_4_MODE_Msk (0x07UL << SCU_SFSP6_4_MODE_Pos) /*!< SCU SFSP6_4: MODE Mask */ -#define SCU_SFSP6_4_EPD_Pos 3 /*!< SCU SFSP6_4: EPD Position */ -#define SCU_SFSP6_4_EPD_Msk (0x01UL << SCU_SFSP6_4_EPD_Pos) /*!< SCU SFSP6_4: EPD Mask */ -#define SCU_SFSP6_4_EPUN_Pos 4 /*!< SCU SFSP6_4: EPUN Position */ -#define SCU_SFSP6_4_EPUN_Msk (0x01UL << SCU_SFSP6_4_EPUN_Pos) /*!< SCU SFSP6_4: EPUN Mask */ -#define SCU_SFSP6_4_EHS_Pos 5 /*!< SCU SFSP6_4: EHS Position */ -#define SCU_SFSP6_4_EHS_Msk (0x01UL << SCU_SFSP6_4_EHS_Pos) /*!< SCU SFSP6_4: EHS Mask */ -#define SCU_SFSP6_4_EZI_Pos 6 /*!< SCU SFSP6_4: EZI Position */ -#define SCU_SFSP6_4_EZI_Msk (0x01UL << SCU_SFSP6_4_EZI_Pos) /*!< SCU SFSP6_4: EZI Mask */ -#define SCU_SFSP6_4_EHD_Pos 8 /*!< SCU SFSP6_4: EHD Position */ -#define SCU_SFSP6_4_EHD_Msk (0x03UL << SCU_SFSP6_4_EHD_Pos) /*!< SCU SFSP6_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_5 ------------------------------------------ -#define SCU_SFSP6_5_MODE_Pos 0 /*!< SCU SFSP6_5: MODE Position */ -#define SCU_SFSP6_5_MODE_Msk (0x07UL << SCU_SFSP6_5_MODE_Pos) /*!< SCU SFSP6_5: MODE Mask */ -#define SCU_SFSP6_5_EPD_Pos 3 /*!< SCU SFSP6_5: EPD Position */ -#define SCU_SFSP6_5_EPD_Msk (0x01UL << SCU_SFSP6_5_EPD_Pos) /*!< SCU SFSP6_5: EPD Mask */ -#define SCU_SFSP6_5_EPUN_Pos 4 /*!< SCU SFSP6_5: EPUN Position */ -#define SCU_SFSP6_5_EPUN_Msk (0x01UL << SCU_SFSP6_5_EPUN_Pos) /*!< SCU SFSP6_5: EPUN Mask */ -#define SCU_SFSP6_5_EHS_Pos 5 /*!< SCU SFSP6_5: EHS Position */ -#define SCU_SFSP6_5_EHS_Msk (0x01UL << SCU_SFSP6_5_EHS_Pos) /*!< SCU SFSP6_5: EHS Mask */ -#define SCU_SFSP6_5_EZI_Pos 6 /*!< SCU SFSP6_5: EZI Position */ -#define SCU_SFSP6_5_EZI_Msk (0x01UL << SCU_SFSP6_5_EZI_Pos) /*!< SCU SFSP6_5: EZI Mask */ -#define SCU_SFSP6_5_EHD_Pos 8 /*!< SCU SFSP6_5: EHD Position */ -#define SCU_SFSP6_5_EHD_Msk (0x03UL << SCU_SFSP6_5_EHD_Pos) /*!< SCU SFSP6_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_6 ------------------------------------------ -#define SCU_SFSP6_6_MODE_Pos 0 /*!< SCU SFSP6_6: MODE Position */ -#define SCU_SFSP6_6_MODE_Msk (0x07UL << SCU_SFSP6_6_MODE_Pos) /*!< SCU SFSP6_6: MODE Mask */ -#define SCU_SFSP6_6_EPD_Pos 3 /*!< SCU SFSP6_6: EPD Position */ -#define SCU_SFSP6_6_EPD_Msk (0x01UL << SCU_SFSP6_6_EPD_Pos) /*!< SCU SFSP6_6: EPD Mask */ -#define SCU_SFSP6_6_EPUN_Pos 4 /*!< SCU SFSP6_6: EPUN Position */ -#define SCU_SFSP6_6_EPUN_Msk (0x01UL << SCU_SFSP6_6_EPUN_Pos) /*!< SCU SFSP6_6: EPUN Mask */ -#define SCU_SFSP6_6_EHS_Pos 5 /*!< SCU SFSP6_6: EHS Position */ -#define SCU_SFSP6_6_EHS_Msk (0x01UL << SCU_SFSP6_6_EHS_Pos) /*!< SCU SFSP6_6: EHS Mask */ -#define SCU_SFSP6_6_EZI_Pos 6 /*!< SCU SFSP6_6: EZI Position */ -#define SCU_SFSP6_6_EZI_Msk (0x01UL << SCU_SFSP6_6_EZI_Pos) /*!< SCU SFSP6_6: EZI Mask */ -#define SCU_SFSP6_6_EHD_Pos 8 /*!< SCU SFSP6_6: EHD Position */ -#define SCU_SFSP6_6_EHD_Msk (0x03UL << SCU_SFSP6_6_EHD_Pos) /*!< SCU SFSP6_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_7 ------------------------------------------ -#define SCU_SFSP6_7_MODE_Pos 0 /*!< SCU SFSP6_7: MODE Position */ -#define SCU_SFSP6_7_MODE_Msk (0x07UL << SCU_SFSP6_7_MODE_Pos) /*!< SCU SFSP6_7: MODE Mask */ -#define SCU_SFSP6_7_EPD_Pos 3 /*!< SCU SFSP6_7: EPD Position */ -#define SCU_SFSP6_7_EPD_Msk (0x01UL << SCU_SFSP6_7_EPD_Pos) /*!< SCU SFSP6_7: EPD Mask */ -#define SCU_SFSP6_7_EPUN_Pos 4 /*!< SCU SFSP6_7: EPUN Position */ -#define SCU_SFSP6_7_EPUN_Msk (0x01UL << SCU_SFSP6_7_EPUN_Pos) /*!< SCU SFSP6_7: EPUN Mask */ -#define SCU_SFSP6_7_EHS_Pos 5 /*!< SCU SFSP6_7: EHS Position */ -#define SCU_SFSP6_7_EHS_Msk (0x01UL << SCU_SFSP6_7_EHS_Pos) /*!< SCU SFSP6_7: EHS Mask */ -#define SCU_SFSP6_7_EZI_Pos 6 /*!< SCU SFSP6_7: EZI Position */ -#define SCU_SFSP6_7_EZI_Msk (0x01UL << SCU_SFSP6_7_EZI_Pos) /*!< SCU SFSP6_7: EZI Mask */ -#define SCU_SFSP6_7_EHD_Pos 8 /*!< SCU SFSP6_7: EHD Position */ -#define SCU_SFSP6_7_EHD_Msk (0x03UL << SCU_SFSP6_7_EHD_Pos) /*!< SCU SFSP6_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_8 ------------------------------------------ -#define SCU_SFSP6_8_MODE_Pos 0 /*!< SCU SFSP6_8: MODE Position */ -#define SCU_SFSP6_8_MODE_Msk (0x07UL << SCU_SFSP6_8_MODE_Pos) /*!< SCU SFSP6_8: MODE Mask */ -#define SCU_SFSP6_8_EPD_Pos 3 /*!< SCU SFSP6_8: EPD Position */ -#define SCU_SFSP6_8_EPD_Msk (0x01UL << SCU_SFSP6_8_EPD_Pos) /*!< SCU SFSP6_8: EPD Mask */ -#define SCU_SFSP6_8_EPUN_Pos 4 /*!< SCU SFSP6_8: EPUN Position */ -#define SCU_SFSP6_8_EPUN_Msk (0x01UL << SCU_SFSP6_8_EPUN_Pos) /*!< SCU SFSP6_8: EPUN Mask */ -#define SCU_SFSP6_8_EHS_Pos 5 /*!< SCU SFSP6_8: EHS Position */ -#define SCU_SFSP6_8_EHS_Msk (0x01UL << SCU_SFSP6_8_EHS_Pos) /*!< SCU SFSP6_8: EHS Mask */ -#define SCU_SFSP6_8_EZI_Pos 6 /*!< SCU SFSP6_8: EZI Position */ -#define SCU_SFSP6_8_EZI_Msk (0x01UL << SCU_SFSP6_8_EZI_Pos) /*!< SCU SFSP6_8: EZI Mask */ -#define SCU_SFSP6_8_EHD_Pos 8 /*!< SCU SFSP6_8: EHD Position */ -#define SCU_SFSP6_8_EHD_Msk (0x03UL << SCU_SFSP6_8_EHD_Pos) /*!< SCU SFSP6_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_9 ------------------------------------------ -#define SCU_SFSP6_9_MODE_Pos 0 /*!< SCU SFSP6_9: MODE Position */ -#define SCU_SFSP6_9_MODE_Msk (0x07UL << SCU_SFSP6_9_MODE_Pos) /*!< SCU SFSP6_9: MODE Mask */ -#define SCU_SFSP6_9_EPD_Pos 3 /*!< SCU SFSP6_9: EPD Position */ -#define SCU_SFSP6_9_EPD_Msk (0x01UL << SCU_SFSP6_9_EPD_Pos) /*!< SCU SFSP6_9: EPD Mask */ -#define SCU_SFSP6_9_EPUN_Pos 4 /*!< SCU SFSP6_9: EPUN Position */ -#define SCU_SFSP6_9_EPUN_Msk (0x01UL << SCU_SFSP6_9_EPUN_Pos) /*!< SCU SFSP6_9: EPUN Mask */ -#define SCU_SFSP6_9_EHS_Pos 5 /*!< SCU SFSP6_9: EHS Position */ -#define SCU_SFSP6_9_EHS_Msk (0x01UL << SCU_SFSP6_9_EHS_Pos) /*!< SCU SFSP6_9: EHS Mask */ -#define SCU_SFSP6_9_EZI_Pos 6 /*!< SCU SFSP6_9: EZI Position */ -#define SCU_SFSP6_9_EZI_Msk (0x01UL << SCU_SFSP6_9_EZI_Pos) /*!< SCU SFSP6_9: EZI Mask */ -#define SCU_SFSP6_9_EHD_Pos 8 /*!< SCU SFSP6_9: EHD Position */ -#define SCU_SFSP6_9_EHD_Msk (0x03UL << SCU_SFSP6_9_EHD_Pos) /*!< SCU SFSP6_9: EHD Mask */ - -// -------------------------------------- SCU_SFSP6_10 ------------------------------------------ -#define SCU_SFSP6_10_MODE_Pos 0 /*!< SCU SFSP6_10: MODE Position */ -#define SCU_SFSP6_10_MODE_Msk (0x07UL << SCU_SFSP6_10_MODE_Pos) /*!< SCU SFSP6_10: MODE Mask */ -#define SCU_SFSP6_10_EPD_Pos 3 /*!< SCU SFSP6_10: EPD Position */ -#define SCU_SFSP6_10_EPD_Msk (0x01UL << SCU_SFSP6_10_EPD_Pos) /*!< SCU SFSP6_10: EPD Mask */ -#define SCU_SFSP6_10_EPUN_Pos 4 /*!< SCU SFSP6_10: EPUN Position */ -#define SCU_SFSP6_10_EPUN_Msk (0x01UL << SCU_SFSP6_10_EPUN_Pos) /*!< SCU SFSP6_10: EPUN Mask */ -#define SCU_SFSP6_10_EHS_Pos 5 /*!< SCU SFSP6_10: EHS Position */ -#define SCU_SFSP6_10_EHS_Msk (0x01UL << SCU_SFSP6_10_EHS_Pos) /*!< SCU SFSP6_10: EHS Mask */ -#define SCU_SFSP6_10_EZI_Pos 6 /*!< SCU SFSP6_10: EZI Position */ -#define SCU_SFSP6_10_EZI_Msk (0x01UL << SCU_SFSP6_10_EZI_Pos) /*!< SCU SFSP6_10: EZI Mask */ -#define SCU_SFSP6_10_EHD_Pos 8 /*!< SCU SFSP6_10: EHD Position */ -#define SCU_SFSP6_10_EHD_Msk (0x03UL << SCU_SFSP6_10_EHD_Pos) /*!< SCU SFSP6_10: EHD Mask */ - -// -------------------------------------- SCU_SFSP6_11 ------------------------------------------ -#define SCU_SFSP6_11_MODE_Pos 0 /*!< SCU SFSP6_11: MODE Position */ -#define SCU_SFSP6_11_MODE_Msk (0x07UL << SCU_SFSP6_11_MODE_Pos) /*!< SCU SFSP6_11: MODE Mask */ -#define SCU_SFSP6_11_EPD_Pos 3 /*!< SCU SFSP6_11: EPD Position */ -#define SCU_SFSP6_11_EPD_Msk (0x01UL << SCU_SFSP6_11_EPD_Pos) /*!< SCU SFSP6_11: EPD Mask */ -#define SCU_SFSP6_11_EPUN_Pos 4 /*!< SCU SFSP6_11: EPUN Position */ -#define SCU_SFSP6_11_EPUN_Msk (0x01UL << SCU_SFSP6_11_EPUN_Pos) /*!< SCU SFSP6_11: EPUN Mask */ -#define SCU_SFSP6_11_EHS_Pos 5 /*!< SCU SFSP6_11: EHS Position */ -#define SCU_SFSP6_11_EHS_Msk (0x01UL << SCU_SFSP6_11_EHS_Pos) /*!< SCU SFSP6_11: EHS Mask */ -#define SCU_SFSP6_11_EZI_Pos 6 /*!< SCU SFSP6_11: EZI Position */ -#define SCU_SFSP6_11_EZI_Msk (0x01UL << SCU_SFSP6_11_EZI_Pos) /*!< SCU SFSP6_11: EZI Mask */ -#define SCU_SFSP6_11_EHD_Pos 8 /*!< SCU SFSP6_11: EHD Position */ -#define SCU_SFSP6_11_EHD_Msk (0x03UL << SCU_SFSP6_11_EHD_Pos) /*!< SCU SFSP6_11: EHD Mask */ - -// -------------------------------------- SCU_SFSP6_12 ------------------------------------------ -#define SCU_SFSP6_12_MODE_Pos 0 /*!< SCU SFSP6_12: MODE Position */ -#define SCU_SFSP6_12_MODE_Msk (0x07UL << SCU_SFSP6_12_MODE_Pos) /*!< SCU SFSP6_12: MODE Mask */ -#define SCU_SFSP6_12_EPD_Pos 3 /*!< SCU SFSP6_12: EPD Position */ -#define SCU_SFSP6_12_EPD_Msk (0x01UL << SCU_SFSP6_12_EPD_Pos) /*!< SCU SFSP6_12: EPD Mask */ -#define SCU_SFSP6_12_EPUN_Pos 4 /*!< SCU SFSP6_12: EPUN Position */ -#define SCU_SFSP6_12_EPUN_Msk (0x01UL << SCU_SFSP6_12_EPUN_Pos) /*!< SCU SFSP6_12: EPUN Mask */ -#define SCU_SFSP6_12_EHS_Pos 5 /*!< SCU SFSP6_12: EHS Position */ -#define SCU_SFSP6_12_EHS_Msk (0x01UL << SCU_SFSP6_12_EHS_Pos) /*!< SCU SFSP6_12: EHS Mask */ -#define SCU_SFSP6_12_EZI_Pos 6 /*!< SCU SFSP6_12: EZI Position */ -#define SCU_SFSP6_12_EZI_Msk (0x01UL << SCU_SFSP6_12_EZI_Pos) /*!< SCU SFSP6_12: EZI Mask */ -#define SCU_SFSP6_12_EHD_Pos 8 /*!< SCU SFSP6_12: EHD Position */ -#define SCU_SFSP6_12_EHD_Msk (0x03UL << SCU_SFSP6_12_EHD_Pos) /*!< SCU SFSP6_12: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_0 ------------------------------------------ -#define SCU_SFSP7_0_MODE_Pos 0 /*!< SCU SFSP7_0: MODE Position */ -#define SCU_SFSP7_0_MODE_Msk (0x07UL << SCU_SFSP7_0_MODE_Pos) /*!< SCU SFSP7_0: MODE Mask */ -#define SCU_SFSP7_0_EPD_Pos 3 /*!< SCU SFSP7_0: EPD Position */ -#define SCU_SFSP7_0_EPD_Msk (0x01UL << SCU_SFSP7_0_EPD_Pos) /*!< SCU SFSP7_0: EPD Mask */ -#define SCU_SFSP7_0_EPUN_Pos 4 /*!< SCU SFSP7_0: EPUN Position */ -#define SCU_SFSP7_0_EPUN_Msk (0x01UL << SCU_SFSP7_0_EPUN_Pos) /*!< SCU SFSP7_0: EPUN Mask */ -#define SCU_SFSP7_0_EHS_Pos 5 /*!< SCU SFSP7_0: EHS Position */ -#define SCU_SFSP7_0_EHS_Msk (0x01UL << SCU_SFSP7_0_EHS_Pos) /*!< SCU SFSP7_0: EHS Mask */ -#define SCU_SFSP7_0_EZI_Pos 6 /*!< SCU SFSP7_0: EZI Position */ -#define SCU_SFSP7_0_EZI_Msk (0x01UL << SCU_SFSP7_0_EZI_Pos) /*!< SCU SFSP7_0: EZI Mask */ -#define SCU_SFSP7_0_EHD_Pos 8 /*!< SCU SFSP7_0: EHD Position */ -#define SCU_SFSP7_0_EHD_Msk (0x03UL << SCU_SFSP7_0_EHD_Pos) /*!< SCU SFSP7_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_1 ------------------------------------------ -#define SCU_SFSP7_1_MODE_Pos 0 /*!< SCU SFSP7_1: MODE Position */ -#define SCU_SFSP7_1_MODE_Msk (0x07UL << SCU_SFSP7_1_MODE_Pos) /*!< SCU SFSP7_1: MODE Mask */ -#define SCU_SFSP7_1_EPD_Pos 3 /*!< SCU SFSP7_1: EPD Position */ -#define SCU_SFSP7_1_EPD_Msk (0x01UL << SCU_SFSP7_1_EPD_Pos) /*!< SCU SFSP7_1: EPD Mask */ -#define SCU_SFSP7_1_EPUN_Pos 4 /*!< SCU SFSP7_1: EPUN Position */ -#define SCU_SFSP7_1_EPUN_Msk (0x01UL << SCU_SFSP7_1_EPUN_Pos) /*!< SCU SFSP7_1: EPUN Mask */ -#define SCU_SFSP7_1_EHS_Pos 5 /*!< SCU SFSP7_1: EHS Position */ -#define SCU_SFSP7_1_EHS_Msk (0x01UL << SCU_SFSP7_1_EHS_Pos) /*!< SCU SFSP7_1: EHS Mask */ -#define SCU_SFSP7_1_EZI_Pos 6 /*!< SCU SFSP7_1: EZI Position */ -#define SCU_SFSP7_1_EZI_Msk (0x01UL << SCU_SFSP7_1_EZI_Pos) /*!< SCU SFSP7_1: EZI Mask */ -#define SCU_SFSP7_1_EHD_Pos 8 /*!< SCU SFSP7_1: EHD Position */ -#define SCU_SFSP7_1_EHD_Msk (0x03UL << SCU_SFSP7_1_EHD_Pos) /*!< SCU SFSP7_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_2 ------------------------------------------ -#define SCU_SFSP7_2_MODE_Pos 0 /*!< SCU SFSP7_2: MODE Position */ -#define SCU_SFSP7_2_MODE_Msk (0x07UL << SCU_SFSP7_2_MODE_Pos) /*!< SCU SFSP7_2: MODE Mask */ -#define SCU_SFSP7_2_EPD_Pos 3 /*!< SCU SFSP7_2: EPD Position */ -#define SCU_SFSP7_2_EPD_Msk (0x01UL << SCU_SFSP7_2_EPD_Pos) /*!< SCU SFSP7_2: EPD Mask */ -#define SCU_SFSP7_2_EPUN_Pos 4 /*!< SCU SFSP7_2: EPUN Position */ -#define SCU_SFSP7_2_EPUN_Msk (0x01UL << SCU_SFSP7_2_EPUN_Pos) /*!< SCU SFSP7_2: EPUN Mask */ -#define SCU_SFSP7_2_EHS_Pos 5 /*!< SCU SFSP7_2: EHS Position */ -#define SCU_SFSP7_2_EHS_Msk (0x01UL << SCU_SFSP7_2_EHS_Pos) /*!< SCU SFSP7_2: EHS Mask */ -#define SCU_SFSP7_2_EZI_Pos 6 /*!< SCU SFSP7_2: EZI Position */ -#define SCU_SFSP7_2_EZI_Msk (0x01UL << SCU_SFSP7_2_EZI_Pos) /*!< SCU SFSP7_2: EZI Mask */ -#define SCU_SFSP7_2_EHD_Pos 8 /*!< SCU SFSP7_2: EHD Position */ -#define SCU_SFSP7_2_EHD_Msk (0x03UL << SCU_SFSP7_2_EHD_Pos) /*!< SCU SFSP7_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_3 ------------------------------------------ -#define SCU_SFSP7_3_MODE_Pos 0 /*!< SCU SFSP7_3: MODE Position */ -#define SCU_SFSP7_3_MODE_Msk (0x07UL << SCU_SFSP7_3_MODE_Pos) /*!< SCU SFSP7_3: MODE Mask */ -#define SCU_SFSP7_3_EPD_Pos 3 /*!< SCU SFSP7_3: EPD Position */ -#define SCU_SFSP7_3_EPD_Msk (0x01UL << SCU_SFSP7_3_EPD_Pos) /*!< SCU SFSP7_3: EPD Mask */ -#define SCU_SFSP7_3_EPUN_Pos 4 /*!< SCU SFSP7_3: EPUN Position */ -#define SCU_SFSP7_3_EPUN_Msk (0x01UL << SCU_SFSP7_3_EPUN_Pos) /*!< SCU SFSP7_3: EPUN Mask */ -#define SCU_SFSP7_3_EHS_Pos 5 /*!< SCU SFSP7_3: EHS Position */ -#define SCU_SFSP7_3_EHS_Msk (0x01UL << SCU_SFSP7_3_EHS_Pos) /*!< SCU SFSP7_3: EHS Mask */ -#define SCU_SFSP7_3_EZI_Pos 6 /*!< SCU SFSP7_3: EZI Position */ -#define SCU_SFSP7_3_EZI_Msk (0x01UL << SCU_SFSP7_3_EZI_Pos) /*!< SCU SFSP7_3: EZI Mask */ -#define SCU_SFSP7_3_EHD_Pos 8 /*!< SCU SFSP7_3: EHD Position */ -#define SCU_SFSP7_3_EHD_Msk (0x03UL << SCU_SFSP7_3_EHD_Pos) /*!< SCU SFSP7_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_4 ------------------------------------------ -#define SCU_SFSP7_4_MODE_Pos 0 /*!< SCU SFSP7_4: MODE Position */ -#define SCU_SFSP7_4_MODE_Msk (0x07UL << SCU_SFSP7_4_MODE_Pos) /*!< SCU SFSP7_4: MODE Mask */ -#define SCU_SFSP7_4_EPD_Pos 3 /*!< SCU SFSP7_4: EPD Position */ -#define SCU_SFSP7_4_EPD_Msk (0x01UL << SCU_SFSP7_4_EPD_Pos) /*!< SCU SFSP7_4: EPD Mask */ -#define SCU_SFSP7_4_EPUN_Pos 4 /*!< SCU SFSP7_4: EPUN Position */ -#define SCU_SFSP7_4_EPUN_Msk (0x01UL << SCU_SFSP7_4_EPUN_Pos) /*!< SCU SFSP7_4: EPUN Mask */ -#define SCU_SFSP7_4_EHS_Pos 5 /*!< SCU SFSP7_4: EHS Position */ -#define SCU_SFSP7_4_EHS_Msk (0x01UL << SCU_SFSP7_4_EHS_Pos) /*!< SCU SFSP7_4: EHS Mask */ -#define SCU_SFSP7_4_EZI_Pos 6 /*!< SCU SFSP7_4: EZI Position */ -#define SCU_SFSP7_4_EZI_Msk (0x01UL << SCU_SFSP7_4_EZI_Pos) /*!< SCU SFSP7_4: EZI Mask */ -#define SCU_SFSP7_4_EHD_Pos 8 /*!< SCU SFSP7_4: EHD Position */ -#define SCU_SFSP7_4_EHD_Msk (0x03UL << SCU_SFSP7_4_EHD_Pos) /*!< SCU SFSP7_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_5 ------------------------------------------ -#define SCU_SFSP7_5_MODE_Pos 0 /*!< SCU SFSP7_5: MODE Position */ -#define SCU_SFSP7_5_MODE_Msk (0x07UL << SCU_SFSP7_5_MODE_Pos) /*!< SCU SFSP7_5: MODE Mask */ -#define SCU_SFSP7_5_EPD_Pos 3 /*!< SCU SFSP7_5: EPD Position */ -#define SCU_SFSP7_5_EPD_Msk (0x01UL << SCU_SFSP7_5_EPD_Pos) /*!< SCU SFSP7_5: EPD Mask */ -#define SCU_SFSP7_5_EPUN_Pos 4 /*!< SCU SFSP7_5: EPUN Position */ -#define SCU_SFSP7_5_EPUN_Msk (0x01UL << SCU_SFSP7_5_EPUN_Pos) /*!< SCU SFSP7_5: EPUN Mask */ -#define SCU_SFSP7_5_EHS_Pos 5 /*!< SCU SFSP7_5: EHS Position */ -#define SCU_SFSP7_5_EHS_Msk (0x01UL << SCU_SFSP7_5_EHS_Pos) /*!< SCU SFSP7_5: EHS Mask */ -#define SCU_SFSP7_5_EZI_Pos 6 /*!< SCU SFSP7_5: EZI Position */ -#define SCU_SFSP7_5_EZI_Msk (0x01UL << SCU_SFSP7_5_EZI_Pos) /*!< SCU SFSP7_5: EZI Mask */ -#define SCU_SFSP7_5_EHD_Pos 8 /*!< SCU SFSP7_5: EHD Position */ -#define SCU_SFSP7_5_EHD_Msk (0x03UL << SCU_SFSP7_5_EHD_Pos) /*!< SCU SFSP7_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_6 ------------------------------------------ -#define SCU_SFSP7_6_MODE_Pos 0 /*!< SCU SFSP7_6: MODE Position */ -#define SCU_SFSP7_6_MODE_Msk (0x07UL << SCU_SFSP7_6_MODE_Pos) /*!< SCU SFSP7_6: MODE Mask */ -#define SCU_SFSP7_6_EPD_Pos 3 /*!< SCU SFSP7_6: EPD Position */ -#define SCU_SFSP7_6_EPD_Msk (0x01UL << SCU_SFSP7_6_EPD_Pos) /*!< SCU SFSP7_6: EPD Mask */ -#define SCU_SFSP7_6_EPUN_Pos 4 /*!< SCU SFSP7_6: EPUN Position */ -#define SCU_SFSP7_6_EPUN_Msk (0x01UL << SCU_SFSP7_6_EPUN_Pos) /*!< SCU SFSP7_6: EPUN Mask */ -#define SCU_SFSP7_6_EHS_Pos 5 /*!< SCU SFSP7_6: EHS Position */ -#define SCU_SFSP7_6_EHS_Msk (0x01UL << SCU_SFSP7_6_EHS_Pos) /*!< SCU SFSP7_6: EHS Mask */ -#define SCU_SFSP7_6_EZI_Pos 6 /*!< SCU SFSP7_6: EZI Position */ -#define SCU_SFSP7_6_EZI_Msk (0x01UL << SCU_SFSP7_6_EZI_Pos) /*!< SCU SFSP7_6: EZI Mask */ -#define SCU_SFSP7_6_EHD_Pos 8 /*!< SCU SFSP7_6: EHD Position */ -#define SCU_SFSP7_6_EHD_Msk (0x03UL << SCU_SFSP7_6_EHD_Pos) /*!< SCU SFSP7_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_7 ------------------------------------------ -#define SCU_SFSP7_7_MODE_Pos 0 /*!< SCU SFSP7_7: MODE Position */ -#define SCU_SFSP7_7_MODE_Msk (0x07UL << SCU_SFSP7_7_MODE_Pos) /*!< SCU SFSP7_7: MODE Mask */ -#define SCU_SFSP7_7_EPD_Pos 3 /*!< SCU SFSP7_7: EPD Position */ -#define SCU_SFSP7_7_EPD_Msk (0x01UL << SCU_SFSP7_7_EPD_Pos) /*!< SCU SFSP7_7: EPD Mask */ -#define SCU_SFSP7_7_EPUN_Pos 4 /*!< SCU SFSP7_7: EPUN Position */ -#define SCU_SFSP7_7_EPUN_Msk (0x01UL << SCU_SFSP7_7_EPUN_Pos) /*!< SCU SFSP7_7: EPUN Mask */ -#define SCU_SFSP7_7_EHS_Pos 5 /*!< SCU SFSP7_7: EHS Position */ -#define SCU_SFSP7_7_EHS_Msk (0x01UL << SCU_SFSP7_7_EHS_Pos) /*!< SCU SFSP7_7: EHS Mask */ -#define SCU_SFSP7_7_EZI_Pos 6 /*!< SCU SFSP7_7: EZI Position */ -#define SCU_SFSP7_7_EZI_Msk (0x01UL << SCU_SFSP7_7_EZI_Pos) /*!< SCU SFSP7_7: EZI Mask */ -#define SCU_SFSP7_7_EHD_Pos 8 /*!< SCU SFSP7_7: EHD Position */ -#define SCU_SFSP7_7_EHD_Msk (0x03UL << SCU_SFSP7_7_EHD_Pos) /*!< SCU SFSP7_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_0 ------------------------------------------ -#define SCU_SFSP8_0_MODE_Pos 0 /*!< SCU SFSP8_0: MODE Position */ -#define SCU_SFSP8_0_MODE_Msk (0x07UL << SCU_SFSP8_0_MODE_Pos) /*!< SCU SFSP8_0: MODE Mask */ -#define SCU_SFSP8_0_EPD_Pos 3 /*!< SCU SFSP8_0: EPD Position */ -#define SCU_SFSP8_0_EPD_Msk (0x01UL << SCU_SFSP8_0_EPD_Pos) /*!< SCU SFSP8_0: EPD Mask */ -#define SCU_SFSP8_0_EPUN_Pos 4 /*!< SCU SFSP8_0: EPUN Position */ -#define SCU_SFSP8_0_EPUN_Msk (0x01UL << SCU_SFSP8_0_EPUN_Pos) /*!< SCU SFSP8_0: EPUN Mask */ -#define SCU_SFSP8_0_EHS_Pos 5 /*!< SCU SFSP8_0: EHS Position */ -#define SCU_SFSP8_0_EHS_Msk (0x01UL << SCU_SFSP8_0_EHS_Pos) /*!< SCU SFSP8_0: EHS Mask */ -#define SCU_SFSP8_0_EZI_Pos 6 /*!< SCU SFSP8_0: EZI Position */ -#define SCU_SFSP8_0_EZI_Msk (0x01UL << SCU_SFSP8_0_EZI_Pos) /*!< SCU SFSP8_0: EZI Mask */ -#define SCU_SFSP8_0_EHD_Pos 8 /*!< SCU SFSP8_0: EHD Position */ -#define SCU_SFSP8_0_EHD_Msk (0x03UL << SCU_SFSP8_0_EHD_Pos) /*!< SCU SFSP8_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_1 ------------------------------------------ -#define SCU_SFSP8_1_MODE_Pos 0 /*!< SCU SFSP8_1: MODE Position */ -#define SCU_SFSP8_1_MODE_Msk (0x07UL << SCU_SFSP8_1_MODE_Pos) /*!< SCU SFSP8_1: MODE Mask */ -#define SCU_SFSP8_1_EPD_Pos 3 /*!< SCU SFSP8_1: EPD Position */ -#define SCU_SFSP8_1_EPD_Msk (0x01UL << SCU_SFSP8_1_EPD_Pos) /*!< SCU SFSP8_1: EPD Mask */ -#define SCU_SFSP8_1_EPUN_Pos 4 /*!< SCU SFSP8_1: EPUN Position */ -#define SCU_SFSP8_1_EPUN_Msk (0x01UL << SCU_SFSP8_1_EPUN_Pos) /*!< SCU SFSP8_1: EPUN Mask */ -#define SCU_SFSP8_1_EHS_Pos 5 /*!< SCU SFSP8_1: EHS Position */ -#define SCU_SFSP8_1_EHS_Msk (0x01UL << SCU_SFSP8_1_EHS_Pos) /*!< SCU SFSP8_1: EHS Mask */ -#define SCU_SFSP8_1_EZI_Pos 6 /*!< SCU SFSP8_1: EZI Position */ -#define SCU_SFSP8_1_EZI_Msk (0x01UL << SCU_SFSP8_1_EZI_Pos) /*!< SCU SFSP8_1: EZI Mask */ -#define SCU_SFSP8_1_EHD_Pos 8 /*!< SCU SFSP8_1: EHD Position */ -#define SCU_SFSP8_1_EHD_Msk (0x03UL << SCU_SFSP8_1_EHD_Pos) /*!< SCU SFSP8_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_2 ------------------------------------------ -#define SCU_SFSP8_2_MODE_Pos 0 /*!< SCU SFSP8_2: MODE Position */ -#define SCU_SFSP8_2_MODE_Msk (0x07UL << SCU_SFSP8_2_MODE_Pos) /*!< SCU SFSP8_2: MODE Mask */ -#define SCU_SFSP8_2_EPD_Pos 3 /*!< SCU SFSP8_2: EPD Position */ -#define SCU_SFSP8_2_EPD_Msk (0x01UL << SCU_SFSP8_2_EPD_Pos) /*!< SCU SFSP8_2: EPD Mask */ -#define SCU_SFSP8_2_EPUN_Pos 4 /*!< SCU SFSP8_2: EPUN Position */ -#define SCU_SFSP8_2_EPUN_Msk (0x01UL << SCU_SFSP8_2_EPUN_Pos) /*!< SCU SFSP8_2: EPUN Mask */ -#define SCU_SFSP8_2_EHS_Pos 5 /*!< SCU SFSP8_2: EHS Position */ -#define SCU_SFSP8_2_EHS_Msk (0x01UL << SCU_SFSP8_2_EHS_Pos) /*!< SCU SFSP8_2: EHS Mask */ -#define SCU_SFSP8_2_EZI_Pos 6 /*!< SCU SFSP8_2: EZI Position */ -#define SCU_SFSP8_2_EZI_Msk (0x01UL << SCU_SFSP8_2_EZI_Pos) /*!< SCU SFSP8_2: EZI Mask */ -#define SCU_SFSP8_2_EHD_Pos 8 /*!< SCU SFSP8_2: EHD Position */ -#define SCU_SFSP8_2_EHD_Msk (0x03UL << SCU_SFSP8_2_EHD_Pos) /*!< SCU SFSP8_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_3 ------------------------------------------ -#define SCU_SFSP8_3_MODE_Pos 0 /*!< SCU SFSP8_3: MODE Position */ -#define SCU_SFSP8_3_MODE_Msk (0x07UL << SCU_SFSP8_3_MODE_Pos) /*!< SCU SFSP8_3: MODE Mask */ -#define SCU_SFSP8_3_EPD_Pos 3 /*!< SCU SFSP8_3: EPD Position */ -#define SCU_SFSP8_3_EPD_Msk (0x01UL << SCU_SFSP8_3_EPD_Pos) /*!< SCU SFSP8_3: EPD Mask */ -#define SCU_SFSP8_3_EPUN_Pos 4 /*!< SCU SFSP8_3: EPUN Position */ -#define SCU_SFSP8_3_EPUN_Msk (0x01UL << SCU_SFSP8_3_EPUN_Pos) /*!< SCU SFSP8_3: EPUN Mask */ -#define SCU_SFSP8_3_EHS_Pos 5 /*!< SCU SFSP8_3: EHS Position */ -#define SCU_SFSP8_3_EHS_Msk (0x01UL << SCU_SFSP8_3_EHS_Pos) /*!< SCU SFSP8_3: EHS Mask */ -#define SCU_SFSP8_3_EZI_Pos 6 /*!< SCU SFSP8_3: EZI Position */ -#define SCU_SFSP8_3_EZI_Msk (0x01UL << SCU_SFSP8_3_EZI_Pos) /*!< SCU SFSP8_3: EZI Mask */ -#define SCU_SFSP8_3_EHD_Pos 8 /*!< SCU SFSP8_3: EHD Position */ -#define SCU_SFSP8_3_EHD_Msk (0x03UL << SCU_SFSP8_3_EHD_Pos) /*!< SCU SFSP8_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_4 ------------------------------------------ -#define SCU_SFSP8_4_MODE_Pos 0 /*!< SCU SFSP8_4: MODE Position */ -#define SCU_SFSP8_4_MODE_Msk (0x07UL << SCU_SFSP8_4_MODE_Pos) /*!< SCU SFSP8_4: MODE Mask */ -#define SCU_SFSP8_4_EPD_Pos 3 /*!< SCU SFSP8_4: EPD Position */ -#define SCU_SFSP8_4_EPD_Msk (0x01UL << SCU_SFSP8_4_EPD_Pos) /*!< SCU SFSP8_4: EPD Mask */ -#define SCU_SFSP8_4_EPUN_Pos 4 /*!< SCU SFSP8_4: EPUN Position */ -#define SCU_SFSP8_4_EPUN_Msk (0x01UL << SCU_SFSP8_4_EPUN_Pos) /*!< SCU SFSP8_4: EPUN Mask */ -#define SCU_SFSP8_4_EHS_Pos 5 /*!< SCU SFSP8_4: EHS Position */ -#define SCU_SFSP8_4_EHS_Msk (0x01UL << SCU_SFSP8_4_EHS_Pos) /*!< SCU SFSP8_4: EHS Mask */ -#define SCU_SFSP8_4_EZI_Pos 6 /*!< SCU SFSP8_4: EZI Position */ -#define SCU_SFSP8_4_EZI_Msk (0x01UL << SCU_SFSP8_4_EZI_Pos) /*!< SCU SFSP8_4: EZI Mask */ -#define SCU_SFSP8_4_EHD_Pos 8 /*!< SCU SFSP8_4: EHD Position */ -#define SCU_SFSP8_4_EHD_Msk (0x03UL << SCU_SFSP8_4_EHD_Pos) /*!< SCU SFSP8_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_5 ------------------------------------------ -#define SCU_SFSP8_5_MODE_Pos 0 /*!< SCU SFSP8_5: MODE Position */ -#define SCU_SFSP8_5_MODE_Msk (0x07UL << SCU_SFSP8_5_MODE_Pos) /*!< SCU SFSP8_5: MODE Mask */ -#define SCU_SFSP8_5_EPD_Pos 3 /*!< SCU SFSP8_5: EPD Position */ -#define SCU_SFSP8_5_EPD_Msk (0x01UL << SCU_SFSP8_5_EPD_Pos) /*!< SCU SFSP8_5: EPD Mask */ -#define SCU_SFSP8_5_EPUN_Pos 4 /*!< SCU SFSP8_5: EPUN Position */ -#define SCU_SFSP8_5_EPUN_Msk (0x01UL << SCU_SFSP8_5_EPUN_Pos) /*!< SCU SFSP8_5: EPUN Mask */ -#define SCU_SFSP8_5_EHS_Pos 5 /*!< SCU SFSP8_5: EHS Position */ -#define SCU_SFSP8_5_EHS_Msk (0x01UL << SCU_SFSP8_5_EHS_Pos) /*!< SCU SFSP8_5: EHS Mask */ -#define SCU_SFSP8_5_EZI_Pos 6 /*!< SCU SFSP8_5: EZI Position */ -#define SCU_SFSP8_5_EZI_Msk (0x01UL << SCU_SFSP8_5_EZI_Pos) /*!< SCU SFSP8_5: EZI Mask */ -#define SCU_SFSP8_5_EHD_Pos 8 /*!< SCU SFSP8_5: EHD Position */ -#define SCU_SFSP8_5_EHD_Msk (0x03UL << SCU_SFSP8_5_EHD_Pos) /*!< SCU SFSP8_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_6 ------------------------------------------ -#define SCU_SFSP8_6_MODE_Pos 0 /*!< SCU SFSP8_6: MODE Position */ -#define SCU_SFSP8_6_MODE_Msk (0x07UL << SCU_SFSP8_6_MODE_Pos) /*!< SCU SFSP8_6: MODE Mask */ -#define SCU_SFSP8_6_EPD_Pos 3 /*!< SCU SFSP8_6: EPD Position */ -#define SCU_SFSP8_6_EPD_Msk (0x01UL << SCU_SFSP8_6_EPD_Pos) /*!< SCU SFSP8_6: EPD Mask */ -#define SCU_SFSP8_6_EPUN_Pos 4 /*!< SCU SFSP8_6: EPUN Position */ -#define SCU_SFSP8_6_EPUN_Msk (0x01UL << SCU_SFSP8_6_EPUN_Pos) /*!< SCU SFSP8_6: EPUN Mask */ -#define SCU_SFSP8_6_EHS_Pos 5 /*!< SCU SFSP8_6: EHS Position */ -#define SCU_SFSP8_6_EHS_Msk (0x01UL << SCU_SFSP8_6_EHS_Pos) /*!< SCU SFSP8_6: EHS Mask */ -#define SCU_SFSP8_6_EZI_Pos 6 /*!< SCU SFSP8_6: EZI Position */ -#define SCU_SFSP8_6_EZI_Msk (0x01UL << SCU_SFSP8_6_EZI_Pos) /*!< SCU SFSP8_6: EZI Mask */ -#define SCU_SFSP8_6_EHD_Pos 8 /*!< SCU SFSP8_6: EHD Position */ -#define SCU_SFSP8_6_EHD_Msk (0x03UL << SCU_SFSP8_6_EHD_Pos) /*!< SCU SFSP8_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_7 ------------------------------------------ -#define SCU_SFSP8_7_MODE_Pos 0 /*!< SCU SFSP8_7: MODE Position */ -#define SCU_SFSP8_7_MODE_Msk (0x07UL << SCU_SFSP8_7_MODE_Pos) /*!< SCU SFSP8_7: MODE Mask */ -#define SCU_SFSP8_7_EPD_Pos 3 /*!< SCU SFSP8_7: EPD Position */ -#define SCU_SFSP8_7_EPD_Msk (0x01UL << SCU_SFSP8_7_EPD_Pos) /*!< SCU SFSP8_7: EPD Mask */ -#define SCU_SFSP8_7_EPUN_Pos 4 /*!< SCU SFSP8_7: EPUN Position */ -#define SCU_SFSP8_7_EPUN_Msk (0x01UL << SCU_SFSP8_7_EPUN_Pos) /*!< SCU SFSP8_7: EPUN Mask */ -#define SCU_SFSP8_7_EHS_Pos 5 /*!< SCU SFSP8_7: EHS Position */ -#define SCU_SFSP8_7_EHS_Msk (0x01UL << SCU_SFSP8_7_EHS_Pos) /*!< SCU SFSP8_7: EHS Mask */ -#define SCU_SFSP8_7_EZI_Pos 6 /*!< SCU SFSP8_7: EZI Position */ -#define SCU_SFSP8_7_EZI_Msk (0x01UL << SCU_SFSP8_7_EZI_Pos) /*!< SCU SFSP8_7: EZI Mask */ -#define SCU_SFSP8_7_EHD_Pos 8 /*!< SCU SFSP8_7: EHD Position */ -#define SCU_SFSP8_7_EHD_Msk (0x03UL << SCU_SFSP8_7_EHD_Pos) /*!< SCU SFSP8_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_8 ------------------------------------------ -#define SCU_SFSP8_8_MODE_Pos 0 /*!< SCU SFSP8_8: MODE Position */ -#define SCU_SFSP8_8_MODE_Msk (0x07UL << SCU_SFSP8_8_MODE_Pos) /*!< SCU SFSP8_8: MODE Mask */ -#define SCU_SFSP8_8_EPD_Pos 3 /*!< SCU SFSP8_8: EPD Position */ -#define SCU_SFSP8_8_EPD_Msk (0x01UL << SCU_SFSP8_8_EPD_Pos) /*!< SCU SFSP8_8: EPD Mask */ -#define SCU_SFSP8_8_EPUN_Pos 4 /*!< SCU SFSP8_8: EPUN Position */ -#define SCU_SFSP8_8_EPUN_Msk (0x01UL << SCU_SFSP8_8_EPUN_Pos) /*!< SCU SFSP8_8: EPUN Mask */ -#define SCU_SFSP8_8_EHS_Pos 5 /*!< SCU SFSP8_8: EHS Position */ -#define SCU_SFSP8_8_EHS_Msk (0x01UL << SCU_SFSP8_8_EHS_Pos) /*!< SCU SFSP8_8: EHS Mask */ -#define SCU_SFSP8_8_EZI_Pos 6 /*!< SCU SFSP8_8: EZI Position */ -#define SCU_SFSP8_8_EZI_Msk (0x01UL << SCU_SFSP8_8_EZI_Pos) /*!< SCU SFSP8_8: EZI Mask */ -#define SCU_SFSP8_8_EHD_Pos 8 /*!< SCU SFSP8_8: EHD Position */ -#define SCU_SFSP8_8_EHD_Msk (0x03UL << SCU_SFSP8_8_EHD_Pos) /*!< SCU SFSP8_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_0 ------------------------------------------ -#define SCU_SFSP9_0_MODE_Pos 0 /*!< SCU SFSP9_0: MODE Position */ -#define SCU_SFSP9_0_MODE_Msk (0x07UL << SCU_SFSP9_0_MODE_Pos) /*!< SCU SFSP9_0: MODE Mask */ -#define SCU_SFSP9_0_EPD_Pos 3 /*!< SCU SFSP9_0: EPD Position */ -#define SCU_SFSP9_0_EPD_Msk (0x01UL << SCU_SFSP9_0_EPD_Pos) /*!< SCU SFSP9_0: EPD Mask */ -#define SCU_SFSP9_0_EPUN_Pos 4 /*!< SCU SFSP9_0: EPUN Position */ -#define SCU_SFSP9_0_EPUN_Msk (0x01UL << SCU_SFSP9_0_EPUN_Pos) /*!< SCU SFSP9_0: EPUN Mask */ -#define SCU_SFSP9_0_EHS_Pos 5 /*!< SCU SFSP9_0: EHS Position */ -#define SCU_SFSP9_0_EHS_Msk (0x01UL << SCU_SFSP9_0_EHS_Pos) /*!< SCU SFSP9_0: EHS Mask */ -#define SCU_SFSP9_0_EZI_Pos 6 /*!< SCU SFSP9_0: EZI Position */ -#define SCU_SFSP9_0_EZI_Msk (0x01UL << SCU_SFSP9_0_EZI_Pos) /*!< SCU SFSP9_0: EZI Mask */ -#define SCU_SFSP9_0_EHD_Pos 8 /*!< SCU SFSP9_0: EHD Position */ -#define SCU_SFSP9_0_EHD_Msk (0x03UL << SCU_SFSP9_0_EHD_Pos) /*!< SCU SFSP9_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_1 ------------------------------------------ -#define SCU_SFSP9_1_MODE_Pos 0 /*!< SCU SFSP9_1: MODE Position */ -#define SCU_SFSP9_1_MODE_Msk (0x07UL << SCU_SFSP9_1_MODE_Pos) /*!< SCU SFSP9_1: MODE Mask */ -#define SCU_SFSP9_1_EPD_Pos 3 /*!< SCU SFSP9_1: EPD Position */ -#define SCU_SFSP9_1_EPD_Msk (0x01UL << SCU_SFSP9_1_EPD_Pos) /*!< SCU SFSP9_1: EPD Mask */ -#define SCU_SFSP9_1_EPUN_Pos 4 /*!< SCU SFSP9_1: EPUN Position */ -#define SCU_SFSP9_1_EPUN_Msk (0x01UL << SCU_SFSP9_1_EPUN_Pos) /*!< SCU SFSP9_1: EPUN Mask */ -#define SCU_SFSP9_1_EHS_Pos 5 /*!< SCU SFSP9_1: EHS Position */ -#define SCU_SFSP9_1_EHS_Msk (0x01UL << SCU_SFSP9_1_EHS_Pos) /*!< SCU SFSP9_1: EHS Mask */ -#define SCU_SFSP9_1_EZI_Pos 6 /*!< SCU SFSP9_1: EZI Position */ -#define SCU_SFSP9_1_EZI_Msk (0x01UL << SCU_SFSP9_1_EZI_Pos) /*!< SCU SFSP9_1: EZI Mask */ -#define SCU_SFSP9_1_EHD_Pos 8 /*!< SCU SFSP9_1: EHD Position */ -#define SCU_SFSP9_1_EHD_Msk (0x03UL << SCU_SFSP9_1_EHD_Pos) /*!< SCU SFSP9_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_2 ------------------------------------------ -#define SCU_SFSP9_2_MODE_Pos 0 /*!< SCU SFSP9_2: MODE Position */ -#define SCU_SFSP9_2_MODE_Msk (0x07UL << SCU_SFSP9_2_MODE_Pos) /*!< SCU SFSP9_2: MODE Mask */ -#define SCU_SFSP9_2_EPD_Pos 3 /*!< SCU SFSP9_2: EPD Position */ -#define SCU_SFSP9_2_EPD_Msk (0x01UL << SCU_SFSP9_2_EPD_Pos) /*!< SCU SFSP9_2: EPD Mask */ -#define SCU_SFSP9_2_EPUN_Pos 4 /*!< SCU SFSP9_2: EPUN Position */ -#define SCU_SFSP9_2_EPUN_Msk (0x01UL << SCU_SFSP9_2_EPUN_Pos) /*!< SCU SFSP9_2: EPUN Mask */ -#define SCU_SFSP9_2_EHS_Pos 5 /*!< SCU SFSP9_2: EHS Position */ -#define SCU_SFSP9_2_EHS_Msk (0x01UL << SCU_SFSP9_2_EHS_Pos) /*!< SCU SFSP9_2: EHS Mask */ -#define SCU_SFSP9_2_EZI_Pos 6 /*!< SCU SFSP9_2: EZI Position */ -#define SCU_SFSP9_2_EZI_Msk (0x01UL << SCU_SFSP9_2_EZI_Pos) /*!< SCU SFSP9_2: EZI Mask */ -#define SCU_SFSP9_2_EHD_Pos 8 /*!< SCU SFSP9_2: EHD Position */ -#define SCU_SFSP9_2_EHD_Msk (0x03UL << SCU_SFSP9_2_EHD_Pos) /*!< SCU SFSP9_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_3 ------------------------------------------ -#define SCU_SFSP9_3_MODE_Pos 0 /*!< SCU SFSP9_3: MODE Position */ -#define SCU_SFSP9_3_MODE_Msk (0x07UL << SCU_SFSP9_3_MODE_Pos) /*!< SCU SFSP9_3: MODE Mask */ -#define SCU_SFSP9_3_EPD_Pos 3 /*!< SCU SFSP9_3: EPD Position */ -#define SCU_SFSP9_3_EPD_Msk (0x01UL << SCU_SFSP9_3_EPD_Pos) /*!< SCU SFSP9_3: EPD Mask */ -#define SCU_SFSP9_3_EPUN_Pos 4 /*!< SCU SFSP9_3: EPUN Position */ -#define SCU_SFSP9_3_EPUN_Msk (0x01UL << SCU_SFSP9_3_EPUN_Pos) /*!< SCU SFSP9_3: EPUN Mask */ -#define SCU_SFSP9_3_EHS_Pos 5 /*!< SCU SFSP9_3: EHS Position */ -#define SCU_SFSP9_3_EHS_Msk (0x01UL << SCU_SFSP9_3_EHS_Pos) /*!< SCU SFSP9_3: EHS Mask */ -#define SCU_SFSP9_3_EZI_Pos 6 /*!< SCU SFSP9_3: EZI Position */ -#define SCU_SFSP9_3_EZI_Msk (0x01UL << SCU_SFSP9_3_EZI_Pos) /*!< SCU SFSP9_3: EZI Mask */ -#define SCU_SFSP9_3_EHD_Pos 8 /*!< SCU SFSP9_3: EHD Position */ -#define SCU_SFSP9_3_EHD_Msk (0x03UL << SCU_SFSP9_3_EHD_Pos) /*!< SCU SFSP9_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_4 ------------------------------------------ -#define SCU_SFSP9_4_MODE_Pos 0 /*!< SCU SFSP9_4: MODE Position */ -#define SCU_SFSP9_4_MODE_Msk (0x07UL << SCU_SFSP9_4_MODE_Pos) /*!< SCU SFSP9_4: MODE Mask */ -#define SCU_SFSP9_4_EPD_Pos 3 /*!< SCU SFSP9_4: EPD Position */ -#define SCU_SFSP9_4_EPD_Msk (0x01UL << SCU_SFSP9_4_EPD_Pos) /*!< SCU SFSP9_4: EPD Mask */ -#define SCU_SFSP9_4_EPUN_Pos 4 /*!< SCU SFSP9_4: EPUN Position */ -#define SCU_SFSP9_4_EPUN_Msk (0x01UL << SCU_SFSP9_4_EPUN_Pos) /*!< SCU SFSP9_4: EPUN Mask */ -#define SCU_SFSP9_4_EHS_Pos 5 /*!< SCU SFSP9_4: EHS Position */ -#define SCU_SFSP9_4_EHS_Msk (0x01UL << SCU_SFSP9_4_EHS_Pos) /*!< SCU SFSP9_4: EHS Mask */ -#define SCU_SFSP9_4_EZI_Pos 6 /*!< SCU SFSP9_4: EZI Position */ -#define SCU_SFSP9_4_EZI_Msk (0x01UL << SCU_SFSP9_4_EZI_Pos) /*!< SCU SFSP9_4: EZI Mask */ -#define SCU_SFSP9_4_EHD_Pos 8 /*!< SCU SFSP9_4: EHD Position */ -#define SCU_SFSP9_4_EHD_Msk (0x03UL << SCU_SFSP9_4_EHD_Pos) /*!< SCU SFSP9_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_5 ------------------------------------------ -#define SCU_SFSP9_5_MODE_Pos 0 /*!< SCU SFSP9_5: MODE Position */ -#define SCU_SFSP9_5_MODE_Msk (0x07UL << SCU_SFSP9_5_MODE_Pos) /*!< SCU SFSP9_5: MODE Mask */ -#define SCU_SFSP9_5_EPD_Pos 3 /*!< SCU SFSP9_5: EPD Position */ -#define SCU_SFSP9_5_EPD_Msk (0x01UL << SCU_SFSP9_5_EPD_Pos) /*!< SCU SFSP9_5: EPD Mask */ -#define SCU_SFSP9_5_EPUN_Pos 4 /*!< SCU SFSP9_5: EPUN Position */ -#define SCU_SFSP9_5_EPUN_Msk (0x01UL << SCU_SFSP9_5_EPUN_Pos) /*!< SCU SFSP9_5: EPUN Mask */ -#define SCU_SFSP9_5_EHS_Pos 5 /*!< SCU SFSP9_5: EHS Position */ -#define SCU_SFSP9_5_EHS_Msk (0x01UL << SCU_SFSP9_5_EHS_Pos) /*!< SCU SFSP9_5: EHS Mask */ -#define SCU_SFSP9_5_EZI_Pos 6 /*!< SCU SFSP9_5: EZI Position */ -#define SCU_SFSP9_5_EZI_Msk (0x01UL << SCU_SFSP9_5_EZI_Pos) /*!< SCU SFSP9_5: EZI Mask */ -#define SCU_SFSP9_5_EHD_Pos 8 /*!< SCU SFSP9_5: EHD Position */ -#define SCU_SFSP9_5_EHD_Msk (0x03UL << SCU_SFSP9_5_EHD_Pos) /*!< SCU SFSP9_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_6 ------------------------------------------ -#define SCU_SFSP9_6_MODE_Pos 0 /*!< SCU SFSP9_6: MODE Position */ -#define SCU_SFSP9_6_MODE_Msk (0x07UL << SCU_SFSP9_6_MODE_Pos) /*!< SCU SFSP9_6: MODE Mask */ -#define SCU_SFSP9_6_EPD_Pos 3 /*!< SCU SFSP9_6: EPD Position */ -#define SCU_SFSP9_6_EPD_Msk (0x01UL << SCU_SFSP9_6_EPD_Pos) /*!< SCU SFSP9_6: EPD Mask */ -#define SCU_SFSP9_6_EPUN_Pos 4 /*!< SCU SFSP9_6: EPUN Position */ -#define SCU_SFSP9_6_EPUN_Msk (0x01UL << SCU_SFSP9_6_EPUN_Pos) /*!< SCU SFSP9_6: EPUN Mask */ -#define SCU_SFSP9_6_EHS_Pos 5 /*!< SCU SFSP9_6: EHS Position */ -#define SCU_SFSP9_6_EHS_Msk (0x01UL << SCU_SFSP9_6_EHS_Pos) /*!< SCU SFSP9_6: EHS Mask */ -#define SCU_SFSP9_6_EZI_Pos 6 /*!< SCU SFSP9_6: EZI Position */ -#define SCU_SFSP9_6_EZI_Msk (0x01UL << SCU_SFSP9_6_EZI_Pos) /*!< SCU SFSP9_6: EZI Mask */ -#define SCU_SFSP9_6_EHD_Pos 8 /*!< SCU SFSP9_6: EHD Position */ -#define SCU_SFSP9_6_EHD_Msk (0x03UL << SCU_SFSP9_6_EHD_Pos) /*!< SCU SFSP9_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_0 ------------------------------------------ -#define SCU_SFSPA_0_MODE_Pos 0 /*!< SCU SFSPA_0: MODE Position */ -#define SCU_SFSPA_0_MODE_Msk (0x07UL << SCU_SFSPA_0_MODE_Pos) /*!< SCU SFSPA_0: MODE Mask */ -#define SCU_SFSPA_0_EPD_Pos 3 /*!< SCU SFSPA_0: EPD Position */ -#define SCU_SFSPA_0_EPD_Msk (0x01UL << SCU_SFSPA_0_EPD_Pos) /*!< SCU SFSPA_0: EPD Mask */ -#define SCU_SFSPA_0_EPUN_Pos 4 /*!< SCU SFSPA_0: EPUN Position */ -#define SCU_SFSPA_0_EPUN_Msk (0x01UL << SCU_SFSPA_0_EPUN_Pos) /*!< SCU SFSPA_0: EPUN Mask */ -#define SCU_SFSPA_0_EHS_Pos 5 /*!< SCU SFSPA_0: EHS Position */ -#define SCU_SFSPA_0_EHS_Msk (0x01UL << SCU_SFSPA_0_EHS_Pos) /*!< SCU SFSPA_0: EHS Mask */ -#define SCU_SFSPA_0_EZI_Pos 6 /*!< SCU SFSPA_0: EZI Position */ -#define SCU_SFSPA_0_EZI_Msk (0x01UL << SCU_SFSPA_0_EZI_Pos) /*!< SCU SFSPA_0: EZI Mask */ -#define SCU_SFSPA_0_EHD_Pos 8 /*!< SCU SFSPA_0: EHD Position */ -#define SCU_SFSPA_0_EHD_Msk (0x03UL << SCU_SFSPA_0_EHD_Pos) /*!< SCU SFSPA_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_1 ------------------------------------------ -#define SCU_SFSPA_1_MODE_Pos 0 /*!< SCU SFSPA_1: MODE Position */ -#define SCU_SFSPA_1_MODE_Msk (0x07UL << SCU_SFSPA_1_MODE_Pos) /*!< SCU SFSPA_1: MODE Mask */ -#define SCU_SFSPA_1_EPD_Pos 3 /*!< SCU SFSPA_1: EPD Position */ -#define SCU_SFSPA_1_EPD_Msk (0x01UL << SCU_SFSPA_1_EPD_Pos) /*!< SCU SFSPA_1: EPD Mask */ -#define SCU_SFSPA_1_EPUN_Pos 4 /*!< SCU SFSPA_1: EPUN Position */ -#define SCU_SFSPA_1_EPUN_Msk (0x01UL << SCU_SFSPA_1_EPUN_Pos) /*!< SCU SFSPA_1: EPUN Mask */ -#define SCU_SFSPA_1_EHS_Pos 5 /*!< SCU SFSPA_1: EHS Position */ -#define SCU_SFSPA_1_EHS_Msk (0x01UL << SCU_SFSPA_1_EHS_Pos) /*!< SCU SFSPA_1: EHS Mask */ -#define SCU_SFSPA_1_EZI_Pos 6 /*!< SCU SFSPA_1: EZI Position */ -#define SCU_SFSPA_1_EZI_Msk (0x01UL << SCU_SFSPA_1_EZI_Pos) /*!< SCU SFSPA_1: EZI Mask */ -#define SCU_SFSPA_1_EHD_Pos 8 /*!< SCU SFSPA_1: EHD Position */ -#define SCU_SFSPA_1_EHD_Msk (0x03UL << SCU_SFSPA_1_EHD_Pos) /*!< SCU SFSPA_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_2 ------------------------------------------ -#define SCU_SFSPA_2_MODE_Pos 0 /*!< SCU SFSPA_2: MODE Position */ -#define SCU_SFSPA_2_MODE_Msk (0x07UL << SCU_SFSPA_2_MODE_Pos) /*!< SCU SFSPA_2: MODE Mask */ -#define SCU_SFSPA_2_EPD_Pos 3 /*!< SCU SFSPA_2: EPD Position */ -#define SCU_SFSPA_2_EPD_Msk (0x01UL << SCU_SFSPA_2_EPD_Pos) /*!< SCU SFSPA_2: EPD Mask */ -#define SCU_SFSPA_2_EPUN_Pos 4 /*!< SCU SFSPA_2: EPUN Position */ -#define SCU_SFSPA_2_EPUN_Msk (0x01UL << SCU_SFSPA_2_EPUN_Pos) /*!< SCU SFSPA_2: EPUN Mask */ -#define SCU_SFSPA_2_EHS_Pos 5 /*!< SCU SFSPA_2: EHS Position */ -#define SCU_SFSPA_2_EHS_Msk (0x01UL << SCU_SFSPA_2_EHS_Pos) /*!< SCU SFSPA_2: EHS Mask */ -#define SCU_SFSPA_2_EZI_Pos 6 /*!< SCU SFSPA_2: EZI Position */ -#define SCU_SFSPA_2_EZI_Msk (0x01UL << SCU_SFSPA_2_EZI_Pos) /*!< SCU SFSPA_2: EZI Mask */ -#define SCU_SFSPA_2_EHD_Pos 8 /*!< SCU SFSPA_2: EHD Position */ -#define SCU_SFSPA_2_EHD_Msk (0x03UL << SCU_SFSPA_2_EHD_Pos) /*!< SCU SFSPA_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_3 ------------------------------------------ -#define SCU_SFSPA_3_MODE_Pos 0 /*!< SCU SFSPA_3: MODE Position */ -#define SCU_SFSPA_3_MODE_Msk (0x07UL << SCU_SFSPA_3_MODE_Pos) /*!< SCU SFSPA_3: MODE Mask */ -#define SCU_SFSPA_3_EPD_Pos 3 /*!< SCU SFSPA_3: EPD Position */ -#define SCU_SFSPA_3_EPD_Msk (0x01UL << SCU_SFSPA_3_EPD_Pos) /*!< SCU SFSPA_3: EPD Mask */ -#define SCU_SFSPA_3_EPUN_Pos 4 /*!< SCU SFSPA_3: EPUN Position */ -#define SCU_SFSPA_3_EPUN_Msk (0x01UL << SCU_SFSPA_3_EPUN_Pos) /*!< SCU SFSPA_3: EPUN Mask */ -#define SCU_SFSPA_3_EHS_Pos 5 /*!< SCU SFSPA_3: EHS Position */ -#define SCU_SFSPA_3_EHS_Msk (0x01UL << SCU_SFSPA_3_EHS_Pos) /*!< SCU SFSPA_3: EHS Mask */ -#define SCU_SFSPA_3_EZI_Pos 6 /*!< SCU SFSPA_3: EZI Position */ -#define SCU_SFSPA_3_EZI_Msk (0x01UL << SCU_SFSPA_3_EZI_Pos) /*!< SCU SFSPA_3: EZI Mask */ -#define SCU_SFSPA_3_EHD_Pos 8 /*!< SCU SFSPA_3: EHD Position */ -#define SCU_SFSPA_3_EHD_Msk (0x03UL << SCU_SFSPA_3_EHD_Pos) /*!< SCU SFSPA_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_4 ------------------------------------------ -#define SCU_SFSPA_4_MODE_Pos 0 /*!< SCU SFSPA_4: MODE Position */ -#define SCU_SFSPA_4_MODE_Msk (0x07UL << SCU_SFSPA_4_MODE_Pos) /*!< SCU SFSPA_4: MODE Mask */ -#define SCU_SFSPA_4_EPD_Pos 3 /*!< SCU SFSPA_4: EPD Position */ -#define SCU_SFSPA_4_EPD_Msk (0x01UL << SCU_SFSPA_4_EPD_Pos) /*!< SCU SFSPA_4: EPD Mask */ -#define SCU_SFSPA_4_EPUN_Pos 4 /*!< SCU SFSPA_4: EPUN Position */ -#define SCU_SFSPA_4_EPUN_Msk (0x01UL << SCU_SFSPA_4_EPUN_Pos) /*!< SCU SFSPA_4: EPUN Mask */ -#define SCU_SFSPA_4_EHS_Pos 5 /*!< SCU SFSPA_4: EHS Position */ -#define SCU_SFSPA_4_EHS_Msk (0x01UL << SCU_SFSPA_4_EHS_Pos) /*!< SCU SFSPA_4: EHS Mask */ -#define SCU_SFSPA_4_EZI_Pos 6 /*!< SCU SFSPA_4: EZI Position */ -#define SCU_SFSPA_4_EZI_Msk (0x01UL << SCU_SFSPA_4_EZI_Pos) /*!< SCU SFSPA_4: EZI Mask */ -#define SCU_SFSPA_4_EHD_Pos 8 /*!< SCU SFSPA_4: EHD Position */ -#define SCU_SFSPA_4_EHD_Msk (0x03UL << SCU_SFSPA_4_EHD_Pos) /*!< SCU SFSPA_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_0 ------------------------------------------ -#define SCU_SFSPB_0_MODE_Pos 0 /*!< SCU SFSPB_0: MODE Position */ -#define SCU_SFSPB_0_MODE_Msk (0x07UL << SCU_SFSPB_0_MODE_Pos) /*!< SCU SFSPB_0: MODE Mask */ -#define SCU_SFSPB_0_EPD_Pos 3 /*!< SCU SFSPB_0: EPD Position */ -#define SCU_SFSPB_0_EPD_Msk (0x01UL << SCU_SFSPB_0_EPD_Pos) /*!< SCU SFSPB_0: EPD Mask */ -#define SCU_SFSPB_0_EPUN_Pos 4 /*!< SCU SFSPB_0: EPUN Position */ -#define SCU_SFSPB_0_EPUN_Msk (0x01UL << SCU_SFSPB_0_EPUN_Pos) /*!< SCU SFSPB_0: EPUN Mask */ -#define SCU_SFSPB_0_EHS_Pos 5 /*!< SCU SFSPB_0: EHS Position */ -#define SCU_SFSPB_0_EHS_Msk (0x01UL << SCU_SFSPB_0_EHS_Pos) /*!< SCU SFSPB_0: EHS Mask */ -#define SCU_SFSPB_0_EZI_Pos 6 /*!< SCU SFSPB_0: EZI Position */ -#define SCU_SFSPB_0_EZI_Msk (0x01UL << SCU_SFSPB_0_EZI_Pos) /*!< SCU SFSPB_0: EZI Mask */ -#define SCU_SFSPB_0_EHD_Pos 8 /*!< SCU SFSPB_0: EHD Position */ -#define SCU_SFSPB_0_EHD_Msk (0x03UL << SCU_SFSPB_0_EHD_Pos) /*!< SCU SFSPB_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_1 ------------------------------------------ -#define SCU_SFSPB_1_MODE_Pos 0 /*!< SCU SFSPB_1: MODE Position */ -#define SCU_SFSPB_1_MODE_Msk (0x07UL << SCU_SFSPB_1_MODE_Pos) /*!< SCU SFSPB_1: MODE Mask */ -#define SCU_SFSPB_1_EPD_Pos 3 /*!< SCU SFSPB_1: EPD Position */ -#define SCU_SFSPB_1_EPD_Msk (0x01UL << SCU_SFSPB_1_EPD_Pos) /*!< SCU SFSPB_1: EPD Mask */ -#define SCU_SFSPB_1_EPUN_Pos 4 /*!< SCU SFSPB_1: EPUN Position */ -#define SCU_SFSPB_1_EPUN_Msk (0x01UL << SCU_SFSPB_1_EPUN_Pos) /*!< SCU SFSPB_1: EPUN Mask */ -#define SCU_SFSPB_1_EHS_Pos 5 /*!< SCU SFSPB_1: EHS Position */ -#define SCU_SFSPB_1_EHS_Msk (0x01UL << SCU_SFSPB_1_EHS_Pos) /*!< SCU SFSPB_1: EHS Mask */ -#define SCU_SFSPB_1_EZI_Pos 6 /*!< SCU SFSPB_1: EZI Position */ -#define SCU_SFSPB_1_EZI_Msk (0x01UL << SCU_SFSPB_1_EZI_Pos) /*!< SCU SFSPB_1: EZI Mask */ -#define SCU_SFSPB_1_EHD_Pos 8 /*!< SCU SFSPB_1: EHD Position */ -#define SCU_SFSPB_1_EHD_Msk (0x03UL << SCU_SFSPB_1_EHD_Pos) /*!< SCU SFSPB_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_2 ------------------------------------------ -#define SCU_SFSPB_2_MODE_Pos 0 /*!< SCU SFSPB_2: MODE Position */ -#define SCU_SFSPB_2_MODE_Msk (0x07UL << SCU_SFSPB_2_MODE_Pos) /*!< SCU SFSPB_2: MODE Mask */ -#define SCU_SFSPB_2_EPD_Pos 3 /*!< SCU SFSPB_2: EPD Position */ -#define SCU_SFSPB_2_EPD_Msk (0x01UL << SCU_SFSPB_2_EPD_Pos) /*!< SCU SFSPB_2: EPD Mask */ -#define SCU_SFSPB_2_EPUN_Pos 4 /*!< SCU SFSPB_2: EPUN Position */ -#define SCU_SFSPB_2_EPUN_Msk (0x01UL << SCU_SFSPB_2_EPUN_Pos) /*!< SCU SFSPB_2: EPUN Mask */ -#define SCU_SFSPB_2_EHS_Pos 5 /*!< SCU SFSPB_2: EHS Position */ -#define SCU_SFSPB_2_EHS_Msk (0x01UL << SCU_SFSPB_2_EHS_Pos) /*!< SCU SFSPB_2: EHS Mask */ -#define SCU_SFSPB_2_EZI_Pos 6 /*!< SCU SFSPB_2: EZI Position */ -#define SCU_SFSPB_2_EZI_Msk (0x01UL << SCU_SFSPB_2_EZI_Pos) /*!< SCU SFSPB_2: EZI Mask */ -#define SCU_SFSPB_2_EHD_Pos 8 /*!< SCU SFSPB_2: EHD Position */ -#define SCU_SFSPB_2_EHD_Msk (0x03UL << SCU_SFSPB_2_EHD_Pos) /*!< SCU SFSPB_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_3 ------------------------------------------ -#define SCU_SFSPB_3_MODE_Pos 0 /*!< SCU SFSPB_3: MODE Position */ -#define SCU_SFSPB_3_MODE_Msk (0x07UL << SCU_SFSPB_3_MODE_Pos) /*!< SCU SFSPB_3: MODE Mask */ -#define SCU_SFSPB_3_EPD_Pos 3 /*!< SCU SFSPB_3: EPD Position */ -#define SCU_SFSPB_3_EPD_Msk (0x01UL << SCU_SFSPB_3_EPD_Pos) /*!< SCU SFSPB_3: EPD Mask */ -#define SCU_SFSPB_3_EPUN_Pos 4 /*!< SCU SFSPB_3: EPUN Position */ -#define SCU_SFSPB_3_EPUN_Msk (0x01UL << SCU_SFSPB_3_EPUN_Pos) /*!< SCU SFSPB_3: EPUN Mask */ -#define SCU_SFSPB_3_EHS_Pos 5 /*!< SCU SFSPB_3: EHS Position */ -#define SCU_SFSPB_3_EHS_Msk (0x01UL << SCU_SFSPB_3_EHS_Pos) /*!< SCU SFSPB_3: EHS Mask */ -#define SCU_SFSPB_3_EZI_Pos 6 /*!< SCU SFSPB_3: EZI Position */ -#define SCU_SFSPB_3_EZI_Msk (0x01UL << SCU_SFSPB_3_EZI_Pos) /*!< SCU SFSPB_3: EZI Mask */ -#define SCU_SFSPB_3_EHD_Pos 8 /*!< SCU SFSPB_3: EHD Position */ -#define SCU_SFSPB_3_EHD_Msk (0x03UL << SCU_SFSPB_3_EHD_Pos) /*!< SCU SFSPB_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_4 ------------------------------------------ -#define SCU_SFSPB_4_MODE_Pos 0 /*!< SCU SFSPB_4: MODE Position */ -#define SCU_SFSPB_4_MODE_Msk (0x07UL << SCU_SFSPB_4_MODE_Pos) /*!< SCU SFSPB_4: MODE Mask */ -#define SCU_SFSPB_4_EPD_Pos 3 /*!< SCU SFSPB_4: EPD Position */ -#define SCU_SFSPB_4_EPD_Msk (0x01UL << SCU_SFSPB_4_EPD_Pos) /*!< SCU SFSPB_4: EPD Mask */ -#define SCU_SFSPB_4_EPUN_Pos 4 /*!< SCU SFSPB_4: EPUN Position */ -#define SCU_SFSPB_4_EPUN_Msk (0x01UL << SCU_SFSPB_4_EPUN_Pos) /*!< SCU SFSPB_4: EPUN Mask */ -#define SCU_SFSPB_4_EHS_Pos 5 /*!< SCU SFSPB_4: EHS Position */ -#define SCU_SFSPB_4_EHS_Msk (0x01UL << SCU_SFSPB_4_EHS_Pos) /*!< SCU SFSPB_4: EHS Mask */ -#define SCU_SFSPB_4_EZI_Pos 6 /*!< SCU SFSPB_4: EZI Position */ -#define SCU_SFSPB_4_EZI_Msk (0x01UL << SCU_SFSPB_4_EZI_Pos) /*!< SCU SFSPB_4: EZI Mask */ -#define SCU_SFSPB_4_EHD_Pos 8 /*!< SCU SFSPB_4: EHD Position */ -#define SCU_SFSPB_4_EHD_Msk (0x03UL << SCU_SFSPB_4_EHD_Pos) /*!< SCU SFSPB_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_5 ------------------------------------------ -#define SCU_SFSPB_5_MODE_Pos 0 /*!< SCU SFSPB_5: MODE Position */ -#define SCU_SFSPB_5_MODE_Msk (0x07UL << SCU_SFSPB_5_MODE_Pos) /*!< SCU SFSPB_5: MODE Mask */ -#define SCU_SFSPB_5_EPD_Pos 3 /*!< SCU SFSPB_5: EPD Position */ -#define SCU_SFSPB_5_EPD_Msk (0x01UL << SCU_SFSPB_5_EPD_Pos) /*!< SCU SFSPB_5: EPD Mask */ -#define SCU_SFSPB_5_EPUN_Pos 4 /*!< SCU SFSPB_5: EPUN Position */ -#define SCU_SFSPB_5_EPUN_Msk (0x01UL << SCU_SFSPB_5_EPUN_Pos) /*!< SCU SFSPB_5: EPUN Mask */ -#define SCU_SFSPB_5_EHS_Pos 5 /*!< SCU SFSPB_5: EHS Position */ -#define SCU_SFSPB_5_EHS_Msk (0x01UL << SCU_SFSPB_5_EHS_Pos) /*!< SCU SFSPB_5: EHS Mask */ -#define SCU_SFSPB_5_EZI_Pos 6 /*!< SCU SFSPB_5: EZI Position */ -#define SCU_SFSPB_5_EZI_Msk (0x01UL << SCU_SFSPB_5_EZI_Pos) /*!< SCU SFSPB_5: EZI Mask */ -#define SCU_SFSPB_5_EHD_Pos 8 /*!< SCU SFSPB_5: EHD Position */ -#define SCU_SFSPB_5_EHD_Msk (0x03UL << SCU_SFSPB_5_EHD_Pos) /*!< SCU SFSPB_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_6 ------------------------------------------ -#define SCU_SFSPB_6_MODE_Pos 0 /*!< SCU SFSPB_6: MODE Position */ -#define SCU_SFSPB_6_MODE_Msk (0x07UL << SCU_SFSPB_6_MODE_Pos) /*!< SCU SFSPB_6: MODE Mask */ -#define SCU_SFSPB_6_EPD_Pos 3 /*!< SCU SFSPB_6: EPD Position */ -#define SCU_SFSPB_6_EPD_Msk (0x01UL << SCU_SFSPB_6_EPD_Pos) /*!< SCU SFSPB_6: EPD Mask */ -#define SCU_SFSPB_6_EPUN_Pos 4 /*!< SCU SFSPB_6: EPUN Position */ -#define SCU_SFSPB_6_EPUN_Msk (0x01UL << SCU_SFSPB_6_EPUN_Pos) /*!< SCU SFSPB_6: EPUN Mask */ -#define SCU_SFSPB_6_EHS_Pos 5 /*!< SCU SFSPB_6: EHS Position */ -#define SCU_SFSPB_6_EHS_Msk (0x01UL << SCU_SFSPB_6_EHS_Pos) /*!< SCU SFSPB_6: EHS Mask */ -#define SCU_SFSPB_6_EZI_Pos 6 /*!< SCU SFSPB_6: EZI Position */ -#define SCU_SFSPB_6_EZI_Msk (0x01UL << SCU_SFSPB_6_EZI_Pos) /*!< SCU SFSPB_6: EZI Mask */ -#define SCU_SFSPB_6_EHD_Pos 8 /*!< SCU SFSPB_6: EHD Position */ -#define SCU_SFSPB_6_EHD_Msk (0x03UL << SCU_SFSPB_6_EHD_Pos) /*!< SCU SFSPB_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_0 ------------------------------------------ -#define SCU_SFSPC_0_MODE_Pos 0 /*!< SCU SFSPC_0: MODE Position */ -#define SCU_SFSPC_0_MODE_Msk (0x07UL << SCU_SFSPC_0_MODE_Pos) /*!< SCU SFSPC_0: MODE Mask */ -#define SCU_SFSPC_0_EPD_Pos 3 /*!< SCU SFSPC_0: EPD Position */ -#define SCU_SFSPC_0_EPD_Msk (0x01UL << SCU_SFSPC_0_EPD_Pos) /*!< SCU SFSPC_0: EPD Mask */ -#define SCU_SFSPC_0_EPUN_Pos 4 /*!< SCU SFSPC_0: EPUN Position */ -#define SCU_SFSPC_0_EPUN_Msk (0x01UL << SCU_SFSPC_0_EPUN_Pos) /*!< SCU SFSPC_0: EPUN Mask */ -#define SCU_SFSPC_0_EHS_Pos 5 /*!< SCU SFSPC_0: EHS Position */ -#define SCU_SFSPC_0_EHS_Msk (0x01UL << SCU_SFSPC_0_EHS_Pos) /*!< SCU SFSPC_0: EHS Mask */ -#define SCU_SFSPC_0_EZI_Pos 6 /*!< SCU SFSPC_0: EZI Position */ -#define SCU_SFSPC_0_EZI_Msk (0x01UL << SCU_SFSPC_0_EZI_Pos) /*!< SCU SFSPC_0: EZI Mask */ -#define SCU_SFSPC_0_EHD_Pos 8 /*!< SCU SFSPC_0: EHD Position */ -#define SCU_SFSPC_0_EHD_Msk (0x03UL << SCU_SFSPC_0_EHD_Pos) /*!< SCU SFSPC_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_1 ------------------------------------------ -#define SCU_SFSPC_1_MODE_Pos 0 /*!< SCU SFSPC_1: MODE Position */ -#define SCU_SFSPC_1_MODE_Msk (0x07UL << SCU_SFSPC_1_MODE_Pos) /*!< SCU SFSPC_1: MODE Mask */ -#define SCU_SFSPC_1_EPD_Pos 3 /*!< SCU SFSPC_1: EPD Position */ -#define SCU_SFSPC_1_EPD_Msk (0x01UL << SCU_SFSPC_1_EPD_Pos) /*!< SCU SFSPC_1: EPD Mask */ -#define SCU_SFSPC_1_EPUN_Pos 4 /*!< SCU SFSPC_1: EPUN Position */ -#define SCU_SFSPC_1_EPUN_Msk (0x01UL << SCU_SFSPC_1_EPUN_Pos) /*!< SCU SFSPC_1: EPUN Mask */ -#define SCU_SFSPC_1_EHS_Pos 5 /*!< SCU SFSPC_1: EHS Position */ -#define SCU_SFSPC_1_EHS_Msk (0x01UL << SCU_SFSPC_1_EHS_Pos) /*!< SCU SFSPC_1: EHS Mask */ -#define SCU_SFSPC_1_EZI_Pos 6 /*!< SCU SFSPC_1: EZI Position */ -#define SCU_SFSPC_1_EZI_Msk (0x01UL << SCU_SFSPC_1_EZI_Pos) /*!< SCU SFSPC_1: EZI Mask */ -#define SCU_SFSPC_1_EHD_Pos 8 /*!< SCU SFSPC_1: EHD Position */ -#define SCU_SFSPC_1_EHD_Msk (0x03UL << SCU_SFSPC_1_EHD_Pos) /*!< SCU SFSPC_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_2 ------------------------------------------ -#define SCU_SFSPC_2_MODE_Pos 0 /*!< SCU SFSPC_2: MODE Position */ -#define SCU_SFSPC_2_MODE_Msk (0x07UL << SCU_SFSPC_2_MODE_Pos) /*!< SCU SFSPC_2: MODE Mask */ -#define SCU_SFSPC_2_EPD_Pos 3 /*!< SCU SFSPC_2: EPD Position */ -#define SCU_SFSPC_2_EPD_Msk (0x01UL << SCU_SFSPC_2_EPD_Pos) /*!< SCU SFSPC_2: EPD Mask */ -#define SCU_SFSPC_2_EPUN_Pos 4 /*!< SCU SFSPC_2: EPUN Position */ -#define SCU_SFSPC_2_EPUN_Msk (0x01UL << SCU_SFSPC_2_EPUN_Pos) /*!< SCU SFSPC_2: EPUN Mask */ -#define SCU_SFSPC_2_EHS_Pos 5 /*!< SCU SFSPC_2: EHS Position */ -#define SCU_SFSPC_2_EHS_Msk (0x01UL << SCU_SFSPC_2_EHS_Pos) /*!< SCU SFSPC_2: EHS Mask */ -#define SCU_SFSPC_2_EZI_Pos 6 /*!< SCU SFSPC_2: EZI Position */ -#define SCU_SFSPC_2_EZI_Msk (0x01UL << SCU_SFSPC_2_EZI_Pos) /*!< SCU SFSPC_2: EZI Mask */ -#define SCU_SFSPC_2_EHD_Pos 8 /*!< SCU SFSPC_2: EHD Position */ -#define SCU_SFSPC_2_EHD_Msk (0x03UL << SCU_SFSPC_2_EHD_Pos) /*!< SCU SFSPC_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_3 ------------------------------------------ -#define SCU_SFSPC_3_MODE_Pos 0 /*!< SCU SFSPC_3: MODE Position */ -#define SCU_SFSPC_3_MODE_Msk (0x07UL << SCU_SFSPC_3_MODE_Pos) /*!< SCU SFSPC_3: MODE Mask */ -#define SCU_SFSPC_3_EPD_Pos 3 /*!< SCU SFSPC_3: EPD Position */ -#define SCU_SFSPC_3_EPD_Msk (0x01UL << SCU_SFSPC_3_EPD_Pos) /*!< SCU SFSPC_3: EPD Mask */ -#define SCU_SFSPC_3_EPUN_Pos 4 /*!< SCU SFSPC_3: EPUN Position */ -#define SCU_SFSPC_3_EPUN_Msk (0x01UL << SCU_SFSPC_3_EPUN_Pos) /*!< SCU SFSPC_3: EPUN Mask */ -#define SCU_SFSPC_3_EHS_Pos 5 /*!< SCU SFSPC_3: EHS Position */ -#define SCU_SFSPC_3_EHS_Msk (0x01UL << SCU_SFSPC_3_EHS_Pos) /*!< SCU SFSPC_3: EHS Mask */ -#define SCU_SFSPC_3_EZI_Pos 6 /*!< SCU SFSPC_3: EZI Position */ -#define SCU_SFSPC_3_EZI_Msk (0x01UL << SCU_SFSPC_3_EZI_Pos) /*!< SCU SFSPC_3: EZI Mask */ -#define SCU_SFSPC_3_EHD_Pos 8 /*!< SCU SFSPC_3: EHD Position */ -#define SCU_SFSPC_3_EHD_Msk (0x03UL << SCU_SFSPC_3_EHD_Pos) /*!< SCU SFSPC_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_4 ------------------------------------------ -#define SCU_SFSPC_4_MODE_Pos 0 /*!< SCU SFSPC_4: MODE Position */ -#define SCU_SFSPC_4_MODE_Msk (0x07UL << SCU_SFSPC_4_MODE_Pos) /*!< SCU SFSPC_4: MODE Mask */ -#define SCU_SFSPC_4_EPD_Pos 3 /*!< SCU SFSPC_4: EPD Position */ -#define SCU_SFSPC_4_EPD_Msk (0x01UL << SCU_SFSPC_4_EPD_Pos) /*!< SCU SFSPC_4: EPD Mask */ -#define SCU_SFSPC_4_EPUN_Pos 4 /*!< SCU SFSPC_4: EPUN Position */ -#define SCU_SFSPC_4_EPUN_Msk (0x01UL << SCU_SFSPC_4_EPUN_Pos) /*!< SCU SFSPC_4: EPUN Mask */ -#define SCU_SFSPC_4_EHS_Pos 5 /*!< SCU SFSPC_4: EHS Position */ -#define SCU_SFSPC_4_EHS_Msk (0x01UL << SCU_SFSPC_4_EHS_Pos) /*!< SCU SFSPC_4: EHS Mask */ -#define SCU_SFSPC_4_EZI_Pos 6 /*!< SCU SFSPC_4: EZI Position */ -#define SCU_SFSPC_4_EZI_Msk (0x01UL << SCU_SFSPC_4_EZI_Pos) /*!< SCU SFSPC_4: EZI Mask */ -#define SCU_SFSPC_4_EHD_Pos 8 /*!< SCU SFSPC_4: EHD Position */ -#define SCU_SFSPC_4_EHD_Msk (0x03UL << SCU_SFSPC_4_EHD_Pos) /*!< SCU SFSPC_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_5 ------------------------------------------ -#define SCU_SFSPC_5_MODE_Pos 0 /*!< SCU SFSPC_5: MODE Position */ -#define SCU_SFSPC_5_MODE_Msk (0x07UL << SCU_SFSPC_5_MODE_Pos) /*!< SCU SFSPC_5: MODE Mask */ -#define SCU_SFSPC_5_EPD_Pos 3 /*!< SCU SFSPC_5: EPD Position */ -#define SCU_SFSPC_5_EPD_Msk (0x01UL << SCU_SFSPC_5_EPD_Pos) /*!< SCU SFSPC_5: EPD Mask */ -#define SCU_SFSPC_5_EPUN_Pos 4 /*!< SCU SFSPC_5: EPUN Position */ -#define SCU_SFSPC_5_EPUN_Msk (0x01UL << SCU_SFSPC_5_EPUN_Pos) /*!< SCU SFSPC_5: EPUN Mask */ -#define SCU_SFSPC_5_EHS_Pos 5 /*!< SCU SFSPC_5: EHS Position */ -#define SCU_SFSPC_5_EHS_Msk (0x01UL << SCU_SFSPC_5_EHS_Pos) /*!< SCU SFSPC_5: EHS Mask */ -#define SCU_SFSPC_5_EZI_Pos 6 /*!< SCU SFSPC_5: EZI Position */ -#define SCU_SFSPC_5_EZI_Msk (0x01UL << SCU_SFSPC_5_EZI_Pos) /*!< SCU SFSPC_5: EZI Mask */ -#define SCU_SFSPC_5_EHD_Pos 8 /*!< SCU SFSPC_5: EHD Position */ -#define SCU_SFSPC_5_EHD_Msk (0x03UL << SCU_SFSPC_5_EHD_Pos) /*!< SCU SFSPC_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_6 ------------------------------------------ -#define SCU_SFSPC_6_MODE_Pos 0 /*!< SCU SFSPC_6: MODE Position */ -#define SCU_SFSPC_6_MODE_Msk (0x07UL << SCU_SFSPC_6_MODE_Pos) /*!< SCU SFSPC_6: MODE Mask */ -#define SCU_SFSPC_6_EPD_Pos 3 /*!< SCU SFSPC_6: EPD Position */ -#define SCU_SFSPC_6_EPD_Msk (0x01UL << SCU_SFSPC_6_EPD_Pos) /*!< SCU SFSPC_6: EPD Mask */ -#define SCU_SFSPC_6_EPUN_Pos 4 /*!< SCU SFSPC_6: EPUN Position */ -#define SCU_SFSPC_6_EPUN_Msk (0x01UL << SCU_SFSPC_6_EPUN_Pos) /*!< SCU SFSPC_6: EPUN Mask */ -#define SCU_SFSPC_6_EHS_Pos 5 /*!< SCU SFSPC_6: EHS Position */ -#define SCU_SFSPC_6_EHS_Msk (0x01UL << SCU_SFSPC_6_EHS_Pos) /*!< SCU SFSPC_6: EHS Mask */ -#define SCU_SFSPC_6_EZI_Pos 6 /*!< SCU SFSPC_6: EZI Position */ -#define SCU_SFSPC_6_EZI_Msk (0x01UL << SCU_SFSPC_6_EZI_Pos) /*!< SCU SFSPC_6: EZI Mask */ -#define SCU_SFSPC_6_EHD_Pos 8 /*!< SCU SFSPC_6: EHD Position */ -#define SCU_SFSPC_6_EHD_Msk (0x03UL << SCU_SFSPC_6_EHD_Pos) /*!< SCU SFSPC_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_7 ------------------------------------------ -#define SCU_SFSPC_7_MODE_Pos 0 /*!< SCU SFSPC_7: MODE Position */ -#define SCU_SFSPC_7_MODE_Msk (0x07UL << SCU_SFSPC_7_MODE_Pos) /*!< SCU SFSPC_7: MODE Mask */ -#define SCU_SFSPC_7_EPD_Pos 3 /*!< SCU SFSPC_7: EPD Position */ -#define SCU_SFSPC_7_EPD_Msk (0x01UL << SCU_SFSPC_7_EPD_Pos) /*!< SCU SFSPC_7: EPD Mask */ -#define SCU_SFSPC_7_EPUN_Pos 4 /*!< SCU SFSPC_7: EPUN Position */ -#define SCU_SFSPC_7_EPUN_Msk (0x01UL << SCU_SFSPC_7_EPUN_Pos) /*!< SCU SFSPC_7: EPUN Mask */ -#define SCU_SFSPC_7_EHS_Pos 5 /*!< SCU SFSPC_7: EHS Position */ -#define SCU_SFSPC_7_EHS_Msk (0x01UL << SCU_SFSPC_7_EHS_Pos) /*!< SCU SFSPC_7: EHS Mask */ -#define SCU_SFSPC_7_EZI_Pos 6 /*!< SCU SFSPC_7: EZI Position */ -#define SCU_SFSPC_7_EZI_Msk (0x01UL << SCU_SFSPC_7_EZI_Pos) /*!< SCU SFSPC_7: EZI Mask */ -#define SCU_SFSPC_7_EHD_Pos 8 /*!< SCU SFSPC_7: EHD Position */ -#define SCU_SFSPC_7_EHD_Msk (0x03UL << SCU_SFSPC_7_EHD_Pos) /*!< SCU SFSPC_7: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_8 ------------------------------------------ -#define SCU_SFSPC_8_MODE_Pos 0 /*!< SCU SFSPC_8: MODE Position */ -#define SCU_SFSPC_8_MODE_Msk (0x07UL << SCU_SFSPC_8_MODE_Pos) /*!< SCU SFSPC_8: MODE Mask */ -#define SCU_SFSPC_8_EPD_Pos 3 /*!< SCU SFSPC_8: EPD Position */ -#define SCU_SFSPC_8_EPD_Msk (0x01UL << SCU_SFSPC_8_EPD_Pos) /*!< SCU SFSPC_8: EPD Mask */ -#define SCU_SFSPC_8_EPUN_Pos 4 /*!< SCU SFSPC_8: EPUN Position */ -#define SCU_SFSPC_8_EPUN_Msk (0x01UL << SCU_SFSPC_8_EPUN_Pos) /*!< SCU SFSPC_8: EPUN Mask */ -#define SCU_SFSPC_8_EHS_Pos 5 /*!< SCU SFSPC_8: EHS Position */ -#define SCU_SFSPC_8_EHS_Msk (0x01UL << SCU_SFSPC_8_EHS_Pos) /*!< SCU SFSPC_8: EHS Mask */ -#define SCU_SFSPC_8_EZI_Pos 6 /*!< SCU SFSPC_8: EZI Position */ -#define SCU_SFSPC_8_EZI_Msk (0x01UL << SCU_SFSPC_8_EZI_Pos) /*!< SCU SFSPC_8: EZI Mask */ -#define SCU_SFSPC_8_EHD_Pos 8 /*!< SCU SFSPC_8: EHD Position */ -#define SCU_SFSPC_8_EHD_Msk (0x03UL << SCU_SFSPC_8_EHD_Pos) /*!< SCU SFSPC_8: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_9 ------------------------------------------ -#define SCU_SFSPC_9_MODE_Pos 0 /*!< SCU SFSPC_9: MODE Position */ -#define SCU_SFSPC_9_MODE_Msk (0x07UL << SCU_SFSPC_9_MODE_Pos) /*!< SCU SFSPC_9: MODE Mask */ -#define SCU_SFSPC_9_EPD_Pos 3 /*!< SCU SFSPC_9: EPD Position */ -#define SCU_SFSPC_9_EPD_Msk (0x01UL << SCU_SFSPC_9_EPD_Pos) /*!< SCU SFSPC_9: EPD Mask */ -#define SCU_SFSPC_9_EPUN_Pos 4 /*!< SCU SFSPC_9: EPUN Position */ -#define SCU_SFSPC_9_EPUN_Msk (0x01UL << SCU_SFSPC_9_EPUN_Pos) /*!< SCU SFSPC_9: EPUN Mask */ -#define SCU_SFSPC_9_EHS_Pos 5 /*!< SCU SFSPC_9: EHS Position */ -#define SCU_SFSPC_9_EHS_Msk (0x01UL << SCU_SFSPC_9_EHS_Pos) /*!< SCU SFSPC_9: EHS Mask */ -#define SCU_SFSPC_9_EZI_Pos 6 /*!< SCU SFSPC_9: EZI Position */ -#define SCU_SFSPC_9_EZI_Msk (0x01UL << SCU_SFSPC_9_EZI_Pos) /*!< SCU SFSPC_9: EZI Mask */ -#define SCU_SFSPC_9_EHD_Pos 8 /*!< SCU SFSPC_9: EHD Position */ -#define SCU_SFSPC_9_EHD_Msk (0x03UL << SCU_SFSPC_9_EHD_Pos) /*!< SCU SFSPC_9: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_10 ------------------------------------------ -#define SCU_SFSPC_10_MODE_Pos 0 /*!< SCU SFSPC_10: MODE Position */ -#define SCU_SFSPC_10_MODE_Msk (0x07UL << SCU_SFSPC_10_MODE_Pos) /*!< SCU SFSPC_10: MODE Mask */ -#define SCU_SFSPC_10_EPD_Pos 3 /*!< SCU SFSPC_10: EPD Position */ -#define SCU_SFSPC_10_EPD_Msk (0x01UL << SCU_SFSPC_10_EPD_Pos) /*!< SCU SFSPC_10: EPD Mask */ -#define SCU_SFSPC_10_EPUN_Pos 4 /*!< SCU SFSPC_10: EPUN Position */ -#define SCU_SFSPC_10_EPUN_Msk (0x01UL << SCU_SFSPC_10_EPUN_Pos) /*!< SCU SFSPC_10: EPUN Mask */ -#define SCU_SFSPC_10_EHS_Pos 5 /*!< SCU SFSPC_10: EHS Position */ -#define SCU_SFSPC_10_EHS_Msk (0x01UL << SCU_SFSPC_10_EHS_Pos) /*!< SCU SFSPC_10: EHS Mask */ -#define SCU_SFSPC_10_EZI_Pos 6 /*!< SCU SFSPC_10: EZI Position */ -#define SCU_SFSPC_10_EZI_Msk (0x01UL << SCU_SFSPC_10_EZI_Pos) /*!< SCU SFSPC_10: EZI Mask */ -#define SCU_SFSPC_10_EHD_Pos 8 /*!< SCU SFSPC_10: EHD Position */ -#define SCU_SFSPC_10_EHD_Msk (0x03UL << SCU_SFSPC_10_EHD_Pos) /*!< SCU SFSPC_10: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_11 ------------------------------------------ -#define SCU_SFSPC_11_MODE_Pos 0 /*!< SCU SFSPC_11: MODE Position */ -#define SCU_SFSPC_11_MODE_Msk (0x07UL << SCU_SFSPC_11_MODE_Pos) /*!< SCU SFSPC_11: MODE Mask */ -#define SCU_SFSPC_11_EPD_Pos 3 /*!< SCU SFSPC_11: EPD Position */ -#define SCU_SFSPC_11_EPD_Msk (0x01UL << SCU_SFSPC_11_EPD_Pos) /*!< SCU SFSPC_11: EPD Mask */ -#define SCU_SFSPC_11_EPUN_Pos 4 /*!< SCU SFSPC_11: EPUN Position */ -#define SCU_SFSPC_11_EPUN_Msk (0x01UL << SCU_SFSPC_11_EPUN_Pos) /*!< SCU SFSPC_11: EPUN Mask */ -#define SCU_SFSPC_11_EHS_Pos 5 /*!< SCU SFSPC_11: EHS Position */ -#define SCU_SFSPC_11_EHS_Msk (0x01UL << SCU_SFSPC_11_EHS_Pos) /*!< SCU SFSPC_11: EHS Mask */ -#define SCU_SFSPC_11_EZI_Pos 6 /*!< SCU SFSPC_11: EZI Position */ -#define SCU_SFSPC_11_EZI_Msk (0x01UL << SCU_SFSPC_11_EZI_Pos) /*!< SCU SFSPC_11: EZI Mask */ -#define SCU_SFSPC_11_EHD_Pos 8 /*!< SCU SFSPC_11: EHD Position */ -#define SCU_SFSPC_11_EHD_Msk (0x03UL << SCU_SFSPC_11_EHD_Pos) /*!< SCU SFSPC_11: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_12 ------------------------------------------ -#define SCU_SFSPC_12_MODE_Pos 0 /*!< SCU SFSPC_12: MODE Position */ -#define SCU_SFSPC_12_MODE_Msk (0x07UL << SCU_SFSPC_12_MODE_Pos) /*!< SCU SFSPC_12: MODE Mask */ -#define SCU_SFSPC_12_EPD_Pos 3 /*!< SCU SFSPC_12: EPD Position */ -#define SCU_SFSPC_12_EPD_Msk (0x01UL << SCU_SFSPC_12_EPD_Pos) /*!< SCU SFSPC_12: EPD Mask */ -#define SCU_SFSPC_12_EPUN_Pos 4 /*!< SCU SFSPC_12: EPUN Position */ -#define SCU_SFSPC_12_EPUN_Msk (0x01UL << SCU_SFSPC_12_EPUN_Pos) /*!< SCU SFSPC_12: EPUN Mask */ -#define SCU_SFSPC_12_EHS_Pos 5 /*!< SCU SFSPC_12: EHS Position */ -#define SCU_SFSPC_12_EHS_Msk (0x01UL << SCU_SFSPC_12_EHS_Pos) /*!< SCU SFSPC_12: EHS Mask */ -#define SCU_SFSPC_12_EZI_Pos 6 /*!< SCU SFSPC_12: EZI Position */ -#define SCU_SFSPC_12_EZI_Msk (0x01UL << SCU_SFSPC_12_EZI_Pos) /*!< SCU SFSPC_12: EZI Mask */ -#define SCU_SFSPC_12_EHD_Pos 8 /*!< SCU SFSPC_12: EHD Position */ -#define SCU_SFSPC_12_EHD_Msk (0x03UL << SCU_SFSPC_12_EHD_Pos) /*!< SCU SFSPC_12: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_13 ------------------------------------------ -#define SCU_SFSPC_13_MODE_Pos 0 /*!< SCU SFSPC_13: MODE Position */ -#define SCU_SFSPC_13_MODE_Msk (0x07UL << SCU_SFSPC_13_MODE_Pos) /*!< SCU SFSPC_13: MODE Mask */ -#define SCU_SFSPC_13_EPD_Pos 3 /*!< SCU SFSPC_13: EPD Position */ -#define SCU_SFSPC_13_EPD_Msk (0x01UL << SCU_SFSPC_13_EPD_Pos) /*!< SCU SFSPC_13: EPD Mask */ -#define SCU_SFSPC_13_EPUN_Pos 4 /*!< SCU SFSPC_13: EPUN Position */ -#define SCU_SFSPC_13_EPUN_Msk (0x01UL << SCU_SFSPC_13_EPUN_Pos) /*!< SCU SFSPC_13: EPUN Mask */ -#define SCU_SFSPC_13_EHS_Pos 5 /*!< SCU SFSPC_13: EHS Position */ -#define SCU_SFSPC_13_EHS_Msk (0x01UL << SCU_SFSPC_13_EHS_Pos) /*!< SCU SFSPC_13: EHS Mask */ -#define SCU_SFSPC_13_EZI_Pos 6 /*!< SCU SFSPC_13: EZI Position */ -#define SCU_SFSPC_13_EZI_Msk (0x01UL << SCU_SFSPC_13_EZI_Pos) /*!< SCU SFSPC_13: EZI Mask */ -#define SCU_SFSPC_13_EHD_Pos 8 /*!< SCU SFSPC_13: EHD Position */ -#define SCU_SFSPC_13_EHD_Msk (0x03UL << SCU_SFSPC_13_EHD_Pos) /*!< SCU SFSPC_13: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_14 ------------------------------------------ -#define SCU_SFSPC_14_MODE_Pos 0 /*!< SCU SFSPC_14: MODE Position */ -#define SCU_SFSPC_14_MODE_Msk (0x07UL << SCU_SFSPC_14_MODE_Pos) /*!< SCU SFSPC_14: MODE Mask */ -#define SCU_SFSPC_14_EPD_Pos 3 /*!< SCU SFSPC_14: EPD Position */ -#define SCU_SFSPC_14_EPD_Msk (0x01UL << SCU_SFSPC_14_EPD_Pos) /*!< SCU SFSPC_14: EPD Mask */ -#define SCU_SFSPC_14_EPUN_Pos 4 /*!< SCU SFSPC_14: EPUN Position */ -#define SCU_SFSPC_14_EPUN_Msk (0x01UL << SCU_SFSPC_14_EPUN_Pos) /*!< SCU SFSPC_14: EPUN Mask */ -#define SCU_SFSPC_14_EHS_Pos 5 /*!< SCU SFSPC_14: EHS Position */ -#define SCU_SFSPC_14_EHS_Msk (0x01UL << SCU_SFSPC_14_EHS_Pos) /*!< SCU SFSPC_14: EHS Mask */ -#define SCU_SFSPC_14_EZI_Pos 6 /*!< SCU SFSPC_14: EZI Position */ -#define SCU_SFSPC_14_EZI_Msk (0x01UL << SCU_SFSPC_14_EZI_Pos) /*!< SCU SFSPC_14: EZI Mask */ -#define SCU_SFSPC_14_EHD_Pos 8 /*!< SCU SFSPC_14: EHD Position */ -#define SCU_SFSPC_14_EHD_Msk (0x03UL << SCU_SFSPC_14_EHD_Pos) /*!< SCU SFSPC_14: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_0 ------------------------------------------ -#define SCU_SFSPD_0_MODE_Pos 0 /*!< SCU SFSPD_0: MODE Position */ -#define SCU_SFSPD_0_MODE_Msk (0x07UL << SCU_SFSPD_0_MODE_Pos) /*!< SCU SFSPD_0: MODE Mask */ -#define SCU_SFSPD_0_EPD_Pos 3 /*!< SCU SFSPD_0: EPD Position */ -#define SCU_SFSPD_0_EPD_Msk (0x01UL << SCU_SFSPD_0_EPD_Pos) /*!< SCU SFSPD_0: EPD Mask */ -#define SCU_SFSPD_0_EPUN_Pos 4 /*!< SCU SFSPD_0: EPUN Position */ -#define SCU_SFSPD_0_EPUN_Msk (0x01UL << SCU_SFSPD_0_EPUN_Pos) /*!< SCU SFSPD_0: EPUN Mask */ -#define SCU_SFSPD_0_EHS_Pos 5 /*!< SCU SFSPD_0: EHS Position */ -#define SCU_SFSPD_0_EHS_Msk (0x01UL << SCU_SFSPD_0_EHS_Pos) /*!< SCU SFSPD_0: EHS Mask */ -#define SCU_SFSPD_0_EZI_Pos 6 /*!< SCU SFSPD_0: EZI Position */ -#define SCU_SFSPD_0_EZI_Msk (0x01UL << SCU_SFSPD_0_EZI_Pos) /*!< SCU SFSPD_0: EZI Mask */ -#define SCU_SFSPD_0_EHD_Pos 8 /*!< SCU SFSPD_0: EHD Position */ -#define SCU_SFSPD_0_EHD_Msk (0x03UL << SCU_SFSPD_0_EHD_Pos) /*!< SCU SFSPD_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_1 ------------------------------------------ -#define SCU_SFSPD_1_MODE_Pos 0 /*!< SCU SFSPD_1: MODE Position */ -#define SCU_SFSPD_1_MODE_Msk (0x07UL << SCU_SFSPD_1_MODE_Pos) /*!< SCU SFSPD_1: MODE Mask */ -#define SCU_SFSPD_1_EPD_Pos 3 /*!< SCU SFSPD_1: EPD Position */ -#define SCU_SFSPD_1_EPD_Msk (0x01UL << SCU_SFSPD_1_EPD_Pos) /*!< SCU SFSPD_1: EPD Mask */ -#define SCU_SFSPD_1_EPUN_Pos 4 /*!< SCU SFSPD_1: EPUN Position */ -#define SCU_SFSPD_1_EPUN_Msk (0x01UL << SCU_SFSPD_1_EPUN_Pos) /*!< SCU SFSPD_1: EPUN Mask */ -#define SCU_SFSPD_1_EHS_Pos 5 /*!< SCU SFSPD_1: EHS Position */ -#define SCU_SFSPD_1_EHS_Msk (0x01UL << SCU_SFSPD_1_EHS_Pos) /*!< SCU SFSPD_1: EHS Mask */ -#define SCU_SFSPD_1_EZI_Pos 6 /*!< SCU SFSPD_1: EZI Position */ -#define SCU_SFSPD_1_EZI_Msk (0x01UL << SCU_SFSPD_1_EZI_Pos) /*!< SCU SFSPD_1: EZI Mask */ -#define SCU_SFSPD_1_EHD_Pos 8 /*!< SCU SFSPD_1: EHD Position */ -#define SCU_SFSPD_1_EHD_Msk (0x03UL << SCU_SFSPD_1_EHD_Pos) /*!< SCU SFSPD_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_2 ------------------------------------------ -#define SCU_SFSPD_2_MODE_Pos 0 /*!< SCU SFSPD_2: MODE Position */ -#define SCU_SFSPD_2_MODE_Msk (0x07UL << SCU_SFSPD_2_MODE_Pos) /*!< SCU SFSPD_2: MODE Mask */ -#define SCU_SFSPD_2_EPD_Pos 3 /*!< SCU SFSPD_2: EPD Position */ -#define SCU_SFSPD_2_EPD_Msk (0x01UL << SCU_SFSPD_2_EPD_Pos) /*!< SCU SFSPD_2: EPD Mask */ -#define SCU_SFSPD_2_EPUN_Pos 4 /*!< SCU SFSPD_2: EPUN Position */ -#define SCU_SFSPD_2_EPUN_Msk (0x01UL << SCU_SFSPD_2_EPUN_Pos) /*!< SCU SFSPD_2: EPUN Mask */ -#define SCU_SFSPD_2_EHS_Pos 5 /*!< SCU SFSPD_2: EHS Position */ -#define SCU_SFSPD_2_EHS_Msk (0x01UL << SCU_SFSPD_2_EHS_Pos) /*!< SCU SFSPD_2: EHS Mask */ -#define SCU_SFSPD_2_EZI_Pos 6 /*!< SCU SFSPD_2: EZI Position */ -#define SCU_SFSPD_2_EZI_Msk (0x01UL << SCU_SFSPD_2_EZI_Pos) /*!< SCU SFSPD_2: EZI Mask */ -#define SCU_SFSPD_2_EHD_Pos 8 /*!< SCU SFSPD_2: EHD Position */ -#define SCU_SFSPD_2_EHD_Msk (0x03UL << SCU_SFSPD_2_EHD_Pos) /*!< SCU SFSPD_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_3 ------------------------------------------ -#define SCU_SFSPD_3_MODE_Pos 0 /*!< SCU SFSPD_3: MODE Position */ -#define SCU_SFSPD_3_MODE_Msk (0x07UL << SCU_SFSPD_3_MODE_Pos) /*!< SCU SFSPD_3: MODE Mask */ -#define SCU_SFSPD_3_EPD_Pos 3 /*!< SCU SFSPD_3: EPD Position */ -#define SCU_SFSPD_3_EPD_Msk (0x01UL << SCU_SFSPD_3_EPD_Pos) /*!< SCU SFSPD_3: EPD Mask */ -#define SCU_SFSPD_3_EPUN_Pos 4 /*!< SCU SFSPD_3: EPUN Position */ -#define SCU_SFSPD_3_EPUN_Msk (0x01UL << SCU_SFSPD_3_EPUN_Pos) /*!< SCU SFSPD_3: EPUN Mask */ -#define SCU_SFSPD_3_EHS_Pos 5 /*!< SCU SFSPD_3: EHS Position */ -#define SCU_SFSPD_3_EHS_Msk (0x01UL << SCU_SFSPD_3_EHS_Pos) /*!< SCU SFSPD_3: EHS Mask */ -#define SCU_SFSPD_3_EZI_Pos 6 /*!< SCU SFSPD_3: EZI Position */ -#define SCU_SFSPD_3_EZI_Msk (0x01UL << SCU_SFSPD_3_EZI_Pos) /*!< SCU SFSPD_3: EZI Mask */ -#define SCU_SFSPD_3_EHD_Pos 8 /*!< SCU SFSPD_3: EHD Position */ -#define SCU_SFSPD_3_EHD_Msk (0x03UL << SCU_SFSPD_3_EHD_Pos) /*!< SCU SFSPD_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_4 ------------------------------------------ -#define SCU_SFSPD_4_MODE_Pos 0 /*!< SCU SFSPD_4: MODE Position */ -#define SCU_SFSPD_4_MODE_Msk (0x07UL << SCU_SFSPD_4_MODE_Pos) /*!< SCU SFSPD_4: MODE Mask */ -#define SCU_SFSPD_4_EPD_Pos 3 /*!< SCU SFSPD_4: EPD Position */ -#define SCU_SFSPD_4_EPD_Msk (0x01UL << SCU_SFSPD_4_EPD_Pos) /*!< SCU SFSPD_4: EPD Mask */ -#define SCU_SFSPD_4_EPUN_Pos 4 /*!< SCU SFSPD_4: EPUN Position */ -#define SCU_SFSPD_4_EPUN_Msk (0x01UL << SCU_SFSPD_4_EPUN_Pos) /*!< SCU SFSPD_4: EPUN Mask */ -#define SCU_SFSPD_4_EHS_Pos 5 /*!< SCU SFSPD_4: EHS Position */ -#define SCU_SFSPD_4_EHS_Msk (0x01UL << SCU_SFSPD_4_EHS_Pos) /*!< SCU SFSPD_4: EHS Mask */ -#define SCU_SFSPD_4_EZI_Pos 6 /*!< SCU SFSPD_4: EZI Position */ -#define SCU_SFSPD_4_EZI_Msk (0x01UL << SCU_SFSPD_4_EZI_Pos) /*!< SCU SFSPD_4: EZI Mask */ -#define SCU_SFSPD_4_EHD_Pos 8 /*!< SCU SFSPD_4: EHD Position */ -#define SCU_SFSPD_4_EHD_Msk (0x03UL << SCU_SFSPD_4_EHD_Pos) /*!< SCU SFSPD_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_5 ------------------------------------------ -#define SCU_SFSPD_5_MODE_Pos 0 /*!< SCU SFSPD_5: MODE Position */ -#define SCU_SFSPD_5_MODE_Msk (0x07UL << SCU_SFSPD_5_MODE_Pos) /*!< SCU SFSPD_5: MODE Mask */ -#define SCU_SFSPD_5_EPD_Pos 3 /*!< SCU SFSPD_5: EPD Position */ -#define SCU_SFSPD_5_EPD_Msk (0x01UL << SCU_SFSPD_5_EPD_Pos) /*!< SCU SFSPD_5: EPD Mask */ -#define SCU_SFSPD_5_EPUN_Pos 4 /*!< SCU SFSPD_5: EPUN Position */ -#define SCU_SFSPD_5_EPUN_Msk (0x01UL << SCU_SFSPD_5_EPUN_Pos) /*!< SCU SFSPD_5: EPUN Mask */ -#define SCU_SFSPD_5_EHS_Pos 5 /*!< SCU SFSPD_5: EHS Position */ -#define SCU_SFSPD_5_EHS_Msk (0x01UL << SCU_SFSPD_5_EHS_Pos) /*!< SCU SFSPD_5: EHS Mask */ -#define SCU_SFSPD_5_EZI_Pos 6 /*!< SCU SFSPD_5: EZI Position */ -#define SCU_SFSPD_5_EZI_Msk (0x01UL << SCU_SFSPD_5_EZI_Pos) /*!< SCU SFSPD_5: EZI Mask */ -#define SCU_SFSPD_5_EHD_Pos 8 /*!< SCU SFSPD_5: EHD Position */ -#define SCU_SFSPD_5_EHD_Msk (0x03UL << SCU_SFSPD_5_EHD_Pos) /*!< SCU SFSPD_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_6 ------------------------------------------ -#define SCU_SFSPD_6_MODE_Pos 0 /*!< SCU SFSPD_6: MODE Position */ -#define SCU_SFSPD_6_MODE_Msk (0x07UL << SCU_SFSPD_6_MODE_Pos) /*!< SCU SFSPD_6: MODE Mask */ -#define SCU_SFSPD_6_EPD_Pos 3 /*!< SCU SFSPD_6: EPD Position */ -#define SCU_SFSPD_6_EPD_Msk (0x01UL << SCU_SFSPD_6_EPD_Pos) /*!< SCU SFSPD_6: EPD Mask */ -#define SCU_SFSPD_6_EPUN_Pos 4 /*!< SCU SFSPD_6: EPUN Position */ -#define SCU_SFSPD_6_EPUN_Msk (0x01UL << SCU_SFSPD_6_EPUN_Pos) /*!< SCU SFSPD_6: EPUN Mask */ -#define SCU_SFSPD_6_EHS_Pos 5 /*!< SCU SFSPD_6: EHS Position */ -#define SCU_SFSPD_6_EHS_Msk (0x01UL << SCU_SFSPD_6_EHS_Pos) /*!< SCU SFSPD_6: EHS Mask */ -#define SCU_SFSPD_6_EZI_Pos 6 /*!< SCU SFSPD_6: EZI Position */ -#define SCU_SFSPD_6_EZI_Msk (0x01UL << SCU_SFSPD_6_EZI_Pos) /*!< SCU SFSPD_6: EZI Mask */ -#define SCU_SFSPD_6_EHD_Pos 8 /*!< SCU SFSPD_6: EHD Position */ -#define SCU_SFSPD_6_EHD_Msk (0x03UL << SCU_SFSPD_6_EHD_Pos) /*!< SCU SFSPD_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_7 ------------------------------------------ -#define SCU_SFSPD_7_MODE_Pos 0 /*!< SCU SFSPD_7: MODE Position */ -#define SCU_SFSPD_7_MODE_Msk (0x07UL << SCU_SFSPD_7_MODE_Pos) /*!< SCU SFSPD_7: MODE Mask */ -#define SCU_SFSPD_7_EPD_Pos 3 /*!< SCU SFSPD_7: EPD Position */ -#define SCU_SFSPD_7_EPD_Msk (0x01UL << SCU_SFSPD_7_EPD_Pos) /*!< SCU SFSPD_7: EPD Mask */ -#define SCU_SFSPD_7_EPUN_Pos 4 /*!< SCU SFSPD_7: EPUN Position */ -#define SCU_SFSPD_7_EPUN_Msk (0x01UL << SCU_SFSPD_7_EPUN_Pos) /*!< SCU SFSPD_7: EPUN Mask */ -#define SCU_SFSPD_7_EHS_Pos 5 /*!< SCU SFSPD_7: EHS Position */ -#define SCU_SFSPD_7_EHS_Msk (0x01UL << SCU_SFSPD_7_EHS_Pos) /*!< SCU SFSPD_7: EHS Mask */ -#define SCU_SFSPD_7_EZI_Pos 6 /*!< SCU SFSPD_7: EZI Position */ -#define SCU_SFSPD_7_EZI_Msk (0x01UL << SCU_SFSPD_7_EZI_Pos) /*!< SCU SFSPD_7: EZI Mask */ -#define SCU_SFSPD_7_EHD_Pos 8 /*!< SCU SFSPD_7: EHD Position */ -#define SCU_SFSPD_7_EHD_Msk (0x03UL << SCU_SFSPD_7_EHD_Pos) /*!< SCU SFSPD_7: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_8 ------------------------------------------ -#define SCU_SFSPD_8_MODE_Pos 0 /*!< SCU SFSPD_8: MODE Position */ -#define SCU_SFSPD_8_MODE_Msk (0x07UL << SCU_SFSPD_8_MODE_Pos) /*!< SCU SFSPD_8: MODE Mask */ -#define SCU_SFSPD_8_EPD_Pos 3 /*!< SCU SFSPD_8: EPD Position */ -#define SCU_SFSPD_8_EPD_Msk (0x01UL << SCU_SFSPD_8_EPD_Pos) /*!< SCU SFSPD_8: EPD Mask */ -#define SCU_SFSPD_8_EPUN_Pos 4 /*!< SCU SFSPD_8: EPUN Position */ -#define SCU_SFSPD_8_EPUN_Msk (0x01UL << SCU_SFSPD_8_EPUN_Pos) /*!< SCU SFSPD_8: EPUN Mask */ -#define SCU_SFSPD_8_EHS_Pos 5 /*!< SCU SFSPD_8: EHS Position */ -#define SCU_SFSPD_8_EHS_Msk (0x01UL << SCU_SFSPD_8_EHS_Pos) /*!< SCU SFSPD_8: EHS Mask */ -#define SCU_SFSPD_8_EZI_Pos 6 /*!< SCU SFSPD_8: EZI Position */ -#define SCU_SFSPD_8_EZI_Msk (0x01UL << SCU_SFSPD_8_EZI_Pos) /*!< SCU SFSPD_8: EZI Mask */ -#define SCU_SFSPD_8_EHD_Pos 8 /*!< SCU SFSPD_8: EHD Position */ -#define SCU_SFSPD_8_EHD_Msk (0x03UL << SCU_SFSPD_8_EHD_Pos) /*!< SCU SFSPD_8: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_9 ------------------------------------------ -#define SCU_SFSPD_9_MODE_Pos 0 /*!< SCU SFSPD_9: MODE Position */ -#define SCU_SFSPD_9_MODE_Msk (0x07UL << SCU_SFSPD_9_MODE_Pos) /*!< SCU SFSPD_9: MODE Mask */ -#define SCU_SFSPD_9_EPD_Pos 3 /*!< SCU SFSPD_9: EPD Position */ -#define SCU_SFSPD_9_EPD_Msk (0x01UL << SCU_SFSPD_9_EPD_Pos) /*!< SCU SFSPD_9: EPD Mask */ -#define SCU_SFSPD_9_EPUN_Pos 4 /*!< SCU SFSPD_9: EPUN Position */ -#define SCU_SFSPD_9_EPUN_Msk (0x01UL << SCU_SFSPD_9_EPUN_Pos) /*!< SCU SFSPD_9: EPUN Mask */ -#define SCU_SFSPD_9_EHS_Pos 5 /*!< SCU SFSPD_9: EHS Position */ -#define SCU_SFSPD_9_EHS_Msk (0x01UL << SCU_SFSPD_9_EHS_Pos) /*!< SCU SFSPD_9: EHS Mask */ -#define SCU_SFSPD_9_EZI_Pos 6 /*!< SCU SFSPD_9: EZI Position */ -#define SCU_SFSPD_9_EZI_Msk (0x01UL << SCU_SFSPD_9_EZI_Pos) /*!< SCU SFSPD_9: EZI Mask */ -#define SCU_SFSPD_9_EHD_Pos 8 /*!< SCU SFSPD_9: EHD Position */ -#define SCU_SFSPD_9_EHD_Msk (0x03UL << SCU_SFSPD_9_EHD_Pos) /*!< SCU SFSPD_9: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_10 ------------------------------------------ -#define SCU_SFSPD_10_MODE_Pos 0 /*!< SCU SFSPD_10: MODE Position */ -#define SCU_SFSPD_10_MODE_Msk (0x07UL << SCU_SFSPD_10_MODE_Pos) /*!< SCU SFSPD_10: MODE Mask */ -#define SCU_SFSPD_10_EPD_Pos 3 /*!< SCU SFSPD_10: EPD Position */ -#define SCU_SFSPD_10_EPD_Msk (0x01UL << SCU_SFSPD_10_EPD_Pos) /*!< SCU SFSPD_10: EPD Mask */ -#define SCU_SFSPD_10_EPUN_Pos 4 /*!< SCU SFSPD_10: EPUN Position */ -#define SCU_SFSPD_10_EPUN_Msk (0x01UL << SCU_SFSPD_10_EPUN_Pos) /*!< SCU SFSPD_10: EPUN Mask */ -#define SCU_SFSPD_10_EHS_Pos 5 /*!< SCU SFSPD_10: EHS Position */ -#define SCU_SFSPD_10_EHS_Msk (0x01UL << SCU_SFSPD_10_EHS_Pos) /*!< SCU SFSPD_10: EHS Mask */ -#define SCU_SFSPD_10_EZI_Pos 6 /*!< SCU SFSPD_10: EZI Position */ -#define SCU_SFSPD_10_EZI_Msk (0x01UL << SCU_SFSPD_10_EZI_Pos) /*!< SCU SFSPD_10: EZI Mask */ -#define SCU_SFSPD_10_EHD_Pos 8 /*!< SCU SFSPD_10: EHD Position */ -#define SCU_SFSPD_10_EHD_Msk (0x03UL << SCU_SFSPD_10_EHD_Pos) /*!< SCU SFSPD_10: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_11 ------------------------------------------ -#define SCU_SFSPD_11_MODE_Pos 0 /*!< SCU SFSPD_11: MODE Position */ -#define SCU_SFSPD_11_MODE_Msk (0x07UL << SCU_SFSPD_11_MODE_Pos) /*!< SCU SFSPD_11: MODE Mask */ -#define SCU_SFSPD_11_EPD_Pos 3 /*!< SCU SFSPD_11: EPD Position */ -#define SCU_SFSPD_11_EPD_Msk (0x01UL << SCU_SFSPD_11_EPD_Pos) /*!< SCU SFSPD_11: EPD Mask */ -#define SCU_SFSPD_11_EPUN_Pos 4 /*!< SCU SFSPD_11: EPUN Position */ -#define SCU_SFSPD_11_EPUN_Msk (0x01UL << SCU_SFSPD_11_EPUN_Pos) /*!< SCU SFSPD_11: EPUN Mask */ -#define SCU_SFSPD_11_EHS_Pos 5 /*!< SCU SFSPD_11: EHS Position */ -#define SCU_SFSPD_11_EHS_Msk (0x01UL << SCU_SFSPD_11_EHS_Pos) /*!< SCU SFSPD_11: EHS Mask */ -#define SCU_SFSPD_11_EZI_Pos 6 /*!< SCU SFSPD_11: EZI Position */ -#define SCU_SFSPD_11_EZI_Msk (0x01UL << SCU_SFSPD_11_EZI_Pos) /*!< SCU SFSPD_11: EZI Mask */ -#define SCU_SFSPD_11_EHD_Pos 8 /*!< SCU SFSPD_11: EHD Position */ -#define SCU_SFSPD_11_EHD_Msk (0x03UL << SCU_SFSPD_11_EHD_Pos) /*!< SCU SFSPD_11: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_12 ------------------------------------------ -#define SCU_SFSPD_12_MODE_Pos 0 /*!< SCU SFSPD_12: MODE Position */ -#define SCU_SFSPD_12_MODE_Msk (0x07UL << SCU_SFSPD_12_MODE_Pos) /*!< SCU SFSPD_12: MODE Mask */ -#define SCU_SFSPD_12_EPD_Pos 3 /*!< SCU SFSPD_12: EPD Position */ -#define SCU_SFSPD_12_EPD_Msk (0x01UL << SCU_SFSPD_12_EPD_Pos) /*!< SCU SFSPD_12: EPD Mask */ -#define SCU_SFSPD_12_EPUN_Pos 4 /*!< SCU SFSPD_12: EPUN Position */ -#define SCU_SFSPD_12_EPUN_Msk (0x01UL << SCU_SFSPD_12_EPUN_Pos) /*!< SCU SFSPD_12: EPUN Mask */ -#define SCU_SFSPD_12_EHS_Pos 5 /*!< SCU SFSPD_12: EHS Position */ -#define SCU_SFSPD_12_EHS_Msk (0x01UL << SCU_SFSPD_12_EHS_Pos) /*!< SCU SFSPD_12: EHS Mask */ -#define SCU_SFSPD_12_EZI_Pos 6 /*!< SCU SFSPD_12: EZI Position */ -#define SCU_SFSPD_12_EZI_Msk (0x01UL << SCU_SFSPD_12_EZI_Pos) /*!< SCU SFSPD_12: EZI Mask */ -#define SCU_SFSPD_12_EHD_Pos 8 /*!< SCU SFSPD_12: EHD Position */ -#define SCU_SFSPD_12_EHD_Msk (0x03UL << SCU_SFSPD_12_EHD_Pos) /*!< SCU SFSPD_12: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_13 ------------------------------------------ -#define SCU_SFSPD_13_MODE_Pos 0 /*!< SCU SFSPD_13: MODE Position */ -#define SCU_SFSPD_13_MODE_Msk (0x07UL << SCU_SFSPD_13_MODE_Pos) /*!< SCU SFSPD_13: MODE Mask */ -#define SCU_SFSPD_13_EPD_Pos 3 /*!< SCU SFSPD_13: EPD Position */ -#define SCU_SFSPD_13_EPD_Msk (0x01UL << SCU_SFSPD_13_EPD_Pos) /*!< SCU SFSPD_13: EPD Mask */ -#define SCU_SFSPD_13_EPUN_Pos 4 /*!< SCU SFSPD_13: EPUN Position */ -#define SCU_SFSPD_13_EPUN_Msk (0x01UL << SCU_SFSPD_13_EPUN_Pos) /*!< SCU SFSPD_13: EPUN Mask */ -#define SCU_SFSPD_13_EHS_Pos 5 /*!< SCU SFSPD_13: EHS Position */ -#define SCU_SFSPD_13_EHS_Msk (0x01UL << SCU_SFSPD_13_EHS_Pos) /*!< SCU SFSPD_13: EHS Mask */ -#define SCU_SFSPD_13_EZI_Pos 6 /*!< SCU SFSPD_13: EZI Position */ -#define SCU_SFSPD_13_EZI_Msk (0x01UL << SCU_SFSPD_13_EZI_Pos) /*!< SCU SFSPD_13: EZI Mask */ -#define SCU_SFSPD_13_EHD_Pos 8 /*!< SCU SFSPD_13: EHD Position */ -#define SCU_SFSPD_13_EHD_Msk (0x03UL << SCU_SFSPD_13_EHD_Pos) /*!< SCU SFSPD_13: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_14 ------------------------------------------ -#define SCU_SFSPD_14_MODE_Pos 0 /*!< SCU SFSPD_14: MODE Position */ -#define SCU_SFSPD_14_MODE_Msk (0x07UL << SCU_SFSPD_14_MODE_Pos) /*!< SCU SFSPD_14: MODE Mask */ -#define SCU_SFSPD_14_EPD_Pos 3 /*!< SCU SFSPD_14: EPD Position */ -#define SCU_SFSPD_14_EPD_Msk (0x01UL << SCU_SFSPD_14_EPD_Pos) /*!< SCU SFSPD_14: EPD Mask */ -#define SCU_SFSPD_14_EPUN_Pos 4 /*!< SCU SFSPD_14: EPUN Position */ -#define SCU_SFSPD_14_EPUN_Msk (0x01UL << SCU_SFSPD_14_EPUN_Pos) /*!< SCU SFSPD_14: EPUN Mask */ -#define SCU_SFSPD_14_EHS_Pos 5 /*!< SCU SFSPD_14: EHS Position */ -#define SCU_SFSPD_14_EHS_Msk (0x01UL << SCU_SFSPD_14_EHS_Pos) /*!< SCU SFSPD_14: EHS Mask */ -#define SCU_SFSPD_14_EZI_Pos 6 /*!< SCU SFSPD_14: EZI Position */ -#define SCU_SFSPD_14_EZI_Msk (0x01UL << SCU_SFSPD_14_EZI_Pos) /*!< SCU SFSPD_14: EZI Mask */ -#define SCU_SFSPD_14_EHD_Pos 8 /*!< SCU SFSPD_14: EHD Position */ -#define SCU_SFSPD_14_EHD_Msk (0x03UL << SCU_SFSPD_14_EHD_Pos) /*!< SCU SFSPD_14: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_15 ------------------------------------------ -#define SCU_SFSPD_15_MODE_Pos 0 /*!< SCU SFSPD_15: MODE Position */ -#define SCU_SFSPD_15_MODE_Msk (0x07UL << SCU_SFSPD_15_MODE_Pos) /*!< SCU SFSPD_15: MODE Mask */ -#define SCU_SFSPD_15_EPD_Pos 3 /*!< SCU SFSPD_15: EPD Position */ -#define SCU_SFSPD_15_EPD_Msk (0x01UL << SCU_SFSPD_15_EPD_Pos) /*!< SCU SFSPD_15: EPD Mask */ -#define SCU_SFSPD_15_EPUN_Pos 4 /*!< SCU SFSPD_15: EPUN Position */ -#define SCU_SFSPD_15_EPUN_Msk (0x01UL << SCU_SFSPD_15_EPUN_Pos) /*!< SCU SFSPD_15: EPUN Mask */ -#define SCU_SFSPD_15_EHS_Pos 5 /*!< SCU SFSPD_15: EHS Position */ -#define SCU_SFSPD_15_EHS_Msk (0x01UL << SCU_SFSPD_15_EHS_Pos) /*!< SCU SFSPD_15: EHS Mask */ -#define SCU_SFSPD_15_EZI_Pos 6 /*!< SCU SFSPD_15: EZI Position */ -#define SCU_SFSPD_15_EZI_Msk (0x01UL << SCU_SFSPD_15_EZI_Pos) /*!< SCU SFSPD_15: EZI Mask */ -#define SCU_SFSPD_15_EHD_Pos 8 /*!< SCU SFSPD_15: EHD Position */ -#define SCU_SFSPD_15_EHD_Msk (0x03UL << SCU_SFSPD_15_EHD_Pos) /*!< SCU SFSPD_15: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_16 ------------------------------------------ -#define SCU_SFSPD_16_MODE_Pos 0 /*!< SCU SFSPD_16: MODE Position */ -#define SCU_SFSPD_16_MODE_Msk (0x07UL << SCU_SFSPD_16_MODE_Pos) /*!< SCU SFSPD_16: MODE Mask */ -#define SCU_SFSPD_16_EPD_Pos 3 /*!< SCU SFSPD_16: EPD Position */ -#define SCU_SFSPD_16_EPD_Msk (0x01UL << SCU_SFSPD_16_EPD_Pos) /*!< SCU SFSPD_16: EPD Mask */ -#define SCU_SFSPD_16_EPUN_Pos 4 /*!< SCU SFSPD_16: EPUN Position */ -#define SCU_SFSPD_16_EPUN_Msk (0x01UL << SCU_SFSPD_16_EPUN_Pos) /*!< SCU SFSPD_16: EPUN Mask */ -#define SCU_SFSPD_16_EHS_Pos 5 /*!< SCU SFSPD_16: EHS Position */ -#define SCU_SFSPD_16_EHS_Msk (0x01UL << SCU_SFSPD_16_EHS_Pos) /*!< SCU SFSPD_16: EHS Mask */ -#define SCU_SFSPD_16_EZI_Pos 6 /*!< SCU SFSPD_16: EZI Position */ -#define SCU_SFSPD_16_EZI_Msk (0x01UL << SCU_SFSPD_16_EZI_Pos) /*!< SCU SFSPD_16: EZI Mask */ -#define SCU_SFSPD_16_EHD_Pos 8 /*!< SCU SFSPD_16: EHD Position */ -#define SCU_SFSPD_16_EHD_Msk (0x03UL << SCU_SFSPD_16_EHD_Pos) /*!< SCU SFSPD_16: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_0 ------------------------------------------ -#define SCU_SFSPE_0_MODE_Pos 0 /*!< SCU SFSPE_0: MODE Position */ -#define SCU_SFSPE_0_MODE_Msk (0x07UL << SCU_SFSPE_0_MODE_Pos) /*!< SCU SFSPE_0: MODE Mask */ -#define SCU_SFSPE_0_EPD_Pos 3 /*!< SCU SFSPE_0: EPD Position */ -#define SCU_SFSPE_0_EPD_Msk (0x01UL << SCU_SFSPE_0_EPD_Pos) /*!< SCU SFSPE_0: EPD Mask */ -#define SCU_SFSPE_0_EPUN_Pos 4 /*!< SCU SFSPE_0: EPUN Position */ -#define SCU_SFSPE_0_EPUN_Msk (0x01UL << SCU_SFSPE_0_EPUN_Pos) /*!< SCU SFSPE_0: EPUN Mask */ -#define SCU_SFSPE_0_EHS_Pos 5 /*!< SCU SFSPE_0: EHS Position */ -#define SCU_SFSPE_0_EHS_Msk (0x01UL << SCU_SFSPE_0_EHS_Pos) /*!< SCU SFSPE_0: EHS Mask */ -#define SCU_SFSPE_0_EZI_Pos 6 /*!< SCU SFSPE_0: EZI Position */ -#define SCU_SFSPE_0_EZI_Msk (0x01UL << SCU_SFSPE_0_EZI_Pos) /*!< SCU SFSPE_0: EZI Mask */ -#define SCU_SFSPE_0_EHD_Pos 8 /*!< SCU SFSPE_0: EHD Position */ -#define SCU_SFSPE_0_EHD_Msk (0x03UL << SCU_SFSPE_0_EHD_Pos) /*!< SCU SFSPE_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_1 ------------------------------------------ -#define SCU_SFSPE_1_MODE_Pos 0 /*!< SCU SFSPE_1: MODE Position */ -#define SCU_SFSPE_1_MODE_Msk (0x07UL << SCU_SFSPE_1_MODE_Pos) /*!< SCU SFSPE_1: MODE Mask */ -#define SCU_SFSPE_1_EPD_Pos 3 /*!< SCU SFSPE_1: EPD Position */ -#define SCU_SFSPE_1_EPD_Msk (0x01UL << SCU_SFSPE_1_EPD_Pos) /*!< SCU SFSPE_1: EPD Mask */ -#define SCU_SFSPE_1_EPUN_Pos 4 /*!< SCU SFSPE_1: EPUN Position */ -#define SCU_SFSPE_1_EPUN_Msk (0x01UL << SCU_SFSPE_1_EPUN_Pos) /*!< SCU SFSPE_1: EPUN Mask */ -#define SCU_SFSPE_1_EHS_Pos 5 /*!< SCU SFSPE_1: EHS Position */ -#define SCU_SFSPE_1_EHS_Msk (0x01UL << SCU_SFSPE_1_EHS_Pos) /*!< SCU SFSPE_1: EHS Mask */ -#define SCU_SFSPE_1_EZI_Pos 6 /*!< SCU SFSPE_1: EZI Position */ -#define SCU_SFSPE_1_EZI_Msk (0x01UL << SCU_SFSPE_1_EZI_Pos) /*!< SCU SFSPE_1: EZI Mask */ -#define SCU_SFSPE_1_EHD_Pos 8 /*!< SCU SFSPE_1: EHD Position */ -#define SCU_SFSPE_1_EHD_Msk (0x03UL << SCU_SFSPE_1_EHD_Pos) /*!< SCU SFSPE_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_2 ------------------------------------------ -#define SCU_SFSPE_2_MODE_Pos 0 /*!< SCU SFSPE_2: MODE Position */ -#define SCU_SFSPE_2_MODE_Msk (0x07UL << SCU_SFSPE_2_MODE_Pos) /*!< SCU SFSPE_2: MODE Mask */ -#define SCU_SFSPE_2_EPD_Pos 3 /*!< SCU SFSPE_2: EPD Position */ -#define SCU_SFSPE_2_EPD_Msk (0x01UL << SCU_SFSPE_2_EPD_Pos) /*!< SCU SFSPE_2: EPD Mask */ -#define SCU_SFSPE_2_EPUN_Pos 4 /*!< SCU SFSPE_2: EPUN Position */ -#define SCU_SFSPE_2_EPUN_Msk (0x01UL << SCU_SFSPE_2_EPUN_Pos) /*!< SCU SFSPE_2: EPUN Mask */ -#define SCU_SFSPE_2_EHS_Pos 5 /*!< SCU SFSPE_2: EHS Position */ -#define SCU_SFSPE_2_EHS_Msk (0x01UL << SCU_SFSPE_2_EHS_Pos) /*!< SCU SFSPE_2: EHS Mask */ -#define SCU_SFSPE_2_EZI_Pos 6 /*!< SCU SFSPE_2: EZI Position */ -#define SCU_SFSPE_2_EZI_Msk (0x01UL << SCU_SFSPE_2_EZI_Pos) /*!< SCU SFSPE_2: EZI Mask */ -#define SCU_SFSPE_2_EHD_Pos 8 /*!< SCU SFSPE_2: EHD Position */ -#define SCU_SFSPE_2_EHD_Msk (0x03UL << SCU_SFSPE_2_EHD_Pos) /*!< SCU SFSPE_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_3 ------------------------------------------ -#define SCU_SFSPE_3_MODE_Pos 0 /*!< SCU SFSPE_3: MODE Position */ -#define SCU_SFSPE_3_MODE_Msk (0x07UL << SCU_SFSPE_3_MODE_Pos) /*!< SCU SFSPE_3: MODE Mask */ -#define SCU_SFSPE_3_EPD_Pos 3 /*!< SCU SFSPE_3: EPD Position */ -#define SCU_SFSPE_3_EPD_Msk (0x01UL << SCU_SFSPE_3_EPD_Pos) /*!< SCU SFSPE_3: EPD Mask */ -#define SCU_SFSPE_3_EPUN_Pos 4 /*!< SCU SFSPE_3: EPUN Position */ -#define SCU_SFSPE_3_EPUN_Msk (0x01UL << SCU_SFSPE_3_EPUN_Pos) /*!< SCU SFSPE_3: EPUN Mask */ -#define SCU_SFSPE_3_EHS_Pos 5 /*!< SCU SFSPE_3: EHS Position */ -#define SCU_SFSPE_3_EHS_Msk (0x01UL << SCU_SFSPE_3_EHS_Pos) /*!< SCU SFSPE_3: EHS Mask */ -#define SCU_SFSPE_3_EZI_Pos 6 /*!< SCU SFSPE_3: EZI Position */ -#define SCU_SFSPE_3_EZI_Msk (0x01UL << SCU_SFSPE_3_EZI_Pos) /*!< SCU SFSPE_3: EZI Mask */ -#define SCU_SFSPE_3_EHD_Pos 8 /*!< SCU SFSPE_3: EHD Position */ -#define SCU_SFSPE_3_EHD_Msk (0x03UL << SCU_SFSPE_3_EHD_Pos) /*!< SCU SFSPE_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_4 ------------------------------------------ -#define SCU_SFSPE_4_MODE_Pos 0 /*!< SCU SFSPE_4: MODE Position */ -#define SCU_SFSPE_4_MODE_Msk (0x07UL << SCU_SFSPE_4_MODE_Pos) /*!< SCU SFSPE_4: MODE Mask */ -#define SCU_SFSPE_4_EPD_Pos 3 /*!< SCU SFSPE_4: EPD Position */ -#define SCU_SFSPE_4_EPD_Msk (0x01UL << SCU_SFSPE_4_EPD_Pos) /*!< SCU SFSPE_4: EPD Mask */ -#define SCU_SFSPE_4_EPUN_Pos 4 /*!< SCU SFSPE_4: EPUN Position */ -#define SCU_SFSPE_4_EPUN_Msk (0x01UL << SCU_SFSPE_4_EPUN_Pos) /*!< SCU SFSPE_4: EPUN Mask */ -#define SCU_SFSPE_4_EHS_Pos 5 /*!< SCU SFSPE_4: EHS Position */ -#define SCU_SFSPE_4_EHS_Msk (0x01UL << SCU_SFSPE_4_EHS_Pos) /*!< SCU SFSPE_4: EHS Mask */ -#define SCU_SFSPE_4_EZI_Pos 6 /*!< SCU SFSPE_4: EZI Position */ -#define SCU_SFSPE_4_EZI_Msk (0x01UL << SCU_SFSPE_4_EZI_Pos) /*!< SCU SFSPE_4: EZI Mask */ -#define SCU_SFSPE_4_EHD_Pos 8 /*!< SCU SFSPE_4: EHD Position */ -#define SCU_SFSPE_4_EHD_Msk (0x03UL << SCU_SFSPE_4_EHD_Pos) /*!< SCU SFSPE_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_5 ------------------------------------------ -#define SCU_SFSPE_5_MODE_Pos 0 /*!< SCU SFSPE_5: MODE Position */ -#define SCU_SFSPE_5_MODE_Msk (0x07UL << SCU_SFSPE_5_MODE_Pos) /*!< SCU SFSPE_5: MODE Mask */ -#define SCU_SFSPE_5_EPD_Pos 3 /*!< SCU SFSPE_5: EPD Position */ -#define SCU_SFSPE_5_EPD_Msk (0x01UL << SCU_SFSPE_5_EPD_Pos) /*!< SCU SFSPE_5: EPD Mask */ -#define SCU_SFSPE_5_EPUN_Pos 4 /*!< SCU SFSPE_5: EPUN Position */ -#define SCU_SFSPE_5_EPUN_Msk (0x01UL << SCU_SFSPE_5_EPUN_Pos) /*!< SCU SFSPE_5: EPUN Mask */ -#define SCU_SFSPE_5_EHS_Pos 5 /*!< SCU SFSPE_5: EHS Position */ -#define SCU_SFSPE_5_EHS_Msk (0x01UL << SCU_SFSPE_5_EHS_Pos) /*!< SCU SFSPE_5: EHS Mask */ -#define SCU_SFSPE_5_EZI_Pos 6 /*!< SCU SFSPE_5: EZI Position */ -#define SCU_SFSPE_5_EZI_Msk (0x01UL << SCU_SFSPE_5_EZI_Pos) /*!< SCU SFSPE_5: EZI Mask */ -#define SCU_SFSPE_5_EHD_Pos 8 /*!< SCU SFSPE_5: EHD Position */ -#define SCU_SFSPE_5_EHD_Msk (0x03UL << SCU_SFSPE_5_EHD_Pos) /*!< SCU SFSPE_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_6 ------------------------------------------ -#define SCU_SFSPE_6_MODE_Pos 0 /*!< SCU SFSPE_6: MODE Position */ -#define SCU_SFSPE_6_MODE_Msk (0x07UL << SCU_SFSPE_6_MODE_Pos) /*!< SCU SFSPE_6: MODE Mask */ -#define SCU_SFSPE_6_EPD_Pos 3 /*!< SCU SFSPE_6: EPD Position */ -#define SCU_SFSPE_6_EPD_Msk (0x01UL << SCU_SFSPE_6_EPD_Pos) /*!< SCU SFSPE_6: EPD Mask */ -#define SCU_SFSPE_6_EPUN_Pos 4 /*!< SCU SFSPE_6: EPUN Position */ -#define SCU_SFSPE_6_EPUN_Msk (0x01UL << SCU_SFSPE_6_EPUN_Pos) /*!< SCU SFSPE_6: EPUN Mask */ -#define SCU_SFSPE_6_EHS_Pos 5 /*!< SCU SFSPE_6: EHS Position */ -#define SCU_SFSPE_6_EHS_Msk (0x01UL << SCU_SFSPE_6_EHS_Pos) /*!< SCU SFSPE_6: EHS Mask */ -#define SCU_SFSPE_6_EZI_Pos 6 /*!< SCU SFSPE_6: EZI Position */ -#define SCU_SFSPE_6_EZI_Msk (0x01UL << SCU_SFSPE_6_EZI_Pos) /*!< SCU SFSPE_6: EZI Mask */ -#define SCU_SFSPE_6_EHD_Pos 8 /*!< SCU SFSPE_6: EHD Position */ -#define SCU_SFSPE_6_EHD_Msk (0x03UL << SCU_SFSPE_6_EHD_Pos) /*!< SCU SFSPE_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_7 ------------------------------------------ -#define SCU_SFSPE_7_MODE_Pos 0 /*!< SCU SFSPE_7: MODE Position */ -#define SCU_SFSPE_7_MODE_Msk (0x07UL << SCU_SFSPE_7_MODE_Pos) /*!< SCU SFSPE_7: MODE Mask */ -#define SCU_SFSPE_7_EPD_Pos 3 /*!< SCU SFSPE_7: EPD Position */ -#define SCU_SFSPE_7_EPD_Msk (0x01UL << SCU_SFSPE_7_EPD_Pos) /*!< SCU SFSPE_7: EPD Mask */ -#define SCU_SFSPE_7_EPUN_Pos 4 /*!< SCU SFSPE_7: EPUN Position */ -#define SCU_SFSPE_7_EPUN_Msk (0x01UL << SCU_SFSPE_7_EPUN_Pos) /*!< SCU SFSPE_7: EPUN Mask */ -#define SCU_SFSPE_7_EHS_Pos 5 /*!< SCU SFSPE_7: EHS Position */ -#define SCU_SFSPE_7_EHS_Msk (0x01UL << SCU_SFSPE_7_EHS_Pos) /*!< SCU SFSPE_7: EHS Mask */ -#define SCU_SFSPE_7_EZI_Pos 6 /*!< SCU SFSPE_7: EZI Position */ -#define SCU_SFSPE_7_EZI_Msk (0x01UL << SCU_SFSPE_7_EZI_Pos) /*!< SCU SFSPE_7: EZI Mask */ -#define SCU_SFSPE_7_EHD_Pos 8 /*!< SCU SFSPE_7: EHD Position */ -#define SCU_SFSPE_7_EHD_Msk (0x03UL << SCU_SFSPE_7_EHD_Pos) /*!< SCU SFSPE_7: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_8 ------------------------------------------ -#define SCU_SFSPE_8_MODE_Pos 0 /*!< SCU SFSPE_8: MODE Position */ -#define SCU_SFSPE_8_MODE_Msk (0x07UL << SCU_SFSPE_8_MODE_Pos) /*!< SCU SFSPE_8: MODE Mask */ -#define SCU_SFSPE_8_EPD_Pos 3 /*!< SCU SFSPE_8: EPD Position */ -#define SCU_SFSPE_8_EPD_Msk (0x01UL << SCU_SFSPE_8_EPD_Pos) /*!< SCU SFSPE_8: EPD Mask */ -#define SCU_SFSPE_8_EPUN_Pos 4 /*!< SCU SFSPE_8: EPUN Position */ -#define SCU_SFSPE_8_EPUN_Msk (0x01UL << SCU_SFSPE_8_EPUN_Pos) /*!< SCU SFSPE_8: EPUN Mask */ -#define SCU_SFSPE_8_EHS_Pos 5 /*!< SCU SFSPE_8: EHS Position */ -#define SCU_SFSPE_8_EHS_Msk (0x01UL << SCU_SFSPE_8_EHS_Pos) /*!< SCU SFSPE_8: EHS Mask */ -#define SCU_SFSPE_8_EZI_Pos 6 /*!< SCU SFSPE_8: EZI Position */ -#define SCU_SFSPE_8_EZI_Msk (0x01UL << SCU_SFSPE_8_EZI_Pos) /*!< SCU SFSPE_8: EZI Mask */ -#define SCU_SFSPE_8_EHD_Pos 8 /*!< SCU SFSPE_8: EHD Position */ -#define SCU_SFSPE_8_EHD_Msk (0x03UL << SCU_SFSPE_8_EHD_Pos) /*!< SCU SFSPE_8: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_9 ------------------------------------------ -#define SCU_SFSPE_9_MODE_Pos 0 /*!< SCU SFSPE_9: MODE Position */ -#define SCU_SFSPE_9_MODE_Msk (0x07UL << SCU_SFSPE_9_MODE_Pos) /*!< SCU SFSPE_9: MODE Mask */ -#define SCU_SFSPE_9_EPD_Pos 3 /*!< SCU SFSPE_9: EPD Position */ -#define SCU_SFSPE_9_EPD_Msk (0x01UL << SCU_SFSPE_9_EPD_Pos) /*!< SCU SFSPE_9: EPD Mask */ -#define SCU_SFSPE_9_EPUN_Pos 4 /*!< SCU SFSPE_9: EPUN Position */ -#define SCU_SFSPE_9_EPUN_Msk (0x01UL << SCU_SFSPE_9_EPUN_Pos) /*!< SCU SFSPE_9: EPUN Mask */ -#define SCU_SFSPE_9_EHS_Pos 5 /*!< SCU SFSPE_9: EHS Position */ -#define SCU_SFSPE_9_EHS_Msk (0x01UL << SCU_SFSPE_9_EHS_Pos) /*!< SCU SFSPE_9: EHS Mask */ -#define SCU_SFSPE_9_EZI_Pos 6 /*!< SCU SFSPE_9: EZI Position */ -#define SCU_SFSPE_9_EZI_Msk (0x01UL << SCU_SFSPE_9_EZI_Pos) /*!< SCU SFSPE_9: EZI Mask */ -#define SCU_SFSPE_9_EHD_Pos 8 /*!< SCU SFSPE_9: EHD Position */ -#define SCU_SFSPE_9_EHD_Msk (0x03UL << SCU_SFSPE_9_EHD_Pos) /*!< SCU SFSPE_9: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_10 ------------------------------------------ -#define SCU_SFSPE_10_MODE_Pos 0 /*!< SCU SFSPE_10: MODE Position */ -#define SCU_SFSPE_10_MODE_Msk (0x07UL << SCU_SFSPE_10_MODE_Pos) /*!< SCU SFSPE_10: MODE Mask */ -#define SCU_SFSPE_10_EPD_Pos 3 /*!< SCU SFSPE_10: EPD Position */ -#define SCU_SFSPE_10_EPD_Msk (0x01UL << SCU_SFSPE_10_EPD_Pos) /*!< SCU SFSPE_10: EPD Mask */ -#define SCU_SFSPE_10_EPUN_Pos 4 /*!< SCU SFSPE_10: EPUN Position */ -#define SCU_SFSPE_10_EPUN_Msk (0x01UL << SCU_SFSPE_10_EPUN_Pos) /*!< SCU SFSPE_10: EPUN Mask */ -#define SCU_SFSPE_10_EHS_Pos 5 /*!< SCU SFSPE_10: EHS Position */ -#define SCU_SFSPE_10_EHS_Msk (0x01UL << SCU_SFSPE_10_EHS_Pos) /*!< SCU SFSPE_10: EHS Mask */ -#define SCU_SFSPE_10_EZI_Pos 6 /*!< SCU SFSPE_10: EZI Position */ -#define SCU_SFSPE_10_EZI_Msk (0x01UL << SCU_SFSPE_10_EZI_Pos) /*!< SCU SFSPE_10: EZI Mask */ -#define SCU_SFSPE_10_EHD_Pos 8 /*!< SCU SFSPE_10: EHD Position */ -#define SCU_SFSPE_10_EHD_Msk (0x03UL << SCU_SFSPE_10_EHD_Pos) /*!< SCU SFSPE_10: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_11 ------------------------------------------ -#define SCU_SFSPE_11_MODE_Pos 0 /*!< SCU SFSPE_11: MODE Position */ -#define SCU_SFSPE_11_MODE_Msk (0x07UL << SCU_SFSPE_11_MODE_Pos) /*!< SCU SFSPE_11: MODE Mask */ -#define SCU_SFSPE_11_EPD_Pos 3 /*!< SCU SFSPE_11: EPD Position */ -#define SCU_SFSPE_11_EPD_Msk (0x01UL << SCU_SFSPE_11_EPD_Pos) /*!< SCU SFSPE_11: EPD Mask */ -#define SCU_SFSPE_11_EPUN_Pos 4 /*!< SCU SFSPE_11: EPUN Position */ -#define SCU_SFSPE_11_EPUN_Msk (0x01UL << SCU_SFSPE_11_EPUN_Pos) /*!< SCU SFSPE_11: EPUN Mask */ -#define SCU_SFSPE_11_EHS_Pos 5 /*!< SCU SFSPE_11: EHS Position */ -#define SCU_SFSPE_11_EHS_Msk (0x01UL << SCU_SFSPE_11_EHS_Pos) /*!< SCU SFSPE_11: EHS Mask */ -#define SCU_SFSPE_11_EZI_Pos 6 /*!< SCU SFSPE_11: EZI Position */ -#define SCU_SFSPE_11_EZI_Msk (0x01UL << SCU_SFSPE_11_EZI_Pos) /*!< SCU SFSPE_11: EZI Mask */ -#define SCU_SFSPE_11_EHD_Pos 8 /*!< SCU SFSPE_11: EHD Position */ -#define SCU_SFSPE_11_EHD_Msk (0x03UL << SCU_SFSPE_11_EHD_Pos) /*!< SCU SFSPE_11: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_12 ------------------------------------------ -#define SCU_SFSPE_12_MODE_Pos 0 /*!< SCU SFSPE_12: MODE Position */ -#define SCU_SFSPE_12_MODE_Msk (0x07UL << SCU_SFSPE_12_MODE_Pos) /*!< SCU SFSPE_12: MODE Mask */ -#define SCU_SFSPE_12_EPD_Pos 3 /*!< SCU SFSPE_12: EPD Position */ -#define SCU_SFSPE_12_EPD_Msk (0x01UL << SCU_SFSPE_12_EPD_Pos) /*!< SCU SFSPE_12: EPD Mask */ -#define SCU_SFSPE_12_EPUN_Pos 4 /*!< SCU SFSPE_12: EPUN Position */ -#define SCU_SFSPE_12_EPUN_Msk (0x01UL << SCU_SFSPE_12_EPUN_Pos) /*!< SCU SFSPE_12: EPUN Mask */ -#define SCU_SFSPE_12_EHS_Pos 5 /*!< SCU SFSPE_12: EHS Position */ -#define SCU_SFSPE_12_EHS_Msk (0x01UL << SCU_SFSPE_12_EHS_Pos) /*!< SCU SFSPE_12: EHS Mask */ -#define SCU_SFSPE_12_EZI_Pos 6 /*!< SCU SFSPE_12: EZI Position */ -#define SCU_SFSPE_12_EZI_Msk (0x01UL << SCU_SFSPE_12_EZI_Pos) /*!< SCU SFSPE_12: EZI Mask */ -#define SCU_SFSPE_12_EHD_Pos 8 /*!< SCU SFSPE_12: EHD Position */ -#define SCU_SFSPE_12_EHD_Msk (0x03UL << SCU_SFSPE_12_EHD_Pos) /*!< SCU SFSPE_12: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_13 ------------------------------------------ -#define SCU_SFSPE_13_MODE_Pos 0 /*!< SCU SFSPE_13: MODE Position */ -#define SCU_SFSPE_13_MODE_Msk (0x07UL << SCU_SFSPE_13_MODE_Pos) /*!< SCU SFSPE_13: MODE Mask */ -#define SCU_SFSPE_13_EPD_Pos 3 /*!< SCU SFSPE_13: EPD Position */ -#define SCU_SFSPE_13_EPD_Msk (0x01UL << SCU_SFSPE_13_EPD_Pos) /*!< SCU SFSPE_13: EPD Mask */ -#define SCU_SFSPE_13_EPUN_Pos 4 /*!< SCU SFSPE_13: EPUN Position */ -#define SCU_SFSPE_13_EPUN_Msk (0x01UL << SCU_SFSPE_13_EPUN_Pos) /*!< SCU SFSPE_13: EPUN Mask */ -#define SCU_SFSPE_13_EHS_Pos 5 /*!< SCU SFSPE_13: EHS Position */ -#define SCU_SFSPE_13_EHS_Msk (0x01UL << SCU_SFSPE_13_EHS_Pos) /*!< SCU SFSPE_13: EHS Mask */ -#define SCU_SFSPE_13_EZI_Pos 6 /*!< SCU SFSPE_13: EZI Position */ -#define SCU_SFSPE_13_EZI_Msk (0x01UL << SCU_SFSPE_13_EZI_Pos) /*!< SCU SFSPE_13: EZI Mask */ -#define SCU_SFSPE_13_EHD_Pos 8 /*!< SCU SFSPE_13: EHD Position */ -#define SCU_SFSPE_13_EHD_Msk (0x03UL << SCU_SFSPE_13_EHD_Pos) /*!< SCU SFSPE_13: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_14 ------------------------------------------ -#define SCU_SFSPE_14_MODE_Pos 0 /*!< SCU SFSPE_14: MODE Position */ -#define SCU_SFSPE_14_MODE_Msk (0x07UL << SCU_SFSPE_14_MODE_Pos) /*!< SCU SFSPE_14: MODE Mask */ -#define SCU_SFSPE_14_EPD_Pos 3 /*!< SCU SFSPE_14: EPD Position */ -#define SCU_SFSPE_14_EPD_Msk (0x01UL << SCU_SFSPE_14_EPD_Pos) /*!< SCU SFSPE_14: EPD Mask */ -#define SCU_SFSPE_14_EPUN_Pos 4 /*!< SCU SFSPE_14: EPUN Position */ -#define SCU_SFSPE_14_EPUN_Msk (0x01UL << SCU_SFSPE_14_EPUN_Pos) /*!< SCU SFSPE_14: EPUN Mask */ -#define SCU_SFSPE_14_EHS_Pos 5 /*!< SCU SFSPE_14: EHS Position */ -#define SCU_SFSPE_14_EHS_Msk (0x01UL << SCU_SFSPE_14_EHS_Pos) /*!< SCU SFSPE_14: EHS Mask */ -#define SCU_SFSPE_14_EZI_Pos 6 /*!< SCU SFSPE_14: EZI Position */ -#define SCU_SFSPE_14_EZI_Msk (0x01UL << SCU_SFSPE_14_EZI_Pos) /*!< SCU SFSPE_14: EZI Mask */ -#define SCU_SFSPE_14_EHD_Pos 8 /*!< SCU SFSPE_14: EHD Position */ -#define SCU_SFSPE_14_EHD_Msk (0x03UL << SCU_SFSPE_14_EHD_Pos) /*!< SCU SFSPE_14: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_15 ------------------------------------------ -#define SCU_SFSPE_15_MODE_Pos 0 /*!< SCU SFSPE_15: MODE Position */ -#define SCU_SFSPE_15_MODE_Msk (0x07UL << SCU_SFSPE_15_MODE_Pos) /*!< SCU SFSPE_15: MODE Mask */ -#define SCU_SFSPE_15_EPD_Pos 3 /*!< SCU SFSPE_15: EPD Position */ -#define SCU_SFSPE_15_EPD_Msk (0x01UL << SCU_SFSPE_15_EPD_Pos) /*!< SCU SFSPE_15: EPD Mask */ -#define SCU_SFSPE_15_EPUN_Pos 4 /*!< SCU SFSPE_15: EPUN Position */ -#define SCU_SFSPE_15_EPUN_Msk (0x01UL << SCU_SFSPE_15_EPUN_Pos) /*!< SCU SFSPE_15: EPUN Mask */ -#define SCU_SFSPE_15_EHS_Pos 5 /*!< SCU SFSPE_15: EHS Position */ -#define SCU_SFSPE_15_EHS_Msk (0x01UL << SCU_SFSPE_15_EHS_Pos) /*!< SCU SFSPE_15: EHS Mask */ -#define SCU_SFSPE_15_EZI_Pos 6 /*!< SCU SFSPE_15: EZI Position */ -#define SCU_SFSPE_15_EZI_Msk (0x01UL << SCU_SFSPE_15_EZI_Pos) /*!< SCU SFSPE_15: EZI Mask */ -#define SCU_SFSPE_15_EHD_Pos 8 /*!< SCU SFSPE_15: EHD Position */ -#define SCU_SFSPE_15_EHD_Msk (0x03UL << SCU_SFSPE_15_EHD_Pos) /*!< SCU SFSPE_15: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_0 ------------------------------------------ -#define SCU_SFSPF_0_MODE_Pos 0 /*!< SCU SFSPF_0: MODE Position */ -#define SCU_SFSPF_0_MODE_Msk (0x07UL << SCU_SFSPF_0_MODE_Pos) /*!< SCU SFSPF_0: MODE Mask */ -#define SCU_SFSPF_0_EPD_Pos 3 /*!< SCU SFSPF_0: EPD Position */ -#define SCU_SFSPF_0_EPD_Msk (0x01UL << SCU_SFSPF_0_EPD_Pos) /*!< SCU SFSPF_0: EPD Mask */ -#define SCU_SFSPF_0_EPUN_Pos 4 /*!< SCU SFSPF_0: EPUN Position */ -#define SCU_SFSPF_0_EPUN_Msk (0x01UL << SCU_SFSPF_0_EPUN_Pos) /*!< SCU SFSPF_0: EPUN Mask */ -#define SCU_SFSPF_0_EHS_Pos 5 /*!< SCU SFSPF_0: EHS Position */ -#define SCU_SFSPF_0_EHS_Msk (0x01UL << SCU_SFSPF_0_EHS_Pos) /*!< SCU SFSPF_0: EHS Mask */ -#define SCU_SFSPF_0_EZI_Pos 6 /*!< SCU SFSPF_0: EZI Position */ -#define SCU_SFSPF_0_EZI_Msk (0x01UL << SCU_SFSPF_0_EZI_Pos) /*!< SCU SFSPF_0: EZI Mask */ -#define SCU_SFSPF_0_EHD_Pos 8 /*!< SCU SFSPF_0: EHD Position */ -#define SCU_SFSPF_0_EHD_Msk (0x03UL << SCU_SFSPF_0_EHD_Pos) /*!< SCU SFSPF_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_1 ------------------------------------------ -#define SCU_SFSPF_1_MODE_Pos 0 /*!< SCU SFSPF_1: MODE Position */ -#define SCU_SFSPF_1_MODE_Msk (0x07UL << SCU_SFSPF_1_MODE_Pos) /*!< SCU SFSPF_1: MODE Mask */ -#define SCU_SFSPF_1_EPD_Pos 3 /*!< SCU SFSPF_1: EPD Position */ -#define SCU_SFSPF_1_EPD_Msk (0x01UL << SCU_SFSPF_1_EPD_Pos) /*!< SCU SFSPF_1: EPD Mask */ -#define SCU_SFSPF_1_EPUN_Pos 4 /*!< SCU SFSPF_1: EPUN Position */ -#define SCU_SFSPF_1_EPUN_Msk (0x01UL << SCU_SFSPF_1_EPUN_Pos) /*!< SCU SFSPF_1: EPUN Mask */ -#define SCU_SFSPF_1_EHS_Pos 5 /*!< SCU SFSPF_1: EHS Position */ -#define SCU_SFSPF_1_EHS_Msk (0x01UL << SCU_SFSPF_1_EHS_Pos) /*!< SCU SFSPF_1: EHS Mask */ -#define SCU_SFSPF_1_EZI_Pos 6 /*!< SCU SFSPF_1: EZI Position */ -#define SCU_SFSPF_1_EZI_Msk (0x01UL << SCU_SFSPF_1_EZI_Pos) /*!< SCU SFSPF_1: EZI Mask */ -#define SCU_SFSPF_1_EHD_Pos 8 /*!< SCU SFSPF_1: EHD Position */ -#define SCU_SFSPF_1_EHD_Msk (0x03UL << SCU_SFSPF_1_EHD_Pos) /*!< SCU SFSPF_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_2 ------------------------------------------ -#define SCU_SFSPF_2_MODE_Pos 0 /*!< SCU SFSPF_2: MODE Position */ -#define SCU_SFSPF_2_MODE_Msk (0x07UL << SCU_SFSPF_2_MODE_Pos) /*!< SCU SFSPF_2: MODE Mask */ -#define SCU_SFSPF_2_EPD_Pos 3 /*!< SCU SFSPF_2: EPD Position */ -#define SCU_SFSPF_2_EPD_Msk (0x01UL << SCU_SFSPF_2_EPD_Pos) /*!< SCU SFSPF_2: EPD Mask */ -#define SCU_SFSPF_2_EPUN_Pos 4 /*!< SCU SFSPF_2: EPUN Position */ -#define SCU_SFSPF_2_EPUN_Msk (0x01UL << SCU_SFSPF_2_EPUN_Pos) /*!< SCU SFSPF_2: EPUN Mask */ -#define SCU_SFSPF_2_EHS_Pos 5 /*!< SCU SFSPF_2: EHS Position */ -#define SCU_SFSPF_2_EHS_Msk (0x01UL << SCU_SFSPF_2_EHS_Pos) /*!< SCU SFSPF_2: EHS Mask */ -#define SCU_SFSPF_2_EZI_Pos 6 /*!< SCU SFSPF_2: EZI Position */ -#define SCU_SFSPF_2_EZI_Msk (0x01UL << SCU_SFSPF_2_EZI_Pos) /*!< SCU SFSPF_2: EZI Mask */ -#define SCU_SFSPF_2_EHD_Pos 8 /*!< SCU SFSPF_2: EHD Position */ -#define SCU_SFSPF_2_EHD_Msk (0x03UL << SCU_SFSPF_2_EHD_Pos) /*!< SCU SFSPF_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_3 ------------------------------------------ -#define SCU_SFSPF_3_MODE_Pos 0 /*!< SCU SFSPF_3: MODE Position */ -#define SCU_SFSPF_3_MODE_Msk (0x07UL << SCU_SFSPF_3_MODE_Pos) /*!< SCU SFSPF_3: MODE Mask */ -#define SCU_SFSPF_3_EPD_Pos 3 /*!< SCU SFSPF_3: EPD Position */ -#define SCU_SFSPF_3_EPD_Msk (0x01UL << SCU_SFSPF_3_EPD_Pos) /*!< SCU SFSPF_3: EPD Mask */ -#define SCU_SFSPF_3_EPUN_Pos 4 /*!< SCU SFSPF_3: EPUN Position */ -#define SCU_SFSPF_3_EPUN_Msk (0x01UL << SCU_SFSPF_3_EPUN_Pos) /*!< SCU SFSPF_3: EPUN Mask */ -#define SCU_SFSPF_3_EHS_Pos 5 /*!< SCU SFSPF_3: EHS Position */ -#define SCU_SFSPF_3_EHS_Msk (0x01UL << SCU_SFSPF_3_EHS_Pos) /*!< SCU SFSPF_3: EHS Mask */ -#define SCU_SFSPF_3_EZI_Pos 6 /*!< SCU SFSPF_3: EZI Position */ -#define SCU_SFSPF_3_EZI_Msk (0x01UL << SCU_SFSPF_3_EZI_Pos) /*!< SCU SFSPF_3: EZI Mask */ -#define SCU_SFSPF_3_EHD_Pos 8 /*!< SCU SFSPF_3: EHD Position */ -#define SCU_SFSPF_3_EHD_Msk (0x03UL << SCU_SFSPF_3_EHD_Pos) /*!< SCU SFSPF_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_4 ------------------------------------------ -#define SCU_SFSPF_4_MODE_Pos 0 /*!< SCU SFSPF_4: MODE Position */ -#define SCU_SFSPF_4_MODE_Msk (0x07UL << SCU_SFSPF_4_MODE_Pos) /*!< SCU SFSPF_4: MODE Mask */ -#define SCU_SFSPF_4_EPD_Pos 3 /*!< SCU SFSPF_4: EPD Position */ -#define SCU_SFSPF_4_EPD_Msk (0x01UL << SCU_SFSPF_4_EPD_Pos) /*!< SCU SFSPF_4: EPD Mask */ -#define SCU_SFSPF_4_EPUN_Pos 4 /*!< SCU SFSPF_4: EPUN Position */ -#define SCU_SFSPF_4_EPUN_Msk (0x01UL << SCU_SFSPF_4_EPUN_Pos) /*!< SCU SFSPF_4: EPUN Mask */ -#define SCU_SFSPF_4_EHS_Pos 5 /*!< SCU SFSPF_4: EHS Position */ -#define SCU_SFSPF_4_EHS_Msk (0x01UL << SCU_SFSPF_4_EHS_Pos) /*!< SCU SFSPF_4: EHS Mask */ -#define SCU_SFSPF_4_EZI_Pos 6 /*!< SCU SFSPF_4: EZI Position */ -#define SCU_SFSPF_4_EZI_Msk (0x01UL << SCU_SFSPF_4_EZI_Pos) /*!< SCU SFSPF_4: EZI Mask */ -#define SCU_SFSPF_4_EHD_Pos 8 /*!< SCU SFSPF_4: EHD Position */ -#define SCU_SFSPF_4_EHD_Msk (0x03UL << SCU_SFSPF_4_EHD_Pos) /*!< SCU SFSPF_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_5 ------------------------------------------ -#define SCU_SFSPF_5_MODE_Pos 0 /*!< SCU SFSPF_5: MODE Position */ -#define SCU_SFSPF_5_MODE_Msk (0x07UL << SCU_SFSPF_5_MODE_Pos) /*!< SCU SFSPF_5: MODE Mask */ -#define SCU_SFSPF_5_EPD_Pos 3 /*!< SCU SFSPF_5: EPD Position */ -#define SCU_SFSPF_5_EPD_Msk (0x01UL << SCU_SFSPF_5_EPD_Pos) /*!< SCU SFSPF_5: EPD Mask */ -#define SCU_SFSPF_5_EPUN_Pos 4 /*!< SCU SFSPF_5: EPUN Position */ -#define SCU_SFSPF_5_EPUN_Msk (0x01UL << SCU_SFSPF_5_EPUN_Pos) /*!< SCU SFSPF_5: EPUN Mask */ -#define SCU_SFSPF_5_EHS_Pos 5 /*!< SCU SFSPF_5: EHS Position */ -#define SCU_SFSPF_5_EHS_Msk (0x01UL << SCU_SFSPF_5_EHS_Pos) /*!< SCU SFSPF_5: EHS Mask */ -#define SCU_SFSPF_5_EZI_Pos 6 /*!< SCU SFSPF_5: EZI Position */ -#define SCU_SFSPF_5_EZI_Msk (0x01UL << SCU_SFSPF_5_EZI_Pos) /*!< SCU SFSPF_5: EZI Mask */ -#define SCU_SFSPF_5_EHD_Pos 8 /*!< SCU SFSPF_5: EHD Position */ -#define SCU_SFSPF_5_EHD_Msk (0x03UL << SCU_SFSPF_5_EHD_Pos) /*!< SCU SFSPF_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_6 ------------------------------------------ -#define SCU_SFSPF_6_MODE_Pos 0 /*!< SCU SFSPF_6: MODE Position */ -#define SCU_SFSPF_6_MODE_Msk (0x07UL << SCU_SFSPF_6_MODE_Pos) /*!< SCU SFSPF_6: MODE Mask */ -#define SCU_SFSPF_6_EPD_Pos 3 /*!< SCU SFSPF_6: EPD Position */ -#define SCU_SFSPF_6_EPD_Msk (0x01UL << SCU_SFSPF_6_EPD_Pos) /*!< SCU SFSPF_6: EPD Mask */ -#define SCU_SFSPF_6_EPUN_Pos 4 /*!< SCU SFSPF_6: EPUN Position */ -#define SCU_SFSPF_6_EPUN_Msk (0x01UL << SCU_SFSPF_6_EPUN_Pos) /*!< SCU SFSPF_6: EPUN Mask */ -#define SCU_SFSPF_6_EHS_Pos 5 /*!< SCU SFSPF_6: EHS Position */ -#define SCU_SFSPF_6_EHS_Msk (0x01UL << SCU_SFSPF_6_EHS_Pos) /*!< SCU SFSPF_6: EHS Mask */ -#define SCU_SFSPF_6_EZI_Pos 6 /*!< SCU SFSPF_6: EZI Position */ -#define SCU_SFSPF_6_EZI_Msk (0x01UL << SCU_SFSPF_6_EZI_Pos) /*!< SCU SFSPF_6: EZI Mask */ -#define SCU_SFSPF_6_EHD_Pos 8 /*!< SCU SFSPF_6: EHD Position */ -#define SCU_SFSPF_6_EHD_Msk (0x03UL << SCU_SFSPF_6_EHD_Pos) /*!< SCU SFSPF_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_7 ------------------------------------------ -#define SCU_SFSPF_7_MODE_Pos 0 /*!< SCU SFSPF_7: MODE Position */ -#define SCU_SFSPF_7_MODE_Msk (0x07UL << SCU_SFSPF_7_MODE_Pos) /*!< SCU SFSPF_7: MODE Mask */ -#define SCU_SFSPF_7_EPD_Pos 3 /*!< SCU SFSPF_7: EPD Position */ -#define SCU_SFSPF_7_EPD_Msk (0x01UL << SCU_SFSPF_7_EPD_Pos) /*!< SCU SFSPF_7: EPD Mask */ -#define SCU_SFSPF_7_EPUN_Pos 4 /*!< SCU SFSPF_7: EPUN Position */ -#define SCU_SFSPF_7_EPUN_Msk (0x01UL << SCU_SFSPF_7_EPUN_Pos) /*!< SCU SFSPF_7: EPUN Mask */ -#define SCU_SFSPF_7_EHS_Pos 5 /*!< SCU SFSPF_7: EHS Position */ -#define SCU_SFSPF_7_EHS_Msk (0x01UL << SCU_SFSPF_7_EHS_Pos) /*!< SCU SFSPF_7: EHS Mask */ -#define SCU_SFSPF_7_EZI_Pos 6 /*!< SCU SFSPF_7: EZI Position */ -#define SCU_SFSPF_7_EZI_Msk (0x01UL << SCU_SFSPF_7_EZI_Pos) /*!< SCU SFSPF_7: EZI Mask */ -#define SCU_SFSPF_7_EHD_Pos 8 /*!< SCU SFSPF_7: EHD Position */ -#define SCU_SFSPF_7_EHD_Msk (0x03UL << SCU_SFSPF_7_EHD_Pos) /*!< SCU SFSPF_7: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_8 ------------------------------------------ -#define SCU_SFSPF_8_MODE_Pos 0 /*!< SCU SFSPF_8: MODE Position */ -#define SCU_SFSPF_8_MODE_Msk (0x07UL << SCU_SFSPF_8_MODE_Pos) /*!< SCU SFSPF_8: MODE Mask */ -#define SCU_SFSPF_8_EPD_Pos 3 /*!< SCU SFSPF_8: EPD Position */ -#define SCU_SFSPF_8_EPD_Msk (0x01UL << SCU_SFSPF_8_EPD_Pos) /*!< SCU SFSPF_8: EPD Mask */ -#define SCU_SFSPF_8_EPUN_Pos 4 /*!< SCU SFSPF_8: EPUN Position */ -#define SCU_SFSPF_8_EPUN_Msk (0x01UL << SCU_SFSPF_8_EPUN_Pos) /*!< SCU SFSPF_8: EPUN Mask */ -#define SCU_SFSPF_8_EHS_Pos 5 /*!< SCU SFSPF_8: EHS Position */ -#define SCU_SFSPF_8_EHS_Msk (0x01UL << SCU_SFSPF_8_EHS_Pos) /*!< SCU SFSPF_8: EHS Mask */ -#define SCU_SFSPF_8_EZI_Pos 6 /*!< SCU SFSPF_8: EZI Position */ -#define SCU_SFSPF_8_EZI_Msk (0x01UL << SCU_SFSPF_8_EZI_Pos) /*!< SCU SFSPF_8: EZI Mask */ -#define SCU_SFSPF_8_EHD_Pos 8 /*!< SCU SFSPF_8: EHD Position */ -#define SCU_SFSPF_8_EHD_Msk (0x03UL << SCU_SFSPF_8_EHD_Pos) /*!< SCU SFSPF_8: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_9 ------------------------------------------ -#define SCU_SFSPF_9_MODE_Pos 0 /*!< SCU SFSPF_9: MODE Position */ -#define SCU_SFSPF_9_MODE_Msk (0x07UL << SCU_SFSPF_9_MODE_Pos) /*!< SCU SFSPF_9: MODE Mask */ -#define SCU_SFSPF_9_EPD_Pos 3 /*!< SCU SFSPF_9: EPD Position */ -#define SCU_SFSPF_9_EPD_Msk (0x01UL << SCU_SFSPF_9_EPD_Pos) /*!< SCU SFSPF_9: EPD Mask */ -#define SCU_SFSPF_9_EPUN_Pos 4 /*!< SCU SFSPF_9: EPUN Position */ -#define SCU_SFSPF_9_EPUN_Msk (0x01UL << SCU_SFSPF_9_EPUN_Pos) /*!< SCU SFSPF_9: EPUN Mask */ -#define SCU_SFSPF_9_EHS_Pos 5 /*!< SCU SFSPF_9: EHS Position */ -#define SCU_SFSPF_9_EHS_Msk (0x01UL << SCU_SFSPF_9_EHS_Pos) /*!< SCU SFSPF_9: EHS Mask */ -#define SCU_SFSPF_9_EZI_Pos 6 /*!< SCU SFSPF_9: EZI Position */ -#define SCU_SFSPF_9_EZI_Msk (0x01UL << SCU_SFSPF_9_EZI_Pos) /*!< SCU SFSPF_9: EZI Mask */ -#define SCU_SFSPF_9_EHD_Pos 8 /*!< SCU SFSPF_9: EHD Position */ -#define SCU_SFSPF_9_EHD_Msk (0x03UL << SCU_SFSPF_9_EHD_Pos) /*!< SCU SFSPF_9: EHD Mask */ - -// -------------------------------------- SCU_SFSPF_10 ------------------------------------------ -#define SCU_SFSPF_10_MODE_Pos 0 /*!< SCU SFSPF_10: MODE Position */ -#define SCU_SFSPF_10_MODE_Msk (0x07UL << SCU_SFSPF_10_MODE_Pos) /*!< SCU SFSPF_10: MODE Mask */ -#define SCU_SFSPF_10_EPD_Pos 3 /*!< SCU SFSPF_10: EPD Position */ -#define SCU_SFSPF_10_EPD_Msk (0x01UL << SCU_SFSPF_10_EPD_Pos) /*!< SCU SFSPF_10: EPD Mask */ -#define SCU_SFSPF_10_EPUN_Pos 4 /*!< SCU SFSPF_10: EPUN Position */ -#define SCU_SFSPF_10_EPUN_Msk (0x01UL << SCU_SFSPF_10_EPUN_Pos) /*!< SCU SFSPF_10: EPUN Mask */ -#define SCU_SFSPF_10_EHS_Pos 5 /*!< SCU SFSPF_10: EHS Position */ -#define SCU_SFSPF_10_EHS_Msk (0x01UL << SCU_SFSPF_10_EHS_Pos) /*!< SCU SFSPF_10: EHS Mask */ -#define SCU_SFSPF_10_EZI_Pos 6 /*!< SCU SFSPF_10: EZI Position */ -#define SCU_SFSPF_10_EZI_Msk (0x01UL << SCU_SFSPF_10_EZI_Pos) /*!< SCU SFSPF_10: EZI Mask */ -#define SCU_SFSPF_10_EHD_Pos 8 /*!< SCU SFSPF_10: EHD Position */ -#define SCU_SFSPF_10_EHD_Msk (0x03UL << SCU_SFSPF_10_EHD_Pos) /*!< SCU SFSPF_10: EHD Mask */ - -// -------------------------------------- SCU_SFSPF_11 ------------------------------------------ -#define SCU_SFSPF_11_MODE_Pos 0 /*!< SCU SFSPF_11: MODE Position */ -#define SCU_SFSPF_11_MODE_Msk (0x07UL << SCU_SFSPF_11_MODE_Pos) /*!< SCU SFSPF_11: MODE Mask */ -#define SCU_SFSPF_11_EPD_Pos 3 /*!< SCU SFSPF_11: EPD Position */ -#define SCU_SFSPF_11_EPD_Msk (0x01UL << SCU_SFSPF_11_EPD_Pos) /*!< SCU SFSPF_11: EPD Mask */ -#define SCU_SFSPF_11_EPUN_Pos 4 /*!< SCU SFSPF_11: EPUN Position */ -#define SCU_SFSPF_11_EPUN_Msk (0x01UL << SCU_SFSPF_11_EPUN_Pos) /*!< SCU SFSPF_11: EPUN Mask */ -#define SCU_SFSPF_11_EHS_Pos 5 /*!< SCU SFSPF_11: EHS Position */ -#define SCU_SFSPF_11_EHS_Msk (0x01UL << SCU_SFSPF_11_EHS_Pos) /*!< SCU SFSPF_11: EHS Mask */ -#define SCU_SFSPF_11_EZI_Pos 6 /*!< SCU SFSPF_11: EZI Position */ -#define SCU_SFSPF_11_EZI_Msk (0x01UL << SCU_SFSPF_11_EZI_Pos) /*!< SCU SFSPF_11: EZI Mask */ -#define SCU_SFSPF_11_EHD_Pos 8 /*!< SCU SFSPF_11: EHD Position */ -#define SCU_SFSPF_11_EHD_Msk (0x03UL << SCU_SFSPF_11_EHD_Pos) /*!< SCU SFSPF_11: EHD Mask */ - -// -------------------------------------- SCU_SFSCLK_0 ------------------------------------------ -#define SCU_SFSCLK_0_MODE_Pos 0 /*!< SCU SFSCLK_0: MODE Position */ -#define SCU_SFSCLK_0_MODE_Msk (0x07UL << SCU_SFSCLK_0_MODE_Pos) /*!< SCU SFSCLK_0: MODE Mask */ -#define SCU_SFSCLK_0_EPD_Pos 3 /*!< SCU SFSCLK_0: EPD Position */ -#define SCU_SFSCLK_0_EPD_Msk (0x01UL << SCU_SFSCLK_0_EPD_Pos) /*!< SCU SFSCLK_0: EPD Mask */ -#define SCU_SFSCLK_0_EPUN_Pos 4 /*!< SCU SFSCLK_0: EPUN Position */ -#define SCU_SFSCLK_0_EPUN_Msk (0x01UL << SCU_SFSCLK_0_EPUN_Pos) /*!< SCU SFSCLK_0: EPUN Mask */ -#define SCU_SFSCLK_0_EHS_Pos 5 /*!< SCU SFSCLK_0: EHS Position */ -#define SCU_SFSCLK_0_EHS_Msk (0x01UL << SCU_SFSCLK_0_EHS_Pos) /*!< SCU SFSCLK_0: EHS Mask */ -#define SCU_SFSCLK_0_EZI_Pos 6 /*!< SCU SFSCLK_0: EZI Position */ -#define SCU_SFSCLK_0_EZI_Msk (0x01UL << SCU_SFSCLK_0_EZI_Pos) /*!< SCU SFSCLK_0: EZI Mask */ -#define SCU_SFSCLK_0_EHD_Pos 8 /*!< SCU SFSCLK_0: EHD Position */ -#define SCU_SFSCLK_0_EHD_Msk (0x03UL << SCU_SFSCLK_0_EHD_Pos) /*!< SCU SFSCLK_0: EHD Mask */ - -// -------------------------------------- SCU_SFSCLK_1 ------------------------------------------ -#define SCU_SFSCLK_1_MODE_Pos 0 /*!< SCU SFSCLK_1: MODE Position */ -#define SCU_SFSCLK_1_MODE_Msk (0x07UL << SCU_SFSCLK_1_MODE_Pos) /*!< SCU SFSCLK_1: MODE Mask */ -#define SCU_SFSCLK_1_EPD_Pos 3 /*!< SCU SFSCLK_1: EPD Position */ -#define SCU_SFSCLK_1_EPD_Msk (0x01UL << SCU_SFSCLK_1_EPD_Pos) /*!< SCU SFSCLK_1: EPD Mask */ -#define SCU_SFSCLK_1_EPUN_Pos 4 /*!< SCU SFSCLK_1: EPUN Position */ -#define SCU_SFSCLK_1_EPUN_Msk (0x01UL << SCU_SFSCLK_1_EPUN_Pos) /*!< SCU SFSCLK_1: EPUN Mask */ -#define SCU_SFSCLK_1_EHS_Pos 5 /*!< SCU SFSCLK_1: EHS Position */ -#define SCU_SFSCLK_1_EHS_Msk (0x01UL << SCU_SFSCLK_1_EHS_Pos) /*!< SCU SFSCLK_1: EHS Mask */ -#define SCU_SFSCLK_1_EZI_Pos 6 /*!< SCU SFSCLK_1: EZI Position */ -#define SCU_SFSCLK_1_EZI_Msk (0x01UL << SCU_SFSCLK_1_EZI_Pos) /*!< SCU SFSCLK_1: EZI Mask */ -#define SCU_SFSCLK_1_EHD_Pos 8 /*!< SCU SFSCLK_1: EHD Position */ -#define SCU_SFSCLK_1_EHD_Msk (0x03UL << SCU_SFSCLK_1_EHD_Pos) /*!< SCU SFSCLK_1: EHD Mask */ - -// -------------------------------------- SCU_SFSCLK_2 ------------------------------------------ -#define SCU_SFSCLK_2_MODE_Pos 0 /*!< SCU SFSCLK_2: MODE Position */ -#define SCU_SFSCLK_2_MODE_Msk (0x07UL << SCU_SFSCLK_2_MODE_Pos) /*!< SCU SFSCLK_2: MODE Mask */ -#define SCU_SFSCLK_2_EPD_Pos 3 /*!< SCU SFSCLK_2: EPD Position */ -#define SCU_SFSCLK_2_EPD_Msk (0x01UL << SCU_SFSCLK_2_EPD_Pos) /*!< SCU SFSCLK_2: EPD Mask */ -#define SCU_SFSCLK_2_EPUN_Pos 4 /*!< SCU SFSCLK_2: EPUN Position */ -#define SCU_SFSCLK_2_EPUN_Msk (0x01UL << SCU_SFSCLK_2_EPUN_Pos) /*!< SCU SFSCLK_2: EPUN Mask */ -#define SCU_SFSCLK_2_EHS_Pos 5 /*!< SCU SFSCLK_2: EHS Position */ -#define SCU_SFSCLK_2_EHS_Msk (0x01UL << SCU_SFSCLK_2_EHS_Pos) /*!< SCU SFSCLK_2: EHS Mask */ -#define SCU_SFSCLK_2_EZI_Pos 6 /*!< SCU SFSCLK_2: EZI Position */ -#define SCU_SFSCLK_2_EZI_Msk (0x01UL << SCU_SFSCLK_2_EZI_Pos) /*!< SCU SFSCLK_2: EZI Mask */ -#define SCU_SFSCLK_2_EHD_Pos 8 /*!< SCU SFSCLK_2: EHD Position */ -#define SCU_SFSCLK_2_EHD_Msk (0x03UL << SCU_SFSCLK_2_EHD_Pos) /*!< SCU SFSCLK_2: EHD Mask */ - -// -------------------------------------- SCU_SFSCLK_3 ------------------------------------------ -#define SCU_SFSCLK_3_MODE_Pos 0 /*!< SCU SFSCLK_3: MODE Position */ -#define SCU_SFSCLK_3_MODE_Msk (0x07UL << SCU_SFSCLK_3_MODE_Pos) /*!< SCU SFSCLK_3: MODE Mask */ -#define SCU_SFSCLK_3_EPD_Pos 3 /*!< SCU SFSCLK_3: EPD Position */ -#define SCU_SFSCLK_3_EPD_Msk (0x01UL << SCU_SFSCLK_3_EPD_Pos) /*!< SCU SFSCLK_3: EPD Mask */ -#define SCU_SFSCLK_3_EPUN_Pos 4 /*!< SCU SFSCLK_3: EPUN Position */ -#define SCU_SFSCLK_3_EPUN_Msk (0x01UL << SCU_SFSCLK_3_EPUN_Pos) /*!< SCU SFSCLK_3: EPUN Mask */ -#define SCU_SFSCLK_3_EHS_Pos 5 /*!< SCU SFSCLK_3: EHS Position */ -#define SCU_SFSCLK_3_EHS_Msk (0x01UL << SCU_SFSCLK_3_EHS_Pos) /*!< SCU SFSCLK_3: EHS Mask */ -#define SCU_SFSCLK_3_EZI_Pos 6 /*!< SCU SFSCLK_3: EZI Position */ -#define SCU_SFSCLK_3_EZI_Msk (0x01UL << SCU_SFSCLK_3_EZI_Pos) /*!< SCU SFSCLK_3: EZI Mask */ -#define SCU_SFSCLK_3_EHD_Pos 8 /*!< SCU SFSCLK_3: EHD Position */ -#define SCU_SFSCLK_3_EHD_Msk (0x03UL << SCU_SFSCLK_3_EHD_Pos) /*!< SCU SFSCLK_3: EHD Mask */ - -// --------------------------------------- SCU_SFSUSB ------------------------------------------- -#define SCU_SFSUSB_USB_AIM_Pos 0 /*!< SCU SFSUSB: USB_AIM Position */ -#define SCU_SFSUSB_USB_AIM_Msk (0x01UL << SCU_SFSUSB_USB_AIM_Pos) /*!< SCU SFSUSB: USB_AIM Mask */ -#define SCU_SFSUSB_USB_ESEA_Pos 1 /*!< SCU SFSUSB: USB_ESEA Position */ -#define SCU_SFSUSB_USB_ESEA_Msk (0x01UL << SCU_SFSUSB_USB_ESEA_Pos) /*!< SCU SFSUSB: USB_ESEA Mask */ - -// --------------------------------------- SCU_SFSI2C0 ------------------------------------------ -#define SCU_SFSI2C0_SDA_EHS_Pos 0 /*!< SCU SFSI2C0: SDA_EHS Position */ -#define SCU_SFSI2C0_SDA_EHS_Msk (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos) /*!< SCU SFSI2C0: SDA_EHS Mask */ -#define SCU_SFSI2C0_SCL_EHS_Pos 1 /*!< SCU SFSI2C0: SCL_EHS Position */ -#define SCU_SFSI2C0_SCL_EHS_Msk (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos) /*!< SCU SFSI2C0: SCL_EHS Mask */ -#define SCU_SFSI2C0_SCL_ECS_Pos 2 /*!< SCU SFSI2C0: SCL_ECS Position */ -#define SCU_SFSI2C0_SCL_ECS_Msk (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos) /*!< SCU SFSI2C0: SCL_ECS Mask */ - -// --------------------------------------- SCU_ENAIO0 ------------------------------------------- -#define SCU_ENAIO0_ADC0_0_Pos 0 /*!< SCU ENAIO0: ADC0_0 Position */ -#define SCU_ENAIO0_ADC0_0_Msk (0x01UL << SCU_ENAIO0_ADC0_0_Pos) /*!< SCU ENAIO0: ADC0_0 Mask */ -#define SCU_ENAIO0_ADC0_1_Pos 1 /*!< SCU ENAIO0: ADC0_1 Position */ -#define SCU_ENAIO0_ADC0_1_Msk (0x01UL << SCU_ENAIO0_ADC0_1_Pos) /*!< SCU ENAIO0: ADC0_1 Mask */ -#define SCU_ENAIO0_ADC0_2_Pos 2 /*!< SCU ENAIO0: ADC0_2 Position */ -#define SCU_ENAIO0_ADC0_2_Msk (0x01UL << SCU_ENAIO0_ADC0_2_Pos) /*!< SCU ENAIO0: ADC0_2 Mask */ -#define SCU_ENAIO0_ADC0_3_Pos 3 /*!< SCU ENAIO0: ADC0_3 Position */ -#define SCU_ENAIO0_ADC0_3_Msk (0x01UL << SCU_ENAIO0_ADC0_3_Pos) /*!< SCU ENAIO0: ADC0_3 Mask */ -#define SCU_ENAIO0_ADC0_4_Pos 4 /*!< SCU ENAIO0: ADC0_4 Position */ -#define SCU_ENAIO0_ADC0_4_Msk (0x01UL << SCU_ENAIO0_ADC0_4_Pos) /*!< SCU ENAIO0: ADC0_4 Mask */ -#define SCU_ENAIO0_ADC0_5_Pos 5 /*!< SCU ENAIO0: ADC0_5 Position */ -#define SCU_ENAIO0_ADC0_5_Msk (0x01UL << SCU_ENAIO0_ADC0_5_Pos) /*!< SCU ENAIO0: ADC0_5 Mask */ -#define SCU_ENAIO0_ADC0_6_Pos 6 /*!< SCU ENAIO0: ADC0_6 Position */ -#define SCU_ENAIO0_ADC0_6_Msk (0x01UL << SCU_ENAIO0_ADC0_6_Pos) /*!< SCU ENAIO0: ADC0_6 Mask */ - -// --------------------------------------- SCU_ENAIO1 ------------------------------------------- -#define SCU_ENAIO1_ADC1_0_Pos 0 /*!< SCU ENAIO1: ADC1_0 Position */ -#define SCU_ENAIO1_ADC1_0_Msk (0x01UL << SCU_ENAIO1_ADC1_0_Pos) /*!< SCU ENAIO1: ADC1_0 Mask */ -#define SCU_ENAIO1_ADC1_1_Pos 1 /*!< SCU ENAIO1: ADC1_1 Position */ -#define SCU_ENAIO1_ADC1_1_Msk (0x01UL << SCU_ENAIO1_ADC1_1_Pos) /*!< SCU ENAIO1: ADC1_1 Mask */ -#define SCU_ENAIO1_ADC1_2_Pos 2 /*!< SCU ENAIO1: ADC1_2 Position */ -#define SCU_ENAIO1_ADC1_2_Msk (0x01UL << SCU_ENAIO1_ADC1_2_Pos) /*!< SCU ENAIO1: ADC1_2 Mask */ -#define SCU_ENAIO1_ADC1_3_Pos 3 /*!< SCU ENAIO1: ADC1_3 Position */ -#define SCU_ENAIO1_ADC1_3_Msk (0x01UL << SCU_ENAIO1_ADC1_3_Pos) /*!< SCU ENAIO1: ADC1_3 Mask */ -#define SCU_ENAIO1_ADC1_4_Pos 4 /*!< SCU ENAIO1: ADC1_4 Position */ -#define SCU_ENAIO1_ADC1_4_Msk (0x01UL << SCU_ENAIO1_ADC1_4_Pos) /*!< SCU ENAIO1: ADC1_4 Mask */ -#define SCU_ENAIO1_ADC1_5_Pos 5 /*!< SCU ENAIO1: ADC1_5 Position */ -#define SCU_ENAIO1_ADC1_5_Msk (0x01UL << SCU_ENAIO1_ADC1_5_Pos) /*!< SCU ENAIO1: ADC1_5 Mask */ -#define SCU_ENAIO1_ADC1_6_Pos 6 /*!< SCU ENAIO1: ADC1_6 Position */ -#define SCU_ENAIO1_ADC1_6_Msk (0x01UL << SCU_ENAIO1_ADC1_6_Pos) /*!< SCU ENAIO1: ADC1_6 Mask */ -#define SCU_ENAIO1_ADC1_7_Pos 7 /*!< SCU ENAIO1: ADC1_7 Position */ -#define SCU_ENAIO1_ADC1_7_Msk (0x01UL << SCU_ENAIO1_ADC1_7_Pos) /*!< SCU ENAIO1: ADC1_7 Mask */ - -// --------------------------------------- SCU_ENAIO2 ------------------------------------------- -#define SCU_ENAIO2_DAC_Pos 0 /*!< SCU ENAIO2: DAC Position */ -#define SCU_ENAIO2_DAC_Msk (0x01UL << SCU_ENAIO2_DAC_Pos) /*!< SCU ENAIO2: DAC Mask */ -#define SCU_ENAIO2_BG_Pos 4 /*!< SCU ENAIO2: BG Position */ -#define SCU_ENAIO2_BG_Msk (0x01UL << SCU_ENAIO2_BG_Pos) /*!< SCU ENAIO2: BG Mask */ - -// ------------------------------------- SCU_EMCDELAYCLK ---------------------------------------- -#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos 0 /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */ -#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask */ -#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos 4 /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */ -#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask */ -#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos 8 /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */ -#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask */ -#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos 12 /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */ -#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask */ -#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos 16 /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */ -#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask */ -#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos 20 /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */ -#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask */ -#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos 24 /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */ -#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask */ -#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos 28 /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */ -#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask */ - -// -------------------------------------- SCU_PINTSEL0 ------------------------------------------ -#define SCU_PINTSEL0_INTPIN0_Pos 0 /*!< SCU PINTSEL0: INTPIN0 Position */ -#define SCU_PINTSEL0_INTPIN0_Msk (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos) /*!< SCU PINTSEL0: INTPIN0 Mask */ -#define SCU_PINTSEL0_PORTSEL0_Pos 5 /*!< SCU PINTSEL0: PORTSEL0 Position */ -#define SCU_PINTSEL0_PORTSEL0_Msk (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos) /*!< SCU PINTSEL0: PORTSEL0 Mask */ -#define SCU_PINTSEL0_INTPIN1_Pos 8 /*!< SCU PINTSEL0: INTPIN1 Position */ -#define SCU_PINTSEL0_INTPIN1_Msk (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos) /*!< SCU PINTSEL0: INTPIN1 Mask */ -#define SCU_PINTSEL0_PORTSEL1_Pos 13 /*!< SCU PINTSEL0: PORTSEL1 Position */ -#define SCU_PINTSEL0_PORTSEL1_Msk (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos) /*!< SCU PINTSEL0: PORTSEL1 Mask */ -#define SCU_PINTSEL0_INTPIN2_Pos 16 /*!< SCU PINTSEL0: INTPIN2 Position */ -#define SCU_PINTSEL0_INTPIN2_Msk (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos) /*!< SCU PINTSEL0: INTPIN2 Mask */ -#define SCU_PINTSEL0_PORTSEL2_Pos 21 /*!< SCU PINTSEL0: PORTSEL2 Position */ -#define SCU_PINTSEL0_PORTSEL2_Msk (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos) /*!< SCU PINTSEL0: PORTSEL2 Mask */ -#define SCU_PINTSEL0_INTPIN3_Pos 24 /*!< SCU PINTSEL0: INTPIN3 Position */ -#define SCU_PINTSEL0_INTPIN3_Msk (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos) /*!< SCU PINTSEL0: INTPIN3 Mask */ -#define SCU_PINTSEL0_PORTSEL3_Pos 29 /*!< SCU PINTSEL0: PORTSEL3 Position */ -#define SCU_PINTSEL0_PORTSEL3_Msk (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos) /*!< SCU PINTSEL0: PORTSEL3 Mask */ - -// -------------------------------------- SCU_PINTSEL1 ------------------------------------------ -#define SCU_PINTSEL1_INTPIN4_Pos 0 /*!< SCU PINTSEL1: INTPIN4 Position */ -#define SCU_PINTSEL1_INTPIN4_Msk (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos) /*!< SCU PINTSEL1: INTPIN4 Mask */ -#define SCU_PINTSEL1_PORTSEL4_Pos 5 /*!< SCU PINTSEL1: PORTSEL4 Position */ -#define SCU_PINTSEL1_PORTSEL4_Msk (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos) /*!< SCU PINTSEL1: PORTSEL4 Mask */ -#define SCU_PINTSEL1_INTPIN5_Pos 8 /*!< SCU PINTSEL1: INTPIN5 Position */ -#define SCU_PINTSEL1_INTPIN5_Msk (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos) /*!< SCU PINTSEL1: INTPIN5 Mask */ -#define SCU_PINTSEL1_PORTSEL5_Pos 13 /*!< SCU PINTSEL1: PORTSEL5 Position */ -#define SCU_PINTSEL1_PORTSEL5_Msk (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos) /*!< SCU PINTSEL1: PORTSEL5 Mask */ -#define SCU_PINTSEL1_INTPIN6_Pos 16 /*!< SCU PINTSEL1: INTPIN6 Position */ -#define SCU_PINTSEL1_INTPIN6_Msk (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos) /*!< SCU PINTSEL1: INTPIN6 Mask */ -#define SCU_PINTSEL1_PORTSEL6_Pos 21 /*!< SCU PINTSEL1: PORTSEL6 Position */ -#define SCU_PINTSEL1_PORTSEL6_Msk (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos) /*!< SCU PINTSEL1: PORTSEL6 Mask */ -#define SCU_PINTSEL1_INTPIN7_Pos 24 /*!< SCU PINTSEL1: INTPIN7 Position */ -#define SCU_PINTSEL1_INTPIN7_Msk (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos) /*!< SCU PINTSEL1: INTPIN7 Mask */ -#define SCU_PINTSEL1_PORTSEL7_Pos 29 /*!< SCU PINTSEL1: PORTSEL7 Position */ -#define SCU_PINTSEL1_PORTSEL7_Msk (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos) /*!< SCU PINTSEL1: PORTSEL7 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PIN_INT Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------ GPIO_PIN_INT_ISEL --------------------------------------- -#define GPIO_PIN_INT_ISEL_PMODE0_Pos 0 /*!< GPIO_PIN_INT ISEL: PMODE0 Position */ -#define GPIO_PIN_INT_ISEL_PMODE0_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos) /*!< GPIO_PIN_INT ISEL: PMODE0 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE1_Pos 1 /*!< GPIO_PIN_INT ISEL: PMODE1 Position */ -#define GPIO_PIN_INT_ISEL_PMODE1_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos) /*!< GPIO_PIN_INT ISEL: PMODE1 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE2_Pos 2 /*!< GPIO_PIN_INT ISEL: PMODE2 Position */ -#define GPIO_PIN_INT_ISEL_PMODE2_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos) /*!< GPIO_PIN_INT ISEL: PMODE2 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE3_Pos 3 /*!< GPIO_PIN_INT ISEL: PMODE3 Position */ -#define GPIO_PIN_INT_ISEL_PMODE3_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos) /*!< GPIO_PIN_INT ISEL: PMODE3 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE4_Pos 4 /*!< GPIO_PIN_INT ISEL: PMODE4 Position */ -#define GPIO_PIN_INT_ISEL_PMODE4_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos) /*!< GPIO_PIN_INT ISEL: PMODE4 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE5_Pos 5 /*!< GPIO_PIN_INT ISEL: PMODE5 Position */ -#define GPIO_PIN_INT_ISEL_PMODE5_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos) /*!< GPIO_PIN_INT ISEL: PMODE5 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE6_Pos 6 /*!< GPIO_PIN_INT ISEL: PMODE6 Position */ -#define GPIO_PIN_INT_ISEL_PMODE6_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos) /*!< GPIO_PIN_INT ISEL: PMODE6 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE7_Pos 7 /*!< GPIO_PIN_INT ISEL: PMODE7 Position */ -#define GPIO_PIN_INT_ISEL_PMODE7_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos) /*!< GPIO_PIN_INT ISEL: PMODE7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_IENR --------------------------------------- -#define GPIO_PIN_INT_IENR_ENRL0_Pos 0 /*!< GPIO_PIN_INT IENR: ENRL0 Position */ -#define GPIO_PIN_INT_IENR_ENRL0_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos) /*!< GPIO_PIN_INT IENR: ENRL0 Mask */ -#define GPIO_PIN_INT_IENR_ENRL1_Pos 1 /*!< GPIO_PIN_INT IENR: ENRL1 Position */ -#define GPIO_PIN_INT_IENR_ENRL1_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos) /*!< GPIO_PIN_INT IENR: ENRL1 Mask */ -#define GPIO_PIN_INT_IENR_ENRL2_Pos 2 /*!< GPIO_PIN_INT IENR: ENRL2 Position */ -#define GPIO_PIN_INT_IENR_ENRL2_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos) /*!< GPIO_PIN_INT IENR: ENRL2 Mask */ -#define GPIO_PIN_INT_IENR_ENRL3_Pos 3 /*!< GPIO_PIN_INT IENR: ENRL3 Position */ -#define GPIO_PIN_INT_IENR_ENRL3_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos) /*!< GPIO_PIN_INT IENR: ENRL3 Mask */ -#define GPIO_PIN_INT_IENR_ENRL4_Pos 4 /*!< GPIO_PIN_INT IENR: ENRL4 Position */ -#define GPIO_PIN_INT_IENR_ENRL4_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos) /*!< GPIO_PIN_INT IENR: ENRL4 Mask */ -#define GPIO_PIN_INT_IENR_ENRL5_Pos 5 /*!< GPIO_PIN_INT IENR: ENRL5 Position */ -#define GPIO_PIN_INT_IENR_ENRL5_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos) /*!< GPIO_PIN_INT IENR: ENRL5 Mask */ -#define GPIO_PIN_INT_IENR_ENRL6_Pos 6 /*!< GPIO_PIN_INT IENR: ENRL6 Position */ -#define GPIO_PIN_INT_IENR_ENRL6_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos) /*!< GPIO_PIN_INT IENR: ENRL6 Mask */ -#define GPIO_PIN_INT_IENR_ENRL7_Pos 7 /*!< GPIO_PIN_INT IENR: ENRL7 Position */ -#define GPIO_PIN_INT_IENR_ENRL7_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos) /*!< GPIO_PIN_INT IENR: ENRL7 Mask */ - -// ----------------------------------- GPIO_PIN_INT_SIENR --------------------------------------- -#define GPIO_PIN_INT_SIENR_SETENRL0_Pos 0 /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL0_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL1_Pos 1 /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL1_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL2_Pos 2 /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL2_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL3_Pos 3 /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL3_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL4_Pos 4 /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL4_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL5_Pos 5 /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL5_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL6_Pos 6 /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL6_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL7_Pos 7 /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL7_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask */ - -// ----------------------------------- GPIO_PIN_INT_CIENR --------------------------------------- -#define GPIO_PIN_INT_CIENR_CENRL0_Pos 0 /*!< GPIO_PIN_INT CIENR: CENRL0 Position */ -#define GPIO_PIN_INT_CIENR_CENRL0_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos) /*!< GPIO_PIN_INT CIENR: CENRL0 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL1_Pos 1 /*!< GPIO_PIN_INT CIENR: CENRL1 Position */ -#define GPIO_PIN_INT_CIENR_CENRL1_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos) /*!< GPIO_PIN_INT CIENR: CENRL1 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL2_Pos 2 /*!< GPIO_PIN_INT CIENR: CENRL2 Position */ -#define GPIO_PIN_INT_CIENR_CENRL2_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos) /*!< GPIO_PIN_INT CIENR: CENRL2 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL3_Pos 3 /*!< GPIO_PIN_INT CIENR: CENRL3 Position */ -#define GPIO_PIN_INT_CIENR_CENRL3_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos) /*!< GPIO_PIN_INT CIENR: CENRL3 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL4_Pos 4 /*!< GPIO_PIN_INT CIENR: CENRL4 Position */ -#define GPIO_PIN_INT_CIENR_CENRL4_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos) /*!< GPIO_PIN_INT CIENR: CENRL4 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL5_Pos 5 /*!< GPIO_PIN_INT CIENR: CENRL5 Position */ -#define GPIO_PIN_INT_CIENR_CENRL5_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos) /*!< GPIO_PIN_INT CIENR: CENRL5 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL6_Pos 6 /*!< GPIO_PIN_INT CIENR: CENRL6 Position */ -#define GPIO_PIN_INT_CIENR_CENRL6_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos) /*!< GPIO_PIN_INT CIENR: CENRL6 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL7_Pos 7 /*!< GPIO_PIN_INT CIENR: CENRL7 Position */ -#define GPIO_PIN_INT_CIENR_CENRL7_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos) /*!< GPIO_PIN_INT CIENR: CENRL7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_IENF --------------------------------------- -#define GPIO_PIN_INT_IENF_ENAF0_Pos 0 /*!< GPIO_PIN_INT IENF: ENAF0 Position */ -#define GPIO_PIN_INT_IENF_ENAF0_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos) /*!< GPIO_PIN_INT IENF: ENAF0 Mask */ -#define GPIO_PIN_INT_IENF_ENAF1_Pos 1 /*!< GPIO_PIN_INT IENF: ENAF1 Position */ -#define GPIO_PIN_INT_IENF_ENAF1_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos) /*!< GPIO_PIN_INT IENF: ENAF1 Mask */ -#define GPIO_PIN_INT_IENF_ENAF2_Pos 2 /*!< GPIO_PIN_INT IENF: ENAF2 Position */ -#define GPIO_PIN_INT_IENF_ENAF2_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos) /*!< GPIO_PIN_INT IENF: ENAF2 Mask */ -#define GPIO_PIN_INT_IENF_ENAF3_Pos 3 /*!< GPIO_PIN_INT IENF: ENAF3 Position */ -#define GPIO_PIN_INT_IENF_ENAF3_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos) /*!< GPIO_PIN_INT IENF: ENAF3 Mask */ -#define GPIO_PIN_INT_IENF_ENAF4_Pos 4 /*!< GPIO_PIN_INT IENF: ENAF4 Position */ -#define GPIO_PIN_INT_IENF_ENAF4_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos) /*!< GPIO_PIN_INT IENF: ENAF4 Mask */ -#define GPIO_PIN_INT_IENF_ENAF5_Pos 5 /*!< GPIO_PIN_INT IENF: ENAF5 Position */ -#define GPIO_PIN_INT_IENF_ENAF5_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos) /*!< GPIO_PIN_INT IENF: ENAF5 Mask */ -#define GPIO_PIN_INT_IENF_ENAF6_Pos 6 /*!< GPIO_PIN_INT IENF: ENAF6 Position */ -#define GPIO_PIN_INT_IENF_ENAF6_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos) /*!< GPIO_PIN_INT IENF: ENAF6 Mask */ -#define GPIO_PIN_INT_IENF_ENAF7_Pos 7 /*!< GPIO_PIN_INT IENF: ENAF7 Position */ -#define GPIO_PIN_INT_IENF_ENAF7_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos) /*!< GPIO_PIN_INT IENF: ENAF7 Mask */ - -// ----------------------------------- GPIO_PIN_INT_SIENF --------------------------------------- -#define GPIO_PIN_INT_SIENF_SETENAF0_Pos 0 /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF0_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF1_Pos 1 /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF1_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF2_Pos 2 /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF2_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF3_Pos 3 /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF3_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF4_Pos 4 /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF4_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF5_Pos 5 /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF5_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF6_Pos 6 /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF6_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF7_Pos 7 /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF7_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask */ - -// ----------------------------------- GPIO_PIN_INT_CIENF --------------------------------------- -#define GPIO_PIN_INT_CIENF_CENAF0_Pos 0 /*!< GPIO_PIN_INT CIENF: CENAF0 Position */ -#define GPIO_PIN_INT_CIENF_CENAF0_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos) /*!< GPIO_PIN_INT CIENF: CENAF0 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF1_Pos 1 /*!< GPIO_PIN_INT CIENF: CENAF1 Position */ -#define GPIO_PIN_INT_CIENF_CENAF1_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos) /*!< GPIO_PIN_INT CIENF: CENAF1 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF2_Pos 2 /*!< GPIO_PIN_INT CIENF: CENAF2 Position */ -#define GPIO_PIN_INT_CIENF_CENAF2_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos) /*!< GPIO_PIN_INT CIENF: CENAF2 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF3_Pos 3 /*!< GPIO_PIN_INT CIENF: CENAF3 Position */ -#define GPIO_PIN_INT_CIENF_CENAF3_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos) /*!< GPIO_PIN_INT CIENF: CENAF3 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF4_Pos 4 /*!< GPIO_PIN_INT CIENF: CENAF4 Position */ -#define GPIO_PIN_INT_CIENF_CENAF4_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos) /*!< GPIO_PIN_INT CIENF: CENAF4 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF5_Pos 5 /*!< GPIO_PIN_INT CIENF: CENAF5 Position */ -#define GPIO_PIN_INT_CIENF_CENAF5_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos) /*!< GPIO_PIN_INT CIENF: CENAF5 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF6_Pos 6 /*!< GPIO_PIN_INT CIENF: CENAF6 Position */ -#define GPIO_PIN_INT_CIENF_CENAF6_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos) /*!< GPIO_PIN_INT CIENF: CENAF6 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF7_Pos 7 /*!< GPIO_PIN_INT CIENF: CENAF7 Position */ -#define GPIO_PIN_INT_CIENF_CENAF7_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos) /*!< GPIO_PIN_INT CIENF: CENAF7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_RISE --------------------------------------- -#define GPIO_PIN_INT_RISE_RDET0_Pos 0 /*!< GPIO_PIN_INT RISE: RDET0 Position */ -#define GPIO_PIN_INT_RISE_RDET0_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos) /*!< GPIO_PIN_INT RISE: RDET0 Mask */ -#define GPIO_PIN_INT_RISE_RDET1_Pos 1 /*!< GPIO_PIN_INT RISE: RDET1 Position */ -#define GPIO_PIN_INT_RISE_RDET1_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos) /*!< GPIO_PIN_INT RISE: RDET1 Mask */ -#define GPIO_PIN_INT_RISE_RDET2_Pos 2 /*!< GPIO_PIN_INT RISE: RDET2 Position */ -#define GPIO_PIN_INT_RISE_RDET2_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos) /*!< GPIO_PIN_INT RISE: RDET2 Mask */ -#define GPIO_PIN_INT_RISE_RDET3_Pos 3 /*!< GPIO_PIN_INT RISE: RDET3 Position */ -#define GPIO_PIN_INT_RISE_RDET3_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos) /*!< GPIO_PIN_INT RISE: RDET3 Mask */ -#define GPIO_PIN_INT_RISE_RDET4_Pos 4 /*!< GPIO_PIN_INT RISE: RDET4 Position */ -#define GPIO_PIN_INT_RISE_RDET4_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos) /*!< GPIO_PIN_INT RISE: RDET4 Mask */ -#define GPIO_PIN_INT_RISE_RDET5_Pos 5 /*!< GPIO_PIN_INT RISE: RDET5 Position */ -#define GPIO_PIN_INT_RISE_RDET5_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos) /*!< GPIO_PIN_INT RISE: RDET5 Mask */ -#define GPIO_PIN_INT_RISE_RDET6_Pos 6 /*!< GPIO_PIN_INT RISE: RDET6 Position */ -#define GPIO_PIN_INT_RISE_RDET6_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos) /*!< GPIO_PIN_INT RISE: RDET6 Mask */ -#define GPIO_PIN_INT_RISE_RDET7_Pos 7 /*!< GPIO_PIN_INT RISE: RDET7 Position */ -#define GPIO_PIN_INT_RISE_RDET7_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos) /*!< GPIO_PIN_INT RISE: RDET7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_FALL --------------------------------------- -#define GPIO_PIN_INT_FALL_FDET0_Pos 0 /*!< GPIO_PIN_INT FALL: FDET0 Position */ -#define GPIO_PIN_INT_FALL_FDET0_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos) /*!< GPIO_PIN_INT FALL: FDET0 Mask */ -#define GPIO_PIN_INT_FALL_FDET1_Pos 1 /*!< GPIO_PIN_INT FALL: FDET1 Position */ -#define GPIO_PIN_INT_FALL_FDET1_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos) /*!< GPIO_PIN_INT FALL: FDET1 Mask */ -#define GPIO_PIN_INT_FALL_FDET2_Pos 2 /*!< GPIO_PIN_INT FALL: FDET2 Position */ -#define GPIO_PIN_INT_FALL_FDET2_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos) /*!< GPIO_PIN_INT FALL: FDET2 Mask */ -#define GPIO_PIN_INT_FALL_FDET3_Pos 3 /*!< GPIO_PIN_INT FALL: FDET3 Position */ -#define GPIO_PIN_INT_FALL_FDET3_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos) /*!< GPIO_PIN_INT FALL: FDET3 Mask */ -#define GPIO_PIN_INT_FALL_FDET4_Pos 4 /*!< GPIO_PIN_INT FALL: FDET4 Position */ -#define GPIO_PIN_INT_FALL_FDET4_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos) /*!< GPIO_PIN_INT FALL: FDET4 Mask */ -#define GPIO_PIN_INT_FALL_FDET5_Pos 5 /*!< GPIO_PIN_INT FALL: FDET5 Position */ -#define GPIO_PIN_INT_FALL_FDET5_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos) /*!< GPIO_PIN_INT FALL: FDET5 Mask */ -#define GPIO_PIN_INT_FALL_FDET6_Pos 6 /*!< GPIO_PIN_INT FALL: FDET6 Position */ -#define GPIO_PIN_INT_FALL_FDET6_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos) /*!< GPIO_PIN_INT FALL: FDET6 Mask */ -#define GPIO_PIN_INT_FALL_FDET7_Pos 7 /*!< GPIO_PIN_INT FALL: FDET7 Position */ -#define GPIO_PIN_INT_FALL_FDET7_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos) /*!< GPIO_PIN_INT FALL: FDET7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_IST ---------------------------------------- -#define GPIO_PIN_INT_IST_PSTAT0_Pos 0 /*!< GPIO_PIN_INT IST: PSTAT0 Position */ -#define GPIO_PIN_INT_IST_PSTAT0_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos) /*!< GPIO_PIN_INT IST: PSTAT0 Mask */ -#define GPIO_PIN_INT_IST_PSTAT1_Pos 1 /*!< GPIO_PIN_INT IST: PSTAT1 Position */ -#define GPIO_PIN_INT_IST_PSTAT1_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos) /*!< GPIO_PIN_INT IST: PSTAT1 Mask */ -#define GPIO_PIN_INT_IST_PSTAT2_Pos 2 /*!< GPIO_PIN_INT IST: PSTAT2 Position */ -#define GPIO_PIN_INT_IST_PSTAT2_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos) /*!< GPIO_PIN_INT IST: PSTAT2 Mask */ -#define GPIO_PIN_INT_IST_PSTAT3_Pos 3 /*!< GPIO_PIN_INT IST: PSTAT3 Position */ -#define GPIO_PIN_INT_IST_PSTAT3_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos) /*!< GPIO_PIN_INT IST: PSTAT3 Mask */ -#define GPIO_PIN_INT_IST_PSTAT4_Pos 4 /*!< GPIO_PIN_INT IST: PSTAT4 Position */ -#define GPIO_PIN_INT_IST_PSTAT4_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos) /*!< GPIO_PIN_INT IST: PSTAT4 Mask */ -#define GPIO_PIN_INT_IST_PSTAT5_Pos 5 /*!< GPIO_PIN_INT IST: PSTAT5 Position */ -#define GPIO_PIN_INT_IST_PSTAT5_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos) /*!< GPIO_PIN_INT IST: PSTAT5 Mask */ -#define GPIO_PIN_INT_IST_PSTAT6_Pos 6 /*!< GPIO_PIN_INT IST: PSTAT6 Position */ -#define GPIO_PIN_INT_IST_PSTAT6_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos) /*!< GPIO_PIN_INT IST: PSTAT6 Mask */ -#define GPIO_PIN_INT_IST_PSTAT7_Pos 7 /*!< GPIO_PIN_INT IST: PSTAT7 Position */ -#define GPIO_PIN_INT_IST_PSTAT7_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos) /*!< GPIO_PIN_INT IST: PSTAT7 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INTn Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------- GPIO_GROUP_INTn_CTRL -------------------------------------- -#define GPIO_GROUP_INTn_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INTn CTRL: INT Position */ -#define GPIO_GROUP_INTn_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos) /*!< GPIO_GROUP_INTn CTRL: INT Mask */ -#define GPIO_GROUP_INTn_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INTn CTRL: COMB Position */ -#define GPIO_GROUP_INTn_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos) /*!< GPIO_GROUP_INTn CTRL: COMB Mask */ -#define GPIO_GROUP_INTn_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INTn CTRL: TRIG Position */ -#define GPIO_GROUP_INTn_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INTn CTRL: TRIG Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL0 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL1 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL2 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL3 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL4 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL5 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL6 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL7 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA0 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA1 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA2 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA3 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA4 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA5 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA6 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA7 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INT1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------- GPIO_GROUP_INT1_CTRL -------------------------------------- -#define GPIO_GROUP_INT1_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT1 CTRL: INT Position */ -#define GPIO_GROUP_INT1_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos) /*!< GPIO_GROUP_INT1 CTRL: INT Mask */ -#define GPIO_GROUP_INT1_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT1 CTRL: COMB Position */ -#define GPIO_GROUP_INT1_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT1 CTRL: COMB Mask */ -#define GPIO_GROUP_INT1_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */ -#define GPIO_GROUP_INT1_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL0 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL1 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL2 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL3 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL4 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL5 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL6 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL7 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA0 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA1 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA2 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA3 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA4 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA5 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA6 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA7 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- MCPWM Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- MCPWM_CON ------------------------------------------- -#define MCPWM_CON_RUN0_Pos 0 /*!< MCPWM CON: RUN0 Position */ -#define MCPWM_CON_RUN0_Msk (0x01UL << MCPWM_CON_RUN0_Pos) /*!< MCPWM CON: RUN0 Mask */ -#define MCPWM_CON_CENTER0_Pos 1 /*!< MCPWM CON: CENTER0 Position */ -#define MCPWM_CON_CENTER0_Msk (0x01UL << MCPWM_CON_CENTER0_Pos) /*!< MCPWM CON: CENTER0 Mask */ -#define MCPWM_CON_POLA0_Pos 2 /*!< MCPWM CON: POLA0 Position */ -#define MCPWM_CON_POLA0_Msk (0x01UL << MCPWM_CON_POLA0_Pos) /*!< MCPWM CON: POLA0 Mask */ -#define MCPWM_CON_DTE0_Pos 3 /*!< MCPWM CON: DTE0 Position */ -#define MCPWM_CON_DTE0_Msk (0x01UL << MCPWM_CON_DTE0_Pos) /*!< MCPWM CON: DTE0 Mask */ -#define MCPWM_CON_DISUP0_Pos 4 /*!< MCPWM CON: DISUP0 Position */ -#define MCPWM_CON_DISUP0_Msk (0x01UL << MCPWM_CON_DISUP0_Pos) /*!< MCPWM CON: DISUP0 Mask */ -#define MCPWM_CON_RUN1_Pos 8 /*!< MCPWM CON: RUN1 Position */ -#define MCPWM_CON_RUN1_Msk (0x01UL << MCPWM_CON_RUN1_Pos) /*!< MCPWM CON: RUN1 Mask */ -#define MCPWM_CON_CENTER1_Pos 9 /*!< MCPWM CON: CENTER1 Position */ -#define MCPWM_CON_CENTER1_Msk (0x01UL << MCPWM_CON_CENTER1_Pos) /*!< MCPWM CON: CENTER1 Mask */ -#define MCPWM_CON_POLA1_Pos 10 /*!< MCPWM CON: POLA1 Position */ -#define MCPWM_CON_POLA1_Msk (0x01UL << MCPWM_CON_POLA1_Pos) /*!< MCPWM CON: POLA1 Mask */ -#define MCPWM_CON_DTE1_Pos 11 /*!< MCPWM CON: DTE1 Position */ -#define MCPWM_CON_DTE1_Msk (0x01UL << MCPWM_CON_DTE1_Pos) /*!< MCPWM CON: DTE1 Mask */ -#define MCPWM_CON_DISUP1_Pos 12 /*!< MCPWM CON: DISUP1 Position */ -#define MCPWM_CON_DISUP1_Msk (0x01UL << MCPWM_CON_DISUP1_Pos) /*!< MCPWM CON: DISUP1 Mask */ -#define MCPWM_CON_RUN2_Pos 16 /*!< MCPWM CON: RUN2 Position */ -#define MCPWM_CON_RUN2_Msk (0x01UL << MCPWM_CON_RUN2_Pos) /*!< MCPWM CON: RUN2 Mask */ -#define MCPWM_CON_CENTER2_Pos 17 /*!< MCPWM CON: CENTER2 Position */ -#define MCPWM_CON_CENTER2_Msk (0x01UL << MCPWM_CON_CENTER2_Pos) /*!< MCPWM CON: CENTER2 Mask */ -#define MCPWM_CON_POLA2_Pos 18 /*!< MCPWM CON: POLA2 Position */ -#define MCPWM_CON_POLA2_Msk (0x01UL << MCPWM_CON_POLA2_Pos) /*!< MCPWM CON: POLA2 Mask */ -#define MCPWM_CON_DTE2_Pos 19 /*!< MCPWM CON: DTE2 Position */ -#define MCPWM_CON_DTE2_Msk (0x01UL << MCPWM_CON_DTE2_Pos) /*!< MCPWM CON: DTE2 Mask */ -#define MCPWM_CON_DISUP2_Pos 20 /*!< MCPWM CON: DISUP2 Position */ -#define MCPWM_CON_DISUP2_Msk (0x01UL << MCPWM_CON_DISUP2_Pos) /*!< MCPWM CON: DISUP2 Mask */ -#define MCPWM_CON_INVBDC_Pos 29 /*!< MCPWM CON: INVBDC Position */ -#define MCPWM_CON_INVBDC_Msk (0x01UL << MCPWM_CON_INVBDC_Pos) /*!< MCPWM CON: INVBDC Mask */ -#define MCPWM_CON_ACMODE_Pos 30 /*!< MCPWM CON: ACMODE Position */ -#define MCPWM_CON_ACMODE_Msk (0x01UL << MCPWM_CON_ACMODE_Pos) /*!< MCPWM CON: ACMODE Mask */ -#define MCPWM_CON_DCMODE_Pos 31 /*!< MCPWM CON: DCMODE Position */ -#define MCPWM_CON_DCMODE_Msk (0x01UL << MCPWM_CON_DCMODE_Pos) /*!< MCPWM CON: DCMODE Mask */ - -// -------------------------------------- MCPWM_CON_SET ----------------------------------------- -#define MCPWM_CON_SET_RUN0_SET_Pos 0 /*!< MCPWM CON_SET: RUN0_SET Position */ -#define MCPWM_CON_SET_RUN0_SET_Msk (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos) /*!< MCPWM CON_SET: RUN0_SET Mask */ -#define MCPWM_CON_SET_CENTER0_SET_Pos 1 /*!< MCPWM CON_SET: CENTER0_SET Position */ -#define MCPWM_CON_SET_CENTER0_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos) /*!< MCPWM CON_SET: CENTER0_SET Mask */ -#define MCPWM_CON_SET_POLA0_SET_Pos 2 /*!< MCPWM CON_SET: POLA0_SET Position */ -#define MCPWM_CON_SET_POLA0_SET_Msk (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos) /*!< MCPWM CON_SET: POLA0_SET Mask */ -#define MCPWM_CON_SET_DTE0_SET_Pos 3 /*!< MCPWM CON_SET: DTE0_SET Position */ -#define MCPWM_CON_SET_DTE0_SET_Msk (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos) /*!< MCPWM CON_SET: DTE0_SET Mask */ -#define MCPWM_CON_SET_DISUP0_SET_Pos 4 /*!< MCPWM CON_SET: DISUP0_SET Position */ -#define MCPWM_CON_SET_DISUP0_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos) /*!< MCPWM CON_SET: DISUP0_SET Mask */ -#define MCPWM_CON_SET_RUN1_SET_Pos 8 /*!< MCPWM CON_SET: RUN1_SET Position */ -#define MCPWM_CON_SET_RUN1_SET_Msk (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos) /*!< MCPWM CON_SET: RUN1_SET Mask */ -#define MCPWM_CON_SET_CENTER1_SET_Pos 9 /*!< MCPWM CON_SET: CENTER1_SET Position */ -#define MCPWM_CON_SET_CENTER1_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos) /*!< MCPWM CON_SET: CENTER1_SET Mask */ -#define MCPWM_CON_SET_POLA1_SET_Pos 10 /*!< MCPWM CON_SET: POLA1_SET Position */ -#define MCPWM_CON_SET_POLA1_SET_Msk (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos) /*!< MCPWM CON_SET: POLA1_SET Mask */ -#define MCPWM_CON_SET_DTE1_SET_Pos 11 /*!< MCPWM CON_SET: DTE1_SET Position */ -#define MCPWM_CON_SET_DTE1_SET_Msk (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos) /*!< MCPWM CON_SET: DTE1_SET Mask */ -#define MCPWM_CON_SET_DISUP1_SET_Pos 12 /*!< MCPWM CON_SET: DISUP1_SET Position */ -#define MCPWM_CON_SET_DISUP1_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos) /*!< MCPWM CON_SET: DISUP1_SET Mask */ -#define MCPWM_CON_SET_RUN2_SET_Pos 16 /*!< MCPWM CON_SET: RUN2_SET Position */ -#define MCPWM_CON_SET_RUN2_SET_Msk (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos) /*!< MCPWM CON_SET: RUN2_SET Mask */ -#define MCPWM_CON_SET_CENTER2_SET_Pos 17 /*!< MCPWM CON_SET: CENTER2_SET Position */ -#define MCPWM_CON_SET_CENTER2_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos) /*!< MCPWM CON_SET: CENTER2_SET Mask */ -#define MCPWM_CON_SET_POLA2_SET_Pos 18 /*!< MCPWM CON_SET: POLA2_SET Position */ -#define MCPWM_CON_SET_POLA2_SET_Msk (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos) /*!< MCPWM CON_SET: POLA2_SET Mask */ -#define MCPWM_CON_SET_DTE2_SET_Pos 19 /*!< MCPWM CON_SET: DTE2_SET Position */ -#define MCPWM_CON_SET_DTE2_SET_Msk (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos) /*!< MCPWM CON_SET: DTE2_SET Mask */ -#define MCPWM_CON_SET_DISUP2_SET_Pos 20 /*!< MCPWM CON_SET: DISUP2_SET Position */ -#define MCPWM_CON_SET_DISUP2_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos) /*!< MCPWM CON_SET: DISUP2_SET Mask */ -#define MCPWM_CON_SET_INVBDC_SET_Pos 29 /*!< MCPWM CON_SET: INVBDC_SET Position */ -#define MCPWM_CON_SET_INVBDC_SET_Msk (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos) /*!< MCPWM CON_SET: INVBDC_SET Mask */ -#define MCPWM_CON_SET_ACMODE_SET_Pos 30 /*!< MCPWM CON_SET: ACMODE_SET Position */ -#define MCPWM_CON_SET_ACMODE_SET_Msk (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos) /*!< MCPWM CON_SET: ACMODE_SET Mask */ -#define MCPWM_CON_SET_DCMODE_SET_Pos 31 /*!< MCPWM CON_SET: DCMODE_SET Position */ -#define MCPWM_CON_SET_DCMODE_SET_Msk (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos) /*!< MCPWM CON_SET: DCMODE_SET Mask */ - -// -------------------------------------- MCPWM_CON_CLR ----------------------------------------- -#define MCPWM_CON_CLR_RUN0_CLR_Pos 0 /*!< MCPWM CON_CLR: RUN0_CLR Position */ -#define MCPWM_CON_CLR_RUN0_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos) /*!< MCPWM CON_CLR: RUN0_CLR Mask */ -#define MCPWM_CON_CLR_CENTER0_CLR_Pos 1 /*!< MCPWM CON_CLR: CENTER0_CLR Position */ -#define MCPWM_CON_CLR_CENTER0_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos) /*!< MCPWM CON_CLR: CENTER0_CLR Mask */ -#define MCPWM_CON_CLR_POLA0_CLR_Pos 2 /*!< MCPWM CON_CLR: POLA0_CLR Position */ -#define MCPWM_CON_CLR_POLA0_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos) /*!< MCPWM CON_CLR: POLA0_CLR Mask */ -#define MCPWM_CON_CLR_DTE0_CLR_Pos 3 /*!< MCPWM CON_CLR: DTE0_CLR Position */ -#define MCPWM_CON_CLR_DTE0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos) /*!< MCPWM CON_CLR: DTE0_CLR Mask */ -#define MCPWM_CON_CLR_DISUP0_CLR_Pos 4 /*!< MCPWM CON_CLR: DISUP0_CLR Position */ -#define MCPWM_CON_CLR_DISUP0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos) /*!< MCPWM CON_CLR: DISUP0_CLR Mask */ -#define MCPWM_CON_CLR_RUN1_CLR_Pos 8 /*!< MCPWM CON_CLR: RUN1_CLR Position */ -#define MCPWM_CON_CLR_RUN1_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos) /*!< MCPWM CON_CLR: RUN1_CLR Mask */ -#define MCPWM_CON_CLR_CENTER1_CLR_Pos 9 /*!< MCPWM CON_CLR: CENTER1_CLR Position */ -#define MCPWM_CON_CLR_CENTER1_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos) /*!< MCPWM CON_CLR: CENTER1_CLR Mask */ -#define MCPWM_CON_CLR_POLA1_CLR_Pos 10 /*!< MCPWM CON_CLR: POLA1_CLR Position */ -#define MCPWM_CON_CLR_POLA1_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos) /*!< MCPWM CON_CLR: POLA1_CLR Mask */ -#define MCPWM_CON_CLR_DTE1_CLR_Pos 11 /*!< MCPWM CON_CLR: DTE1_CLR Position */ -#define MCPWM_CON_CLR_DTE1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos) /*!< MCPWM CON_CLR: DTE1_CLR Mask */ -#define MCPWM_CON_CLR_DISUP1_CLR_Pos 12 /*!< MCPWM CON_CLR: DISUP1_CLR Position */ -#define MCPWM_CON_CLR_DISUP1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos) /*!< MCPWM CON_CLR: DISUP1_CLR Mask */ -#define MCPWM_CON_CLR_RUN2_CLR_Pos 16 /*!< MCPWM CON_CLR: RUN2_CLR Position */ -#define MCPWM_CON_CLR_RUN2_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos) /*!< MCPWM CON_CLR: RUN2_CLR Mask */ -#define MCPWM_CON_CLR_CENTER2_CLR_Pos 17 /*!< MCPWM CON_CLR: CENTER2_CLR Position */ -#define MCPWM_CON_CLR_CENTER2_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos) /*!< MCPWM CON_CLR: CENTER2_CLR Mask */ -#define MCPWM_CON_CLR_POLA2_CLR_Pos 18 /*!< MCPWM CON_CLR: POLA2_CLR Position */ -#define MCPWM_CON_CLR_POLA2_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos) /*!< MCPWM CON_CLR: POLA2_CLR Mask */ -#define MCPWM_CON_CLR_DTE2_CLR_Pos 19 /*!< MCPWM CON_CLR: DTE2_CLR Position */ -#define MCPWM_CON_CLR_DTE2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos) /*!< MCPWM CON_CLR: DTE2_CLR Mask */ -#define MCPWM_CON_CLR_DISUP2_CLR_Pos 20 /*!< MCPWM CON_CLR: DISUP2_CLR Position */ -#define MCPWM_CON_CLR_DISUP2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos) /*!< MCPWM CON_CLR: DISUP2_CLR Mask */ -#define MCPWM_CON_CLR_INVBDC_CLR_Pos 29 /*!< MCPWM CON_CLR: INVBDC_CLR Position */ -#define MCPWM_CON_CLR_INVBDC_CLR_Msk (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos) /*!< MCPWM CON_CLR: INVBDC_CLR Mask */ -#define MCPWM_CON_CLR_ACMOD_CLR_Pos 30 /*!< MCPWM CON_CLR: ACMOD_CLR Position */ -#define MCPWM_CON_CLR_ACMOD_CLR_Msk (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos) /*!< MCPWM CON_CLR: ACMOD_CLR Mask */ -#define MCPWM_CON_CLR_DCMODE_CLR_Pos 31 /*!< MCPWM CON_CLR: DCMODE_CLR Position */ -#define MCPWM_CON_CLR_DCMODE_CLR_Msk (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos) /*!< MCPWM CON_CLR: DCMODE_CLR Mask */ - -// -------------------------------------- MCPWM_CAPCON ------------------------------------------ -#define MCPWM_CAPCON_CAP0MCI0_RE_Pos 0 /*!< MCPWM CAPCON: CAP0MCI0_RE Position */ -#define MCPWM_CAPCON_CAP0MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_RE Mask */ -#define MCPWM_CAPCON_CAP0MCI0_FE_Pos 1 /*!< MCPWM CAPCON: CAP0MCI0_FE Position */ -#define MCPWM_CAPCON_CAP0MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_FE Mask */ -#define MCPWM_CAPCON_CAP0MCI1_RE_Pos 2 /*!< MCPWM CAPCON: CAP0MCI1_RE Position */ -#define MCPWM_CAPCON_CAP0MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_RE Mask */ -#define MCPWM_CAPCON_CAP0MCI1_FE_Pos 3 /*!< MCPWM CAPCON: CAP0MCI1_FE Position */ -#define MCPWM_CAPCON_CAP0MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_FE Mask */ -#define MCPWM_CAPCON_CAP0MCI2_RE_Pos 4 /*!< MCPWM CAPCON: CAP0MCI2_RE Position */ -#define MCPWM_CAPCON_CAP0MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_RE Mask */ -#define MCPWM_CAPCON_CAP0MCI2_FE_Pos 5 /*!< MCPWM CAPCON: CAP0MCI2_FE Position */ -#define MCPWM_CAPCON_CAP0MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_FE Mask */ -#define MCPWM_CAPCON_CAP1MCI0_RE_Pos 6 /*!< MCPWM CAPCON: CAP1MCI0_RE Position */ -#define MCPWM_CAPCON_CAP1MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_RE Mask */ -#define MCPWM_CAPCON_CAP1MCI0_FE_Pos 7 /*!< MCPWM CAPCON: CAP1MCI0_FE Position */ -#define MCPWM_CAPCON_CAP1MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_FE Mask */ -#define MCPWM_CAPCON_CAP1MCI1_RE_Pos 8 /*!< MCPWM CAPCON: CAP1MCI1_RE Position */ -#define MCPWM_CAPCON_CAP1MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_RE Mask */ -#define MCPWM_CAPCON_CAP1MCI1_FE_Pos 9 /*!< MCPWM CAPCON: CAP1MCI1_FE Position */ -#define MCPWM_CAPCON_CAP1MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_FE Mask */ -#define MCPWM_CAPCON_CAP1MCI2_RE_Pos 10 /*!< MCPWM CAPCON: CAP1MCI2_RE Position */ -#define MCPWM_CAPCON_CAP1MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_RE Mask */ -#define MCPWM_CAPCON_CAP1MCI2_FE_Pos 11 /*!< MCPWM CAPCON: CAP1MCI2_FE Position */ -#define MCPWM_CAPCON_CAP1MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_FE Mask */ -#define MCPWM_CAPCON_CAP2MCI0_RE_Pos 12 /*!< MCPWM CAPCON: CAP2MCI0_RE Position */ -#define MCPWM_CAPCON_CAP2MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_RE Mask */ -#define MCPWM_CAPCON_CAP2MCI0_FE_Pos 13 /*!< MCPWM CAPCON: CAP2MCI0_FE Position */ -#define MCPWM_CAPCON_CAP2MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_FE Mask */ -#define MCPWM_CAPCON_CAP2MCI1_RE_Pos 14 /*!< MCPWM CAPCON: CAP2MCI1_RE Position */ -#define MCPWM_CAPCON_CAP2MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_RE Mask */ -#define MCPWM_CAPCON_CAP2MCI1_FE_Pos 15 /*!< MCPWM CAPCON: CAP2MCI1_FE Position */ -#define MCPWM_CAPCON_CAP2MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_FE Mask */ -#define MCPWM_CAPCON_CAP2MCI2_RE_Pos 16 /*!< MCPWM CAPCON: CAP2MCI2_RE Position */ -#define MCPWM_CAPCON_CAP2MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_RE Mask */ -#define MCPWM_CAPCON_CAP2MCI2_FE_Pos 17 /*!< MCPWM CAPCON: CAP2MCI2_FE Position */ -#define MCPWM_CAPCON_CAP2MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_FE Mask */ -#define MCPWM_CAPCON_RT0_Pos 18 /*!< MCPWM CAPCON: RT0 Position */ -#define MCPWM_CAPCON_RT0_Msk (0x01UL << MCPWM_CAPCON_RT0_Pos) /*!< MCPWM CAPCON: RT0 Mask */ -#define MCPWM_CAPCON_RT1_Pos 19 /*!< MCPWM CAPCON: RT1 Position */ -#define MCPWM_CAPCON_RT1_Msk (0x01UL << MCPWM_CAPCON_RT1_Pos) /*!< MCPWM CAPCON: RT1 Mask */ -#define MCPWM_CAPCON_RT2_Pos 20 /*!< MCPWM CAPCON: RT2 Position */ -#define MCPWM_CAPCON_RT2_Msk (0x01UL << MCPWM_CAPCON_RT2_Pos) /*!< MCPWM CAPCON: RT2 Mask */ -#define MCPWM_CAPCON_HNFCAP0_Pos 21 /*!< MCPWM CAPCON: HNFCAP0 Position */ -#define MCPWM_CAPCON_HNFCAP0_Msk (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos) /*!< MCPWM CAPCON: HNFCAP0 Mask */ -#define MCPWM_CAPCON_HNFCAP1_Pos 22 /*!< MCPWM CAPCON: HNFCAP1 Position */ -#define MCPWM_CAPCON_HNFCAP1_Msk (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos) /*!< MCPWM CAPCON: HNFCAP1 Mask */ -#define MCPWM_CAPCON_HNFCAP2_Pos 23 /*!< MCPWM CAPCON: HNFCAP2 Position */ -#define MCPWM_CAPCON_HNFCAP2_Msk (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos) /*!< MCPWM CAPCON: HNFCAP2 Mask */ - -// ------------------------------------ MCPWM_CAPCON_SET ---------------------------------------- -#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos 0 /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos 1 /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos 2 /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos 3 /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos 4 /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos 5 /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos 6 /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos 7 /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos 8 /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos 9 /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos 10 /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos 11 /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos 12 /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos 13 /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos 14 /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos 15 /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos 16 /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos 17 /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */ -#define MCPWM_CAPCON_SET_RT0_SET_Pos 18 /*!< MCPWM CAPCON_SET: RT0_SET Position */ -#define MCPWM_CAPCON_SET_RT0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos) /*!< MCPWM CAPCON_SET: RT0_SET Mask */ -#define MCPWM_CAPCON_SET_RT1_SET_Pos 19 /*!< MCPWM CAPCON_SET: RT1_SET Position */ -#define MCPWM_CAPCON_SET_RT1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos) /*!< MCPWM CAPCON_SET: RT1_SET Mask */ -#define MCPWM_CAPCON_SET_RT2_SET_Pos 20 /*!< MCPWM CAPCON_SET: RT2_SET Position */ -#define MCPWM_CAPCON_SET_RT2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos) /*!< MCPWM CAPCON_SET: RT2_SET Mask */ -#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos 21 /*!< MCPWM CAPCON_SET: HNFCAP0_SET Position */ -#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP0_SET Mask */ -#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos 22 /*!< MCPWM CAPCON_SET: HNFCAP1_SET Position */ -#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP1_SET Mask */ -#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos 23 /*!< MCPWM CAPCON_SET: HNFCAP2_SET Position */ -#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP2_SET Mask */ - -// ------------------------------------ MCPWM_CAPCON_CLR ---------------------------------------- -#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos 0 /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos 1 /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos 2 /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos 3 /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos 4 /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos 5 /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos 6 /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos 7 /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos 8 /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos 9 /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos 10 /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos 11 /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos 12 /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos 13 /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos 14 /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos 15 /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos 16 /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos 17 /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_RT0_CLR_Pos 18 /*!< MCPWM CAPCON_CLR: RT0_CLR Position */ -#define MCPWM_CAPCON_CLR_RT0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT0_CLR Mask */ -#define MCPWM_CAPCON_CLR_RT1_CLR_Pos 19 /*!< MCPWM CAPCON_CLR: RT1_CLR Position */ -#define MCPWM_CAPCON_CLR_RT1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT1_CLR Mask */ -#define MCPWM_CAPCON_CLR_RT2_CLR_Pos 20 /*!< MCPWM CAPCON_CLR: RT2_CLR Position */ -#define MCPWM_CAPCON_CLR_RT2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT2_CLR Mask */ -#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos 21 /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Position */ -#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Mask */ -#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos 22 /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Position */ -#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Mask */ -#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos 23 /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Position */ -#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Mask */ - -// ---------------------------------------- MCPWM_TC0 ------------------------------------------- -#define MCPWM_TC0_MCTC_Pos 0 /*!< MCPWM TC0: MCTC Position */ -#define MCPWM_TC0_MCTC_Msk (0xffffffffUL << MCPWM_TC0_MCTC_Pos) /*!< MCPWM TC0: MCTC Mask */ - -// ---------------------------------------- MCPWM_TC1 ------------------------------------------- -#define MCPWM_TC1_MCTC_Pos 0 /*!< MCPWM TC1: MCTC Position */ -#define MCPWM_TC1_MCTC_Msk (0xffffffffUL << MCPWM_TC1_MCTC_Pos) /*!< MCPWM TC1: MCTC Mask */ - -// ---------------------------------------- MCPWM_TC2 ------------------------------------------- -#define MCPWM_TC2_MCTC_Pos 0 /*!< MCPWM TC2: MCTC Position */ -#define MCPWM_TC2_MCTC_Msk (0xffffffffUL << MCPWM_TC2_MCTC_Pos) /*!< MCPWM TC2: MCTC Mask */ - -// --------------------------------------- MCPWM_LIM0 ------------------------------------------- -#define MCPWM_LIM0_MCLIM_Pos 0 /*!< MCPWM LIM0: MCLIM Position */ -#define MCPWM_LIM0_MCLIM_Msk (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos) /*!< MCPWM LIM0: MCLIM Mask */ - -// --------------------------------------- MCPWM_LIM1 ------------------------------------------- -#define MCPWM_LIM1_MCLIM_Pos 0 /*!< MCPWM LIM1: MCLIM Position */ -#define MCPWM_LIM1_MCLIM_Msk (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos) /*!< MCPWM LIM1: MCLIM Mask */ - -// --------------------------------------- MCPWM_LIM2 ------------------------------------------- -#define MCPWM_LIM2_MCLIM_Pos 0 /*!< MCPWM LIM2: MCLIM Position */ -#define MCPWM_LIM2_MCLIM_Msk (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos) /*!< MCPWM LIM2: MCLIM Mask */ - -// --------------------------------------- MCPWM_MAT0 ------------------------------------------- -#define MCPWM_MAT0_MCMAT_Pos 0 /*!< MCPWM MAT0: MCMAT Position */ -#define MCPWM_MAT0_MCMAT_Msk (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos) /*!< MCPWM MAT0: MCMAT Mask */ - -// --------------------------------------- MCPWM_MAT1 ------------------------------------------- -#define MCPWM_MAT1_MCMAT_Pos 0 /*!< MCPWM MAT1: MCMAT Position */ -#define MCPWM_MAT1_MCMAT_Msk (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos) /*!< MCPWM MAT1: MCMAT Mask */ - -// --------------------------------------- MCPWM_MAT2 ------------------------------------------- -#define MCPWM_MAT2_MCMAT_Pos 0 /*!< MCPWM MAT2: MCMAT Position */ -#define MCPWM_MAT2_MCMAT_Msk (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos) /*!< MCPWM MAT2: MCMAT Mask */ - -// ---------------------------------------- MCPWM_DT -------------------------------------------- -#define MCPWM_DT_DT0_Pos 0 /*!< MCPWM DT: DT0 Position */ -#define MCPWM_DT_DT0_Msk (0x000003ffUL << MCPWM_DT_DT0_Pos) /*!< MCPWM DT: DT0 Mask */ -#define MCPWM_DT_DT1_Pos 10 /*!< MCPWM DT: DT1 Position */ -#define MCPWM_DT_DT1_Msk (0x000003ffUL << MCPWM_DT_DT1_Pos) /*!< MCPWM DT: DT1 Mask */ -#define MCPWM_DT_DT2_Pos 20 /*!< MCPWM DT: DT2 Position */ -#define MCPWM_DT_DT2_Msk (0x000003ffUL << MCPWM_DT_DT2_Pos) /*!< MCPWM DT: DT2 Mask */ - -// ---------------------------------------- MCPWM_CCP ------------------------------------------- -#define MCPWM_CCP_CCPA0_Pos 0 /*!< MCPWM CCP: CCPA0 Position */ -#define MCPWM_CCP_CCPA0_Msk (0x01UL << MCPWM_CCP_CCPA0_Pos) /*!< MCPWM CCP: CCPA0 Mask */ -#define MCPWM_CCP_CCPB0_Pos 1 /*!< MCPWM CCP: CCPB0 Position */ -#define MCPWM_CCP_CCPB0_Msk (0x01UL << MCPWM_CCP_CCPB0_Pos) /*!< MCPWM CCP: CCPB0 Mask */ -#define MCPWM_CCP_CCPA1_Pos 2 /*!< MCPWM CCP: CCPA1 Position */ -#define MCPWM_CCP_CCPA1_Msk (0x01UL << MCPWM_CCP_CCPA1_Pos) /*!< MCPWM CCP: CCPA1 Mask */ -#define MCPWM_CCP_CCPB1_Pos 3 /*!< MCPWM CCP: CCPB1 Position */ -#define MCPWM_CCP_CCPB1_Msk (0x01UL << MCPWM_CCP_CCPB1_Pos) /*!< MCPWM CCP: CCPB1 Mask */ -#define MCPWM_CCP_CCPA2_Pos 4 /*!< MCPWM CCP: CCPA2 Position */ -#define MCPWM_CCP_CCPA2_Msk (0x01UL << MCPWM_CCP_CCPA2_Pos) /*!< MCPWM CCP: CCPA2 Mask */ -#define MCPWM_CCP_CCPB2_Pos 5 /*!< MCPWM CCP: CCPB2 Position */ -#define MCPWM_CCP_CCPB2_Msk (0x01UL << MCPWM_CCP_CCPB2_Pos) /*!< MCPWM CCP: CCPB2 Mask */ - -// --------------------------------------- MCPWM_CAP0 ------------------------------------------- -#define MCPWM_CAP0_CAP_Pos 0 /*!< MCPWM CAP0: CAP Position */ -#define MCPWM_CAP0_CAP_Msk (0xffffffffUL << MCPWM_CAP0_CAP_Pos) /*!< MCPWM CAP0: CAP Mask */ - -// --------------------------------------- MCPWM_CAP1 ------------------------------------------- -#define MCPWM_CAP1_CAP_Pos 0 /*!< MCPWM CAP1: CAP Position */ -#define MCPWM_CAP1_CAP_Msk (0xffffffffUL << MCPWM_CAP1_CAP_Pos) /*!< MCPWM CAP1: CAP Mask */ - -// --------------------------------------- MCPWM_CAP2 ------------------------------------------- -#define MCPWM_CAP2_CAP_Pos 0 /*!< MCPWM CAP2: CAP Position */ -#define MCPWM_CAP2_CAP_Msk (0xffffffffUL << MCPWM_CAP2_CAP_Pos) /*!< MCPWM CAP2: CAP Mask */ - -// --------------------------------------- MCPWM_INTEN ------------------------------------------ -#define MCPWM_INTEN_ILIM0_Pos 0 /*!< MCPWM INTEN: ILIM0 Position */ -#define MCPWM_INTEN_ILIM0_Msk (0x01UL << MCPWM_INTEN_ILIM0_Pos) /*!< MCPWM INTEN: ILIM0 Mask */ -#define MCPWM_INTEN_IMAT0_Pos 1 /*!< MCPWM INTEN: IMAT0 Position */ -#define MCPWM_INTEN_IMAT0_Msk (0x01UL << MCPWM_INTEN_IMAT0_Pos) /*!< MCPWM INTEN: IMAT0 Mask */ -#define MCPWM_INTEN_ICAP0_Pos 2 /*!< MCPWM INTEN: ICAP0 Position */ -#define MCPWM_INTEN_ICAP0_Msk (0x01UL << MCPWM_INTEN_ICAP0_Pos) /*!< MCPWM INTEN: ICAP0 Mask */ -#define MCPWM_INTEN_ILIM1_Pos 4 /*!< MCPWM INTEN: ILIM1 Position */ -#define MCPWM_INTEN_ILIM1_Msk (0x01UL << MCPWM_INTEN_ILIM1_Pos) /*!< MCPWM INTEN: ILIM1 Mask */ -#define MCPWM_INTEN_IMAT1_Pos 5 /*!< MCPWM INTEN: IMAT1 Position */ -#define MCPWM_INTEN_IMAT1_Msk (0x01UL << MCPWM_INTEN_IMAT1_Pos) /*!< MCPWM INTEN: IMAT1 Mask */ -#define MCPWM_INTEN_ICAP1_Pos 6 /*!< MCPWM INTEN: ICAP1 Position */ -#define MCPWM_INTEN_ICAP1_Msk (0x01UL << MCPWM_INTEN_ICAP1_Pos) /*!< MCPWM INTEN: ICAP1 Mask */ -#define MCPWM_INTEN_ILIM2_Pos 8 /*!< MCPWM INTEN: ILIM2 Position */ -#define MCPWM_INTEN_ILIM2_Msk (0x01UL << MCPWM_INTEN_ILIM2_Pos) /*!< MCPWM INTEN: ILIM2 Mask */ -#define MCPWM_INTEN_IMAT2_Pos 9 /*!< MCPWM INTEN: IMAT2 Position */ -#define MCPWM_INTEN_IMAT2_Msk (0x01UL << MCPWM_INTEN_IMAT2_Pos) /*!< MCPWM INTEN: IMAT2 Mask */ -#define MCPWM_INTEN_ICAP2_Pos 10 /*!< MCPWM INTEN: ICAP2 Position */ -#define MCPWM_INTEN_ICAP2_Msk (0x01UL << MCPWM_INTEN_ICAP2_Pos) /*!< MCPWM INTEN: ICAP2 Mask */ -#define MCPWM_INTEN_ABORT_Pos 15 /*!< MCPWM INTEN: ABORT Position */ -#define MCPWM_INTEN_ABORT_Msk (0x01UL << MCPWM_INTEN_ABORT_Pos) /*!< MCPWM INTEN: ABORT Mask */ - -// ------------------------------------- MCPWM_INTEN_SET ---------------------------------------- -#define MCPWM_INTEN_SET_ILIM0_SET_Pos 0 /*!< MCPWM INTEN_SET: ILIM0_SET Position */ -#define MCPWM_INTEN_SET_ILIM0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos) /*!< MCPWM INTEN_SET: ILIM0_SET Mask */ -#define MCPWM_INTEN_SET_IMAT0_SET_Pos 1 /*!< MCPWM INTEN_SET: IMAT0_SET Position */ -#define MCPWM_INTEN_SET_IMAT0_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos) /*!< MCPWM INTEN_SET: IMAT0_SET Mask */ -#define MCPWM_INTEN_SET_ICAP0_SET_Pos 2 /*!< MCPWM INTEN_SET: ICAP0_SET Position */ -#define MCPWM_INTEN_SET_ICAP0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos) /*!< MCPWM INTEN_SET: ICAP0_SET Mask */ -#define MCPWM_INTEN_SET_ILIM1_SET_Pos 4 /*!< MCPWM INTEN_SET: ILIM1_SET Position */ -#define MCPWM_INTEN_SET_ILIM1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos) /*!< MCPWM INTEN_SET: ILIM1_SET Mask */ -#define MCPWM_INTEN_SET_IMAT1_SET_Pos 5 /*!< MCPWM INTEN_SET: IMAT1_SET Position */ -#define MCPWM_INTEN_SET_IMAT1_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos) /*!< MCPWM INTEN_SET: IMAT1_SET Mask */ -#define MCPWM_INTEN_SET_ICAP1_SET_Pos 6 /*!< MCPWM INTEN_SET: ICAP1_SET Position */ -#define MCPWM_INTEN_SET_ICAP1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos) /*!< MCPWM INTEN_SET: ICAP1_SET Mask */ -#define MCPWM_INTEN_SET_ILIM2_SET_Pos 9 /*!< MCPWM INTEN_SET: ILIM2_SET Position */ -#define MCPWM_INTEN_SET_ILIM2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos) /*!< MCPWM INTEN_SET: ILIM2_SET Mask */ -#define MCPWM_INTEN_SET_IMAT2_SET_Pos 10 /*!< MCPWM INTEN_SET: IMAT2_SET Position */ -#define MCPWM_INTEN_SET_IMAT2_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos) /*!< MCPWM INTEN_SET: IMAT2_SET Mask */ -#define MCPWM_INTEN_SET_ICAP2_SET_Pos 11 /*!< MCPWM INTEN_SET: ICAP2_SET Position */ -#define MCPWM_INTEN_SET_ICAP2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos) /*!< MCPWM INTEN_SET: ICAP2_SET Mask */ -#define MCPWM_INTEN_SET_ABORT_SET_Pos 15 /*!< MCPWM INTEN_SET: ABORT_SET Position */ -#define MCPWM_INTEN_SET_ABORT_SET_Msk (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos) /*!< MCPWM INTEN_SET: ABORT_SET Mask */ - -// ------------------------------------- MCPWM_INTEN_CLR ---------------------------------------- -#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos 0 /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */ -#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask */ -#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos 1 /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */ -#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask */ -#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos 2 /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */ -#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask */ -#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos 4 /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */ -#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask */ -#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos 5 /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */ -#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask */ -#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos 6 /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */ -#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask */ -#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos 8 /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */ -#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask */ -#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos 9 /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */ -#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask */ -#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos 10 /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */ -#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask */ -#define MCPWM_INTEN_CLR_ABORT_CLR_Pos 15 /*!< MCPWM INTEN_CLR: ABORT_CLR Position */ -#define MCPWM_INTEN_CLR_ABORT_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos) /*!< MCPWM INTEN_CLR: ABORT_CLR Mask */ - -// -------------------------------------- MCPWM_CNTCON ------------------------------------------ -#define MCPWM_CNTCON_TC0MCI0_RE_Pos 0 /*!< MCPWM CNTCON: TC0MCI0_RE Position */ -#define MCPWM_CNTCON_TC0MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos) /*!< MCPWM CNTCON: TC0MCI0_RE Mask */ -#define MCPWM_CNTCON_TC0MCI0_FE_Pos 1 /*!< MCPWM CNTCON: TC0MCI0_FE Position */ -#define MCPWM_CNTCON_TC0MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos) /*!< MCPWM CNTCON: TC0MCI0_FE Mask */ -#define MCPWM_CNTCON_TC0MCI1_RE_Pos 2 /*!< MCPWM CNTCON: TC0MCI1_RE Position */ -#define MCPWM_CNTCON_TC0MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos) /*!< MCPWM CNTCON: TC0MCI1_RE Mask */ -#define MCPWM_CNTCON_TC0MCI1_FE_Pos 3 /*!< MCPWM CNTCON: TC0MCI1_FE Position */ -#define MCPWM_CNTCON_TC0MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos) /*!< MCPWM CNTCON: TC0MCI1_FE Mask */ -#define MCPWM_CNTCON_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON: TC0MCI2_RE Position */ -#define MCPWM_CNTCON_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON: TC0MCI2_RE Mask */ -#define MCPWM_CNTCON_TC0MCI2_FE_Pos 5 /*!< MCPWM CNTCON: TC0MCI2_FE Position */ -#define MCPWM_CNTCON_TC0MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos) /*!< MCPWM CNTCON: TC0MCI2_FE Mask */ -#define MCPWM_CNTCON_TC1MCI0_RE_Pos 6 /*!< MCPWM CNTCON: TC1MCI0_RE Position */ -#define MCPWM_CNTCON_TC1MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos) /*!< MCPWM CNTCON: TC1MCI0_RE Mask */ -#define MCPWM_CNTCON_TC1MCI0_FE_Pos 7 /*!< MCPWM CNTCON: TC1MCI0_FE Position */ -#define MCPWM_CNTCON_TC1MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos) /*!< MCPWM CNTCON: TC1MCI0_FE Mask */ -#define MCPWM_CNTCON_TC1MCI1_RE_Pos 8 /*!< MCPWM CNTCON: TC1MCI1_RE Position */ -#define MCPWM_CNTCON_TC1MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos) /*!< MCPWM CNTCON: TC1MCI1_RE Mask */ -#define MCPWM_CNTCON_TC1MCI1_FE_Pos 9 /*!< MCPWM CNTCON: TC1MCI1_FE Position */ -#define MCPWM_CNTCON_TC1MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos) /*!< MCPWM CNTCON: TC1MCI1_FE Mask */ -#define MCPWM_CNTCON_TC1MCI2_RE_Pos 10 /*!< MCPWM CNTCON: TC1MCI2_RE Position */ -#define MCPWM_CNTCON_TC1MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos) /*!< MCPWM CNTCON: TC1MCI2_RE Mask */ -#define MCPWM_CNTCON_TC1MCI2_FE_Pos 11 /*!< MCPWM CNTCON: TC1MCI2_FE Position */ -#define MCPWM_CNTCON_TC1MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos) /*!< MCPWM CNTCON: TC1MCI2_FE Mask */ -#define MCPWM_CNTCON_TC2MCI0_RE_Pos 12 /*!< MCPWM CNTCON: TC2MCI0_RE Position */ -#define MCPWM_CNTCON_TC2MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos) /*!< MCPWM CNTCON: TC2MCI0_RE Mask */ -#define MCPWM_CNTCON_TC2MCI0_FE_Pos 13 /*!< MCPWM CNTCON: TC2MCI0_FE Position */ -#define MCPWM_CNTCON_TC2MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos) /*!< MCPWM CNTCON: TC2MCI0_FE Mask */ -#define MCPWM_CNTCON_TC2MCI1_RE_Pos 14 /*!< MCPWM CNTCON: TC2MCI1_RE Position */ -#define MCPWM_CNTCON_TC2MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos) /*!< MCPWM CNTCON: TC2MCI1_RE Mask */ -#define MCPWM_CNTCON_TC2MCI1_FE_Pos 15 /*!< MCPWM CNTCON: TC2MCI1_FE Position */ -#define MCPWM_CNTCON_TC2MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos) /*!< MCPWM CNTCON: TC2MCI1_FE Mask */ -#define MCPWM_CNTCON_TC2MCI2_RE_Pos 16 /*!< MCPWM CNTCON: TC2MCI2_RE Position */ -#define MCPWM_CNTCON_TC2MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos) /*!< MCPWM CNTCON: TC2MCI2_RE Mask */ -#define MCPWM_CNTCON_TC2MCI2_FE_Pos 17 /*!< MCPWM CNTCON: TC2MCI2_FE Position */ -#define MCPWM_CNTCON_TC2MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos) /*!< MCPWM CNTCON: TC2MCI2_FE Mask */ -#define MCPWM_CNTCON_CNTR0_Pos 29 /*!< MCPWM CNTCON: CNTR0 Position */ -#define MCPWM_CNTCON_CNTR0_Msk (0x01UL << MCPWM_CNTCON_CNTR0_Pos) /*!< MCPWM CNTCON: CNTR0 Mask */ -#define MCPWM_CNTCON_CNTR1_Pos 30 /*!< MCPWM CNTCON: CNTR1 Position */ -#define MCPWM_CNTCON_CNTR1_Msk (0x01UL << MCPWM_CNTCON_CNTR1_Pos) /*!< MCPWM CNTCON: CNTR1 Mask */ -#define MCPWM_CNTCON_CNTR2_Pos 31 /*!< MCPWM CNTCON: CNTR2 Position */ -#define MCPWM_CNTCON_CNTR2_Msk (0x01UL << MCPWM_CNTCON_CNTR2_Pos) /*!< MCPWM CNTCON: CNTR2 Mask */ - -// ------------------------------------ MCPWM_CNTCON_SET ---------------------------------------- -#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos 0 /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos 1 /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos 2 /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos 3 /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos 4 /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos 5 /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos 6 /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos 7 /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos 8 /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos 9 /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos 10 /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos 11 /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos 12 /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos 13 /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos 14 /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos 15 /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos 16 /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos 17 /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */ -#define MCPWM_CNTCON_SET_CNTR0_SET_Pos 29 /*!< MCPWM CNTCON_SET: CNTR0_SET Position */ -#define MCPWM_CNTCON_SET_CNTR0_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR0_SET Mask */ -#define MCPWM_CNTCON_SET_CNTR1_SET_Pos 30 /*!< MCPWM CNTCON_SET: CNTR1_SET Position */ -#define MCPWM_CNTCON_SET_CNTR1_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR1_SET Mask */ -#define MCPWM_CNTCON_SET_CNTR2_SET_Pos 31 /*!< MCPWM CNTCON_SET: CNTR2_SET Position */ -#define MCPWM_CNTCON_SET_CNTR2_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR2_SET Mask */ - -// ------------------------------------ MCPWM_CNTCON_CLR ---------------------------------------- -#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos 0 /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos 1 /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos 2 /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos 3 /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */ -#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos 5 /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos 6 /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos 7 /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos 8 /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos 9 /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos 10 /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos 11 /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos 12 /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos 13 /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos 14 /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos 15 /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos 16 /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos 17 /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos 29 /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */ -#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask */ -#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos 30 /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */ -#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask */ -#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos 31 /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */ -#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask */ - -// --------------------------------------- MCPWM_INTF ------------------------------------------- -#define MCPWM_INTF_ILIM0_F_Pos 0 /*!< MCPWM INTF: ILIM0_F Position */ -#define MCPWM_INTF_ILIM0_F_Msk (0x01UL << MCPWM_INTF_ILIM0_F_Pos) /*!< MCPWM INTF: ILIM0_F Mask */ -#define MCPWM_INTF_IMAT0_F_Pos 1 /*!< MCPWM INTF: IMAT0_F Position */ -#define MCPWM_INTF_IMAT0_F_Msk (0x01UL << MCPWM_INTF_IMAT0_F_Pos) /*!< MCPWM INTF: IMAT0_F Mask */ -#define MCPWM_INTF_ICAP0_F_Pos 2 /*!< MCPWM INTF: ICAP0_F Position */ -#define MCPWM_INTF_ICAP0_F_Msk (0x01UL << MCPWM_INTF_ICAP0_F_Pos) /*!< MCPWM INTF: ICAP0_F Mask */ -#define MCPWM_INTF_ILIM1_F_Pos 4 /*!< MCPWM INTF: ILIM1_F Position */ -#define MCPWM_INTF_ILIM1_F_Msk (0x01UL << MCPWM_INTF_ILIM1_F_Pos) /*!< MCPWM INTF: ILIM1_F Mask */ -#define MCPWM_INTF_IMAT1_F_Pos 5 /*!< MCPWM INTF: IMAT1_F Position */ -#define MCPWM_INTF_IMAT1_F_Msk (0x01UL << MCPWM_INTF_IMAT1_F_Pos) /*!< MCPWM INTF: IMAT1_F Mask */ -#define MCPWM_INTF_ICAP1_F_Pos 6 /*!< MCPWM INTF: ICAP1_F Position */ -#define MCPWM_INTF_ICAP1_F_Msk (0x01UL << MCPWM_INTF_ICAP1_F_Pos) /*!< MCPWM INTF: ICAP1_F Mask */ -#define MCPWM_INTF_ILIM2_F_Pos 8 /*!< MCPWM INTF: ILIM2_F Position */ -#define MCPWM_INTF_ILIM2_F_Msk (0x01UL << MCPWM_INTF_ILIM2_F_Pos) /*!< MCPWM INTF: ILIM2_F Mask */ -#define MCPWM_INTF_IMAT2_F_Pos 9 /*!< MCPWM INTF: IMAT2_F Position */ -#define MCPWM_INTF_IMAT2_F_Msk (0x01UL << MCPWM_INTF_IMAT2_F_Pos) /*!< MCPWM INTF: IMAT2_F Mask */ -#define MCPWM_INTF_ICAP2_F_Pos 10 /*!< MCPWM INTF: ICAP2_F Position */ -#define MCPWM_INTF_ICAP2_F_Msk (0x01UL << MCPWM_INTF_ICAP2_F_Pos) /*!< MCPWM INTF: ICAP2_F Mask */ -#define MCPWM_INTF_ABORT_F_Pos 15 /*!< MCPWM INTF: ABORT_F Position */ -#define MCPWM_INTF_ABORT_F_Msk (0x01UL << MCPWM_INTF_ABORT_F_Pos) /*!< MCPWM INTF: ABORT_F Mask */ - -// ------------------------------------- MCPWM_INTF_SET ----------------------------------------- -#define MCPWM_INTF_SET_ILIM0_F_SET_Pos 0 /*!< MCPWM INTF_SET: ILIM0_F_SET Position */ -#define MCPWM_INTF_SET_ILIM0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM0_F_SET Mask */ -#define MCPWM_INTF_SET_IMAT0_F_SET_Pos 1 /*!< MCPWM INTF_SET: IMAT0_F_SET Position */ -#define MCPWM_INTF_SET_IMAT0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT0_F_SET Mask */ -#define MCPWM_INTF_SET_ICAP0_F_SET_Pos 2 /*!< MCPWM INTF_SET: ICAP0_F_SET Position */ -#define MCPWM_INTF_SET_ICAP0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP0_F_SET Mask */ -#define MCPWM_INTF_SET_ILIM1_F_SET_Pos 4 /*!< MCPWM INTF_SET: ILIM1_F_SET Position */ -#define MCPWM_INTF_SET_ILIM1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM1_F_SET Mask */ -#define MCPWM_INTF_SET_IMAT1_F_SET_Pos 5 /*!< MCPWM INTF_SET: IMAT1_F_SET Position */ -#define MCPWM_INTF_SET_IMAT1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT1_F_SET Mask */ -#define MCPWM_INTF_SET_ICAP1_F_SET_Pos 6 /*!< MCPWM INTF_SET: ICAP1_F_SET Position */ -#define MCPWM_INTF_SET_ICAP1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP1_F_SET Mask */ -#define MCPWM_INTF_SET_ILIM2_F_SET_Pos 8 /*!< MCPWM INTF_SET: ILIM2_F_SET Position */ -#define MCPWM_INTF_SET_ILIM2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM2_F_SET Mask */ -#define MCPWM_INTF_SET_IMAT2_F_SET_Pos 9 /*!< MCPWM INTF_SET: IMAT2_F_SET Position */ -#define MCPWM_INTF_SET_IMAT2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT2_F_SET Mask */ -#define MCPWM_INTF_SET_ICAP2_F_SET_Pos 10 /*!< MCPWM INTF_SET: ICAP2_F_SET Position */ -#define MCPWM_INTF_SET_ICAP2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP2_F_SET Mask */ -#define MCPWM_INTF_SET_ABORT_F_SET_Pos 15 /*!< MCPWM INTF_SET: ABORT_F_SET Position */ -#define MCPWM_INTF_SET_ABORT_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos) /*!< MCPWM INTF_SET: ABORT_F_SET Mask */ - -// ------------------------------------- MCPWM_INTF_CLR ----------------------------------------- -#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos 0 /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */ -#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask */ -#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos 1 /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */ -#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask */ -#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos 2 /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */ -#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask */ -#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos 4 /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */ -#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask */ -#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos 5 /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */ -#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask */ -#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos 6 /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */ -#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask */ -#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos 8 /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */ -#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask */ -#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos 9 /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */ -#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask */ -#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos 10 /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */ -#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask */ -#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos 15 /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */ -#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos) /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask */ - -// -------------------------------------- MCPWM_CAP_CLR ----------------------------------------- -#define MCPWM_CAP_CLR_CAP_CLR0_Pos 0 /*!< MCPWM CAP_CLR: CAP_CLR0 Position */ -#define MCPWM_CAP_CLR_CAP_CLR0_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos) /*!< MCPWM CAP_CLR: CAP_CLR0 Mask */ -#define MCPWM_CAP_CLR_CAP_CLR1_Pos 1 /*!< MCPWM CAP_CLR: CAP_CLR1 Position */ -#define MCPWM_CAP_CLR_CAP_CLR1_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos) /*!< MCPWM CAP_CLR: CAP_CLR1 Mask */ -#define MCPWM_CAP_CLR_CAP_CLR2_Pos 2 /*!< MCPWM CAP_CLR: CAP_CLR2 Position */ -#define MCPWM_CAP_CLR_CAP_CLR2_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos) /*!< MCPWM CAP_CLR: CAP_CLR2 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- I2C0_CONSET ------------------------------------------ -#define I2C0_CONSET_AA_Pos 2 /*!< I2C0 CONSET: AA Position */ -#define I2C0_CONSET_AA_Msk (0x01UL << I2C0_CONSET_AA_Pos) /*!< I2C0 CONSET: AA Mask */ -#define I2C0_CONSET_SI_Pos 3 /*!< I2C0 CONSET: SI Position */ -#define I2C0_CONSET_SI_Msk (0x01UL << I2C0_CONSET_SI_Pos) /*!< I2C0 CONSET: SI Mask */ -#define I2C0_CONSET_STO_Pos 4 /*!< I2C0 CONSET: STO Position */ -#define I2C0_CONSET_STO_Msk (0x01UL << I2C0_CONSET_STO_Pos) /*!< I2C0 CONSET: STO Mask */ -#define I2C0_CONSET_STA_Pos 5 /*!< I2C0 CONSET: STA Position */ -#define I2C0_CONSET_STA_Msk (0x01UL << I2C0_CONSET_STA_Pos) /*!< I2C0 CONSET: STA Mask */ -#define I2C0_CONSET_I2EN_Pos 6 /*!< I2C0 CONSET: I2EN Position */ -#define I2C0_CONSET_I2EN_Msk (0x01UL << I2C0_CONSET_I2EN_Pos) /*!< I2C0 CONSET: I2EN Mask */ - -// ---------------------------------------- I2C0_STAT ------------------------------------------- -#define I2C0_STAT_Status_Pos 3 /*!< I2C0 STAT: Status Position */ -#define I2C0_STAT_Status_Msk (0x1fUL << I2C0_STAT_Status_Pos) /*!< I2C0 STAT: Status Mask */ - -// ---------------------------------------- I2C0_DAT -------------------------------------------- -#define I2C0_DAT_Data_Pos 0 /*!< I2C0 DAT: Data Position */ -#define I2C0_DAT_Data_Msk (0x000000ffUL << I2C0_DAT_Data_Pos) /*!< I2C0 DAT: Data Mask */ - -// ---------------------------------------- I2C0_ADR0 ------------------------------------------- -#define I2C0_ADR0_GC_Pos 0 /*!< I2C0 ADR0: GC Position */ -#define I2C0_ADR0_GC_Msk (0x01UL << I2C0_ADR0_GC_Pos) /*!< I2C0 ADR0: GC Mask */ -#define I2C0_ADR0_Address_Pos 1 /*!< I2C0 ADR0: Address Position */ -#define I2C0_ADR0_Address_Msk (0x7fUL << I2C0_ADR0_Address_Pos) /*!< I2C0 ADR0: Address Mask */ - -// ---------------------------------------- I2C0_SCLH ------------------------------------------- -#define I2C0_SCLH_SCLH_Pos 0 /*!< I2C0 SCLH: SCLH Position */ -#define I2C0_SCLH_SCLH_Msk (0x0000ffffUL << I2C0_SCLH_SCLH_Pos) /*!< I2C0 SCLH: SCLH Mask */ - -// ---------------------------------------- I2C0_SCLL ------------------------------------------- -#define I2C0_SCLL_SCLL_Pos 0 /*!< I2C0 SCLL: SCLL Position */ -#define I2C0_SCLL_SCLL_Msk (0x0000ffffUL << I2C0_SCLL_SCLL_Pos) /*!< I2C0 SCLL: SCLL Mask */ - -// --------------------------------------- I2C0_CONCLR ------------------------------------------ -#define I2C0_CONCLR_AAC_Pos 2 /*!< I2C0 CONCLR: AAC Position */ -#define I2C0_CONCLR_AAC_Msk (0x01UL << I2C0_CONCLR_AAC_Pos) /*!< I2C0 CONCLR: AAC Mask */ -#define I2C0_CONCLR_SIC_Pos 3 /*!< I2C0 CONCLR: SIC Position */ -#define I2C0_CONCLR_SIC_Msk (0x01UL << I2C0_CONCLR_SIC_Pos) /*!< I2C0 CONCLR: SIC Mask */ -#define I2C0_CONCLR_STAC_Pos 5 /*!< I2C0 CONCLR: STAC Position */ -#define I2C0_CONCLR_STAC_Msk (0x01UL << I2C0_CONCLR_STAC_Pos) /*!< I2C0 CONCLR: STAC Mask */ -#define I2C0_CONCLR_I2ENC_Pos 6 /*!< I2C0 CONCLR: I2ENC Position */ -#define I2C0_CONCLR_I2ENC_Msk (0x01UL << I2C0_CONCLR_I2ENC_Pos) /*!< I2C0 CONCLR: I2ENC Mask */ - -// --------------------------------------- I2C0_MMCTRL ------------------------------------------ -#define I2C0_MMCTRL_MM_ENA_Pos 0 /*!< I2C0 MMCTRL: MM_ENA Position */ -#define I2C0_MMCTRL_MM_ENA_Msk (0x01UL << I2C0_MMCTRL_MM_ENA_Pos) /*!< I2C0 MMCTRL: MM_ENA Mask */ -#define I2C0_MMCTRL_ENA_SCL_Pos 1 /*!< I2C0 MMCTRL: ENA_SCL Position */ -#define I2C0_MMCTRL_ENA_SCL_Msk (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos) /*!< I2C0 MMCTRL: ENA_SCL Mask */ -#define I2C0_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C0 MMCTRL: MATCH_ALL Position */ -#define I2C0_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos) /*!< I2C0 MMCTRL: MATCH_ALL Mask */ - -// ---------------------------------------- I2C0_ADR1 ------------------------------------------- -#define I2C0_ADR1_GC_Pos 0 /*!< I2C0 ADR1: GC Position */ -#define I2C0_ADR1_GC_Msk (0x01UL << I2C0_ADR1_GC_Pos) /*!< I2C0 ADR1: GC Mask */ -#define I2C0_ADR1_Address_Pos 1 /*!< I2C0 ADR1: Address Position */ -#define I2C0_ADR1_Address_Msk (0x7fUL << I2C0_ADR1_Address_Pos) /*!< I2C0 ADR1: Address Mask */ - -// ---------------------------------------- I2C0_ADR2 ------------------------------------------- -#define I2C0_ADR2_GC_Pos 0 /*!< I2C0 ADR2: GC Position */ -#define I2C0_ADR2_GC_Msk (0x01UL << I2C0_ADR2_GC_Pos) /*!< I2C0 ADR2: GC Mask */ -#define I2C0_ADR2_Address_Pos 1 /*!< I2C0 ADR2: Address Position */ -#define I2C0_ADR2_Address_Msk (0x7fUL << I2C0_ADR2_Address_Pos) /*!< I2C0 ADR2: Address Mask */ - -// ---------------------------------------- I2C0_ADR3 ------------------------------------------- -#define I2C0_ADR3_GC_Pos 0 /*!< I2C0 ADR3: GC Position */ -#define I2C0_ADR3_GC_Msk (0x01UL << I2C0_ADR3_GC_Pos) /*!< I2C0 ADR3: GC Mask */ -#define I2C0_ADR3_Address_Pos 1 /*!< I2C0 ADR3: Address Position */ -#define I2C0_ADR3_Address_Msk (0x7fUL << I2C0_ADR3_Address_Pos) /*!< I2C0 ADR3: Address Mask */ - -// ------------------------------------ I2C0_DATA_BUFFER ---------------------------------------- -#define I2C0_DATA_BUFFER_Data_Pos 0 /*!< I2C0 DATA_BUFFER: Data Position */ -#define I2C0_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos) /*!< I2C0 DATA_BUFFER: Data Mask */ - -// --------------------------------------- I2C0_MASK0 ------------------------------------------- -#define I2C0_MASK0_MASK_Pos 1 /*!< I2C0 MASK0: MASK Position */ -#define I2C0_MASK0_MASK_Msk (0x7fUL << I2C0_MASK0_MASK_Pos) /*!< I2C0 MASK0: MASK Mask */ - -// --------------------------------------- I2C0_MASK1 ------------------------------------------- -#define I2C0_MASK1_MASK_Pos 1 /*!< I2C0 MASK1: MASK Position */ -#define I2C0_MASK1_MASK_Msk (0x7fUL << I2C0_MASK1_MASK_Pos) /*!< I2C0 MASK1: MASK Mask */ - -// --------------------------------------- I2C0_MASK2 ------------------------------------------- -#define I2C0_MASK2_MASK_Pos 1 /*!< I2C0 MASK2: MASK Position */ -#define I2C0_MASK2_MASK_Msk (0x7fUL << I2C0_MASK2_MASK_Pos) /*!< I2C0 MASK2: MASK Mask */ - -// --------------------------------------- I2C0_MASK3 ------------------------------------------- -#define I2C0_MASK3_MASK_Pos 1 /*!< I2C0 MASK3: MASK Position */ -#define I2C0_MASK3_MASK_Msk (0x7fUL << I2C0_MASK3_MASK_Pos) /*!< I2C0 MASK3: MASK Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- I2C1_CONSET ------------------------------------------ -#define I2C1_CONSET_AA_Pos 2 /*!< I2C1 CONSET: AA Position */ -#define I2C1_CONSET_AA_Msk (0x01UL << I2C1_CONSET_AA_Pos) /*!< I2C1 CONSET: AA Mask */ -#define I2C1_CONSET_SI_Pos 3 /*!< I2C1 CONSET: SI Position */ -#define I2C1_CONSET_SI_Msk (0x01UL << I2C1_CONSET_SI_Pos) /*!< I2C1 CONSET: SI Mask */ -#define I2C1_CONSET_STO_Pos 4 /*!< I2C1 CONSET: STO Position */ -#define I2C1_CONSET_STO_Msk (0x01UL << I2C1_CONSET_STO_Pos) /*!< I2C1 CONSET: STO Mask */ -#define I2C1_CONSET_STA_Pos 5 /*!< I2C1 CONSET: STA Position */ -#define I2C1_CONSET_STA_Msk (0x01UL << I2C1_CONSET_STA_Pos) /*!< I2C1 CONSET: STA Mask */ -#define I2C1_CONSET_I2EN_Pos 6 /*!< I2C1 CONSET: I2EN Position */ -#define I2C1_CONSET_I2EN_Msk (0x01UL << I2C1_CONSET_I2EN_Pos) /*!< I2C1 CONSET: I2EN Mask */ - -// ---------------------------------------- I2C1_STAT ------------------------------------------- -#define I2C1_STAT_Status_Pos 3 /*!< I2C1 STAT: Status Position */ -#define I2C1_STAT_Status_Msk (0x1fUL << I2C1_STAT_Status_Pos) /*!< I2C1 STAT: Status Mask */ - -// ---------------------------------------- I2C1_DAT -------------------------------------------- -#define I2C1_DAT_Data_Pos 0 /*!< I2C1 DAT: Data Position */ -#define I2C1_DAT_Data_Msk (0x000000ffUL << I2C1_DAT_Data_Pos) /*!< I2C1 DAT: Data Mask */ - -// ---------------------------------------- I2C1_ADR0 ------------------------------------------- -#define I2C1_ADR0_GC_Pos 0 /*!< I2C1 ADR0: GC Position */ -#define I2C1_ADR0_GC_Msk (0x01UL << I2C1_ADR0_GC_Pos) /*!< I2C1 ADR0: GC Mask */ -#define I2C1_ADR0_Address_Pos 1 /*!< I2C1 ADR0: Address Position */ -#define I2C1_ADR0_Address_Msk (0x7fUL << I2C1_ADR0_Address_Pos) /*!< I2C1 ADR0: Address Mask */ - -// ---------------------------------------- I2C1_SCLH ------------------------------------------- -#define I2C1_SCLH_SCLH_Pos 0 /*!< I2C1 SCLH: SCLH Position */ -#define I2C1_SCLH_SCLH_Msk (0x0000ffffUL << I2C1_SCLH_SCLH_Pos) /*!< I2C1 SCLH: SCLH Mask */ - -// ---------------------------------------- I2C1_SCLL ------------------------------------------- -#define I2C1_SCLL_SCLL_Pos 0 /*!< I2C1 SCLL: SCLL Position */ -#define I2C1_SCLL_SCLL_Msk (0x0000ffffUL << I2C1_SCLL_SCLL_Pos) /*!< I2C1 SCLL: SCLL Mask */ - -// --------------------------------------- I2C1_CONCLR ------------------------------------------ -#define I2C1_CONCLR_AAC_Pos 2 /*!< I2C1 CONCLR: AAC Position */ -#define I2C1_CONCLR_AAC_Msk (0x01UL << I2C1_CONCLR_AAC_Pos) /*!< I2C1 CONCLR: AAC Mask */ -#define I2C1_CONCLR_SIC_Pos 3 /*!< I2C1 CONCLR: SIC Position */ -#define I2C1_CONCLR_SIC_Msk (0x01UL << I2C1_CONCLR_SIC_Pos) /*!< I2C1 CONCLR: SIC Mask */ -#define I2C1_CONCLR_STAC_Pos 5 /*!< I2C1 CONCLR: STAC Position */ -#define I2C1_CONCLR_STAC_Msk (0x01UL << I2C1_CONCLR_STAC_Pos) /*!< I2C1 CONCLR: STAC Mask */ -#define I2C1_CONCLR_I2ENC_Pos 6 /*!< I2C1 CONCLR: I2ENC Position */ -#define I2C1_CONCLR_I2ENC_Msk (0x01UL << I2C1_CONCLR_I2ENC_Pos) /*!< I2C1 CONCLR: I2ENC Mask */ - -// --------------------------------------- I2C1_MMCTRL ------------------------------------------ -#define I2C1_MMCTRL_MM_ENA_Pos 0 /*!< I2C1 MMCTRL: MM_ENA Position */ -#define I2C1_MMCTRL_MM_ENA_Msk (0x01UL << I2C1_MMCTRL_MM_ENA_Pos) /*!< I2C1 MMCTRL: MM_ENA Mask */ -#define I2C1_MMCTRL_ENA_SCL_Pos 1 /*!< I2C1 MMCTRL: ENA_SCL Position */ -#define I2C1_MMCTRL_ENA_SCL_Msk (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos) /*!< I2C1 MMCTRL: ENA_SCL Mask */ -#define I2C1_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C1 MMCTRL: MATCH_ALL Position */ -#define I2C1_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos) /*!< I2C1 MMCTRL: MATCH_ALL Mask */ - -// ---------------------------------------- I2C1_ADR1 ------------------------------------------- -#define I2C1_ADR1_GC_Pos 0 /*!< I2C1 ADR1: GC Position */ -#define I2C1_ADR1_GC_Msk (0x01UL << I2C1_ADR1_GC_Pos) /*!< I2C1 ADR1: GC Mask */ -#define I2C1_ADR1_Address_Pos 1 /*!< I2C1 ADR1: Address Position */ -#define I2C1_ADR1_Address_Msk (0x7fUL << I2C1_ADR1_Address_Pos) /*!< I2C1 ADR1: Address Mask */ - -// ---------------------------------------- I2C1_ADR2 ------------------------------------------- -#define I2C1_ADR2_GC_Pos 0 /*!< I2C1 ADR2: GC Position */ -#define I2C1_ADR2_GC_Msk (0x01UL << I2C1_ADR2_GC_Pos) /*!< I2C1 ADR2: GC Mask */ -#define I2C1_ADR2_Address_Pos 1 /*!< I2C1 ADR2: Address Position */ -#define I2C1_ADR2_Address_Msk (0x7fUL << I2C1_ADR2_Address_Pos) /*!< I2C1 ADR2: Address Mask */ - -// ---------------------------------------- I2C1_ADR3 ------------------------------------------- -#define I2C1_ADR3_GC_Pos 0 /*!< I2C1 ADR3: GC Position */ -#define I2C1_ADR3_GC_Msk (0x01UL << I2C1_ADR3_GC_Pos) /*!< I2C1 ADR3: GC Mask */ -#define I2C1_ADR3_Address_Pos 1 /*!< I2C1 ADR3: Address Position */ -#define I2C1_ADR3_Address_Msk (0x7fUL << I2C1_ADR3_Address_Pos) /*!< I2C1 ADR3: Address Mask */ - -// ------------------------------------ I2C1_DATA_BUFFER ---------------------------------------- -#define I2C1_DATA_BUFFER_Data_Pos 0 /*!< I2C1 DATA_BUFFER: Data Position */ -#define I2C1_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos) /*!< I2C1 DATA_BUFFER: Data Mask */ - -// --------------------------------------- I2C1_MASK0 ------------------------------------------- -#define I2C1_MASK0_MASK_Pos 1 /*!< I2C1 MASK0: MASK Position */ -#define I2C1_MASK0_MASK_Msk (0x7fUL << I2C1_MASK0_MASK_Pos) /*!< I2C1 MASK0: MASK Mask */ - -// --------------------------------------- I2C1_MASK1 ------------------------------------------- -#define I2C1_MASK1_MASK_Pos 1 /*!< I2C1 MASK1: MASK Position */ -#define I2C1_MASK1_MASK_Msk (0x7fUL << I2C1_MASK1_MASK_Pos) /*!< I2C1 MASK1: MASK Mask */ - -// --------------------------------------- I2C1_MASK2 ------------------------------------------- -#define I2C1_MASK2_MASK_Pos 1 /*!< I2C1 MASK2: MASK Position */ -#define I2C1_MASK2_MASK_Msk (0x7fUL << I2C1_MASK2_MASK_Pos) /*!< I2C1 MASK2: MASK Mask */ - -// --------------------------------------- I2C1_MASK3 ------------------------------------------- -#define I2C1_MASK3_MASK_Pos 1 /*!< I2C1 MASK3: MASK Position */ -#define I2C1_MASK3_MASK_Msk (0x7fUL << I2C1_MASK3_MASK_Pos) /*!< I2C1 MASK3: MASK Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2S0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- I2S0_DAO -------------------------------------------- -#define I2S0_DAO_WORDWIDTH_Pos 0 /*!< I2S0 DAO: WORDWIDTH Position */ -#define I2S0_DAO_WORDWIDTH_Msk (0x03UL << I2S0_DAO_WORDWIDTH_Pos) /*!< I2S0 DAO: WORDWIDTH Mask */ -#define I2S0_DAO_MONO_Pos 2 /*!< I2S0 DAO: MONO Position */ -#define I2S0_DAO_MONO_Msk (0x01UL << I2S0_DAO_MONO_Pos) /*!< I2S0 DAO: MONO Mask */ -#define I2S0_DAO_STOP_Pos 3 /*!< I2S0 DAO: STOP Position */ -#define I2S0_DAO_STOP_Msk (0x01UL << I2S0_DAO_STOP_Pos) /*!< I2S0 DAO: STOP Mask */ -#define I2S0_DAO_RESET_Pos 4 /*!< I2S0 DAO: RESET Position */ -#define I2S0_DAO_RESET_Msk (0x01UL << I2S0_DAO_RESET_Pos) /*!< I2S0 DAO: RESET Mask */ -#define I2S0_DAO_WS_SEL_Pos 5 /*!< I2S0 DAO: WS_SEL Position */ -#define I2S0_DAO_WS_SEL_Msk (0x01UL << I2S0_DAO_WS_SEL_Pos) /*!< I2S0 DAO: WS_SEL Mask */ -#define I2S0_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAO: WS_HALFPERIOD Position */ -#define I2S0_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos) /*!< I2S0 DAO: WS_HALFPERIOD Mask */ -#define I2S0_DAO_MUTE_Pos 15 /*!< I2S0 DAO: MUTE Position */ -#define I2S0_DAO_MUTE_Msk (0x01UL << I2S0_DAO_MUTE_Pos) /*!< I2S0 DAO: MUTE Mask */ - -// ---------------------------------------- I2S0_DAI -------------------------------------------- -#define I2S0_DAI_WORDWIDTH_Pos 0 /*!< I2S0 DAI: WORDWIDTH Position */ -#define I2S0_DAI_WORDWIDTH_Msk (0x03UL << I2S0_DAI_WORDWIDTH_Pos) /*!< I2S0 DAI: WORDWIDTH Mask */ -#define I2S0_DAI_MONO_Pos 2 /*!< I2S0 DAI: MONO Position */ -#define I2S0_DAI_MONO_Msk (0x01UL << I2S0_DAI_MONO_Pos) /*!< I2S0 DAI: MONO Mask */ -#define I2S0_DAI_STOP_Pos 3 /*!< I2S0 DAI: STOP Position */ -#define I2S0_DAI_STOP_Msk (0x01UL << I2S0_DAI_STOP_Pos) /*!< I2S0 DAI: STOP Mask */ -#define I2S0_DAI_RESET_Pos 4 /*!< I2S0 DAI: RESET Position */ -#define I2S0_DAI_RESET_Msk (0x01UL << I2S0_DAI_RESET_Pos) /*!< I2S0 DAI: RESET Mask */ -#define I2S0_DAI_WS_SEL_Pos 5 /*!< I2S0 DAI: WS_SEL Position */ -#define I2S0_DAI_WS_SEL_Msk (0x01UL << I2S0_DAI_WS_SEL_Pos) /*!< I2S0 DAI: WS_SEL Mask */ -#define I2S0_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAI: WS_HALFPERIOD Position */ -#define I2S0_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos) /*!< I2S0 DAI: WS_HALFPERIOD Mask */ - -// --------------------------------------- I2S0_TXFIFO ------------------------------------------ -#define I2S0_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S0 TXFIFO: I2STXFIFO Position */ -#define I2S0_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos) /*!< I2S0 TXFIFO: I2STXFIFO Mask */ - -// --------------------------------------- I2S0_RXFIFO ------------------------------------------ -#define I2S0_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S0 RXFIFO: I2SRXFIFO Position */ -#define I2S0_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos) /*!< I2S0 RXFIFO: I2SRXFIFO Mask */ - -// --------------------------------------- I2S0_STATE ------------------------------------------- -#define I2S0_STATE_IRQ_Pos 0 /*!< I2S0 STATE: IRQ Position */ -#define I2S0_STATE_IRQ_Msk (0x01UL << I2S0_STATE_IRQ_Pos) /*!< I2S0 STATE: IRQ Mask */ -#define I2S0_STATE_DMAREQ1_Pos 1 /*!< I2S0 STATE: DMAREQ1 Position */ -#define I2S0_STATE_DMAREQ1_Msk (0x01UL << I2S0_STATE_DMAREQ1_Pos) /*!< I2S0 STATE: DMAREQ1 Mask */ -#define I2S0_STATE_DMAREQ2_Pos 2 /*!< I2S0 STATE: DMAREQ2 Position */ -#define I2S0_STATE_DMAREQ2_Msk (0x01UL << I2S0_STATE_DMAREQ2_Pos) /*!< I2S0 STATE: DMAREQ2 Mask */ -#define I2S0_STATE_RX_LEVEL_Pos 8 /*!< I2S0 STATE: RX_LEVEL Position */ -#define I2S0_STATE_RX_LEVEL_Msk (0x0fUL << I2S0_STATE_RX_LEVEL_Pos) /*!< I2S0 STATE: RX_LEVEL Mask */ -#define I2S0_STATE_TX_LEVEL_Pos 16 /*!< I2S0 STATE: TX_LEVEL Position */ -#define I2S0_STATE_TX_LEVEL_Msk (0x0fUL << I2S0_STATE_TX_LEVEL_Pos) /*!< I2S0 STATE: TX_LEVEL Mask */ - -// ---------------------------------------- I2S0_DMA1 ------------------------------------------- -#define I2S0_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S0 DMA1: RX_DMA1_ENABLE Position */ -#define I2S0_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask */ -#define I2S0_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S0 DMA1: TX_DMA1_ENABLE Position */ -#define I2S0_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask */ -#define I2S0_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position */ -#define I2S0_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask */ -#define I2S0_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position */ -#define I2S0_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask */ - -// ---------------------------------------- I2S0_DMA2 ------------------------------------------- -#define I2S0_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S0 DMA2: RX_DMA2_ENABLE Position */ -#define I2S0_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask */ -#define I2S0_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S0 DMA2: TX_DMA2_ENABLE Position */ -#define I2S0_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask */ -#define I2S0_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position */ -#define I2S0_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask */ -#define I2S0_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position */ -#define I2S0_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask */ - -// ---------------------------------------- I2S0_IRQ -------------------------------------------- -#define I2S0_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S0 IRQ: RX_IRQ_ENABLE Position */ -#define I2S0_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask */ -#define I2S0_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S0 IRQ: TX_IRQ_ENABLE Position */ -#define I2S0_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask */ -#define I2S0_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S0 IRQ: RX_DEPTH_IRQ Position */ -#define I2S0_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask */ -#define I2S0_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S0 IRQ: TX_DEPTH_IRQ Position */ -#define I2S0_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask */ - -// --------------------------------------- I2S0_TXRATE ------------------------------------------ -#define I2S0_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 TXRATE: Y_DIVIDER Position */ -#define I2S0_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos) /*!< I2S0 TXRATE: Y_DIVIDER Mask */ -#define I2S0_TXRATE_X_DIVIDER_Pos 8 /*!< I2S0 TXRATE: X_DIVIDER Position */ -#define I2S0_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos) /*!< I2S0 TXRATE: X_DIVIDER Mask */ - -// --------------------------------------- I2S0_RXRATE ------------------------------------------ -#define I2S0_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 RXRATE: Y_DIVIDER Position */ -#define I2S0_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos) /*!< I2S0 RXRATE: Y_DIVIDER Mask */ -#define I2S0_RXRATE_X_DIVIDER_Pos 8 /*!< I2S0 RXRATE: X_DIVIDER Position */ -#define I2S0_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos) /*!< I2S0 RXRATE: X_DIVIDER Mask */ - -// ------------------------------------- I2S0_TXBITRATE ----------------------------------------- -#define I2S0_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S0 TXBITRATE: TX_BITRATE Position */ -#define I2S0_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos) /*!< I2S0 TXBITRATE: TX_BITRATE Mask */ - -// ------------------------------------- I2S0_RXBITRATE ----------------------------------------- -#define I2S0_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S0 RXBITRATE: RX_BITRATE Position */ -#define I2S0_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos) /*!< I2S0 RXBITRATE: RX_BITRATE Mask */ - -// --------------------------------------- I2S0_TXMODE ------------------------------------------ -#define I2S0_TXMODE_TXCLKSEL_Pos 0 /*!< I2S0 TXMODE: TXCLKSEL Position */ -#define I2S0_TXMODE_TXCLKSEL_Msk (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos) /*!< I2S0 TXMODE: TXCLKSEL Mask */ -#define I2S0_TXMODE_TX4PIN_Pos 2 /*!< I2S0 TXMODE: TX4PIN Position */ -#define I2S0_TXMODE_TX4PIN_Msk (0x01UL << I2S0_TXMODE_TX4PIN_Pos) /*!< I2S0 TXMODE: TX4PIN Mask */ -#define I2S0_TXMODE_TXMCENA_Pos 3 /*!< I2S0 TXMODE: TXMCENA Position */ -#define I2S0_TXMODE_TXMCENA_Msk (0x01UL << I2S0_TXMODE_TXMCENA_Pos) /*!< I2S0 TXMODE: TXMCENA Mask */ - -// --------------------------------------- I2S0_RXMODE ------------------------------------------ -#define I2S0_RXMODE_RXCLKSEL_Pos 0 /*!< I2S0 RXMODE: RXCLKSEL Position */ -#define I2S0_RXMODE_RXCLKSEL_Msk (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos) /*!< I2S0 RXMODE: RXCLKSEL Mask */ -#define I2S0_RXMODE_RX4PIN_Pos 2 /*!< I2S0 RXMODE: RX4PIN Position */ -#define I2S0_RXMODE_RX4PIN_Msk (0x01UL << I2S0_RXMODE_RX4PIN_Pos) /*!< I2S0 RXMODE: RX4PIN Mask */ -#define I2S0_RXMODE_RXMCENA_Pos 3 /*!< I2S0 RXMODE: RXMCENA Position */ -#define I2S0_RXMODE_RXMCENA_Msk (0x01UL << I2S0_RXMODE_RXMCENA_Pos) /*!< I2S0 RXMODE: RXMCENA Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2S1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- I2S1_DAO -------------------------------------------- -#define I2S1_DAO_WORDWIDTH_Pos 0 /*!< I2S1 DAO: WORDWIDTH Position */ -#define I2S1_DAO_WORDWIDTH_Msk (0x03UL << I2S1_DAO_WORDWIDTH_Pos) /*!< I2S1 DAO: WORDWIDTH Mask */ -#define I2S1_DAO_MONO_Pos 2 /*!< I2S1 DAO: MONO Position */ -#define I2S1_DAO_MONO_Msk (0x01UL << I2S1_DAO_MONO_Pos) /*!< I2S1 DAO: MONO Mask */ -#define I2S1_DAO_STOP_Pos 3 /*!< I2S1 DAO: STOP Position */ -#define I2S1_DAO_STOP_Msk (0x01UL << I2S1_DAO_STOP_Pos) /*!< I2S1 DAO: STOP Mask */ -#define I2S1_DAO_RESET_Pos 4 /*!< I2S1 DAO: RESET Position */ -#define I2S1_DAO_RESET_Msk (0x01UL << I2S1_DAO_RESET_Pos) /*!< I2S1 DAO: RESET Mask */ -#define I2S1_DAO_WS_SEL_Pos 5 /*!< I2S1 DAO: WS_SEL Position */ -#define I2S1_DAO_WS_SEL_Msk (0x01UL << I2S1_DAO_WS_SEL_Pos) /*!< I2S1 DAO: WS_SEL Mask */ -#define I2S1_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAO: WS_HALFPERIOD Position */ -#define I2S1_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos) /*!< I2S1 DAO: WS_HALFPERIOD Mask */ -#define I2S1_DAO_MUTE_Pos 15 /*!< I2S1 DAO: MUTE Position */ -#define I2S1_DAO_MUTE_Msk (0x01UL << I2S1_DAO_MUTE_Pos) /*!< I2S1 DAO: MUTE Mask */ - -// ---------------------------------------- I2S1_DAI -------------------------------------------- -#define I2S1_DAI_WORDWIDTH_Pos 0 /*!< I2S1 DAI: WORDWIDTH Position */ -#define I2S1_DAI_WORDWIDTH_Msk (0x03UL << I2S1_DAI_WORDWIDTH_Pos) /*!< I2S1 DAI: WORDWIDTH Mask */ -#define I2S1_DAI_MONO_Pos 2 /*!< I2S1 DAI: MONO Position */ -#define I2S1_DAI_MONO_Msk (0x01UL << I2S1_DAI_MONO_Pos) /*!< I2S1 DAI: MONO Mask */ -#define I2S1_DAI_STOP_Pos 3 /*!< I2S1 DAI: STOP Position */ -#define I2S1_DAI_STOP_Msk (0x01UL << I2S1_DAI_STOP_Pos) /*!< I2S1 DAI: STOP Mask */ -#define I2S1_DAI_RESET_Pos 4 /*!< I2S1 DAI: RESET Position */ -#define I2S1_DAI_RESET_Msk (0x01UL << I2S1_DAI_RESET_Pos) /*!< I2S1 DAI: RESET Mask */ -#define I2S1_DAI_WS_SEL_Pos 5 /*!< I2S1 DAI: WS_SEL Position */ -#define I2S1_DAI_WS_SEL_Msk (0x01UL << I2S1_DAI_WS_SEL_Pos) /*!< I2S1 DAI: WS_SEL Mask */ -#define I2S1_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAI: WS_HALFPERIOD Position */ -#define I2S1_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos) /*!< I2S1 DAI: WS_HALFPERIOD Mask */ - -// --------------------------------------- I2S1_TXFIFO ------------------------------------------ -#define I2S1_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S1 TXFIFO: I2STXFIFO Position */ -#define I2S1_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos) /*!< I2S1 TXFIFO: I2STXFIFO Mask */ - -// --------------------------------------- I2S1_RXFIFO ------------------------------------------ -#define I2S1_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S1 RXFIFO: I2SRXFIFO Position */ -#define I2S1_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos) /*!< I2S1 RXFIFO: I2SRXFIFO Mask */ - -// --------------------------------------- I2S1_STATE ------------------------------------------- -#define I2S1_STATE_IRQ_Pos 0 /*!< I2S1 STATE: IRQ Position */ -#define I2S1_STATE_IRQ_Msk (0x01UL << I2S1_STATE_IRQ_Pos) /*!< I2S1 STATE: IRQ Mask */ -#define I2S1_STATE_DMAREQ1_Pos 1 /*!< I2S1 STATE: DMAREQ1 Position */ -#define I2S1_STATE_DMAREQ1_Msk (0x01UL << I2S1_STATE_DMAREQ1_Pos) /*!< I2S1 STATE: DMAREQ1 Mask */ -#define I2S1_STATE_DMAREQ2_Pos 2 /*!< I2S1 STATE: DMAREQ2 Position */ -#define I2S1_STATE_DMAREQ2_Msk (0x01UL << I2S1_STATE_DMAREQ2_Pos) /*!< I2S1 STATE: DMAREQ2 Mask */ -#define I2S1_STATE_RX_LEVEL_Pos 8 /*!< I2S1 STATE: RX_LEVEL Position */ -#define I2S1_STATE_RX_LEVEL_Msk (0x0fUL << I2S1_STATE_RX_LEVEL_Pos) /*!< I2S1 STATE: RX_LEVEL Mask */ -#define I2S1_STATE_TX_LEVEL_Pos 16 /*!< I2S1 STATE: TX_LEVEL Position */ -#define I2S1_STATE_TX_LEVEL_Msk (0x0fUL << I2S1_STATE_TX_LEVEL_Pos) /*!< I2S1 STATE: TX_LEVEL Mask */ - -// ---------------------------------------- I2S1_DMA1 ------------------------------------------- -#define I2S1_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S1 DMA1: RX_DMA1_ENABLE Position */ -#define I2S1_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask */ -#define I2S1_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S1 DMA1: TX_DMA1_ENABLE Position */ -#define I2S1_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask */ -#define I2S1_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position */ -#define I2S1_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask */ -#define I2S1_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position */ -#define I2S1_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask */ - -// ---------------------------------------- I2S1_DMA2 ------------------------------------------- -#define I2S1_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S1 DMA2: RX_DMA2_ENABLE Position */ -#define I2S1_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask */ -#define I2S1_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S1 DMA2: TX_DMA2_ENABLE Position */ -#define I2S1_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask */ -#define I2S1_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position */ -#define I2S1_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask */ -#define I2S1_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position */ -#define I2S1_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask */ - -// ---------------------------------------- I2S1_IRQ -------------------------------------------- -#define I2S1_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S1 IRQ: RX_IRQ_ENABLE Position */ -#define I2S1_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask */ -#define I2S1_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S1 IRQ: TX_IRQ_ENABLE Position */ -#define I2S1_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask */ -#define I2S1_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S1 IRQ: RX_DEPTH_IRQ Position */ -#define I2S1_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask */ -#define I2S1_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S1 IRQ: TX_DEPTH_IRQ Position */ -#define I2S1_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask */ - -// --------------------------------------- I2S1_TXRATE ------------------------------------------ -#define I2S1_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 TXRATE: Y_DIVIDER Position */ -#define I2S1_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos) /*!< I2S1 TXRATE: Y_DIVIDER Mask */ -#define I2S1_TXRATE_X_DIVIDER_Pos 8 /*!< I2S1 TXRATE: X_DIVIDER Position */ -#define I2S1_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos) /*!< I2S1 TXRATE: X_DIVIDER Mask */ - -// --------------------------------------- I2S1_RXRATE ------------------------------------------ -#define I2S1_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 RXRATE: Y_DIVIDER Position */ -#define I2S1_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos) /*!< I2S1 RXRATE: Y_DIVIDER Mask */ -#define I2S1_RXRATE_X_DIVIDER_Pos 8 /*!< I2S1 RXRATE: X_DIVIDER Position */ -#define I2S1_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos) /*!< I2S1 RXRATE: X_DIVIDER Mask */ - -// ------------------------------------- I2S1_TXBITRATE ----------------------------------------- -#define I2S1_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S1 TXBITRATE: TX_BITRATE Position */ -#define I2S1_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos) /*!< I2S1 TXBITRATE: TX_BITRATE Mask */ - -// ------------------------------------- I2S1_RXBITRATE ----------------------------------------- -#define I2S1_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S1 RXBITRATE: RX_BITRATE Position */ -#define I2S1_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos) /*!< I2S1 RXBITRATE: RX_BITRATE Mask */ - -// --------------------------------------- I2S1_TXMODE ------------------------------------------ -#define I2S1_TXMODE_TXCLKSEL_Pos 0 /*!< I2S1 TXMODE: TXCLKSEL Position */ -#define I2S1_TXMODE_TXCLKSEL_Msk (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos) /*!< I2S1 TXMODE: TXCLKSEL Mask */ -#define I2S1_TXMODE_TX4PIN_Pos 2 /*!< I2S1 TXMODE: TX4PIN Position */ -#define I2S1_TXMODE_TX4PIN_Msk (0x01UL << I2S1_TXMODE_TX4PIN_Pos) /*!< I2S1 TXMODE: TX4PIN Mask */ -#define I2S1_TXMODE_TXMCENA_Pos 3 /*!< I2S1 TXMODE: TXMCENA Position */ -#define I2S1_TXMODE_TXMCENA_Msk (0x01UL << I2S1_TXMODE_TXMCENA_Pos) /*!< I2S1 TXMODE: TXMCENA Mask */ - -// --------------------------------------- I2S1_RXMODE ------------------------------------------ -#define I2S1_RXMODE_RXCLKSEL_Pos 0 /*!< I2S1 RXMODE: RXCLKSEL Position */ -#define I2S1_RXMODE_RXCLKSEL_Msk (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos) /*!< I2S1 RXMODE: RXCLKSEL Mask */ -#define I2S1_RXMODE_RX4PIN_Pos 2 /*!< I2S1 RXMODE: RX4PIN Position */ -#define I2S1_RXMODE_RX4PIN_Msk (0x01UL << I2S1_RXMODE_RX4PIN_Pos) /*!< I2S1 RXMODE: RX4PIN Mask */ -#define I2S1_RXMODE_RXMCENA_Pos 3 /*!< I2S1 RXMODE: RXMCENA Position */ -#define I2S1_RXMODE_RXMCENA_Msk (0x01UL << I2S1_RXMODE_RXMCENA_Pos) /*!< I2S1 RXMODE: RXMCENA Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- C_CAN1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- C_CAN1_CNTL ------------------------------------------ -#define C_CAN1_CNTL_INIT_Pos 0 /*!< C_CAN1 CNTL: INIT Position */ -#define C_CAN1_CNTL_INIT_Msk (0x01UL << C_CAN1_CNTL_INIT_Pos) /*!< C_CAN1 CNTL: INIT Mask */ -#define C_CAN1_CNTL_IE_Pos 1 /*!< C_CAN1 CNTL: IE Position */ -#define C_CAN1_CNTL_IE_Msk (0x01UL << C_CAN1_CNTL_IE_Pos) /*!< C_CAN1 CNTL: IE Mask */ -#define C_CAN1_CNTL_SIE_Pos 2 /*!< C_CAN1 CNTL: SIE Position */ -#define C_CAN1_CNTL_SIE_Msk (0x01UL << C_CAN1_CNTL_SIE_Pos) /*!< C_CAN1 CNTL: SIE Mask */ -#define C_CAN1_CNTL_EIE_Pos 3 /*!< C_CAN1 CNTL: EIE Position */ -#define C_CAN1_CNTL_EIE_Msk (0x01UL << C_CAN1_CNTL_EIE_Pos) /*!< C_CAN1 CNTL: EIE Mask */ -#define C_CAN1_CNTL_DAR_Pos 5 /*!< C_CAN1 CNTL: DAR Position */ -#define C_CAN1_CNTL_DAR_Msk (0x01UL << C_CAN1_CNTL_DAR_Pos) /*!< C_CAN1 CNTL: DAR Mask */ -#define C_CAN1_CNTL_CCE_Pos 6 /*!< C_CAN1 CNTL: CCE Position */ -#define C_CAN1_CNTL_CCE_Msk (0x01UL << C_CAN1_CNTL_CCE_Pos) /*!< C_CAN1 CNTL: CCE Mask */ -#define C_CAN1_CNTL_TEST_Pos 7 /*!< C_CAN1 CNTL: TEST Position */ -#define C_CAN1_CNTL_TEST_Msk (0x01UL << C_CAN1_CNTL_TEST_Pos) /*!< C_CAN1 CNTL: TEST Mask */ - -// --------------------------------------- C_CAN1_STAT ------------------------------------------ -#define C_CAN1_STAT_LEC_Pos 0 /*!< C_CAN1 STAT: LEC Position */ -#define C_CAN1_STAT_LEC_Msk (0x07UL << C_CAN1_STAT_LEC_Pos) /*!< C_CAN1 STAT: LEC Mask */ -#define C_CAN1_STAT_TXOK_Pos 3 /*!< C_CAN1 STAT: TXOK Position */ -#define C_CAN1_STAT_TXOK_Msk (0x01UL << C_CAN1_STAT_TXOK_Pos) /*!< C_CAN1 STAT: TXOK Mask */ -#define C_CAN1_STAT_RXOK_Pos 4 /*!< C_CAN1 STAT: RXOK Position */ -#define C_CAN1_STAT_RXOK_Msk (0x01UL << C_CAN1_STAT_RXOK_Pos) /*!< C_CAN1 STAT: RXOK Mask */ -#define C_CAN1_STAT_EPASS_Pos 5 /*!< C_CAN1 STAT: EPASS Position */ -#define C_CAN1_STAT_EPASS_Msk (0x01UL << C_CAN1_STAT_EPASS_Pos) /*!< C_CAN1 STAT: EPASS Mask */ -#define C_CAN1_STAT_EWARN_Pos 6 /*!< C_CAN1 STAT: EWARN Position */ -#define C_CAN1_STAT_EWARN_Msk (0x01UL << C_CAN1_STAT_EWARN_Pos) /*!< C_CAN1 STAT: EWARN Mask */ -#define C_CAN1_STAT_BOFF_Pos 7 /*!< C_CAN1 STAT: BOFF Position */ -#define C_CAN1_STAT_BOFF_Msk (0x01UL << C_CAN1_STAT_BOFF_Pos) /*!< C_CAN1 STAT: BOFF Mask */ - -// ---------------------------------------- C_CAN1_EC ------------------------------------------- -#define C_CAN1_EC_TEC_7_0_Pos 0 /*!< C_CAN1 EC: TEC_7_0 Position */ -#define C_CAN1_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos) /*!< C_CAN1 EC: TEC_7_0 Mask */ -#define C_CAN1_EC_REC_6_0_Pos 8 /*!< C_CAN1 EC: REC_6_0 Position */ -#define C_CAN1_EC_REC_6_0_Msk (0x7fUL << C_CAN1_EC_REC_6_0_Pos) /*!< C_CAN1 EC: REC_6_0 Mask */ -#define C_CAN1_EC_RP_Pos 15 /*!< C_CAN1 EC: RP Position */ -#define C_CAN1_EC_RP_Msk (0x01UL << C_CAN1_EC_RP_Pos) /*!< C_CAN1 EC: RP Mask */ - -// ---------------------------------------- C_CAN1_BT ------------------------------------------- -#define C_CAN1_BT_BRP_Pos 0 /*!< C_CAN1 BT: BRP Position */ -#define C_CAN1_BT_BRP_Msk (0x3fUL << C_CAN1_BT_BRP_Pos) /*!< C_CAN1 BT: BRP Mask */ -#define C_CAN1_BT_SJW_Pos 6 /*!< C_CAN1 BT: SJW Position */ -#define C_CAN1_BT_SJW_Msk (0x03UL << C_CAN1_BT_SJW_Pos) /*!< C_CAN1 BT: SJW Mask */ -#define C_CAN1_BT_TSEG1_Pos 8 /*!< C_CAN1 BT: TSEG1 Position */ -#define C_CAN1_BT_TSEG1_Msk (0x0fUL << C_CAN1_BT_TSEG1_Pos) /*!< C_CAN1 BT: TSEG1 Mask */ -#define C_CAN1_BT_TSEG2_Pos 12 /*!< C_CAN1 BT: TSEG2 Position */ -#define C_CAN1_BT_TSEG2_Msk (0x07UL << C_CAN1_BT_TSEG2_Pos) /*!< C_CAN1 BT: TSEG2 Mask */ - -// --------------------------------------- C_CAN1_INT ------------------------------------------- -#define C_CAN1_INT_INTID15_0_Pos 0 /*!< C_CAN1 INT: INTID15_0 Position */ -#define C_CAN1_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos) /*!< C_CAN1 INT: INTID15_0 Mask */ - -// --------------------------------------- C_CAN1_TEST ------------------------------------------ -#define C_CAN1_TEST_BASIC_Pos 2 /*!< C_CAN1 TEST: BASIC Position */ -#define C_CAN1_TEST_BASIC_Msk (0x01UL << C_CAN1_TEST_BASIC_Pos) /*!< C_CAN1 TEST: BASIC Mask */ -#define C_CAN1_TEST_SILENT_Pos 3 /*!< C_CAN1 TEST: SILENT Position */ -#define C_CAN1_TEST_SILENT_Msk (0x01UL << C_CAN1_TEST_SILENT_Pos) /*!< C_CAN1 TEST: SILENT Mask */ -#define C_CAN1_TEST_LBACK_Pos 4 /*!< C_CAN1 TEST: LBACK Position */ -#define C_CAN1_TEST_LBACK_Msk (0x01UL << C_CAN1_TEST_LBACK_Pos) /*!< C_CAN1 TEST: LBACK Mask */ -#define C_CAN1_TEST_TX1_0_Pos 5 /*!< C_CAN1 TEST: TX1_0 Position */ -#define C_CAN1_TEST_TX1_0_Msk (0x03UL << C_CAN1_TEST_TX1_0_Pos) /*!< C_CAN1 TEST: TX1_0 Mask */ -#define C_CAN1_TEST_RX_Pos 7 /*!< C_CAN1 TEST: RX Position */ -#define C_CAN1_TEST_RX_Msk (0x01UL << C_CAN1_TEST_RX_Pos) /*!< C_CAN1 TEST: RX Mask */ - -// --------------------------------------- C_CAN1_BRPE ------------------------------------------ -#define C_CAN1_BRPE_BRPE_Pos 0 /*!< C_CAN1 BRPE: BRPE Position */ -#define C_CAN1_BRPE_BRPE_Msk (0x0fUL << C_CAN1_BRPE_BRPE_Pos) /*!< C_CAN1 BRPE: BRPE Mask */ - -// ------------------------------------ C_CAN1_IF1_CMDREQ --------------------------------------- -#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */ -#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask */ -#define C_CAN1_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF1_CMDREQ: BUSY Position */ -#define C_CAN1_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF1_CMDREQ: BUSY Mask */ - -// ----------------------------------- C_CAN1_IF1_CMDMSK_W -------------------------------------- -#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */ -#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask */ -#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */ -#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask */ -#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */ -#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask */ -#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */ -#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */ -#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position */ -#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask */ -#define C_CAN1_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_W: ARB Position */ -#define C_CAN1_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask */ -#define C_CAN1_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_W: MASK Position */ -#define C_CAN1_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask */ -#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */ -#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask */ - -// ----------------------------------- C_CAN1_IF1_CMDMSK_R -------------------------------------- -#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */ -#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask */ -#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */ -#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask */ -#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */ -#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask */ -#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */ -#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */ -#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position */ -#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask */ -#define C_CAN1_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_R: ARB Position */ -#define C_CAN1_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask */ -#define C_CAN1_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_R: MASK Position */ -#define C_CAN1_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask */ -#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */ -#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask */ - -// ------------------------------------- C_CAN1_IF1_MSK1 ---------------------------------------- -#define C_CAN1_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF1_MSK1: MSK15_0 Position */ -#define C_CAN1_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask */ - -// ------------------------------------- C_CAN1_IF1_MSK2 ---------------------------------------- -#define C_CAN1_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF1_MSK2: MSK28_16 Position */ -#define C_CAN1_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask */ -#define C_CAN1_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF1_MSK2: MDIR Position */ -#define C_CAN1_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos) /*!< C_CAN1 IF1_MSK2: MDIR Mask */ -#define C_CAN1_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF1_MSK2: MXTD Position */ -#define C_CAN1_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos) /*!< C_CAN1 IF1_MSK2: MXTD Mask */ - -// ------------------------------------- C_CAN1_IF1_ARB1 ---------------------------------------- -#define C_CAN1_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF1_ARB1: ID15_0 Position */ -#define C_CAN1_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos) /*!< C_CAN1 IF1_ARB1: ID15_0 Mask */ - -// ------------------------------------- C_CAN1_IF1_ARB2 ---------------------------------------- -#define C_CAN1_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF1_ARB2: ID28_16 Position */ -#define C_CAN1_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos) /*!< C_CAN1 IF1_ARB2: ID28_16 Mask */ -#define C_CAN1_IF1_ARB2_DIR_Pos 13 /*!< C_CAN1 IF1_ARB2: DIR Position */ -#define C_CAN1_IF1_ARB2_DIR_Msk (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos) /*!< C_CAN1 IF1_ARB2: DIR Mask */ -#define C_CAN1_IF1_ARB2_XTD_Pos 14 /*!< C_CAN1 IF1_ARB2: XTD Position */ -#define C_CAN1_IF1_ARB2_XTD_Msk (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos) /*!< C_CAN1 IF1_ARB2: XTD Mask */ -#define C_CAN1_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF1_ARB2: MSGVAL Position */ -#define C_CAN1_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF1_ARB2: MSGVAL Mask */ - -// ------------------------------------ C_CAN1_IF1_MCTRL ---------------------------------------- -#define C_CAN1_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position */ -#define C_CAN1_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask */ -#define C_CAN1_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF1_MCTRL: EOB Position */ -#define C_CAN1_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos) /*!< C_CAN1 IF1_MCTRL: EOB Mask */ -#define C_CAN1_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF1_MCTRL: TXRQST Position */ -#define C_CAN1_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF1_MCTRL: TXRQST Mask */ -#define C_CAN1_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF1_MCTRL: RMTEN Position */ -#define C_CAN1_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF1_MCTRL: RMTEN Mask */ -#define C_CAN1_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF1_MCTRL: RXIE Position */ -#define C_CAN1_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos) /*!< C_CAN1 IF1_MCTRL: RXIE Mask */ -#define C_CAN1_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF1_MCTRL: TXIE Position */ -#define C_CAN1_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos) /*!< C_CAN1 IF1_MCTRL: TXIE Mask */ -#define C_CAN1_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF1_MCTRL: UMASK Position */ -#define C_CAN1_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos) /*!< C_CAN1 IF1_MCTRL: UMASK Mask */ -#define C_CAN1_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF1_MCTRL: INTPND Position */ -#define C_CAN1_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos) /*!< C_CAN1 IF1_MCTRL: INTPND Mask */ -#define C_CAN1_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF1_MCTRL: MSGLST Position */ -#define C_CAN1_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF1_MCTRL: MSGLST Mask */ -#define C_CAN1_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF1_MCTRL: NEWDAT Position */ -#define C_CAN1_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask */ - -// ------------------------------------- C_CAN1_IF1_DA1 ----------------------------------------- -#define C_CAN1_IF1_DA1_DATA0_Pos 0 /*!< C_CAN1 IF1_DA1: DATA0 Position */ -#define C_CAN1_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos) /*!< C_CAN1 IF1_DA1: DATA0 Mask */ -#define C_CAN1_IF1_DA1_DATA1_Pos 8 /*!< C_CAN1 IF1_DA1: DATA1 Position */ -#define C_CAN1_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos) /*!< C_CAN1 IF1_DA1: DATA1 Mask */ - -// ------------------------------------- C_CAN1_IF1_DA2 ----------------------------------------- -#define C_CAN1_IF1_DA2_DATA2_Pos 0 /*!< C_CAN1 IF1_DA2: DATA2 Position */ -#define C_CAN1_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos) /*!< C_CAN1 IF1_DA2: DATA2 Mask */ -#define C_CAN1_IF1_DA2_DATA3_Pos 8 /*!< C_CAN1 IF1_DA2: DATA3 Position */ -#define C_CAN1_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos) /*!< C_CAN1 IF1_DA2: DATA3 Mask */ - -// ------------------------------------- C_CAN1_IF1_DB1 ----------------------------------------- -#define C_CAN1_IF1_DB1_DATA4_Pos 0 /*!< C_CAN1 IF1_DB1: DATA4 Position */ -#define C_CAN1_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos) /*!< C_CAN1 IF1_DB1: DATA4 Mask */ -#define C_CAN1_IF1_DB1_DATA5_Pos 8 /*!< C_CAN1 IF1_DB1: DATA5 Position */ -#define C_CAN1_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos) /*!< C_CAN1 IF1_DB1: DATA5 Mask */ - -// ------------------------------------- C_CAN1_IF1_DB2 ----------------------------------------- -#define C_CAN1_IF1_DB2_DATA6_Pos 0 /*!< C_CAN1 IF1_DB2: DATA6 Position */ -#define C_CAN1_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos) /*!< C_CAN1 IF1_DB2: DATA6 Mask */ -#define C_CAN1_IF1_DB2_DATA7_Pos 8 /*!< C_CAN1 IF1_DB2: DATA7 Position */ -#define C_CAN1_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos) /*!< C_CAN1 IF1_DB2: DATA7 Mask */ - -// ------------------------------------ C_CAN1_IF2_CMDREQ --------------------------------------- -#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */ -#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask */ -#define C_CAN1_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF2_CMDREQ: BUSY Position */ -#define C_CAN1_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF2_CMDREQ: BUSY Mask */ - -// ----------------------------------- C_CAN1_IF2_CMDMSK_W -------------------------------------- -#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */ -#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask */ -#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */ -#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask */ -#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */ -#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask */ -#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */ -#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */ -#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position */ -#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask */ -#define C_CAN1_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_W: ARB Position */ -#define C_CAN1_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask */ -#define C_CAN1_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_W: MASK Position */ -#define C_CAN1_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask */ -#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */ -#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask */ - -// ----------------------------------- C_CAN1_IF2_CMDMSK_R -------------------------------------- -#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */ -#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask */ -#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */ -#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask */ -#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */ -#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask */ -#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */ -#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */ -#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position */ -#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask */ -#define C_CAN1_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_R: ARB Position */ -#define C_CAN1_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask */ -#define C_CAN1_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_R: MASK Position */ -#define C_CAN1_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask */ -#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */ -#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask */ - -// ------------------------------------- C_CAN1_IF2_MSK1 ---------------------------------------- -#define C_CAN1_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF2_MSK1: MSK15_0 Position */ -#define C_CAN1_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask */ - -// ------------------------------------- C_CAN1_IF2_MSK2 ---------------------------------------- -#define C_CAN1_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF2_MSK2: MSK28_16 Position */ -#define C_CAN1_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask */ -#define C_CAN1_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF2_MSK2: MDIR Position */ -#define C_CAN1_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos) /*!< C_CAN1 IF2_MSK2: MDIR Mask */ -#define C_CAN1_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF2_MSK2: MXTD Position */ -#define C_CAN1_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos) /*!< C_CAN1 IF2_MSK2: MXTD Mask */ - -// ------------------------------------- C_CAN1_IF2_ARB1 ---------------------------------------- -#define C_CAN1_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF2_ARB1: ID15_0 Position */ -#define C_CAN1_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos) /*!< C_CAN1 IF2_ARB1: ID15_0 Mask */ - -// ------------------------------------- C_CAN1_IF2_ARB2 ---------------------------------------- -#define C_CAN1_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF2_ARB2: ID28_16 Position */ -#define C_CAN1_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos) /*!< C_CAN1 IF2_ARB2: ID28_16 Mask */ -#define C_CAN1_IF2_ARB2_DIR_Pos 13 /*!< C_CAN1 IF2_ARB2: DIR Position */ -#define C_CAN1_IF2_ARB2_DIR_Msk (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos) /*!< C_CAN1 IF2_ARB2: DIR Mask */ -#define C_CAN1_IF2_ARB2_XTD_Pos 14 /*!< C_CAN1 IF2_ARB2: XTD Position */ -#define C_CAN1_IF2_ARB2_XTD_Msk (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos) /*!< C_CAN1 IF2_ARB2: XTD Mask */ -#define C_CAN1_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF2_ARB2: MSGVAL Position */ -#define C_CAN1_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF2_ARB2: MSGVAL Mask */ - -// ------------------------------------ C_CAN1_IF2_MCTRL ---------------------------------------- -#define C_CAN1_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position */ -#define C_CAN1_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask */ -#define C_CAN1_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF2_MCTRL: EOB Position */ -#define C_CAN1_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos) /*!< C_CAN1 IF2_MCTRL: EOB Mask */ -#define C_CAN1_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF2_MCTRL: TXRQST Position */ -#define C_CAN1_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF2_MCTRL: TXRQST Mask */ -#define C_CAN1_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF2_MCTRL: RMTEN Position */ -#define C_CAN1_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF2_MCTRL: RMTEN Mask */ -#define C_CAN1_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF2_MCTRL: RXIE Position */ -#define C_CAN1_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos) /*!< C_CAN1 IF2_MCTRL: RXIE Mask */ -#define C_CAN1_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF2_MCTRL: TXIE Position */ -#define C_CAN1_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos) /*!< C_CAN1 IF2_MCTRL: TXIE Mask */ -#define C_CAN1_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF2_MCTRL: UMASK Position */ -#define C_CAN1_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos) /*!< C_CAN1 IF2_MCTRL: UMASK Mask */ -#define C_CAN1_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF2_MCTRL: INTPND Position */ -#define C_CAN1_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos) /*!< C_CAN1 IF2_MCTRL: INTPND Mask */ -#define C_CAN1_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF2_MCTRL: MSGLST Position */ -#define C_CAN1_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF2_MCTRL: MSGLST Mask */ -#define C_CAN1_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF2_MCTRL: NEWDAT Position */ -#define C_CAN1_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask */ - -// ------------------------------------- C_CAN1_IF2_DA1 ----------------------------------------- -#define C_CAN1_IF2_DA1_DATA0_Pos 0 /*!< C_CAN1 IF2_DA1: DATA0 Position */ -#define C_CAN1_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos) /*!< C_CAN1 IF2_DA1: DATA0 Mask */ -#define C_CAN1_IF2_DA1_DATA1_Pos 8 /*!< C_CAN1 IF2_DA1: DATA1 Position */ -#define C_CAN1_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos) /*!< C_CAN1 IF2_DA1: DATA1 Mask */ - -// ------------------------------------- C_CAN1_IF2_DA2 ----------------------------------------- -#define C_CAN1_IF2_DA2_DATA2_Pos 0 /*!< C_CAN1 IF2_DA2: DATA2 Position */ -#define C_CAN1_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos) /*!< C_CAN1 IF2_DA2: DATA2 Mask */ -#define C_CAN1_IF2_DA2_DATA3_Pos 8 /*!< C_CAN1 IF2_DA2: DATA3 Position */ -#define C_CAN1_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos) /*!< C_CAN1 IF2_DA2: DATA3 Mask */ - -// ------------------------------------- C_CAN1_IF2_DB1 ----------------------------------------- -#define C_CAN1_IF2_DB1_DATA4_Pos 0 /*!< C_CAN1 IF2_DB1: DATA4 Position */ -#define C_CAN1_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos) /*!< C_CAN1 IF2_DB1: DATA4 Mask */ -#define C_CAN1_IF2_DB1_DATA5_Pos 8 /*!< C_CAN1 IF2_DB1: DATA5 Position */ -#define C_CAN1_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos) /*!< C_CAN1 IF2_DB1: DATA5 Mask */ - -// ------------------------------------- C_CAN1_IF2_DB2 ----------------------------------------- -#define C_CAN1_IF2_DB2_DATA6_Pos 0 /*!< C_CAN1 IF2_DB2: DATA6 Position */ -#define C_CAN1_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos) /*!< C_CAN1 IF2_DB2: DATA6 Mask */ -#define C_CAN1_IF2_DB2_DATA7_Pos 8 /*!< C_CAN1 IF2_DB2: DATA7 Position */ -#define C_CAN1_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos) /*!< C_CAN1 IF2_DB2: DATA7 Mask */ - -// -------------------------------------- C_CAN1_TXREQ1 ----------------------------------------- -#define C_CAN1_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN1 TXREQ1: TXRQST16_1 Position */ -#define C_CAN1_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask */ - -// -------------------------------------- C_CAN1_TXREQ2 ----------------------------------------- -#define C_CAN1_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */ -#define C_CAN1_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask */ - -// --------------------------------------- C_CAN1_ND1 ------------------------------------------- -#define C_CAN1_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN1 ND1: NEWDAT16_1 Position */ -#define C_CAN1_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos) /*!< C_CAN1 ND1: NEWDAT16_1 Mask */ - -// --------------------------------------- C_CAN1_ND2 ------------------------------------------- -#define C_CAN1_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN1 ND2: NEWDAT32_17 Position */ -#define C_CAN1_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos) /*!< C_CAN1 ND2: NEWDAT32_17 Mask */ - -// --------------------------------------- C_CAN1_IR1 ------------------------------------------- -#define C_CAN1_IR1_INTPND16_1_Pos 0 /*!< C_CAN1 IR1: INTPND16_1 Position */ -#define C_CAN1_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos) /*!< C_CAN1 IR1: INTPND16_1 Mask */ - -// --------------------------------------- C_CAN1_IR2 ------------------------------------------- -#define C_CAN1_IR2_INTPND32_17_Pos 0 /*!< C_CAN1 IR2: INTPND32_17 Position */ -#define C_CAN1_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos) /*!< C_CAN1 IR2: INTPND32_17 Mask */ - -// -------------------------------------- C_CAN1_MSGV1 ------------------------------------------ -#define C_CAN1_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN1 MSGV1: MSGVAL16_1 Position */ -#define C_CAN1_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask */ - -// -------------------------------------- C_CAN1_MSGV2 ------------------------------------------ -#define C_CAN1_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN1 MSGV2: MSGVAL32_17 Position */ -#define C_CAN1_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask */ - -// -------------------------------------- C_CAN1_CLKDIV ----------------------------------------- -#define C_CAN1_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN1 CLKDIV: CLKDIVVAL Position */ -#define C_CAN1_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- RITIMER Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- RITIMER_COMPVAL ---------------------------------------- -#define RITIMER_COMPVAL_RICOMP_Pos 0 /*!< RITIMER COMPVAL: RICOMP Position */ -#define RITIMER_COMPVAL_RICOMP_Msk (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos) /*!< RITIMER COMPVAL: RICOMP Mask */ - -// -------------------------------------- RITIMER_MASK ------------------------------------------ -#define RITIMER_MASK_RIMASK_Pos 0 /*!< RITIMER MASK: RIMASK Position */ -#define RITIMER_MASK_RIMASK_Msk (0xffffffffUL << RITIMER_MASK_RIMASK_Pos) /*!< RITIMER MASK: RIMASK Mask */ - -// -------------------------------------- RITIMER_CTRL ------------------------------------------ -#define RITIMER_CTRL_RITINT_Pos 0 /*!< RITIMER CTRL: RITINT Position */ -#define RITIMER_CTRL_RITINT_Msk (0x01UL << RITIMER_CTRL_RITINT_Pos) /*!< RITIMER CTRL: RITINT Mask */ -#define RITIMER_CTRL_RITENCLR_Pos 1 /*!< RITIMER CTRL: RITENCLR Position */ -#define RITIMER_CTRL_RITENCLR_Msk (0x01UL << RITIMER_CTRL_RITENCLR_Pos) /*!< RITIMER CTRL: RITENCLR Mask */ -#define RITIMER_CTRL_RITENBR_Pos 2 /*!< RITIMER CTRL: RITENBR Position */ -#define RITIMER_CTRL_RITENBR_Msk (0x01UL << RITIMER_CTRL_RITENBR_Pos) /*!< RITIMER CTRL: RITENBR Mask */ -#define RITIMER_CTRL_RITEN_Pos 3 /*!< RITIMER CTRL: RITEN Position */ -#define RITIMER_CTRL_RITEN_Msk (0x01UL << RITIMER_CTRL_RITEN_Pos) /*!< RITIMER CTRL: RITEN Mask */ - -// ------------------------------------- RITIMER_COUNTER ---------------------------------------- -#define RITIMER_COUNTER_RICOUNTER_Pos 0 /*!< RITIMER COUNTER: RICOUNTER Position */ -#define RITIMER_COUNTER_RICOUNTER_Msk (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos) /*!< RITIMER COUNTER: RICOUNTER Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- QEI Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- QEI_CON -------------------------------------------- -#define QEI_CON_RESP_Pos 0 /*!< QEI CON: RESP Position */ -#define QEI_CON_RESP_Msk (0x01UL << QEI_CON_RESP_Pos) /*!< QEI CON: RESP Mask */ -#define QEI_CON_RESPI_Pos 1 /*!< QEI CON: RESPI Position */ -#define QEI_CON_RESPI_Msk (0x01UL << QEI_CON_RESPI_Pos) /*!< QEI CON: RESPI Mask */ -#define QEI_CON_RESV_Pos 2 /*!< QEI CON: RESV Position */ -#define QEI_CON_RESV_Msk (0x01UL << QEI_CON_RESV_Pos) /*!< QEI CON: RESV Mask */ -#define QEI_CON_RESI_Pos 3 /*!< QEI CON: RESI Position */ -#define QEI_CON_RESI_Msk (0x01UL << QEI_CON_RESI_Pos) /*!< QEI CON: RESI Mask */ - -// ---------------------------------------- QEI_STAT -------------------------------------------- -#define QEI_STAT_DIR_Pos 0 /*!< QEI STAT: DIR Position */ -#define QEI_STAT_DIR_Msk (0x01UL << QEI_STAT_DIR_Pos) /*!< QEI STAT: DIR Mask */ - -// ---------------------------------------- QEI_CONF -------------------------------------------- -#define QEI_CONF_DIRINV_Pos 0 /*!< QEI CONF: DIRINV Position */ -#define QEI_CONF_DIRINV_Msk (0x01UL << QEI_CONF_DIRINV_Pos) /*!< QEI CONF: DIRINV Mask */ -#define QEI_CONF_SIGMODE_Pos 1 /*!< QEI CONF: SIGMODE Position */ -#define QEI_CONF_SIGMODE_Msk (0x01UL << QEI_CONF_SIGMODE_Pos) /*!< QEI CONF: SIGMODE Mask */ -#define QEI_CONF_CAPMODE_Pos 2 /*!< QEI CONF: CAPMODE Position */ -#define QEI_CONF_CAPMODE_Msk (0x01UL << QEI_CONF_CAPMODE_Pos) /*!< QEI CONF: CAPMODE Mask */ -#define QEI_CONF_INVINX_Pos 3 /*!< QEI CONF: INVINX Position */ -#define QEI_CONF_INVINX_Msk (0x01UL << QEI_CONF_INVINX_Pos) /*!< QEI CONF: INVINX Mask */ -#define QEI_CONF_CRESPI_Pos 4 /*!< QEI CONF: CRESPI Position */ -#define QEI_CONF_CRESPI_Msk (0x01UL << QEI_CONF_CRESPI_Pos) /*!< QEI CONF: CRESPI Mask */ -#define QEI_CONF_INXGATE_Pos 16 /*!< QEI CONF: INXGATE Position */ -#define QEI_CONF_INXGATE_Msk (0x0fUL << QEI_CONF_INXGATE_Pos) /*!< QEI CONF: INXGATE Mask */ - -// ----------------------------------------- QEI_POS -------------------------------------------- -#define QEI_POS_POS_Pos 0 /*!< QEI POS: POS Position */ -#define QEI_POS_POS_Msk (0xffffffffUL << QEI_POS_POS_Pos) /*!< QEI POS: POS Mask */ - -// --------------------------------------- QEI_MAXPOS ------------------------------------------- -#define QEI_MAXPOS_MAXPOS_Pos 0 /*!< QEI MAXPOS: MAXPOS Position */ -#define QEI_MAXPOS_MAXPOS_Msk (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos) /*!< QEI MAXPOS: MAXPOS Mask */ - -// --------------------------------------- QEI_CMPOS0 ------------------------------------------- -#define QEI_CMPOS0_PCMP0_Pos 0 /*!< QEI CMPOS0: PCMP0 Position */ -#define QEI_CMPOS0_PCMP0_Msk (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos) /*!< QEI CMPOS0: PCMP0 Mask */ - -// --------------------------------------- QEI_CMPOS1 ------------------------------------------- -#define QEI_CMPOS1_PCMP1_Pos 0 /*!< QEI CMPOS1: PCMP1 Position */ -#define QEI_CMPOS1_PCMP1_Msk (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos) /*!< QEI CMPOS1: PCMP1 Mask */ - -// --------------------------------------- QEI_CMPOS2 ------------------------------------------- -#define QEI_CMPOS2_PCMP2_Pos 0 /*!< QEI CMPOS2: PCMP2 Position */ -#define QEI_CMPOS2_PCMP2_Msk (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos) /*!< QEI CMPOS2: PCMP2 Mask */ - -// --------------------------------------- QEI_INXCNT ------------------------------------------- -#define QEI_INXCNT_ENCPOS_Pos 0 /*!< QEI INXCNT: ENCPOS Position */ -#define QEI_INXCNT_ENCPOS_Msk (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos) /*!< QEI INXCNT: ENCPOS Mask */ - -// --------------------------------------- QEI_INXCMP0 ------------------------------------------ -#define QEI_INXCMP0_ICMP0_Pos 0 /*!< QEI INXCMP0: ICMP0 Position */ -#define QEI_INXCMP0_ICMP0_Msk (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos) /*!< QEI INXCMP0: ICMP0 Mask */ - -// ---------------------------------------- QEI_LOAD -------------------------------------------- -#define QEI_LOAD_VELLOAD_Pos 0 /*!< QEI LOAD: VELLOAD Position */ -#define QEI_LOAD_VELLOAD_Msk (0xffffffffUL << QEI_LOAD_VELLOAD_Pos) /*!< QEI LOAD: VELLOAD Mask */ - -// ---------------------------------------- QEI_TIME -------------------------------------------- -#define QEI_TIME_VELVAL_Pos 0 /*!< QEI TIME: VELVAL Position */ -#define QEI_TIME_VELVAL_Msk (0xffffffffUL << QEI_TIME_VELVAL_Pos) /*!< QEI TIME: VELVAL Mask */ - -// ----------------------------------------- QEI_VEL -------------------------------------------- -#define QEI_VEL_VELPC_Pos 0 /*!< QEI VEL: VELPC Position */ -#define QEI_VEL_VELPC_Msk (0xffffffffUL << QEI_VEL_VELPC_Pos) /*!< QEI VEL: VELPC Mask */ - -// ----------------------------------------- QEI_CAP -------------------------------------------- -#define QEI_CAP_VELCAP_Pos 0 /*!< QEI CAP: VELCAP Position */ -#define QEI_CAP_VELCAP_Msk (0xffffffffUL << QEI_CAP_VELCAP_Pos) /*!< QEI CAP: VELCAP Mask */ - -// --------------------------------------- QEI_VELCOMP ------------------------------------------ -#define QEI_VELCOMP_VELCMP_Pos 0 /*!< QEI VELCOMP: VELCMP Position */ -#define QEI_VELCOMP_VELCMP_Msk (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos) /*!< QEI VELCOMP: VELCMP Mask */ - -// -------------------------------------- QEI_FILTERPHA ----------------------------------------- -#define QEI_FILTERPHA_FILTA_Pos 0 /*!< QEI FILTERPHA: FILTA Position */ -#define QEI_FILTERPHA_FILTA_Msk (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos) /*!< QEI FILTERPHA: FILTA Mask */ - -// -------------------------------------- QEI_FILTERPHB ----------------------------------------- -#define QEI_FILTERPHB_FILTB_Pos 0 /*!< QEI FILTERPHB: FILTB Position */ -#define QEI_FILTERPHB_FILTB_Msk (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos) /*!< QEI FILTERPHB: FILTB Mask */ - -// -------------------------------------- QEI_FILTERINX ----------------------------------------- -#define QEI_FILTERINX_FITLINX_Pos 0 /*!< QEI FILTERINX: FITLINX Position */ -#define QEI_FILTERINX_FITLINX_Msk (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos) /*!< QEI FILTERINX: FITLINX Mask */ - -// --------------------------------------- QEI_WINDOW ------------------------------------------- -#define QEI_WINDOW_WINDOW_Pos 0 /*!< QEI WINDOW: WINDOW Position */ -#define QEI_WINDOW_WINDOW_Msk (0xffffffffUL << QEI_WINDOW_WINDOW_Pos) /*!< QEI WINDOW: WINDOW Mask */ - -// --------------------------------------- QEI_INXCMP1 ------------------------------------------ -#define QEI_INXCMP1_ICMP1_Pos 0 /*!< QEI INXCMP1: ICMP1 Position */ -#define QEI_INXCMP1_ICMP1_Msk (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos) /*!< QEI INXCMP1: ICMP1 Mask */ - -// --------------------------------------- QEI_INXCMP2 ------------------------------------------ -#define QEI_INXCMP2_ICMP2_Pos 0 /*!< QEI INXCMP2: ICMP2 Position */ -#define QEI_INXCMP2_ICMP2_Msk (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos) /*!< QEI INXCMP2: ICMP2 Mask */ - -// ----------------------------------------- QEI_IEC -------------------------------------------- -#define QEI_IEC_INX_EN_Pos 0 /*!< QEI IEC: INX_EN Position */ -#define QEI_IEC_INX_EN_Msk (0x01UL << QEI_IEC_INX_EN_Pos) /*!< QEI IEC: INX_EN Mask */ -#define QEI_IEC_TIM_EN_Pos 1 /*!< QEI IEC: TIM_EN Position */ -#define QEI_IEC_TIM_EN_Msk (0x01UL << QEI_IEC_TIM_EN_Pos) /*!< QEI IEC: TIM_EN Mask */ -#define QEI_IEC_VELC_EN_Pos 2 /*!< QEI IEC: VELC_EN Position */ -#define QEI_IEC_VELC_EN_Msk (0x01UL << QEI_IEC_VELC_EN_Pos) /*!< QEI IEC: VELC_EN Mask */ -#define QEI_IEC_DIR_EN_Pos 3 /*!< QEI IEC: DIR_EN Position */ -#define QEI_IEC_DIR_EN_Msk (0x01UL << QEI_IEC_DIR_EN_Pos) /*!< QEI IEC: DIR_EN Mask */ -#define QEI_IEC_ERR_EN_Pos 4 /*!< QEI IEC: ERR_EN Position */ -#define QEI_IEC_ERR_EN_Msk (0x01UL << QEI_IEC_ERR_EN_Pos) /*!< QEI IEC: ERR_EN Mask */ -#define QEI_IEC_ENCLK_EN_Pos 5 /*!< QEI IEC: ENCLK_EN Position */ -#define QEI_IEC_ENCLK_EN_Msk (0x01UL << QEI_IEC_ENCLK_EN_Pos) /*!< QEI IEC: ENCLK_EN Mask */ -#define QEI_IEC_POS0_Int_Pos 6 /*!< QEI IEC: POS0_Int Position */ -#define QEI_IEC_POS0_Int_Msk (0x01UL << QEI_IEC_POS0_Int_Pos) /*!< QEI IEC: POS0_Int Mask */ -#define QEI_IEC_POS1_Int_Pos 7 /*!< QEI IEC: POS1_Int Position */ -#define QEI_IEC_POS1_Int_Msk (0x01UL << QEI_IEC_POS1_Int_Pos) /*!< QEI IEC: POS1_Int Mask */ -#define QEI_IEC_POS2_Int_Pos 8 /*!< QEI IEC: POS2_Int Position */ -#define QEI_IEC_POS2_Int_Msk (0x01UL << QEI_IEC_POS2_Int_Pos) /*!< QEI IEC: POS2_Int Mask */ -#define QEI_IEC_REV_Int_Pos 9 /*!< QEI IEC: REV_Int Position */ -#define QEI_IEC_REV_Int_Msk (0x01UL << QEI_IEC_REV_Int_Pos) /*!< QEI IEC: REV_Int Mask */ -#define QEI_IEC_POS0REV_Int_Pos 10 /*!< QEI IEC: POS0REV_Int Position */ -#define QEI_IEC_POS0REV_Int_Msk (0x01UL << QEI_IEC_POS0REV_Int_Pos) /*!< QEI IEC: POS0REV_Int Mask */ -#define QEI_IEC_POS1REV_Int_Pos 11 /*!< QEI IEC: POS1REV_Int Position */ -#define QEI_IEC_POS1REV_Int_Msk (0x01UL << QEI_IEC_POS1REV_Int_Pos) /*!< QEI IEC: POS1REV_Int Mask */ -#define QEI_IEC_POS2REV_Int_Pos 12 /*!< QEI IEC: POS2REV_Int Position */ -#define QEI_IEC_POS2REV_Int_Msk (0x01UL << QEI_IEC_POS2REV_Int_Pos) /*!< QEI IEC: POS2REV_Int Mask */ -#define QEI_IEC_REV1_Int_Pos 13 /*!< QEI IEC: REV1_Int Position */ -#define QEI_IEC_REV1_Int_Msk (0x01UL << QEI_IEC_REV1_Int_Pos) /*!< QEI IEC: REV1_Int Mask */ -#define QEI_IEC_REV2_Int_Pos 14 /*!< QEI IEC: REV2_Int Position */ -#define QEI_IEC_REV2_Int_Msk (0x01UL << QEI_IEC_REV2_Int_Pos) /*!< QEI IEC: REV2_Int Mask */ -#define QEI_IEC_MAXPOS_Int_Pos 15 /*!< QEI IEC: MAXPOS_Int Position */ -#define QEI_IEC_MAXPOS_Int_Msk (0x01UL << QEI_IEC_MAXPOS_Int_Pos) /*!< QEI IEC: MAXPOS_Int Mask */ - -// ----------------------------------------- QEI_IES -------------------------------------------- -#define QEI_IES_INX_EN_Pos 0 /*!< QEI IES: INX_EN Position */ -#define QEI_IES_INX_EN_Msk (0x01UL << QEI_IES_INX_EN_Pos) /*!< QEI IES: INX_EN Mask */ -#define QEI_IES_TIM_EN_Pos 1 /*!< QEI IES: TIM_EN Position */ -#define QEI_IES_TIM_EN_Msk (0x01UL << QEI_IES_TIM_EN_Pos) /*!< QEI IES: TIM_EN Mask */ -#define QEI_IES_VELC_EN_Pos 2 /*!< QEI IES: VELC_EN Position */ -#define QEI_IES_VELC_EN_Msk (0x01UL << QEI_IES_VELC_EN_Pos) /*!< QEI IES: VELC_EN Mask */ -#define QEI_IES_DIR_EN_Pos 3 /*!< QEI IES: DIR_EN Position */ -#define QEI_IES_DIR_EN_Msk (0x01UL << QEI_IES_DIR_EN_Pos) /*!< QEI IES: DIR_EN Mask */ -#define QEI_IES_ERR_EN_Pos 4 /*!< QEI IES: ERR_EN Position */ -#define QEI_IES_ERR_EN_Msk (0x01UL << QEI_IES_ERR_EN_Pos) /*!< QEI IES: ERR_EN Mask */ -#define QEI_IES_ENCLK_EN_Pos 5 /*!< QEI IES: ENCLK_EN Position */ -#define QEI_IES_ENCLK_EN_Msk (0x01UL << QEI_IES_ENCLK_EN_Pos) /*!< QEI IES: ENCLK_EN Mask */ -#define QEI_IES_POS0_Int_Pos 6 /*!< QEI IES: POS0_Int Position */ -#define QEI_IES_POS0_Int_Msk (0x01UL << QEI_IES_POS0_Int_Pos) /*!< QEI IES: POS0_Int Mask */ -#define QEI_IES_POS1_Int_Pos 7 /*!< QEI IES: POS1_Int Position */ -#define QEI_IES_POS1_Int_Msk (0x01UL << QEI_IES_POS1_Int_Pos) /*!< QEI IES: POS1_Int Mask */ -#define QEI_IES_POS2_Int_Pos 8 /*!< QEI IES: POS2_Int Position */ -#define QEI_IES_POS2_Int_Msk (0x01UL << QEI_IES_POS2_Int_Pos) /*!< QEI IES: POS2_Int Mask */ -#define QEI_IES_REV_Int_Pos 9 /*!< QEI IES: REV_Int Position */ -#define QEI_IES_REV_Int_Msk (0x01UL << QEI_IES_REV_Int_Pos) /*!< QEI IES: REV_Int Mask */ -#define QEI_IES_POS0REV_Int_Pos 10 /*!< QEI IES: POS0REV_Int Position */ -#define QEI_IES_POS0REV_Int_Msk (0x01UL << QEI_IES_POS0REV_Int_Pos) /*!< QEI IES: POS0REV_Int Mask */ -#define QEI_IES_POS1REV_Int_Pos 11 /*!< QEI IES: POS1REV_Int Position */ -#define QEI_IES_POS1REV_Int_Msk (0x01UL << QEI_IES_POS1REV_Int_Pos) /*!< QEI IES: POS1REV_Int Mask */ -#define QEI_IES_POS2REV_Int_Pos 12 /*!< QEI IES: POS2REV_Int Position */ -#define QEI_IES_POS2REV_Int_Msk (0x01UL << QEI_IES_POS2REV_Int_Pos) /*!< QEI IES: POS2REV_Int Mask */ -#define QEI_IES_REV1_Int_Pos 13 /*!< QEI IES: REV1_Int Position */ -#define QEI_IES_REV1_Int_Msk (0x01UL << QEI_IES_REV1_Int_Pos) /*!< QEI IES: REV1_Int Mask */ -#define QEI_IES_REV2_Int_Pos 14 /*!< QEI IES: REV2_Int Position */ -#define QEI_IES_REV2_Int_Msk (0x01UL << QEI_IES_REV2_Int_Pos) /*!< QEI IES: REV2_Int Mask */ -#define QEI_IES_MAXPOS_Int_Pos 15 /*!< QEI IES: MAXPOS_Int Position */ -#define QEI_IES_MAXPOS_Int_Msk (0x01UL << QEI_IES_MAXPOS_Int_Pos) /*!< QEI IES: MAXPOS_Int Mask */ - -// --------------------------------------- QEI_INTSTAT ------------------------------------------ -#define QEI_INTSTAT_INX_Int_Pos 0 /*!< QEI INTSTAT: INX_Int Position */ -#define QEI_INTSTAT_INX_Int_Msk (0x01UL << QEI_INTSTAT_INX_Int_Pos) /*!< QEI INTSTAT: INX_Int Mask */ -#define QEI_INTSTAT_TIM_Int_Pos 1 /*!< QEI INTSTAT: TIM_Int Position */ -#define QEI_INTSTAT_TIM_Int_Msk (0x01UL << QEI_INTSTAT_TIM_Int_Pos) /*!< QEI INTSTAT: TIM_Int Mask */ -#define QEI_INTSTAT_VELC_Int_Pos 2 /*!< QEI INTSTAT: VELC_Int Position */ -#define QEI_INTSTAT_VELC_Int_Msk (0x01UL << QEI_INTSTAT_VELC_Int_Pos) /*!< QEI INTSTAT: VELC_Int Mask */ -#define QEI_INTSTAT_DIR_Int_Pos 3 /*!< QEI INTSTAT: DIR_Int Position */ -#define QEI_INTSTAT_DIR_Int_Msk (0x01UL << QEI_INTSTAT_DIR_Int_Pos) /*!< QEI INTSTAT: DIR_Int Mask */ -#define QEI_INTSTAT_ERR_Int_Pos 4 /*!< QEI INTSTAT: ERR_Int Position */ -#define QEI_INTSTAT_ERR_Int_Msk (0x01UL << QEI_INTSTAT_ERR_Int_Pos) /*!< QEI INTSTAT: ERR_Int Mask */ -#define QEI_INTSTAT_ENCLK_Int_Pos 5 /*!< QEI INTSTAT: ENCLK_Int Position */ -#define QEI_INTSTAT_ENCLK_Int_Msk (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos) /*!< QEI INTSTAT: ENCLK_Int Mask */ -#define QEI_INTSTAT_POS0_Int_Pos 6 /*!< QEI INTSTAT: POS0_Int Position */ -#define QEI_INTSTAT_POS0_Int_Msk (0x01UL << QEI_INTSTAT_POS0_Int_Pos) /*!< QEI INTSTAT: POS0_Int Mask */ -#define QEI_INTSTAT_POS1_Int_Pos 7 /*!< QEI INTSTAT: POS1_Int Position */ -#define QEI_INTSTAT_POS1_Int_Msk (0x01UL << QEI_INTSTAT_POS1_Int_Pos) /*!< QEI INTSTAT: POS1_Int Mask */ -#define QEI_INTSTAT_POS2_Int_Pos 8 /*!< QEI INTSTAT: POS2_Int Position */ -#define QEI_INTSTAT_POS2_Int_Msk (0x01UL << QEI_INTSTAT_POS2_Int_Pos) /*!< QEI INTSTAT: POS2_Int Mask */ -#define QEI_INTSTAT_REV_Int_Pos 9 /*!< QEI INTSTAT: REV_Int Position */ -#define QEI_INTSTAT_REV_Int_Msk (0x01UL << QEI_INTSTAT_REV_Int_Pos) /*!< QEI INTSTAT: REV_Int Mask */ -#define QEI_INTSTAT_POS0REV_Int_Pos 10 /*!< QEI INTSTAT: POS0REV_Int Position */ -#define QEI_INTSTAT_POS0REV_Int_Msk (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos) /*!< QEI INTSTAT: POS0REV_Int Mask */ -#define QEI_INTSTAT_POS1REV_Int_Pos 11 /*!< QEI INTSTAT: POS1REV_Int Position */ -#define QEI_INTSTAT_POS1REV_Int_Msk (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos) /*!< QEI INTSTAT: POS1REV_Int Mask */ -#define QEI_INTSTAT_POS2REV_Int_Pos 12 /*!< QEI INTSTAT: POS2REV_Int Position */ -#define QEI_INTSTAT_POS2REV_Int_Msk (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos) /*!< QEI INTSTAT: POS2REV_Int Mask */ -#define QEI_INTSTAT_REV1_Int_Pos 13 /*!< QEI INTSTAT: REV1_Int Position */ -#define QEI_INTSTAT_REV1_Int_Msk (0x01UL << QEI_INTSTAT_REV1_Int_Pos) /*!< QEI INTSTAT: REV1_Int Mask */ -#define QEI_INTSTAT_REV2_Int_Pos 14 /*!< QEI INTSTAT: REV2_Int Position */ -#define QEI_INTSTAT_REV2_Int_Msk (0x01UL << QEI_INTSTAT_REV2_Int_Pos) /*!< QEI INTSTAT: REV2_Int Mask */ -#define QEI_INTSTAT_MAXPOS_Int_Pos 15 /*!< QEI INTSTAT: MAXPOS_Int Position */ -#define QEI_INTSTAT_MAXPOS_Int_Msk (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos) /*!< QEI INTSTAT: MAXPOS_Int Mask */ - -// ----------------------------------------- QEI_IE --------------------------------------------- -#define QEI_IE_INX_Int_Pos 0 /*!< QEI IE: INX_Int Position */ -#define QEI_IE_INX_Int_Msk (0x01UL << QEI_IE_INX_Int_Pos) /*!< QEI IE: INX_Int Mask */ -#define QEI_IE_TIM_Int_Pos 1 /*!< QEI IE: TIM_Int Position */ -#define QEI_IE_TIM_Int_Msk (0x01UL << QEI_IE_TIM_Int_Pos) /*!< QEI IE: TIM_Int Mask */ -#define QEI_IE_VELC_Int_Pos 2 /*!< QEI IE: VELC_Int Position */ -#define QEI_IE_VELC_Int_Msk (0x01UL << QEI_IE_VELC_Int_Pos) /*!< QEI IE: VELC_Int Mask */ -#define QEI_IE_DIR_Int_Pos 3 /*!< QEI IE: DIR_Int Position */ -#define QEI_IE_DIR_Int_Msk (0x01UL << QEI_IE_DIR_Int_Pos) /*!< QEI IE: DIR_Int Mask */ -#define QEI_IE_ERR_Int_Pos 4 /*!< QEI IE: ERR_Int Position */ -#define QEI_IE_ERR_Int_Msk (0x01UL << QEI_IE_ERR_Int_Pos) /*!< QEI IE: ERR_Int Mask */ -#define QEI_IE_ENCLK_Int_Pos 5 /*!< QEI IE: ENCLK_Int Position */ -#define QEI_IE_ENCLK_Int_Msk (0x01UL << QEI_IE_ENCLK_Int_Pos) /*!< QEI IE: ENCLK_Int Mask */ -#define QEI_IE_POS0_Int_Pos 6 /*!< QEI IE: POS0_Int Position */ -#define QEI_IE_POS0_Int_Msk (0x01UL << QEI_IE_POS0_Int_Pos) /*!< QEI IE: POS0_Int Mask */ -#define QEI_IE_POS1_Int_Pos 7 /*!< QEI IE: POS1_Int Position */ -#define QEI_IE_POS1_Int_Msk (0x01UL << QEI_IE_POS1_Int_Pos) /*!< QEI IE: POS1_Int Mask */ -#define QEI_IE_POS2_Int_Pos 8 /*!< QEI IE: POS2_Int Position */ -#define QEI_IE_POS2_Int_Msk (0x01UL << QEI_IE_POS2_Int_Pos) /*!< QEI IE: POS2_Int Mask */ -#define QEI_IE_REV_Int_Pos 9 /*!< QEI IE: REV_Int Position */ -#define QEI_IE_REV_Int_Msk (0x01UL << QEI_IE_REV_Int_Pos) /*!< QEI IE: REV_Int Mask */ -#define QEI_IE_POS0REV_Int_Pos 10 /*!< QEI IE: POS0REV_Int Position */ -#define QEI_IE_POS0REV_Int_Msk (0x01UL << QEI_IE_POS0REV_Int_Pos) /*!< QEI IE: POS0REV_Int Mask */ -#define QEI_IE_POS1REV_Int_Pos 11 /*!< QEI IE: POS1REV_Int Position */ -#define QEI_IE_POS1REV_Int_Msk (0x01UL << QEI_IE_POS1REV_Int_Pos) /*!< QEI IE: POS1REV_Int Mask */ -#define QEI_IE_POS2REV_Int_Pos 12 /*!< QEI IE: POS2REV_Int Position */ -#define QEI_IE_POS2REV_Int_Msk (0x01UL << QEI_IE_POS2REV_Int_Pos) /*!< QEI IE: POS2REV_Int Mask */ -#define QEI_IE_REV1_Int_Pos 13 /*!< QEI IE: REV1_Int Position */ -#define QEI_IE_REV1_Int_Msk (0x01UL << QEI_IE_REV1_Int_Pos) /*!< QEI IE: REV1_Int Mask */ -#define QEI_IE_REV2_Int_Pos 14 /*!< QEI IE: REV2_Int Position */ -#define QEI_IE_REV2_Int_Msk (0x01UL << QEI_IE_REV2_Int_Pos) /*!< QEI IE: REV2_Int Mask */ -#define QEI_IE_MAXPOS_Int_Pos 15 /*!< QEI IE: MAXPOS_Int Position */ -#define QEI_IE_MAXPOS_Int_Msk (0x01UL << QEI_IE_MAXPOS_Int_Pos) /*!< QEI IE: MAXPOS_Int Mask */ - -// ----------------------------------------- QEI_CLR -------------------------------------------- -#define QEI_CLR_INX_Int_Pos 0 /*!< QEI CLR: INX_Int Position */ -#define QEI_CLR_INX_Int_Msk (0x01UL << QEI_CLR_INX_Int_Pos) /*!< QEI CLR: INX_Int Mask */ -#define QEI_CLR_TIM_Int_Pos 1 /*!< QEI CLR: TIM_Int Position */ -#define QEI_CLR_TIM_Int_Msk (0x01UL << QEI_CLR_TIM_Int_Pos) /*!< QEI CLR: TIM_Int Mask */ -#define QEI_CLR_VELC_Int_Pos 2 /*!< QEI CLR: VELC_Int Position */ -#define QEI_CLR_VELC_Int_Msk (0x01UL << QEI_CLR_VELC_Int_Pos) /*!< QEI CLR: VELC_Int Mask */ -#define QEI_CLR_DIR_Int_Pos 3 /*!< QEI CLR: DIR_Int Position */ -#define QEI_CLR_DIR_Int_Msk (0x01UL << QEI_CLR_DIR_Int_Pos) /*!< QEI CLR: DIR_Int Mask */ -#define QEI_CLR_ERR_Int_Pos 4 /*!< QEI CLR: ERR_Int Position */ -#define QEI_CLR_ERR_Int_Msk (0x01UL << QEI_CLR_ERR_Int_Pos) /*!< QEI CLR: ERR_Int Mask */ -#define QEI_CLR_ENCLK_Int_Pos 5 /*!< QEI CLR: ENCLK_Int Position */ -#define QEI_CLR_ENCLK_Int_Msk (0x01UL << QEI_CLR_ENCLK_Int_Pos) /*!< QEI CLR: ENCLK_Int Mask */ -#define QEI_CLR_POS0_Int_Pos 6 /*!< QEI CLR: POS0_Int Position */ -#define QEI_CLR_POS0_Int_Msk (0x01UL << QEI_CLR_POS0_Int_Pos) /*!< QEI CLR: POS0_Int Mask */ -#define QEI_CLR_POS1_Int_Pos 7 /*!< QEI CLR: POS1_Int Position */ -#define QEI_CLR_POS1_Int_Msk (0x01UL << QEI_CLR_POS1_Int_Pos) /*!< QEI CLR: POS1_Int Mask */ -#define QEI_CLR_POS2_Int_Pos 8 /*!< QEI CLR: POS2_Int Position */ -#define QEI_CLR_POS2_Int_Msk (0x01UL << QEI_CLR_POS2_Int_Pos) /*!< QEI CLR: POS2_Int Mask */ -#define QEI_CLR_REV_Int_Pos 9 /*!< QEI CLR: REV_Int Position */ -#define QEI_CLR_REV_Int_Msk (0x01UL << QEI_CLR_REV_Int_Pos) /*!< QEI CLR: REV_Int Mask */ -#define QEI_CLR_POS0REV_Int_Pos 10 /*!< QEI CLR: POS0REV_Int Position */ -#define QEI_CLR_POS0REV_Int_Msk (0x01UL << QEI_CLR_POS0REV_Int_Pos) /*!< QEI CLR: POS0REV_Int Mask */ -#define QEI_CLR_POS1REV_Int_Pos 11 /*!< QEI CLR: POS1REV_Int Position */ -#define QEI_CLR_POS1REV_Int_Msk (0x01UL << QEI_CLR_POS1REV_Int_Pos) /*!< QEI CLR: POS1REV_Int Mask */ -#define QEI_CLR_REV1_Int_Pos 13 /*!< QEI CLR: REV1_Int Position */ -#define QEI_CLR_REV1_Int_Msk (0x01UL << QEI_CLR_REV1_Int_Pos) /*!< QEI CLR: REV1_Int Mask */ -#define QEI_CLR_REV2_Int_Pos 14 /*!< QEI CLR: REV2_Int Position */ -#define QEI_CLR_REV2_Int_Msk (0x01UL << QEI_CLR_REV2_Int_Pos) /*!< QEI CLR: REV2_Int Mask */ -#define QEI_CLR_MAXPOS_Int_Pos 15 /*!< QEI CLR: MAXPOS_Int Position */ -#define QEI_CLR_MAXPOS_Int_Msk (0x01UL << QEI_CLR_MAXPOS_Int_Pos) /*!< QEI CLR: MAXPOS_Int Mask */ - -// ----------------------------------------- QEI_SET -------------------------------------------- -#define QEI_SET_INX_Int_Pos 0 /*!< QEI SET: INX_Int Position */ -#define QEI_SET_INX_Int_Msk (0x01UL << QEI_SET_INX_Int_Pos) /*!< QEI SET: INX_Int Mask */ -#define QEI_SET_TIM_Int_Pos 1 /*!< QEI SET: TIM_Int Position */ -#define QEI_SET_TIM_Int_Msk (0x01UL << QEI_SET_TIM_Int_Pos) /*!< QEI SET: TIM_Int Mask */ -#define QEI_SET_VELC_Int_Pos 2 /*!< QEI SET: VELC_Int Position */ -#define QEI_SET_VELC_Int_Msk (0x01UL << QEI_SET_VELC_Int_Pos) /*!< QEI SET: VELC_Int Mask */ -#define QEI_SET_DIR_Int_Pos 3 /*!< QEI SET: DIR_Int Position */ -#define QEI_SET_DIR_Int_Msk (0x01UL << QEI_SET_DIR_Int_Pos) /*!< QEI SET: DIR_Int Mask */ -#define QEI_SET_ERR_Int_Pos 4 /*!< QEI SET: ERR_Int Position */ -#define QEI_SET_ERR_Int_Msk (0x01UL << QEI_SET_ERR_Int_Pos) /*!< QEI SET: ERR_Int Mask */ -#define QEI_SET_ENCLK_Int_Pos 5 /*!< QEI SET: ENCLK_Int Position */ -#define QEI_SET_ENCLK_Int_Msk (0x01UL << QEI_SET_ENCLK_Int_Pos) /*!< QEI SET: ENCLK_Int Mask */ -#define QEI_SET_POS0_Int_Pos 6 /*!< QEI SET: POS0_Int Position */ -#define QEI_SET_POS0_Int_Msk (0x01UL << QEI_SET_POS0_Int_Pos) /*!< QEI SET: POS0_Int Mask */ -#define QEI_SET_POS1_Int_Pos 7 /*!< QEI SET: POS1_Int Position */ -#define QEI_SET_POS1_Int_Msk (0x01UL << QEI_SET_POS1_Int_Pos) /*!< QEI SET: POS1_Int Mask */ -#define QEI_SET_POS2_Int_Pos 8 /*!< QEI SET: POS2_Int Position */ -#define QEI_SET_POS2_Int_Msk (0x01UL << QEI_SET_POS2_Int_Pos) /*!< QEI SET: POS2_Int Mask */ -#define QEI_SET_REV_Int_Pos 9 /*!< QEI SET: REV_Int Position */ -#define QEI_SET_REV_Int_Msk (0x01UL << QEI_SET_REV_Int_Pos) /*!< QEI SET: REV_Int Mask */ -#define QEI_SET_POS0REV_Int_Pos 10 /*!< QEI SET: POS0REV_Int Position */ -#define QEI_SET_POS0REV_Int_Msk (0x01UL << QEI_SET_POS0REV_Int_Pos) /*!< QEI SET: POS0REV_Int Mask */ -#define QEI_SET_POS1REV_Int_Pos 11 /*!< QEI SET: POS1REV_Int Position */ -#define QEI_SET_POS1REV_Int_Msk (0x01UL << QEI_SET_POS1REV_Int_Pos) /*!< QEI SET: POS1REV_Int Mask */ -#define QEI_SET_POS2REV_Int_Pos 12 /*!< QEI SET: POS2REV_Int Position */ -#define QEI_SET_POS2REV_Int_Msk (0x01UL << QEI_SET_POS2REV_Int_Pos) /*!< QEI SET: POS2REV_Int Mask */ -#define QEI_SET_REV1_Int_Pos 13 /*!< QEI SET: REV1_Int Position */ -#define QEI_SET_REV1_Int_Msk (0x01UL << QEI_SET_REV1_Int_Pos) /*!< QEI SET: REV1_Int Mask */ -#define QEI_SET_REV2_Int_Pos 14 /*!< QEI SET: REV2_Int Position */ -#define QEI_SET_REV2_Int_Msk (0x01UL << QEI_SET_REV2_Int_Pos) /*!< QEI SET: REV2_Int Mask */ -#define QEI_SET_MAXPOS_Int_Pos 15 /*!< QEI SET: MAXPOS_Int Position */ -#define QEI_SET_MAXPOS_Int_Msk (0x01UL << QEI_SET_MAXPOS_Int_Pos) /*!< QEI SET: MAXPOS_Int Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GIMA Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- GIMA_CAP0_0_IN ----------------------------------------- -#define GIMA_CAP0_0_IN_INV_Pos 0 /*!< GIMA CAP0_0_IN: INV Position */ -#define GIMA_CAP0_0_IN_INV_Msk (0x01UL << GIMA_CAP0_0_IN_INV_Pos) /*!< GIMA CAP0_0_IN: INV Mask */ -#define GIMA_CAP0_0_IN_EDGE_Pos 1 /*!< GIMA CAP0_0_IN: EDGE Position */ -#define GIMA_CAP0_0_IN_EDGE_Msk (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos) /*!< GIMA CAP0_0_IN: EDGE Mask */ -#define GIMA_CAP0_0_IN_SYNCH_Pos 2 /*!< GIMA CAP0_0_IN: SYNCH Position */ -#define GIMA_CAP0_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos) /*!< GIMA CAP0_0_IN: SYNCH Mask */ -#define GIMA_CAP0_0_IN_PULSE_Pos 3 /*!< GIMA CAP0_0_IN: PULSE Position */ -#define GIMA_CAP0_0_IN_PULSE_Msk (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos) /*!< GIMA CAP0_0_IN: PULSE Mask */ -#define GIMA_CAP0_0_IN_SELECT_Pos 4 /*!< GIMA CAP0_0_IN: SELECT Position */ -#define GIMA_CAP0_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos) /*!< GIMA CAP0_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP0_1_IN ----------------------------------------- -#define GIMA_CAP0_1_IN_INV_Pos 0 /*!< GIMA CAP0_1_IN: INV Position */ -#define GIMA_CAP0_1_IN_INV_Msk (0x01UL << GIMA_CAP0_1_IN_INV_Pos) /*!< GIMA CAP0_1_IN: INV Mask */ -#define GIMA_CAP0_1_IN_EDGE_Pos 1 /*!< GIMA CAP0_1_IN: EDGE Position */ -#define GIMA_CAP0_1_IN_EDGE_Msk (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos) /*!< GIMA CAP0_1_IN: EDGE Mask */ -#define GIMA_CAP0_1_IN_SYNCH_Pos 2 /*!< GIMA CAP0_1_IN: SYNCH Position */ -#define GIMA_CAP0_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos) /*!< GIMA CAP0_1_IN: SYNCH Mask */ -#define GIMA_CAP0_1_IN_PULSE_Pos 3 /*!< GIMA CAP0_1_IN: PULSE Position */ -#define GIMA_CAP0_1_IN_PULSE_Msk (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos) /*!< GIMA CAP0_1_IN: PULSE Mask */ -#define GIMA_CAP0_1_IN_SELECT_Pos 4 /*!< GIMA CAP0_1_IN: SELECT Position */ -#define GIMA_CAP0_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos) /*!< GIMA CAP0_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP0_2_IN ----------------------------------------- -#define GIMA_CAP0_2_IN_INV_Pos 0 /*!< GIMA CAP0_2_IN: INV Position */ -#define GIMA_CAP0_2_IN_INV_Msk (0x01UL << GIMA_CAP0_2_IN_INV_Pos) /*!< GIMA CAP0_2_IN: INV Mask */ -#define GIMA_CAP0_2_IN_EDGE_Pos 1 /*!< GIMA CAP0_2_IN: EDGE Position */ -#define GIMA_CAP0_2_IN_EDGE_Msk (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos) /*!< GIMA CAP0_2_IN: EDGE Mask */ -#define GIMA_CAP0_2_IN_SYNCH_Pos 2 /*!< GIMA CAP0_2_IN: SYNCH Position */ -#define GIMA_CAP0_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos) /*!< GIMA CAP0_2_IN: SYNCH Mask */ -#define GIMA_CAP0_2_IN_PULSE_Pos 3 /*!< GIMA CAP0_2_IN: PULSE Position */ -#define GIMA_CAP0_2_IN_PULSE_Msk (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos) /*!< GIMA CAP0_2_IN: PULSE Mask */ -#define GIMA_CAP0_2_IN_SELECT_Pos 4 /*!< GIMA CAP0_2_IN: SELECT Position */ -#define GIMA_CAP0_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos) /*!< GIMA CAP0_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP0_3_IN ----------------------------------------- -#define GIMA_CAP0_3_IN_INV_Pos 0 /*!< GIMA CAP0_3_IN: INV Position */ -#define GIMA_CAP0_3_IN_INV_Msk (0x01UL << GIMA_CAP0_3_IN_INV_Pos) /*!< GIMA CAP0_3_IN: INV Mask */ -#define GIMA_CAP0_3_IN_EDGE_Pos 1 /*!< GIMA CAP0_3_IN: EDGE Position */ -#define GIMA_CAP0_3_IN_EDGE_Msk (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos) /*!< GIMA CAP0_3_IN: EDGE Mask */ -#define GIMA_CAP0_3_IN_SYNCH_Pos 2 /*!< GIMA CAP0_3_IN: SYNCH Position */ -#define GIMA_CAP0_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos) /*!< GIMA CAP0_3_IN: SYNCH Mask */ -#define GIMA_CAP0_3_IN_PULSE_Pos 3 /*!< GIMA CAP0_3_IN: PULSE Position */ -#define GIMA_CAP0_3_IN_PULSE_Msk (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos) /*!< GIMA CAP0_3_IN: PULSE Mask */ -#define GIMA_CAP0_3_IN_SELECT_Pos 4 /*!< GIMA CAP0_3_IN: SELECT Position */ -#define GIMA_CAP0_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos) /*!< GIMA CAP0_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP1_0_IN ----------------------------------------- -#define GIMA_CAP1_0_IN_INV_Pos 0 /*!< GIMA CAP1_0_IN: INV Position */ -#define GIMA_CAP1_0_IN_INV_Msk (0x01UL << GIMA_CAP1_0_IN_INV_Pos) /*!< GIMA CAP1_0_IN: INV Mask */ -#define GIMA_CAP1_0_IN_EDGE_Pos 1 /*!< GIMA CAP1_0_IN: EDGE Position */ -#define GIMA_CAP1_0_IN_EDGE_Msk (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos) /*!< GIMA CAP1_0_IN: EDGE Mask */ -#define GIMA_CAP1_0_IN_SYNCH_Pos 2 /*!< GIMA CAP1_0_IN: SYNCH Position */ -#define GIMA_CAP1_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos) /*!< GIMA CAP1_0_IN: SYNCH Mask */ -#define GIMA_CAP1_0_IN_PULSE_Pos 3 /*!< GIMA CAP1_0_IN: PULSE Position */ -#define GIMA_CAP1_0_IN_PULSE_Msk (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos) /*!< GIMA CAP1_0_IN: PULSE Mask */ -#define GIMA_CAP1_0_IN_SELECT_Pos 4 /*!< GIMA CAP1_0_IN: SELECT Position */ -#define GIMA_CAP1_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos) /*!< GIMA CAP1_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP1_1_IN ----------------------------------------- -#define GIMA_CAP1_1_IN_INV_Pos 0 /*!< GIMA CAP1_1_IN: INV Position */ -#define GIMA_CAP1_1_IN_INV_Msk (0x01UL << GIMA_CAP1_1_IN_INV_Pos) /*!< GIMA CAP1_1_IN: INV Mask */ -#define GIMA_CAP1_1_IN_EDGE_Pos 1 /*!< GIMA CAP1_1_IN: EDGE Position */ -#define GIMA_CAP1_1_IN_EDGE_Msk (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos) /*!< GIMA CAP1_1_IN: EDGE Mask */ -#define GIMA_CAP1_1_IN_SYNCH_Pos 2 /*!< GIMA CAP1_1_IN: SYNCH Position */ -#define GIMA_CAP1_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos) /*!< GIMA CAP1_1_IN: SYNCH Mask */ -#define GIMA_CAP1_1_IN_PULSE_Pos 3 /*!< GIMA CAP1_1_IN: PULSE Position */ -#define GIMA_CAP1_1_IN_PULSE_Msk (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos) /*!< GIMA CAP1_1_IN: PULSE Mask */ -#define GIMA_CAP1_1_IN_SELECT_Pos 4 /*!< GIMA CAP1_1_IN: SELECT Position */ -#define GIMA_CAP1_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos) /*!< GIMA CAP1_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP1_2_IN ----------------------------------------- -#define GIMA_CAP1_2_IN_INV_Pos 0 /*!< GIMA CAP1_2_IN: INV Position */ -#define GIMA_CAP1_2_IN_INV_Msk (0x01UL << GIMA_CAP1_2_IN_INV_Pos) /*!< GIMA CAP1_2_IN: INV Mask */ -#define GIMA_CAP1_2_IN_EDGE_Pos 1 /*!< GIMA CAP1_2_IN: EDGE Position */ -#define GIMA_CAP1_2_IN_EDGE_Msk (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos) /*!< GIMA CAP1_2_IN: EDGE Mask */ -#define GIMA_CAP1_2_IN_SYNCH_Pos 2 /*!< GIMA CAP1_2_IN: SYNCH Position */ -#define GIMA_CAP1_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos) /*!< GIMA CAP1_2_IN: SYNCH Mask */ -#define GIMA_CAP1_2_IN_PULSE_Pos 3 /*!< GIMA CAP1_2_IN: PULSE Position */ -#define GIMA_CAP1_2_IN_PULSE_Msk (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos) /*!< GIMA CAP1_2_IN: PULSE Mask */ -#define GIMA_CAP1_2_IN_SELECT_Pos 4 /*!< GIMA CAP1_2_IN: SELECT Position */ -#define GIMA_CAP1_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos) /*!< GIMA CAP1_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP1_3_IN ----------------------------------------- -#define GIMA_CAP1_3_IN_INV_Pos 0 /*!< GIMA CAP1_3_IN: INV Position */ -#define GIMA_CAP1_3_IN_INV_Msk (0x01UL << GIMA_CAP1_3_IN_INV_Pos) /*!< GIMA CAP1_3_IN: INV Mask */ -#define GIMA_CAP1_3_IN_EDGE_Pos 1 /*!< GIMA CAP1_3_IN: EDGE Position */ -#define GIMA_CAP1_3_IN_EDGE_Msk (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos) /*!< GIMA CAP1_3_IN: EDGE Mask */ -#define GIMA_CAP1_3_IN_SYNCH_Pos 2 /*!< GIMA CAP1_3_IN: SYNCH Position */ -#define GIMA_CAP1_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos) /*!< GIMA CAP1_3_IN: SYNCH Mask */ -#define GIMA_CAP1_3_IN_PULSE_Pos 3 /*!< GIMA CAP1_3_IN: PULSE Position */ -#define GIMA_CAP1_3_IN_PULSE_Msk (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos) /*!< GIMA CAP1_3_IN: PULSE Mask */ -#define GIMA_CAP1_3_IN_SELECT_Pos 4 /*!< GIMA CAP1_3_IN: SELECT Position */ -#define GIMA_CAP1_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos) /*!< GIMA CAP1_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP2_0_IN ----------------------------------------- -#define GIMA_CAP2_0_IN_INV_Pos 0 /*!< GIMA CAP2_0_IN: INV Position */ -#define GIMA_CAP2_0_IN_INV_Msk (0x01UL << GIMA_CAP2_0_IN_INV_Pos) /*!< GIMA CAP2_0_IN: INV Mask */ -#define GIMA_CAP2_0_IN_EDGE_Pos 1 /*!< GIMA CAP2_0_IN: EDGE Position */ -#define GIMA_CAP2_0_IN_EDGE_Msk (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos) /*!< GIMA CAP2_0_IN: EDGE Mask */ -#define GIMA_CAP2_0_IN_SYNCH_Pos 2 /*!< GIMA CAP2_0_IN: SYNCH Position */ -#define GIMA_CAP2_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos) /*!< GIMA CAP2_0_IN: SYNCH Mask */ -#define GIMA_CAP2_0_IN_PULSE_Pos 3 /*!< GIMA CAP2_0_IN: PULSE Position */ -#define GIMA_CAP2_0_IN_PULSE_Msk (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos) /*!< GIMA CAP2_0_IN: PULSE Mask */ -#define GIMA_CAP2_0_IN_SELECT_Pos 4 /*!< GIMA CAP2_0_IN: SELECT Position */ -#define GIMA_CAP2_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos) /*!< GIMA CAP2_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP2_1_IN ----------------------------------------- -#define GIMA_CAP2_1_IN_INV_Pos 0 /*!< GIMA CAP2_1_IN: INV Position */ -#define GIMA_CAP2_1_IN_INV_Msk (0x01UL << GIMA_CAP2_1_IN_INV_Pos) /*!< GIMA CAP2_1_IN: INV Mask */ -#define GIMA_CAP2_1_IN_EDGE_Pos 1 /*!< GIMA CAP2_1_IN: EDGE Position */ -#define GIMA_CAP2_1_IN_EDGE_Msk (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos) /*!< GIMA CAP2_1_IN: EDGE Mask */ -#define GIMA_CAP2_1_IN_SYNCH_Pos 2 /*!< GIMA CAP2_1_IN: SYNCH Position */ -#define GIMA_CAP2_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos) /*!< GIMA CAP2_1_IN: SYNCH Mask */ -#define GIMA_CAP2_1_IN_PULSE_Pos 3 /*!< GIMA CAP2_1_IN: PULSE Position */ -#define GIMA_CAP2_1_IN_PULSE_Msk (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos) /*!< GIMA CAP2_1_IN: PULSE Mask */ -#define GIMA_CAP2_1_IN_SELECT_Pos 4 /*!< GIMA CAP2_1_IN: SELECT Position */ -#define GIMA_CAP2_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos) /*!< GIMA CAP2_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP2_2_IN ----------------------------------------- -#define GIMA_CAP2_2_IN_INV_Pos 0 /*!< GIMA CAP2_2_IN: INV Position */ -#define GIMA_CAP2_2_IN_INV_Msk (0x01UL << GIMA_CAP2_2_IN_INV_Pos) /*!< GIMA CAP2_2_IN: INV Mask */ -#define GIMA_CAP2_2_IN_EDGE_Pos 1 /*!< GIMA CAP2_2_IN: EDGE Position */ -#define GIMA_CAP2_2_IN_EDGE_Msk (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos) /*!< GIMA CAP2_2_IN: EDGE Mask */ -#define GIMA_CAP2_2_IN_SYNCH_Pos 2 /*!< GIMA CAP2_2_IN: SYNCH Position */ -#define GIMA_CAP2_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos) /*!< GIMA CAP2_2_IN: SYNCH Mask */ -#define GIMA_CAP2_2_IN_PULSE_Pos 3 /*!< GIMA CAP2_2_IN: PULSE Position */ -#define GIMA_CAP2_2_IN_PULSE_Msk (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos) /*!< GIMA CAP2_2_IN: PULSE Mask */ -#define GIMA_CAP2_2_IN_SELECT_Pos 4 /*!< GIMA CAP2_2_IN: SELECT Position */ -#define GIMA_CAP2_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos) /*!< GIMA CAP2_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP2_3_IN ----------------------------------------- -#define GIMA_CAP2_3_IN_INV_Pos 0 /*!< GIMA CAP2_3_IN: INV Position */ -#define GIMA_CAP2_3_IN_INV_Msk (0x01UL << GIMA_CAP2_3_IN_INV_Pos) /*!< GIMA CAP2_3_IN: INV Mask */ -#define GIMA_CAP2_3_IN_EDGE_Pos 1 /*!< GIMA CAP2_3_IN: EDGE Position */ -#define GIMA_CAP2_3_IN_EDGE_Msk (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos) /*!< GIMA CAP2_3_IN: EDGE Mask */ -#define GIMA_CAP2_3_IN_SYNCH_Pos 2 /*!< GIMA CAP2_3_IN: SYNCH Position */ -#define GIMA_CAP2_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos) /*!< GIMA CAP2_3_IN: SYNCH Mask */ -#define GIMA_CAP2_3_IN_PULSE_Pos 3 /*!< GIMA CAP2_3_IN: PULSE Position */ -#define GIMA_CAP2_3_IN_PULSE_Msk (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos) /*!< GIMA CAP2_3_IN: PULSE Mask */ -#define GIMA_CAP2_3_IN_SELECT_Pos 4 /*!< GIMA CAP2_3_IN: SELECT Position */ -#define GIMA_CAP2_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos) /*!< GIMA CAP2_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP3_0_IN ----------------------------------------- -#define GIMA_CAP3_0_IN_INV_Pos 0 /*!< GIMA CAP3_0_IN: INV Position */ -#define GIMA_CAP3_0_IN_INV_Msk (0x01UL << GIMA_CAP3_0_IN_INV_Pos) /*!< GIMA CAP3_0_IN: INV Mask */ -#define GIMA_CAP3_0_IN_EDGE_Pos 1 /*!< GIMA CAP3_0_IN: EDGE Position */ -#define GIMA_CAP3_0_IN_EDGE_Msk (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos) /*!< GIMA CAP3_0_IN: EDGE Mask */ -#define GIMA_CAP3_0_IN_SYNCH_Pos 2 /*!< GIMA CAP3_0_IN: SYNCH Position */ -#define GIMA_CAP3_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos) /*!< GIMA CAP3_0_IN: SYNCH Mask */ -#define GIMA_CAP3_0_IN_PULSE_Pos 3 /*!< GIMA CAP3_0_IN: PULSE Position */ -#define GIMA_CAP3_0_IN_PULSE_Msk (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos) /*!< GIMA CAP3_0_IN: PULSE Mask */ -#define GIMA_CAP3_0_IN_SELECT_Pos 4 /*!< GIMA CAP3_0_IN: SELECT Position */ -#define GIMA_CAP3_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos) /*!< GIMA CAP3_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP3_1_IN ----------------------------------------- -#define GIMA_CAP3_1_IN_INV_Pos 0 /*!< GIMA CAP3_1_IN: INV Position */ -#define GIMA_CAP3_1_IN_INV_Msk (0x01UL << GIMA_CAP3_1_IN_INV_Pos) /*!< GIMA CAP3_1_IN: INV Mask */ -#define GIMA_CAP3_1_IN_EDGE_Pos 1 /*!< GIMA CAP3_1_IN: EDGE Position */ -#define GIMA_CAP3_1_IN_EDGE_Msk (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos) /*!< GIMA CAP3_1_IN: EDGE Mask */ -#define GIMA_CAP3_1_IN_SYNCH_Pos 2 /*!< GIMA CAP3_1_IN: SYNCH Position */ -#define GIMA_CAP3_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos) /*!< GIMA CAP3_1_IN: SYNCH Mask */ -#define GIMA_CAP3_1_IN_PULSE_Pos 3 /*!< GIMA CAP3_1_IN: PULSE Position */ -#define GIMA_CAP3_1_IN_PULSE_Msk (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos) /*!< GIMA CAP3_1_IN: PULSE Mask */ -#define GIMA_CAP3_1_IN_SELECT_Pos 4 /*!< GIMA CAP3_1_IN: SELECT Position */ -#define GIMA_CAP3_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos) /*!< GIMA CAP3_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP3_2_IN ----------------------------------------- -#define GIMA_CAP3_2_IN_INV_Pos 0 /*!< GIMA CAP3_2_IN: INV Position */ -#define GIMA_CAP3_2_IN_INV_Msk (0x01UL << GIMA_CAP3_2_IN_INV_Pos) /*!< GIMA CAP3_2_IN: INV Mask */ -#define GIMA_CAP3_2_IN_EDGE_Pos 1 /*!< GIMA CAP3_2_IN: EDGE Position */ -#define GIMA_CAP3_2_IN_EDGE_Msk (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos) /*!< GIMA CAP3_2_IN: EDGE Mask */ -#define GIMA_CAP3_2_IN_SYNCH_Pos 2 /*!< GIMA CAP3_2_IN: SYNCH Position */ -#define GIMA_CAP3_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos) /*!< GIMA CAP3_2_IN: SYNCH Mask */ -#define GIMA_CAP3_2_IN_PULSE_Pos 3 /*!< GIMA CAP3_2_IN: PULSE Position */ -#define GIMA_CAP3_2_IN_PULSE_Msk (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos) /*!< GIMA CAP3_2_IN: PULSE Mask */ -#define GIMA_CAP3_2_IN_SELECT_Pos 4 /*!< GIMA CAP3_2_IN: SELECT Position */ -#define GIMA_CAP3_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos) /*!< GIMA CAP3_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP3_3_IN ----------------------------------------- -#define GIMA_CAP3_3_IN_INV_Pos 0 /*!< GIMA CAP3_3_IN: INV Position */ -#define GIMA_CAP3_3_IN_INV_Msk (0x01UL << GIMA_CAP3_3_IN_INV_Pos) /*!< GIMA CAP3_3_IN: INV Mask */ -#define GIMA_CAP3_3_IN_EDGE_Pos 1 /*!< GIMA CAP3_3_IN: EDGE Position */ -#define GIMA_CAP3_3_IN_EDGE_Msk (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos) /*!< GIMA CAP3_3_IN: EDGE Mask */ -#define GIMA_CAP3_3_IN_SYNCH_Pos 2 /*!< GIMA CAP3_3_IN: SYNCH Position */ -#define GIMA_CAP3_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos) /*!< GIMA CAP3_3_IN: SYNCH Mask */ -#define GIMA_CAP3_3_IN_PULSE_Pos 3 /*!< GIMA CAP3_3_IN: PULSE Position */ -#define GIMA_CAP3_3_IN_PULSE_Msk (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos) /*!< GIMA CAP3_3_IN: PULSE Mask */ -#define GIMA_CAP3_3_IN_SELECT_Pos 4 /*!< GIMA CAP3_3_IN: SELECT Position */ -#define GIMA_CAP3_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos) /*!< GIMA CAP3_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_0_IN ----------------------------------------- -#define GIMA_CTIN_0_IN_INV_Pos 0 /*!< GIMA CTIN_0_IN: INV Position */ -#define GIMA_CTIN_0_IN_INV_Msk (0x01UL << GIMA_CTIN_0_IN_INV_Pos) /*!< GIMA CTIN_0_IN: INV Mask */ -#define GIMA_CTIN_0_IN_EDGE_Pos 1 /*!< GIMA CTIN_0_IN: EDGE Position */ -#define GIMA_CTIN_0_IN_EDGE_Msk (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos) /*!< GIMA CTIN_0_IN: EDGE Mask */ -#define GIMA_CTIN_0_IN_SYNCH_Pos 2 /*!< GIMA CTIN_0_IN: SYNCH Position */ -#define GIMA_CTIN_0_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos) /*!< GIMA CTIN_0_IN: SYNCH Mask */ -#define GIMA_CTIN_0_IN_PULSE_Pos 3 /*!< GIMA CTIN_0_IN: PULSE Position */ -#define GIMA_CTIN_0_IN_PULSE_Msk (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos) /*!< GIMA CTIN_0_IN: PULSE Mask */ -#define GIMA_CTIN_0_IN_SELECT_Pos 4 /*!< GIMA CTIN_0_IN: SELECT Position */ -#define GIMA_CTIN_0_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos) /*!< GIMA CTIN_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_1_IN ----------------------------------------- -#define GIMA_CTIN_1_IN_INV_Pos 0 /*!< GIMA CTIN_1_IN: INV Position */ -#define GIMA_CTIN_1_IN_INV_Msk (0x01UL << GIMA_CTIN_1_IN_INV_Pos) /*!< GIMA CTIN_1_IN: INV Mask */ -#define GIMA_CTIN_1_IN_EDGE_Pos 1 /*!< GIMA CTIN_1_IN: EDGE Position */ -#define GIMA_CTIN_1_IN_EDGE_Msk (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos) /*!< GIMA CTIN_1_IN: EDGE Mask */ -#define GIMA_CTIN_1_IN_SYNCH_Pos 2 /*!< GIMA CTIN_1_IN: SYNCH Position */ -#define GIMA_CTIN_1_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos) /*!< GIMA CTIN_1_IN: SYNCH Mask */ -#define GIMA_CTIN_1_IN_PULSE_Pos 3 /*!< GIMA CTIN_1_IN: PULSE Position */ -#define GIMA_CTIN_1_IN_PULSE_Msk (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos) /*!< GIMA CTIN_1_IN: PULSE Mask */ -#define GIMA_CTIN_1_IN_SELECT_Pos 4 /*!< GIMA CTIN_1_IN: SELECT Position */ -#define GIMA_CTIN_1_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos) /*!< GIMA CTIN_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_2_IN ----------------------------------------- -#define GIMA_CTIN_2_IN_INV_Pos 0 /*!< GIMA CTIN_2_IN: INV Position */ -#define GIMA_CTIN_2_IN_INV_Msk (0x01UL << GIMA_CTIN_2_IN_INV_Pos) /*!< GIMA CTIN_2_IN: INV Mask */ -#define GIMA_CTIN_2_IN_EDGE_Pos 1 /*!< GIMA CTIN_2_IN: EDGE Position */ -#define GIMA_CTIN_2_IN_EDGE_Msk (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos) /*!< GIMA CTIN_2_IN: EDGE Mask */ -#define GIMA_CTIN_2_IN_SYNCH_Pos 2 /*!< GIMA CTIN_2_IN: SYNCH Position */ -#define GIMA_CTIN_2_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos) /*!< GIMA CTIN_2_IN: SYNCH Mask */ -#define GIMA_CTIN_2_IN_PULSE_Pos 3 /*!< GIMA CTIN_2_IN: PULSE Position */ -#define GIMA_CTIN_2_IN_PULSE_Msk (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos) /*!< GIMA CTIN_2_IN: PULSE Mask */ -#define GIMA_CTIN_2_IN_SELECT_Pos 4 /*!< GIMA CTIN_2_IN: SELECT Position */ -#define GIMA_CTIN_2_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos) /*!< GIMA CTIN_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_3_IN ----------------------------------------- -#define GIMA_CTIN_3_IN_INV_Pos 0 /*!< GIMA CTIN_3_IN: INV Position */ -#define GIMA_CTIN_3_IN_INV_Msk (0x01UL << GIMA_CTIN_3_IN_INV_Pos) /*!< GIMA CTIN_3_IN: INV Mask */ -#define GIMA_CTIN_3_IN_EDGE_Pos 1 /*!< GIMA CTIN_3_IN: EDGE Position */ -#define GIMA_CTIN_3_IN_EDGE_Msk (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos) /*!< GIMA CTIN_3_IN: EDGE Mask */ -#define GIMA_CTIN_3_IN_SYNCH_Pos 2 /*!< GIMA CTIN_3_IN: SYNCH Position */ -#define GIMA_CTIN_3_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos) /*!< GIMA CTIN_3_IN: SYNCH Mask */ -#define GIMA_CTIN_3_IN_PULSE_Pos 3 /*!< GIMA CTIN_3_IN: PULSE Position */ -#define GIMA_CTIN_3_IN_PULSE_Msk (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos) /*!< GIMA CTIN_3_IN: PULSE Mask */ -#define GIMA_CTIN_3_IN_SELECT_Pos 4 /*!< GIMA CTIN_3_IN: SELECT Position */ -#define GIMA_CTIN_3_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos) /*!< GIMA CTIN_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_4_IN ----------------------------------------- -#define GIMA_CTIN_4_IN_INV_Pos 0 /*!< GIMA CTIN_4_IN: INV Position */ -#define GIMA_CTIN_4_IN_INV_Msk (0x01UL << GIMA_CTIN_4_IN_INV_Pos) /*!< GIMA CTIN_4_IN: INV Mask */ -#define GIMA_CTIN_4_IN_EDGE_Pos 1 /*!< GIMA CTIN_4_IN: EDGE Position */ -#define GIMA_CTIN_4_IN_EDGE_Msk (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos) /*!< GIMA CTIN_4_IN: EDGE Mask */ -#define GIMA_CTIN_4_IN_SYNCH_Pos 2 /*!< GIMA CTIN_4_IN: SYNCH Position */ -#define GIMA_CTIN_4_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos) /*!< GIMA CTIN_4_IN: SYNCH Mask */ -#define GIMA_CTIN_4_IN_PULSE_Pos 3 /*!< GIMA CTIN_4_IN: PULSE Position */ -#define GIMA_CTIN_4_IN_PULSE_Msk (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos) /*!< GIMA CTIN_4_IN: PULSE Mask */ -#define GIMA_CTIN_4_IN_SELECT_Pos 4 /*!< GIMA CTIN_4_IN: SELECT Position */ -#define GIMA_CTIN_4_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos) /*!< GIMA CTIN_4_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_5_IN ----------------------------------------- -#define GIMA_CTIN_5_IN_INV_Pos 0 /*!< GIMA CTIN_5_IN: INV Position */ -#define GIMA_CTIN_5_IN_INV_Msk (0x01UL << GIMA_CTIN_5_IN_INV_Pos) /*!< GIMA CTIN_5_IN: INV Mask */ -#define GIMA_CTIN_5_IN_EDGE_Pos 1 /*!< GIMA CTIN_5_IN: EDGE Position */ -#define GIMA_CTIN_5_IN_EDGE_Msk (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos) /*!< GIMA CTIN_5_IN: EDGE Mask */ -#define GIMA_CTIN_5_IN_SYNCH_Pos 2 /*!< GIMA CTIN_5_IN: SYNCH Position */ -#define GIMA_CTIN_5_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos) /*!< GIMA CTIN_5_IN: SYNCH Mask */ -#define GIMA_CTIN_5_IN_PULSE_Pos 3 /*!< GIMA CTIN_5_IN: PULSE Position */ -#define GIMA_CTIN_5_IN_PULSE_Msk (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos) /*!< GIMA CTIN_5_IN: PULSE Mask */ -#define GIMA_CTIN_5_IN_SELECT_Pos 4 /*!< GIMA CTIN_5_IN: SELECT Position */ -#define GIMA_CTIN_5_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos) /*!< GIMA CTIN_5_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_6_IN ----------------------------------------- -#define GIMA_CTIN_6_IN_INV_Pos 0 /*!< GIMA CTIN_6_IN: INV Position */ -#define GIMA_CTIN_6_IN_INV_Msk (0x01UL << GIMA_CTIN_6_IN_INV_Pos) /*!< GIMA CTIN_6_IN: INV Mask */ -#define GIMA_CTIN_6_IN_EDGE_Pos 1 /*!< GIMA CTIN_6_IN: EDGE Position */ -#define GIMA_CTIN_6_IN_EDGE_Msk (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos) /*!< GIMA CTIN_6_IN: EDGE Mask */ -#define GIMA_CTIN_6_IN_SYNCH_Pos 2 /*!< GIMA CTIN_6_IN: SYNCH Position */ -#define GIMA_CTIN_6_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos) /*!< GIMA CTIN_6_IN: SYNCH Mask */ -#define GIMA_CTIN_6_IN_PULSE_Pos 3 /*!< GIMA CTIN_6_IN: PULSE Position */ -#define GIMA_CTIN_6_IN_PULSE_Msk (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos) /*!< GIMA CTIN_6_IN: PULSE Mask */ -#define GIMA_CTIN_6_IN_SELECT_Pos 4 /*!< GIMA CTIN_6_IN: SELECT Position */ -#define GIMA_CTIN_6_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos) /*!< GIMA CTIN_6_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_7_IN ----------------------------------------- -#define GIMA_CTIN_7_IN_INV_Pos 0 /*!< GIMA CTIN_7_IN: INV Position */ -#define GIMA_CTIN_7_IN_INV_Msk (0x01UL << GIMA_CTIN_7_IN_INV_Pos) /*!< GIMA CTIN_7_IN: INV Mask */ -#define GIMA_CTIN_7_IN_EDGE_Pos 1 /*!< GIMA CTIN_7_IN: EDGE Position */ -#define GIMA_CTIN_7_IN_EDGE_Msk (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos) /*!< GIMA CTIN_7_IN: EDGE Mask */ -#define GIMA_CTIN_7_IN_SYNCH_Pos 2 /*!< GIMA CTIN_7_IN: SYNCH Position */ -#define GIMA_CTIN_7_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos) /*!< GIMA CTIN_7_IN: SYNCH Mask */ -#define GIMA_CTIN_7_IN_PULSE_Pos 3 /*!< GIMA CTIN_7_IN: PULSE Position */ -#define GIMA_CTIN_7_IN_PULSE_Msk (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos) /*!< GIMA CTIN_7_IN: PULSE Mask */ -#define GIMA_CTIN_7_IN_SELECT_Pos 4 /*!< GIMA CTIN_7_IN: SELECT Position */ -#define GIMA_CTIN_7_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos) /*!< GIMA CTIN_7_IN: SELECT Mask */ - -// ---------------------------------- GIMA_VADC_TRIGGER_IN -------------------------------------- -#define GIMA_VADC_TRIGGER_IN_INV_Pos 0 /*!< GIMA VADC_TRIGGER_IN: INV Position */ -#define GIMA_VADC_TRIGGER_IN_INV_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos) /*!< GIMA VADC_TRIGGER_IN: INV Mask */ -#define GIMA_VADC_TRIGGER_IN_EDGE_Pos 1 /*!< GIMA VADC_TRIGGER_IN: EDGE Position */ -#define GIMA_VADC_TRIGGER_IN_EDGE_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos) /*!< GIMA VADC_TRIGGER_IN: EDGE Mask */ -#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos 2 /*!< GIMA VADC_TRIGGER_IN: SYNCH Position */ -#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos) /*!< GIMA VADC_TRIGGER_IN: SYNCH Mask */ -#define GIMA_VADC_TRIGGER_IN_PULSE_Pos 3 /*!< GIMA VADC_TRIGGER_IN: PULSE Position */ -#define GIMA_VADC_TRIGGER_IN_PULSE_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos) /*!< GIMA VADC_TRIGGER_IN: PULSE Mask */ -#define GIMA_VADC_TRIGGER_IN_SELECT_Pos 4 /*!< GIMA VADC_TRIGGER_IN: SELECT Position */ -#define GIMA_VADC_TRIGGER_IN_SELECT_Msk (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos) /*!< GIMA VADC_TRIGGER_IN: SELECT Mask */ - -// --------------------------------- GIMA_EVENTROUTER_13_IN ------------------------------------- -#define GIMA_EVENTROUTER_13_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_13_IN: INV Position */ -#define GIMA_EVENTROUTER_13_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos) /*!< GIMA EVENTROUTER_13_IN: INV Mask */ -#define GIMA_EVENTROUTER_13_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_13_IN: EDGE Position */ -#define GIMA_EVENTROUTER_13_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_13_IN: EDGE Mask */ -#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */ -#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask */ -#define GIMA_EVENTROUTER_13_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_13_IN: PULSE Position */ -#define GIMA_EVENTROUTER_13_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_13_IN: PULSE Mask */ -#define GIMA_EVENTROUTER_13_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_13_IN: SELECT Position */ -#define GIMA_EVENTROUTER_13_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */ - -// --------------------------------- GIMA_EVENTROUTER_14_IN ------------------------------------- -#define GIMA_EVENTROUTER_14_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_14_IN: INV Position */ -#define GIMA_EVENTROUTER_14_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos) /*!< GIMA EVENTROUTER_14_IN: INV Mask */ -#define GIMA_EVENTROUTER_14_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_14_IN: EDGE Position */ -#define GIMA_EVENTROUTER_14_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_14_IN: EDGE Mask */ -#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */ -#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask */ -#define GIMA_EVENTROUTER_14_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_14_IN: PULSE Position */ -#define GIMA_EVENTROUTER_14_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_14_IN: PULSE Mask */ -#define GIMA_EVENTROUTER_14_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_14_IN: SELECT Position */ -#define GIMA_EVENTROUTER_14_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */ - -// --------------------------------- GIMA_EVENTROUTER_16_IN ------------------------------------- -#define GIMA_EVENTROUTER_16_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_16_IN: INV Position */ -#define GIMA_EVENTROUTER_16_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos) /*!< GIMA EVENTROUTER_16_IN: INV Mask */ -#define GIMA_EVENTROUTER_16_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_16_IN: EDGE Position */ -#define GIMA_EVENTROUTER_16_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_16_IN: EDGE Mask */ -#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */ -#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask */ -#define GIMA_EVENTROUTER_16_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_16_IN: PULSE Position */ -#define GIMA_EVENTROUTER_16_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_16_IN: PULSE Mask */ -#define GIMA_EVENTROUTER_16_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_16_IN: SELECT Position */ -#define GIMA_EVENTROUTER_16_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */ - -// ------------------------------------ GIMA_ADCSTART0_IN --------------------------------------- -#define GIMA_ADCSTART0_IN_INV_Pos 0 /*!< GIMA ADCSTART0_IN: INV Position */ -#define GIMA_ADCSTART0_IN_INV_Msk (0x01UL << GIMA_ADCSTART0_IN_INV_Pos) /*!< GIMA ADCSTART0_IN: INV Mask */ -#define GIMA_ADCSTART0_IN_EDGE_Pos 1 /*!< GIMA ADCSTART0_IN: EDGE Position */ -#define GIMA_ADCSTART0_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos) /*!< GIMA ADCSTART0_IN: EDGE Mask */ -#define GIMA_ADCSTART0_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART0_IN: SYNCH Position */ -#define GIMA_ADCSTART0_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos) /*!< GIMA ADCSTART0_IN: SYNCH Mask */ -#define GIMA_ADCSTART0_IN_PULSE_Pos 3 /*!< GIMA ADCSTART0_IN: PULSE Position */ -#define GIMA_ADCSTART0_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos) /*!< GIMA ADCSTART0_IN: PULSE Mask */ -#define GIMA_ADCSTART0_IN_SELECT_Pos 4 /*!< GIMA ADCSTART0_IN: SELECT Position */ -#define GIMA_ADCSTART0_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos) /*!< GIMA ADCSTART0_IN: SELECT Mask */ - -// ------------------------------------ GIMA_ADCSTART1_IN --------------------------------------- -#define GIMA_ADCSTART1_IN_INV_Pos 0 /*!< GIMA ADCSTART1_IN: INV Position */ -#define GIMA_ADCSTART1_IN_INV_Msk (0x01UL << GIMA_ADCSTART1_IN_INV_Pos) /*!< GIMA ADCSTART1_IN: INV Mask */ -#define GIMA_ADCSTART1_IN_EDGE_Pos 1 /*!< GIMA ADCSTART1_IN: EDGE Position */ -#define GIMA_ADCSTART1_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos) /*!< GIMA ADCSTART1_IN: EDGE Mask */ -#define GIMA_ADCSTART1_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART1_IN: SYNCH Position */ -#define GIMA_ADCSTART1_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos) /*!< GIMA ADCSTART1_IN: SYNCH Mask */ -#define GIMA_ADCSTART1_IN_PULSE_Pos 3 /*!< GIMA ADCSTART1_IN: PULSE Position */ -#define GIMA_ADCSTART1_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos) /*!< GIMA ADCSTART1_IN: PULSE Mask */ -#define GIMA_ADCSTART1_IN_SELECT_Pos 4 /*!< GIMA ADCSTART1_IN: SELECT Position */ -#define GIMA_ADCSTART1_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos) /*!< GIMA ADCSTART1_IN: SELECT Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- DAC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- DAC_CR --------------------------------------------- -#define DAC_CR_VALUE_Pos 6 /*!< DAC CR: VALUE Position */ -#define DAC_CR_VALUE_Msk (0x000003ffUL << DAC_CR_VALUE_Pos) /*!< DAC CR: VALUE Mask */ -#define DAC_CR_BIAS_Pos 16 /*!< DAC CR: BIAS Position */ -#define DAC_CR_BIAS_Msk (0x01UL << DAC_CR_BIAS_Pos) /*!< DAC CR: BIAS Mask */ - -// ---------------------------------------- DAC_CTRL -------------------------------------------- -#define DAC_CTRL_INT_DMA_REQ_Pos 0 /*!< DAC CTRL: INT_DMA_REQ Position */ -#define DAC_CTRL_INT_DMA_REQ_Msk (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos) /*!< DAC CTRL: INT_DMA_REQ Mask */ -#define DAC_CTRL_DBLBUF_ENA_Pos 1 /*!< DAC CTRL: DBLBUF_ENA Position */ -#define DAC_CTRL_DBLBUF_ENA_Msk (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos) /*!< DAC CTRL: DBLBUF_ENA Mask */ -#define DAC_CTRL_CNT_ENA_Pos 2 /*!< DAC CTRL: CNT_ENA Position */ -#define DAC_CTRL_CNT_ENA_Msk (0x01UL << DAC_CTRL_CNT_ENA_Pos) /*!< DAC CTRL: CNT_ENA Mask */ -#define DAC_CTRL_DMA_ENA_Pos 3 /*!< DAC CTRL: DMA_ENA Position */ -#define DAC_CTRL_DMA_ENA_Msk (0x01UL << DAC_CTRL_DMA_ENA_Pos) /*!< DAC CTRL: DMA_ENA Mask */ - -// --------------------------------------- DAC_CNTVAL ------------------------------------------- -#define DAC_CNTVAL_VALUE_Pos 0 /*!< DAC CNTVAL: VALUE Position */ -#define DAC_CNTVAL_VALUE_Msk (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos) /*!< DAC CNTVAL: VALUE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- C_CAN0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- C_CAN0_CNTL ------------------------------------------ -#define C_CAN0_CNTL_INIT_Pos 0 /*!< C_CAN0 CNTL: INIT Position */ -#define C_CAN0_CNTL_INIT_Msk (0x01UL << C_CAN0_CNTL_INIT_Pos) /*!< C_CAN0 CNTL: INIT Mask */ -#define C_CAN0_CNTL_IE_Pos 1 /*!< C_CAN0 CNTL: IE Position */ -#define C_CAN0_CNTL_IE_Msk (0x01UL << C_CAN0_CNTL_IE_Pos) /*!< C_CAN0 CNTL: IE Mask */ -#define C_CAN0_CNTL_SIE_Pos 2 /*!< C_CAN0 CNTL: SIE Position */ -#define C_CAN0_CNTL_SIE_Msk (0x01UL << C_CAN0_CNTL_SIE_Pos) /*!< C_CAN0 CNTL: SIE Mask */ -#define C_CAN0_CNTL_EIE_Pos 3 /*!< C_CAN0 CNTL: EIE Position */ -#define C_CAN0_CNTL_EIE_Msk (0x01UL << C_CAN0_CNTL_EIE_Pos) /*!< C_CAN0 CNTL: EIE Mask */ -#define C_CAN0_CNTL_DAR_Pos 5 /*!< C_CAN0 CNTL: DAR Position */ -#define C_CAN0_CNTL_DAR_Msk (0x01UL << C_CAN0_CNTL_DAR_Pos) /*!< C_CAN0 CNTL: DAR Mask */ -#define C_CAN0_CNTL_CCE_Pos 6 /*!< C_CAN0 CNTL: CCE Position */ -#define C_CAN0_CNTL_CCE_Msk (0x01UL << C_CAN0_CNTL_CCE_Pos) /*!< C_CAN0 CNTL: CCE Mask */ -#define C_CAN0_CNTL_TEST_Pos 7 /*!< C_CAN0 CNTL: TEST Position */ -#define C_CAN0_CNTL_TEST_Msk (0x01UL << C_CAN0_CNTL_TEST_Pos) /*!< C_CAN0 CNTL: TEST Mask */ - -// --------------------------------------- C_CAN0_STAT ------------------------------------------ -#define C_CAN0_STAT_LEC_Pos 0 /*!< C_CAN0 STAT: LEC Position */ -#define C_CAN0_STAT_LEC_Msk (0x07UL << C_CAN0_STAT_LEC_Pos) /*!< C_CAN0 STAT: LEC Mask */ -#define C_CAN0_STAT_TXOK_Pos 3 /*!< C_CAN0 STAT: TXOK Position */ -#define C_CAN0_STAT_TXOK_Msk (0x01UL << C_CAN0_STAT_TXOK_Pos) /*!< C_CAN0 STAT: TXOK Mask */ -#define C_CAN0_STAT_RXOK_Pos 4 /*!< C_CAN0 STAT: RXOK Position */ -#define C_CAN0_STAT_RXOK_Msk (0x01UL << C_CAN0_STAT_RXOK_Pos) /*!< C_CAN0 STAT: RXOK Mask */ -#define C_CAN0_STAT_EPASS_Pos 5 /*!< C_CAN0 STAT: EPASS Position */ -#define C_CAN0_STAT_EPASS_Msk (0x01UL << C_CAN0_STAT_EPASS_Pos) /*!< C_CAN0 STAT: EPASS Mask */ -#define C_CAN0_STAT_EWARN_Pos 6 /*!< C_CAN0 STAT: EWARN Position */ -#define C_CAN0_STAT_EWARN_Msk (0x01UL << C_CAN0_STAT_EWARN_Pos) /*!< C_CAN0 STAT: EWARN Mask */ -#define C_CAN0_STAT_BOFF_Pos 7 /*!< C_CAN0 STAT: BOFF Position */ -#define C_CAN0_STAT_BOFF_Msk (0x01UL << C_CAN0_STAT_BOFF_Pos) /*!< C_CAN0 STAT: BOFF Mask */ - -// ---------------------------------------- C_CAN0_EC ------------------------------------------- -#define C_CAN0_EC_TEC_7_0_Pos 0 /*!< C_CAN0 EC: TEC_7_0 Position */ -#define C_CAN0_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos) /*!< C_CAN0 EC: TEC_7_0 Mask */ -#define C_CAN0_EC_REC_6_0_Pos 8 /*!< C_CAN0 EC: REC_6_0 Position */ -#define C_CAN0_EC_REC_6_0_Msk (0x7fUL << C_CAN0_EC_REC_6_0_Pos) /*!< C_CAN0 EC: REC_6_0 Mask */ -#define C_CAN0_EC_RP_Pos 15 /*!< C_CAN0 EC: RP Position */ -#define C_CAN0_EC_RP_Msk (0x01UL << C_CAN0_EC_RP_Pos) /*!< C_CAN0 EC: RP Mask */ - -// ---------------------------------------- C_CAN0_BT ------------------------------------------- -#define C_CAN0_BT_BRP_Pos 0 /*!< C_CAN0 BT: BRP Position */ -#define C_CAN0_BT_BRP_Msk (0x3fUL << C_CAN0_BT_BRP_Pos) /*!< C_CAN0 BT: BRP Mask */ -#define C_CAN0_BT_SJW_Pos 6 /*!< C_CAN0 BT: SJW Position */ -#define C_CAN0_BT_SJW_Msk (0x03UL << C_CAN0_BT_SJW_Pos) /*!< C_CAN0 BT: SJW Mask */ -#define C_CAN0_BT_TSEG1_Pos 8 /*!< C_CAN0 BT: TSEG1 Position */ -#define C_CAN0_BT_TSEG1_Msk (0x0fUL << C_CAN0_BT_TSEG1_Pos) /*!< C_CAN0 BT: TSEG1 Mask */ -#define C_CAN0_BT_TSEG2_Pos 12 /*!< C_CAN0 BT: TSEG2 Position */ -#define C_CAN0_BT_TSEG2_Msk (0x07UL << C_CAN0_BT_TSEG2_Pos) /*!< C_CAN0 BT: TSEG2 Mask */ - -// --------------------------------------- C_CAN0_INT ------------------------------------------- -#define C_CAN0_INT_INTID15_0_Pos 0 /*!< C_CAN0 INT: INTID15_0 Position */ -#define C_CAN0_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos) /*!< C_CAN0 INT: INTID15_0 Mask */ - -// --------------------------------------- C_CAN0_TEST ------------------------------------------ -#define C_CAN0_TEST_BASIC_Pos 2 /*!< C_CAN0 TEST: BASIC Position */ -#define C_CAN0_TEST_BASIC_Msk (0x01UL << C_CAN0_TEST_BASIC_Pos) /*!< C_CAN0 TEST: BASIC Mask */ -#define C_CAN0_TEST_SILENT_Pos 3 /*!< C_CAN0 TEST: SILENT Position */ -#define C_CAN0_TEST_SILENT_Msk (0x01UL << C_CAN0_TEST_SILENT_Pos) /*!< C_CAN0 TEST: SILENT Mask */ -#define C_CAN0_TEST_LBACK_Pos 4 /*!< C_CAN0 TEST: LBACK Position */ -#define C_CAN0_TEST_LBACK_Msk (0x01UL << C_CAN0_TEST_LBACK_Pos) /*!< C_CAN0 TEST: LBACK Mask */ -#define C_CAN0_TEST_TX1_0_Pos 5 /*!< C_CAN0 TEST: TX1_0 Position */ -#define C_CAN0_TEST_TX1_0_Msk (0x03UL << C_CAN0_TEST_TX1_0_Pos) /*!< C_CAN0 TEST: TX1_0 Mask */ -#define C_CAN0_TEST_RX_Pos 7 /*!< C_CAN0 TEST: RX Position */ -#define C_CAN0_TEST_RX_Msk (0x01UL << C_CAN0_TEST_RX_Pos) /*!< C_CAN0 TEST: RX Mask */ - -// --------------------------------------- C_CAN0_BRPE ------------------------------------------ -#define C_CAN0_BRPE_BRPE_Pos 0 /*!< C_CAN0 BRPE: BRPE Position */ -#define C_CAN0_BRPE_BRPE_Msk (0x0fUL << C_CAN0_BRPE_BRPE_Pos) /*!< C_CAN0 BRPE: BRPE Mask */ - -// ------------------------------------ C_CAN0_IF1_CMDREQ --------------------------------------- -#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */ -#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask */ -#define C_CAN0_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF1_CMDREQ: BUSY Position */ -#define C_CAN0_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF1_CMDREQ: BUSY Mask */ - -// ----------------------------------- C_CAN0_IF1_CMDMSK_R -------------------------------------- -#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */ -#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask */ -#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */ -#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask */ -#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */ -#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask */ -#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */ -#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */ -#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position */ -#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask */ -#define C_CAN0_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_R: ARB Position */ -#define C_CAN0_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask */ -#define C_CAN0_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_R: MASK Position */ -#define C_CAN0_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask */ -#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */ -#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask */ - -// ----------------------------------- C_CAN0_IF1_CMDMSK_W -------------------------------------- -#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */ -#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask */ -#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */ -#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask */ -#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */ -#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask */ -#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */ -#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */ -#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position */ -#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask */ -#define C_CAN0_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_W: ARB Position */ -#define C_CAN0_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask */ -#define C_CAN0_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_W: MASK Position */ -#define C_CAN0_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask */ -#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */ -#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask */ - -// ------------------------------------- C_CAN0_IF1_MSK1 ---------------------------------------- -#define C_CAN0_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF1_MSK1: MSK15_0 Position */ -#define C_CAN0_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask */ - -// ------------------------------------- C_CAN0_IF1_MSK2 ---------------------------------------- -#define C_CAN0_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF1_MSK2: MSK28_16 Position */ -#define C_CAN0_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask */ -#define C_CAN0_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF1_MSK2: MDIR Position */ -#define C_CAN0_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos) /*!< C_CAN0 IF1_MSK2: MDIR Mask */ -#define C_CAN0_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF1_MSK2: MXTD Position */ -#define C_CAN0_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos) /*!< C_CAN0 IF1_MSK2: MXTD Mask */ - -// ------------------------------------- C_CAN0_IF1_ARB1 ---------------------------------------- -#define C_CAN0_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF1_ARB1: ID15_0 Position */ -#define C_CAN0_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos) /*!< C_CAN0 IF1_ARB1: ID15_0 Mask */ - -// ------------------------------------- C_CAN0_IF1_ARB2 ---------------------------------------- -#define C_CAN0_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF1_ARB2: ID28_16 Position */ -#define C_CAN0_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos) /*!< C_CAN0 IF1_ARB2: ID28_16 Mask */ -#define C_CAN0_IF1_ARB2_DIR_Pos 13 /*!< C_CAN0 IF1_ARB2: DIR Position */ -#define C_CAN0_IF1_ARB2_DIR_Msk (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos) /*!< C_CAN0 IF1_ARB2: DIR Mask */ -#define C_CAN0_IF1_ARB2_XTD_Pos 14 /*!< C_CAN0 IF1_ARB2: XTD Position */ -#define C_CAN0_IF1_ARB2_XTD_Msk (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos) /*!< C_CAN0 IF1_ARB2: XTD Mask */ -#define C_CAN0_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF1_ARB2: MSGVAL Position */ -#define C_CAN0_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF1_ARB2: MSGVAL Mask */ - -// ------------------------------------ C_CAN0_IF1_MCTRL ---------------------------------------- -#define C_CAN0_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position */ -#define C_CAN0_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask */ -#define C_CAN0_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF1_MCTRL: EOB Position */ -#define C_CAN0_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos) /*!< C_CAN0 IF1_MCTRL: EOB Mask */ -#define C_CAN0_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF1_MCTRL: TXRQST Position */ -#define C_CAN0_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF1_MCTRL: TXRQST Mask */ -#define C_CAN0_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF1_MCTRL: RMTEN Position */ -#define C_CAN0_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF1_MCTRL: RMTEN Mask */ -#define C_CAN0_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF1_MCTRL: RXIE Position */ -#define C_CAN0_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos) /*!< C_CAN0 IF1_MCTRL: RXIE Mask */ -#define C_CAN0_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF1_MCTRL: TXIE Position */ -#define C_CAN0_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos) /*!< C_CAN0 IF1_MCTRL: TXIE Mask */ -#define C_CAN0_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF1_MCTRL: UMASK Position */ -#define C_CAN0_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos) /*!< C_CAN0 IF1_MCTRL: UMASK Mask */ -#define C_CAN0_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF1_MCTRL: INTPND Position */ -#define C_CAN0_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos) /*!< C_CAN0 IF1_MCTRL: INTPND Mask */ -#define C_CAN0_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF1_MCTRL: MSGLST Position */ -#define C_CAN0_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF1_MCTRL: MSGLST Mask */ -#define C_CAN0_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF1_MCTRL: NEWDAT Position */ -#define C_CAN0_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask */ - -// ------------------------------------- C_CAN0_IF1_DA1 ----------------------------------------- -#define C_CAN0_IF1_DA1_DATA0_Pos 0 /*!< C_CAN0 IF1_DA1: DATA0 Position */ -#define C_CAN0_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos) /*!< C_CAN0 IF1_DA1: DATA0 Mask */ -#define C_CAN0_IF1_DA1_DATA1_Pos 8 /*!< C_CAN0 IF1_DA1: DATA1 Position */ -#define C_CAN0_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos) /*!< C_CAN0 IF1_DA1: DATA1 Mask */ - -// ------------------------------------- C_CAN0_IF1_DA2 ----------------------------------------- -#define C_CAN0_IF1_DA2_DATA2_Pos 0 /*!< C_CAN0 IF1_DA2: DATA2 Position */ -#define C_CAN0_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos) /*!< C_CAN0 IF1_DA2: DATA2 Mask */ -#define C_CAN0_IF1_DA2_DATA3_Pos 8 /*!< C_CAN0 IF1_DA2: DATA3 Position */ -#define C_CAN0_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos) /*!< C_CAN0 IF1_DA2: DATA3 Mask */ - -// ------------------------------------- C_CAN0_IF1_DB1 ----------------------------------------- -#define C_CAN0_IF1_DB1_DATA4_Pos 0 /*!< C_CAN0 IF1_DB1: DATA4 Position */ -#define C_CAN0_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos) /*!< C_CAN0 IF1_DB1: DATA4 Mask */ -#define C_CAN0_IF1_DB1_DATA5_Pos 8 /*!< C_CAN0 IF1_DB1: DATA5 Position */ -#define C_CAN0_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos) /*!< C_CAN0 IF1_DB1: DATA5 Mask */ - -// ------------------------------------- C_CAN0_IF1_DB2 ----------------------------------------- -#define C_CAN0_IF1_DB2_DATA6_Pos 0 /*!< C_CAN0 IF1_DB2: DATA6 Position */ -#define C_CAN0_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos) /*!< C_CAN0 IF1_DB2: DATA6 Mask */ -#define C_CAN0_IF1_DB2_DATA7_Pos 8 /*!< C_CAN0 IF1_DB2: DATA7 Position */ -#define C_CAN0_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos) /*!< C_CAN0 IF1_DB2: DATA7 Mask */ - -// ------------------------------------ C_CAN0_IF2_CMDREQ --------------------------------------- -#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */ -#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask */ -#define C_CAN0_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF2_CMDREQ: BUSY Position */ -#define C_CAN0_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF2_CMDREQ: BUSY Mask */ - -// ----------------------------------- C_CAN0_IF2_CMDMSK_R -------------------------------------- -#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */ -#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask */ -#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */ -#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask */ -#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */ -#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask */ -#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */ -#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */ -#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position */ -#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask */ -#define C_CAN0_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_R: ARB Position */ -#define C_CAN0_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask */ -#define C_CAN0_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_R: MASK Position */ -#define C_CAN0_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask */ -#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */ -#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask */ - -// ----------------------------------- C_CAN0_IF2_CMDMSK_W -------------------------------------- -#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */ -#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask */ -#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */ -#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask */ -#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */ -#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask */ -#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */ -#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */ -#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position */ -#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask */ -#define C_CAN0_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_W: ARB Position */ -#define C_CAN0_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask */ -#define C_CAN0_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_W: MASK Position */ -#define C_CAN0_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask */ -#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */ -#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask */ - -// ------------------------------------- C_CAN0_IF2_MSK1 ---------------------------------------- -#define C_CAN0_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF2_MSK1: MSK15_0 Position */ -#define C_CAN0_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask */ - -// ------------------------------------- C_CAN0_IF2_MSK2 ---------------------------------------- -#define C_CAN0_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF2_MSK2: MSK28_16 Position */ -#define C_CAN0_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask */ -#define C_CAN0_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF2_MSK2: MDIR Position */ -#define C_CAN0_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos) /*!< C_CAN0 IF2_MSK2: MDIR Mask */ -#define C_CAN0_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF2_MSK2: MXTD Position */ -#define C_CAN0_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos) /*!< C_CAN0 IF2_MSK2: MXTD Mask */ - -// ------------------------------------- C_CAN0_IF2_ARB1 ---------------------------------------- -#define C_CAN0_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF2_ARB1: ID15_0 Position */ -#define C_CAN0_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos) /*!< C_CAN0 IF2_ARB1: ID15_0 Mask */ - -// ------------------------------------- C_CAN0_IF2_ARB2 ---------------------------------------- -#define C_CAN0_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF2_ARB2: ID28_16 Position */ -#define C_CAN0_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos) /*!< C_CAN0 IF2_ARB2: ID28_16 Mask */ -#define C_CAN0_IF2_ARB2_DIR_Pos 13 /*!< C_CAN0 IF2_ARB2: DIR Position */ -#define C_CAN0_IF2_ARB2_DIR_Msk (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos) /*!< C_CAN0 IF2_ARB2: DIR Mask */ -#define C_CAN0_IF2_ARB2_XTD_Pos 14 /*!< C_CAN0 IF2_ARB2: XTD Position */ -#define C_CAN0_IF2_ARB2_XTD_Msk (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos) /*!< C_CAN0 IF2_ARB2: XTD Mask */ -#define C_CAN0_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF2_ARB2: MSGVAL Position */ -#define C_CAN0_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF2_ARB2: MSGVAL Mask */ - -// ------------------------------------ C_CAN0_IF2_MCTRL ---------------------------------------- -#define C_CAN0_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position */ -#define C_CAN0_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask */ -#define C_CAN0_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF2_MCTRL: EOB Position */ -#define C_CAN0_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos) /*!< C_CAN0 IF2_MCTRL: EOB Mask */ -#define C_CAN0_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF2_MCTRL: TXRQST Position */ -#define C_CAN0_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF2_MCTRL: TXRQST Mask */ -#define C_CAN0_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF2_MCTRL: RMTEN Position */ -#define C_CAN0_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF2_MCTRL: RMTEN Mask */ -#define C_CAN0_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF2_MCTRL: RXIE Position */ -#define C_CAN0_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos) /*!< C_CAN0 IF2_MCTRL: RXIE Mask */ -#define C_CAN0_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF2_MCTRL: TXIE Position */ -#define C_CAN0_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos) /*!< C_CAN0 IF2_MCTRL: TXIE Mask */ -#define C_CAN0_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF2_MCTRL: UMASK Position */ -#define C_CAN0_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos) /*!< C_CAN0 IF2_MCTRL: UMASK Mask */ -#define C_CAN0_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF2_MCTRL: INTPND Position */ -#define C_CAN0_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos) /*!< C_CAN0 IF2_MCTRL: INTPND Mask */ -#define C_CAN0_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF2_MCTRL: MSGLST Position */ -#define C_CAN0_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF2_MCTRL: MSGLST Mask */ -#define C_CAN0_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF2_MCTRL: NEWDAT Position */ -#define C_CAN0_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask */ - -// ------------------------------------- C_CAN0_IF2_DA1 ----------------------------------------- -#define C_CAN0_IF2_DA1_DATA0_Pos 0 /*!< C_CAN0 IF2_DA1: DATA0 Position */ -#define C_CAN0_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos) /*!< C_CAN0 IF2_DA1: DATA0 Mask */ -#define C_CAN0_IF2_DA1_DATA1_Pos 8 /*!< C_CAN0 IF2_DA1: DATA1 Position */ -#define C_CAN0_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos) /*!< C_CAN0 IF2_DA1: DATA1 Mask */ - -// ------------------------------------- C_CAN0_IF2_DA2 ----------------------------------------- -#define C_CAN0_IF2_DA2_DATA2_Pos 0 /*!< C_CAN0 IF2_DA2: DATA2 Position */ -#define C_CAN0_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos) /*!< C_CAN0 IF2_DA2: DATA2 Mask */ -#define C_CAN0_IF2_DA2_DATA3_Pos 8 /*!< C_CAN0 IF2_DA2: DATA3 Position */ -#define C_CAN0_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos) /*!< C_CAN0 IF2_DA2: DATA3 Mask */ - -// ------------------------------------- C_CAN0_IF2_DB1 ----------------------------------------- -#define C_CAN0_IF2_DB1_DATA4_Pos 0 /*!< C_CAN0 IF2_DB1: DATA4 Position */ -#define C_CAN0_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos) /*!< C_CAN0 IF2_DB1: DATA4 Mask */ -#define C_CAN0_IF2_DB1_DATA5_Pos 8 /*!< C_CAN0 IF2_DB1: DATA5 Position */ -#define C_CAN0_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos) /*!< C_CAN0 IF2_DB1: DATA5 Mask */ - -// ------------------------------------- C_CAN0_IF2_DB2 ----------------------------------------- -#define C_CAN0_IF2_DB2_DATA6_Pos 0 /*!< C_CAN0 IF2_DB2: DATA6 Position */ -#define C_CAN0_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos) /*!< C_CAN0 IF2_DB2: DATA6 Mask */ -#define C_CAN0_IF2_DB2_DATA7_Pos 8 /*!< C_CAN0 IF2_DB2: DATA7 Position */ -#define C_CAN0_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos) /*!< C_CAN0 IF2_DB2: DATA7 Mask */ - -// -------------------------------------- C_CAN0_TXREQ1 ----------------------------------------- -#define C_CAN0_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN0 TXREQ1: TXRQST16_1 Position */ -#define C_CAN0_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask */ - -// -------------------------------------- C_CAN0_TXREQ2 ----------------------------------------- -#define C_CAN0_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */ -#define C_CAN0_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask */ - -// --------------------------------------- C_CAN0_ND1 ------------------------------------------- -#define C_CAN0_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN0 ND1: NEWDAT16_1 Position */ -#define C_CAN0_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos) /*!< C_CAN0 ND1: NEWDAT16_1 Mask */ - -// --------------------------------------- C_CAN0_ND2 ------------------------------------------- -#define C_CAN0_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN0 ND2: NEWDAT32_17 Position */ -#define C_CAN0_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos) /*!< C_CAN0 ND2: NEWDAT32_17 Mask */ - -// --------------------------------------- C_CAN0_IR1 ------------------------------------------- -#define C_CAN0_IR1_INTPND16_1_Pos 0 /*!< C_CAN0 IR1: INTPND16_1 Position */ -#define C_CAN0_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos) /*!< C_CAN0 IR1: INTPND16_1 Mask */ - -// --------------------------------------- C_CAN0_IR2 ------------------------------------------- -#define C_CAN0_IR2_INTPND32_17_Pos 0 /*!< C_CAN0 IR2: INTPND32_17 Position */ -#define C_CAN0_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos) /*!< C_CAN0 IR2: INTPND32_17 Mask */ - -// -------------------------------------- C_CAN0_MSGV1 ------------------------------------------ -#define C_CAN0_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN0 MSGV1: MSGVAL16_1 Position */ -#define C_CAN0_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask */ - -// -------------------------------------- C_CAN0_MSGV2 ------------------------------------------ -#define C_CAN0_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN0 MSGV2: MSGVAL32_17 Position */ -#define C_CAN0_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask */ - -// -------------------------------------- C_CAN0_CLKDIV ----------------------------------------- -#define C_CAN0_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN0 CLKDIV: CLKDIVVAL Position */ -#define C_CAN0_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- ADC0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- ADC0_CR -------------------------------------------- -#define ADC0_CR_SEL_Pos 0 /*!< ADC0 CR: SEL Position */ -#define ADC0_CR_SEL_Msk (0x000000ffUL << ADC0_CR_SEL_Pos) /*!< ADC0 CR: SEL Mask */ -#define ADC0_CR_CLKDIV_Pos 8 /*!< ADC0 CR: CLKDIV Position */ -#define ADC0_CR_CLKDIV_Msk (0x000000ffUL << ADC0_CR_CLKDIV_Pos) /*!< ADC0 CR: CLKDIV Mask */ -#define ADC0_CR_BURST_Pos 16 /*!< ADC0 CR: BURST Position */ -#define ADC0_CR_BURST_Msk (0x01UL << ADC0_CR_BURST_Pos) /*!< ADC0 CR: BURST Mask */ -#define ADC0_CR_CLKS_Pos 17 /*!< ADC0 CR: CLKS Position */ -#define ADC0_CR_CLKS_Msk (0x07UL << ADC0_CR_CLKS_Pos) /*!< ADC0 CR: CLKS Mask */ -#define ADC0_CR_PDN_Pos 21 /*!< ADC0 CR: PDN Position */ -#define ADC0_CR_PDN_Msk (0x01UL << ADC0_CR_PDN_Pos) /*!< ADC0 CR: PDN Mask */ -#define ADC0_CR_START_Pos 24 /*!< ADC0 CR: START Position */ -#define ADC0_CR_START_Msk (0x07UL << ADC0_CR_START_Pos) /*!< ADC0 CR: START Mask */ -#define ADC0_CR_EDGE_Pos 27 /*!< ADC0 CR: EDGE Position */ -#define ADC0_CR_EDGE_Msk (0x01UL << ADC0_CR_EDGE_Pos) /*!< ADC0 CR: EDGE Mask */ - -// ---------------------------------------- ADC0_GDR -------------------------------------------- -#define ADC0_GDR_V_VREF_Pos 6 /*!< ADC0 GDR: V_VREF Position */ -#define ADC0_GDR_V_VREF_Msk (0x000003ffUL << ADC0_GDR_V_VREF_Pos) /*!< ADC0 GDR: V_VREF Mask */ -#define ADC0_GDR_CHN_Pos 24 /*!< ADC0 GDR: CHN Position */ -#define ADC0_GDR_CHN_Msk (0x07UL << ADC0_GDR_CHN_Pos) /*!< ADC0 GDR: CHN Mask */ -#define ADC0_GDR_OVERRUN_Pos 30 /*!< ADC0 GDR: OVERRUN Position */ -#define ADC0_GDR_OVERRUN_Msk (0x01UL << ADC0_GDR_OVERRUN_Pos) /*!< ADC0 GDR: OVERRUN Mask */ -#define ADC0_GDR_DONE_Pos 31 /*!< ADC0 GDR: DONE Position */ -#define ADC0_GDR_DONE_Msk (0x01UL << ADC0_GDR_DONE_Pos) /*!< ADC0 GDR: DONE Mask */ - -// --------------------------------------- ADC0_INTEN ------------------------------------------- -#define ADC0_INTEN_ADINTEN_Pos 0 /*!< ADC0 INTEN: ADINTEN Position */ -#define ADC0_INTEN_ADINTEN_Msk (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos) /*!< ADC0 INTEN: ADINTEN Mask */ -#define ADC0_INTEN_ADGINTEN_Pos 8 /*!< ADC0 INTEN: ADGINTEN Position */ -#define ADC0_INTEN_ADGINTEN_Msk (0x01UL << ADC0_INTEN_ADGINTEN_Pos) /*!< ADC0 INTEN: ADGINTEN Mask */ - -// ---------------------------------------- ADC0_DR0 -------------------------------------------- -#define ADC0_DR0_V_VREF_Pos 6 /*!< ADC0 DR0: V_VREF Position */ -#define ADC0_DR0_V_VREF_Msk (0x000003ffUL << ADC0_DR0_V_VREF_Pos) /*!< ADC0 DR0: V_VREF Mask */ -#define ADC0_DR0_OVERRUN_Pos 30 /*!< ADC0 DR0: OVERRUN Position */ -#define ADC0_DR0_OVERRUN_Msk (0x01UL << ADC0_DR0_OVERRUN_Pos) /*!< ADC0 DR0: OVERRUN Mask */ -#define ADC0_DR0_DONE_Pos 31 /*!< ADC0 DR0: DONE Position */ -#define ADC0_DR0_DONE_Msk (0x01UL << ADC0_DR0_DONE_Pos) /*!< ADC0 DR0: DONE Mask */ - -// ---------------------------------------- ADC0_DR1 -------------------------------------------- -#define ADC0_DR1_V_VREF_Pos 6 /*!< ADC0 DR1: V_VREF Position */ -#define ADC0_DR1_V_VREF_Msk (0x000003ffUL << ADC0_DR1_V_VREF_Pos) /*!< ADC0 DR1: V_VREF Mask */ -#define ADC0_DR1_OVERRUN_Pos 30 /*!< ADC0 DR1: OVERRUN Position */ -#define ADC0_DR1_OVERRUN_Msk (0x01UL << ADC0_DR1_OVERRUN_Pos) /*!< ADC0 DR1: OVERRUN Mask */ -#define ADC0_DR1_DONE_Pos 31 /*!< ADC0 DR1: DONE Position */ -#define ADC0_DR1_DONE_Msk (0x01UL << ADC0_DR1_DONE_Pos) /*!< ADC0 DR1: DONE Mask */ - -// ---------------------------------------- ADC0_DR2 -------------------------------------------- -#define ADC0_DR2_V_VREF_Pos 6 /*!< ADC0 DR2: V_VREF Position */ -#define ADC0_DR2_V_VREF_Msk (0x000003ffUL << ADC0_DR2_V_VREF_Pos) /*!< ADC0 DR2: V_VREF Mask */ -#define ADC0_DR2_OVERRUN_Pos 30 /*!< ADC0 DR2: OVERRUN Position */ -#define ADC0_DR2_OVERRUN_Msk (0x01UL << ADC0_DR2_OVERRUN_Pos) /*!< ADC0 DR2: OVERRUN Mask */ -#define ADC0_DR2_DONE_Pos 31 /*!< ADC0 DR2: DONE Position */ -#define ADC0_DR2_DONE_Msk (0x01UL << ADC0_DR2_DONE_Pos) /*!< ADC0 DR2: DONE Mask */ - -// ---------------------------------------- ADC0_DR3 -------------------------------------------- -#define ADC0_DR3_V_VREF_Pos 6 /*!< ADC0 DR3: V_VREF Position */ -#define ADC0_DR3_V_VREF_Msk (0x000003ffUL << ADC0_DR3_V_VREF_Pos) /*!< ADC0 DR3: V_VREF Mask */ -#define ADC0_DR3_OVERRUN_Pos 30 /*!< ADC0 DR3: OVERRUN Position */ -#define ADC0_DR3_OVERRUN_Msk (0x01UL << ADC0_DR3_OVERRUN_Pos) /*!< ADC0 DR3: OVERRUN Mask */ -#define ADC0_DR3_DONE_Pos 31 /*!< ADC0 DR3: DONE Position */ -#define ADC0_DR3_DONE_Msk (0x01UL << ADC0_DR3_DONE_Pos) /*!< ADC0 DR3: DONE Mask */ - -// ---------------------------------------- ADC0_DR4 -------------------------------------------- -#define ADC0_DR4_V_VREF_Pos 6 /*!< ADC0 DR4: V_VREF Position */ -#define ADC0_DR4_V_VREF_Msk (0x000003ffUL << ADC0_DR4_V_VREF_Pos) /*!< ADC0 DR4: V_VREF Mask */ -#define ADC0_DR4_OVERRUN_Pos 30 /*!< ADC0 DR4: OVERRUN Position */ -#define ADC0_DR4_OVERRUN_Msk (0x01UL << ADC0_DR4_OVERRUN_Pos) /*!< ADC0 DR4: OVERRUN Mask */ -#define ADC0_DR4_DONE_Pos 31 /*!< ADC0 DR4: DONE Position */ -#define ADC0_DR4_DONE_Msk (0x01UL << ADC0_DR4_DONE_Pos) /*!< ADC0 DR4: DONE Mask */ - -// ---------------------------------------- ADC0_DR5 -------------------------------------------- -#define ADC0_DR5_V_VREF_Pos 6 /*!< ADC0 DR5: V_VREF Position */ -#define ADC0_DR5_V_VREF_Msk (0x000003ffUL << ADC0_DR5_V_VREF_Pos) /*!< ADC0 DR5: V_VREF Mask */ -#define ADC0_DR5_OVERRUN_Pos 30 /*!< ADC0 DR5: OVERRUN Position */ -#define ADC0_DR5_OVERRUN_Msk (0x01UL << ADC0_DR5_OVERRUN_Pos) /*!< ADC0 DR5: OVERRUN Mask */ -#define ADC0_DR5_DONE_Pos 31 /*!< ADC0 DR5: DONE Position */ -#define ADC0_DR5_DONE_Msk (0x01UL << ADC0_DR5_DONE_Pos) /*!< ADC0 DR5: DONE Mask */ - -// ---------------------------------------- ADC0_DR6 -------------------------------------------- -#define ADC0_DR6_V_VREF_Pos 6 /*!< ADC0 DR6: V_VREF Position */ -#define ADC0_DR6_V_VREF_Msk (0x000003ffUL << ADC0_DR6_V_VREF_Pos) /*!< ADC0 DR6: V_VREF Mask */ -#define ADC0_DR6_OVERRUN_Pos 30 /*!< ADC0 DR6: OVERRUN Position */ -#define ADC0_DR6_OVERRUN_Msk (0x01UL << ADC0_DR6_OVERRUN_Pos) /*!< ADC0 DR6: OVERRUN Mask */ -#define ADC0_DR6_DONE_Pos 31 /*!< ADC0 DR6: DONE Position */ -#define ADC0_DR6_DONE_Msk (0x01UL << ADC0_DR6_DONE_Pos) /*!< ADC0 DR6: DONE Mask */ - -// ---------------------------------------- ADC0_DR7 -------------------------------------------- -#define ADC0_DR7_V_VREF_Pos 6 /*!< ADC0 DR7: V_VREF Position */ -#define ADC0_DR7_V_VREF_Msk (0x000003ffUL << ADC0_DR7_V_VREF_Pos) /*!< ADC0 DR7: V_VREF Mask */ -#define ADC0_DR7_OVERRUN_Pos 30 /*!< ADC0 DR7: OVERRUN Position */ -#define ADC0_DR7_OVERRUN_Msk (0x01UL << ADC0_DR7_OVERRUN_Pos) /*!< ADC0 DR7: OVERRUN Mask */ -#define ADC0_DR7_DONE_Pos 31 /*!< ADC0 DR7: DONE Position */ -#define ADC0_DR7_DONE_Msk (0x01UL << ADC0_DR7_DONE_Pos) /*!< ADC0 DR7: DONE Mask */ - -// ---------------------------------------- ADC0_STAT ------------------------------------------- -#define ADC0_STAT_DONE_Pos 0 /*!< ADC0 STAT: DONE Position */ -#define ADC0_STAT_DONE_Msk (0x000000ffUL << ADC0_STAT_DONE_Pos) /*!< ADC0 STAT: DONE Mask */ -#define ADC0_STAT_OVERUN_Pos 8 /*!< ADC0 STAT: OVERUN Position */ -#define ADC0_STAT_OVERUN_Msk (0x000000ffUL << ADC0_STAT_OVERUN_Pos) /*!< ADC0 STAT: OVERUN Mask */ -#define ADC0_STAT_ADINT_Pos 16 /*!< ADC0 STAT: ADINT Position */ -#define ADC0_STAT_ADINT_Msk (0x01UL << ADC0_STAT_ADINT_Pos) /*!< ADC0 STAT: ADINT Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- ADC1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- ADC1_CR -------------------------------------------- -#define ADC1_CR_SEL_Pos 0 /*!< ADC1 CR: SEL Position */ -#define ADC1_CR_SEL_Msk (0x000000ffUL << ADC1_CR_SEL_Pos) /*!< ADC1 CR: SEL Mask */ -#define ADC1_CR_CLKDIV_Pos 8 /*!< ADC1 CR: CLKDIV Position */ -#define ADC1_CR_CLKDIV_Msk (0x000000ffUL << ADC1_CR_CLKDIV_Pos) /*!< ADC1 CR: CLKDIV Mask */ -#define ADC1_CR_BURST_Pos 16 /*!< ADC1 CR: BURST Position */ -#define ADC1_CR_BURST_Msk (0x01UL << ADC1_CR_BURST_Pos) /*!< ADC1 CR: BURST Mask */ -#define ADC1_CR_CLKS_Pos 17 /*!< ADC1 CR: CLKS Position */ -#define ADC1_CR_CLKS_Msk (0x07UL << ADC1_CR_CLKS_Pos) /*!< ADC1 CR: CLKS Mask */ -#define ADC1_CR_PDN_Pos 21 /*!< ADC1 CR: PDN Position */ -#define ADC1_CR_PDN_Msk (0x01UL << ADC1_CR_PDN_Pos) /*!< ADC1 CR: PDN Mask */ -#define ADC1_CR_START_Pos 24 /*!< ADC1 CR: START Position */ -#define ADC1_CR_START_Msk (0x07UL << ADC1_CR_START_Pos) /*!< ADC1 CR: START Mask */ -#define ADC1_CR_EDGE_Pos 27 /*!< ADC1 CR: EDGE Position */ -#define ADC1_CR_EDGE_Msk (0x01UL << ADC1_CR_EDGE_Pos) /*!< ADC1 CR: EDGE Mask */ - -// ---------------------------------------- ADC1_GDR -------------------------------------------- -#define ADC1_GDR_V_VREF_Pos 6 /*!< ADC1 GDR: V_VREF Position */ -#define ADC1_GDR_V_VREF_Msk (0x000003ffUL << ADC1_GDR_V_VREF_Pos) /*!< ADC1 GDR: V_VREF Mask */ -#define ADC1_GDR_CHN_Pos 24 /*!< ADC1 GDR: CHN Position */ -#define ADC1_GDR_CHN_Msk (0x07UL << ADC1_GDR_CHN_Pos) /*!< ADC1 GDR: CHN Mask */ -#define ADC1_GDR_OVERRUN_Pos 30 /*!< ADC1 GDR: OVERRUN Position */ -#define ADC1_GDR_OVERRUN_Msk (0x01UL << ADC1_GDR_OVERRUN_Pos) /*!< ADC1 GDR: OVERRUN Mask */ -#define ADC1_GDR_DONE_Pos 31 /*!< ADC1 GDR: DONE Position */ -#define ADC1_GDR_DONE_Msk (0x01UL << ADC1_GDR_DONE_Pos) /*!< ADC1 GDR: DONE Mask */ - -// --------------------------------------- ADC1_INTEN ------------------------------------------- -#define ADC1_INTEN_ADINTEN_Pos 0 /*!< ADC1 INTEN: ADINTEN Position */ -#define ADC1_INTEN_ADINTEN_Msk (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos) /*!< ADC1 INTEN: ADINTEN Mask */ -#define ADC1_INTEN_ADGINTEN_Pos 8 /*!< ADC1 INTEN: ADGINTEN Position */ -#define ADC1_INTEN_ADGINTEN_Msk (0x01UL << ADC1_INTEN_ADGINTEN_Pos) /*!< ADC1 INTEN: ADGINTEN Mask */ - -// ---------------------------------------- ADC1_DR0 -------------------------------------------- -#define ADC1_DR0_V_VREF_Pos 6 /*!< ADC1 DR0: V_VREF Position */ -#define ADC1_DR0_V_VREF_Msk (0x000003ffUL << ADC1_DR0_V_VREF_Pos) /*!< ADC1 DR0: V_VREF Mask */ -#define ADC1_DR0_OVERRUN_Pos 30 /*!< ADC1 DR0: OVERRUN Position */ -#define ADC1_DR0_OVERRUN_Msk (0x01UL << ADC1_DR0_OVERRUN_Pos) /*!< ADC1 DR0: OVERRUN Mask */ -#define ADC1_DR0_DONE_Pos 31 /*!< ADC1 DR0: DONE Position */ -#define ADC1_DR0_DONE_Msk (0x01UL << ADC1_DR0_DONE_Pos) /*!< ADC1 DR0: DONE Mask */ - -// ---------------------------------------- ADC1_DR1 -------------------------------------------- -#define ADC1_DR1_V_VREF_Pos 6 /*!< ADC1 DR1: V_VREF Position */ -#define ADC1_DR1_V_VREF_Msk (0x000003ffUL << ADC1_DR1_V_VREF_Pos) /*!< ADC1 DR1: V_VREF Mask */ -#define ADC1_DR1_OVERRUN_Pos 30 /*!< ADC1 DR1: OVERRUN Position */ -#define ADC1_DR1_OVERRUN_Msk (0x01UL << ADC1_DR1_OVERRUN_Pos) /*!< ADC1 DR1: OVERRUN Mask */ -#define ADC1_DR1_DONE_Pos 31 /*!< ADC1 DR1: DONE Position */ -#define ADC1_DR1_DONE_Msk (0x01UL << ADC1_DR1_DONE_Pos) /*!< ADC1 DR1: DONE Mask */ - -// ---------------------------------------- ADC1_DR2 -------------------------------------------- -#define ADC1_DR2_V_VREF_Pos 6 /*!< ADC1 DR2: V_VREF Position */ -#define ADC1_DR2_V_VREF_Msk (0x000003ffUL << ADC1_DR2_V_VREF_Pos) /*!< ADC1 DR2: V_VREF Mask */ -#define ADC1_DR2_OVERRUN_Pos 30 /*!< ADC1 DR2: OVERRUN Position */ -#define ADC1_DR2_OVERRUN_Msk (0x01UL << ADC1_DR2_OVERRUN_Pos) /*!< ADC1 DR2: OVERRUN Mask */ -#define ADC1_DR2_DONE_Pos 31 /*!< ADC1 DR2: DONE Position */ -#define ADC1_DR2_DONE_Msk (0x01UL << ADC1_DR2_DONE_Pos) /*!< ADC1 DR2: DONE Mask */ - -// ---------------------------------------- ADC1_DR3 -------------------------------------------- -#define ADC1_DR3_V_VREF_Pos 6 /*!< ADC1 DR3: V_VREF Position */ -#define ADC1_DR3_V_VREF_Msk (0x000003ffUL << ADC1_DR3_V_VREF_Pos) /*!< ADC1 DR3: V_VREF Mask */ -#define ADC1_DR3_OVERRUN_Pos 30 /*!< ADC1 DR3: OVERRUN Position */ -#define ADC1_DR3_OVERRUN_Msk (0x01UL << ADC1_DR3_OVERRUN_Pos) /*!< ADC1 DR3: OVERRUN Mask */ -#define ADC1_DR3_DONE_Pos 31 /*!< ADC1 DR3: DONE Position */ -#define ADC1_DR3_DONE_Msk (0x01UL << ADC1_DR3_DONE_Pos) /*!< ADC1 DR3: DONE Mask */ - -// ---------------------------------------- ADC1_DR4 -------------------------------------------- -#define ADC1_DR4_V_VREF_Pos 6 /*!< ADC1 DR4: V_VREF Position */ -#define ADC1_DR4_V_VREF_Msk (0x000003ffUL << ADC1_DR4_V_VREF_Pos) /*!< ADC1 DR4: V_VREF Mask */ -#define ADC1_DR4_OVERRUN_Pos 30 /*!< ADC1 DR4: OVERRUN Position */ -#define ADC1_DR4_OVERRUN_Msk (0x01UL << ADC1_DR4_OVERRUN_Pos) /*!< ADC1 DR4: OVERRUN Mask */ -#define ADC1_DR4_DONE_Pos 31 /*!< ADC1 DR4: DONE Position */ -#define ADC1_DR4_DONE_Msk (0x01UL << ADC1_DR4_DONE_Pos) /*!< ADC1 DR4: DONE Mask */ - -// ---------------------------------------- ADC1_DR5 -------------------------------------------- -#define ADC1_DR5_V_VREF_Pos 6 /*!< ADC1 DR5: V_VREF Position */ -#define ADC1_DR5_V_VREF_Msk (0x000003ffUL << ADC1_DR5_V_VREF_Pos) /*!< ADC1 DR5: V_VREF Mask */ -#define ADC1_DR5_OVERRUN_Pos 30 /*!< ADC1 DR5: OVERRUN Position */ -#define ADC1_DR5_OVERRUN_Msk (0x01UL << ADC1_DR5_OVERRUN_Pos) /*!< ADC1 DR5: OVERRUN Mask */ -#define ADC1_DR5_DONE_Pos 31 /*!< ADC1 DR5: DONE Position */ -#define ADC1_DR5_DONE_Msk (0x01UL << ADC1_DR5_DONE_Pos) /*!< ADC1 DR5: DONE Mask */ - -// ---------------------------------------- ADC1_DR6 -------------------------------------------- -#define ADC1_DR6_V_VREF_Pos 6 /*!< ADC1 DR6: V_VREF Position */ -#define ADC1_DR6_V_VREF_Msk (0x000003ffUL << ADC1_DR6_V_VREF_Pos) /*!< ADC1 DR6: V_VREF Mask */ -#define ADC1_DR6_OVERRUN_Pos 30 /*!< ADC1 DR6: OVERRUN Position */ -#define ADC1_DR6_OVERRUN_Msk (0x01UL << ADC1_DR6_OVERRUN_Pos) /*!< ADC1 DR6: OVERRUN Mask */ -#define ADC1_DR6_DONE_Pos 31 /*!< ADC1 DR6: DONE Position */ -#define ADC1_DR6_DONE_Msk (0x01UL << ADC1_DR6_DONE_Pos) /*!< ADC1 DR6: DONE Mask */ - -// ---------------------------------------- ADC1_DR7 -------------------------------------------- -#define ADC1_DR7_V_VREF_Pos 6 /*!< ADC1 DR7: V_VREF Position */ -#define ADC1_DR7_V_VREF_Msk (0x000003ffUL << ADC1_DR7_V_VREF_Pos) /*!< ADC1 DR7: V_VREF Mask */ -#define ADC1_DR7_OVERRUN_Pos 30 /*!< ADC1 DR7: OVERRUN Position */ -#define ADC1_DR7_OVERRUN_Msk (0x01UL << ADC1_DR7_OVERRUN_Pos) /*!< ADC1 DR7: OVERRUN Mask */ -#define ADC1_DR7_DONE_Pos 31 /*!< ADC1 DR7: DONE Position */ -#define ADC1_DR7_DONE_Msk (0x01UL << ADC1_DR7_DONE_Pos) /*!< ADC1 DR7: DONE Mask */ - -// ---------------------------------------- ADC1_STAT ------------------------------------------- -#define ADC1_STAT_DONE_Pos 0 /*!< ADC1 STAT: DONE Position */ -#define ADC1_STAT_DONE_Msk (0x000000ffUL << ADC1_STAT_DONE_Pos) /*!< ADC1 STAT: DONE Mask */ -#define ADC1_STAT_OVERUN_Pos 8 /*!< ADC1 STAT: OVERUN Position */ -#define ADC1_STAT_OVERUN_Msk (0x000000ffUL << ADC1_STAT_OVERUN_Pos) /*!< ADC1 STAT: OVERUN Mask */ -#define ADC1_STAT_ADINT_Pos 16 /*!< ADC1 STAT: ADINT Position */ -#define ADC1_STAT_ADINT_Msk (0x01UL << ADC1_STAT_ADINT_Pos) /*!< ADC1 STAT: ADINT Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// -------------------------------------- GPIO_PORT_B0 ------------------------------------------ -#define GPIO_PORT_B0_PBYTE_Pos 0 /*!< GPIO_PORT B0: PBYTE Position */ -#define GPIO_PORT_B0_PBYTE_Msk (0x01UL << GPIO_PORT_B0_PBYTE_Pos) /*!< GPIO_PORT B0: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B1 ------------------------------------------ -#define GPIO_PORT_B1_PBYTE_Pos 0 /*!< GPIO_PORT B1: PBYTE Position */ -#define GPIO_PORT_B1_PBYTE_Msk (0x01UL << GPIO_PORT_B1_PBYTE_Pos) /*!< GPIO_PORT B1: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B2 ------------------------------------------ -#define GPIO_PORT_B2_PBYTE_Pos 0 /*!< GPIO_PORT B2: PBYTE Position */ -#define GPIO_PORT_B2_PBYTE_Msk (0x01UL << GPIO_PORT_B2_PBYTE_Pos) /*!< GPIO_PORT B2: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B3 ------------------------------------------ -#define GPIO_PORT_B3_PBYTE_Pos 0 /*!< GPIO_PORT B3: PBYTE Position */ -#define GPIO_PORT_B3_PBYTE_Msk (0x01UL << GPIO_PORT_B3_PBYTE_Pos) /*!< GPIO_PORT B3: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B4 ------------------------------------------ -#define GPIO_PORT_B4_PBYTE_Pos 0 /*!< GPIO_PORT B4: PBYTE Position */ -#define GPIO_PORT_B4_PBYTE_Msk (0x01UL << GPIO_PORT_B4_PBYTE_Pos) /*!< GPIO_PORT B4: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B5 ------------------------------------------ -#define GPIO_PORT_B5_PBYTE_Pos 0 /*!< GPIO_PORT B5: PBYTE Position */ -#define GPIO_PORT_B5_PBYTE_Msk (0x01UL << GPIO_PORT_B5_PBYTE_Pos) /*!< GPIO_PORT B5: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B6 ------------------------------------------ -#define GPIO_PORT_B6_PBYTE_Pos 0 /*!< GPIO_PORT B6: PBYTE Position */ -#define GPIO_PORT_B6_PBYTE_Msk (0x01UL << GPIO_PORT_B6_PBYTE_Pos) /*!< GPIO_PORT B6: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B7 ------------------------------------------ -#define GPIO_PORT_B7_PBYTE_Pos 0 /*!< GPIO_PORT B7: PBYTE Position */ -#define GPIO_PORT_B7_PBYTE_Msk (0x01UL << GPIO_PORT_B7_PBYTE_Pos) /*!< GPIO_PORT B7: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B8 ------------------------------------------ -#define GPIO_PORT_B8_PBYTE_Pos 0 /*!< GPIO_PORT B8: PBYTE Position */ -#define GPIO_PORT_B8_PBYTE_Msk (0x01UL << GPIO_PORT_B8_PBYTE_Pos) /*!< GPIO_PORT B8: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B9 ------------------------------------------ -#define GPIO_PORT_B9_PBYTE_Pos 0 /*!< GPIO_PORT B9: PBYTE Position */ -#define GPIO_PORT_B9_PBYTE_Msk (0x01UL << GPIO_PORT_B9_PBYTE_Pos) /*!< GPIO_PORT B9: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B10 ----------------------------------------- -#define GPIO_PORT_B10_PBYTE_Pos 0 /*!< GPIO_PORT B10: PBYTE Position */ -#define GPIO_PORT_B10_PBYTE_Msk (0x01UL << GPIO_PORT_B10_PBYTE_Pos) /*!< GPIO_PORT B10: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B11 ----------------------------------------- -#define GPIO_PORT_B11_PBYTE_Pos 0 /*!< GPIO_PORT B11: PBYTE Position */ -#define GPIO_PORT_B11_PBYTE_Msk (0x01UL << GPIO_PORT_B11_PBYTE_Pos) /*!< GPIO_PORT B11: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B12 ----------------------------------------- -#define GPIO_PORT_B12_PBYTE_Pos 0 /*!< GPIO_PORT B12: PBYTE Position */ -#define GPIO_PORT_B12_PBYTE_Msk (0x01UL << GPIO_PORT_B12_PBYTE_Pos) /*!< GPIO_PORT B12: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B13 ----------------------------------------- -#define GPIO_PORT_B13_PBYTE_Pos 0 /*!< GPIO_PORT B13: PBYTE Position */ -#define GPIO_PORT_B13_PBYTE_Msk (0x01UL << GPIO_PORT_B13_PBYTE_Pos) /*!< GPIO_PORT B13: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B14 ----------------------------------------- -#define GPIO_PORT_B14_PBYTE_Pos 0 /*!< GPIO_PORT B14: PBYTE Position */ -#define GPIO_PORT_B14_PBYTE_Msk (0x01UL << GPIO_PORT_B14_PBYTE_Pos) /*!< GPIO_PORT B14: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B15 ----------------------------------------- -#define GPIO_PORT_B15_PBYTE_Pos 0 /*!< GPIO_PORT B15: PBYTE Position */ -#define GPIO_PORT_B15_PBYTE_Msk (0x01UL << GPIO_PORT_B15_PBYTE_Pos) /*!< GPIO_PORT B15: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B16 ----------------------------------------- -#define GPIO_PORT_B16_PBYTE_Pos 0 /*!< GPIO_PORT B16: PBYTE Position */ -#define GPIO_PORT_B16_PBYTE_Msk (0x01UL << GPIO_PORT_B16_PBYTE_Pos) /*!< GPIO_PORT B16: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B17 ----------------------------------------- -#define GPIO_PORT_B17_PBYTE_Pos 0 /*!< GPIO_PORT B17: PBYTE Position */ -#define GPIO_PORT_B17_PBYTE_Msk (0x01UL << GPIO_PORT_B17_PBYTE_Pos) /*!< GPIO_PORT B17: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B18 ----------------------------------------- -#define GPIO_PORT_B18_PBYTE_Pos 0 /*!< GPIO_PORT B18: PBYTE Position */ -#define GPIO_PORT_B18_PBYTE_Msk (0x01UL << GPIO_PORT_B18_PBYTE_Pos) /*!< GPIO_PORT B18: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B19 ----------------------------------------- -#define GPIO_PORT_B19_PBYTE_Pos 0 /*!< GPIO_PORT B19: PBYTE Position */ -#define GPIO_PORT_B19_PBYTE_Msk (0x01UL << GPIO_PORT_B19_PBYTE_Pos) /*!< GPIO_PORT B19: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B20 ----------------------------------------- -#define GPIO_PORT_B20_PBYTE_Pos 0 /*!< GPIO_PORT B20: PBYTE Position */ -#define GPIO_PORT_B20_PBYTE_Msk (0x01UL << GPIO_PORT_B20_PBYTE_Pos) /*!< GPIO_PORT B20: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B21 ----------------------------------------- -#define GPIO_PORT_B21_PBYTE_Pos 0 /*!< GPIO_PORT B21: PBYTE Position */ -#define GPIO_PORT_B21_PBYTE_Msk (0x01UL << GPIO_PORT_B21_PBYTE_Pos) /*!< GPIO_PORT B21: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B22 ----------------------------------------- -#define GPIO_PORT_B22_PBYTE_Pos 0 /*!< GPIO_PORT B22: PBYTE Position */ -#define GPIO_PORT_B22_PBYTE_Msk (0x01UL << GPIO_PORT_B22_PBYTE_Pos) /*!< GPIO_PORT B22: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B23 ----------------------------------------- -#define GPIO_PORT_B23_PBYTE_Pos 0 /*!< GPIO_PORT B23: PBYTE Position */ -#define GPIO_PORT_B23_PBYTE_Msk (0x01UL << GPIO_PORT_B23_PBYTE_Pos) /*!< GPIO_PORT B23: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B24 ----------------------------------------- -#define GPIO_PORT_B24_PBYTE_Pos 0 /*!< GPIO_PORT B24: PBYTE Position */ -#define GPIO_PORT_B24_PBYTE_Msk (0x01UL << GPIO_PORT_B24_PBYTE_Pos) /*!< GPIO_PORT B24: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B25 ----------------------------------------- -#define GPIO_PORT_B25_PBYTE_Pos 0 /*!< GPIO_PORT B25: PBYTE Position */ -#define GPIO_PORT_B25_PBYTE_Msk (0x01UL << GPIO_PORT_B25_PBYTE_Pos) /*!< GPIO_PORT B25: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B26 ----------------------------------------- -#define GPIO_PORT_B26_PBYTE_Pos 0 /*!< GPIO_PORT B26: PBYTE Position */ -#define GPIO_PORT_B26_PBYTE_Msk (0x01UL << GPIO_PORT_B26_PBYTE_Pos) /*!< GPIO_PORT B26: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B27 ----------------------------------------- -#define GPIO_PORT_B27_PBYTE_Pos 0 /*!< GPIO_PORT B27: PBYTE Position */ -#define GPIO_PORT_B27_PBYTE_Msk (0x01UL << GPIO_PORT_B27_PBYTE_Pos) /*!< GPIO_PORT B27: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B28 ----------------------------------------- -#define GPIO_PORT_B28_PBYTE_Pos 0 /*!< GPIO_PORT B28: PBYTE Position */ -#define GPIO_PORT_B28_PBYTE_Msk (0x01UL << GPIO_PORT_B28_PBYTE_Pos) /*!< GPIO_PORT B28: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B29 ----------------------------------------- -#define GPIO_PORT_B29_PBYTE_Pos 0 /*!< GPIO_PORT B29: PBYTE Position */ -#define GPIO_PORT_B29_PBYTE_Msk (0x01UL << GPIO_PORT_B29_PBYTE_Pos) /*!< GPIO_PORT B29: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B30 ----------------------------------------- -#define GPIO_PORT_B30_PBYTE_Pos 0 /*!< GPIO_PORT B30: PBYTE Position */ -#define GPIO_PORT_B30_PBYTE_Msk (0x01UL << GPIO_PORT_B30_PBYTE_Pos) /*!< GPIO_PORT B30: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B31 ----------------------------------------- -#define GPIO_PORT_B31_PBYTE_Pos 0 /*!< GPIO_PORT B31: PBYTE Position */ -#define GPIO_PORT_B31_PBYTE_Msk (0x01UL << GPIO_PORT_B31_PBYTE_Pos) /*!< GPIO_PORT B31: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B32 ----------------------------------------- -#define GPIO_PORT_B32_PBYTE_Pos 0 /*!< GPIO_PORT B32: PBYTE Position */ -#define GPIO_PORT_B32_PBYTE_Msk (0x01UL << GPIO_PORT_B32_PBYTE_Pos) /*!< GPIO_PORT B32: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B33 ----------------------------------------- -#define GPIO_PORT_B33_PBYTE_Pos 0 /*!< GPIO_PORT B33: PBYTE Position */ -#define GPIO_PORT_B33_PBYTE_Msk (0x01UL << GPIO_PORT_B33_PBYTE_Pos) /*!< GPIO_PORT B33: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B34 ----------------------------------------- -#define GPIO_PORT_B34_PBYTE_Pos 0 /*!< GPIO_PORT B34: PBYTE Position */ -#define GPIO_PORT_B34_PBYTE_Msk (0x01UL << GPIO_PORT_B34_PBYTE_Pos) /*!< GPIO_PORT B34: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B35 ----------------------------------------- -#define GPIO_PORT_B35_PBYTE_Pos 0 /*!< GPIO_PORT B35: PBYTE Position */ -#define GPIO_PORT_B35_PBYTE_Msk (0x01UL << GPIO_PORT_B35_PBYTE_Pos) /*!< GPIO_PORT B35: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B36 ----------------------------------------- -#define GPIO_PORT_B36_PBYTE_Pos 0 /*!< GPIO_PORT B36: PBYTE Position */ -#define GPIO_PORT_B36_PBYTE_Msk (0x01UL << GPIO_PORT_B36_PBYTE_Pos) /*!< GPIO_PORT B36: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B37 ----------------------------------------- -#define GPIO_PORT_B37_PBYTE_Pos 0 /*!< GPIO_PORT B37: PBYTE Position */ -#define GPIO_PORT_B37_PBYTE_Msk (0x01UL << GPIO_PORT_B37_PBYTE_Pos) /*!< GPIO_PORT B37: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B38 ----------------------------------------- -#define GPIO_PORT_B38_PBYTE_Pos 0 /*!< GPIO_PORT B38: PBYTE Position */ -#define GPIO_PORT_B38_PBYTE_Msk (0x01UL << GPIO_PORT_B38_PBYTE_Pos) /*!< GPIO_PORT B38: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B39 ----------------------------------------- -#define GPIO_PORT_B39_PBYTE_Pos 0 /*!< GPIO_PORT B39: PBYTE Position */ -#define GPIO_PORT_B39_PBYTE_Msk (0x01UL << GPIO_PORT_B39_PBYTE_Pos) /*!< GPIO_PORT B39: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B40 ----------------------------------------- -#define GPIO_PORT_B40_PBYTE_Pos 0 /*!< GPIO_PORT B40: PBYTE Position */ -#define GPIO_PORT_B40_PBYTE_Msk (0x01UL << GPIO_PORT_B40_PBYTE_Pos) /*!< GPIO_PORT B40: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B41 ----------------------------------------- -#define GPIO_PORT_B41_PBYTE_Pos 0 /*!< GPIO_PORT B41: PBYTE Position */ -#define GPIO_PORT_B41_PBYTE_Msk (0x01UL << GPIO_PORT_B41_PBYTE_Pos) /*!< GPIO_PORT B41: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B42 ----------------------------------------- -#define GPIO_PORT_B42_PBYTE_Pos 0 /*!< GPIO_PORT B42: PBYTE Position */ -#define GPIO_PORT_B42_PBYTE_Msk (0x01UL << GPIO_PORT_B42_PBYTE_Pos) /*!< GPIO_PORT B42: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B43 ----------------------------------------- -#define GPIO_PORT_B43_PBYTE_Pos 0 /*!< GPIO_PORT B43: PBYTE Position */ -#define GPIO_PORT_B43_PBYTE_Msk (0x01UL << GPIO_PORT_B43_PBYTE_Pos) /*!< GPIO_PORT B43: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B44 ----------------------------------------- -#define GPIO_PORT_B44_PBYTE_Pos 0 /*!< GPIO_PORT B44: PBYTE Position */ -#define GPIO_PORT_B44_PBYTE_Msk (0x01UL << GPIO_PORT_B44_PBYTE_Pos) /*!< GPIO_PORT B44: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B45 ----------------------------------------- -#define GPIO_PORT_B45_PBYTE_Pos 0 /*!< GPIO_PORT B45: PBYTE Position */ -#define GPIO_PORT_B45_PBYTE_Msk (0x01UL << GPIO_PORT_B45_PBYTE_Pos) /*!< GPIO_PORT B45: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B46 ----------------------------------------- -#define GPIO_PORT_B46_PBYTE_Pos 0 /*!< GPIO_PORT B46: PBYTE Position */ -#define GPIO_PORT_B46_PBYTE_Msk (0x01UL << GPIO_PORT_B46_PBYTE_Pos) /*!< GPIO_PORT B46: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B47 ----------------------------------------- -#define GPIO_PORT_B47_PBYTE_Pos 0 /*!< GPIO_PORT B47: PBYTE Position */ -#define GPIO_PORT_B47_PBYTE_Msk (0x01UL << GPIO_PORT_B47_PBYTE_Pos) /*!< GPIO_PORT B47: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B48 ----------------------------------------- -#define GPIO_PORT_B48_PBYTE_Pos 0 /*!< GPIO_PORT B48: PBYTE Position */ -#define GPIO_PORT_B48_PBYTE_Msk (0x01UL << GPIO_PORT_B48_PBYTE_Pos) /*!< GPIO_PORT B48: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B49 ----------------------------------------- -#define GPIO_PORT_B49_PBYTE_Pos 0 /*!< GPIO_PORT B49: PBYTE Position */ -#define GPIO_PORT_B49_PBYTE_Msk (0x01UL << GPIO_PORT_B49_PBYTE_Pos) /*!< GPIO_PORT B49: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B50 ----------------------------------------- -#define GPIO_PORT_B50_PBYTE_Pos 0 /*!< GPIO_PORT B50: PBYTE Position */ -#define GPIO_PORT_B50_PBYTE_Msk (0x01UL << GPIO_PORT_B50_PBYTE_Pos) /*!< GPIO_PORT B50: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B51 ----------------------------------------- -#define GPIO_PORT_B51_PBYTE_Pos 0 /*!< GPIO_PORT B51: PBYTE Position */ -#define GPIO_PORT_B51_PBYTE_Msk (0x01UL << GPIO_PORT_B51_PBYTE_Pos) /*!< GPIO_PORT B51: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B52 ----------------------------------------- -#define GPIO_PORT_B52_PBYTE_Pos 0 /*!< GPIO_PORT B52: PBYTE Position */ -#define GPIO_PORT_B52_PBYTE_Msk (0x01UL << GPIO_PORT_B52_PBYTE_Pos) /*!< GPIO_PORT B52: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B53 ----------------------------------------- -#define GPIO_PORT_B53_PBYTE_Pos 0 /*!< GPIO_PORT B53: PBYTE Position */ -#define GPIO_PORT_B53_PBYTE_Msk (0x01UL << GPIO_PORT_B53_PBYTE_Pos) /*!< GPIO_PORT B53: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B54 ----------------------------------------- -#define GPIO_PORT_B54_PBYTE_Pos 0 /*!< GPIO_PORT B54: PBYTE Position */ -#define GPIO_PORT_B54_PBYTE_Msk (0x01UL << GPIO_PORT_B54_PBYTE_Pos) /*!< GPIO_PORT B54: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B55 ----------------------------------------- -#define GPIO_PORT_B55_PBYTE_Pos 0 /*!< GPIO_PORT B55: PBYTE Position */ -#define GPIO_PORT_B55_PBYTE_Msk (0x01UL << GPIO_PORT_B55_PBYTE_Pos) /*!< GPIO_PORT B55: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B56 ----------------------------------------- -#define GPIO_PORT_B56_PBYTE_Pos 0 /*!< GPIO_PORT B56: PBYTE Position */ -#define GPIO_PORT_B56_PBYTE_Msk (0x01UL << GPIO_PORT_B56_PBYTE_Pos) /*!< GPIO_PORT B56: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B57 ----------------------------------------- -#define GPIO_PORT_B57_PBYTE_Pos 0 /*!< GPIO_PORT B57: PBYTE Position */ -#define GPIO_PORT_B57_PBYTE_Msk (0x01UL << GPIO_PORT_B57_PBYTE_Pos) /*!< GPIO_PORT B57: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B58 ----------------------------------------- -#define GPIO_PORT_B58_PBYTE_Pos 0 /*!< GPIO_PORT B58: PBYTE Position */ -#define GPIO_PORT_B58_PBYTE_Msk (0x01UL << GPIO_PORT_B58_PBYTE_Pos) /*!< GPIO_PORT B58: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B59 ----------------------------------------- -#define GPIO_PORT_B59_PBYTE_Pos 0 /*!< GPIO_PORT B59: PBYTE Position */ -#define GPIO_PORT_B59_PBYTE_Msk (0x01UL << GPIO_PORT_B59_PBYTE_Pos) /*!< GPIO_PORT B59: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B60 ----------------------------------------- -#define GPIO_PORT_B60_PBYTE_Pos 0 /*!< GPIO_PORT B60: PBYTE Position */ -#define GPIO_PORT_B60_PBYTE_Msk (0x01UL << GPIO_PORT_B60_PBYTE_Pos) /*!< GPIO_PORT B60: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B61 ----------------------------------------- -#define GPIO_PORT_B61_PBYTE_Pos 0 /*!< GPIO_PORT B61: PBYTE Position */ -#define GPIO_PORT_B61_PBYTE_Msk (0x01UL << GPIO_PORT_B61_PBYTE_Pos) /*!< GPIO_PORT B61: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B62 ----------------------------------------- -#define GPIO_PORT_B62_PBYTE_Pos 0 /*!< GPIO_PORT B62: PBYTE Position */ -#define GPIO_PORT_B62_PBYTE_Msk (0x01UL << GPIO_PORT_B62_PBYTE_Pos) /*!< GPIO_PORT B62: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B63 ----------------------------------------- -#define GPIO_PORT_B63_PBYTE_Pos 0 /*!< GPIO_PORT B63: PBYTE Position */ -#define GPIO_PORT_B63_PBYTE_Msk (0x01UL << GPIO_PORT_B63_PBYTE_Pos) /*!< GPIO_PORT B63: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B64 ----------------------------------------- -#define GPIO_PORT_B64_PBYTE_Pos 0 /*!< GPIO_PORT B64: PBYTE Position */ -#define GPIO_PORT_B64_PBYTE_Msk (0x01UL << GPIO_PORT_B64_PBYTE_Pos) /*!< GPIO_PORT B64: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B65 ----------------------------------------- -#define GPIO_PORT_B65_PBYTE_Pos 0 /*!< GPIO_PORT B65: PBYTE Position */ -#define GPIO_PORT_B65_PBYTE_Msk (0x01UL << GPIO_PORT_B65_PBYTE_Pos) /*!< GPIO_PORT B65: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B66 ----------------------------------------- -#define GPIO_PORT_B66_PBYTE_Pos 0 /*!< GPIO_PORT B66: PBYTE Position */ -#define GPIO_PORT_B66_PBYTE_Msk (0x01UL << GPIO_PORT_B66_PBYTE_Pos) /*!< GPIO_PORT B66: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B67 ----------------------------------------- -#define GPIO_PORT_B67_PBYTE_Pos 0 /*!< GPIO_PORT B67: PBYTE Position */ -#define GPIO_PORT_B67_PBYTE_Msk (0x01UL << GPIO_PORT_B67_PBYTE_Pos) /*!< GPIO_PORT B67: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B68 ----------------------------------------- -#define GPIO_PORT_B68_PBYTE_Pos 0 /*!< GPIO_PORT B68: PBYTE Position */ -#define GPIO_PORT_B68_PBYTE_Msk (0x01UL << GPIO_PORT_B68_PBYTE_Pos) /*!< GPIO_PORT B68: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B69 ----------------------------------------- -#define GPIO_PORT_B69_PBYTE_Pos 0 /*!< GPIO_PORT B69: PBYTE Position */ -#define GPIO_PORT_B69_PBYTE_Msk (0x01UL << GPIO_PORT_B69_PBYTE_Pos) /*!< GPIO_PORT B69: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B70 ----------------------------------------- -#define GPIO_PORT_B70_PBYTE_Pos 0 /*!< GPIO_PORT B70: PBYTE Position */ -#define GPIO_PORT_B70_PBYTE_Msk (0x01UL << GPIO_PORT_B70_PBYTE_Pos) /*!< GPIO_PORT B70: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B71 ----------------------------------------- -#define GPIO_PORT_B71_PBYTE_Pos 0 /*!< GPIO_PORT B71: PBYTE Position */ -#define GPIO_PORT_B71_PBYTE_Msk (0x01UL << GPIO_PORT_B71_PBYTE_Pos) /*!< GPIO_PORT B71: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B72 ----------------------------------------- -#define GPIO_PORT_B72_PBYTE_Pos 0 /*!< GPIO_PORT B72: PBYTE Position */ -#define GPIO_PORT_B72_PBYTE_Msk (0x01UL << GPIO_PORT_B72_PBYTE_Pos) /*!< GPIO_PORT B72: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B73 ----------------------------------------- -#define GPIO_PORT_B73_PBYTE_Pos 0 /*!< GPIO_PORT B73: PBYTE Position */ -#define GPIO_PORT_B73_PBYTE_Msk (0x01UL << GPIO_PORT_B73_PBYTE_Pos) /*!< GPIO_PORT B73: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B74 ----------------------------------------- -#define GPIO_PORT_B74_PBYTE_Pos 0 /*!< GPIO_PORT B74: PBYTE Position */ -#define GPIO_PORT_B74_PBYTE_Msk (0x01UL << GPIO_PORT_B74_PBYTE_Pos) /*!< GPIO_PORT B74: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B75 ----------------------------------------- -#define GPIO_PORT_B75_PBYTE_Pos 0 /*!< GPIO_PORT B75: PBYTE Position */ -#define GPIO_PORT_B75_PBYTE_Msk (0x01UL << GPIO_PORT_B75_PBYTE_Pos) /*!< GPIO_PORT B75: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B76 ----------------------------------------- -#define GPIO_PORT_B76_PBYTE_Pos 0 /*!< GPIO_PORT B76: PBYTE Position */ -#define GPIO_PORT_B76_PBYTE_Msk (0x01UL << GPIO_PORT_B76_PBYTE_Pos) /*!< GPIO_PORT B76: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B77 ----------------------------------------- -#define GPIO_PORT_B77_PBYTE_Pos 0 /*!< GPIO_PORT B77: PBYTE Position */ -#define GPIO_PORT_B77_PBYTE_Msk (0x01UL << GPIO_PORT_B77_PBYTE_Pos) /*!< GPIO_PORT B77: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B78 ----------------------------------------- -#define GPIO_PORT_B78_PBYTE_Pos 0 /*!< GPIO_PORT B78: PBYTE Position */ -#define GPIO_PORT_B78_PBYTE_Msk (0x01UL << GPIO_PORT_B78_PBYTE_Pos) /*!< GPIO_PORT B78: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B79 ----------------------------------------- -#define GPIO_PORT_B79_PBYTE_Pos 0 /*!< GPIO_PORT B79: PBYTE Position */ -#define GPIO_PORT_B79_PBYTE_Msk (0x01UL << GPIO_PORT_B79_PBYTE_Pos) /*!< GPIO_PORT B79: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B80 ----------------------------------------- -#define GPIO_PORT_B80_PBYTE_Pos 0 /*!< GPIO_PORT B80: PBYTE Position */ -#define GPIO_PORT_B80_PBYTE_Msk (0x01UL << GPIO_PORT_B80_PBYTE_Pos) /*!< GPIO_PORT B80: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B81 ----------------------------------------- -#define GPIO_PORT_B81_PBYTE_Pos 0 /*!< GPIO_PORT B81: PBYTE Position */ -#define GPIO_PORT_B81_PBYTE_Msk (0x01UL << GPIO_PORT_B81_PBYTE_Pos) /*!< GPIO_PORT B81: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B82 ----------------------------------------- -#define GPIO_PORT_B82_PBYTE_Pos 0 /*!< GPIO_PORT B82: PBYTE Position */ -#define GPIO_PORT_B82_PBYTE_Msk (0x01UL << GPIO_PORT_B82_PBYTE_Pos) /*!< GPIO_PORT B82: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B83 ----------------------------------------- -#define GPIO_PORT_B83_PBYTE_Pos 0 /*!< GPIO_PORT B83: PBYTE Position */ -#define GPIO_PORT_B83_PBYTE_Msk (0x01UL << GPIO_PORT_B83_PBYTE_Pos) /*!< GPIO_PORT B83: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B84 ----------------------------------------- -#define GPIO_PORT_B84_PBYTE_Pos 0 /*!< GPIO_PORT B84: PBYTE Position */ -#define GPIO_PORT_B84_PBYTE_Msk (0x01UL << GPIO_PORT_B84_PBYTE_Pos) /*!< GPIO_PORT B84: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B85 ----------------------------------------- -#define GPIO_PORT_B85_PBYTE_Pos 0 /*!< GPIO_PORT B85: PBYTE Position */ -#define GPIO_PORT_B85_PBYTE_Msk (0x01UL << GPIO_PORT_B85_PBYTE_Pos) /*!< GPIO_PORT B85: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B86 ----------------------------------------- -#define GPIO_PORT_B86_PBYTE_Pos 0 /*!< GPIO_PORT B86: PBYTE Position */ -#define GPIO_PORT_B86_PBYTE_Msk (0x01UL << GPIO_PORT_B86_PBYTE_Pos) /*!< GPIO_PORT B86: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B87 ----------------------------------------- -#define GPIO_PORT_B87_PBYTE_Pos 0 /*!< GPIO_PORT B87: PBYTE Position */ -#define GPIO_PORT_B87_PBYTE_Msk (0x01UL << GPIO_PORT_B87_PBYTE_Pos) /*!< GPIO_PORT B87: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B88 ----------------------------------------- -#define GPIO_PORT_B88_PBYTE_Pos 0 /*!< GPIO_PORT B88: PBYTE Position */ -#define GPIO_PORT_B88_PBYTE_Msk (0x01UL << GPIO_PORT_B88_PBYTE_Pos) /*!< GPIO_PORT B88: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B89 ----------------------------------------- -#define GPIO_PORT_B89_PBYTE_Pos 0 /*!< GPIO_PORT B89: PBYTE Position */ -#define GPIO_PORT_B89_PBYTE_Msk (0x01UL << GPIO_PORT_B89_PBYTE_Pos) /*!< GPIO_PORT B89: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B90 ----------------------------------------- -#define GPIO_PORT_B90_PBYTE_Pos 0 /*!< GPIO_PORT B90: PBYTE Position */ -#define GPIO_PORT_B90_PBYTE_Msk (0x01UL << GPIO_PORT_B90_PBYTE_Pos) /*!< GPIO_PORT B90: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B91 ----------------------------------------- -#define GPIO_PORT_B91_PBYTE_Pos 0 /*!< GPIO_PORT B91: PBYTE Position */ -#define GPIO_PORT_B91_PBYTE_Msk (0x01UL << GPIO_PORT_B91_PBYTE_Pos) /*!< GPIO_PORT B91: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B92 ----------------------------------------- -#define GPIO_PORT_B92_PBYTE_Pos 0 /*!< GPIO_PORT B92: PBYTE Position */ -#define GPIO_PORT_B92_PBYTE_Msk (0x01UL << GPIO_PORT_B92_PBYTE_Pos) /*!< GPIO_PORT B92: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B93 ----------------------------------------- -#define GPIO_PORT_B93_PBYTE_Pos 0 /*!< GPIO_PORT B93: PBYTE Position */ -#define GPIO_PORT_B93_PBYTE_Msk (0x01UL << GPIO_PORT_B93_PBYTE_Pos) /*!< GPIO_PORT B93: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B94 ----------------------------------------- -#define GPIO_PORT_B94_PBYTE_Pos 0 /*!< GPIO_PORT B94: PBYTE Position */ -#define GPIO_PORT_B94_PBYTE_Msk (0x01UL << GPIO_PORT_B94_PBYTE_Pos) /*!< GPIO_PORT B94: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B95 ----------------------------------------- -#define GPIO_PORT_B95_PBYTE_Pos 0 /*!< GPIO_PORT B95: PBYTE Position */ -#define GPIO_PORT_B95_PBYTE_Msk (0x01UL << GPIO_PORT_B95_PBYTE_Pos) /*!< GPIO_PORT B95: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B96 ----------------------------------------- -#define GPIO_PORT_B96_PBYTE_Pos 0 /*!< GPIO_PORT B96: PBYTE Position */ -#define GPIO_PORT_B96_PBYTE_Msk (0x01UL << GPIO_PORT_B96_PBYTE_Pos) /*!< GPIO_PORT B96: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B97 ----------------------------------------- -#define GPIO_PORT_B97_PBYTE_Pos 0 /*!< GPIO_PORT B97: PBYTE Position */ -#define GPIO_PORT_B97_PBYTE_Msk (0x01UL << GPIO_PORT_B97_PBYTE_Pos) /*!< GPIO_PORT B97: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B98 ----------------------------------------- -#define GPIO_PORT_B98_PBYTE_Pos 0 /*!< GPIO_PORT B98: PBYTE Position */ -#define GPIO_PORT_B98_PBYTE_Msk (0x01UL << GPIO_PORT_B98_PBYTE_Pos) /*!< GPIO_PORT B98: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B99 ----------------------------------------- -#define GPIO_PORT_B99_PBYTE_Pos 0 /*!< GPIO_PORT B99: PBYTE Position */ -#define GPIO_PORT_B99_PBYTE_Msk (0x01UL << GPIO_PORT_B99_PBYTE_Pos) /*!< GPIO_PORT B99: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B100 ----------------------------------------- -#define GPIO_PORT_B100_PBYTE_Pos 0 /*!< GPIO_PORT B100: PBYTE Position */ -#define GPIO_PORT_B100_PBYTE_Msk (0x01UL << GPIO_PORT_B100_PBYTE_Pos) /*!< GPIO_PORT B100: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B101 ----------------------------------------- -#define GPIO_PORT_B101_PBYTE_Pos 0 /*!< GPIO_PORT B101: PBYTE Position */ -#define GPIO_PORT_B101_PBYTE_Msk (0x01UL << GPIO_PORT_B101_PBYTE_Pos) /*!< GPIO_PORT B101: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B102 ----------------------------------------- -#define GPIO_PORT_B102_PBYTE_Pos 0 /*!< GPIO_PORT B102: PBYTE Position */ -#define GPIO_PORT_B102_PBYTE_Msk (0x01UL << GPIO_PORT_B102_PBYTE_Pos) /*!< GPIO_PORT B102: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B103 ----------------------------------------- -#define GPIO_PORT_B103_PBYTE_Pos 0 /*!< GPIO_PORT B103: PBYTE Position */ -#define GPIO_PORT_B103_PBYTE_Msk (0x01UL << GPIO_PORT_B103_PBYTE_Pos) /*!< GPIO_PORT B103: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B104 ----------------------------------------- -#define GPIO_PORT_B104_PBYTE_Pos 0 /*!< GPIO_PORT B104: PBYTE Position */ -#define GPIO_PORT_B104_PBYTE_Msk (0x01UL << GPIO_PORT_B104_PBYTE_Pos) /*!< GPIO_PORT B104: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B105 ----------------------------------------- -#define GPIO_PORT_B105_PBYTE_Pos 0 /*!< GPIO_PORT B105: PBYTE Position */ -#define GPIO_PORT_B105_PBYTE_Msk (0x01UL << GPIO_PORT_B105_PBYTE_Pos) /*!< GPIO_PORT B105: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B106 ----------------------------------------- -#define GPIO_PORT_B106_PBYTE_Pos 0 /*!< GPIO_PORT B106: PBYTE Position */ -#define GPIO_PORT_B106_PBYTE_Msk (0x01UL << GPIO_PORT_B106_PBYTE_Pos) /*!< GPIO_PORT B106: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B107 ----------------------------------------- -#define GPIO_PORT_B107_PBYTE_Pos 0 /*!< GPIO_PORT B107: PBYTE Position */ -#define GPIO_PORT_B107_PBYTE_Msk (0x01UL << GPIO_PORT_B107_PBYTE_Pos) /*!< GPIO_PORT B107: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B108 ----------------------------------------- -#define GPIO_PORT_B108_PBYTE_Pos 0 /*!< GPIO_PORT B108: PBYTE Position */ -#define GPIO_PORT_B108_PBYTE_Msk (0x01UL << GPIO_PORT_B108_PBYTE_Pos) /*!< GPIO_PORT B108: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B109 ----------------------------------------- -#define GPIO_PORT_B109_PBYTE_Pos 0 /*!< GPIO_PORT B109: PBYTE Position */ -#define GPIO_PORT_B109_PBYTE_Msk (0x01UL << GPIO_PORT_B109_PBYTE_Pos) /*!< GPIO_PORT B109: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B110 ----------------------------------------- -#define GPIO_PORT_B110_PBYTE_Pos 0 /*!< GPIO_PORT B110: PBYTE Position */ -#define GPIO_PORT_B110_PBYTE_Msk (0x01UL << GPIO_PORT_B110_PBYTE_Pos) /*!< GPIO_PORT B110: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B111 ----------------------------------------- -#define GPIO_PORT_B111_PBYTE_Pos 0 /*!< GPIO_PORT B111: PBYTE Position */ -#define GPIO_PORT_B111_PBYTE_Msk (0x01UL << GPIO_PORT_B111_PBYTE_Pos) /*!< GPIO_PORT B111: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B112 ----------------------------------------- -#define GPIO_PORT_B112_PBYTE_Pos 0 /*!< GPIO_PORT B112: PBYTE Position */ -#define GPIO_PORT_B112_PBYTE_Msk (0x01UL << GPIO_PORT_B112_PBYTE_Pos) /*!< GPIO_PORT B112: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B113 ----------------------------------------- -#define GPIO_PORT_B113_PBYTE_Pos 0 /*!< GPIO_PORT B113: PBYTE Position */ -#define GPIO_PORT_B113_PBYTE_Msk (0x01UL << GPIO_PORT_B113_PBYTE_Pos) /*!< GPIO_PORT B113: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B114 ----------------------------------------- -#define GPIO_PORT_B114_PBYTE_Pos 0 /*!< GPIO_PORT B114: PBYTE Position */ -#define GPIO_PORT_B114_PBYTE_Msk (0x01UL << GPIO_PORT_B114_PBYTE_Pos) /*!< GPIO_PORT B114: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B115 ----------------------------------------- -#define GPIO_PORT_B115_PBYTE_Pos 0 /*!< GPIO_PORT B115: PBYTE Position */ -#define GPIO_PORT_B115_PBYTE_Msk (0x01UL << GPIO_PORT_B115_PBYTE_Pos) /*!< GPIO_PORT B115: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B116 ----------------------------------------- -#define GPIO_PORT_B116_PBYTE_Pos 0 /*!< GPIO_PORT B116: PBYTE Position */ -#define GPIO_PORT_B116_PBYTE_Msk (0x01UL << GPIO_PORT_B116_PBYTE_Pos) /*!< GPIO_PORT B116: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B117 ----------------------------------------- -#define GPIO_PORT_B117_PBYTE_Pos 0 /*!< GPIO_PORT B117: PBYTE Position */ -#define GPIO_PORT_B117_PBYTE_Msk (0x01UL << GPIO_PORT_B117_PBYTE_Pos) /*!< GPIO_PORT B117: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B118 ----------------------------------------- -#define GPIO_PORT_B118_PBYTE_Pos 0 /*!< GPIO_PORT B118: PBYTE Position */ -#define GPIO_PORT_B118_PBYTE_Msk (0x01UL << GPIO_PORT_B118_PBYTE_Pos) /*!< GPIO_PORT B118: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B119 ----------------------------------------- -#define GPIO_PORT_B119_PBYTE_Pos 0 /*!< GPIO_PORT B119: PBYTE Position */ -#define GPIO_PORT_B119_PBYTE_Msk (0x01UL << GPIO_PORT_B119_PBYTE_Pos) /*!< GPIO_PORT B119: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B120 ----------------------------------------- -#define GPIO_PORT_B120_PBYTE_Pos 0 /*!< GPIO_PORT B120: PBYTE Position */ -#define GPIO_PORT_B120_PBYTE_Msk (0x01UL << GPIO_PORT_B120_PBYTE_Pos) /*!< GPIO_PORT B120: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B121 ----------------------------------------- -#define GPIO_PORT_B121_PBYTE_Pos 0 /*!< GPIO_PORT B121: PBYTE Position */ -#define GPIO_PORT_B121_PBYTE_Msk (0x01UL << GPIO_PORT_B121_PBYTE_Pos) /*!< GPIO_PORT B121: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B122 ----------------------------------------- -#define GPIO_PORT_B122_PBYTE_Pos 0 /*!< GPIO_PORT B122: PBYTE Position */ -#define GPIO_PORT_B122_PBYTE_Msk (0x01UL << GPIO_PORT_B122_PBYTE_Pos) /*!< GPIO_PORT B122: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B123 ----------------------------------------- -#define GPIO_PORT_B123_PBYTE_Pos 0 /*!< GPIO_PORT B123: PBYTE Position */ -#define GPIO_PORT_B123_PBYTE_Msk (0x01UL << GPIO_PORT_B123_PBYTE_Pos) /*!< GPIO_PORT B123: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B124 ----------------------------------------- -#define GPIO_PORT_B124_PBYTE_Pos 0 /*!< GPIO_PORT B124: PBYTE Position */ -#define GPIO_PORT_B124_PBYTE_Msk (0x01UL << GPIO_PORT_B124_PBYTE_Pos) /*!< GPIO_PORT B124: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B125 ----------------------------------------- -#define GPIO_PORT_B125_PBYTE_Pos 0 /*!< GPIO_PORT B125: PBYTE Position */ -#define GPIO_PORT_B125_PBYTE_Msk (0x01UL << GPIO_PORT_B125_PBYTE_Pos) /*!< GPIO_PORT B125: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B126 ----------------------------------------- -#define GPIO_PORT_B126_PBYTE_Pos 0 /*!< GPIO_PORT B126: PBYTE Position */ -#define GPIO_PORT_B126_PBYTE_Msk (0x01UL << GPIO_PORT_B126_PBYTE_Pos) /*!< GPIO_PORT B126: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B127 ----------------------------------------- -#define GPIO_PORT_B127_PBYTE_Pos 0 /*!< GPIO_PORT B127: PBYTE Position */ -#define GPIO_PORT_B127_PBYTE_Msk (0x01UL << GPIO_PORT_B127_PBYTE_Pos) /*!< GPIO_PORT B127: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B128 ----------------------------------------- -#define GPIO_PORT_B128_PBYTE_Pos 0 /*!< GPIO_PORT B128: PBYTE Position */ -#define GPIO_PORT_B128_PBYTE_Msk (0x01UL << GPIO_PORT_B128_PBYTE_Pos) /*!< GPIO_PORT B128: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B129 ----------------------------------------- -#define GPIO_PORT_B129_PBYTE_Pos 0 /*!< GPIO_PORT B129: PBYTE Position */ -#define GPIO_PORT_B129_PBYTE_Msk (0x01UL << GPIO_PORT_B129_PBYTE_Pos) /*!< GPIO_PORT B129: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B130 ----------------------------------------- -#define GPIO_PORT_B130_PBYTE_Pos 0 /*!< GPIO_PORT B130: PBYTE Position */ -#define GPIO_PORT_B130_PBYTE_Msk (0x01UL << GPIO_PORT_B130_PBYTE_Pos) /*!< GPIO_PORT B130: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B131 ----------------------------------------- -#define GPIO_PORT_B131_PBYTE_Pos 0 /*!< GPIO_PORT B131: PBYTE Position */ -#define GPIO_PORT_B131_PBYTE_Msk (0x01UL << GPIO_PORT_B131_PBYTE_Pos) /*!< GPIO_PORT B131: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B132 ----------------------------------------- -#define GPIO_PORT_B132_PBYTE_Pos 0 /*!< GPIO_PORT B132: PBYTE Position */ -#define GPIO_PORT_B132_PBYTE_Msk (0x01UL << GPIO_PORT_B132_PBYTE_Pos) /*!< GPIO_PORT B132: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B133 ----------------------------------------- -#define GPIO_PORT_B133_PBYTE_Pos 0 /*!< GPIO_PORT B133: PBYTE Position */ -#define GPIO_PORT_B133_PBYTE_Msk (0x01UL << GPIO_PORT_B133_PBYTE_Pos) /*!< GPIO_PORT B133: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B134 ----------------------------------------- -#define GPIO_PORT_B134_PBYTE_Pos 0 /*!< GPIO_PORT B134: PBYTE Position */ -#define GPIO_PORT_B134_PBYTE_Msk (0x01UL << GPIO_PORT_B134_PBYTE_Pos) /*!< GPIO_PORT B134: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B135 ----------------------------------------- -#define GPIO_PORT_B135_PBYTE_Pos 0 /*!< GPIO_PORT B135: PBYTE Position */ -#define GPIO_PORT_B135_PBYTE_Msk (0x01UL << GPIO_PORT_B135_PBYTE_Pos) /*!< GPIO_PORT B135: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B136 ----------------------------------------- -#define GPIO_PORT_B136_PBYTE_Pos 0 /*!< GPIO_PORT B136: PBYTE Position */ -#define GPIO_PORT_B136_PBYTE_Msk (0x01UL << GPIO_PORT_B136_PBYTE_Pos) /*!< GPIO_PORT B136: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B137 ----------------------------------------- -#define GPIO_PORT_B137_PBYTE_Pos 0 /*!< GPIO_PORT B137: PBYTE Position */ -#define GPIO_PORT_B137_PBYTE_Msk (0x01UL << GPIO_PORT_B137_PBYTE_Pos) /*!< GPIO_PORT B137: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B138 ----------------------------------------- -#define GPIO_PORT_B138_PBYTE_Pos 0 /*!< GPIO_PORT B138: PBYTE Position */ -#define GPIO_PORT_B138_PBYTE_Msk (0x01UL << GPIO_PORT_B138_PBYTE_Pos) /*!< GPIO_PORT B138: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B139 ----------------------------------------- -#define GPIO_PORT_B139_PBYTE_Pos 0 /*!< GPIO_PORT B139: PBYTE Position */ -#define GPIO_PORT_B139_PBYTE_Msk (0x01UL << GPIO_PORT_B139_PBYTE_Pos) /*!< GPIO_PORT B139: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B140 ----------------------------------------- -#define GPIO_PORT_B140_PBYTE_Pos 0 /*!< GPIO_PORT B140: PBYTE Position */ -#define GPIO_PORT_B140_PBYTE_Msk (0x01UL << GPIO_PORT_B140_PBYTE_Pos) /*!< GPIO_PORT B140: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B141 ----------------------------------------- -#define GPIO_PORT_B141_PBYTE_Pos 0 /*!< GPIO_PORT B141: PBYTE Position */ -#define GPIO_PORT_B141_PBYTE_Msk (0x01UL << GPIO_PORT_B141_PBYTE_Pos) /*!< GPIO_PORT B141: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B142 ----------------------------------------- -#define GPIO_PORT_B142_PBYTE_Pos 0 /*!< GPIO_PORT B142: PBYTE Position */ -#define GPIO_PORT_B142_PBYTE_Msk (0x01UL << GPIO_PORT_B142_PBYTE_Pos) /*!< GPIO_PORT B142: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B143 ----------------------------------------- -#define GPIO_PORT_B143_PBYTE_Pos 0 /*!< GPIO_PORT B143: PBYTE Position */ -#define GPIO_PORT_B143_PBYTE_Msk (0x01UL << GPIO_PORT_B143_PBYTE_Pos) /*!< GPIO_PORT B143: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B144 ----------------------------------------- -#define GPIO_PORT_B144_PBYTE_Pos 0 /*!< GPIO_PORT B144: PBYTE Position */ -#define GPIO_PORT_B144_PBYTE_Msk (0x01UL << GPIO_PORT_B144_PBYTE_Pos) /*!< GPIO_PORT B144: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B145 ----------------------------------------- -#define GPIO_PORT_B145_PBYTE_Pos 0 /*!< GPIO_PORT B145: PBYTE Position */ -#define GPIO_PORT_B145_PBYTE_Msk (0x01UL << GPIO_PORT_B145_PBYTE_Pos) /*!< GPIO_PORT B145: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B146 ----------------------------------------- -#define GPIO_PORT_B146_PBYTE_Pos 0 /*!< GPIO_PORT B146: PBYTE Position */ -#define GPIO_PORT_B146_PBYTE_Msk (0x01UL << GPIO_PORT_B146_PBYTE_Pos) /*!< GPIO_PORT B146: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B147 ----------------------------------------- -#define GPIO_PORT_B147_PBYTE_Pos 0 /*!< GPIO_PORT B147: PBYTE Position */ -#define GPIO_PORT_B147_PBYTE_Msk (0x01UL << GPIO_PORT_B147_PBYTE_Pos) /*!< GPIO_PORT B147: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B148 ----------------------------------------- -#define GPIO_PORT_B148_PBYTE_Pos 0 /*!< GPIO_PORT B148: PBYTE Position */ -#define GPIO_PORT_B148_PBYTE_Msk (0x01UL << GPIO_PORT_B148_PBYTE_Pos) /*!< GPIO_PORT B148: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B149 ----------------------------------------- -#define GPIO_PORT_B149_PBYTE_Pos 0 /*!< GPIO_PORT B149: PBYTE Position */ -#define GPIO_PORT_B149_PBYTE_Msk (0x01UL << GPIO_PORT_B149_PBYTE_Pos) /*!< GPIO_PORT B149: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B150 ----------------------------------------- -#define GPIO_PORT_B150_PBYTE_Pos 0 /*!< GPIO_PORT B150: PBYTE Position */ -#define GPIO_PORT_B150_PBYTE_Msk (0x01UL << GPIO_PORT_B150_PBYTE_Pos) /*!< GPIO_PORT B150: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B151 ----------------------------------------- -#define GPIO_PORT_B151_PBYTE_Pos 0 /*!< GPIO_PORT B151: PBYTE Position */ -#define GPIO_PORT_B151_PBYTE_Msk (0x01UL << GPIO_PORT_B151_PBYTE_Pos) /*!< GPIO_PORT B151: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B152 ----------------------------------------- -#define GPIO_PORT_B152_PBYTE_Pos 0 /*!< GPIO_PORT B152: PBYTE Position */ -#define GPIO_PORT_B152_PBYTE_Msk (0x01UL << GPIO_PORT_B152_PBYTE_Pos) /*!< GPIO_PORT B152: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B153 ----------------------------------------- -#define GPIO_PORT_B153_PBYTE_Pos 0 /*!< GPIO_PORT B153: PBYTE Position */ -#define GPIO_PORT_B153_PBYTE_Msk (0x01UL << GPIO_PORT_B153_PBYTE_Pos) /*!< GPIO_PORT B153: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B154 ----------------------------------------- -#define GPIO_PORT_B154_PBYTE_Pos 0 /*!< GPIO_PORT B154: PBYTE Position */ -#define GPIO_PORT_B154_PBYTE_Msk (0x01UL << GPIO_PORT_B154_PBYTE_Pos) /*!< GPIO_PORT B154: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B155 ----------------------------------------- -#define GPIO_PORT_B155_PBYTE_Pos 0 /*!< GPIO_PORT B155: PBYTE Position */ -#define GPIO_PORT_B155_PBYTE_Msk (0x01UL << GPIO_PORT_B155_PBYTE_Pos) /*!< GPIO_PORT B155: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B156 ----------------------------------------- -#define GPIO_PORT_B156_PBYTE_Pos 0 /*!< GPIO_PORT B156: PBYTE Position */ -#define GPIO_PORT_B156_PBYTE_Msk (0x01UL << GPIO_PORT_B156_PBYTE_Pos) /*!< GPIO_PORT B156: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B157 ----------------------------------------- -#define GPIO_PORT_B157_PBYTE_Pos 0 /*!< GPIO_PORT B157: PBYTE Position */ -#define GPIO_PORT_B157_PBYTE_Msk (0x01UL << GPIO_PORT_B157_PBYTE_Pos) /*!< GPIO_PORT B157: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B158 ----------------------------------------- -#define GPIO_PORT_B158_PBYTE_Pos 0 /*!< GPIO_PORT B158: PBYTE Position */ -#define GPIO_PORT_B158_PBYTE_Msk (0x01UL << GPIO_PORT_B158_PBYTE_Pos) /*!< GPIO_PORT B158: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B159 ----------------------------------------- -#define GPIO_PORT_B159_PBYTE_Pos 0 /*!< GPIO_PORT B159: PBYTE Position */ -#define GPIO_PORT_B159_PBYTE_Msk (0x01UL << GPIO_PORT_B159_PBYTE_Pos) /*!< GPIO_PORT B159: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B160 ----------------------------------------- -#define GPIO_PORT_B160_PBYTE_Pos 0 /*!< GPIO_PORT B160: PBYTE Position */ -#define GPIO_PORT_B160_PBYTE_Msk (0x01UL << GPIO_PORT_B160_PBYTE_Pos) /*!< GPIO_PORT B160: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B161 ----------------------------------------- -#define GPIO_PORT_B161_PBYTE_Pos 0 /*!< GPIO_PORT B161: PBYTE Position */ -#define GPIO_PORT_B161_PBYTE_Msk (0x01UL << GPIO_PORT_B161_PBYTE_Pos) /*!< GPIO_PORT B161: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B162 ----------------------------------------- -#define GPIO_PORT_B162_PBYTE_Pos 0 /*!< GPIO_PORT B162: PBYTE Position */ -#define GPIO_PORT_B162_PBYTE_Msk (0x01UL << GPIO_PORT_B162_PBYTE_Pos) /*!< GPIO_PORT B162: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B163 ----------------------------------------- -#define GPIO_PORT_B163_PBYTE_Pos 0 /*!< GPIO_PORT B163: PBYTE Position */ -#define GPIO_PORT_B163_PBYTE_Msk (0x01UL << GPIO_PORT_B163_PBYTE_Pos) /*!< GPIO_PORT B163: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B164 ----------------------------------------- -#define GPIO_PORT_B164_PBYTE_Pos 0 /*!< GPIO_PORT B164: PBYTE Position */ -#define GPIO_PORT_B164_PBYTE_Msk (0x01UL << GPIO_PORT_B164_PBYTE_Pos) /*!< GPIO_PORT B164: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B165 ----------------------------------------- -#define GPIO_PORT_B165_PBYTE_Pos 0 /*!< GPIO_PORT B165: PBYTE Position */ -#define GPIO_PORT_B165_PBYTE_Msk (0x01UL << GPIO_PORT_B165_PBYTE_Pos) /*!< GPIO_PORT B165: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B166 ----------------------------------------- -#define GPIO_PORT_B166_PBYTE_Pos 0 /*!< GPIO_PORT B166: PBYTE Position */ -#define GPIO_PORT_B166_PBYTE_Msk (0x01UL << GPIO_PORT_B166_PBYTE_Pos) /*!< GPIO_PORT B166: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B167 ----------------------------------------- -#define GPIO_PORT_B167_PBYTE_Pos 0 /*!< GPIO_PORT B167: PBYTE Position */ -#define GPIO_PORT_B167_PBYTE_Msk (0x01UL << GPIO_PORT_B167_PBYTE_Pos) /*!< GPIO_PORT B167: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B168 ----------------------------------------- -#define GPIO_PORT_B168_PBYTE_Pos 0 /*!< GPIO_PORT B168: PBYTE Position */ -#define GPIO_PORT_B168_PBYTE_Msk (0x01UL << GPIO_PORT_B168_PBYTE_Pos) /*!< GPIO_PORT B168: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B169 ----------------------------------------- -#define GPIO_PORT_B169_PBYTE_Pos 0 /*!< GPIO_PORT B169: PBYTE Position */ -#define GPIO_PORT_B169_PBYTE_Msk (0x01UL << GPIO_PORT_B169_PBYTE_Pos) /*!< GPIO_PORT B169: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B170 ----------------------------------------- -#define GPIO_PORT_B170_PBYTE_Pos 0 /*!< GPIO_PORT B170: PBYTE Position */ -#define GPIO_PORT_B170_PBYTE_Msk (0x01UL << GPIO_PORT_B170_PBYTE_Pos) /*!< GPIO_PORT B170: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B171 ----------------------------------------- -#define GPIO_PORT_B171_PBYTE_Pos 0 /*!< GPIO_PORT B171: PBYTE Position */ -#define GPIO_PORT_B171_PBYTE_Msk (0x01UL << GPIO_PORT_B171_PBYTE_Pos) /*!< GPIO_PORT B171: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B172 ----------------------------------------- -#define GPIO_PORT_B172_PBYTE_Pos 0 /*!< GPIO_PORT B172: PBYTE Position */ -#define GPIO_PORT_B172_PBYTE_Msk (0x01UL << GPIO_PORT_B172_PBYTE_Pos) /*!< GPIO_PORT B172: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B173 ----------------------------------------- -#define GPIO_PORT_B173_PBYTE_Pos 0 /*!< GPIO_PORT B173: PBYTE Position */ -#define GPIO_PORT_B173_PBYTE_Msk (0x01UL << GPIO_PORT_B173_PBYTE_Pos) /*!< GPIO_PORT B173: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B174 ----------------------------------------- -#define GPIO_PORT_B174_PBYTE_Pos 0 /*!< GPIO_PORT B174: PBYTE Position */ -#define GPIO_PORT_B174_PBYTE_Msk (0x01UL << GPIO_PORT_B174_PBYTE_Pos) /*!< GPIO_PORT B174: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B175 ----------------------------------------- -#define GPIO_PORT_B175_PBYTE_Pos 0 /*!< GPIO_PORT B175: PBYTE Position */ -#define GPIO_PORT_B175_PBYTE_Msk (0x01UL << GPIO_PORT_B175_PBYTE_Pos) /*!< GPIO_PORT B175: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B176 ----------------------------------------- -#define GPIO_PORT_B176_PBYTE_Pos 0 /*!< GPIO_PORT B176: PBYTE Position */ -#define GPIO_PORT_B176_PBYTE_Msk (0x01UL << GPIO_PORT_B176_PBYTE_Pos) /*!< GPIO_PORT B176: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B177 ----------------------------------------- -#define GPIO_PORT_B177_PBYTE_Pos 0 /*!< GPIO_PORT B177: PBYTE Position */ -#define GPIO_PORT_B177_PBYTE_Msk (0x01UL << GPIO_PORT_B177_PBYTE_Pos) /*!< GPIO_PORT B177: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B178 ----------------------------------------- -#define GPIO_PORT_B178_PBYTE_Pos 0 /*!< GPIO_PORT B178: PBYTE Position */ -#define GPIO_PORT_B178_PBYTE_Msk (0x01UL << GPIO_PORT_B178_PBYTE_Pos) /*!< GPIO_PORT B178: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B179 ----------------------------------------- -#define GPIO_PORT_B179_PBYTE_Pos 0 /*!< GPIO_PORT B179: PBYTE Position */ -#define GPIO_PORT_B179_PBYTE_Msk (0x01UL << GPIO_PORT_B179_PBYTE_Pos) /*!< GPIO_PORT B179: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B180 ----------------------------------------- -#define GPIO_PORT_B180_PBYTE_Pos 0 /*!< GPIO_PORT B180: PBYTE Position */ -#define GPIO_PORT_B180_PBYTE_Msk (0x01UL << GPIO_PORT_B180_PBYTE_Pos) /*!< GPIO_PORT B180: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B181 ----------------------------------------- -#define GPIO_PORT_B181_PBYTE_Pos 0 /*!< GPIO_PORT B181: PBYTE Position */ -#define GPIO_PORT_B181_PBYTE_Msk (0x01UL << GPIO_PORT_B181_PBYTE_Pos) /*!< GPIO_PORT B181: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B182 ----------------------------------------- -#define GPIO_PORT_B182_PBYTE_Pos 0 /*!< GPIO_PORT B182: PBYTE Position */ -#define GPIO_PORT_B182_PBYTE_Msk (0x01UL << GPIO_PORT_B182_PBYTE_Pos) /*!< GPIO_PORT B182: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B183 ----------------------------------------- -#define GPIO_PORT_B183_PBYTE_Pos 0 /*!< GPIO_PORT B183: PBYTE Position */ -#define GPIO_PORT_B183_PBYTE_Msk (0x01UL << GPIO_PORT_B183_PBYTE_Pos) /*!< GPIO_PORT B183: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B184 ----------------------------------------- -#define GPIO_PORT_B184_PBYTE_Pos 0 /*!< GPIO_PORT B184: PBYTE Position */ -#define GPIO_PORT_B184_PBYTE_Msk (0x01UL << GPIO_PORT_B184_PBYTE_Pos) /*!< GPIO_PORT B184: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B185 ----------------------------------------- -#define GPIO_PORT_B185_PBYTE_Pos 0 /*!< GPIO_PORT B185: PBYTE Position */ -#define GPIO_PORT_B185_PBYTE_Msk (0x01UL << GPIO_PORT_B185_PBYTE_Pos) /*!< GPIO_PORT B185: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B186 ----------------------------------------- -#define GPIO_PORT_B186_PBYTE_Pos 0 /*!< GPIO_PORT B186: PBYTE Position */ -#define GPIO_PORT_B186_PBYTE_Msk (0x01UL << GPIO_PORT_B186_PBYTE_Pos) /*!< GPIO_PORT B186: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B187 ----------------------------------------- -#define GPIO_PORT_B187_PBYTE_Pos 0 /*!< GPIO_PORT B187: PBYTE Position */ -#define GPIO_PORT_B187_PBYTE_Msk (0x01UL << GPIO_PORT_B187_PBYTE_Pos) /*!< GPIO_PORT B187: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B188 ----------------------------------------- -#define GPIO_PORT_B188_PBYTE_Pos 0 /*!< GPIO_PORT B188: PBYTE Position */ -#define GPIO_PORT_B188_PBYTE_Msk (0x01UL << GPIO_PORT_B188_PBYTE_Pos) /*!< GPIO_PORT B188: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B189 ----------------------------------------- -#define GPIO_PORT_B189_PBYTE_Pos 0 /*!< GPIO_PORT B189: PBYTE Position */ -#define GPIO_PORT_B189_PBYTE_Msk (0x01UL << GPIO_PORT_B189_PBYTE_Pos) /*!< GPIO_PORT B189: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B190 ----------------------------------------- -#define GPIO_PORT_B190_PBYTE_Pos 0 /*!< GPIO_PORT B190: PBYTE Position */ -#define GPIO_PORT_B190_PBYTE_Msk (0x01UL << GPIO_PORT_B190_PBYTE_Pos) /*!< GPIO_PORT B190: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B191 ----------------------------------------- -#define GPIO_PORT_B191_PBYTE_Pos 0 /*!< GPIO_PORT B191: PBYTE Position */ -#define GPIO_PORT_B191_PBYTE_Msk (0x01UL << GPIO_PORT_B191_PBYTE_Pos) /*!< GPIO_PORT B191: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B192 ----------------------------------------- -#define GPIO_PORT_B192_PBYTE_Pos 0 /*!< GPIO_PORT B192: PBYTE Position */ -#define GPIO_PORT_B192_PBYTE_Msk (0x01UL << GPIO_PORT_B192_PBYTE_Pos) /*!< GPIO_PORT B192: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B193 ----------------------------------------- -#define GPIO_PORT_B193_PBYTE_Pos 0 /*!< GPIO_PORT B193: PBYTE Position */ -#define GPIO_PORT_B193_PBYTE_Msk (0x01UL << GPIO_PORT_B193_PBYTE_Pos) /*!< GPIO_PORT B193: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B194 ----------------------------------------- -#define GPIO_PORT_B194_PBYTE_Pos 0 /*!< GPIO_PORT B194: PBYTE Position */ -#define GPIO_PORT_B194_PBYTE_Msk (0x01UL << GPIO_PORT_B194_PBYTE_Pos) /*!< GPIO_PORT B194: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B195 ----------------------------------------- -#define GPIO_PORT_B195_PBYTE_Pos 0 /*!< GPIO_PORT B195: PBYTE Position */ -#define GPIO_PORT_B195_PBYTE_Msk (0x01UL << GPIO_PORT_B195_PBYTE_Pos) /*!< GPIO_PORT B195: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B196 ----------------------------------------- -#define GPIO_PORT_B196_PBYTE_Pos 0 /*!< GPIO_PORT B196: PBYTE Position */ -#define GPIO_PORT_B196_PBYTE_Msk (0x01UL << GPIO_PORT_B196_PBYTE_Pos) /*!< GPIO_PORT B196: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B197 ----------------------------------------- -#define GPIO_PORT_B197_PBYTE_Pos 0 /*!< GPIO_PORT B197: PBYTE Position */ -#define GPIO_PORT_B197_PBYTE_Msk (0x01UL << GPIO_PORT_B197_PBYTE_Pos) /*!< GPIO_PORT B197: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B198 ----------------------------------------- -#define GPIO_PORT_B198_PBYTE_Pos 0 /*!< GPIO_PORT B198: PBYTE Position */ -#define GPIO_PORT_B198_PBYTE_Msk (0x01UL << GPIO_PORT_B198_PBYTE_Pos) /*!< GPIO_PORT B198: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B199 ----------------------------------------- -#define GPIO_PORT_B199_PBYTE_Pos 0 /*!< GPIO_PORT B199: PBYTE Position */ -#define GPIO_PORT_B199_PBYTE_Msk (0x01UL << GPIO_PORT_B199_PBYTE_Pos) /*!< GPIO_PORT B199: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B200 ----------------------------------------- -#define GPIO_PORT_B200_PBYTE_Pos 0 /*!< GPIO_PORT B200: PBYTE Position */ -#define GPIO_PORT_B200_PBYTE_Msk (0x01UL << GPIO_PORT_B200_PBYTE_Pos) /*!< GPIO_PORT B200: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B201 ----------------------------------------- -#define GPIO_PORT_B201_PBYTE_Pos 0 /*!< GPIO_PORT B201: PBYTE Position */ -#define GPIO_PORT_B201_PBYTE_Msk (0x01UL << GPIO_PORT_B201_PBYTE_Pos) /*!< GPIO_PORT B201: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B202 ----------------------------------------- -#define GPIO_PORT_B202_PBYTE_Pos 0 /*!< GPIO_PORT B202: PBYTE Position */ -#define GPIO_PORT_B202_PBYTE_Msk (0x01UL << GPIO_PORT_B202_PBYTE_Pos) /*!< GPIO_PORT B202: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B203 ----------------------------------------- -#define GPIO_PORT_B203_PBYTE_Pos 0 /*!< GPIO_PORT B203: PBYTE Position */ -#define GPIO_PORT_B203_PBYTE_Msk (0x01UL << GPIO_PORT_B203_PBYTE_Pos) /*!< GPIO_PORT B203: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B204 ----------------------------------------- -#define GPIO_PORT_B204_PBYTE_Pos 0 /*!< GPIO_PORT B204: PBYTE Position */ -#define GPIO_PORT_B204_PBYTE_Msk (0x01UL << GPIO_PORT_B204_PBYTE_Pos) /*!< GPIO_PORT B204: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B205 ----------------------------------------- -#define GPIO_PORT_B205_PBYTE_Pos 0 /*!< GPIO_PORT B205: PBYTE Position */ -#define GPIO_PORT_B205_PBYTE_Msk (0x01UL << GPIO_PORT_B205_PBYTE_Pos) /*!< GPIO_PORT B205: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B206 ----------------------------------------- -#define GPIO_PORT_B206_PBYTE_Pos 0 /*!< GPIO_PORT B206: PBYTE Position */ -#define GPIO_PORT_B206_PBYTE_Msk (0x01UL << GPIO_PORT_B206_PBYTE_Pos) /*!< GPIO_PORT B206: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B207 ----------------------------------------- -#define GPIO_PORT_B207_PBYTE_Pos 0 /*!< GPIO_PORT B207: PBYTE Position */ -#define GPIO_PORT_B207_PBYTE_Msk (0x01UL << GPIO_PORT_B207_PBYTE_Pos) /*!< GPIO_PORT B207: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B208 ----------------------------------------- -#define GPIO_PORT_B208_PBYTE_Pos 0 /*!< GPIO_PORT B208: PBYTE Position */ -#define GPIO_PORT_B208_PBYTE_Msk (0x01UL << GPIO_PORT_B208_PBYTE_Pos) /*!< GPIO_PORT B208: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B209 ----------------------------------------- -#define GPIO_PORT_B209_PBYTE_Pos 0 /*!< GPIO_PORT B209: PBYTE Position */ -#define GPIO_PORT_B209_PBYTE_Msk (0x01UL << GPIO_PORT_B209_PBYTE_Pos) /*!< GPIO_PORT B209: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B210 ----------------------------------------- -#define GPIO_PORT_B210_PBYTE_Pos 0 /*!< GPIO_PORT B210: PBYTE Position */ -#define GPIO_PORT_B210_PBYTE_Msk (0x01UL << GPIO_PORT_B210_PBYTE_Pos) /*!< GPIO_PORT B210: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B211 ----------------------------------------- -#define GPIO_PORT_B211_PBYTE_Pos 0 /*!< GPIO_PORT B211: PBYTE Position */ -#define GPIO_PORT_B211_PBYTE_Msk (0x01UL << GPIO_PORT_B211_PBYTE_Pos) /*!< GPIO_PORT B211: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B212 ----------------------------------------- -#define GPIO_PORT_B212_PBYTE_Pos 0 /*!< GPIO_PORT B212: PBYTE Position */ -#define GPIO_PORT_B212_PBYTE_Msk (0x01UL << GPIO_PORT_B212_PBYTE_Pos) /*!< GPIO_PORT B212: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B213 ----------------------------------------- -#define GPIO_PORT_B213_PBYTE_Pos 0 /*!< GPIO_PORT B213: PBYTE Position */ -#define GPIO_PORT_B213_PBYTE_Msk (0x01UL << GPIO_PORT_B213_PBYTE_Pos) /*!< GPIO_PORT B213: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B214 ----------------------------------------- -#define GPIO_PORT_B214_PBYTE_Pos 0 /*!< GPIO_PORT B214: PBYTE Position */ -#define GPIO_PORT_B214_PBYTE_Msk (0x01UL << GPIO_PORT_B214_PBYTE_Pos) /*!< GPIO_PORT B214: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B215 ----------------------------------------- -#define GPIO_PORT_B215_PBYTE_Pos 0 /*!< GPIO_PORT B215: PBYTE Position */ -#define GPIO_PORT_B215_PBYTE_Msk (0x01UL << GPIO_PORT_B215_PBYTE_Pos) /*!< GPIO_PORT B215: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B216 ----------------------------------------- -#define GPIO_PORT_B216_PBYTE_Pos 0 /*!< GPIO_PORT B216: PBYTE Position */ -#define GPIO_PORT_B216_PBYTE_Msk (0x01UL << GPIO_PORT_B216_PBYTE_Pos) /*!< GPIO_PORT B216: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B217 ----------------------------------------- -#define GPIO_PORT_B217_PBYTE_Pos 0 /*!< GPIO_PORT B217: PBYTE Position */ -#define GPIO_PORT_B217_PBYTE_Msk (0x01UL << GPIO_PORT_B217_PBYTE_Pos) /*!< GPIO_PORT B217: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B218 ----------------------------------------- -#define GPIO_PORT_B218_PBYTE_Pos 0 /*!< GPIO_PORT B218: PBYTE Position */ -#define GPIO_PORT_B218_PBYTE_Msk (0x01UL << GPIO_PORT_B218_PBYTE_Pos) /*!< GPIO_PORT B218: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B219 ----------------------------------------- -#define GPIO_PORT_B219_PBYTE_Pos 0 /*!< GPIO_PORT B219: PBYTE Position */ -#define GPIO_PORT_B219_PBYTE_Msk (0x01UL << GPIO_PORT_B219_PBYTE_Pos) /*!< GPIO_PORT B219: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B220 ----------------------------------------- -#define GPIO_PORT_B220_PBYTE_Pos 0 /*!< GPIO_PORT B220: PBYTE Position */ -#define GPIO_PORT_B220_PBYTE_Msk (0x01UL << GPIO_PORT_B220_PBYTE_Pos) /*!< GPIO_PORT B220: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B221 ----------------------------------------- -#define GPIO_PORT_B221_PBYTE_Pos 0 /*!< GPIO_PORT B221: PBYTE Position */ -#define GPIO_PORT_B221_PBYTE_Msk (0x01UL << GPIO_PORT_B221_PBYTE_Pos) /*!< GPIO_PORT B221: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B222 ----------------------------------------- -#define GPIO_PORT_B222_PBYTE_Pos 0 /*!< GPIO_PORT B222: PBYTE Position */ -#define GPIO_PORT_B222_PBYTE_Msk (0x01UL << GPIO_PORT_B222_PBYTE_Pos) /*!< GPIO_PORT B222: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B223 ----------------------------------------- -#define GPIO_PORT_B223_PBYTE_Pos 0 /*!< GPIO_PORT B223: PBYTE Position */ -#define GPIO_PORT_B223_PBYTE_Msk (0x01UL << GPIO_PORT_B223_PBYTE_Pos) /*!< GPIO_PORT B223: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B224 ----------------------------------------- -#define GPIO_PORT_B224_PBYTE_Pos 0 /*!< GPIO_PORT B224: PBYTE Position */ -#define GPIO_PORT_B224_PBYTE_Msk (0x01UL << GPIO_PORT_B224_PBYTE_Pos) /*!< GPIO_PORT B224: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B225 ----------------------------------------- -#define GPIO_PORT_B225_PBYTE_Pos 0 /*!< GPIO_PORT B225: PBYTE Position */ -#define GPIO_PORT_B225_PBYTE_Msk (0x01UL << GPIO_PORT_B225_PBYTE_Pos) /*!< GPIO_PORT B225: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B226 ----------------------------------------- -#define GPIO_PORT_B226_PBYTE_Pos 0 /*!< GPIO_PORT B226: PBYTE Position */ -#define GPIO_PORT_B226_PBYTE_Msk (0x01UL << GPIO_PORT_B226_PBYTE_Pos) /*!< GPIO_PORT B226: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B227 ----------------------------------------- -#define GPIO_PORT_B227_PBYTE_Pos 0 /*!< GPIO_PORT B227: PBYTE Position */ -#define GPIO_PORT_B227_PBYTE_Msk (0x01UL << GPIO_PORT_B227_PBYTE_Pos) /*!< GPIO_PORT B227: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B228 ----------------------------------------- -#define GPIO_PORT_B228_PBYTE_Pos 0 /*!< GPIO_PORT B228: PBYTE Position */ -#define GPIO_PORT_B228_PBYTE_Msk (0x01UL << GPIO_PORT_B228_PBYTE_Pos) /*!< GPIO_PORT B228: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B229 ----------------------------------------- -#define GPIO_PORT_B229_PBYTE_Pos 0 /*!< GPIO_PORT B229: PBYTE Position */ -#define GPIO_PORT_B229_PBYTE_Msk (0x01UL << GPIO_PORT_B229_PBYTE_Pos) /*!< GPIO_PORT B229: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B230 ----------------------------------------- -#define GPIO_PORT_B230_PBYTE_Pos 0 /*!< GPIO_PORT B230: PBYTE Position */ -#define GPIO_PORT_B230_PBYTE_Msk (0x01UL << GPIO_PORT_B230_PBYTE_Pos) /*!< GPIO_PORT B230: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B231 ----------------------------------------- -#define GPIO_PORT_B231_PBYTE_Pos 0 /*!< GPIO_PORT B231: PBYTE Position */ -#define GPIO_PORT_B231_PBYTE_Msk (0x01UL << GPIO_PORT_B231_PBYTE_Pos) /*!< GPIO_PORT B231: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B232 ----------------------------------------- -#define GPIO_PORT_B232_PBYTE_Pos 0 /*!< GPIO_PORT B232: PBYTE Position */ -#define GPIO_PORT_B232_PBYTE_Msk (0x01UL << GPIO_PORT_B232_PBYTE_Pos) /*!< GPIO_PORT B232: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B233 ----------------------------------------- -#define GPIO_PORT_B233_PBYTE_Pos 0 /*!< GPIO_PORT B233: PBYTE Position */ -#define GPIO_PORT_B233_PBYTE_Msk (0x01UL << GPIO_PORT_B233_PBYTE_Pos) /*!< GPIO_PORT B233: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B234 ----------------------------------------- -#define GPIO_PORT_B234_PBYTE_Pos 0 /*!< GPIO_PORT B234: PBYTE Position */ -#define GPIO_PORT_B234_PBYTE_Msk (0x01UL << GPIO_PORT_B234_PBYTE_Pos) /*!< GPIO_PORT B234: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B235 ----------------------------------------- -#define GPIO_PORT_B235_PBYTE_Pos 0 /*!< GPIO_PORT B235: PBYTE Position */ -#define GPIO_PORT_B235_PBYTE_Msk (0x01UL << GPIO_PORT_B235_PBYTE_Pos) /*!< GPIO_PORT B235: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B236 ----------------------------------------- -#define GPIO_PORT_B236_PBYTE_Pos 0 /*!< GPIO_PORT B236: PBYTE Position */ -#define GPIO_PORT_B236_PBYTE_Msk (0x01UL << GPIO_PORT_B236_PBYTE_Pos) /*!< GPIO_PORT B236: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B237 ----------------------------------------- -#define GPIO_PORT_B237_PBYTE_Pos 0 /*!< GPIO_PORT B237: PBYTE Position */ -#define GPIO_PORT_B237_PBYTE_Msk (0x01UL << GPIO_PORT_B237_PBYTE_Pos) /*!< GPIO_PORT B237: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B238 ----------------------------------------- -#define GPIO_PORT_B238_PBYTE_Pos 0 /*!< GPIO_PORT B238: PBYTE Position */ -#define GPIO_PORT_B238_PBYTE_Msk (0x01UL << GPIO_PORT_B238_PBYTE_Pos) /*!< GPIO_PORT B238: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B239 ----------------------------------------- -#define GPIO_PORT_B239_PBYTE_Pos 0 /*!< GPIO_PORT B239: PBYTE Position */ -#define GPIO_PORT_B239_PBYTE_Msk (0x01UL << GPIO_PORT_B239_PBYTE_Pos) /*!< GPIO_PORT B239: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B240 ----------------------------------------- -#define GPIO_PORT_B240_PBYTE_Pos 0 /*!< GPIO_PORT B240: PBYTE Position */ -#define GPIO_PORT_B240_PBYTE_Msk (0x01UL << GPIO_PORT_B240_PBYTE_Pos) /*!< GPIO_PORT B240: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B241 ----------------------------------------- -#define GPIO_PORT_B241_PBYTE_Pos 0 /*!< GPIO_PORT B241: PBYTE Position */ -#define GPIO_PORT_B241_PBYTE_Msk (0x01UL << GPIO_PORT_B241_PBYTE_Pos) /*!< GPIO_PORT B241: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B242 ----------------------------------------- -#define GPIO_PORT_B242_PBYTE_Pos 0 /*!< GPIO_PORT B242: PBYTE Position */ -#define GPIO_PORT_B242_PBYTE_Msk (0x01UL << GPIO_PORT_B242_PBYTE_Pos) /*!< GPIO_PORT B242: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B243 ----------------------------------------- -#define GPIO_PORT_B243_PBYTE_Pos 0 /*!< GPIO_PORT B243: PBYTE Position */ -#define GPIO_PORT_B243_PBYTE_Msk (0x01UL << GPIO_PORT_B243_PBYTE_Pos) /*!< GPIO_PORT B243: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B244 ----------------------------------------- -#define GPIO_PORT_B244_PBYTE_Pos 0 /*!< GPIO_PORT B244: PBYTE Position */ -#define GPIO_PORT_B244_PBYTE_Msk (0x01UL << GPIO_PORT_B244_PBYTE_Pos) /*!< GPIO_PORT B244: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B245 ----------------------------------------- -#define GPIO_PORT_B245_PBYTE_Pos 0 /*!< GPIO_PORT B245: PBYTE Position */ -#define GPIO_PORT_B245_PBYTE_Msk (0x01UL << GPIO_PORT_B245_PBYTE_Pos) /*!< GPIO_PORT B245: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B246 ----------------------------------------- -#define GPIO_PORT_B246_PBYTE_Pos 0 /*!< GPIO_PORT B246: PBYTE Position */ -#define GPIO_PORT_B246_PBYTE_Msk (0x01UL << GPIO_PORT_B246_PBYTE_Pos) /*!< GPIO_PORT B246: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B247 ----------------------------------------- -#define GPIO_PORT_B247_PBYTE_Pos 0 /*!< GPIO_PORT B247: PBYTE Position */ -#define GPIO_PORT_B247_PBYTE_Msk (0x01UL << GPIO_PORT_B247_PBYTE_Pos) /*!< GPIO_PORT B247: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B248 ----------------------------------------- -#define GPIO_PORT_B248_PBYTE_Pos 0 /*!< GPIO_PORT B248: PBYTE Position */ -#define GPIO_PORT_B248_PBYTE_Msk (0x01UL << GPIO_PORT_B248_PBYTE_Pos) /*!< GPIO_PORT B248: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B249 ----------------------------------------- -#define GPIO_PORT_B249_PBYTE_Pos 0 /*!< GPIO_PORT B249: PBYTE Position */ -#define GPIO_PORT_B249_PBYTE_Msk (0x01UL << GPIO_PORT_B249_PBYTE_Pos) /*!< GPIO_PORT B249: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B250 ----------------------------------------- -#define GPIO_PORT_B250_PBYTE_Pos 0 /*!< GPIO_PORT B250: PBYTE Position */ -#define GPIO_PORT_B250_PBYTE_Msk (0x01UL << GPIO_PORT_B250_PBYTE_Pos) /*!< GPIO_PORT B250: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B251 ----------------------------------------- -#define GPIO_PORT_B251_PBYTE_Pos 0 /*!< GPIO_PORT B251: PBYTE Position */ -#define GPIO_PORT_B251_PBYTE_Msk (0x01UL << GPIO_PORT_B251_PBYTE_Pos) /*!< GPIO_PORT B251: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B252 ----------------------------------------- -#define GPIO_PORT_B252_PBYTE_Pos 0 /*!< GPIO_PORT B252: PBYTE Position */ -#define GPIO_PORT_B252_PBYTE_Msk (0x01UL << GPIO_PORT_B252_PBYTE_Pos) /*!< GPIO_PORT B252: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B253 ----------------------------------------- -#define GPIO_PORT_B253_PBYTE_Pos 0 /*!< GPIO_PORT B253: PBYTE Position */ -#define GPIO_PORT_B253_PBYTE_Msk (0x01UL << GPIO_PORT_B253_PBYTE_Pos) /*!< GPIO_PORT B253: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B254 ----------------------------------------- -#define GPIO_PORT_B254_PBYTE_Pos 0 /*!< GPIO_PORT B254: PBYTE Position */ -#define GPIO_PORT_B254_PBYTE_Msk (0x01UL << GPIO_PORT_B254_PBYTE_Pos) /*!< GPIO_PORT B254: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B255 ----------------------------------------- -#define GPIO_PORT_B255_PBYTE_Pos 0 /*!< GPIO_PORT B255: PBYTE Position */ -#define GPIO_PORT_B255_PBYTE_Msk (0x01UL << GPIO_PORT_B255_PBYTE_Pos) /*!< GPIO_PORT B255: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_W0 ------------------------------------------ -#define GPIO_PORT_W0_PWORD_Pos 0 /*!< GPIO_PORT W0: PWORD Position */ -#define GPIO_PORT_W0_PWORD_Msk (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos) /*!< GPIO_PORT W0: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W1 ------------------------------------------ -#define GPIO_PORT_W1_PWORD_Pos 0 /*!< GPIO_PORT W1: PWORD Position */ -#define GPIO_PORT_W1_PWORD_Msk (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos) /*!< GPIO_PORT W1: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W2 ------------------------------------------ -#define GPIO_PORT_W2_PWORD_Pos 0 /*!< GPIO_PORT W2: PWORD Position */ -#define GPIO_PORT_W2_PWORD_Msk (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos) /*!< GPIO_PORT W2: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W3 ------------------------------------------ -#define GPIO_PORT_W3_PWORD_Pos 0 /*!< GPIO_PORT W3: PWORD Position */ -#define GPIO_PORT_W3_PWORD_Msk (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos) /*!< GPIO_PORT W3: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W4 ------------------------------------------ -#define GPIO_PORT_W4_PWORD_Pos 0 /*!< GPIO_PORT W4: PWORD Position */ -#define GPIO_PORT_W4_PWORD_Msk (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos) /*!< GPIO_PORT W4: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W5 ------------------------------------------ -#define GPIO_PORT_W5_PWORD_Pos 0 /*!< GPIO_PORT W5: PWORD Position */ -#define GPIO_PORT_W5_PWORD_Msk (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos) /*!< GPIO_PORT W5: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W6 ------------------------------------------ -#define GPIO_PORT_W6_PWORD_Pos 0 /*!< GPIO_PORT W6: PWORD Position */ -#define GPIO_PORT_W6_PWORD_Msk (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos) /*!< GPIO_PORT W6: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W7 ------------------------------------------ -#define GPIO_PORT_W7_PWORD_Pos 0 /*!< GPIO_PORT W7: PWORD Position */ -#define GPIO_PORT_W7_PWORD_Msk (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos) /*!< GPIO_PORT W7: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W8 ------------------------------------------ -#define GPIO_PORT_W8_PWORD_Pos 0 /*!< GPIO_PORT W8: PWORD Position */ -#define GPIO_PORT_W8_PWORD_Msk (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos) /*!< GPIO_PORT W8: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W9 ------------------------------------------ -#define GPIO_PORT_W9_PWORD_Pos 0 /*!< GPIO_PORT W9: PWORD Position */ -#define GPIO_PORT_W9_PWORD_Msk (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos) /*!< GPIO_PORT W9: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W10 ----------------------------------------- -#define GPIO_PORT_W10_PWORD_Pos 0 /*!< GPIO_PORT W10: PWORD Position */ -#define GPIO_PORT_W10_PWORD_Msk (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos) /*!< GPIO_PORT W10: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W11 ----------------------------------------- -#define GPIO_PORT_W11_PWORD_Pos 0 /*!< GPIO_PORT W11: PWORD Position */ -#define GPIO_PORT_W11_PWORD_Msk (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos) /*!< GPIO_PORT W11: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W12 ----------------------------------------- -#define GPIO_PORT_W12_PWORD_Pos 0 /*!< GPIO_PORT W12: PWORD Position */ -#define GPIO_PORT_W12_PWORD_Msk (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos) /*!< GPIO_PORT W12: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W13 ----------------------------------------- -#define GPIO_PORT_W13_PWORD_Pos 0 /*!< GPIO_PORT W13: PWORD Position */ -#define GPIO_PORT_W13_PWORD_Msk (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos) /*!< GPIO_PORT W13: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W14 ----------------------------------------- -#define GPIO_PORT_W14_PWORD_Pos 0 /*!< GPIO_PORT W14: PWORD Position */ -#define GPIO_PORT_W14_PWORD_Msk (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos) /*!< GPIO_PORT W14: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W15 ----------------------------------------- -#define GPIO_PORT_W15_PWORD_Pos 0 /*!< GPIO_PORT W15: PWORD Position */ -#define GPIO_PORT_W15_PWORD_Msk (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos) /*!< GPIO_PORT W15: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W16 ----------------------------------------- -#define GPIO_PORT_W16_PWORD_Pos 0 /*!< GPIO_PORT W16: PWORD Position */ -#define GPIO_PORT_W16_PWORD_Msk (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos) /*!< GPIO_PORT W16: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W17 ----------------------------------------- -#define GPIO_PORT_W17_PWORD_Pos 0 /*!< GPIO_PORT W17: PWORD Position */ -#define GPIO_PORT_W17_PWORD_Msk (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos) /*!< GPIO_PORT W17: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W18 ----------------------------------------- -#define GPIO_PORT_W18_PWORD_Pos 0 /*!< GPIO_PORT W18: PWORD Position */ -#define GPIO_PORT_W18_PWORD_Msk (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos) /*!< GPIO_PORT W18: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W19 ----------------------------------------- -#define GPIO_PORT_W19_PWORD_Pos 0 /*!< GPIO_PORT W19: PWORD Position */ -#define GPIO_PORT_W19_PWORD_Msk (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos) /*!< GPIO_PORT W19: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W20 ----------------------------------------- -#define GPIO_PORT_W20_PWORD_Pos 0 /*!< GPIO_PORT W20: PWORD Position */ -#define GPIO_PORT_W20_PWORD_Msk (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos) /*!< GPIO_PORT W20: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W21 ----------------------------------------- -#define GPIO_PORT_W21_PWORD_Pos 0 /*!< GPIO_PORT W21: PWORD Position */ -#define GPIO_PORT_W21_PWORD_Msk (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos) /*!< GPIO_PORT W21: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W22 ----------------------------------------- -#define GPIO_PORT_W22_PWORD_Pos 0 /*!< GPIO_PORT W22: PWORD Position */ -#define GPIO_PORT_W22_PWORD_Msk (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos) /*!< GPIO_PORT W22: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W23 ----------------------------------------- -#define GPIO_PORT_W23_PWORD_Pos 0 /*!< GPIO_PORT W23: PWORD Position */ -#define GPIO_PORT_W23_PWORD_Msk (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos) /*!< GPIO_PORT W23: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W24 ----------------------------------------- -#define GPIO_PORT_W24_PWORD_Pos 0 /*!< GPIO_PORT W24: PWORD Position */ -#define GPIO_PORT_W24_PWORD_Msk (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos) /*!< GPIO_PORT W24: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W25 ----------------------------------------- -#define GPIO_PORT_W25_PWORD_Pos 0 /*!< GPIO_PORT W25: PWORD Position */ -#define GPIO_PORT_W25_PWORD_Msk (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos) /*!< GPIO_PORT W25: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W26 ----------------------------------------- -#define GPIO_PORT_W26_PWORD_Pos 0 /*!< GPIO_PORT W26: PWORD Position */ -#define GPIO_PORT_W26_PWORD_Msk (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos) /*!< GPIO_PORT W26: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W27 ----------------------------------------- -#define GPIO_PORT_W27_PWORD_Pos 0 /*!< GPIO_PORT W27: PWORD Position */ -#define GPIO_PORT_W27_PWORD_Msk (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos) /*!< GPIO_PORT W27: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W28 ----------------------------------------- -#define GPIO_PORT_W28_PWORD_Pos 0 /*!< GPIO_PORT W28: PWORD Position */ -#define GPIO_PORT_W28_PWORD_Msk (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos) /*!< GPIO_PORT W28: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W29 ----------------------------------------- -#define GPIO_PORT_W29_PWORD_Pos 0 /*!< GPIO_PORT W29: PWORD Position */ -#define GPIO_PORT_W29_PWORD_Msk (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos) /*!< GPIO_PORT W29: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W30 ----------------------------------------- -#define GPIO_PORT_W30_PWORD_Pos 0 /*!< GPIO_PORT W30: PWORD Position */ -#define GPIO_PORT_W30_PWORD_Msk (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos) /*!< GPIO_PORT W30: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W31 ----------------------------------------- -#define GPIO_PORT_W31_PWORD_Pos 0 /*!< GPIO_PORT W31: PWORD Position */ -#define GPIO_PORT_W31_PWORD_Msk (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos) /*!< GPIO_PORT W31: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W32 ----------------------------------------- -#define GPIO_PORT_W32_PWORD_Pos 0 /*!< GPIO_PORT W32: PWORD Position */ -#define GPIO_PORT_W32_PWORD_Msk (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos) /*!< GPIO_PORT W32: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W33 ----------------------------------------- -#define GPIO_PORT_W33_PWORD_Pos 0 /*!< GPIO_PORT W33: PWORD Position */ -#define GPIO_PORT_W33_PWORD_Msk (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos) /*!< GPIO_PORT W33: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W34 ----------------------------------------- -#define GPIO_PORT_W34_PWORD_Pos 0 /*!< GPIO_PORT W34: PWORD Position */ -#define GPIO_PORT_W34_PWORD_Msk (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos) /*!< GPIO_PORT W34: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W35 ----------------------------------------- -#define GPIO_PORT_W35_PWORD_Pos 0 /*!< GPIO_PORT W35: PWORD Position */ -#define GPIO_PORT_W35_PWORD_Msk (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos) /*!< GPIO_PORT W35: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W36 ----------------------------------------- -#define GPIO_PORT_W36_PWORD_Pos 0 /*!< GPIO_PORT W36: PWORD Position */ -#define GPIO_PORT_W36_PWORD_Msk (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos) /*!< GPIO_PORT W36: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W37 ----------------------------------------- -#define GPIO_PORT_W37_PWORD_Pos 0 /*!< GPIO_PORT W37: PWORD Position */ -#define GPIO_PORT_W37_PWORD_Msk (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos) /*!< GPIO_PORT W37: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W38 ----------------------------------------- -#define GPIO_PORT_W38_PWORD_Pos 0 /*!< GPIO_PORT W38: PWORD Position */ -#define GPIO_PORT_W38_PWORD_Msk (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos) /*!< GPIO_PORT W38: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W39 ----------------------------------------- -#define GPIO_PORT_W39_PWORD_Pos 0 /*!< GPIO_PORT W39: PWORD Position */ -#define GPIO_PORT_W39_PWORD_Msk (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos) /*!< GPIO_PORT W39: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W40 ----------------------------------------- -#define GPIO_PORT_W40_PWORD_Pos 0 /*!< GPIO_PORT W40: PWORD Position */ -#define GPIO_PORT_W40_PWORD_Msk (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos) /*!< GPIO_PORT W40: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W41 ----------------------------------------- -#define GPIO_PORT_W41_PWORD_Pos 0 /*!< GPIO_PORT W41: PWORD Position */ -#define GPIO_PORT_W41_PWORD_Msk (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos) /*!< GPIO_PORT W41: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W42 ----------------------------------------- -#define GPIO_PORT_W42_PWORD_Pos 0 /*!< GPIO_PORT W42: PWORD Position */ -#define GPIO_PORT_W42_PWORD_Msk (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos) /*!< GPIO_PORT W42: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W43 ----------------------------------------- -#define GPIO_PORT_W43_PWORD_Pos 0 /*!< GPIO_PORT W43: PWORD Position */ -#define GPIO_PORT_W43_PWORD_Msk (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos) /*!< GPIO_PORT W43: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W44 ----------------------------------------- -#define GPIO_PORT_W44_PWORD_Pos 0 /*!< GPIO_PORT W44: PWORD Position */ -#define GPIO_PORT_W44_PWORD_Msk (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos) /*!< GPIO_PORT W44: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W45 ----------------------------------------- -#define GPIO_PORT_W45_PWORD_Pos 0 /*!< GPIO_PORT W45: PWORD Position */ -#define GPIO_PORT_W45_PWORD_Msk (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos) /*!< GPIO_PORT W45: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W46 ----------------------------------------- -#define GPIO_PORT_W46_PWORD_Pos 0 /*!< GPIO_PORT W46: PWORD Position */ -#define GPIO_PORT_W46_PWORD_Msk (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos) /*!< GPIO_PORT W46: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W47 ----------------------------------------- -#define GPIO_PORT_W47_PWORD_Pos 0 /*!< GPIO_PORT W47: PWORD Position */ -#define GPIO_PORT_W47_PWORD_Msk (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos) /*!< GPIO_PORT W47: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W48 ----------------------------------------- -#define GPIO_PORT_W48_PWORD_Pos 0 /*!< GPIO_PORT W48: PWORD Position */ -#define GPIO_PORT_W48_PWORD_Msk (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos) /*!< GPIO_PORT W48: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W49 ----------------------------------------- -#define GPIO_PORT_W49_PWORD_Pos 0 /*!< GPIO_PORT W49: PWORD Position */ -#define GPIO_PORT_W49_PWORD_Msk (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos) /*!< GPIO_PORT W49: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W50 ----------------------------------------- -#define GPIO_PORT_W50_PWORD_Pos 0 /*!< GPIO_PORT W50: PWORD Position */ -#define GPIO_PORT_W50_PWORD_Msk (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos) /*!< GPIO_PORT W50: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W51 ----------------------------------------- -#define GPIO_PORT_W51_PWORD_Pos 0 /*!< GPIO_PORT W51: PWORD Position */ -#define GPIO_PORT_W51_PWORD_Msk (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos) /*!< GPIO_PORT W51: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W52 ----------------------------------------- -#define GPIO_PORT_W52_PWORD_Pos 0 /*!< GPIO_PORT W52: PWORD Position */ -#define GPIO_PORT_W52_PWORD_Msk (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos) /*!< GPIO_PORT W52: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W53 ----------------------------------------- -#define GPIO_PORT_W53_PWORD_Pos 0 /*!< GPIO_PORT W53: PWORD Position */ -#define GPIO_PORT_W53_PWORD_Msk (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos) /*!< GPIO_PORT W53: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W54 ----------------------------------------- -#define GPIO_PORT_W54_PWORD_Pos 0 /*!< GPIO_PORT W54: PWORD Position */ -#define GPIO_PORT_W54_PWORD_Msk (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos) /*!< GPIO_PORT W54: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W55 ----------------------------------------- -#define GPIO_PORT_W55_PWORD_Pos 0 /*!< GPIO_PORT W55: PWORD Position */ -#define GPIO_PORT_W55_PWORD_Msk (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos) /*!< GPIO_PORT W55: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W56 ----------------------------------------- -#define GPIO_PORT_W56_PWORD_Pos 0 /*!< GPIO_PORT W56: PWORD Position */ -#define GPIO_PORT_W56_PWORD_Msk (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos) /*!< GPIO_PORT W56: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W57 ----------------------------------------- -#define GPIO_PORT_W57_PWORD_Pos 0 /*!< GPIO_PORT W57: PWORD Position */ -#define GPIO_PORT_W57_PWORD_Msk (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos) /*!< GPIO_PORT W57: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W58 ----------------------------------------- -#define GPIO_PORT_W58_PWORD_Pos 0 /*!< GPIO_PORT W58: PWORD Position */ -#define GPIO_PORT_W58_PWORD_Msk (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos) /*!< GPIO_PORT W58: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W59 ----------------------------------------- -#define GPIO_PORT_W59_PWORD_Pos 0 /*!< GPIO_PORT W59: PWORD Position */ -#define GPIO_PORT_W59_PWORD_Msk (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos) /*!< GPIO_PORT W59: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W60 ----------------------------------------- -#define GPIO_PORT_W60_PWORD_Pos 0 /*!< GPIO_PORT W60: PWORD Position */ -#define GPIO_PORT_W60_PWORD_Msk (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos) /*!< GPIO_PORT W60: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W61 ----------------------------------------- -#define GPIO_PORT_W61_PWORD_Pos 0 /*!< GPIO_PORT W61: PWORD Position */ -#define GPIO_PORT_W61_PWORD_Msk (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos) /*!< GPIO_PORT W61: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W62 ----------------------------------------- -#define GPIO_PORT_W62_PWORD_Pos 0 /*!< GPIO_PORT W62: PWORD Position */ -#define GPIO_PORT_W62_PWORD_Msk (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos) /*!< GPIO_PORT W62: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W63 ----------------------------------------- -#define GPIO_PORT_W63_PWORD_Pos 0 /*!< GPIO_PORT W63: PWORD Position */ -#define GPIO_PORT_W63_PWORD_Msk (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos) /*!< GPIO_PORT W63: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W64 ----------------------------------------- -#define GPIO_PORT_W64_PWORD_Pos 0 /*!< GPIO_PORT W64: PWORD Position */ -#define GPIO_PORT_W64_PWORD_Msk (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos) /*!< GPIO_PORT W64: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W65 ----------------------------------------- -#define GPIO_PORT_W65_PWORD_Pos 0 /*!< GPIO_PORT W65: PWORD Position */ -#define GPIO_PORT_W65_PWORD_Msk (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos) /*!< GPIO_PORT W65: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W66 ----------------------------------------- -#define GPIO_PORT_W66_PWORD_Pos 0 /*!< GPIO_PORT W66: PWORD Position */ -#define GPIO_PORT_W66_PWORD_Msk (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos) /*!< GPIO_PORT W66: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W67 ----------------------------------------- -#define GPIO_PORT_W67_PWORD_Pos 0 /*!< GPIO_PORT W67: PWORD Position */ -#define GPIO_PORT_W67_PWORD_Msk (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos) /*!< GPIO_PORT W67: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W68 ----------------------------------------- -#define GPIO_PORT_W68_PWORD_Pos 0 /*!< GPIO_PORT W68: PWORD Position */ -#define GPIO_PORT_W68_PWORD_Msk (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos) /*!< GPIO_PORT W68: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W69 ----------------------------------------- -#define GPIO_PORT_W69_PWORD_Pos 0 /*!< GPIO_PORT W69: PWORD Position */ -#define GPIO_PORT_W69_PWORD_Msk (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos) /*!< GPIO_PORT W69: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W70 ----------------------------------------- -#define GPIO_PORT_W70_PWORD_Pos 0 /*!< GPIO_PORT W70: PWORD Position */ -#define GPIO_PORT_W70_PWORD_Msk (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos) /*!< GPIO_PORT W70: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W71 ----------------------------------------- -#define GPIO_PORT_W71_PWORD_Pos 0 /*!< GPIO_PORT W71: PWORD Position */ -#define GPIO_PORT_W71_PWORD_Msk (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos) /*!< GPIO_PORT W71: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W72 ----------------------------------------- -#define GPIO_PORT_W72_PWORD_Pos 0 /*!< GPIO_PORT W72: PWORD Position */ -#define GPIO_PORT_W72_PWORD_Msk (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos) /*!< GPIO_PORT W72: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W73 ----------------------------------------- -#define GPIO_PORT_W73_PWORD_Pos 0 /*!< GPIO_PORT W73: PWORD Position */ -#define GPIO_PORT_W73_PWORD_Msk (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos) /*!< GPIO_PORT W73: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W74 ----------------------------------------- -#define GPIO_PORT_W74_PWORD_Pos 0 /*!< GPIO_PORT W74: PWORD Position */ -#define GPIO_PORT_W74_PWORD_Msk (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos) /*!< GPIO_PORT W74: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W75 ----------------------------------------- -#define GPIO_PORT_W75_PWORD_Pos 0 /*!< GPIO_PORT W75: PWORD Position */ -#define GPIO_PORT_W75_PWORD_Msk (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos) /*!< GPIO_PORT W75: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W76 ----------------------------------------- -#define GPIO_PORT_W76_PWORD_Pos 0 /*!< GPIO_PORT W76: PWORD Position */ -#define GPIO_PORT_W76_PWORD_Msk (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos) /*!< GPIO_PORT W76: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W77 ----------------------------------------- -#define GPIO_PORT_W77_PWORD_Pos 0 /*!< GPIO_PORT W77: PWORD Position */ -#define GPIO_PORT_W77_PWORD_Msk (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos) /*!< GPIO_PORT W77: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W78 ----------------------------------------- -#define GPIO_PORT_W78_PWORD_Pos 0 /*!< GPIO_PORT W78: PWORD Position */ -#define GPIO_PORT_W78_PWORD_Msk (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos) /*!< GPIO_PORT W78: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W79 ----------------------------------------- -#define GPIO_PORT_W79_PWORD_Pos 0 /*!< GPIO_PORT W79: PWORD Position */ -#define GPIO_PORT_W79_PWORD_Msk (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos) /*!< GPIO_PORT W79: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W80 ----------------------------------------- -#define GPIO_PORT_W80_PWORD_Pos 0 /*!< GPIO_PORT W80: PWORD Position */ -#define GPIO_PORT_W80_PWORD_Msk (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos) /*!< GPIO_PORT W80: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W81 ----------------------------------------- -#define GPIO_PORT_W81_PWORD_Pos 0 /*!< GPIO_PORT W81: PWORD Position */ -#define GPIO_PORT_W81_PWORD_Msk (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos) /*!< GPIO_PORT W81: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W82 ----------------------------------------- -#define GPIO_PORT_W82_PWORD_Pos 0 /*!< GPIO_PORT W82: PWORD Position */ -#define GPIO_PORT_W82_PWORD_Msk (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos) /*!< GPIO_PORT W82: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W83 ----------------------------------------- -#define GPIO_PORT_W83_PWORD_Pos 0 /*!< GPIO_PORT W83: PWORD Position */ -#define GPIO_PORT_W83_PWORD_Msk (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos) /*!< GPIO_PORT W83: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W84 ----------------------------------------- -#define GPIO_PORT_W84_PWORD_Pos 0 /*!< GPIO_PORT W84: PWORD Position */ -#define GPIO_PORT_W84_PWORD_Msk (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos) /*!< GPIO_PORT W84: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W85 ----------------------------------------- -#define GPIO_PORT_W85_PWORD_Pos 0 /*!< GPIO_PORT W85: PWORD Position */ -#define GPIO_PORT_W85_PWORD_Msk (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos) /*!< GPIO_PORT W85: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W86 ----------------------------------------- -#define GPIO_PORT_W86_PWORD_Pos 0 /*!< GPIO_PORT W86: PWORD Position */ -#define GPIO_PORT_W86_PWORD_Msk (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos) /*!< GPIO_PORT W86: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W87 ----------------------------------------- -#define GPIO_PORT_W87_PWORD_Pos 0 /*!< GPIO_PORT W87: PWORD Position */ -#define GPIO_PORT_W87_PWORD_Msk (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos) /*!< GPIO_PORT W87: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W88 ----------------------------------------- -#define GPIO_PORT_W88_PWORD_Pos 0 /*!< GPIO_PORT W88: PWORD Position */ -#define GPIO_PORT_W88_PWORD_Msk (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos) /*!< GPIO_PORT W88: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W89 ----------------------------------------- -#define GPIO_PORT_W89_PWORD_Pos 0 /*!< GPIO_PORT W89: PWORD Position */ -#define GPIO_PORT_W89_PWORD_Msk (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos) /*!< GPIO_PORT W89: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W90 ----------------------------------------- -#define GPIO_PORT_W90_PWORD_Pos 0 /*!< GPIO_PORT W90: PWORD Position */ -#define GPIO_PORT_W90_PWORD_Msk (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos) /*!< GPIO_PORT W90: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W91 ----------------------------------------- -#define GPIO_PORT_W91_PWORD_Pos 0 /*!< GPIO_PORT W91: PWORD Position */ -#define GPIO_PORT_W91_PWORD_Msk (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos) /*!< GPIO_PORT W91: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W92 ----------------------------------------- -#define GPIO_PORT_W92_PWORD_Pos 0 /*!< GPIO_PORT W92: PWORD Position */ -#define GPIO_PORT_W92_PWORD_Msk (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos) /*!< GPIO_PORT W92: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W93 ----------------------------------------- -#define GPIO_PORT_W93_PWORD_Pos 0 /*!< GPIO_PORT W93: PWORD Position */ -#define GPIO_PORT_W93_PWORD_Msk (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos) /*!< GPIO_PORT W93: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W94 ----------------------------------------- -#define GPIO_PORT_W94_PWORD_Pos 0 /*!< GPIO_PORT W94: PWORD Position */ -#define GPIO_PORT_W94_PWORD_Msk (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos) /*!< GPIO_PORT W94: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W95 ----------------------------------------- -#define GPIO_PORT_W95_PWORD_Pos 0 /*!< GPIO_PORT W95: PWORD Position */ -#define GPIO_PORT_W95_PWORD_Msk (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos) /*!< GPIO_PORT W95: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W96 ----------------------------------------- -#define GPIO_PORT_W96_PWORD_Pos 0 /*!< GPIO_PORT W96: PWORD Position */ -#define GPIO_PORT_W96_PWORD_Msk (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos) /*!< GPIO_PORT W96: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W97 ----------------------------------------- -#define GPIO_PORT_W97_PWORD_Pos 0 /*!< GPIO_PORT W97: PWORD Position */ -#define GPIO_PORT_W97_PWORD_Msk (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos) /*!< GPIO_PORT W97: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W98 ----------------------------------------- -#define GPIO_PORT_W98_PWORD_Pos 0 /*!< GPIO_PORT W98: PWORD Position */ -#define GPIO_PORT_W98_PWORD_Msk (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos) /*!< GPIO_PORT W98: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W99 ----------------------------------------- -#define GPIO_PORT_W99_PWORD_Pos 0 /*!< GPIO_PORT W99: PWORD Position */ -#define GPIO_PORT_W99_PWORD_Msk (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos) /*!< GPIO_PORT W99: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W100 ----------------------------------------- -#define GPIO_PORT_W100_PWORD_Pos 0 /*!< GPIO_PORT W100: PWORD Position */ -#define GPIO_PORT_W100_PWORD_Msk (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos) /*!< GPIO_PORT W100: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W101 ----------------------------------------- -#define GPIO_PORT_W101_PWORD_Pos 0 /*!< GPIO_PORT W101: PWORD Position */ -#define GPIO_PORT_W101_PWORD_Msk (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos) /*!< GPIO_PORT W101: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W102 ----------------------------------------- -#define GPIO_PORT_W102_PWORD_Pos 0 /*!< GPIO_PORT W102: PWORD Position */ -#define GPIO_PORT_W102_PWORD_Msk (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos) /*!< GPIO_PORT W102: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W103 ----------------------------------------- -#define GPIO_PORT_W103_PWORD_Pos 0 /*!< GPIO_PORT W103: PWORD Position */ -#define GPIO_PORT_W103_PWORD_Msk (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos) /*!< GPIO_PORT W103: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W104 ----------------------------------------- -#define GPIO_PORT_W104_PWORD_Pos 0 /*!< GPIO_PORT W104: PWORD Position */ -#define GPIO_PORT_W104_PWORD_Msk (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos) /*!< GPIO_PORT W104: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W105 ----------------------------------------- -#define GPIO_PORT_W105_PWORD_Pos 0 /*!< GPIO_PORT W105: PWORD Position */ -#define GPIO_PORT_W105_PWORD_Msk (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos) /*!< GPIO_PORT W105: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W106 ----------------------------------------- -#define GPIO_PORT_W106_PWORD_Pos 0 /*!< GPIO_PORT W106: PWORD Position */ -#define GPIO_PORT_W106_PWORD_Msk (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos) /*!< GPIO_PORT W106: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W107 ----------------------------------------- -#define GPIO_PORT_W107_PWORD_Pos 0 /*!< GPIO_PORT W107: PWORD Position */ -#define GPIO_PORT_W107_PWORD_Msk (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos) /*!< GPIO_PORT W107: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W108 ----------------------------------------- -#define GPIO_PORT_W108_PWORD_Pos 0 /*!< GPIO_PORT W108: PWORD Position */ -#define GPIO_PORT_W108_PWORD_Msk (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos) /*!< GPIO_PORT W108: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W109 ----------------------------------------- -#define GPIO_PORT_W109_PWORD_Pos 0 /*!< GPIO_PORT W109: PWORD Position */ -#define GPIO_PORT_W109_PWORD_Msk (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos) /*!< GPIO_PORT W109: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W110 ----------------------------------------- -#define GPIO_PORT_W110_PWORD_Pos 0 /*!< GPIO_PORT W110: PWORD Position */ -#define GPIO_PORT_W110_PWORD_Msk (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos) /*!< GPIO_PORT W110: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W111 ----------------------------------------- -#define GPIO_PORT_W111_PWORD_Pos 0 /*!< GPIO_PORT W111: PWORD Position */ -#define GPIO_PORT_W111_PWORD_Msk (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos) /*!< GPIO_PORT W111: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W112 ----------------------------------------- -#define GPIO_PORT_W112_PWORD_Pos 0 /*!< GPIO_PORT W112: PWORD Position */ -#define GPIO_PORT_W112_PWORD_Msk (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos) /*!< GPIO_PORT W112: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W113 ----------------------------------------- -#define GPIO_PORT_W113_PWORD_Pos 0 /*!< GPIO_PORT W113: PWORD Position */ -#define GPIO_PORT_W113_PWORD_Msk (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos) /*!< GPIO_PORT W113: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W114 ----------------------------------------- -#define GPIO_PORT_W114_PWORD_Pos 0 /*!< GPIO_PORT W114: PWORD Position */ -#define GPIO_PORT_W114_PWORD_Msk (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos) /*!< GPIO_PORT W114: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W115 ----------------------------------------- -#define GPIO_PORT_W115_PWORD_Pos 0 /*!< GPIO_PORT W115: PWORD Position */ -#define GPIO_PORT_W115_PWORD_Msk (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos) /*!< GPIO_PORT W115: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W116 ----------------------------------------- -#define GPIO_PORT_W116_PWORD_Pos 0 /*!< GPIO_PORT W116: PWORD Position */ -#define GPIO_PORT_W116_PWORD_Msk (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos) /*!< GPIO_PORT W116: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W117 ----------------------------------------- -#define GPIO_PORT_W117_PWORD_Pos 0 /*!< GPIO_PORT W117: PWORD Position */ -#define GPIO_PORT_W117_PWORD_Msk (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos) /*!< GPIO_PORT W117: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W118 ----------------------------------------- -#define GPIO_PORT_W118_PWORD_Pos 0 /*!< GPIO_PORT W118: PWORD Position */ -#define GPIO_PORT_W118_PWORD_Msk (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos) /*!< GPIO_PORT W118: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W119 ----------------------------------------- -#define GPIO_PORT_W119_PWORD_Pos 0 /*!< GPIO_PORT W119: PWORD Position */ -#define GPIO_PORT_W119_PWORD_Msk (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos) /*!< GPIO_PORT W119: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W120 ----------------------------------------- -#define GPIO_PORT_W120_PWORD_Pos 0 /*!< GPIO_PORT W120: PWORD Position */ -#define GPIO_PORT_W120_PWORD_Msk (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos) /*!< GPIO_PORT W120: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W121 ----------------------------------------- -#define GPIO_PORT_W121_PWORD_Pos 0 /*!< GPIO_PORT W121: PWORD Position */ -#define GPIO_PORT_W121_PWORD_Msk (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos) /*!< GPIO_PORT W121: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W122 ----------------------------------------- -#define GPIO_PORT_W122_PWORD_Pos 0 /*!< GPIO_PORT W122: PWORD Position */ -#define GPIO_PORT_W122_PWORD_Msk (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos) /*!< GPIO_PORT W122: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W123 ----------------------------------------- -#define GPIO_PORT_W123_PWORD_Pos 0 /*!< GPIO_PORT W123: PWORD Position */ -#define GPIO_PORT_W123_PWORD_Msk (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos) /*!< GPIO_PORT W123: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W124 ----------------------------------------- -#define GPIO_PORT_W124_PWORD_Pos 0 /*!< GPIO_PORT W124: PWORD Position */ -#define GPIO_PORT_W124_PWORD_Msk (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos) /*!< GPIO_PORT W124: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W125 ----------------------------------------- -#define GPIO_PORT_W125_PWORD_Pos 0 /*!< GPIO_PORT W125: PWORD Position */ -#define GPIO_PORT_W125_PWORD_Msk (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos) /*!< GPIO_PORT W125: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W126 ----------------------------------------- -#define GPIO_PORT_W126_PWORD_Pos 0 /*!< GPIO_PORT W126: PWORD Position */ -#define GPIO_PORT_W126_PWORD_Msk (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos) /*!< GPIO_PORT W126: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W127 ----------------------------------------- -#define GPIO_PORT_W127_PWORD_Pos 0 /*!< GPIO_PORT W127: PWORD Position */ -#define GPIO_PORT_W127_PWORD_Msk (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos) /*!< GPIO_PORT W127: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W128 ----------------------------------------- -#define GPIO_PORT_W128_PWORD_Pos 0 /*!< GPIO_PORT W128: PWORD Position */ -#define GPIO_PORT_W128_PWORD_Msk (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos) /*!< GPIO_PORT W128: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W129 ----------------------------------------- -#define GPIO_PORT_W129_PWORD_Pos 0 /*!< GPIO_PORT W129: PWORD Position */ -#define GPIO_PORT_W129_PWORD_Msk (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos) /*!< GPIO_PORT W129: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W130 ----------------------------------------- -#define GPIO_PORT_W130_PWORD_Pos 0 /*!< GPIO_PORT W130: PWORD Position */ -#define GPIO_PORT_W130_PWORD_Msk (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos) /*!< GPIO_PORT W130: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W131 ----------------------------------------- -#define GPIO_PORT_W131_PWORD_Pos 0 /*!< GPIO_PORT W131: PWORD Position */ -#define GPIO_PORT_W131_PWORD_Msk (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos) /*!< GPIO_PORT W131: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W132 ----------------------------------------- -#define GPIO_PORT_W132_PWORD_Pos 0 /*!< GPIO_PORT W132: PWORD Position */ -#define GPIO_PORT_W132_PWORD_Msk (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos) /*!< GPIO_PORT W132: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W133 ----------------------------------------- -#define GPIO_PORT_W133_PWORD_Pos 0 /*!< GPIO_PORT W133: PWORD Position */ -#define GPIO_PORT_W133_PWORD_Msk (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos) /*!< GPIO_PORT W133: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W134 ----------------------------------------- -#define GPIO_PORT_W134_PWORD_Pos 0 /*!< GPIO_PORT W134: PWORD Position */ -#define GPIO_PORT_W134_PWORD_Msk (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos) /*!< GPIO_PORT W134: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W135 ----------------------------------------- -#define GPIO_PORT_W135_PWORD_Pos 0 /*!< GPIO_PORT W135: PWORD Position */ -#define GPIO_PORT_W135_PWORD_Msk (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos) /*!< GPIO_PORT W135: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W136 ----------------------------------------- -#define GPIO_PORT_W136_PWORD_Pos 0 /*!< GPIO_PORT W136: PWORD Position */ -#define GPIO_PORT_W136_PWORD_Msk (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos) /*!< GPIO_PORT W136: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W137 ----------------------------------------- -#define GPIO_PORT_W137_PWORD_Pos 0 /*!< GPIO_PORT W137: PWORD Position */ -#define GPIO_PORT_W137_PWORD_Msk (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos) /*!< GPIO_PORT W137: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W138 ----------------------------------------- -#define GPIO_PORT_W138_PWORD_Pos 0 /*!< GPIO_PORT W138: PWORD Position */ -#define GPIO_PORT_W138_PWORD_Msk (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos) /*!< GPIO_PORT W138: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W139 ----------------------------------------- -#define GPIO_PORT_W139_PWORD_Pos 0 /*!< GPIO_PORT W139: PWORD Position */ -#define GPIO_PORT_W139_PWORD_Msk (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos) /*!< GPIO_PORT W139: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W140 ----------------------------------------- -#define GPIO_PORT_W140_PWORD_Pos 0 /*!< GPIO_PORT W140: PWORD Position */ -#define GPIO_PORT_W140_PWORD_Msk (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos) /*!< GPIO_PORT W140: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W141 ----------------------------------------- -#define GPIO_PORT_W141_PWORD_Pos 0 /*!< GPIO_PORT W141: PWORD Position */ -#define GPIO_PORT_W141_PWORD_Msk (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos) /*!< GPIO_PORT W141: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W142 ----------------------------------------- -#define GPIO_PORT_W142_PWORD_Pos 0 /*!< GPIO_PORT W142: PWORD Position */ -#define GPIO_PORT_W142_PWORD_Msk (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos) /*!< GPIO_PORT W142: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W143 ----------------------------------------- -#define GPIO_PORT_W143_PWORD_Pos 0 /*!< GPIO_PORT W143: PWORD Position */ -#define GPIO_PORT_W143_PWORD_Msk (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos) /*!< GPIO_PORT W143: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W144 ----------------------------------------- -#define GPIO_PORT_W144_PWORD_Pos 0 /*!< GPIO_PORT W144: PWORD Position */ -#define GPIO_PORT_W144_PWORD_Msk (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos) /*!< GPIO_PORT W144: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W145 ----------------------------------------- -#define GPIO_PORT_W145_PWORD_Pos 0 /*!< GPIO_PORT W145: PWORD Position */ -#define GPIO_PORT_W145_PWORD_Msk (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos) /*!< GPIO_PORT W145: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W146 ----------------------------------------- -#define GPIO_PORT_W146_PWORD_Pos 0 /*!< GPIO_PORT W146: PWORD Position */ -#define GPIO_PORT_W146_PWORD_Msk (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos) /*!< GPIO_PORT W146: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W147 ----------------------------------------- -#define GPIO_PORT_W147_PWORD_Pos 0 /*!< GPIO_PORT W147: PWORD Position */ -#define GPIO_PORT_W147_PWORD_Msk (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos) /*!< GPIO_PORT W147: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W148 ----------------------------------------- -#define GPIO_PORT_W148_PWORD_Pos 0 /*!< GPIO_PORT W148: PWORD Position */ -#define GPIO_PORT_W148_PWORD_Msk (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos) /*!< GPIO_PORT W148: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W149 ----------------------------------------- -#define GPIO_PORT_W149_PWORD_Pos 0 /*!< GPIO_PORT W149: PWORD Position */ -#define GPIO_PORT_W149_PWORD_Msk (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos) /*!< GPIO_PORT W149: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W150 ----------------------------------------- -#define GPIO_PORT_W150_PWORD_Pos 0 /*!< GPIO_PORT W150: PWORD Position */ -#define GPIO_PORT_W150_PWORD_Msk (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos) /*!< GPIO_PORT W150: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W151 ----------------------------------------- -#define GPIO_PORT_W151_PWORD_Pos 0 /*!< GPIO_PORT W151: PWORD Position */ -#define GPIO_PORT_W151_PWORD_Msk (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos) /*!< GPIO_PORT W151: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W152 ----------------------------------------- -#define GPIO_PORT_W152_PWORD_Pos 0 /*!< GPIO_PORT W152: PWORD Position */ -#define GPIO_PORT_W152_PWORD_Msk (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos) /*!< GPIO_PORT W152: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W153 ----------------------------------------- -#define GPIO_PORT_W153_PWORD_Pos 0 /*!< GPIO_PORT W153: PWORD Position */ -#define GPIO_PORT_W153_PWORD_Msk (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos) /*!< GPIO_PORT W153: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W154 ----------------------------------------- -#define GPIO_PORT_W154_PWORD_Pos 0 /*!< GPIO_PORT W154: PWORD Position */ -#define GPIO_PORT_W154_PWORD_Msk (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos) /*!< GPIO_PORT W154: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W155 ----------------------------------------- -#define GPIO_PORT_W155_PWORD_Pos 0 /*!< GPIO_PORT W155: PWORD Position */ -#define GPIO_PORT_W155_PWORD_Msk (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos) /*!< GPIO_PORT W155: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W156 ----------------------------------------- -#define GPIO_PORT_W156_PWORD_Pos 0 /*!< GPIO_PORT W156: PWORD Position */ -#define GPIO_PORT_W156_PWORD_Msk (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos) /*!< GPIO_PORT W156: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W157 ----------------------------------------- -#define GPIO_PORT_W157_PWORD_Pos 0 /*!< GPIO_PORT W157: PWORD Position */ -#define GPIO_PORT_W157_PWORD_Msk (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos) /*!< GPIO_PORT W157: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W158 ----------------------------------------- -#define GPIO_PORT_W158_PWORD_Pos 0 /*!< GPIO_PORT W158: PWORD Position */ -#define GPIO_PORT_W158_PWORD_Msk (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos) /*!< GPIO_PORT W158: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W159 ----------------------------------------- -#define GPIO_PORT_W159_PWORD_Pos 0 /*!< GPIO_PORT W159: PWORD Position */ -#define GPIO_PORT_W159_PWORD_Msk (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos) /*!< GPIO_PORT W159: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W160 ----------------------------------------- -#define GPIO_PORT_W160_PWORD_Pos 0 /*!< GPIO_PORT W160: PWORD Position */ -#define GPIO_PORT_W160_PWORD_Msk (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos) /*!< GPIO_PORT W160: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W161 ----------------------------------------- -#define GPIO_PORT_W161_PWORD_Pos 0 /*!< GPIO_PORT W161: PWORD Position */ -#define GPIO_PORT_W161_PWORD_Msk (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos) /*!< GPIO_PORT W161: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W162 ----------------------------------------- -#define GPIO_PORT_W162_PWORD_Pos 0 /*!< GPIO_PORT W162: PWORD Position */ -#define GPIO_PORT_W162_PWORD_Msk (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos) /*!< GPIO_PORT W162: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W163 ----------------------------------------- -#define GPIO_PORT_W163_PWORD_Pos 0 /*!< GPIO_PORT W163: PWORD Position */ -#define GPIO_PORT_W163_PWORD_Msk (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos) /*!< GPIO_PORT W163: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W164 ----------------------------------------- -#define GPIO_PORT_W164_PWORD_Pos 0 /*!< GPIO_PORT W164: PWORD Position */ -#define GPIO_PORT_W164_PWORD_Msk (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos) /*!< GPIO_PORT W164: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W165 ----------------------------------------- -#define GPIO_PORT_W165_PWORD_Pos 0 /*!< GPIO_PORT W165: PWORD Position */ -#define GPIO_PORT_W165_PWORD_Msk (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos) /*!< GPIO_PORT W165: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W166 ----------------------------------------- -#define GPIO_PORT_W166_PWORD_Pos 0 /*!< GPIO_PORT W166: PWORD Position */ -#define GPIO_PORT_W166_PWORD_Msk (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos) /*!< GPIO_PORT W166: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W167 ----------------------------------------- -#define GPIO_PORT_W167_PWORD_Pos 0 /*!< GPIO_PORT W167: PWORD Position */ -#define GPIO_PORT_W167_PWORD_Msk (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos) /*!< GPIO_PORT W167: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W168 ----------------------------------------- -#define GPIO_PORT_W168_PWORD_Pos 0 /*!< GPIO_PORT W168: PWORD Position */ -#define GPIO_PORT_W168_PWORD_Msk (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos) /*!< GPIO_PORT W168: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W169 ----------------------------------------- -#define GPIO_PORT_W169_PWORD_Pos 0 /*!< GPIO_PORT W169: PWORD Position */ -#define GPIO_PORT_W169_PWORD_Msk (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos) /*!< GPIO_PORT W169: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W170 ----------------------------------------- -#define GPIO_PORT_W170_PWORD_Pos 0 /*!< GPIO_PORT W170: PWORD Position */ -#define GPIO_PORT_W170_PWORD_Msk (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos) /*!< GPIO_PORT W170: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W171 ----------------------------------------- -#define GPIO_PORT_W171_PWORD_Pos 0 /*!< GPIO_PORT W171: PWORD Position */ -#define GPIO_PORT_W171_PWORD_Msk (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos) /*!< GPIO_PORT W171: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W172 ----------------------------------------- -#define GPIO_PORT_W172_PWORD_Pos 0 /*!< GPIO_PORT W172: PWORD Position */ -#define GPIO_PORT_W172_PWORD_Msk (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos) /*!< GPIO_PORT W172: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W173 ----------------------------------------- -#define GPIO_PORT_W173_PWORD_Pos 0 /*!< GPIO_PORT W173: PWORD Position */ -#define GPIO_PORT_W173_PWORD_Msk (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos) /*!< GPIO_PORT W173: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W174 ----------------------------------------- -#define GPIO_PORT_W174_PWORD_Pos 0 /*!< GPIO_PORT W174: PWORD Position */ -#define GPIO_PORT_W174_PWORD_Msk (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos) /*!< GPIO_PORT W174: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W175 ----------------------------------------- -#define GPIO_PORT_W175_PWORD_Pos 0 /*!< GPIO_PORT W175: PWORD Position */ -#define GPIO_PORT_W175_PWORD_Msk (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos) /*!< GPIO_PORT W175: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W176 ----------------------------------------- -#define GPIO_PORT_W176_PWORD_Pos 0 /*!< GPIO_PORT W176: PWORD Position */ -#define GPIO_PORT_W176_PWORD_Msk (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos) /*!< GPIO_PORT W176: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W177 ----------------------------------------- -#define GPIO_PORT_W177_PWORD_Pos 0 /*!< GPIO_PORT W177: PWORD Position */ -#define GPIO_PORT_W177_PWORD_Msk (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos) /*!< GPIO_PORT W177: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W178 ----------------------------------------- -#define GPIO_PORT_W178_PWORD_Pos 0 /*!< GPIO_PORT W178: PWORD Position */ -#define GPIO_PORT_W178_PWORD_Msk (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos) /*!< GPIO_PORT W178: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W179 ----------------------------------------- -#define GPIO_PORT_W179_PWORD_Pos 0 /*!< GPIO_PORT W179: PWORD Position */ -#define GPIO_PORT_W179_PWORD_Msk (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos) /*!< GPIO_PORT W179: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W180 ----------------------------------------- -#define GPIO_PORT_W180_PWORD_Pos 0 /*!< GPIO_PORT W180: PWORD Position */ -#define GPIO_PORT_W180_PWORD_Msk (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos) /*!< GPIO_PORT W180: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W181 ----------------------------------------- -#define GPIO_PORT_W181_PWORD_Pos 0 /*!< GPIO_PORT W181: PWORD Position */ -#define GPIO_PORT_W181_PWORD_Msk (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos) /*!< GPIO_PORT W181: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W182 ----------------------------------------- -#define GPIO_PORT_W182_PWORD_Pos 0 /*!< GPIO_PORT W182: PWORD Position */ -#define GPIO_PORT_W182_PWORD_Msk (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos) /*!< GPIO_PORT W182: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W183 ----------------------------------------- -#define GPIO_PORT_W183_PWORD_Pos 0 /*!< GPIO_PORT W183: PWORD Position */ -#define GPIO_PORT_W183_PWORD_Msk (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos) /*!< GPIO_PORT W183: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W184 ----------------------------------------- -#define GPIO_PORT_W184_PWORD_Pos 0 /*!< GPIO_PORT W184: PWORD Position */ -#define GPIO_PORT_W184_PWORD_Msk (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos) /*!< GPIO_PORT W184: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W185 ----------------------------------------- -#define GPIO_PORT_W185_PWORD_Pos 0 /*!< GPIO_PORT W185: PWORD Position */ -#define GPIO_PORT_W185_PWORD_Msk (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos) /*!< GPIO_PORT W185: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W186 ----------------------------------------- -#define GPIO_PORT_W186_PWORD_Pos 0 /*!< GPIO_PORT W186: PWORD Position */ -#define GPIO_PORT_W186_PWORD_Msk (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos) /*!< GPIO_PORT W186: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W187 ----------------------------------------- -#define GPIO_PORT_W187_PWORD_Pos 0 /*!< GPIO_PORT W187: PWORD Position */ -#define GPIO_PORT_W187_PWORD_Msk (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos) /*!< GPIO_PORT W187: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W188 ----------------------------------------- -#define GPIO_PORT_W188_PWORD_Pos 0 /*!< GPIO_PORT W188: PWORD Position */ -#define GPIO_PORT_W188_PWORD_Msk (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos) /*!< GPIO_PORT W188: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W189 ----------------------------------------- -#define GPIO_PORT_W189_PWORD_Pos 0 /*!< GPIO_PORT W189: PWORD Position */ -#define GPIO_PORT_W189_PWORD_Msk (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos) /*!< GPIO_PORT W189: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W190 ----------------------------------------- -#define GPIO_PORT_W190_PWORD_Pos 0 /*!< GPIO_PORT W190: PWORD Position */ -#define GPIO_PORT_W190_PWORD_Msk (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos) /*!< GPIO_PORT W190: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W191 ----------------------------------------- -#define GPIO_PORT_W191_PWORD_Pos 0 /*!< GPIO_PORT W191: PWORD Position */ -#define GPIO_PORT_W191_PWORD_Msk (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos) /*!< GPIO_PORT W191: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W192 ----------------------------------------- -#define GPIO_PORT_W192_PWORD_Pos 0 /*!< GPIO_PORT W192: PWORD Position */ -#define GPIO_PORT_W192_PWORD_Msk (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos) /*!< GPIO_PORT W192: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W193 ----------------------------------------- -#define GPIO_PORT_W193_PWORD_Pos 0 /*!< GPIO_PORT W193: PWORD Position */ -#define GPIO_PORT_W193_PWORD_Msk (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos) /*!< GPIO_PORT W193: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W194 ----------------------------------------- -#define GPIO_PORT_W194_PWORD_Pos 0 /*!< GPIO_PORT W194: PWORD Position */ -#define GPIO_PORT_W194_PWORD_Msk (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos) /*!< GPIO_PORT W194: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W195 ----------------------------------------- -#define GPIO_PORT_W195_PWORD_Pos 0 /*!< GPIO_PORT W195: PWORD Position */ -#define GPIO_PORT_W195_PWORD_Msk (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos) /*!< GPIO_PORT W195: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W196 ----------------------------------------- -#define GPIO_PORT_W196_PWORD_Pos 0 /*!< GPIO_PORT W196: PWORD Position */ -#define GPIO_PORT_W196_PWORD_Msk (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos) /*!< GPIO_PORT W196: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W197 ----------------------------------------- -#define GPIO_PORT_W197_PWORD_Pos 0 /*!< GPIO_PORT W197: PWORD Position */ -#define GPIO_PORT_W197_PWORD_Msk (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos) /*!< GPIO_PORT W197: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W198 ----------------------------------------- -#define GPIO_PORT_W198_PWORD_Pos 0 /*!< GPIO_PORT W198: PWORD Position */ -#define GPIO_PORT_W198_PWORD_Msk (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos) /*!< GPIO_PORT W198: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W199 ----------------------------------------- -#define GPIO_PORT_W199_PWORD_Pos 0 /*!< GPIO_PORT W199: PWORD Position */ -#define GPIO_PORT_W199_PWORD_Msk (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos) /*!< GPIO_PORT W199: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W200 ----------------------------------------- -#define GPIO_PORT_W200_PWORD_Pos 0 /*!< GPIO_PORT W200: PWORD Position */ -#define GPIO_PORT_W200_PWORD_Msk (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos) /*!< GPIO_PORT W200: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W201 ----------------------------------------- -#define GPIO_PORT_W201_PWORD_Pos 0 /*!< GPIO_PORT W201: PWORD Position */ -#define GPIO_PORT_W201_PWORD_Msk (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos) /*!< GPIO_PORT W201: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W202 ----------------------------------------- -#define GPIO_PORT_W202_PWORD_Pos 0 /*!< GPIO_PORT W202: PWORD Position */ -#define GPIO_PORT_W202_PWORD_Msk (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos) /*!< GPIO_PORT W202: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W203 ----------------------------------------- -#define GPIO_PORT_W203_PWORD_Pos 0 /*!< GPIO_PORT W203: PWORD Position */ -#define GPIO_PORT_W203_PWORD_Msk (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos) /*!< GPIO_PORT W203: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W204 ----------------------------------------- -#define GPIO_PORT_W204_PWORD_Pos 0 /*!< GPIO_PORT W204: PWORD Position */ -#define GPIO_PORT_W204_PWORD_Msk (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos) /*!< GPIO_PORT W204: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W205 ----------------------------------------- -#define GPIO_PORT_W205_PWORD_Pos 0 /*!< GPIO_PORT W205: PWORD Position */ -#define GPIO_PORT_W205_PWORD_Msk (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos) /*!< GPIO_PORT W205: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W206 ----------------------------------------- -#define GPIO_PORT_W206_PWORD_Pos 0 /*!< GPIO_PORT W206: PWORD Position */ -#define GPIO_PORT_W206_PWORD_Msk (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos) /*!< GPIO_PORT W206: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W207 ----------------------------------------- -#define GPIO_PORT_W207_PWORD_Pos 0 /*!< GPIO_PORT W207: PWORD Position */ -#define GPIO_PORT_W207_PWORD_Msk (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos) /*!< GPIO_PORT W207: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W208 ----------------------------------------- -#define GPIO_PORT_W208_PWORD_Pos 0 /*!< GPIO_PORT W208: PWORD Position */ -#define GPIO_PORT_W208_PWORD_Msk (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos) /*!< GPIO_PORT W208: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W209 ----------------------------------------- -#define GPIO_PORT_W209_PWORD_Pos 0 /*!< GPIO_PORT W209: PWORD Position */ -#define GPIO_PORT_W209_PWORD_Msk (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos) /*!< GPIO_PORT W209: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W210 ----------------------------------------- -#define GPIO_PORT_W210_PWORD_Pos 0 /*!< GPIO_PORT W210: PWORD Position */ -#define GPIO_PORT_W210_PWORD_Msk (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos) /*!< GPIO_PORT W210: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W211 ----------------------------------------- -#define GPIO_PORT_W211_PWORD_Pos 0 /*!< GPIO_PORT W211: PWORD Position */ -#define GPIO_PORT_W211_PWORD_Msk (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos) /*!< GPIO_PORT W211: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W212 ----------------------------------------- -#define GPIO_PORT_W212_PWORD_Pos 0 /*!< GPIO_PORT W212: PWORD Position */ -#define GPIO_PORT_W212_PWORD_Msk (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos) /*!< GPIO_PORT W212: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W213 ----------------------------------------- -#define GPIO_PORT_W213_PWORD_Pos 0 /*!< GPIO_PORT W213: PWORD Position */ -#define GPIO_PORT_W213_PWORD_Msk (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos) /*!< GPIO_PORT W213: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W214 ----------------------------------------- -#define GPIO_PORT_W214_PWORD_Pos 0 /*!< GPIO_PORT W214: PWORD Position */ -#define GPIO_PORT_W214_PWORD_Msk (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos) /*!< GPIO_PORT W214: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W215 ----------------------------------------- -#define GPIO_PORT_W215_PWORD_Pos 0 /*!< GPIO_PORT W215: PWORD Position */ -#define GPIO_PORT_W215_PWORD_Msk (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos) /*!< GPIO_PORT W215: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W216 ----------------------------------------- -#define GPIO_PORT_W216_PWORD_Pos 0 /*!< GPIO_PORT W216: PWORD Position */ -#define GPIO_PORT_W216_PWORD_Msk (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos) /*!< GPIO_PORT W216: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W217 ----------------------------------------- -#define GPIO_PORT_W217_PWORD_Pos 0 /*!< GPIO_PORT W217: PWORD Position */ -#define GPIO_PORT_W217_PWORD_Msk (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos) /*!< GPIO_PORT W217: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W218 ----------------------------------------- -#define GPIO_PORT_W218_PWORD_Pos 0 /*!< GPIO_PORT W218: PWORD Position */ -#define GPIO_PORT_W218_PWORD_Msk (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos) /*!< GPIO_PORT W218: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W219 ----------------------------------------- -#define GPIO_PORT_W219_PWORD_Pos 0 /*!< GPIO_PORT W219: PWORD Position */ -#define GPIO_PORT_W219_PWORD_Msk (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos) /*!< GPIO_PORT W219: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W220 ----------------------------------------- -#define GPIO_PORT_W220_PWORD_Pos 0 /*!< GPIO_PORT W220: PWORD Position */ -#define GPIO_PORT_W220_PWORD_Msk (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos) /*!< GPIO_PORT W220: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W221 ----------------------------------------- -#define GPIO_PORT_W221_PWORD_Pos 0 /*!< GPIO_PORT W221: PWORD Position */ -#define GPIO_PORT_W221_PWORD_Msk (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos) /*!< GPIO_PORT W221: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W222 ----------------------------------------- -#define GPIO_PORT_W222_PWORD_Pos 0 /*!< GPIO_PORT W222: PWORD Position */ -#define GPIO_PORT_W222_PWORD_Msk (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos) /*!< GPIO_PORT W222: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W223 ----------------------------------------- -#define GPIO_PORT_W223_PWORD_Pos 0 /*!< GPIO_PORT W223: PWORD Position */ -#define GPIO_PORT_W223_PWORD_Msk (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos) /*!< GPIO_PORT W223: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W224 ----------------------------------------- -#define GPIO_PORT_W224_PWORD_Pos 0 /*!< GPIO_PORT W224: PWORD Position */ -#define GPIO_PORT_W224_PWORD_Msk (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos) /*!< GPIO_PORT W224: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W225 ----------------------------------------- -#define GPIO_PORT_W225_PWORD_Pos 0 /*!< GPIO_PORT W225: PWORD Position */ -#define GPIO_PORT_W225_PWORD_Msk (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos) /*!< GPIO_PORT W225: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W226 ----------------------------------------- -#define GPIO_PORT_W226_PWORD_Pos 0 /*!< GPIO_PORT W226: PWORD Position */ -#define GPIO_PORT_W226_PWORD_Msk (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos) /*!< GPIO_PORT W226: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W227 ----------------------------------------- -#define GPIO_PORT_W227_PWORD_Pos 0 /*!< GPIO_PORT W227: PWORD Position */ -#define GPIO_PORT_W227_PWORD_Msk (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos) /*!< GPIO_PORT W227: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W228 ----------------------------------------- -#define GPIO_PORT_W228_PWORD_Pos 0 /*!< GPIO_PORT W228: PWORD Position */ -#define GPIO_PORT_W228_PWORD_Msk (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos) /*!< GPIO_PORT W228: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W229 ----------------------------------------- -#define GPIO_PORT_W229_PWORD_Pos 0 /*!< GPIO_PORT W229: PWORD Position */ -#define GPIO_PORT_W229_PWORD_Msk (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos) /*!< GPIO_PORT W229: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W230 ----------------------------------------- -#define GPIO_PORT_W230_PWORD_Pos 0 /*!< GPIO_PORT W230: PWORD Position */ -#define GPIO_PORT_W230_PWORD_Msk (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos) /*!< GPIO_PORT W230: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W231 ----------------------------------------- -#define GPIO_PORT_W231_PWORD_Pos 0 /*!< GPIO_PORT W231: PWORD Position */ -#define GPIO_PORT_W231_PWORD_Msk (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos) /*!< GPIO_PORT W231: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W232 ----------------------------------------- -#define GPIO_PORT_W232_PWORD_Pos 0 /*!< GPIO_PORT W232: PWORD Position */ -#define GPIO_PORT_W232_PWORD_Msk (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos) /*!< GPIO_PORT W232: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W233 ----------------------------------------- -#define GPIO_PORT_W233_PWORD_Pos 0 /*!< GPIO_PORT W233: PWORD Position */ -#define GPIO_PORT_W233_PWORD_Msk (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos) /*!< GPIO_PORT W233: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W234 ----------------------------------------- -#define GPIO_PORT_W234_PWORD_Pos 0 /*!< GPIO_PORT W234: PWORD Position */ -#define GPIO_PORT_W234_PWORD_Msk (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos) /*!< GPIO_PORT W234: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W235 ----------------------------------------- -#define GPIO_PORT_W235_PWORD_Pos 0 /*!< GPIO_PORT W235: PWORD Position */ -#define GPIO_PORT_W235_PWORD_Msk (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos) /*!< GPIO_PORT W235: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W236 ----------------------------------------- -#define GPIO_PORT_W236_PWORD_Pos 0 /*!< GPIO_PORT W236: PWORD Position */ -#define GPIO_PORT_W236_PWORD_Msk (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos) /*!< GPIO_PORT W236: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W237 ----------------------------------------- -#define GPIO_PORT_W237_PWORD_Pos 0 /*!< GPIO_PORT W237: PWORD Position */ -#define GPIO_PORT_W237_PWORD_Msk (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos) /*!< GPIO_PORT W237: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W238 ----------------------------------------- -#define GPIO_PORT_W238_PWORD_Pos 0 /*!< GPIO_PORT W238: PWORD Position */ -#define GPIO_PORT_W238_PWORD_Msk (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos) /*!< GPIO_PORT W238: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W239 ----------------------------------------- -#define GPIO_PORT_W239_PWORD_Pos 0 /*!< GPIO_PORT W239: PWORD Position */ -#define GPIO_PORT_W239_PWORD_Msk (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos) /*!< GPIO_PORT W239: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W240 ----------------------------------------- -#define GPIO_PORT_W240_PWORD_Pos 0 /*!< GPIO_PORT W240: PWORD Position */ -#define GPIO_PORT_W240_PWORD_Msk (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos) /*!< GPIO_PORT W240: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W241 ----------------------------------------- -#define GPIO_PORT_W241_PWORD_Pos 0 /*!< GPIO_PORT W241: PWORD Position */ -#define GPIO_PORT_W241_PWORD_Msk (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos) /*!< GPIO_PORT W241: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W242 ----------------------------------------- -#define GPIO_PORT_W242_PWORD_Pos 0 /*!< GPIO_PORT W242: PWORD Position */ -#define GPIO_PORT_W242_PWORD_Msk (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos) /*!< GPIO_PORT W242: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W243 ----------------------------------------- -#define GPIO_PORT_W243_PWORD_Pos 0 /*!< GPIO_PORT W243: PWORD Position */ -#define GPIO_PORT_W243_PWORD_Msk (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos) /*!< GPIO_PORT W243: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W244 ----------------------------------------- -#define GPIO_PORT_W244_PWORD_Pos 0 /*!< GPIO_PORT W244: PWORD Position */ -#define GPIO_PORT_W244_PWORD_Msk (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos) /*!< GPIO_PORT W244: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W245 ----------------------------------------- -#define GPIO_PORT_W245_PWORD_Pos 0 /*!< GPIO_PORT W245: PWORD Position */ -#define GPIO_PORT_W245_PWORD_Msk (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos) /*!< GPIO_PORT W245: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W246 ----------------------------------------- -#define GPIO_PORT_W246_PWORD_Pos 0 /*!< GPIO_PORT W246: PWORD Position */ -#define GPIO_PORT_W246_PWORD_Msk (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos) /*!< GPIO_PORT W246: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W247 ----------------------------------------- -#define GPIO_PORT_W247_PWORD_Pos 0 /*!< GPIO_PORT W247: PWORD Position */ -#define GPIO_PORT_W247_PWORD_Msk (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos) /*!< GPIO_PORT W247: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W248 ----------------------------------------- -#define GPIO_PORT_W248_PWORD_Pos 0 /*!< GPIO_PORT W248: PWORD Position */ -#define GPIO_PORT_W248_PWORD_Msk (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos) /*!< GPIO_PORT W248: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W249 ----------------------------------------- -#define GPIO_PORT_W249_PWORD_Pos 0 /*!< GPIO_PORT W249: PWORD Position */ -#define GPIO_PORT_W249_PWORD_Msk (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos) /*!< GPIO_PORT W249: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W250 ----------------------------------------- -#define GPIO_PORT_W250_PWORD_Pos 0 /*!< GPIO_PORT W250: PWORD Position */ -#define GPIO_PORT_W250_PWORD_Msk (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos) /*!< GPIO_PORT W250: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W251 ----------------------------------------- -#define GPIO_PORT_W251_PWORD_Pos 0 /*!< GPIO_PORT W251: PWORD Position */ -#define GPIO_PORT_W251_PWORD_Msk (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos) /*!< GPIO_PORT W251: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W252 ----------------------------------------- -#define GPIO_PORT_W252_PWORD_Pos 0 /*!< GPIO_PORT W252: PWORD Position */ -#define GPIO_PORT_W252_PWORD_Msk (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos) /*!< GPIO_PORT W252: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W253 ----------------------------------------- -#define GPIO_PORT_W253_PWORD_Pos 0 /*!< GPIO_PORT W253: PWORD Position */ -#define GPIO_PORT_W253_PWORD_Msk (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos) /*!< GPIO_PORT W253: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W254 ----------------------------------------- -#define GPIO_PORT_W254_PWORD_Pos 0 /*!< GPIO_PORT W254: PWORD Position */ -#define GPIO_PORT_W254_PWORD_Msk (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos) /*!< GPIO_PORT W254: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W255 ----------------------------------------- -#define GPIO_PORT_W255_PWORD_Pos 0 /*!< GPIO_PORT W255: PWORD Position */ -#define GPIO_PORT_W255_PWORD_Msk (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos) /*!< GPIO_PORT W255: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_DIR0 ----------------------------------------- -#define GPIO_PORT_DIR0_DIRP0_Pos 0 /*!< GPIO_PORT DIR0: DIRP0 Position */ -#define GPIO_PORT_DIR0_DIRP0_Msk (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos) /*!< GPIO_PORT DIR0: DIRP0 Mask */ -#define GPIO_PORT_DIR0_DIRP1_Pos 1 /*!< GPIO_PORT DIR0: DIRP1 Position */ -#define GPIO_PORT_DIR0_DIRP1_Msk (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos) /*!< GPIO_PORT DIR0: DIRP1 Mask */ -#define GPIO_PORT_DIR0_DIRP2_Pos 2 /*!< GPIO_PORT DIR0: DIRP2 Position */ -#define GPIO_PORT_DIR0_DIRP2_Msk (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos) /*!< GPIO_PORT DIR0: DIRP2 Mask */ -#define GPIO_PORT_DIR0_DIRP3_Pos 3 /*!< GPIO_PORT DIR0: DIRP3 Position */ -#define GPIO_PORT_DIR0_DIRP3_Msk (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos) /*!< GPIO_PORT DIR0: DIRP3 Mask */ -#define GPIO_PORT_DIR0_DIRP4_Pos 4 /*!< GPIO_PORT DIR0: DIRP4 Position */ -#define GPIO_PORT_DIR0_DIRP4_Msk (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos) /*!< GPIO_PORT DIR0: DIRP4 Mask */ -#define GPIO_PORT_DIR0_DIRP5_Pos 5 /*!< GPIO_PORT DIR0: DIRP5 Position */ -#define GPIO_PORT_DIR0_DIRP5_Msk (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos) /*!< GPIO_PORT DIR0: DIRP5 Mask */ -#define GPIO_PORT_DIR0_DIRP6_Pos 6 /*!< GPIO_PORT DIR0: DIRP6 Position */ -#define GPIO_PORT_DIR0_DIRP6_Msk (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos) /*!< GPIO_PORT DIR0: DIRP6 Mask */ -#define GPIO_PORT_DIR0_DIRP7_Pos 7 /*!< GPIO_PORT DIR0: DIRP7 Position */ -#define GPIO_PORT_DIR0_DIRP7_Msk (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos) /*!< GPIO_PORT DIR0: DIRP7 Mask */ -#define GPIO_PORT_DIR0_DIRP8_Pos 8 /*!< GPIO_PORT DIR0: DIRP8 Position */ -#define GPIO_PORT_DIR0_DIRP8_Msk (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos) /*!< GPIO_PORT DIR0: DIRP8 Mask */ -#define GPIO_PORT_DIR0_DIRP9_Pos 9 /*!< GPIO_PORT DIR0: DIRP9 Position */ -#define GPIO_PORT_DIR0_DIRP9_Msk (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos) /*!< GPIO_PORT DIR0: DIRP9 Mask */ -#define GPIO_PORT_DIR0_DIRP10_Pos 10 /*!< GPIO_PORT DIR0: DIRP10 Position */ -#define GPIO_PORT_DIR0_DIRP10_Msk (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos) /*!< GPIO_PORT DIR0: DIRP10 Mask */ -#define GPIO_PORT_DIR0_DIRP11_Pos 11 /*!< GPIO_PORT DIR0: DIRP11 Position */ -#define GPIO_PORT_DIR0_DIRP11_Msk (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos) /*!< GPIO_PORT DIR0: DIRP11 Mask */ -#define GPIO_PORT_DIR0_DIRP12_Pos 12 /*!< GPIO_PORT DIR0: DIRP12 Position */ -#define GPIO_PORT_DIR0_DIRP12_Msk (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos) /*!< GPIO_PORT DIR0: DIRP12 Mask */ -#define GPIO_PORT_DIR0_DIRP13_Pos 13 /*!< GPIO_PORT DIR0: DIRP13 Position */ -#define GPIO_PORT_DIR0_DIRP13_Msk (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos) /*!< GPIO_PORT DIR0: DIRP13 Mask */ -#define GPIO_PORT_DIR0_DIRP14_Pos 14 /*!< GPIO_PORT DIR0: DIRP14 Position */ -#define GPIO_PORT_DIR0_DIRP14_Msk (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos) /*!< GPIO_PORT DIR0: DIRP14 Mask */ -#define GPIO_PORT_DIR0_DIRP15_Pos 15 /*!< GPIO_PORT DIR0: DIRP15 Position */ -#define GPIO_PORT_DIR0_DIRP15_Msk (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos) /*!< GPIO_PORT DIR0: DIRP15 Mask */ -#define GPIO_PORT_DIR0_DIRP16_Pos 16 /*!< GPIO_PORT DIR0: DIRP16 Position */ -#define GPIO_PORT_DIR0_DIRP16_Msk (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos) /*!< GPIO_PORT DIR0: DIRP16 Mask */ -#define GPIO_PORT_DIR0_DIRP17_Pos 17 /*!< GPIO_PORT DIR0: DIRP17 Position */ -#define GPIO_PORT_DIR0_DIRP17_Msk (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos) /*!< GPIO_PORT DIR0: DIRP17 Mask */ -#define GPIO_PORT_DIR0_DIRP18_Pos 18 /*!< GPIO_PORT DIR0: DIRP18 Position */ -#define GPIO_PORT_DIR0_DIRP18_Msk (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos) /*!< GPIO_PORT DIR0: DIRP18 Mask */ -#define GPIO_PORT_DIR0_DIRP19_Pos 19 /*!< GPIO_PORT DIR0: DIRP19 Position */ -#define GPIO_PORT_DIR0_DIRP19_Msk (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos) /*!< GPIO_PORT DIR0: DIRP19 Mask */ -#define GPIO_PORT_DIR0_DIRP20_Pos 20 /*!< GPIO_PORT DIR0: DIRP20 Position */ -#define GPIO_PORT_DIR0_DIRP20_Msk (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos) /*!< GPIO_PORT DIR0: DIRP20 Mask */ -#define GPIO_PORT_DIR0_DIRP21_Pos 21 /*!< GPIO_PORT DIR0: DIRP21 Position */ -#define GPIO_PORT_DIR0_DIRP21_Msk (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos) /*!< GPIO_PORT DIR0: DIRP21 Mask */ -#define GPIO_PORT_DIR0_DIRP22_Pos 22 /*!< GPIO_PORT DIR0: DIRP22 Position */ -#define GPIO_PORT_DIR0_DIRP22_Msk (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos) /*!< GPIO_PORT DIR0: DIRP22 Mask */ -#define GPIO_PORT_DIR0_DIRP23_Pos 23 /*!< GPIO_PORT DIR0: DIRP23 Position */ -#define GPIO_PORT_DIR0_DIRP23_Msk (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos) /*!< GPIO_PORT DIR0: DIRP23 Mask */ -#define GPIO_PORT_DIR0_DIRP24_Pos 24 /*!< GPIO_PORT DIR0: DIRP24 Position */ -#define GPIO_PORT_DIR0_DIRP24_Msk (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos) /*!< GPIO_PORT DIR0: DIRP24 Mask */ -#define GPIO_PORT_DIR0_DIRP25_Pos 25 /*!< GPIO_PORT DIR0: DIRP25 Position */ -#define GPIO_PORT_DIR0_DIRP25_Msk (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos) /*!< GPIO_PORT DIR0: DIRP25 Mask */ -#define GPIO_PORT_DIR0_DIRP26_Pos 26 /*!< GPIO_PORT DIR0: DIRP26 Position */ -#define GPIO_PORT_DIR0_DIRP26_Msk (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos) /*!< GPIO_PORT DIR0: DIRP26 Mask */ -#define GPIO_PORT_DIR0_DIRP27_Pos 27 /*!< GPIO_PORT DIR0: DIRP27 Position */ -#define GPIO_PORT_DIR0_DIRP27_Msk (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos) /*!< GPIO_PORT DIR0: DIRP27 Mask */ -#define GPIO_PORT_DIR0_DIRP28_Pos 28 /*!< GPIO_PORT DIR0: DIRP28 Position */ -#define GPIO_PORT_DIR0_DIRP28_Msk (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos) /*!< GPIO_PORT DIR0: DIRP28 Mask */ -#define GPIO_PORT_DIR0_DIRP29_Pos 29 /*!< GPIO_PORT DIR0: DIRP29 Position */ -#define GPIO_PORT_DIR0_DIRP29_Msk (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos) /*!< GPIO_PORT DIR0: DIRP29 Mask */ -#define GPIO_PORT_DIR0_DIRP30_Pos 30 /*!< GPIO_PORT DIR0: DIRP30 Position */ -#define GPIO_PORT_DIR0_DIRP30_Msk (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos) /*!< GPIO_PORT DIR0: DIRP30 Mask */ -#define GPIO_PORT_DIR0_DIRP31_Pos 31 /*!< GPIO_PORT DIR0: DIRP31 Position */ -#define GPIO_PORT_DIR0_DIRP31_Msk (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos) /*!< GPIO_PORT DIR0: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR1 ----------------------------------------- -#define GPIO_PORT_DIR1_DIRP0_Pos 0 /*!< GPIO_PORT DIR1: DIRP0 Position */ -#define GPIO_PORT_DIR1_DIRP0_Msk (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos) /*!< GPIO_PORT DIR1: DIRP0 Mask */ -#define GPIO_PORT_DIR1_DIRP1_Pos 1 /*!< GPIO_PORT DIR1: DIRP1 Position */ -#define GPIO_PORT_DIR1_DIRP1_Msk (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos) /*!< GPIO_PORT DIR1: DIRP1 Mask */ -#define GPIO_PORT_DIR1_DIRP2_Pos 2 /*!< GPIO_PORT DIR1: DIRP2 Position */ -#define GPIO_PORT_DIR1_DIRP2_Msk (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos) /*!< GPIO_PORT DIR1: DIRP2 Mask */ -#define GPIO_PORT_DIR1_DIRP3_Pos 3 /*!< GPIO_PORT DIR1: DIRP3 Position */ -#define GPIO_PORT_DIR1_DIRP3_Msk (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos) /*!< GPIO_PORT DIR1: DIRP3 Mask */ -#define GPIO_PORT_DIR1_DIRP4_Pos 4 /*!< GPIO_PORT DIR1: DIRP4 Position */ -#define GPIO_PORT_DIR1_DIRP4_Msk (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos) /*!< GPIO_PORT DIR1: DIRP4 Mask */ -#define GPIO_PORT_DIR1_DIRP5_Pos 5 /*!< GPIO_PORT DIR1: DIRP5 Position */ -#define GPIO_PORT_DIR1_DIRP5_Msk (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos) /*!< GPIO_PORT DIR1: DIRP5 Mask */ -#define GPIO_PORT_DIR1_DIRP6_Pos 6 /*!< GPIO_PORT DIR1: DIRP6 Position */ -#define GPIO_PORT_DIR1_DIRP6_Msk (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos) /*!< GPIO_PORT DIR1: DIRP6 Mask */ -#define GPIO_PORT_DIR1_DIRP7_Pos 7 /*!< GPIO_PORT DIR1: DIRP7 Position */ -#define GPIO_PORT_DIR1_DIRP7_Msk (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos) /*!< GPIO_PORT DIR1: DIRP7 Mask */ -#define GPIO_PORT_DIR1_DIRP8_Pos 8 /*!< GPIO_PORT DIR1: DIRP8 Position */ -#define GPIO_PORT_DIR1_DIRP8_Msk (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos) /*!< GPIO_PORT DIR1: DIRP8 Mask */ -#define GPIO_PORT_DIR1_DIRP9_Pos 9 /*!< GPIO_PORT DIR1: DIRP9 Position */ -#define GPIO_PORT_DIR1_DIRP9_Msk (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos) /*!< GPIO_PORT DIR1: DIRP9 Mask */ -#define GPIO_PORT_DIR1_DIRP10_Pos 10 /*!< GPIO_PORT DIR1: DIRP10 Position */ -#define GPIO_PORT_DIR1_DIRP10_Msk (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos) /*!< GPIO_PORT DIR1: DIRP10 Mask */ -#define GPIO_PORT_DIR1_DIRP11_Pos 11 /*!< GPIO_PORT DIR1: DIRP11 Position */ -#define GPIO_PORT_DIR1_DIRP11_Msk (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos) /*!< GPIO_PORT DIR1: DIRP11 Mask */ -#define GPIO_PORT_DIR1_DIRP12_Pos 12 /*!< GPIO_PORT DIR1: DIRP12 Position */ -#define GPIO_PORT_DIR1_DIRP12_Msk (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos) /*!< GPIO_PORT DIR1: DIRP12 Mask */ -#define GPIO_PORT_DIR1_DIRP13_Pos 13 /*!< GPIO_PORT DIR1: DIRP13 Position */ -#define GPIO_PORT_DIR1_DIRP13_Msk (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos) /*!< GPIO_PORT DIR1: DIRP13 Mask */ -#define GPIO_PORT_DIR1_DIRP14_Pos 14 /*!< GPIO_PORT DIR1: DIRP14 Position */ -#define GPIO_PORT_DIR1_DIRP14_Msk (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos) /*!< GPIO_PORT DIR1: DIRP14 Mask */ -#define GPIO_PORT_DIR1_DIRP15_Pos 15 /*!< GPIO_PORT DIR1: DIRP15 Position */ -#define GPIO_PORT_DIR1_DIRP15_Msk (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos) /*!< GPIO_PORT DIR1: DIRP15 Mask */ -#define GPIO_PORT_DIR1_DIRP16_Pos 16 /*!< GPIO_PORT DIR1: DIRP16 Position */ -#define GPIO_PORT_DIR1_DIRP16_Msk (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos) /*!< GPIO_PORT DIR1: DIRP16 Mask */ -#define GPIO_PORT_DIR1_DIRP17_Pos 17 /*!< GPIO_PORT DIR1: DIRP17 Position */ -#define GPIO_PORT_DIR1_DIRP17_Msk (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos) /*!< GPIO_PORT DIR1: DIRP17 Mask */ -#define GPIO_PORT_DIR1_DIRP18_Pos 18 /*!< GPIO_PORT DIR1: DIRP18 Position */ -#define GPIO_PORT_DIR1_DIRP18_Msk (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos) /*!< GPIO_PORT DIR1: DIRP18 Mask */ -#define GPIO_PORT_DIR1_DIRP19_Pos 19 /*!< GPIO_PORT DIR1: DIRP19 Position */ -#define GPIO_PORT_DIR1_DIRP19_Msk (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos) /*!< GPIO_PORT DIR1: DIRP19 Mask */ -#define GPIO_PORT_DIR1_DIRP20_Pos 20 /*!< GPIO_PORT DIR1: DIRP20 Position */ -#define GPIO_PORT_DIR1_DIRP20_Msk (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos) /*!< GPIO_PORT DIR1: DIRP20 Mask */ -#define GPIO_PORT_DIR1_DIRP21_Pos 21 /*!< GPIO_PORT DIR1: DIRP21 Position */ -#define GPIO_PORT_DIR1_DIRP21_Msk (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos) /*!< GPIO_PORT DIR1: DIRP21 Mask */ -#define GPIO_PORT_DIR1_DIRP22_Pos 22 /*!< GPIO_PORT DIR1: DIRP22 Position */ -#define GPIO_PORT_DIR1_DIRP22_Msk (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos) /*!< GPIO_PORT DIR1: DIRP22 Mask */ -#define GPIO_PORT_DIR1_DIRP23_Pos 23 /*!< GPIO_PORT DIR1: DIRP23 Position */ -#define GPIO_PORT_DIR1_DIRP23_Msk (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos) /*!< GPIO_PORT DIR1: DIRP23 Mask */ -#define GPIO_PORT_DIR1_DIRP24_Pos 24 /*!< GPIO_PORT DIR1: DIRP24 Position */ -#define GPIO_PORT_DIR1_DIRP24_Msk (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos) /*!< GPIO_PORT DIR1: DIRP24 Mask */ -#define GPIO_PORT_DIR1_DIRP25_Pos 25 /*!< GPIO_PORT DIR1: DIRP25 Position */ -#define GPIO_PORT_DIR1_DIRP25_Msk (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos) /*!< GPIO_PORT DIR1: DIRP25 Mask */ -#define GPIO_PORT_DIR1_DIRP26_Pos 26 /*!< GPIO_PORT DIR1: DIRP26 Position */ -#define GPIO_PORT_DIR1_DIRP26_Msk (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos) /*!< GPIO_PORT DIR1: DIRP26 Mask */ -#define GPIO_PORT_DIR1_DIRP27_Pos 27 /*!< GPIO_PORT DIR1: DIRP27 Position */ -#define GPIO_PORT_DIR1_DIRP27_Msk (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos) /*!< GPIO_PORT DIR1: DIRP27 Mask */ -#define GPIO_PORT_DIR1_DIRP28_Pos 28 /*!< GPIO_PORT DIR1: DIRP28 Position */ -#define GPIO_PORT_DIR1_DIRP28_Msk (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos) /*!< GPIO_PORT DIR1: DIRP28 Mask */ -#define GPIO_PORT_DIR1_DIRP29_Pos 29 /*!< GPIO_PORT DIR1: DIRP29 Position */ -#define GPIO_PORT_DIR1_DIRP29_Msk (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos) /*!< GPIO_PORT DIR1: DIRP29 Mask */ -#define GPIO_PORT_DIR1_DIRP30_Pos 30 /*!< GPIO_PORT DIR1: DIRP30 Position */ -#define GPIO_PORT_DIR1_DIRP30_Msk (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos) /*!< GPIO_PORT DIR1: DIRP30 Mask */ -#define GPIO_PORT_DIR1_DIRP31_Pos 31 /*!< GPIO_PORT DIR1: DIRP31 Position */ -#define GPIO_PORT_DIR1_DIRP31_Msk (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos) /*!< GPIO_PORT DIR1: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR2 ----------------------------------------- -#define GPIO_PORT_DIR2_DIRP0_Pos 0 /*!< GPIO_PORT DIR2: DIRP0 Position */ -#define GPIO_PORT_DIR2_DIRP0_Msk (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos) /*!< GPIO_PORT DIR2: DIRP0 Mask */ -#define GPIO_PORT_DIR2_DIRP1_Pos 1 /*!< GPIO_PORT DIR2: DIRP1 Position */ -#define GPIO_PORT_DIR2_DIRP1_Msk (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos) /*!< GPIO_PORT DIR2: DIRP1 Mask */ -#define GPIO_PORT_DIR2_DIRP2_Pos 2 /*!< GPIO_PORT DIR2: DIRP2 Position */ -#define GPIO_PORT_DIR2_DIRP2_Msk (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos) /*!< GPIO_PORT DIR2: DIRP2 Mask */ -#define GPIO_PORT_DIR2_DIRP3_Pos 3 /*!< GPIO_PORT DIR2: DIRP3 Position */ -#define GPIO_PORT_DIR2_DIRP3_Msk (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos) /*!< GPIO_PORT DIR2: DIRP3 Mask */ -#define GPIO_PORT_DIR2_DIRP4_Pos 4 /*!< GPIO_PORT DIR2: DIRP4 Position */ -#define GPIO_PORT_DIR2_DIRP4_Msk (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos) /*!< GPIO_PORT DIR2: DIRP4 Mask */ -#define GPIO_PORT_DIR2_DIRP5_Pos 5 /*!< GPIO_PORT DIR2: DIRP5 Position */ -#define GPIO_PORT_DIR2_DIRP5_Msk (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos) /*!< GPIO_PORT DIR2: DIRP5 Mask */ -#define GPIO_PORT_DIR2_DIRP6_Pos 6 /*!< GPIO_PORT DIR2: DIRP6 Position */ -#define GPIO_PORT_DIR2_DIRP6_Msk (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos) /*!< GPIO_PORT DIR2: DIRP6 Mask */ -#define GPIO_PORT_DIR2_DIRP7_Pos 7 /*!< GPIO_PORT DIR2: DIRP7 Position */ -#define GPIO_PORT_DIR2_DIRP7_Msk (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos) /*!< GPIO_PORT DIR2: DIRP7 Mask */ -#define GPIO_PORT_DIR2_DIRP8_Pos 8 /*!< GPIO_PORT DIR2: DIRP8 Position */ -#define GPIO_PORT_DIR2_DIRP8_Msk (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos) /*!< GPIO_PORT DIR2: DIRP8 Mask */ -#define GPIO_PORT_DIR2_DIRP9_Pos 9 /*!< GPIO_PORT DIR2: DIRP9 Position */ -#define GPIO_PORT_DIR2_DIRP9_Msk (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos) /*!< GPIO_PORT DIR2: DIRP9 Mask */ -#define GPIO_PORT_DIR2_DIRP10_Pos 10 /*!< GPIO_PORT DIR2: DIRP10 Position */ -#define GPIO_PORT_DIR2_DIRP10_Msk (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos) /*!< GPIO_PORT DIR2: DIRP10 Mask */ -#define GPIO_PORT_DIR2_DIRP11_Pos 11 /*!< GPIO_PORT DIR2: DIRP11 Position */ -#define GPIO_PORT_DIR2_DIRP11_Msk (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos) /*!< GPIO_PORT DIR2: DIRP11 Mask */ -#define GPIO_PORT_DIR2_DIRP12_Pos 12 /*!< GPIO_PORT DIR2: DIRP12 Position */ -#define GPIO_PORT_DIR2_DIRP12_Msk (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos) /*!< GPIO_PORT DIR2: DIRP12 Mask */ -#define GPIO_PORT_DIR2_DIRP13_Pos 13 /*!< GPIO_PORT DIR2: DIRP13 Position */ -#define GPIO_PORT_DIR2_DIRP13_Msk (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos) /*!< GPIO_PORT DIR2: DIRP13 Mask */ -#define GPIO_PORT_DIR2_DIRP14_Pos 14 /*!< GPIO_PORT DIR2: DIRP14 Position */ -#define GPIO_PORT_DIR2_DIRP14_Msk (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos) /*!< GPIO_PORT DIR2: DIRP14 Mask */ -#define GPIO_PORT_DIR2_DIRP15_Pos 15 /*!< GPIO_PORT DIR2: DIRP15 Position */ -#define GPIO_PORT_DIR2_DIRP15_Msk (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos) /*!< GPIO_PORT DIR2: DIRP15 Mask */ -#define GPIO_PORT_DIR2_DIRP16_Pos 16 /*!< GPIO_PORT DIR2: DIRP16 Position */ -#define GPIO_PORT_DIR2_DIRP16_Msk (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos) /*!< GPIO_PORT DIR2: DIRP16 Mask */ -#define GPIO_PORT_DIR2_DIRP17_Pos 17 /*!< GPIO_PORT DIR2: DIRP17 Position */ -#define GPIO_PORT_DIR2_DIRP17_Msk (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos) /*!< GPIO_PORT DIR2: DIRP17 Mask */ -#define GPIO_PORT_DIR2_DIRP18_Pos 18 /*!< GPIO_PORT DIR2: DIRP18 Position */ -#define GPIO_PORT_DIR2_DIRP18_Msk (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos) /*!< GPIO_PORT DIR2: DIRP18 Mask */ -#define GPIO_PORT_DIR2_DIRP19_Pos 19 /*!< GPIO_PORT DIR2: DIRP19 Position */ -#define GPIO_PORT_DIR2_DIRP19_Msk (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos) /*!< GPIO_PORT DIR2: DIRP19 Mask */ -#define GPIO_PORT_DIR2_DIRP20_Pos 20 /*!< GPIO_PORT DIR2: DIRP20 Position */ -#define GPIO_PORT_DIR2_DIRP20_Msk (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos) /*!< GPIO_PORT DIR2: DIRP20 Mask */ -#define GPIO_PORT_DIR2_DIRP21_Pos 21 /*!< GPIO_PORT DIR2: DIRP21 Position */ -#define GPIO_PORT_DIR2_DIRP21_Msk (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos) /*!< GPIO_PORT DIR2: DIRP21 Mask */ -#define GPIO_PORT_DIR2_DIRP22_Pos 22 /*!< GPIO_PORT DIR2: DIRP22 Position */ -#define GPIO_PORT_DIR2_DIRP22_Msk (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos) /*!< GPIO_PORT DIR2: DIRP22 Mask */ -#define GPIO_PORT_DIR2_DIRP23_Pos 23 /*!< GPIO_PORT DIR2: DIRP23 Position */ -#define GPIO_PORT_DIR2_DIRP23_Msk (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos) /*!< GPIO_PORT DIR2: DIRP23 Mask */ -#define GPIO_PORT_DIR2_DIRP24_Pos 24 /*!< GPIO_PORT DIR2: DIRP24 Position */ -#define GPIO_PORT_DIR2_DIRP24_Msk (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos) /*!< GPIO_PORT DIR2: DIRP24 Mask */ -#define GPIO_PORT_DIR2_DIRP25_Pos 25 /*!< GPIO_PORT DIR2: DIRP25 Position */ -#define GPIO_PORT_DIR2_DIRP25_Msk (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos) /*!< GPIO_PORT DIR2: DIRP25 Mask */ -#define GPIO_PORT_DIR2_DIRP26_Pos 26 /*!< GPIO_PORT DIR2: DIRP26 Position */ -#define GPIO_PORT_DIR2_DIRP26_Msk (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos) /*!< GPIO_PORT DIR2: DIRP26 Mask */ -#define GPIO_PORT_DIR2_DIRP27_Pos 27 /*!< GPIO_PORT DIR2: DIRP27 Position */ -#define GPIO_PORT_DIR2_DIRP27_Msk (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos) /*!< GPIO_PORT DIR2: DIRP27 Mask */ -#define GPIO_PORT_DIR2_DIRP28_Pos 28 /*!< GPIO_PORT DIR2: DIRP28 Position */ -#define GPIO_PORT_DIR2_DIRP28_Msk (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos) /*!< GPIO_PORT DIR2: DIRP28 Mask */ -#define GPIO_PORT_DIR2_DIRP29_Pos 29 /*!< GPIO_PORT DIR2: DIRP29 Position */ -#define GPIO_PORT_DIR2_DIRP29_Msk (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos) /*!< GPIO_PORT DIR2: DIRP29 Mask */ -#define GPIO_PORT_DIR2_DIRP30_Pos 30 /*!< GPIO_PORT DIR2: DIRP30 Position */ -#define GPIO_PORT_DIR2_DIRP30_Msk (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos) /*!< GPIO_PORT DIR2: DIRP30 Mask */ -#define GPIO_PORT_DIR2_DIRP31_Pos 31 /*!< GPIO_PORT DIR2: DIRP31 Position */ -#define GPIO_PORT_DIR2_DIRP31_Msk (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos) /*!< GPIO_PORT DIR2: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR3 ----------------------------------------- -#define GPIO_PORT_DIR3_DIRP0_Pos 0 /*!< GPIO_PORT DIR3: DIRP0 Position */ -#define GPIO_PORT_DIR3_DIRP0_Msk (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos) /*!< GPIO_PORT DIR3: DIRP0 Mask */ -#define GPIO_PORT_DIR3_DIRP1_Pos 1 /*!< GPIO_PORT DIR3: DIRP1 Position */ -#define GPIO_PORT_DIR3_DIRP1_Msk (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos) /*!< GPIO_PORT DIR3: DIRP1 Mask */ -#define GPIO_PORT_DIR3_DIRP2_Pos 2 /*!< GPIO_PORT DIR3: DIRP2 Position */ -#define GPIO_PORT_DIR3_DIRP2_Msk (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos) /*!< GPIO_PORT DIR3: DIRP2 Mask */ -#define GPIO_PORT_DIR3_DIRP3_Pos 3 /*!< GPIO_PORT DIR3: DIRP3 Position */ -#define GPIO_PORT_DIR3_DIRP3_Msk (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos) /*!< GPIO_PORT DIR3: DIRP3 Mask */ -#define GPIO_PORT_DIR3_DIRP4_Pos 4 /*!< GPIO_PORT DIR3: DIRP4 Position */ -#define GPIO_PORT_DIR3_DIRP4_Msk (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos) /*!< GPIO_PORT DIR3: DIRP4 Mask */ -#define GPIO_PORT_DIR3_DIRP5_Pos 5 /*!< GPIO_PORT DIR3: DIRP5 Position */ -#define GPIO_PORT_DIR3_DIRP5_Msk (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos) /*!< GPIO_PORT DIR3: DIRP5 Mask */ -#define GPIO_PORT_DIR3_DIRP6_Pos 6 /*!< GPIO_PORT DIR3: DIRP6 Position */ -#define GPIO_PORT_DIR3_DIRP6_Msk (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos) /*!< GPIO_PORT DIR3: DIRP6 Mask */ -#define GPIO_PORT_DIR3_DIRP7_Pos 7 /*!< GPIO_PORT DIR3: DIRP7 Position */ -#define GPIO_PORT_DIR3_DIRP7_Msk (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos) /*!< GPIO_PORT DIR3: DIRP7 Mask */ -#define GPIO_PORT_DIR3_DIRP8_Pos 8 /*!< GPIO_PORT DIR3: DIRP8 Position */ -#define GPIO_PORT_DIR3_DIRP8_Msk (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos) /*!< GPIO_PORT DIR3: DIRP8 Mask */ -#define GPIO_PORT_DIR3_DIRP9_Pos 9 /*!< GPIO_PORT DIR3: DIRP9 Position */ -#define GPIO_PORT_DIR3_DIRP9_Msk (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos) /*!< GPIO_PORT DIR3: DIRP9 Mask */ -#define GPIO_PORT_DIR3_DIRP10_Pos 10 /*!< GPIO_PORT DIR3: DIRP10 Position */ -#define GPIO_PORT_DIR3_DIRP10_Msk (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos) /*!< GPIO_PORT DIR3: DIRP10 Mask */ -#define GPIO_PORT_DIR3_DIRP11_Pos 11 /*!< GPIO_PORT DIR3: DIRP11 Position */ -#define GPIO_PORT_DIR3_DIRP11_Msk (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos) /*!< GPIO_PORT DIR3: DIRP11 Mask */ -#define GPIO_PORT_DIR3_DIRP12_Pos 12 /*!< GPIO_PORT DIR3: DIRP12 Position */ -#define GPIO_PORT_DIR3_DIRP12_Msk (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos) /*!< GPIO_PORT DIR3: DIRP12 Mask */ -#define GPIO_PORT_DIR3_DIRP13_Pos 13 /*!< GPIO_PORT DIR3: DIRP13 Position */ -#define GPIO_PORT_DIR3_DIRP13_Msk (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos) /*!< GPIO_PORT DIR3: DIRP13 Mask */ -#define GPIO_PORT_DIR3_DIRP14_Pos 14 /*!< GPIO_PORT DIR3: DIRP14 Position */ -#define GPIO_PORT_DIR3_DIRP14_Msk (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos) /*!< GPIO_PORT DIR3: DIRP14 Mask */ -#define GPIO_PORT_DIR3_DIRP15_Pos 15 /*!< GPIO_PORT DIR3: DIRP15 Position */ -#define GPIO_PORT_DIR3_DIRP15_Msk (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos) /*!< GPIO_PORT DIR3: DIRP15 Mask */ -#define GPIO_PORT_DIR3_DIRP16_Pos 16 /*!< GPIO_PORT DIR3: DIRP16 Position */ -#define GPIO_PORT_DIR3_DIRP16_Msk (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos) /*!< GPIO_PORT DIR3: DIRP16 Mask */ -#define GPIO_PORT_DIR3_DIRP17_Pos 17 /*!< GPIO_PORT DIR3: DIRP17 Position */ -#define GPIO_PORT_DIR3_DIRP17_Msk (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos) /*!< GPIO_PORT DIR3: DIRP17 Mask */ -#define GPIO_PORT_DIR3_DIRP18_Pos 18 /*!< GPIO_PORT DIR3: DIRP18 Position */ -#define GPIO_PORT_DIR3_DIRP18_Msk (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos) /*!< GPIO_PORT DIR3: DIRP18 Mask */ -#define GPIO_PORT_DIR3_DIRP19_Pos 19 /*!< GPIO_PORT DIR3: DIRP19 Position */ -#define GPIO_PORT_DIR3_DIRP19_Msk (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos) /*!< GPIO_PORT DIR3: DIRP19 Mask */ -#define GPIO_PORT_DIR3_DIRP20_Pos 20 /*!< GPIO_PORT DIR3: DIRP20 Position */ -#define GPIO_PORT_DIR3_DIRP20_Msk (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos) /*!< GPIO_PORT DIR3: DIRP20 Mask */ -#define GPIO_PORT_DIR3_DIRP21_Pos 21 /*!< GPIO_PORT DIR3: DIRP21 Position */ -#define GPIO_PORT_DIR3_DIRP21_Msk (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos) /*!< GPIO_PORT DIR3: DIRP21 Mask */ -#define GPIO_PORT_DIR3_DIRP22_Pos 22 /*!< GPIO_PORT DIR3: DIRP22 Position */ -#define GPIO_PORT_DIR3_DIRP22_Msk (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos) /*!< GPIO_PORT DIR3: DIRP22 Mask */ -#define GPIO_PORT_DIR3_DIRP23_Pos 23 /*!< GPIO_PORT DIR3: DIRP23 Position */ -#define GPIO_PORT_DIR3_DIRP23_Msk (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos) /*!< GPIO_PORT DIR3: DIRP23 Mask */ -#define GPIO_PORT_DIR3_DIRP24_Pos 24 /*!< GPIO_PORT DIR3: DIRP24 Position */ -#define GPIO_PORT_DIR3_DIRP24_Msk (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos) /*!< GPIO_PORT DIR3: DIRP24 Mask */ -#define GPIO_PORT_DIR3_DIRP25_Pos 25 /*!< GPIO_PORT DIR3: DIRP25 Position */ -#define GPIO_PORT_DIR3_DIRP25_Msk (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos) /*!< GPIO_PORT DIR3: DIRP25 Mask */ -#define GPIO_PORT_DIR3_DIRP26_Pos 26 /*!< GPIO_PORT DIR3: DIRP26 Position */ -#define GPIO_PORT_DIR3_DIRP26_Msk (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos) /*!< GPIO_PORT DIR3: DIRP26 Mask */ -#define GPIO_PORT_DIR3_DIRP27_Pos 27 /*!< GPIO_PORT DIR3: DIRP27 Position */ -#define GPIO_PORT_DIR3_DIRP27_Msk (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos) /*!< GPIO_PORT DIR3: DIRP27 Mask */ -#define GPIO_PORT_DIR3_DIRP28_Pos 28 /*!< GPIO_PORT DIR3: DIRP28 Position */ -#define GPIO_PORT_DIR3_DIRP28_Msk (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos) /*!< GPIO_PORT DIR3: DIRP28 Mask */ -#define GPIO_PORT_DIR3_DIRP29_Pos 29 /*!< GPIO_PORT DIR3: DIRP29 Position */ -#define GPIO_PORT_DIR3_DIRP29_Msk (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos) /*!< GPIO_PORT DIR3: DIRP29 Mask */ -#define GPIO_PORT_DIR3_DIRP30_Pos 30 /*!< GPIO_PORT DIR3: DIRP30 Position */ -#define GPIO_PORT_DIR3_DIRP30_Msk (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos) /*!< GPIO_PORT DIR3: DIRP30 Mask */ -#define GPIO_PORT_DIR3_DIRP31_Pos 31 /*!< GPIO_PORT DIR3: DIRP31 Position */ -#define GPIO_PORT_DIR3_DIRP31_Msk (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos) /*!< GPIO_PORT DIR3: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR4 ----------------------------------------- -#define GPIO_PORT_DIR4_DIRP0_Pos 0 /*!< GPIO_PORT DIR4: DIRP0 Position */ -#define GPIO_PORT_DIR4_DIRP0_Msk (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos) /*!< GPIO_PORT DIR4: DIRP0 Mask */ -#define GPIO_PORT_DIR4_DIRP1_Pos 1 /*!< GPIO_PORT DIR4: DIRP1 Position */ -#define GPIO_PORT_DIR4_DIRP1_Msk (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos) /*!< GPIO_PORT DIR4: DIRP1 Mask */ -#define GPIO_PORT_DIR4_DIRP2_Pos 2 /*!< GPIO_PORT DIR4: DIRP2 Position */ -#define GPIO_PORT_DIR4_DIRP2_Msk (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos) /*!< GPIO_PORT DIR4: DIRP2 Mask */ -#define GPIO_PORT_DIR4_DIRP3_Pos 3 /*!< GPIO_PORT DIR4: DIRP3 Position */ -#define GPIO_PORT_DIR4_DIRP3_Msk (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos) /*!< GPIO_PORT DIR4: DIRP3 Mask */ -#define GPIO_PORT_DIR4_DIRP4_Pos 4 /*!< GPIO_PORT DIR4: DIRP4 Position */ -#define GPIO_PORT_DIR4_DIRP4_Msk (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos) /*!< GPIO_PORT DIR4: DIRP4 Mask */ -#define GPIO_PORT_DIR4_DIRP5_Pos 5 /*!< GPIO_PORT DIR4: DIRP5 Position */ -#define GPIO_PORT_DIR4_DIRP5_Msk (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos) /*!< GPIO_PORT DIR4: DIRP5 Mask */ -#define GPIO_PORT_DIR4_DIRP6_Pos 6 /*!< GPIO_PORT DIR4: DIRP6 Position */ -#define GPIO_PORT_DIR4_DIRP6_Msk (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos) /*!< GPIO_PORT DIR4: DIRP6 Mask */ -#define GPIO_PORT_DIR4_DIRP7_Pos 7 /*!< GPIO_PORT DIR4: DIRP7 Position */ -#define GPIO_PORT_DIR4_DIRP7_Msk (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos) /*!< GPIO_PORT DIR4: DIRP7 Mask */ -#define GPIO_PORT_DIR4_DIRP8_Pos 8 /*!< GPIO_PORT DIR4: DIRP8 Position */ -#define GPIO_PORT_DIR4_DIRP8_Msk (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos) /*!< GPIO_PORT DIR4: DIRP8 Mask */ -#define GPIO_PORT_DIR4_DIRP9_Pos 9 /*!< GPIO_PORT DIR4: DIRP9 Position */ -#define GPIO_PORT_DIR4_DIRP9_Msk (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos) /*!< GPIO_PORT DIR4: DIRP9 Mask */ -#define GPIO_PORT_DIR4_DIRP10_Pos 10 /*!< GPIO_PORT DIR4: DIRP10 Position */ -#define GPIO_PORT_DIR4_DIRP10_Msk (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos) /*!< GPIO_PORT DIR4: DIRP10 Mask */ -#define GPIO_PORT_DIR4_DIRP11_Pos 11 /*!< GPIO_PORT DIR4: DIRP11 Position */ -#define GPIO_PORT_DIR4_DIRP11_Msk (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos) /*!< GPIO_PORT DIR4: DIRP11 Mask */ -#define GPIO_PORT_DIR4_DIRP12_Pos 12 /*!< GPIO_PORT DIR4: DIRP12 Position */ -#define GPIO_PORT_DIR4_DIRP12_Msk (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos) /*!< GPIO_PORT DIR4: DIRP12 Mask */ -#define GPIO_PORT_DIR4_DIRP13_Pos 13 /*!< GPIO_PORT DIR4: DIRP13 Position */ -#define GPIO_PORT_DIR4_DIRP13_Msk (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos) /*!< GPIO_PORT DIR4: DIRP13 Mask */ -#define GPIO_PORT_DIR4_DIRP14_Pos 14 /*!< GPIO_PORT DIR4: DIRP14 Position */ -#define GPIO_PORT_DIR4_DIRP14_Msk (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos) /*!< GPIO_PORT DIR4: DIRP14 Mask */ -#define GPIO_PORT_DIR4_DIRP15_Pos 15 /*!< GPIO_PORT DIR4: DIRP15 Position */ -#define GPIO_PORT_DIR4_DIRP15_Msk (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos) /*!< GPIO_PORT DIR4: DIRP15 Mask */ -#define GPIO_PORT_DIR4_DIRP16_Pos 16 /*!< GPIO_PORT DIR4: DIRP16 Position */ -#define GPIO_PORT_DIR4_DIRP16_Msk (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos) /*!< GPIO_PORT DIR4: DIRP16 Mask */ -#define GPIO_PORT_DIR4_DIRP17_Pos 17 /*!< GPIO_PORT DIR4: DIRP17 Position */ -#define GPIO_PORT_DIR4_DIRP17_Msk (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos) /*!< GPIO_PORT DIR4: DIRP17 Mask */ -#define GPIO_PORT_DIR4_DIRP18_Pos 18 /*!< GPIO_PORT DIR4: DIRP18 Position */ -#define GPIO_PORT_DIR4_DIRP18_Msk (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos) /*!< GPIO_PORT DIR4: DIRP18 Mask */ -#define GPIO_PORT_DIR4_DIRP19_Pos 19 /*!< GPIO_PORT DIR4: DIRP19 Position */ -#define GPIO_PORT_DIR4_DIRP19_Msk (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos) /*!< GPIO_PORT DIR4: DIRP19 Mask */ -#define GPIO_PORT_DIR4_DIRP20_Pos 20 /*!< GPIO_PORT DIR4: DIRP20 Position */ -#define GPIO_PORT_DIR4_DIRP20_Msk (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos) /*!< GPIO_PORT DIR4: DIRP20 Mask */ -#define GPIO_PORT_DIR4_DIRP21_Pos 21 /*!< GPIO_PORT DIR4: DIRP21 Position */ -#define GPIO_PORT_DIR4_DIRP21_Msk (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos) /*!< GPIO_PORT DIR4: DIRP21 Mask */ -#define GPIO_PORT_DIR4_DIRP22_Pos 22 /*!< GPIO_PORT DIR4: DIRP22 Position */ -#define GPIO_PORT_DIR4_DIRP22_Msk (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos) /*!< GPIO_PORT DIR4: DIRP22 Mask */ -#define GPIO_PORT_DIR4_DIRP23_Pos 23 /*!< GPIO_PORT DIR4: DIRP23 Position */ -#define GPIO_PORT_DIR4_DIRP23_Msk (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos) /*!< GPIO_PORT DIR4: DIRP23 Mask */ -#define GPIO_PORT_DIR4_DIRP24_Pos 24 /*!< GPIO_PORT DIR4: DIRP24 Position */ -#define GPIO_PORT_DIR4_DIRP24_Msk (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos) /*!< GPIO_PORT DIR4: DIRP24 Mask */ -#define GPIO_PORT_DIR4_DIRP25_Pos 25 /*!< GPIO_PORT DIR4: DIRP25 Position */ -#define GPIO_PORT_DIR4_DIRP25_Msk (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos) /*!< GPIO_PORT DIR4: DIRP25 Mask */ -#define GPIO_PORT_DIR4_DIRP26_Pos 26 /*!< GPIO_PORT DIR4: DIRP26 Position */ -#define GPIO_PORT_DIR4_DIRP26_Msk (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos) /*!< GPIO_PORT DIR4: DIRP26 Mask */ -#define GPIO_PORT_DIR4_DIRP27_Pos 27 /*!< GPIO_PORT DIR4: DIRP27 Position */ -#define GPIO_PORT_DIR4_DIRP27_Msk (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos) /*!< GPIO_PORT DIR4: DIRP27 Mask */ -#define GPIO_PORT_DIR4_DIRP28_Pos 28 /*!< GPIO_PORT DIR4: DIRP28 Position */ -#define GPIO_PORT_DIR4_DIRP28_Msk (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos) /*!< GPIO_PORT DIR4: DIRP28 Mask */ -#define GPIO_PORT_DIR4_DIRP29_Pos 29 /*!< GPIO_PORT DIR4: DIRP29 Position */ -#define GPIO_PORT_DIR4_DIRP29_Msk (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos) /*!< GPIO_PORT DIR4: DIRP29 Mask */ -#define GPIO_PORT_DIR4_DIRP30_Pos 30 /*!< GPIO_PORT DIR4: DIRP30 Position */ -#define GPIO_PORT_DIR4_DIRP30_Msk (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos) /*!< GPIO_PORT DIR4: DIRP30 Mask */ -#define GPIO_PORT_DIR4_DIRP31_Pos 31 /*!< GPIO_PORT DIR4: DIRP31 Position */ -#define GPIO_PORT_DIR4_DIRP31_Msk (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos) /*!< GPIO_PORT DIR4: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR5 ----------------------------------------- -#define GPIO_PORT_DIR5_DIRP0_Pos 0 /*!< GPIO_PORT DIR5: DIRP0 Position */ -#define GPIO_PORT_DIR5_DIRP0_Msk (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos) /*!< GPIO_PORT DIR5: DIRP0 Mask */ -#define GPIO_PORT_DIR5_DIRP1_Pos 1 /*!< GPIO_PORT DIR5: DIRP1 Position */ -#define GPIO_PORT_DIR5_DIRP1_Msk (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos) /*!< GPIO_PORT DIR5: DIRP1 Mask */ -#define GPIO_PORT_DIR5_DIRP2_Pos 2 /*!< GPIO_PORT DIR5: DIRP2 Position */ -#define GPIO_PORT_DIR5_DIRP2_Msk (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos) /*!< GPIO_PORT DIR5: DIRP2 Mask */ -#define GPIO_PORT_DIR5_DIRP3_Pos 3 /*!< GPIO_PORT DIR5: DIRP3 Position */ -#define GPIO_PORT_DIR5_DIRP3_Msk (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos) /*!< GPIO_PORT DIR5: DIRP3 Mask */ -#define GPIO_PORT_DIR5_DIRP4_Pos 4 /*!< GPIO_PORT DIR5: DIRP4 Position */ -#define GPIO_PORT_DIR5_DIRP4_Msk (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos) /*!< GPIO_PORT DIR5: DIRP4 Mask */ -#define GPIO_PORT_DIR5_DIRP5_Pos 5 /*!< GPIO_PORT DIR5: DIRP5 Position */ -#define GPIO_PORT_DIR5_DIRP5_Msk (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos) /*!< GPIO_PORT DIR5: DIRP5 Mask */ -#define GPIO_PORT_DIR5_DIRP6_Pos 6 /*!< GPIO_PORT DIR5: DIRP6 Position */ -#define GPIO_PORT_DIR5_DIRP6_Msk (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos) /*!< GPIO_PORT DIR5: DIRP6 Mask */ -#define GPIO_PORT_DIR5_DIRP7_Pos 7 /*!< GPIO_PORT DIR5: DIRP7 Position */ -#define GPIO_PORT_DIR5_DIRP7_Msk (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos) /*!< GPIO_PORT DIR5: DIRP7 Mask */ -#define GPIO_PORT_DIR5_DIRP8_Pos 8 /*!< GPIO_PORT DIR5: DIRP8 Position */ -#define GPIO_PORT_DIR5_DIRP8_Msk (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos) /*!< GPIO_PORT DIR5: DIRP8 Mask */ -#define GPIO_PORT_DIR5_DIRP9_Pos 9 /*!< GPIO_PORT DIR5: DIRP9 Position */ -#define GPIO_PORT_DIR5_DIRP9_Msk (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos) /*!< GPIO_PORT DIR5: DIRP9 Mask */ -#define GPIO_PORT_DIR5_DIRP10_Pos 10 /*!< GPIO_PORT DIR5: DIRP10 Position */ -#define GPIO_PORT_DIR5_DIRP10_Msk (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos) /*!< GPIO_PORT DIR5: DIRP10 Mask */ -#define GPIO_PORT_DIR5_DIRP11_Pos 11 /*!< GPIO_PORT DIR5: DIRP11 Position */ -#define GPIO_PORT_DIR5_DIRP11_Msk (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos) /*!< GPIO_PORT DIR5: DIRP11 Mask */ -#define GPIO_PORT_DIR5_DIRP12_Pos 12 /*!< GPIO_PORT DIR5: DIRP12 Position */ -#define GPIO_PORT_DIR5_DIRP12_Msk (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos) /*!< GPIO_PORT DIR5: DIRP12 Mask */ -#define GPIO_PORT_DIR5_DIRP13_Pos 13 /*!< GPIO_PORT DIR5: DIRP13 Position */ -#define GPIO_PORT_DIR5_DIRP13_Msk (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos) /*!< GPIO_PORT DIR5: DIRP13 Mask */ -#define GPIO_PORT_DIR5_DIRP14_Pos 14 /*!< GPIO_PORT DIR5: DIRP14 Position */ -#define GPIO_PORT_DIR5_DIRP14_Msk (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos) /*!< GPIO_PORT DIR5: DIRP14 Mask */ -#define GPIO_PORT_DIR5_DIRP15_Pos 15 /*!< GPIO_PORT DIR5: DIRP15 Position */ -#define GPIO_PORT_DIR5_DIRP15_Msk (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos) /*!< GPIO_PORT DIR5: DIRP15 Mask */ -#define GPIO_PORT_DIR5_DIRP16_Pos 16 /*!< GPIO_PORT DIR5: DIRP16 Position */ -#define GPIO_PORT_DIR5_DIRP16_Msk (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos) /*!< GPIO_PORT DIR5: DIRP16 Mask */ -#define GPIO_PORT_DIR5_DIRP17_Pos 17 /*!< GPIO_PORT DIR5: DIRP17 Position */ -#define GPIO_PORT_DIR5_DIRP17_Msk (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos) /*!< GPIO_PORT DIR5: DIRP17 Mask */ -#define GPIO_PORT_DIR5_DIRP18_Pos 18 /*!< GPIO_PORT DIR5: DIRP18 Position */ -#define GPIO_PORT_DIR5_DIRP18_Msk (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos) /*!< GPIO_PORT DIR5: DIRP18 Mask */ -#define GPIO_PORT_DIR5_DIRP19_Pos 19 /*!< GPIO_PORT DIR5: DIRP19 Position */ -#define GPIO_PORT_DIR5_DIRP19_Msk (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos) /*!< GPIO_PORT DIR5: DIRP19 Mask */ -#define GPIO_PORT_DIR5_DIRP20_Pos 20 /*!< GPIO_PORT DIR5: DIRP20 Position */ -#define GPIO_PORT_DIR5_DIRP20_Msk (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos) /*!< GPIO_PORT DIR5: DIRP20 Mask */ -#define GPIO_PORT_DIR5_DIRP21_Pos 21 /*!< GPIO_PORT DIR5: DIRP21 Position */ -#define GPIO_PORT_DIR5_DIRP21_Msk (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos) /*!< GPIO_PORT DIR5: DIRP21 Mask */ -#define GPIO_PORT_DIR5_DIRP22_Pos 22 /*!< GPIO_PORT DIR5: DIRP22 Position */ -#define GPIO_PORT_DIR5_DIRP22_Msk (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos) /*!< GPIO_PORT DIR5: DIRP22 Mask */ -#define GPIO_PORT_DIR5_DIRP23_Pos 23 /*!< GPIO_PORT DIR5: DIRP23 Position */ -#define GPIO_PORT_DIR5_DIRP23_Msk (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos) /*!< GPIO_PORT DIR5: DIRP23 Mask */ -#define GPIO_PORT_DIR5_DIRP24_Pos 24 /*!< GPIO_PORT DIR5: DIRP24 Position */ -#define GPIO_PORT_DIR5_DIRP24_Msk (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos) /*!< GPIO_PORT DIR5: DIRP24 Mask */ -#define GPIO_PORT_DIR5_DIRP25_Pos 25 /*!< GPIO_PORT DIR5: DIRP25 Position */ -#define GPIO_PORT_DIR5_DIRP25_Msk (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos) /*!< GPIO_PORT DIR5: DIRP25 Mask */ -#define GPIO_PORT_DIR5_DIRP26_Pos 26 /*!< GPIO_PORT DIR5: DIRP26 Position */ -#define GPIO_PORT_DIR5_DIRP26_Msk (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos) /*!< GPIO_PORT DIR5: DIRP26 Mask */ -#define GPIO_PORT_DIR5_DIRP27_Pos 27 /*!< GPIO_PORT DIR5: DIRP27 Position */ -#define GPIO_PORT_DIR5_DIRP27_Msk (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos) /*!< GPIO_PORT DIR5: DIRP27 Mask */ -#define GPIO_PORT_DIR5_DIRP28_Pos 28 /*!< GPIO_PORT DIR5: DIRP28 Position */ -#define GPIO_PORT_DIR5_DIRP28_Msk (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos) /*!< GPIO_PORT DIR5: DIRP28 Mask */ -#define GPIO_PORT_DIR5_DIRP29_Pos 29 /*!< GPIO_PORT DIR5: DIRP29 Position */ -#define GPIO_PORT_DIR5_DIRP29_Msk (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos) /*!< GPIO_PORT DIR5: DIRP29 Mask */ -#define GPIO_PORT_DIR5_DIRP30_Pos 30 /*!< GPIO_PORT DIR5: DIRP30 Position */ -#define GPIO_PORT_DIR5_DIRP30_Msk (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos) /*!< GPIO_PORT DIR5: DIRP30 Mask */ -#define GPIO_PORT_DIR5_DIRP31_Pos 31 /*!< GPIO_PORT DIR5: DIRP31 Position */ -#define GPIO_PORT_DIR5_DIRP31_Msk (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos) /*!< GPIO_PORT DIR5: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR6 ----------------------------------------- -#define GPIO_PORT_DIR6_DIRP0_Pos 0 /*!< GPIO_PORT DIR6: DIRP0 Position */ -#define GPIO_PORT_DIR6_DIRP0_Msk (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos) /*!< GPIO_PORT DIR6: DIRP0 Mask */ -#define GPIO_PORT_DIR6_DIRP1_Pos 1 /*!< GPIO_PORT DIR6: DIRP1 Position */ -#define GPIO_PORT_DIR6_DIRP1_Msk (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos) /*!< GPIO_PORT DIR6: DIRP1 Mask */ -#define GPIO_PORT_DIR6_DIRP2_Pos 2 /*!< GPIO_PORT DIR6: DIRP2 Position */ -#define GPIO_PORT_DIR6_DIRP2_Msk (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos) /*!< GPIO_PORT DIR6: DIRP2 Mask */ -#define GPIO_PORT_DIR6_DIRP3_Pos 3 /*!< GPIO_PORT DIR6: DIRP3 Position */ -#define GPIO_PORT_DIR6_DIRP3_Msk (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos) /*!< GPIO_PORT DIR6: DIRP3 Mask */ -#define GPIO_PORT_DIR6_DIRP4_Pos 4 /*!< GPIO_PORT DIR6: DIRP4 Position */ -#define GPIO_PORT_DIR6_DIRP4_Msk (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos) /*!< GPIO_PORT DIR6: DIRP4 Mask */ -#define GPIO_PORT_DIR6_DIRP5_Pos 5 /*!< GPIO_PORT DIR6: DIRP5 Position */ -#define GPIO_PORT_DIR6_DIRP5_Msk (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos) /*!< GPIO_PORT DIR6: DIRP5 Mask */ -#define GPIO_PORT_DIR6_DIRP6_Pos 6 /*!< GPIO_PORT DIR6: DIRP6 Position */ -#define GPIO_PORT_DIR6_DIRP6_Msk (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos) /*!< GPIO_PORT DIR6: DIRP6 Mask */ -#define GPIO_PORT_DIR6_DIRP7_Pos 7 /*!< GPIO_PORT DIR6: DIRP7 Position */ -#define GPIO_PORT_DIR6_DIRP7_Msk (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos) /*!< GPIO_PORT DIR6: DIRP7 Mask */ -#define GPIO_PORT_DIR6_DIRP8_Pos 8 /*!< GPIO_PORT DIR6: DIRP8 Position */ -#define GPIO_PORT_DIR6_DIRP8_Msk (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos) /*!< GPIO_PORT DIR6: DIRP8 Mask */ -#define GPIO_PORT_DIR6_DIRP9_Pos 9 /*!< GPIO_PORT DIR6: DIRP9 Position */ -#define GPIO_PORT_DIR6_DIRP9_Msk (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos) /*!< GPIO_PORT DIR6: DIRP9 Mask */ -#define GPIO_PORT_DIR6_DIRP10_Pos 10 /*!< GPIO_PORT DIR6: DIRP10 Position */ -#define GPIO_PORT_DIR6_DIRP10_Msk (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos) /*!< GPIO_PORT DIR6: DIRP10 Mask */ -#define GPIO_PORT_DIR6_DIRP11_Pos 11 /*!< GPIO_PORT DIR6: DIRP11 Position */ -#define GPIO_PORT_DIR6_DIRP11_Msk (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos) /*!< GPIO_PORT DIR6: DIRP11 Mask */ -#define GPIO_PORT_DIR6_DIRP12_Pos 12 /*!< GPIO_PORT DIR6: DIRP12 Position */ -#define GPIO_PORT_DIR6_DIRP12_Msk (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos) /*!< GPIO_PORT DIR6: DIRP12 Mask */ -#define GPIO_PORT_DIR6_DIRP13_Pos 13 /*!< GPIO_PORT DIR6: DIRP13 Position */ -#define GPIO_PORT_DIR6_DIRP13_Msk (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos) /*!< GPIO_PORT DIR6: DIRP13 Mask */ -#define GPIO_PORT_DIR6_DIRP14_Pos 14 /*!< GPIO_PORT DIR6: DIRP14 Position */ -#define GPIO_PORT_DIR6_DIRP14_Msk (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos) /*!< GPIO_PORT DIR6: DIRP14 Mask */ -#define GPIO_PORT_DIR6_DIRP15_Pos 15 /*!< GPIO_PORT DIR6: DIRP15 Position */ -#define GPIO_PORT_DIR6_DIRP15_Msk (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos) /*!< GPIO_PORT DIR6: DIRP15 Mask */ -#define GPIO_PORT_DIR6_DIRP16_Pos 16 /*!< GPIO_PORT DIR6: DIRP16 Position */ -#define GPIO_PORT_DIR6_DIRP16_Msk (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos) /*!< GPIO_PORT DIR6: DIRP16 Mask */ -#define GPIO_PORT_DIR6_DIRP17_Pos 17 /*!< GPIO_PORT DIR6: DIRP17 Position */ -#define GPIO_PORT_DIR6_DIRP17_Msk (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos) /*!< GPIO_PORT DIR6: DIRP17 Mask */ -#define GPIO_PORT_DIR6_DIRP18_Pos 18 /*!< GPIO_PORT DIR6: DIRP18 Position */ -#define GPIO_PORT_DIR6_DIRP18_Msk (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos) /*!< GPIO_PORT DIR6: DIRP18 Mask */ -#define GPIO_PORT_DIR6_DIRP19_Pos 19 /*!< GPIO_PORT DIR6: DIRP19 Position */ -#define GPIO_PORT_DIR6_DIRP19_Msk (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos) /*!< GPIO_PORT DIR6: DIRP19 Mask */ -#define GPIO_PORT_DIR6_DIRP20_Pos 20 /*!< GPIO_PORT DIR6: DIRP20 Position */ -#define GPIO_PORT_DIR6_DIRP20_Msk (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos) /*!< GPIO_PORT DIR6: DIRP20 Mask */ -#define GPIO_PORT_DIR6_DIRP21_Pos 21 /*!< GPIO_PORT DIR6: DIRP21 Position */ -#define GPIO_PORT_DIR6_DIRP21_Msk (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos) /*!< GPIO_PORT DIR6: DIRP21 Mask */ -#define GPIO_PORT_DIR6_DIRP22_Pos 22 /*!< GPIO_PORT DIR6: DIRP22 Position */ -#define GPIO_PORT_DIR6_DIRP22_Msk (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos) /*!< GPIO_PORT DIR6: DIRP22 Mask */ -#define GPIO_PORT_DIR6_DIRP23_Pos 23 /*!< GPIO_PORT DIR6: DIRP23 Position */ -#define GPIO_PORT_DIR6_DIRP23_Msk (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos) /*!< GPIO_PORT DIR6: DIRP23 Mask */ -#define GPIO_PORT_DIR6_DIRP24_Pos 24 /*!< GPIO_PORT DIR6: DIRP24 Position */ -#define GPIO_PORT_DIR6_DIRP24_Msk (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos) /*!< GPIO_PORT DIR6: DIRP24 Mask */ -#define GPIO_PORT_DIR6_DIRP25_Pos 25 /*!< GPIO_PORT DIR6: DIRP25 Position */ -#define GPIO_PORT_DIR6_DIRP25_Msk (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos) /*!< GPIO_PORT DIR6: DIRP25 Mask */ -#define GPIO_PORT_DIR6_DIRP26_Pos 26 /*!< GPIO_PORT DIR6: DIRP26 Position */ -#define GPIO_PORT_DIR6_DIRP26_Msk (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos) /*!< GPIO_PORT DIR6: DIRP26 Mask */ -#define GPIO_PORT_DIR6_DIRP27_Pos 27 /*!< GPIO_PORT DIR6: DIRP27 Position */ -#define GPIO_PORT_DIR6_DIRP27_Msk (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos) /*!< GPIO_PORT DIR6: DIRP27 Mask */ -#define GPIO_PORT_DIR6_DIRP28_Pos 28 /*!< GPIO_PORT DIR6: DIRP28 Position */ -#define GPIO_PORT_DIR6_DIRP28_Msk (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos) /*!< GPIO_PORT DIR6: DIRP28 Mask */ -#define GPIO_PORT_DIR6_DIRP29_Pos 29 /*!< GPIO_PORT DIR6: DIRP29 Position */ -#define GPIO_PORT_DIR6_DIRP29_Msk (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos) /*!< GPIO_PORT DIR6: DIRP29 Mask */ -#define GPIO_PORT_DIR6_DIRP30_Pos 30 /*!< GPIO_PORT DIR6: DIRP30 Position */ -#define GPIO_PORT_DIR6_DIRP30_Msk (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos) /*!< GPIO_PORT DIR6: DIRP30 Mask */ -#define GPIO_PORT_DIR6_DIRP31_Pos 31 /*!< GPIO_PORT DIR6: DIRP31 Position */ -#define GPIO_PORT_DIR6_DIRP31_Msk (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos) /*!< GPIO_PORT DIR6: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR7 ----------------------------------------- -#define GPIO_PORT_DIR7_DIRP0_Pos 0 /*!< GPIO_PORT DIR7: DIRP0 Position */ -#define GPIO_PORT_DIR7_DIRP0_Msk (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos) /*!< GPIO_PORT DIR7: DIRP0 Mask */ -#define GPIO_PORT_DIR7_DIRP1_Pos 1 /*!< GPIO_PORT DIR7: DIRP1 Position */ -#define GPIO_PORT_DIR7_DIRP1_Msk (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos) /*!< GPIO_PORT DIR7: DIRP1 Mask */ -#define GPIO_PORT_DIR7_DIRP2_Pos 2 /*!< GPIO_PORT DIR7: DIRP2 Position */ -#define GPIO_PORT_DIR7_DIRP2_Msk (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos) /*!< GPIO_PORT DIR7: DIRP2 Mask */ -#define GPIO_PORT_DIR7_DIRP3_Pos 3 /*!< GPIO_PORT DIR7: DIRP3 Position */ -#define GPIO_PORT_DIR7_DIRP3_Msk (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos) /*!< GPIO_PORT DIR7: DIRP3 Mask */ -#define GPIO_PORT_DIR7_DIRP4_Pos 4 /*!< GPIO_PORT DIR7: DIRP4 Position */ -#define GPIO_PORT_DIR7_DIRP4_Msk (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos) /*!< GPIO_PORT DIR7: DIRP4 Mask */ -#define GPIO_PORT_DIR7_DIRP5_Pos 5 /*!< GPIO_PORT DIR7: DIRP5 Position */ -#define GPIO_PORT_DIR7_DIRP5_Msk (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos) /*!< GPIO_PORT DIR7: DIRP5 Mask */ -#define GPIO_PORT_DIR7_DIRP6_Pos 6 /*!< GPIO_PORT DIR7: DIRP6 Position */ -#define GPIO_PORT_DIR7_DIRP6_Msk (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos) /*!< GPIO_PORT DIR7: DIRP6 Mask */ -#define GPIO_PORT_DIR7_DIRP7_Pos 7 /*!< GPIO_PORT DIR7: DIRP7 Position */ -#define GPIO_PORT_DIR7_DIRP7_Msk (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos) /*!< GPIO_PORT DIR7: DIRP7 Mask */ -#define GPIO_PORT_DIR7_DIRP8_Pos 8 /*!< GPIO_PORT DIR7: DIRP8 Position */ -#define GPIO_PORT_DIR7_DIRP8_Msk (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos) /*!< GPIO_PORT DIR7: DIRP8 Mask */ -#define GPIO_PORT_DIR7_DIRP9_Pos 9 /*!< GPIO_PORT DIR7: DIRP9 Position */ -#define GPIO_PORT_DIR7_DIRP9_Msk (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos) /*!< GPIO_PORT DIR7: DIRP9 Mask */ -#define GPIO_PORT_DIR7_DIRP10_Pos 10 /*!< GPIO_PORT DIR7: DIRP10 Position */ -#define GPIO_PORT_DIR7_DIRP10_Msk (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos) /*!< GPIO_PORT DIR7: DIRP10 Mask */ -#define GPIO_PORT_DIR7_DIRP11_Pos 11 /*!< GPIO_PORT DIR7: DIRP11 Position */ -#define GPIO_PORT_DIR7_DIRP11_Msk (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos) /*!< GPIO_PORT DIR7: DIRP11 Mask */ -#define GPIO_PORT_DIR7_DIRP12_Pos 12 /*!< GPIO_PORT DIR7: DIRP12 Position */ -#define GPIO_PORT_DIR7_DIRP12_Msk (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos) /*!< GPIO_PORT DIR7: DIRP12 Mask */ -#define GPIO_PORT_DIR7_DIRP13_Pos 13 /*!< GPIO_PORT DIR7: DIRP13 Position */ -#define GPIO_PORT_DIR7_DIRP13_Msk (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos) /*!< GPIO_PORT DIR7: DIRP13 Mask */ -#define GPIO_PORT_DIR7_DIRP14_Pos 14 /*!< GPIO_PORT DIR7: DIRP14 Position */ -#define GPIO_PORT_DIR7_DIRP14_Msk (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos) /*!< GPIO_PORT DIR7: DIRP14 Mask */ -#define GPIO_PORT_DIR7_DIRP15_Pos 15 /*!< GPIO_PORT DIR7: DIRP15 Position */ -#define GPIO_PORT_DIR7_DIRP15_Msk (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos) /*!< GPIO_PORT DIR7: DIRP15 Mask */ -#define GPIO_PORT_DIR7_DIRP16_Pos 16 /*!< GPIO_PORT DIR7: DIRP16 Position */ -#define GPIO_PORT_DIR7_DIRP16_Msk (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos) /*!< GPIO_PORT DIR7: DIRP16 Mask */ -#define GPIO_PORT_DIR7_DIRP17_Pos 17 /*!< GPIO_PORT DIR7: DIRP17 Position */ -#define GPIO_PORT_DIR7_DIRP17_Msk (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos) /*!< GPIO_PORT DIR7: DIRP17 Mask */ -#define GPIO_PORT_DIR7_DIRP18_Pos 18 /*!< GPIO_PORT DIR7: DIRP18 Position */ -#define GPIO_PORT_DIR7_DIRP18_Msk (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos) /*!< GPIO_PORT DIR7: DIRP18 Mask */ -#define GPIO_PORT_DIR7_DIRP19_Pos 19 /*!< GPIO_PORT DIR7: DIRP19 Position */ -#define GPIO_PORT_DIR7_DIRP19_Msk (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos) /*!< GPIO_PORT DIR7: DIRP19 Mask */ -#define GPIO_PORT_DIR7_DIRP20_Pos 20 /*!< GPIO_PORT DIR7: DIRP20 Position */ -#define GPIO_PORT_DIR7_DIRP20_Msk (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos) /*!< GPIO_PORT DIR7: DIRP20 Mask */ -#define GPIO_PORT_DIR7_DIRP21_Pos 21 /*!< GPIO_PORT DIR7: DIRP21 Position */ -#define GPIO_PORT_DIR7_DIRP21_Msk (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos) /*!< GPIO_PORT DIR7: DIRP21 Mask */ -#define GPIO_PORT_DIR7_DIRP22_Pos 22 /*!< GPIO_PORT DIR7: DIRP22 Position */ -#define GPIO_PORT_DIR7_DIRP22_Msk (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos) /*!< GPIO_PORT DIR7: DIRP22 Mask */ -#define GPIO_PORT_DIR7_DIRP23_Pos 23 /*!< GPIO_PORT DIR7: DIRP23 Position */ -#define GPIO_PORT_DIR7_DIRP23_Msk (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos) /*!< GPIO_PORT DIR7: DIRP23 Mask */ -#define GPIO_PORT_DIR7_DIRP24_Pos 24 /*!< GPIO_PORT DIR7: DIRP24 Position */ -#define GPIO_PORT_DIR7_DIRP24_Msk (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos) /*!< GPIO_PORT DIR7: DIRP24 Mask */ -#define GPIO_PORT_DIR7_DIRP25_Pos 25 /*!< GPIO_PORT DIR7: DIRP25 Position */ -#define GPIO_PORT_DIR7_DIRP25_Msk (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos) /*!< GPIO_PORT DIR7: DIRP25 Mask */ -#define GPIO_PORT_DIR7_DIRP26_Pos 26 /*!< GPIO_PORT DIR7: DIRP26 Position */ -#define GPIO_PORT_DIR7_DIRP26_Msk (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos) /*!< GPIO_PORT DIR7: DIRP26 Mask */ -#define GPIO_PORT_DIR7_DIRP27_Pos 27 /*!< GPIO_PORT DIR7: DIRP27 Position */ -#define GPIO_PORT_DIR7_DIRP27_Msk (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos) /*!< GPIO_PORT DIR7: DIRP27 Mask */ -#define GPIO_PORT_DIR7_DIRP28_Pos 28 /*!< GPIO_PORT DIR7: DIRP28 Position */ -#define GPIO_PORT_DIR7_DIRP28_Msk (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos) /*!< GPIO_PORT DIR7: DIRP28 Mask */ -#define GPIO_PORT_DIR7_DIRP29_Pos 29 /*!< GPIO_PORT DIR7: DIRP29 Position */ -#define GPIO_PORT_DIR7_DIRP29_Msk (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos) /*!< GPIO_PORT DIR7: DIRP29 Mask */ -#define GPIO_PORT_DIR7_DIRP30_Pos 30 /*!< GPIO_PORT DIR7: DIRP30 Position */ -#define GPIO_PORT_DIR7_DIRP30_Msk (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos) /*!< GPIO_PORT DIR7: DIRP30 Mask */ -#define GPIO_PORT_DIR7_DIRP31_Pos 31 /*!< GPIO_PORT DIR7: DIRP31 Position */ -#define GPIO_PORT_DIR7_DIRP31_Msk (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos) /*!< GPIO_PORT DIR7: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK0 ---------------------------------------- -#define GPIO_PORT_MASK0_MASKP0_Pos 0 /*!< GPIO_PORT MASK0: MASKP0 Position */ -#define GPIO_PORT_MASK0_MASKP0_Msk (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos) /*!< GPIO_PORT MASK0: MASKP0 Mask */ -#define GPIO_PORT_MASK0_MASKP1_Pos 1 /*!< GPIO_PORT MASK0: MASKP1 Position */ -#define GPIO_PORT_MASK0_MASKP1_Msk (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos) /*!< GPIO_PORT MASK0: MASKP1 Mask */ -#define GPIO_PORT_MASK0_MASKP2_Pos 2 /*!< GPIO_PORT MASK0: MASKP2 Position */ -#define GPIO_PORT_MASK0_MASKP2_Msk (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos) /*!< GPIO_PORT MASK0: MASKP2 Mask */ -#define GPIO_PORT_MASK0_MASKP3_Pos 3 /*!< GPIO_PORT MASK0: MASKP3 Position */ -#define GPIO_PORT_MASK0_MASKP3_Msk (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos) /*!< GPIO_PORT MASK0: MASKP3 Mask */ -#define GPIO_PORT_MASK0_MASKP4_Pos 4 /*!< GPIO_PORT MASK0: MASKP4 Position */ -#define GPIO_PORT_MASK0_MASKP4_Msk (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos) /*!< GPIO_PORT MASK0: MASKP4 Mask */ -#define GPIO_PORT_MASK0_MASKP5_Pos 5 /*!< GPIO_PORT MASK0: MASKP5 Position */ -#define GPIO_PORT_MASK0_MASKP5_Msk (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos) /*!< GPIO_PORT MASK0: MASKP5 Mask */ -#define GPIO_PORT_MASK0_MASKP6_Pos 6 /*!< GPIO_PORT MASK0: MASKP6 Position */ -#define GPIO_PORT_MASK0_MASKP6_Msk (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos) /*!< GPIO_PORT MASK0: MASKP6 Mask */ -#define GPIO_PORT_MASK0_MASKP7_Pos 7 /*!< GPIO_PORT MASK0: MASKP7 Position */ -#define GPIO_PORT_MASK0_MASKP7_Msk (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos) /*!< GPIO_PORT MASK0: MASKP7 Mask */ -#define GPIO_PORT_MASK0_MASKP8_Pos 8 /*!< GPIO_PORT MASK0: MASKP8 Position */ -#define GPIO_PORT_MASK0_MASKP8_Msk (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos) /*!< GPIO_PORT MASK0: MASKP8 Mask */ -#define GPIO_PORT_MASK0_MASKP9_Pos 9 /*!< GPIO_PORT MASK0: MASKP9 Position */ -#define GPIO_PORT_MASK0_MASKP9_Msk (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos) /*!< GPIO_PORT MASK0: MASKP9 Mask */ -#define GPIO_PORT_MASK0_MASKP10_Pos 10 /*!< GPIO_PORT MASK0: MASKP10 Position */ -#define GPIO_PORT_MASK0_MASKP10_Msk (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos) /*!< GPIO_PORT MASK0: MASKP10 Mask */ -#define GPIO_PORT_MASK0_MASKP11_Pos 11 /*!< GPIO_PORT MASK0: MASKP11 Position */ -#define GPIO_PORT_MASK0_MASKP11_Msk (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos) /*!< GPIO_PORT MASK0: MASKP11 Mask */ -#define GPIO_PORT_MASK0_MASKP12_Pos 12 /*!< GPIO_PORT MASK0: MASKP12 Position */ -#define GPIO_PORT_MASK0_MASKP12_Msk (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos) /*!< GPIO_PORT MASK0: MASKP12 Mask */ -#define GPIO_PORT_MASK0_MASKP13_Pos 13 /*!< GPIO_PORT MASK0: MASKP13 Position */ -#define GPIO_PORT_MASK0_MASKP13_Msk (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos) /*!< GPIO_PORT MASK0: MASKP13 Mask */ -#define GPIO_PORT_MASK0_MASKP14_Pos 14 /*!< GPIO_PORT MASK0: MASKP14 Position */ -#define GPIO_PORT_MASK0_MASKP14_Msk (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos) /*!< GPIO_PORT MASK0: MASKP14 Mask */ -#define GPIO_PORT_MASK0_MASKP15_Pos 15 /*!< GPIO_PORT MASK0: MASKP15 Position */ -#define GPIO_PORT_MASK0_MASKP15_Msk (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos) /*!< GPIO_PORT MASK0: MASKP15 Mask */ -#define GPIO_PORT_MASK0_MASKP16_Pos 16 /*!< GPIO_PORT MASK0: MASKP16 Position */ -#define GPIO_PORT_MASK0_MASKP16_Msk (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos) /*!< GPIO_PORT MASK0: MASKP16 Mask */ -#define GPIO_PORT_MASK0_MASKP17_Pos 17 /*!< GPIO_PORT MASK0: MASKP17 Position */ -#define GPIO_PORT_MASK0_MASKP17_Msk (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos) /*!< GPIO_PORT MASK0: MASKP17 Mask */ -#define GPIO_PORT_MASK0_MASKP18_Pos 18 /*!< GPIO_PORT MASK0: MASKP18 Position */ -#define GPIO_PORT_MASK0_MASKP18_Msk (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos) /*!< GPIO_PORT MASK0: MASKP18 Mask */ -#define GPIO_PORT_MASK0_MASKP19_Pos 19 /*!< GPIO_PORT MASK0: MASKP19 Position */ -#define GPIO_PORT_MASK0_MASKP19_Msk (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos) /*!< GPIO_PORT MASK0: MASKP19 Mask */ -#define GPIO_PORT_MASK0_MASKP20_Pos 20 /*!< GPIO_PORT MASK0: MASKP20 Position */ -#define GPIO_PORT_MASK0_MASKP20_Msk (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos) /*!< GPIO_PORT MASK0: MASKP20 Mask */ -#define GPIO_PORT_MASK0_MASKP21_Pos 21 /*!< GPIO_PORT MASK0: MASKP21 Position */ -#define GPIO_PORT_MASK0_MASKP21_Msk (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos) /*!< GPIO_PORT MASK0: MASKP21 Mask */ -#define GPIO_PORT_MASK0_MASKP22_Pos 22 /*!< GPIO_PORT MASK0: MASKP22 Position */ -#define GPIO_PORT_MASK0_MASKP22_Msk (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos) /*!< GPIO_PORT MASK0: MASKP22 Mask */ -#define GPIO_PORT_MASK0_MASKP23_Pos 23 /*!< GPIO_PORT MASK0: MASKP23 Position */ -#define GPIO_PORT_MASK0_MASKP23_Msk (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos) /*!< GPIO_PORT MASK0: MASKP23 Mask */ -#define GPIO_PORT_MASK0_MASKP24_Pos 24 /*!< GPIO_PORT MASK0: MASKP24 Position */ -#define GPIO_PORT_MASK0_MASKP24_Msk (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos) /*!< GPIO_PORT MASK0: MASKP24 Mask */ -#define GPIO_PORT_MASK0_MASKP25_Pos 25 /*!< GPIO_PORT MASK0: MASKP25 Position */ -#define GPIO_PORT_MASK0_MASKP25_Msk (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos) /*!< GPIO_PORT MASK0: MASKP25 Mask */ -#define GPIO_PORT_MASK0_MASKP26_Pos 26 /*!< GPIO_PORT MASK0: MASKP26 Position */ -#define GPIO_PORT_MASK0_MASKP26_Msk (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos) /*!< GPIO_PORT MASK0: MASKP26 Mask */ -#define GPIO_PORT_MASK0_MASKP27_Pos 27 /*!< GPIO_PORT MASK0: MASKP27 Position */ -#define GPIO_PORT_MASK0_MASKP27_Msk (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos) /*!< GPIO_PORT MASK0: MASKP27 Mask */ -#define GPIO_PORT_MASK0_MASKP28_Pos 28 /*!< GPIO_PORT MASK0: MASKP28 Position */ -#define GPIO_PORT_MASK0_MASKP28_Msk (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos) /*!< GPIO_PORT MASK0: MASKP28 Mask */ -#define GPIO_PORT_MASK0_MASKP29_Pos 29 /*!< GPIO_PORT MASK0: MASKP29 Position */ -#define GPIO_PORT_MASK0_MASKP29_Msk (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos) /*!< GPIO_PORT MASK0: MASKP29 Mask */ -#define GPIO_PORT_MASK0_MASKP30_Pos 30 /*!< GPIO_PORT MASK0: MASKP30 Position */ -#define GPIO_PORT_MASK0_MASKP30_Msk (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos) /*!< GPIO_PORT MASK0: MASKP30 Mask */ -#define GPIO_PORT_MASK0_MASKP31_Pos 31 /*!< GPIO_PORT MASK0: MASKP31 Position */ -#define GPIO_PORT_MASK0_MASKP31_Msk (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos) /*!< GPIO_PORT MASK0: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK1 ---------------------------------------- -#define GPIO_PORT_MASK1_MASKP0_Pos 0 /*!< GPIO_PORT MASK1: MASKP0 Position */ -#define GPIO_PORT_MASK1_MASKP0_Msk (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos) /*!< GPIO_PORT MASK1: MASKP0 Mask */ -#define GPIO_PORT_MASK1_MASKP1_Pos 1 /*!< GPIO_PORT MASK1: MASKP1 Position */ -#define GPIO_PORT_MASK1_MASKP1_Msk (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos) /*!< GPIO_PORT MASK1: MASKP1 Mask */ -#define GPIO_PORT_MASK1_MASKP2_Pos 2 /*!< GPIO_PORT MASK1: MASKP2 Position */ -#define GPIO_PORT_MASK1_MASKP2_Msk (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos) /*!< GPIO_PORT MASK1: MASKP2 Mask */ -#define GPIO_PORT_MASK1_MASKP3_Pos 3 /*!< GPIO_PORT MASK1: MASKP3 Position */ -#define GPIO_PORT_MASK1_MASKP3_Msk (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos) /*!< GPIO_PORT MASK1: MASKP3 Mask */ -#define GPIO_PORT_MASK1_MASKP4_Pos 4 /*!< GPIO_PORT MASK1: MASKP4 Position */ -#define GPIO_PORT_MASK1_MASKP4_Msk (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos) /*!< GPIO_PORT MASK1: MASKP4 Mask */ -#define GPIO_PORT_MASK1_MASKP5_Pos 5 /*!< GPIO_PORT MASK1: MASKP5 Position */ -#define GPIO_PORT_MASK1_MASKP5_Msk (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos) /*!< GPIO_PORT MASK1: MASKP5 Mask */ -#define GPIO_PORT_MASK1_MASKP6_Pos 6 /*!< GPIO_PORT MASK1: MASKP6 Position */ -#define GPIO_PORT_MASK1_MASKP6_Msk (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos) /*!< GPIO_PORT MASK1: MASKP6 Mask */ -#define GPIO_PORT_MASK1_MASKP7_Pos 7 /*!< GPIO_PORT MASK1: MASKP7 Position */ -#define GPIO_PORT_MASK1_MASKP7_Msk (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos) /*!< GPIO_PORT MASK1: MASKP7 Mask */ -#define GPIO_PORT_MASK1_MASKP8_Pos 8 /*!< GPIO_PORT MASK1: MASKP8 Position */ -#define GPIO_PORT_MASK1_MASKP8_Msk (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos) /*!< GPIO_PORT MASK1: MASKP8 Mask */ -#define GPIO_PORT_MASK1_MASKP9_Pos 9 /*!< GPIO_PORT MASK1: MASKP9 Position */ -#define GPIO_PORT_MASK1_MASKP9_Msk (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos) /*!< GPIO_PORT MASK1: MASKP9 Mask */ -#define GPIO_PORT_MASK1_MASKP10_Pos 10 /*!< GPIO_PORT MASK1: MASKP10 Position */ -#define GPIO_PORT_MASK1_MASKP10_Msk (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos) /*!< GPIO_PORT MASK1: MASKP10 Mask */ -#define GPIO_PORT_MASK1_MASKP11_Pos 11 /*!< GPIO_PORT MASK1: MASKP11 Position */ -#define GPIO_PORT_MASK1_MASKP11_Msk (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos) /*!< GPIO_PORT MASK1: MASKP11 Mask */ -#define GPIO_PORT_MASK1_MASKP12_Pos 12 /*!< GPIO_PORT MASK1: MASKP12 Position */ -#define GPIO_PORT_MASK1_MASKP12_Msk (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos) /*!< GPIO_PORT MASK1: MASKP12 Mask */ -#define GPIO_PORT_MASK1_MASKP13_Pos 13 /*!< GPIO_PORT MASK1: MASKP13 Position */ -#define GPIO_PORT_MASK1_MASKP13_Msk (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos) /*!< GPIO_PORT MASK1: MASKP13 Mask */ -#define GPIO_PORT_MASK1_MASKP14_Pos 14 /*!< GPIO_PORT MASK1: MASKP14 Position */ -#define GPIO_PORT_MASK1_MASKP14_Msk (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos) /*!< GPIO_PORT MASK1: MASKP14 Mask */ -#define GPIO_PORT_MASK1_MASKP15_Pos 15 /*!< GPIO_PORT MASK1: MASKP15 Position */ -#define GPIO_PORT_MASK1_MASKP15_Msk (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos) /*!< GPIO_PORT MASK1: MASKP15 Mask */ -#define GPIO_PORT_MASK1_MASKP16_Pos 16 /*!< GPIO_PORT MASK1: MASKP16 Position */ -#define GPIO_PORT_MASK1_MASKP16_Msk (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos) /*!< GPIO_PORT MASK1: MASKP16 Mask */ -#define GPIO_PORT_MASK1_MASKP17_Pos 17 /*!< GPIO_PORT MASK1: MASKP17 Position */ -#define GPIO_PORT_MASK1_MASKP17_Msk (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos) /*!< GPIO_PORT MASK1: MASKP17 Mask */ -#define GPIO_PORT_MASK1_MASKP18_Pos 18 /*!< GPIO_PORT MASK1: MASKP18 Position */ -#define GPIO_PORT_MASK1_MASKP18_Msk (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos) /*!< GPIO_PORT MASK1: MASKP18 Mask */ -#define GPIO_PORT_MASK1_MASKP19_Pos 19 /*!< GPIO_PORT MASK1: MASKP19 Position */ -#define GPIO_PORT_MASK1_MASKP19_Msk (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos) /*!< GPIO_PORT MASK1: MASKP19 Mask */ -#define GPIO_PORT_MASK1_MASKP20_Pos 20 /*!< GPIO_PORT MASK1: MASKP20 Position */ -#define GPIO_PORT_MASK1_MASKP20_Msk (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos) /*!< GPIO_PORT MASK1: MASKP20 Mask */ -#define GPIO_PORT_MASK1_MASKP21_Pos 21 /*!< GPIO_PORT MASK1: MASKP21 Position */ -#define GPIO_PORT_MASK1_MASKP21_Msk (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos) /*!< GPIO_PORT MASK1: MASKP21 Mask */ -#define GPIO_PORT_MASK1_MASKP22_Pos 22 /*!< GPIO_PORT MASK1: MASKP22 Position */ -#define GPIO_PORT_MASK1_MASKP22_Msk (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos) /*!< GPIO_PORT MASK1: MASKP22 Mask */ -#define GPIO_PORT_MASK1_MASKP23_Pos 23 /*!< GPIO_PORT MASK1: MASKP23 Position */ -#define GPIO_PORT_MASK1_MASKP23_Msk (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos) /*!< GPIO_PORT MASK1: MASKP23 Mask */ -#define GPIO_PORT_MASK1_MASKP24_Pos 24 /*!< GPIO_PORT MASK1: MASKP24 Position */ -#define GPIO_PORT_MASK1_MASKP24_Msk (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos) /*!< GPIO_PORT MASK1: MASKP24 Mask */ -#define GPIO_PORT_MASK1_MASKP25_Pos 25 /*!< GPIO_PORT MASK1: MASKP25 Position */ -#define GPIO_PORT_MASK1_MASKP25_Msk (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos) /*!< GPIO_PORT MASK1: MASKP25 Mask */ -#define GPIO_PORT_MASK1_MASKP26_Pos 26 /*!< GPIO_PORT MASK1: MASKP26 Position */ -#define GPIO_PORT_MASK1_MASKP26_Msk (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos) /*!< GPIO_PORT MASK1: MASKP26 Mask */ -#define GPIO_PORT_MASK1_MASKP27_Pos 27 /*!< GPIO_PORT MASK1: MASKP27 Position */ -#define GPIO_PORT_MASK1_MASKP27_Msk (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos) /*!< GPIO_PORT MASK1: MASKP27 Mask */ -#define GPIO_PORT_MASK1_MASKP28_Pos 28 /*!< GPIO_PORT MASK1: MASKP28 Position */ -#define GPIO_PORT_MASK1_MASKP28_Msk (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos) /*!< GPIO_PORT MASK1: MASKP28 Mask */ -#define GPIO_PORT_MASK1_MASKP29_Pos 29 /*!< GPIO_PORT MASK1: MASKP29 Position */ -#define GPIO_PORT_MASK1_MASKP29_Msk (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos) /*!< GPIO_PORT MASK1: MASKP29 Mask */ -#define GPIO_PORT_MASK1_MASKP30_Pos 30 /*!< GPIO_PORT MASK1: MASKP30 Position */ -#define GPIO_PORT_MASK1_MASKP30_Msk (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos) /*!< GPIO_PORT MASK1: MASKP30 Mask */ -#define GPIO_PORT_MASK1_MASKP31_Pos 31 /*!< GPIO_PORT MASK1: MASKP31 Position */ -#define GPIO_PORT_MASK1_MASKP31_Msk (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos) /*!< GPIO_PORT MASK1: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK2 ---------------------------------------- -#define GPIO_PORT_MASK2_MASKP0_Pos 0 /*!< GPIO_PORT MASK2: MASKP0 Position */ -#define GPIO_PORT_MASK2_MASKP0_Msk (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos) /*!< GPIO_PORT MASK2: MASKP0 Mask */ -#define GPIO_PORT_MASK2_MASKP1_Pos 1 /*!< GPIO_PORT MASK2: MASKP1 Position */ -#define GPIO_PORT_MASK2_MASKP1_Msk (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos) /*!< GPIO_PORT MASK2: MASKP1 Mask */ -#define GPIO_PORT_MASK2_MASKP2_Pos 2 /*!< GPIO_PORT MASK2: MASKP2 Position */ -#define GPIO_PORT_MASK2_MASKP2_Msk (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos) /*!< GPIO_PORT MASK2: MASKP2 Mask */ -#define GPIO_PORT_MASK2_MASKP3_Pos 3 /*!< GPIO_PORT MASK2: MASKP3 Position */ -#define GPIO_PORT_MASK2_MASKP3_Msk (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos) /*!< GPIO_PORT MASK2: MASKP3 Mask */ -#define GPIO_PORT_MASK2_MASKP4_Pos 4 /*!< GPIO_PORT MASK2: MASKP4 Position */ -#define GPIO_PORT_MASK2_MASKP4_Msk (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos) /*!< GPIO_PORT MASK2: MASKP4 Mask */ -#define GPIO_PORT_MASK2_MASKP5_Pos 5 /*!< GPIO_PORT MASK2: MASKP5 Position */ -#define GPIO_PORT_MASK2_MASKP5_Msk (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos) /*!< GPIO_PORT MASK2: MASKP5 Mask */ -#define GPIO_PORT_MASK2_MASKP6_Pos 6 /*!< GPIO_PORT MASK2: MASKP6 Position */ -#define GPIO_PORT_MASK2_MASKP6_Msk (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos) /*!< GPIO_PORT MASK2: MASKP6 Mask */ -#define GPIO_PORT_MASK2_MASKP7_Pos 7 /*!< GPIO_PORT MASK2: MASKP7 Position */ -#define GPIO_PORT_MASK2_MASKP7_Msk (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos) /*!< GPIO_PORT MASK2: MASKP7 Mask */ -#define GPIO_PORT_MASK2_MASKP8_Pos 8 /*!< GPIO_PORT MASK2: MASKP8 Position */ -#define GPIO_PORT_MASK2_MASKP8_Msk (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos) /*!< GPIO_PORT MASK2: MASKP8 Mask */ -#define GPIO_PORT_MASK2_MASKP9_Pos 9 /*!< GPIO_PORT MASK2: MASKP9 Position */ -#define GPIO_PORT_MASK2_MASKP9_Msk (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos) /*!< GPIO_PORT MASK2: MASKP9 Mask */ -#define GPIO_PORT_MASK2_MASKP10_Pos 10 /*!< GPIO_PORT MASK2: MASKP10 Position */ -#define GPIO_PORT_MASK2_MASKP10_Msk (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos) /*!< GPIO_PORT MASK2: MASKP10 Mask */ -#define GPIO_PORT_MASK2_MASKP11_Pos 11 /*!< GPIO_PORT MASK2: MASKP11 Position */ -#define GPIO_PORT_MASK2_MASKP11_Msk (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos) /*!< GPIO_PORT MASK2: MASKP11 Mask */ -#define GPIO_PORT_MASK2_MASKP12_Pos 12 /*!< GPIO_PORT MASK2: MASKP12 Position */ -#define GPIO_PORT_MASK2_MASKP12_Msk (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos) /*!< GPIO_PORT MASK2: MASKP12 Mask */ -#define GPIO_PORT_MASK2_MASKP13_Pos 13 /*!< GPIO_PORT MASK2: MASKP13 Position */ -#define GPIO_PORT_MASK2_MASKP13_Msk (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos) /*!< GPIO_PORT MASK2: MASKP13 Mask */ -#define GPIO_PORT_MASK2_MASKP14_Pos 14 /*!< GPIO_PORT MASK2: MASKP14 Position */ -#define GPIO_PORT_MASK2_MASKP14_Msk (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos) /*!< GPIO_PORT MASK2: MASKP14 Mask */ -#define GPIO_PORT_MASK2_MASKP15_Pos 15 /*!< GPIO_PORT MASK2: MASKP15 Position */ -#define GPIO_PORT_MASK2_MASKP15_Msk (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos) /*!< GPIO_PORT MASK2: MASKP15 Mask */ -#define GPIO_PORT_MASK2_MASKP16_Pos 16 /*!< GPIO_PORT MASK2: MASKP16 Position */ -#define GPIO_PORT_MASK2_MASKP16_Msk (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos) /*!< GPIO_PORT MASK2: MASKP16 Mask */ -#define GPIO_PORT_MASK2_MASKP17_Pos 17 /*!< GPIO_PORT MASK2: MASKP17 Position */ -#define GPIO_PORT_MASK2_MASKP17_Msk (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos) /*!< GPIO_PORT MASK2: MASKP17 Mask */ -#define GPIO_PORT_MASK2_MASKP18_Pos 18 /*!< GPIO_PORT MASK2: MASKP18 Position */ -#define GPIO_PORT_MASK2_MASKP18_Msk (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos) /*!< GPIO_PORT MASK2: MASKP18 Mask */ -#define GPIO_PORT_MASK2_MASKP19_Pos 19 /*!< GPIO_PORT MASK2: MASKP19 Position */ -#define GPIO_PORT_MASK2_MASKP19_Msk (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos) /*!< GPIO_PORT MASK2: MASKP19 Mask */ -#define GPIO_PORT_MASK2_MASKP20_Pos 20 /*!< GPIO_PORT MASK2: MASKP20 Position */ -#define GPIO_PORT_MASK2_MASKP20_Msk (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos) /*!< GPIO_PORT MASK2: MASKP20 Mask */ -#define GPIO_PORT_MASK2_MASKP21_Pos 21 /*!< GPIO_PORT MASK2: MASKP21 Position */ -#define GPIO_PORT_MASK2_MASKP21_Msk (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos) /*!< GPIO_PORT MASK2: MASKP21 Mask */ -#define GPIO_PORT_MASK2_MASKP22_Pos 22 /*!< GPIO_PORT MASK2: MASKP22 Position */ -#define GPIO_PORT_MASK2_MASKP22_Msk (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos) /*!< GPIO_PORT MASK2: MASKP22 Mask */ -#define GPIO_PORT_MASK2_MASKP23_Pos 23 /*!< GPIO_PORT MASK2: MASKP23 Position */ -#define GPIO_PORT_MASK2_MASKP23_Msk (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos) /*!< GPIO_PORT MASK2: MASKP23 Mask */ -#define GPIO_PORT_MASK2_MASKP24_Pos 24 /*!< GPIO_PORT MASK2: MASKP24 Position */ -#define GPIO_PORT_MASK2_MASKP24_Msk (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos) /*!< GPIO_PORT MASK2: MASKP24 Mask */ -#define GPIO_PORT_MASK2_MASKP25_Pos 25 /*!< GPIO_PORT MASK2: MASKP25 Position */ -#define GPIO_PORT_MASK2_MASKP25_Msk (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos) /*!< GPIO_PORT MASK2: MASKP25 Mask */ -#define GPIO_PORT_MASK2_MASKP26_Pos 26 /*!< GPIO_PORT MASK2: MASKP26 Position */ -#define GPIO_PORT_MASK2_MASKP26_Msk (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos) /*!< GPIO_PORT MASK2: MASKP26 Mask */ -#define GPIO_PORT_MASK2_MASKP27_Pos 27 /*!< GPIO_PORT MASK2: MASKP27 Position */ -#define GPIO_PORT_MASK2_MASKP27_Msk (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos) /*!< GPIO_PORT MASK2: MASKP27 Mask */ -#define GPIO_PORT_MASK2_MASKP28_Pos 28 /*!< GPIO_PORT MASK2: MASKP28 Position */ -#define GPIO_PORT_MASK2_MASKP28_Msk (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos) /*!< GPIO_PORT MASK2: MASKP28 Mask */ -#define GPIO_PORT_MASK2_MASKP29_Pos 29 /*!< GPIO_PORT MASK2: MASKP29 Position */ -#define GPIO_PORT_MASK2_MASKP29_Msk (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos) /*!< GPIO_PORT MASK2: MASKP29 Mask */ -#define GPIO_PORT_MASK2_MASKP30_Pos 30 /*!< GPIO_PORT MASK2: MASKP30 Position */ -#define GPIO_PORT_MASK2_MASKP30_Msk (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos) /*!< GPIO_PORT MASK2: MASKP30 Mask */ -#define GPIO_PORT_MASK2_MASKP31_Pos 31 /*!< GPIO_PORT MASK2: MASKP31 Position */ -#define GPIO_PORT_MASK2_MASKP31_Msk (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos) /*!< GPIO_PORT MASK2: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK3 ---------------------------------------- -#define GPIO_PORT_MASK3_MASKP0_Pos 0 /*!< GPIO_PORT MASK3: MASKP0 Position */ -#define GPIO_PORT_MASK3_MASKP0_Msk (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos) /*!< GPIO_PORT MASK3: MASKP0 Mask */ -#define GPIO_PORT_MASK3_MASKP1_Pos 1 /*!< GPIO_PORT MASK3: MASKP1 Position */ -#define GPIO_PORT_MASK3_MASKP1_Msk (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos) /*!< GPIO_PORT MASK3: MASKP1 Mask */ -#define GPIO_PORT_MASK3_MASKP2_Pos 2 /*!< GPIO_PORT MASK3: MASKP2 Position */ -#define GPIO_PORT_MASK3_MASKP2_Msk (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos) /*!< GPIO_PORT MASK3: MASKP2 Mask */ -#define GPIO_PORT_MASK3_MASKP3_Pos 3 /*!< GPIO_PORT MASK3: MASKP3 Position */ -#define GPIO_PORT_MASK3_MASKP3_Msk (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos) /*!< GPIO_PORT MASK3: MASKP3 Mask */ -#define GPIO_PORT_MASK3_MASKP4_Pos 4 /*!< GPIO_PORT MASK3: MASKP4 Position */ -#define GPIO_PORT_MASK3_MASKP4_Msk (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos) /*!< GPIO_PORT MASK3: MASKP4 Mask */ -#define GPIO_PORT_MASK3_MASKP5_Pos 5 /*!< GPIO_PORT MASK3: MASKP5 Position */ -#define GPIO_PORT_MASK3_MASKP5_Msk (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos) /*!< GPIO_PORT MASK3: MASKP5 Mask */ -#define GPIO_PORT_MASK3_MASKP6_Pos 6 /*!< GPIO_PORT MASK3: MASKP6 Position */ -#define GPIO_PORT_MASK3_MASKP6_Msk (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos) /*!< GPIO_PORT MASK3: MASKP6 Mask */ -#define GPIO_PORT_MASK3_MASKP7_Pos 7 /*!< GPIO_PORT MASK3: MASKP7 Position */ -#define GPIO_PORT_MASK3_MASKP7_Msk (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos) /*!< GPIO_PORT MASK3: MASKP7 Mask */ -#define GPIO_PORT_MASK3_MASKP8_Pos 8 /*!< GPIO_PORT MASK3: MASKP8 Position */ -#define GPIO_PORT_MASK3_MASKP8_Msk (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos) /*!< GPIO_PORT MASK3: MASKP8 Mask */ -#define GPIO_PORT_MASK3_MASKP9_Pos 9 /*!< GPIO_PORT MASK3: MASKP9 Position */ -#define GPIO_PORT_MASK3_MASKP9_Msk (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos) /*!< GPIO_PORT MASK3: MASKP9 Mask */ -#define GPIO_PORT_MASK3_MASKP10_Pos 10 /*!< GPIO_PORT MASK3: MASKP10 Position */ -#define GPIO_PORT_MASK3_MASKP10_Msk (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos) /*!< GPIO_PORT MASK3: MASKP10 Mask */ -#define GPIO_PORT_MASK3_MASKP11_Pos 11 /*!< GPIO_PORT MASK3: MASKP11 Position */ -#define GPIO_PORT_MASK3_MASKP11_Msk (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos) /*!< GPIO_PORT MASK3: MASKP11 Mask */ -#define GPIO_PORT_MASK3_MASKP12_Pos 12 /*!< GPIO_PORT MASK3: MASKP12 Position */ -#define GPIO_PORT_MASK3_MASKP12_Msk (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos) /*!< GPIO_PORT MASK3: MASKP12 Mask */ -#define GPIO_PORT_MASK3_MASKP13_Pos 13 /*!< GPIO_PORT MASK3: MASKP13 Position */ -#define GPIO_PORT_MASK3_MASKP13_Msk (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos) /*!< GPIO_PORT MASK3: MASKP13 Mask */ -#define GPIO_PORT_MASK3_MASKP14_Pos 14 /*!< GPIO_PORT MASK3: MASKP14 Position */ -#define GPIO_PORT_MASK3_MASKP14_Msk (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos) /*!< GPIO_PORT MASK3: MASKP14 Mask */ -#define GPIO_PORT_MASK3_MASKP15_Pos 15 /*!< GPIO_PORT MASK3: MASKP15 Position */ -#define GPIO_PORT_MASK3_MASKP15_Msk (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos) /*!< GPIO_PORT MASK3: MASKP15 Mask */ -#define GPIO_PORT_MASK3_MASKP16_Pos 16 /*!< GPIO_PORT MASK3: MASKP16 Position */ -#define GPIO_PORT_MASK3_MASKP16_Msk (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos) /*!< GPIO_PORT MASK3: MASKP16 Mask */ -#define GPIO_PORT_MASK3_MASKP17_Pos 17 /*!< GPIO_PORT MASK3: MASKP17 Position */ -#define GPIO_PORT_MASK3_MASKP17_Msk (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos) /*!< GPIO_PORT MASK3: MASKP17 Mask */ -#define GPIO_PORT_MASK3_MASKP18_Pos 18 /*!< GPIO_PORT MASK3: MASKP18 Position */ -#define GPIO_PORT_MASK3_MASKP18_Msk (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos) /*!< GPIO_PORT MASK3: MASKP18 Mask */ -#define GPIO_PORT_MASK3_MASKP19_Pos 19 /*!< GPIO_PORT MASK3: MASKP19 Position */ -#define GPIO_PORT_MASK3_MASKP19_Msk (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos) /*!< GPIO_PORT MASK3: MASKP19 Mask */ -#define GPIO_PORT_MASK3_MASKP20_Pos 20 /*!< GPIO_PORT MASK3: MASKP20 Position */ -#define GPIO_PORT_MASK3_MASKP20_Msk (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos) /*!< GPIO_PORT MASK3: MASKP20 Mask */ -#define GPIO_PORT_MASK3_MASKP21_Pos 21 /*!< GPIO_PORT MASK3: MASKP21 Position */ -#define GPIO_PORT_MASK3_MASKP21_Msk (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos) /*!< GPIO_PORT MASK3: MASKP21 Mask */ -#define GPIO_PORT_MASK3_MASKP22_Pos 22 /*!< GPIO_PORT MASK3: MASKP22 Position */ -#define GPIO_PORT_MASK3_MASKP22_Msk (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos) /*!< GPIO_PORT MASK3: MASKP22 Mask */ -#define GPIO_PORT_MASK3_MASKP23_Pos 23 /*!< GPIO_PORT MASK3: MASKP23 Position */ -#define GPIO_PORT_MASK3_MASKP23_Msk (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos) /*!< GPIO_PORT MASK3: MASKP23 Mask */ -#define GPIO_PORT_MASK3_MASKP24_Pos 24 /*!< GPIO_PORT MASK3: MASKP24 Position */ -#define GPIO_PORT_MASK3_MASKP24_Msk (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos) /*!< GPIO_PORT MASK3: MASKP24 Mask */ -#define GPIO_PORT_MASK3_MASKP25_Pos 25 /*!< GPIO_PORT MASK3: MASKP25 Position */ -#define GPIO_PORT_MASK3_MASKP25_Msk (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos) /*!< GPIO_PORT MASK3: MASKP25 Mask */ -#define GPIO_PORT_MASK3_MASKP26_Pos 26 /*!< GPIO_PORT MASK3: MASKP26 Position */ -#define GPIO_PORT_MASK3_MASKP26_Msk (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos) /*!< GPIO_PORT MASK3: MASKP26 Mask */ -#define GPIO_PORT_MASK3_MASKP27_Pos 27 /*!< GPIO_PORT MASK3: MASKP27 Position */ -#define GPIO_PORT_MASK3_MASKP27_Msk (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos) /*!< GPIO_PORT MASK3: MASKP27 Mask */ -#define GPIO_PORT_MASK3_MASKP28_Pos 28 /*!< GPIO_PORT MASK3: MASKP28 Position */ -#define GPIO_PORT_MASK3_MASKP28_Msk (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos) /*!< GPIO_PORT MASK3: MASKP28 Mask */ -#define GPIO_PORT_MASK3_MASKP29_Pos 29 /*!< GPIO_PORT MASK3: MASKP29 Position */ -#define GPIO_PORT_MASK3_MASKP29_Msk (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos) /*!< GPIO_PORT MASK3: MASKP29 Mask */ -#define GPIO_PORT_MASK3_MASKP30_Pos 30 /*!< GPIO_PORT MASK3: MASKP30 Position */ -#define GPIO_PORT_MASK3_MASKP30_Msk (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos) /*!< GPIO_PORT MASK3: MASKP30 Mask */ -#define GPIO_PORT_MASK3_MASKP31_Pos 31 /*!< GPIO_PORT MASK3: MASKP31 Position */ -#define GPIO_PORT_MASK3_MASKP31_Msk (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos) /*!< GPIO_PORT MASK3: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK4 ---------------------------------------- -#define GPIO_PORT_MASK4_MASKP0_Pos 0 /*!< GPIO_PORT MASK4: MASKP0 Position */ -#define GPIO_PORT_MASK4_MASKP0_Msk (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos) /*!< GPIO_PORT MASK4: MASKP0 Mask */ -#define GPIO_PORT_MASK4_MASKP1_Pos 1 /*!< GPIO_PORT MASK4: MASKP1 Position */ -#define GPIO_PORT_MASK4_MASKP1_Msk (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos) /*!< GPIO_PORT MASK4: MASKP1 Mask */ -#define GPIO_PORT_MASK4_MASKP2_Pos 2 /*!< GPIO_PORT MASK4: MASKP2 Position */ -#define GPIO_PORT_MASK4_MASKP2_Msk (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos) /*!< GPIO_PORT MASK4: MASKP2 Mask */ -#define GPIO_PORT_MASK4_MASKP3_Pos 3 /*!< GPIO_PORT MASK4: MASKP3 Position */ -#define GPIO_PORT_MASK4_MASKP3_Msk (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos) /*!< GPIO_PORT MASK4: MASKP3 Mask */ -#define GPIO_PORT_MASK4_MASKP4_Pos 4 /*!< GPIO_PORT MASK4: MASKP4 Position */ -#define GPIO_PORT_MASK4_MASKP4_Msk (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos) /*!< GPIO_PORT MASK4: MASKP4 Mask */ -#define GPIO_PORT_MASK4_MASKP5_Pos 5 /*!< GPIO_PORT MASK4: MASKP5 Position */ -#define GPIO_PORT_MASK4_MASKP5_Msk (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos) /*!< GPIO_PORT MASK4: MASKP5 Mask */ -#define GPIO_PORT_MASK4_MASKP6_Pos 6 /*!< GPIO_PORT MASK4: MASKP6 Position */ -#define GPIO_PORT_MASK4_MASKP6_Msk (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos) /*!< GPIO_PORT MASK4: MASKP6 Mask */ -#define GPIO_PORT_MASK4_MASKP7_Pos 7 /*!< GPIO_PORT MASK4: MASKP7 Position */ -#define GPIO_PORT_MASK4_MASKP7_Msk (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos) /*!< GPIO_PORT MASK4: MASKP7 Mask */ -#define GPIO_PORT_MASK4_MASKP8_Pos 8 /*!< GPIO_PORT MASK4: MASKP8 Position */ -#define GPIO_PORT_MASK4_MASKP8_Msk (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos) /*!< GPIO_PORT MASK4: MASKP8 Mask */ -#define GPIO_PORT_MASK4_MASKP9_Pos 9 /*!< GPIO_PORT MASK4: MASKP9 Position */ -#define GPIO_PORT_MASK4_MASKP9_Msk (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos) /*!< GPIO_PORT MASK4: MASKP9 Mask */ -#define GPIO_PORT_MASK4_MASKP10_Pos 10 /*!< GPIO_PORT MASK4: MASKP10 Position */ -#define GPIO_PORT_MASK4_MASKP10_Msk (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos) /*!< GPIO_PORT MASK4: MASKP10 Mask */ -#define GPIO_PORT_MASK4_MASKP11_Pos 11 /*!< GPIO_PORT MASK4: MASKP11 Position */ -#define GPIO_PORT_MASK4_MASKP11_Msk (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos) /*!< GPIO_PORT MASK4: MASKP11 Mask */ -#define GPIO_PORT_MASK4_MASKP12_Pos 12 /*!< GPIO_PORT MASK4: MASKP12 Position */ -#define GPIO_PORT_MASK4_MASKP12_Msk (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos) /*!< GPIO_PORT MASK4: MASKP12 Mask */ -#define GPIO_PORT_MASK4_MASKP13_Pos 13 /*!< GPIO_PORT MASK4: MASKP13 Position */ -#define GPIO_PORT_MASK4_MASKP13_Msk (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos) /*!< GPIO_PORT MASK4: MASKP13 Mask */ -#define GPIO_PORT_MASK4_MASKP14_Pos 14 /*!< GPIO_PORT MASK4: MASKP14 Position */ -#define GPIO_PORT_MASK4_MASKP14_Msk (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos) /*!< GPIO_PORT MASK4: MASKP14 Mask */ -#define GPIO_PORT_MASK4_MASKP15_Pos 15 /*!< GPIO_PORT MASK4: MASKP15 Position */ -#define GPIO_PORT_MASK4_MASKP15_Msk (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos) /*!< GPIO_PORT MASK4: MASKP15 Mask */ -#define GPIO_PORT_MASK4_MASKP16_Pos 16 /*!< GPIO_PORT MASK4: MASKP16 Position */ -#define GPIO_PORT_MASK4_MASKP16_Msk (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos) /*!< GPIO_PORT MASK4: MASKP16 Mask */ -#define GPIO_PORT_MASK4_MASKP17_Pos 17 /*!< GPIO_PORT MASK4: MASKP17 Position */ -#define GPIO_PORT_MASK4_MASKP17_Msk (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos) /*!< GPIO_PORT MASK4: MASKP17 Mask */ -#define GPIO_PORT_MASK4_MASKP18_Pos 18 /*!< GPIO_PORT MASK4: MASKP18 Position */ -#define GPIO_PORT_MASK4_MASKP18_Msk (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos) /*!< GPIO_PORT MASK4: MASKP18 Mask */ -#define GPIO_PORT_MASK4_MASKP19_Pos 19 /*!< GPIO_PORT MASK4: MASKP19 Position */ -#define GPIO_PORT_MASK4_MASKP19_Msk (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos) /*!< GPIO_PORT MASK4: MASKP19 Mask */ -#define GPIO_PORT_MASK4_MASKP20_Pos 20 /*!< GPIO_PORT MASK4: MASKP20 Position */ -#define GPIO_PORT_MASK4_MASKP20_Msk (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos) /*!< GPIO_PORT MASK4: MASKP20 Mask */ -#define GPIO_PORT_MASK4_MASKP21_Pos 21 /*!< GPIO_PORT MASK4: MASKP21 Position */ -#define GPIO_PORT_MASK4_MASKP21_Msk (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos) /*!< GPIO_PORT MASK4: MASKP21 Mask */ -#define GPIO_PORT_MASK4_MASKP22_Pos 22 /*!< GPIO_PORT MASK4: MASKP22 Position */ -#define GPIO_PORT_MASK4_MASKP22_Msk (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos) /*!< GPIO_PORT MASK4: MASKP22 Mask */ -#define GPIO_PORT_MASK4_MASKP23_Pos 23 /*!< GPIO_PORT MASK4: MASKP23 Position */ -#define GPIO_PORT_MASK4_MASKP23_Msk (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos) /*!< GPIO_PORT MASK4: MASKP23 Mask */ -#define GPIO_PORT_MASK4_MASKP24_Pos 24 /*!< GPIO_PORT MASK4: MASKP24 Position */ -#define GPIO_PORT_MASK4_MASKP24_Msk (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos) /*!< GPIO_PORT MASK4: MASKP24 Mask */ -#define GPIO_PORT_MASK4_MASKP25_Pos 25 /*!< GPIO_PORT MASK4: MASKP25 Position */ -#define GPIO_PORT_MASK4_MASKP25_Msk (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos) /*!< GPIO_PORT MASK4: MASKP25 Mask */ -#define GPIO_PORT_MASK4_MASKP26_Pos 26 /*!< GPIO_PORT MASK4: MASKP26 Position */ -#define GPIO_PORT_MASK4_MASKP26_Msk (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos) /*!< GPIO_PORT MASK4: MASKP26 Mask */ -#define GPIO_PORT_MASK4_MASKP27_Pos 27 /*!< GPIO_PORT MASK4: MASKP27 Position */ -#define GPIO_PORT_MASK4_MASKP27_Msk (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos) /*!< GPIO_PORT MASK4: MASKP27 Mask */ -#define GPIO_PORT_MASK4_MASKP28_Pos 28 /*!< GPIO_PORT MASK4: MASKP28 Position */ -#define GPIO_PORT_MASK4_MASKP28_Msk (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos) /*!< GPIO_PORT MASK4: MASKP28 Mask */ -#define GPIO_PORT_MASK4_MASKP29_Pos 29 /*!< GPIO_PORT MASK4: MASKP29 Position */ -#define GPIO_PORT_MASK4_MASKP29_Msk (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos) /*!< GPIO_PORT MASK4: MASKP29 Mask */ -#define GPIO_PORT_MASK4_MASKP30_Pos 30 /*!< GPIO_PORT MASK4: MASKP30 Position */ -#define GPIO_PORT_MASK4_MASKP30_Msk (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos) /*!< GPIO_PORT MASK4: MASKP30 Mask */ -#define GPIO_PORT_MASK4_MASKP31_Pos 31 /*!< GPIO_PORT MASK4: MASKP31 Position */ -#define GPIO_PORT_MASK4_MASKP31_Msk (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos) /*!< GPIO_PORT MASK4: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK5 ---------------------------------------- -#define GPIO_PORT_MASK5_MASKP0_Pos 0 /*!< GPIO_PORT MASK5: MASKP0 Position */ -#define GPIO_PORT_MASK5_MASKP0_Msk (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos) /*!< GPIO_PORT MASK5: MASKP0 Mask */ -#define GPIO_PORT_MASK5_MASKP1_Pos 1 /*!< GPIO_PORT MASK5: MASKP1 Position */ -#define GPIO_PORT_MASK5_MASKP1_Msk (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos) /*!< GPIO_PORT MASK5: MASKP1 Mask */ -#define GPIO_PORT_MASK5_MASKP2_Pos 2 /*!< GPIO_PORT MASK5: MASKP2 Position */ -#define GPIO_PORT_MASK5_MASKP2_Msk (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos) /*!< GPIO_PORT MASK5: MASKP2 Mask */ -#define GPIO_PORT_MASK5_MASKP3_Pos 3 /*!< GPIO_PORT MASK5: MASKP3 Position */ -#define GPIO_PORT_MASK5_MASKP3_Msk (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos) /*!< GPIO_PORT MASK5: MASKP3 Mask */ -#define GPIO_PORT_MASK5_MASKP4_Pos 4 /*!< GPIO_PORT MASK5: MASKP4 Position */ -#define GPIO_PORT_MASK5_MASKP4_Msk (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos) /*!< GPIO_PORT MASK5: MASKP4 Mask */ -#define GPIO_PORT_MASK5_MASKP5_Pos 5 /*!< GPIO_PORT MASK5: MASKP5 Position */ -#define GPIO_PORT_MASK5_MASKP5_Msk (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos) /*!< GPIO_PORT MASK5: MASKP5 Mask */ -#define GPIO_PORT_MASK5_MASKP6_Pos 6 /*!< GPIO_PORT MASK5: MASKP6 Position */ -#define GPIO_PORT_MASK5_MASKP6_Msk (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos) /*!< GPIO_PORT MASK5: MASKP6 Mask */ -#define GPIO_PORT_MASK5_MASKP7_Pos 7 /*!< GPIO_PORT MASK5: MASKP7 Position */ -#define GPIO_PORT_MASK5_MASKP7_Msk (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos) /*!< GPIO_PORT MASK5: MASKP7 Mask */ -#define GPIO_PORT_MASK5_MASKP8_Pos 8 /*!< GPIO_PORT MASK5: MASKP8 Position */ -#define GPIO_PORT_MASK5_MASKP8_Msk (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos) /*!< GPIO_PORT MASK5: MASKP8 Mask */ -#define GPIO_PORT_MASK5_MASKP9_Pos 9 /*!< GPIO_PORT MASK5: MASKP9 Position */ -#define GPIO_PORT_MASK5_MASKP9_Msk (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos) /*!< GPIO_PORT MASK5: MASKP9 Mask */ -#define GPIO_PORT_MASK5_MASKP10_Pos 10 /*!< GPIO_PORT MASK5: MASKP10 Position */ -#define GPIO_PORT_MASK5_MASKP10_Msk (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos) /*!< GPIO_PORT MASK5: MASKP10 Mask */ -#define GPIO_PORT_MASK5_MASKP11_Pos 11 /*!< GPIO_PORT MASK5: MASKP11 Position */ -#define GPIO_PORT_MASK5_MASKP11_Msk (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos) /*!< GPIO_PORT MASK5: MASKP11 Mask */ -#define GPIO_PORT_MASK5_MASKP12_Pos 12 /*!< GPIO_PORT MASK5: MASKP12 Position */ -#define GPIO_PORT_MASK5_MASKP12_Msk (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos) /*!< GPIO_PORT MASK5: MASKP12 Mask */ -#define GPIO_PORT_MASK5_MASKP13_Pos 13 /*!< GPIO_PORT MASK5: MASKP13 Position */ -#define GPIO_PORT_MASK5_MASKP13_Msk (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos) /*!< GPIO_PORT MASK5: MASKP13 Mask */ -#define GPIO_PORT_MASK5_MASKP14_Pos 14 /*!< GPIO_PORT MASK5: MASKP14 Position */ -#define GPIO_PORT_MASK5_MASKP14_Msk (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos) /*!< GPIO_PORT MASK5: MASKP14 Mask */ -#define GPIO_PORT_MASK5_MASKP15_Pos 15 /*!< GPIO_PORT MASK5: MASKP15 Position */ -#define GPIO_PORT_MASK5_MASKP15_Msk (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos) /*!< GPIO_PORT MASK5: MASKP15 Mask */ -#define GPIO_PORT_MASK5_MASKP16_Pos 16 /*!< GPIO_PORT MASK5: MASKP16 Position */ -#define GPIO_PORT_MASK5_MASKP16_Msk (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos) /*!< GPIO_PORT MASK5: MASKP16 Mask */ -#define GPIO_PORT_MASK5_MASKP17_Pos 17 /*!< GPIO_PORT MASK5: MASKP17 Position */ -#define GPIO_PORT_MASK5_MASKP17_Msk (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos) /*!< GPIO_PORT MASK5: MASKP17 Mask */ -#define GPIO_PORT_MASK5_MASKP18_Pos 18 /*!< GPIO_PORT MASK5: MASKP18 Position */ -#define GPIO_PORT_MASK5_MASKP18_Msk (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos) /*!< GPIO_PORT MASK5: MASKP18 Mask */ -#define GPIO_PORT_MASK5_MASKP19_Pos 19 /*!< GPIO_PORT MASK5: MASKP19 Position */ -#define GPIO_PORT_MASK5_MASKP19_Msk (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos) /*!< GPIO_PORT MASK5: MASKP19 Mask */ -#define GPIO_PORT_MASK5_MASKP20_Pos 20 /*!< GPIO_PORT MASK5: MASKP20 Position */ -#define GPIO_PORT_MASK5_MASKP20_Msk (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos) /*!< GPIO_PORT MASK5: MASKP20 Mask */ -#define GPIO_PORT_MASK5_MASKP21_Pos 21 /*!< GPIO_PORT MASK5: MASKP21 Position */ -#define GPIO_PORT_MASK5_MASKP21_Msk (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos) /*!< GPIO_PORT MASK5: MASKP21 Mask */ -#define GPIO_PORT_MASK5_MASKP22_Pos 22 /*!< GPIO_PORT MASK5: MASKP22 Position */ -#define GPIO_PORT_MASK5_MASKP22_Msk (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos) /*!< GPIO_PORT MASK5: MASKP22 Mask */ -#define GPIO_PORT_MASK5_MASKP23_Pos 23 /*!< GPIO_PORT MASK5: MASKP23 Position */ -#define GPIO_PORT_MASK5_MASKP23_Msk (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos) /*!< GPIO_PORT MASK5: MASKP23 Mask */ -#define GPIO_PORT_MASK5_MASKP24_Pos 24 /*!< GPIO_PORT MASK5: MASKP24 Position */ -#define GPIO_PORT_MASK5_MASKP24_Msk (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos) /*!< GPIO_PORT MASK5: MASKP24 Mask */ -#define GPIO_PORT_MASK5_MASKP25_Pos 25 /*!< GPIO_PORT MASK5: MASKP25 Position */ -#define GPIO_PORT_MASK5_MASKP25_Msk (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos) /*!< GPIO_PORT MASK5: MASKP25 Mask */ -#define GPIO_PORT_MASK5_MASKP26_Pos 26 /*!< GPIO_PORT MASK5: MASKP26 Position */ -#define GPIO_PORT_MASK5_MASKP26_Msk (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos) /*!< GPIO_PORT MASK5: MASKP26 Mask */ -#define GPIO_PORT_MASK5_MASKP27_Pos 27 /*!< GPIO_PORT MASK5: MASKP27 Position */ -#define GPIO_PORT_MASK5_MASKP27_Msk (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos) /*!< GPIO_PORT MASK5: MASKP27 Mask */ -#define GPIO_PORT_MASK5_MASKP28_Pos 28 /*!< GPIO_PORT MASK5: MASKP28 Position */ -#define GPIO_PORT_MASK5_MASKP28_Msk (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos) /*!< GPIO_PORT MASK5: MASKP28 Mask */ -#define GPIO_PORT_MASK5_MASKP29_Pos 29 /*!< GPIO_PORT MASK5: MASKP29 Position */ -#define GPIO_PORT_MASK5_MASKP29_Msk (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos) /*!< GPIO_PORT MASK5: MASKP29 Mask */ -#define GPIO_PORT_MASK5_MASKP30_Pos 30 /*!< GPIO_PORT MASK5: MASKP30 Position */ -#define GPIO_PORT_MASK5_MASKP30_Msk (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos) /*!< GPIO_PORT MASK5: MASKP30 Mask */ -#define GPIO_PORT_MASK5_MASKP31_Pos 31 /*!< GPIO_PORT MASK5: MASKP31 Position */ -#define GPIO_PORT_MASK5_MASKP31_Msk (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos) /*!< GPIO_PORT MASK5: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK6 ---------------------------------------- -#define GPIO_PORT_MASK6_MASKP0_Pos 0 /*!< GPIO_PORT MASK6: MASKP0 Position */ -#define GPIO_PORT_MASK6_MASKP0_Msk (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos) /*!< GPIO_PORT MASK6: MASKP0 Mask */ -#define GPIO_PORT_MASK6_MASKP1_Pos 1 /*!< GPIO_PORT MASK6: MASKP1 Position */ -#define GPIO_PORT_MASK6_MASKP1_Msk (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos) /*!< GPIO_PORT MASK6: MASKP1 Mask */ -#define GPIO_PORT_MASK6_MASKP2_Pos 2 /*!< GPIO_PORT MASK6: MASKP2 Position */ -#define GPIO_PORT_MASK6_MASKP2_Msk (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos) /*!< GPIO_PORT MASK6: MASKP2 Mask */ -#define GPIO_PORT_MASK6_MASKP3_Pos 3 /*!< GPIO_PORT MASK6: MASKP3 Position */ -#define GPIO_PORT_MASK6_MASKP3_Msk (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos) /*!< GPIO_PORT MASK6: MASKP3 Mask */ -#define GPIO_PORT_MASK6_MASKP4_Pos 4 /*!< GPIO_PORT MASK6: MASKP4 Position */ -#define GPIO_PORT_MASK6_MASKP4_Msk (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos) /*!< GPIO_PORT MASK6: MASKP4 Mask */ -#define GPIO_PORT_MASK6_MASKP5_Pos 5 /*!< GPIO_PORT MASK6: MASKP5 Position */ -#define GPIO_PORT_MASK6_MASKP5_Msk (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos) /*!< GPIO_PORT MASK6: MASKP5 Mask */ -#define GPIO_PORT_MASK6_MASKP6_Pos 6 /*!< GPIO_PORT MASK6: MASKP6 Position */ -#define GPIO_PORT_MASK6_MASKP6_Msk (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos) /*!< GPIO_PORT MASK6: MASKP6 Mask */ -#define GPIO_PORT_MASK6_MASKP7_Pos 7 /*!< GPIO_PORT MASK6: MASKP7 Position */ -#define GPIO_PORT_MASK6_MASKP7_Msk (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos) /*!< GPIO_PORT MASK6: MASKP7 Mask */ -#define GPIO_PORT_MASK6_MASKP8_Pos 8 /*!< GPIO_PORT MASK6: MASKP8 Position */ -#define GPIO_PORT_MASK6_MASKP8_Msk (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos) /*!< GPIO_PORT MASK6: MASKP8 Mask */ -#define GPIO_PORT_MASK6_MASKP9_Pos 9 /*!< GPIO_PORT MASK6: MASKP9 Position */ -#define GPIO_PORT_MASK6_MASKP9_Msk (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos) /*!< GPIO_PORT MASK6: MASKP9 Mask */ -#define GPIO_PORT_MASK6_MASKP10_Pos 10 /*!< GPIO_PORT MASK6: MASKP10 Position */ -#define GPIO_PORT_MASK6_MASKP10_Msk (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos) /*!< GPIO_PORT MASK6: MASKP10 Mask */ -#define GPIO_PORT_MASK6_MASKP11_Pos 11 /*!< GPIO_PORT MASK6: MASKP11 Position */ -#define GPIO_PORT_MASK6_MASKP11_Msk (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos) /*!< GPIO_PORT MASK6: MASKP11 Mask */ -#define GPIO_PORT_MASK6_MASKP12_Pos 12 /*!< GPIO_PORT MASK6: MASKP12 Position */ -#define GPIO_PORT_MASK6_MASKP12_Msk (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos) /*!< GPIO_PORT MASK6: MASKP12 Mask */ -#define GPIO_PORT_MASK6_MASKP13_Pos 13 /*!< GPIO_PORT MASK6: MASKP13 Position */ -#define GPIO_PORT_MASK6_MASKP13_Msk (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos) /*!< GPIO_PORT MASK6: MASKP13 Mask */ -#define GPIO_PORT_MASK6_MASKP14_Pos 14 /*!< GPIO_PORT MASK6: MASKP14 Position */ -#define GPIO_PORT_MASK6_MASKP14_Msk (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos) /*!< GPIO_PORT MASK6: MASKP14 Mask */ -#define GPIO_PORT_MASK6_MASKP15_Pos 15 /*!< GPIO_PORT MASK6: MASKP15 Position */ -#define GPIO_PORT_MASK6_MASKP15_Msk (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos) /*!< GPIO_PORT MASK6: MASKP15 Mask */ -#define GPIO_PORT_MASK6_MASKP16_Pos 16 /*!< GPIO_PORT MASK6: MASKP16 Position */ -#define GPIO_PORT_MASK6_MASKP16_Msk (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos) /*!< GPIO_PORT MASK6: MASKP16 Mask */ -#define GPIO_PORT_MASK6_MASKP17_Pos 17 /*!< GPIO_PORT MASK6: MASKP17 Position */ -#define GPIO_PORT_MASK6_MASKP17_Msk (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos) /*!< GPIO_PORT MASK6: MASKP17 Mask */ -#define GPIO_PORT_MASK6_MASKP18_Pos 18 /*!< GPIO_PORT MASK6: MASKP18 Position */ -#define GPIO_PORT_MASK6_MASKP18_Msk (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos) /*!< GPIO_PORT MASK6: MASKP18 Mask */ -#define GPIO_PORT_MASK6_MASKP19_Pos 19 /*!< GPIO_PORT MASK6: MASKP19 Position */ -#define GPIO_PORT_MASK6_MASKP19_Msk (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos) /*!< GPIO_PORT MASK6: MASKP19 Mask */ -#define GPIO_PORT_MASK6_MASKP20_Pos 20 /*!< GPIO_PORT MASK6: MASKP20 Position */ -#define GPIO_PORT_MASK6_MASKP20_Msk (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos) /*!< GPIO_PORT MASK6: MASKP20 Mask */ -#define GPIO_PORT_MASK6_MASKP21_Pos 21 /*!< GPIO_PORT MASK6: MASKP21 Position */ -#define GPIO_PORT_MASK6_MASKP21_Msk (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos) /*!< GPIO_PORT MASK6: MASKP21 Mask */ -#define GPIO_PORT_MASK6_MASKP22_Pos 22 /*!< GPIO_PORT MASK6: MASKP22 Position */ -#define GPIO_PORT_MASK6_MASKP22_Msk (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos) /*!< GPIO_PORT MASK6: MASKP22 Mask */ -#define GPIO_PORT_MASK6_MASKP23_Pos 23 /*!< GPIO_PORT MASK6: MASKP23 Position */ -#define GPIO_PORT_MASK6_MASKP23_Msk (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos) /*!< GPIO_PORT MASK6: MASKP23 Mask */ -#define GPIO_PORT_MASK6_MASKP24_Pos 24 /*!< GPIO_PORT MASK6: MASKP24 Position */ -#define GPIO_PORT_MASK6_MASKP24_Msk (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos) /*!< GPIO_PORT MASK6: MASKP24 Mask */ -#define GPIO_PORT_MASK6_MASKP25_Pos 25 /*!< GPIO_PORT MASK6: MASKP25 Position */ -#define GPIO_PORT_MASK6_MASKP25_Msk (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos) /*!< GPIO_PORT MASK6: MASKP25 Mask */ -#define GPIO_PORT_MASK6_MASKP26_Pos 26 /*!< GPIO_PORT MASK6: MASKP26 Position */ -#define GPIO_PORT_MASK6_MASKP26_Msk (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos) /*!< GPIO_PORT MASK6: MASKP26 Mask */ -#define GPIO_PORT_MASK6_MASKP27_Pos 27 /*!< GPIO_PORT MASK6: MASKP27 Position */ -#define GPIO_PORT_MASK6_MASKP27_Msk (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos) /*!< GPIO_PORT MASK6: MASKP27 Mask */ -#define GPIO_PORT_MASK6_MASKP28_Pos 28 /*!< GPIO_PORT MASK6: MASKP28 Position */ -#define GPIO_PORT_MASK6_MASKP28_Msk (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos) /*!< GPIO_PORT MASK6: MASKP28 Mask */ -#define GPIO_PORT_MASK6_MASKP29_Pos 29 /*!< GPIO_PORT MASK6: MASKP29 Position */ -#define GPIO_PORT_MASK6_MASKP29_Msk (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos) /*!< GPIO_PORT MASK6: MASKP29 Mask */ -#define GPIO_PORT_MASK6_MASKP30_Pos 30 /*!< GPIO_PORT MASK6: MASKP30 Position */ -#define GPIO_PORT_MASK6_MASKP30_Msk (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos) /*!< GPIO_PORT MASK6: MASKP30 Mask */ -#define GPIO_PORT_MASK6_MASKP31_Pos 31 /*!< GPIO_PORT MASK6: MASKP31 Position */ -#define GPIO_PORT_MASK6_MASKP31_Msk (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos) /*!< GPIO_PORT MASK6: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK7 ---------------------------------------- -#define GPIO_PORT_MASK7_MASKP0_Pos 0 /*!< GPIO_PORT MASK7: MASKP0 Position */ -#define GPIO_PORT_MASK7_MASKP0_Msk (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos) /*!< GPIO_PORT MASK7: MASKP0 Mask */ -#define GPIO_PORT_MASK7_MASKP1_Pos 1 /*!< GPIO_PORT MASK7: MASKP1 Position */ -#define GPIO_PORT_MASK7_MASKP1_Msk (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos) /*!< GPIO_PORT MASK7: MASKP1 Mask */ -#define GPIO_PORT_MASK7_MASKP2_Pos 2 /*!< GPIO_PORT MASK7: MASKP2 Position */ -#define GPIO_PORT_MASK7_MASKP2_Msk (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos) /*!< GPIO_PORT MASK7: MASKP2 Mask */ -#define GPIO_PORT_MASK7_MASKP3_Pos 3 /*!< GPIO_PORT MASK7: MASKP3 Position */ -#define GPIO_PORT_MASK7_MASKP3_Msk (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos) /*!< GPIO_PORT MASK7: MASKP3 Mask */ -#define GPIO_PORT_MASK7_MASKP4_Pos 4 /*!< GPIO_PORT MASK7: MASKP4 Position */ -#define GPIO_PORT_MASK7_MASKP4_Msk (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos) /*!< GPIO_PORT MASK7: MASKP4 Mask */ -#define GPIO_PORT_MASK7_MASKP5_Pos 5 /*!< GPIO_PORT MASK7: MASKP5 Position */ -#define GPIO_PORT_MASK7_MASKP5_Msk (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos) /*!< GPIO_PORT MASK7: MASKP5 Mask */ -#define GPIO_PORT_MASK7_MASKP6_Pos 6 /*!< GPIO_PORT MASK7: MASKP6 Position */ -#define GPIO_PORT_MASK7_MASKP6_Msk (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos) /*!< GPIO_PORT MASK7: MASKP6 Mask */ -#define GPIO_PORT_MASK7_MASKP7_Pos 7 /*!< GPIO_PORT MASK7: MASKP7 Position */ -#define GPIO_PORT_MASK7_MASKP7_Msk (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos) /*!< GPIO_PORT MASK7: MASKP7 Mask */ -#define GPIO_PORT_MASK7_MASKP8_Pos 8 /*!< GPIO_PORT MASK7: MASKP8 Position */ -#define GPIO_PORT_MASK7_MASKP8_Msk (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos) /*!< GPIO_PORT MASK7: MASKP8 Mask */ -#define GPIO_PORT_MASK7_MASKP9_Pos 9 /*!< GPIO_PORT MASK7: MASKP9 Position */ -#define GPIO_PORT_MASK7_MASKP9_Msk (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos) /*!< GPIO_PORT MASK7: MASKP9 Mask */ -#define GPIO_PORT_MASK7_MASKP10_Pos 10 /*!< GPIO_PORT MASK7: MASKP10 Position */ -#define GPIO_PORT_MASK7_MASKP10_Msk (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos) /*!< GPIO_PORT MASK7: MASKP10 Mask */ -#define GPIO_PORT_MASK7_MASKP11_Pos 11 /*!< GPIO_PORT MASK7: MASKP11 Position */ -#define GPIO_PORT_MASK7_MASKP11_Msk (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos) /*!< GPIO_PORT MASK7: MASKP11 Mask */ -#define GPIO_PORT_MASK7_MASKP12_Pos 12 /*!< GPIO_PORT MASK7: MASKP12 Position */ -#define GPIO_PORT_MASK7_MASKP12_Msk (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos) /*!< GPIO_PORT MASK7: MASKP12 Mask */ -#define GPIO_PORT_MASK7_MASKP13_Pos 13 /*!< GPIO_PORT MASK7: MASKP13 Position */ -#define GPIO_PORT_MASK7_MASKP13_Msk (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos) /*!< GPIO_PORT MASK7: MASKP13 Mask */ -#define GPIO_PORT_MASK7_MASKP14_Pos 14 /*!< GPIO_PORT MASK7: MASKP14 Position */ -#define GPIO_PORT_MASK7_MASKP14_Msk (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos) /*!< GPIO_PORT MASK7: MASKP14 Mask */ -#define GPIO_PORT_MASK7_MASKP15_Pos 15 /*!< GPIO_PORT MASK7: MASKP15 Position */ -#define GPIO_PORT_MASK7_MASKP15_Msk (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos) /*!< GPIO_PORT MASK7: MASKP15 Mask */ -#define GPIO_PORT_MASK7_MASKP16_Pos 16 /*!< GPIO_PORT MASK7: MASKP16 Position */ -#define GPIO_PORT_MASK7_MASKP16_Msk (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos) /*!< GPIO_PORT MASK7: MASKP16 Mask */ -#define GPIO_PORT_MASK7_MASKP17_Pos 17 /*!< GPIO_PORT MASK7: MASKP17 Position */ -#define GPIO_PORT_MASK7_MASKP17_Msk (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos) /*!< GPIO_PORT MASK7: MASKP17 Mask */ -#define GPIO_PORT_MASK7_MASKP18_Pos 18 /*!< GPIO_PORT MASK7: MASKP18 Position */ -#define GPIO_PORT_MASK7_MASKP18_Msk (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos) /*!< GPIO_PORT MASK7: MASKP18 Mask */ -#define GPIO_PORT_MASK7_MASKP19_Pos 19 /*!< GPIO_PORT MASK7: MASKP19 Position */ -#define GPIO_PORT_MASK7_MASKP19_Msk (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos) /*!< GPIO_PORT MASK7: MASKP19 Mask */ -#define GPIO_PORT_MASK7_MASKP20_Pos 20 /*!< GPIO_PORT MASK7: MASKP20 Position */ -#define GPIO_PORT_MASK7_MASKP20_Msk (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos) /*!< GPIO_PORT MASK7: MASKP20 Mask */ -#define GPIO_PORT_MASK7_MASKP21_Pos 21 /*!< GPIO_PORT MASK7: MASKP21 Position */ -#define GPIO_PORT_MASK7_MASKP21_Msk (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos) /*!< GPIO_PORT MASK7: MASKP21 Mask */ -#define GPIO_PORT_MASK7_MASKP22_Pos 22 /*!< GPIO_PORT MASK7: MASKP22 Position */ -#define GPIO_PORT_MASK7_MASKP22_Msk (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos) /*!< GPIO_PORT MASK7: MASKP22 Mask */ -#define GPIO_PORT_MASK7_MASKP23_Pos 23 /*!< GPIO_PORT MASK7: MASKP23 Position */ -#define GPIO_PORT_MASK7_MASKP23_Msk (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos) /*!< GPIO_PORT MASK7: MASKP23 Mask */ -#define GPIO_PORT_MASK7_MASKP24_Pos 24 /*!< GPIO_PORT MASK7: MASKP24 Position */ -#define GPIO_PORT_MASK7_MASKP24_Msk (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos) /*!< GPIO_PORT MASK7: MASKP24 Mask */ -#define GPIO_PORT_MASK7_MASKP25_Pos 25 /*!< GPIO_PORT MASK7: MASKP25 Position */ -#define GPIO_PORT_MASK7_MASKP25_Msk (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos) /*!< GPIO_PORT MASK7: MASKP25 Mask */ -#define GPIO_PORT_MASK7_MASKP26_Pos 26 /*!< GPIO_PORT MASK7: MASKP26 Position */ -#define GPIO_PORT_MASK7_MASKP26_Msk (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos) /*!< GPIO_PORT MASK7: MASKP26 Mask */ -#define GPIO_PORT_MASK7_MASKP27_Pos 27 /*!< GPIO_PORT MASK7: MASKP27 Position */ -#define GPIO_PORT_MASK7_MASKP27_Msk (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos) /*!< GPIO_PORT MASK7: MASKP27 Mask */ -#define GPIO_PORT_MASK7_MASKP28_Pos 28 /*!< GPIO_PORT MASK7: MASKP28 Position */ -#define GPIO_PORT_MASK7_MASKP28_Msk (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos) /*!< GPIO_PORT MASK7: MASKP28 Mask */ -#define GPIO_PORT_MASK7_MASKP29_Pos 29 /*!< GPIO_PORT MASK7: MASKP29 Position */ -#define GPIO_PORT_MASK7_MASKP29_Msk (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos) /*!< GPIO_PORT MASK7: MASKP29 Mask */ -#define GPIO_PORT_MASK7_MASKP30_Pos 30 /*!< GPIO_PORT MASK7: MASKP30 Position */ -#define GPIO_PORT_MASK7_MASKP30_Msk (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos) /*!< GPIO_PORT MASK7: MASKP30 Mask */ -#define GPIO_PORT_MASK7_MASKP31_Pos 31 /*!< GPIO_PORT MASK7: MASKP31 Position */ -#define GPIO_PORT_MASK7_MASKP31_Msk (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos) /*!< GPIO_PORT MASK7: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN0 ----------------------------------------- -#define GPIO_PORT_PIN0_PORT0_Pos 0 /*!< GPIO_PORT PIN0: PORT0 Position */ -#define GPIO_PORT_PIN0_PORT0_Msk (0x01UL << GPIO_PORT_PIN0_PORT0_Pos) /*!< GPIO_PORT PIN0: PORT0 Mask */ -#define GPIO_PORT_PIN0_PORT1_Pos 1 /*!< GPIO_PORT PIN0: PORT1 Position */ -#define GPIO_PORT_PIN0_PORT1_Msk (0x01UL << GPIO_PORT_PIN0_PORT1_Pos) /*!< GPIO_PORT PIN0: PORT1 Mask */ -#define GPIO_PORT_PIN0_PORT2_Pos 2 /*!< GPIO_PORT PIN0: PORT2 Position */ -#define GPIO_PORT_PIN0_PORT2_Msk (0x01UL << GPIO_PORT_PIN0_PORT2_Pos) /*!< GPIO_PORT PIN0: PORT2 Mask */ -#define GPIO_PORT_PIN0_PORT3_Pos 3 /*!< GPIO_PORT PIN0: PORT3 Position */ -#define GPIO_PORT_PIN0_PORT3_Msk (0x01UL << GPIO_PORT_PIN0_PORT3_Pos) /*!< GPIO_PORT PIN0: PORT3 Mask */ -#define GPIO_PORT_PIN0_PORT4_Pos 4 /*!< GPIO_PORT PIN0: PORT4 Position */ -#define GPIO_PORT_PIN0_PORT4_Msk (0x01UL << GPIO_PORT_PIN0_PORT4_Pos) /*!< GPIO_PORT PIN0: PORT4 Mask */ -#define GPIO_PORT_PIN0_PORT5_Pos 5 /*!< GPIO_PORT PIN0: PORT5 Position */ -#define GPIO_PORT_PIN0_PORT5_Msk (0x01UL << GPIO_PORT_PIN0_PORT5_Pos) /*!< GPIO_PORT PIN0: PORT5 Mask */ -#define GPIO_PORT_PIN0_PORT6_Pos 6 /*!< GPIO_PORT PIN0: PORT6 Position */ -#define GPIO_PORT_PIN0_PORT6_Msk (0x01UL << GPIO_PORT_PIN0_PORT6_Pos) /*!< GPIO_PORT PIN0: PORT6 Mask */ -#define GPIO_PORT_PIN0_PORT7_Pos 7 /*!< GPIO_PORT PIN0: PORT7 Position */ -#define GPIO_PORT_PIN0_PORT7_Msk (0x01UL << GPIO_PORT_PIN0_PORT7_Pos) /*!< GPIO_PORT PIN0: PORT7 Mask */ -#define GPIO_PORT_PIN0_PORT8_Pos 8 /*!< GPIO_PORT PIN0: PORT8 Position */ -#define GPIO_PORT_PIN0_PORT8_Msk (0x01UL << GPIO_PORT_PIN0_PORT8_Pos) /*!< GPIO_PORT PIN0: PORT8 Mask */ -#define GPIO_PORT_PIN0_PORT9_Pos 9 /*!< GPIO_PORT PIN0: PORT9 Position */ -#define GPIO_PORT_PIN0_PORT9_Msk (0x01UL << GPIO_PORT_PIN0_PORT9_Pos) /*!< GPIO_PORT PIN0: PORT9 Mask */ -#define GPIO_PORT_PIN0_PORT10_Pos 10 /*!< GPIO_PORT PIN0: PORT10 Position */ -#define GPIO_PORT_PIN0_PORT10_Msk (0x01UL << GPIO_PORT_PIN0_PORT10_Pos) /*!< GPIO_PORT PIN0: PORT10 Mask */ -#define GPIO_PORT_PIN0_PORT11_Pos 11 /*!< GPIO_PORT PIN0: PORT11 Position */ -#define GPIO_PORT_PIN0_PORT11_Msk (0x01UL << GPIO_PORT_PIN0_PORT11_Pos) /*!< GPIO_PORT PIN0: PORT11 Mask */ -#define GPIO_PORT_PIN0_PORT12_Pos 12 /*!< GPIO_PORT PIN0: PORT12 Position */ -#define GPIO_PORT_PIN0_PORT12_Msk (0x01UL << GPIO_PORT_PIN0_PORT12_Pos) /*!< GPIO_PORT PIN0: PORT12 Mask */ -#define GPIO_PORT_PIN0_PORT13_Pos 13 /*!< GPIO_PORT PIN0: PORT13 Position */ -#define GPIO_PORT_PIN0_PORT13_Msk (0x01UL << GPIO_PORT_PIN0_PORT13_Pos) /*!< GPIO_PORT PIN0: PORT13 Mask */ -#define GPIO_PORT_PIN0_PORT14_Pos 14 /*!< GPIO_PORT PIN0: PORT14 Position */ -#define GPIO_PORT_PIN0_PORT14_Msk (0x01UL << GPIO_PORT_PIN0_PORT14_Pos) /*!< GPIO_PORT PIN0: PORT14 Mask */ -#define GPIO_PORT_PIN0_PORT15_Pos 15 /*!< GPIO_PORT PIN0: PORT15 Position */ -#define GPIO_PORT_PIN0_PORT15_Msk (0x01UL << GPIO_PORT_PIN0_PORT15_Pos) /*!< GPIO_PORT PIN0: PORT15 Mask */ -#define GPIO_PORT_PIN0_PORT16_Pos 16 /*!< GPIO_PORT PIN0: PORT16 Position */ -#define GPIO_PORT_PIN0_PORT16_Msk (0x01UL << GPIO_PORT_PIN0_PORT16_Pos) /*!< GPIO_PORT PIN0: PORT16 Mask */ -#define GPIO_PORT_PIN0_PORT17_Pos 17 /*!< GPIO_PORT PIN0: PORT17 Position */ -#define GPIO_PORT_PIN0_PORT17_Msk (0x01UL << GPIO_PORT_PIN0_PORT17_Pos) /*!< GPIO_PORT PIN0: PORT17 Mask */ -#define GPIO_PORT_PIN0_PORT18_Pos 18 /*!< GPIO_PORT PIN0: PORT18 Position */ -#define GPIO_PORT_PIN0_PORT18_Msk (0x01UL << GPIO_PORT_PIN0_PORT18_Pos) /*!< GPIO_PORT PIN0: PORT18 Mask */ -#define GPIO_PORT_PIN0_PORT19_Pos 19 /*!< GPIO_PORT PIN0: PORT19 Position */ -#define GPIO_PORT_PIN0_PORT19_Msk (0x01UL << GPIO_PORT_PIN0_PORT19_Pos) /*!< GPIO_PORT PIN0: PORT19 Mask */ -#define GPIO_PORT_PIN0_PORT20_Pos 20 /*!< GPIO_PORT PIN0: PORT20 Position */ -#define GPIO_PORT_PIN0_PORT20_Msk (0x01UL << GPIO_PORT_PIN0_PORT20_Pos) /*!< GPIO_PORT PIN0: PORT20 Mask */ -#define GPIO_PORT_PIN0_PORT21_Pos 21 /*!< GPIO_PORT PIN0: PORT21 Position */ -#define GPIO_PORT_PIN0_PORT21_Msk (0x01UL << GPIO_PORT_PIN0_PORT21_Pos) /*!< GPIO_PORT PIN0: PORT21 Mask */ -#define GPIO_PORT_PIN0_PORT22_Pos 22 /*!< GPIO_PORT PIN0: PORT22 Position */ -#define GPIO_PORT_PIN0_PORT22_Msk (0x01UL << GPIO_PORT_PIN0_PORT22_Pos) /*!< GPIO_PORT PIN0: PORT22 Mask */ -#define GPIO_PORT_PIN0_PORT23_Pos 23 /*!< GPIO_PORT PIN0: PORT23 Position */ -#define GPIO_PORT_PIN0_PORT23_Msk (0x01UL << GPIO_PORT_PIN0_PORT23_Pos) /*!< GPIO_PORT PIN0: PORT23 Mask */ -#define GPIO_PORT_PIN0_PORT24_Pos 24 /*!< GPIO_PORT PIN0: PORT24 Position */ -#define GPIO_PORT_PIN0_PORT24_Msk (0x01UL << GPIO_PORT_PIN0_PORT24_Pos) /*!< GPIO_PORT PIN0: PORT24 Mask */ -#define GPIO_PORT_PIN0_PORT25_Pos 25 /*!< GPIO_PORT PIN0: PORT25 Position */ -#define GPIO_PORT_PIN0_PORT25_Msk (0x01UL << GPIO_PORT_PIN0_PORT25_Pos) /*!< GPIO_PORT PIN0: PORT25 Mask */ -#define GPIO_PORT_PIN0_PORT26_Pos 26 /*!< GPIO_PORT PIN0: PORT26 Position */ -#define GPIO_PORT_PIN0_PORT26_Msk (0x01UL << GPIO_PORT_PIN0_PORT26_Pos) /*!< GPIO_PORT PIN0: PORT26 Mask */ -#define GPIO_PORT_PIN0_PORT27_Pos 27 /*!< GPIO_PORT PIN0: PORT27 Position */ -#define GPIO_PORT_PIN0_PORT27_Msk (0x01UL << GPIO_PORT_PIN0_PORT27_Pos) /*!< GPIO_PORT PIN0: PORT27 Mask */ -#define GPIO_PORT_PIN0_PORT28_Pos 28 /*!< GPIO_PORT PIN0: PORT28 Position */ -#define GPIO_PORT_PIN0_PORT28_Msk (0x01UL << GPIO_PORT_PIN0_PORT28_Pos) /*!< GPIO_PORT PIN0: PORT28 Mask */ -#define GPIO_PORT_PIN0_PORT29_Pos 29 /*!< GPIO_PORT PIN0: PORT29 Position */ -#define GPIO_PORT_PIN0_PORT29_Msk (0x01UL << GPIO_PORT_PIN0_PORT29_Pos) /*!< GPIO_PORT PIN0: PORT29 Mask */ -#define GPIO_PORT_PIN0_PORT30_Pos 30 /*!< GPIO_PORT PIN0: PORT30 Position */ -#define GPIO_PORT_PIN0_PORT30_Msk (0x01UL << GPIO_PORT_PIN0_PORT30_Pos) /*!< GPIO_PORT PIN0: PORT30 Mask */ -#define GPIO_PORT_PIN0_PORT31_Pos 31 /*!< GPIO_PORT PIN0: PORT31 Position */ -#define GPIO_PORT_PIN0_PORT31_Msk (0x01UL << GPIO_PORT_PIN0_PORT31_Pos) /*!< GPIO_PORT PIN0: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN1 ----------------------------------------- -#define GPIO_PORT_PIN1_PORT0_Pos 0 /*!< GPIO_PORT PIN1: PORT0 Position */ -#define GPIO_PORT_PIN1_PORT0_Msk (0x01UL << GPIO_PORT_PIN1_PORT0_Pos) /*!< GPIO_PORT PIN1: PORT0 Mask */ -#define GPIO_PORT_PIN1_PORT1_Pos 1 /*!< GPIO_PORT PIN1: PORT1 Position */ -#define GPIO_PORT_PIN1_PORT1_Msk (0x01UL << GPIO_PORT_PIN1_PORT1_Pos) /*!< GPIO_PORT PIN1: PORT1 Mask */ -#define GPIO_PORT_PIN1_PORT2_Pos 2 /*!< GPIO_PORT PIN1: PORT2 Position */ -#define GPIO_PORT_PIN1_PORT2_Msk (0x01UL << GPIO_PORT_PIN1_PORT2_Pos) /*!< GPIO_PORT PIN1: PORT2 Mask */ -#define GPIO_PORT_PIN1_PORT3_Pos 3 /*!< GPIO_PORT PIN1: PORT3 Position */ -#define GPIO_PORT_PIN1_PORT3_Msk (0x01UL << GPIO_PORT_PIN1_PORT3_Pos) /*!< GPIO_PORT PIN1: PORT3 Mask */ -#define GPIO_PORT_PIN1_PORT4_Pos 4 /*!< GPIO_PORT PIN1: PORT4 Position */ -#define GPIO_PORT_PIN1_PORT4_Msk (0x01UL << GPIO_PORT_PIN1_PORT4_Pos) /*!< GPIO_PORT PIN1: PORT4 Mask */ -#define GPIO_PORT_PIN1_PORT5_Pos 5 /*!< GPIO_PORT PIN1: PORT5 Position */ -#define GPIO_PORT_PIN1_PORT5_Msk (0x01UL << GPIO_PORT_PIN1_PORT5_Pos) /*!< GPIO_PORT PIN1: PORT5 Mask */ -#define GPIO_PORT_PIN1_PORT6_Pos 6 /*!< GPIO_PORT PIN1: PORT6 Position */ -#define GPIO_PORT_PIN1_PORT6_Msk (0x01UL << GPIO_PORT_PIN1_PORT6_Pos) /*!< GPIO_PORT PIN1: PORT6 Mask */ -#define GPIO_PORT_PIN1_PORT7_Pos 7 /*!< GPIO_PORT PIN1: PORT7 Position */ -#define GPIO_PORT_PIN1_PORT7_Msk (0x01UL << GPIO_PORT_PIN1_PORT7_Pos) /*!< GPIO_PORT PIN1: PORT7 Mask */ -#define GPIO_PORT_PIN1_PORT8_Pos 8 /*!< GPIO_PORT PIN1: PORT8 Position */ -#define GPIO_PORT_PIN1_PORT8_Msk (0x01UL << GPIO_PORT_PIN1_PORT8_Pos) /*!< GPIO_PORT PIN1: PORT8 Mask */ -#define GPIO_PORT_PIN1_PORT9_Pos 9 /*!< GPIO_PORT PIN1: PORT9 Position */ -#define GPIO_PORT_PIN1_PORT9_Msk (0x01UL << GPIO_PORT_PIN1_PORT9_Pos) /*!< GPIO_PORT PIN1: PORT9 Mask */ -#define GPIO_PORT_PIN1_PORT10_Pos 10 /*!< GPIO_PORT PIN1: PORT10 Position */ -#define GPIO_PORT_PIN1_PORT10_Msk (0x01UL << GPIO_PORT_PIN1_PORT10_Pos) /*!< GPIO_PORT PIN1: PORT10 Mask */ -#define GPIO_PORT_PIN1_PORT11_Pos 11 /*!< GPIO_PORT PIN1: PORT11 Position */ -#define GPIO_PORT_PIN1_PORT11_Msk (0x01UL << GPIO_PORT_PIN1_PORT11_Pos) /*!< GPIO_PORT PIN1: PORT11 Mask */ -#define GPIO_PORT_PIN1_PORT12_Pos 12 /*!< GPIO_PORT PIN1: PORT12 Position */ -#define GPIO_PORT_PIN1_PORT12_Msk (0x01UL << GPIO_PORT_PIN1_PORT12_Pos) /*!< GPIO_PORT PIN1: PORT12 Mask */ -#define GPIO_PORT_PIN1_PORT13_Pos 13 /*!< GPIO_PORT PIN1: PORT13 Position */ -#define GPIO_PORT_PIN1_PORT13_Msk (0x01UL << GPIO_PORT_PIN1_PORT13_Pos) /*!< GPIO_PORT PIN1: PORT13 Mask */ -#define GPIO_PORT_PIN1_PORT14_Pos 14 /*!< GPIO_PORT PIN1: PORT14 Position */ -#define GPIO_PORT_PIN1_PORT14_Msk (0x01UL << GPIO_PORT_PIN1_PORT14_Pos) /*!< GPIO_PORT PIN1: PORT14 Mask */ -#define GPIO_PORT_PIN1_PORT15_Pos 15 /*!< GPIO_PORT PIN1: PORT15 Position */ -#define GPIO_PORT_PIN1_PORT15_Msk (0x01UL << GPIO_PORT_PIN1_PORT15_Pos) /*!< GPIO_PORT PIN1: PORT15 Mask */ -#define GPIO_PORT_PIN1_PORT16_Pos 16 /*!< GPIO_PORT PIN1: PORT16 Position */ -#define GPIO_PORT_PIN1_PORT16_Msk (0x01UL << GPIO_PORT_PIN1_PORT16_Pos) /*!< GPIO_PORT PIN1: PORT16 Mask */ -#define GPIO_PORT_PIN1_PORT17_Pos 17 /*!< GPIO_PORT PIN1: PORT17 Position */ -#define GPIO_PORT_PIN1_PORT17_Msk (0x01UL << GPIO_PORT_PIN1_PORT17_Pos) /*!< GPIO_PORT PIN1: PORT17 Mask */ -#define GPIO_PORT_PIN1_PORT18_Pos 18 /*!< GPIO_PORT PIN1: PORT18 Position */ -#define GPIO_PORT_PIN1_PORT18_Msk (0x01UL << GPIO_PORT_PIN1_PORT18_Pos) /*!< GPIO_PORT PIN1: PORT18 Mask */ -#define GPIO_PORT_PIN1_PORT19_Pos 19 /*!< GPIO_PORT PIN1: PORT19 Position */ -#define GPIO_PORT_PIN1_PORT19_Msk (0x01UL << GPIO_PORT_PIN1_PORT19_Pos) /*!< GPIO_PORT PIN1: PORT19 Mask */ -#define GPIO_PORT_PIN1_PORT20_Pos 20 /*!< GPIO_PORT PIN1: PORT20 Position */ -#define GPIO_PORT_PIN1_PORT20_Msk (0x01UL << GPIO_PORT_PIN1_PORT20_Pos) /*!< GPIO_PORT PIN1: PORT20 Mask */ -#define GPIO_PORT_PIN1_PORT21_Pos 21 /*!< GPIO_PORT PIN1: PORT21 Position */ -#define GPIO_PORT_PIN1_PORT21_Msk (0x01UL << GPIO_PORT_PIN1_PORT21_Pos) /*!< GPIO_PORT PIN1: PORT21 Mask */ -#define GPIO_PORT_PIN1_PORT22_Pos 22 /*!< GPIO_PORT PIN1: PORT22 Position */ -#define GPIO_PORT_PIN1_PORT22_Msk (0x01UL << GPIO_PORT_PIN1_PORT22_Pos) /*!< GPIO_PORT PIN1: PORT22 Mask */ -#define GPIO_PORT_PIN1_PORT23_Pos 23 /*!< GPIO_PORT PIN1: PORT23 Position */ -#define GPIO_PORT_PIN1_PORT23_Msk (0x01UL << GPIO_PORT_PIN1_PORT23_Pos) /*!< GPIO_PORT PIN1: PORT23 Mask */ -#define GPIO_PORT_PIN1_PORT24_Pos 24 /*!< GPIO_PORT PIN1: PORT24 Position */ -#define GPIO_PORT_PIN1_PORT24_Msk (0x01UL << GPIO_PORT_PIN1_PORT24_Pos) /*!< GPIO_PORT PIN1: PORT24 Mask */ -#define GPIO_PORT_PIN1_PORT25_Pos 25 /*!< GPIO_PORT PIN1: PORT25 Position */ -#define GPIO_PORT_PIN1_PORT25_Msk (0x01UL << GPIO_PORT_PIN1_PORT25_Pos) /*!< GPIO_PORT PIN1: PORT25 Mask */ -#define GPIO_PORT_PIN1_PORT26_Pos 26 /*!< GPIO_PORT PIN1: PORT26 Position */ -#define GPIO_PORT_PIN1_PORT26_Msk (0x01UL << GPIO_PORT_PIN1_PORT26_Pos) /*!< GPIO_PORT PIN1: PORT26 Mask */ -#define GPIO_PORT_PIN1_PORT27_Pos 27 /*!< GPIO_PORT PIN1: PORT27 Position */ -#define GPIO_PORT_PIN1_PORT27_Msk (0x01UL << GPIO_PORT_PIN1_PORT27_Pos) /*!< GPIO_PORT PIN1: PORT27 Mask */ -#define GPIO_PORT_PIN1_PORT28_Pos 28 /*!< GPIO_PORT PIN1: PORT28 Position */ -#define GPIO_PORT_PIN1_PORT28_Msk (0x01UL << GPIO_PORT_PIN1_PORT28_Pos) /*!< GPIO_PORT PIN1: PORT28 Mask */ -#define GPIO_PORT_PIN1_PORT29_Pos 29 /*!< GPIO_PORT PIN1: PORT29 Position */ -#define GPIO_PORT_PIN1_PORT29_Msk (0x01UL << GPIO_PORT_PIN1_PORT29_Pos) /*!< GPIO_PORT PIN1: PORT29 Mask */ -#define GPIO_PORT_PIN1_PORT30_Pos 30 /*!< GPIO_PORT PIN1: PORT30 Position */ -#define GPIO_PORT_PIN1_PORT30_Msk (0x01UL << GPIO_PORT_PIN1_PORT30_Pos) /*!< GPIO_PORT PIN1: PORT30 Mask */ -#define GPIO_PORT_PIN1_PORT31_Pos 31 /*!< GPIO_PORT PIN1: PORT31 Position */ -#define GPIO_PORT_PIN1_PORT31_Msk (0x01UL << GPIO_PORT_PIN1_PORT31_Pos) /*!< GPIO_PORT PIN1: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN2 ----------------------------------------- -#define GPIO_PORT_PIN2_PORT0_Pos 0 /*!< GPIO_PORT PIN2: PORT0 Position */ -#define GPIO_PORT_PIN2_PORT0_Msk (0x01UL << GPIO_PORT_PIN2_PORT0_Pos) /*!< GPIO_PORT PIN2: PORT0 Mask */ -#define GPIO_PORT_PIN2_PORT1_Pos 1 /*!< GPIO_PORT PIN2: PORT1 Position */ -#define GPIO_PORT_PIN2_PORT1_Msk (0x01UL << GPIO_PORT_PIN2_PORT1_Pos) /*!< GPIO_PORT PIN2: PORT1 Mask */ -#define GPIO_PORT_PIN2_PORT2_Pos 2 /*!< GPIO_PORT PIN2: PORT2 Position */ -#define GPIO_PORT_PIN2_PORT2_Msk (0x01UL << GPIO_PORT_PIN2_PORT2_Pos) /*!< GPIO_PORT PIN2: PORT2 Mask */ -#define GPIO_PORT_PIN2_PORT3_Pos 3 /*!< GPIO_PORT PIN2: PORT3 Position */ -#define GPIO_PORT_PIN2_PORT3_Msk (0x01UL << GPIO_PORT_PIN2_PORT3_Pos) /*!< GPIO_PORT PIN2: PORT3 Mask */ -#define GPIO_PORT_PIN2_PORT4_Pos 4 /*!< GPIO_PORT PIN2: PORT4 Position */ -#define GPIO_PORT_PIN2_PORT4_Msk (0x01UL << GPIO_PORT_PIN2_PORT4_Pos) /*!< GPIO_PORT PIN2: PORT4 Mask */ -#define GPIO_PORT_PIN2_PORT5_Pos 5 /*!< GPIO_PORT PIN2: PORT5 Position */ -#define GPIO_PORT_PIN2_PORT5_Msk (0x01UL << GPIO_PORT_PIN2_PORT5_Pos) /*!< GPIO_PORT PIN2: PORT5 Mask */ -#define GPIO_PORT_PIN2_PORT6_Pos 6 /*!< GPIO_PORT PIN2: PORT6 Position */ -#define GPIO_PORT_PIN2_PORT6_Msk (0x01UL << GPIO_PORT_PIN2_PORT6_Pos) /*!< GPIO_PORT PIN2: PORT6 Mask */ -#define GPIO_PORT_PIN2_PORT7_Pos 7 /*!< GPIO_PORT PIN2: PORT7 Position */ -#define GPIO_PORT_PIN2_PORT7_Msk (0x01UL << GPIO_PORT_PIN2_PORT7_Pos) /*!< GPIO_PORT PIN2: PORT7 Mask */ -#define GPIO_PORT_PIN2_PORT8_Pos 8 /*!< GPIO_PORT PIN2: PORT8 Position */ -#define GPIO_PORT_PIN2_PORT8_Msk (0x01UL << GPIO_PORT_PIN2_PORT8_Pos) /*!< GPIO_PORT PIN2: PORT8 Mask */ -#define GPIO_PORT_PIN2_PORT9_Pos 9 /*!< GPIO_PORT PIN2: PORT9 Position */ -#define GPIO_PORT_PIN2_PORT9_Msk (0x01UL << GPIO_PORT_PIN2_PORT9_Pos) /*!< GPIO_PORT PIN2: PORT9 Mask */ -#define GPIO_PORT_PIN2_PORT10_Pos 10 /*!< GPIO_PORT PIN2: PORT10 Position */ -#define GPIO_PORT_PIN2_PORT10_Msk (0x01UL << GPIO_PORT_PIN2_PORT10_Pos) /*!< GPIO_PORT PIN2: PORT10 Mask */ -#define GPIO_PORT_PIN2_PORT11_Pos 11 /*!< GPIO_PORT PIN2: PORT11 Position */ -#define GPIO_PORT_PIN2_PORT11_Msk (0x01UL << GPIO_PORT_PIN2_PORT11_Pos) /*!< GPIO_PORT PIN2: PORT11 Mask */ -#define GPIO_PORT_PIN2_PORT12_Pos 12 /*!< GPIO_PORT PIN2: PORT12 Position */ -#define GPIO_PORT_PIN2_PORT12_Msk (0x01UL << GPIO_PORT_PIN2_PORT12_Pos) /*!< GPIO_PORT PIN2: PORT12 Mask */ -#define GPIO_PORT_PIN2_PORT13_Pos 13 /*!< GPIO_PORT PIN2: PORT13 Position */ -#define GPIO_PORT_PIN2_PORT13_Msk (0x01UL << GPIO_PORT_PIN2_PORT13_Pos) /*!< GPIO_PORT PIN2: PORT13 Mask */ -#define GPIO_PORT_PIN2_PORT14_Pos 14 /*!< GPIO_PORT PIN2: PORT14 Position */ -#define GPIO_PORT_PIN2_PORT14_Msk (0x01UL << GPIO_PORT_PIN2_PORT14_Pos) /*!< GPIO_PORT PIN2: PORT14 Mask */ -#define GPIO_PORT_PIN2_PORT15_Pos 15 /*!< GPIO_PORT PIN2: PORT15 Position */ -#define GPIO_PORT_PIN2_PORT15_Msk (0x01UL << GPIO_PORT_PIN2_PORT15_Pos) /*!< GPIO_PORT PIN2: PORT15 Mask */ -#define GPIO_PORT_PIN2_PORT16_Pos 16 /*!< GPIO_PORT PIN2: PORT16 Position */ -#define GPIO_PORT_PIN2_PORT16_Msk (0x01UL << GPIO_PORT_PIN2_PORT16_Pos) /*!< GPIO_PORT PIN2: PORT16 Mask */ -#define GPIO_PORT_PIN2_PORT17_Pos 17 /*!< GPIO_PORT PIN2: PORT17 Position */ -#define GPIO_PORT_PIN2_PORT17_Msk (0x01UL << GPIO_PORT_PIN2_PORT17_Pos) /*!< GPIO_PORT PIN2: PORT17 Mask */ -#define GPIO_PORT_PIN2_PORT18_Pos 18 /*!< GPIO_PORT PIN2: PORT18 Position */ -#define GPIO_PORT_PIN2_PORT18_Msk (0x01UL << GPIO_PORT_PIN2_PORT18_Pos) /*!< GPIO_PORT PIN2: PORT18 Mask */ -#define GPIO_PORT_PIN2_PORT19_Pos 19 /*!< GPIO_PORT PIN2: PORT19 Position */ -#define GPIO_PORT_PIN2_PORT19_Msk (0x01UL << GPIO_PORT_PIN2_PORT19_Pos) /*!< GPIO_PORT PIN2: PORT19 Mask */ -#define GPIO_PORT_PIN2_PORT20_Pos 20 /*!< GPIO_PORT PIN2: PORT20 Position */ -#define GPIO_PORT_PIN2_PORT20_Msk (0x01UL << GPIO_PORT_PIN2_PORT20_Pos) /*!< GPIO_PORT PIN2: PORT20 Mask */ -#define GPIO_PORT_PIN2_PORT21_Pos 21 /*!< GPIO_PORT PIN2: PORT21 Position */ -#define GPIO_PORT_PIN2_PORT21_Msk (0x01UL << GPIO_PORT_PIN2_PORT21_Pos) /*!< GPIO_PORT PIN2: PORT21 Mask */ -#define GPIO_PORT_PIN2_PORT22_Pos 22 /*!< GPIO_PORT PIN2: PORT22 Position */ -#define GPIO_PORT_PIN2_PORT22_Msk (0x01UL << GPIO_PORT_PIN2_PORT22_Pos) /*!< GPIO_PORT PIN2: PORT22 Mask */ -#define GPIO_PORT_PIN2_PORT23_Pos 23 /*!< GPIO_PORT PIN2: PORT23 Position */ -#define GPIO_PORT_PIN2_PORT23_Msk (0x01UL << GPIO_PORT_PIN2_PORT23_Pos) /*!< GPIO_PORT PIN2: PORT23 Mask */ -#define GPIO_PORT_PIN2_PORT24_Pos 24 /*!< GPIO_PORT PIN2: PORT24 Position */ -#define GPIO_PORT_PIN2_PORT24_Msk (0x01UL << GPIO_PORT_PIN2_PORT24_Pos) /*!< GPIO_PORT PIN2: PORT24 Mask */ -#define GPIO_PORT_PIN2_PORT25_Pos 25 /*!< GPIO_PORT PIN2: PORT25 Position */ -#define GPIO_PORT_PIN2_PORT25_Msk (0x01UL << GPIO_PORT_PIN2_PORT25_Pos) /*!< GPIO_PORT PIN2: PORT25 Mask */ -#define GPIO_PORT_PIN2_PORT26_Pos 26 /*!< GPIO_PORT PIN2: PORT26 Position */ -#define GPIO_PORT_PIN2_PORT26_Msk (0x01UL << GPIO_PORT_PIN2_PORT26_Pos) /*!< GPIO_PORT PIN2: PORT26 Mask */ -#define GPIO_PORT_PIN2_PORT27_Pos 27 /*!< GPIO_PORT PIN2: PORT27 Position */ -#define GPIO_PORT_PIN2_PORT27_Msk (0x01UL << GPIO_PORT_PIN2_PORT27_Pos) /*!< GPIO_PORT PIN2: PORT27 Mask */ -#define GPIO_PORT_PIN2_PORT28_Pos 28 /*!< GPIO_PORT PIN2: PORT28 Position */ -#define GPIO_PORT_PIN2_PORT28_Msk (0x01UL << GPIO_PORT_PIN2_PORT28_Pos) /*!< GPIO_PORT PIN2: PORT28 Mask */ -#define GPIO_PORT_PIN2_PORT29_Pos 29 /*!< GPIO_PORT PIN2: PORT29 Position */ -#define GPIO_PORT_PIN2_PORT29_Msk (0x01UL << GPIO_PORT_PIN2_PORT29_Pos) /*!< GPIO_PORT PIN2: PORT29 Mask */ -#define GPIO_PORT_PIN2_PORT30_Pos 30 /*!< GPIO_PORT PIN2: PORT30 Position */ -#define GPIO_PORT_PIN2_PORT30_Msk (0x01UL << GPIO_PORT_PIN2_PORT30_Pos) /*!< GPIO_PORT PIN2: PORT30 Mask */ -#define GPIO_PORT_PIN2_PORT31_Pos 31 /*!< GPIO_PORT PIN2: PORT31 Position */ -#define GPIO_PORT_PIN2_PORT31_Msk (0x01UL << GPIO_PORT_PIN2_PORT31_Pos) /*!< GPIO_PORT PIN2: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN3 ----------------------------------------- -#define GPIO_PORT_PIN3_PORT0_Pos 0 /*!< GPIO_PORT PIN3: PORT0 Position */ -#define GPIO_PORT_PIN3_PORT0_Msk (0x01UL << GPIO_PORT_PIN3_PORT0_Pos) /*!< GPIO_PORT PIN3: PORT0 Mask */ -#define GPIO_PORT_PIN3_PORT1_Pos 1 /*!< GPIO_PORT PIN3: PORT1 Position */ -#define GPIO_PORT_PIN3_PORT1_Msk (0x01UL << GPIO_PORT_PIN3_PORT1_Pos) /*!< GPIO_PORT PIN3: PORT1 Mask */ -#define GPIO_PORT_PIN3_PORT2_Pos 2 /*!< GPIO_PORT PIN3: PORT2 Position */ -#define GPIO_PORT_PIN3_PORT2_Msk (0x01UL << GPIO_PORT_PIN3_PORT2_Pos) /*!< GPIO_PORT PIN3: PORT2 Mask */ -#define GPIO_PORT_PIN3_PORT3_Pos 3 /*!< GPIO_PORT PIN3: PORT3 Position */ -#define GPIO_PORT_PIN3_PORT3_Msk (0x01UL << GPIO_PORT_PIN3_PORT3_Pos) /*!< GPIO_PORT PIN3: PORT3 Mask */ -#define GPIO_PORT_PIN3_PORT4_Pos 4 /*!< GPIO_PORT PIN3: PORT4 Position */ -#define GPIO_PORT_PIN3_PORT4_Msk (0x01UL << GPIO_PORT_PIN3_PORT4_Pos) /*!< GPIO_PORT PIN3: PORT4 Mask */ -#define GPIO_PORT_PIN3_PORT5_Pos 5 /*!< GPIO_PORT PIN3: PORT5 Position */ -#define GPIO_PORT_PIN3_PORT5_Msk (0x01UL << GPIO_PORT_PIN3_PORT5_Pos) /*!< GPIO_PORT PIN3: PORT5 Mask */ -#define GPIO_PORT_PIN3_PORT6_Pos 6 /*!< GPIO_PORT PIN3: PORT6 Position */ -#define GPIO_PORT_PIN3_PORT6_Msk (0x01UL << GPIO_PORT_PIN3_PORT6_Pos) /*!< GPIO_PORT PIN3: PORT6 Mask */ -#define GPIO_PORT_PIN3_PORT7_Pos 7 /*!< GPIO_PORT PIN3: PORT7 Position */ -#define GPIO_PORT_PIN3_PORT7_Msk (0x01UL << GPIO_PORT_PIN3_PORT7_Pos) /*!< GPIO_PORT PIN3: PORT7 Mask */ -#define GPIO_PORT_PIN3_PORT8_Pos 8 /*!< GPIO_PORT PIN3: PORT8 Position */ -#define GPIO_PORT_PIN3_PORT8_Msk (0x01UL << GPIO_PORT_PIN3_PORT8_Pos) /*!< GPIO_PORT PIN3: PORT8 Mask */ -#define GPIO_PORT_PIN3_PORT9_Pos 9 /*!< GPIO_PORT PIN3: PORT9 Position */ -#define GPIO_PORT_PIN3_PORT9_Msk (0x01UL << GPIO_PORT_PIN3_PORT9_Pos) /*!< GPIO_PORT PIN3: PORT9 Mask */ -#define GPIO_PORT_PIN3_PORT10_Pos 10 /*!< GPIO_PORT PIN3: PORT10 Position */ -#define GPIO_PORT_PIN3_PORT10_Msk (0x01UL << GPIO_PORT_PIN3_PORT10_Pos) /*!< GPIO_PORT PIN3: PORT10 Mask */ -#define GPIO_PORT_PIN3_PORT11_Pos 11 /*!< GPIO_PORT PIN3: PORT11 Position */ -#define GPIO_PORT_PIN3_PORT11_Msk (0x01UL << GPIO_PORT_PIN3_PORT11_Pos) /*!< GPIO_PORT PIN3: PORT11 Mask */ -#define GPIO_PORT_PIN3_PORT12_Pos 12 /*!< GPIO_PORT PIN3: PORT12 Position */ -#define GPIO_PORT_PIN3_PORT12_Msk (0x01UL << GPIO_PORT_PIN3_PORT12_Pos) /*!< GPIO_PORT PIN3: PORT12 Mask */ -#define GPIO_PORT_PIN3_PORT13_Pos 13 /*!< GPIO_PORT PIN3: PORT13 Position */ -#define GPIO_PORT_PIN3_PORT13_Msk (0x01UL << GPIO_PORT_PIN3_PORT13_Pos) /*!< GPIO_PORT PIN3: PORT13 Mask */ -#define GPIO_PORT_PIN3_PORT14_Pos 14 /*!< GPIO_PORT PIN3: PORT14 Position */ -#define GPIO_PORT_PIN3_PORT14_Msk (0x01UL << GPIO_PORT_PIN3_PORT14_Pos) /*!< GPIO_PORT PIN3: PORT14 Mask */ -#define GPIO_PORT_PIN3_PORT15_Pos 15 /*!< GPIO_PORT PIN3: PORT15 Position */ -#define GPIO_PORT_PIN3_PORT15_Msk (0x01UL << GPIO_PORT_PIN3_PORT15_Pos) /*!< GPIO_PORT PIN3: PORT15 Mask */ -#define GPIO_PORT_PIN3_PORT16_Pos 16 /*!< GPIO_PORT PIN3: PORT16 Position */ -#define GPIO_PORT_PIN3_PORT16_Msk (0x01UL << GPIO_PORT_PIN3_PORT16_Pos) /*!< GPIO_PORT PIN3: PORT16 Mask */ -#define GPIO_PORT_PIN3_PORT17_Pos 17 /*!< GPIO_PORT PIN3: PORT17 Position */ -#define GPIO_PORT_PIN3_PORT17_Msk (0x01UL << GPIO_PORT_PIN3_PORT17_Pos) /*!< GPIO_PORT PIN3: PORT17 Mask */ -#define GPIO_PORT_PIN3_PORT18_Pos 18 /*!< GPIO_PORT PIN3: PORT18 Position */ -#define GPIO_PORT_PIN3_PORT18_Msk (0x01UL << GPIO_PORT_PIN3_PORT18_Pos) /*!< GPIO_PORT PIN3: PORT18 Mask */ -#define GPIO_PORT_PIN3_PORT19_Pos 19 /*!< GPIO_PORT PIN3: PORT19 Position */ -#define GPIO_PORT_PIN3_PORT19_Msk (0x01UL << GPIO_PORT_PIN3_PORT19_Pos) /*!< GPIO_PORT PIN3: PORT19 Mask */ -#define GPIO_PORT_PIN3_PORT20_Pos 20 /*!< GPIO_PORT PIN3: PORT20 Position */ -#define GPIO_PORT_PIN3_PORT20_Msk (0x01UL << GPIO_PORT_PIN3_PORT20_Pos) /*!< GPIO_PORT PIN3: PORT20 Mask */ -#define GPIO_PORT_PIN3_PORT21_Pos 21 /*!< GPIO_PORT PIN3: PORT21 Position */ -#define GPIO_PORT_PIN3_PORT21_Msk (0x01UL << GPIO_PORT_PIN3_PORT21_Pos) /*!< GPIO_PORT PIN3: PORT21 Mask */ -#define GPIO_PORT_PIN3_PORT22_Pos 22 /*!< GPIO_PORT PIN3: PORT22 Position */ -#define GPIO_PORT_PIN3_PORT22_Msk (0x01UL << GPIO_PORT_PIN3_PORT22_Pos) /*!< GPIO_PORT PIN3: PORT22 Mask */ -#define GPIO_PORT_PIN3_PORT23_Pos 23 /*!< GPIO_PORT PIN3: PORT23 Position */ -#define GPIO_PORT_PIN3_PORT23_Msk (0x01UL << GPIO_PORT_PIN3_PORT23_Pos) /*!< GPIO_PORT PIN3: PORT23 Mask */ -#define GPIO_PORT_PIN3_PORT24_Pos 24 /*!< GPIO_PORT PIN3: PORT24 Position */ -#define GPIO_PORT_PIN3_PORT24_Msk (0x01UL << GPIO_PORT_PIN3_PORT24_Pos) /*!< GPIO_PORT PIN3: PORT24 Mask */ -#define GPIO_PORT_PIN3_PORT25_Pos 25 /*!< GPIO_PORT PIN3: PORT25 Position */ -#define GPIO_PORT_PIN3_PORT25_Msk (0x01UL << GPIO_PORT_PIN3_PORT25_Pos) /*!< GPIO_PORT PIN3: PORT25 Mask */ -#define GPIO_PORT_PIN3_PORT26_Pos 26 /*!< GPIO_PORT PIN3: PORT26 Position */ -#define GPIO_PORT_PIN3_PORT26_Msk (0x01UL << GPIO_PORT_PIN3_PORT26_Pos) /*!< GPIO_PORT PIN3: PORT26 Mask */ -#define GPIO_PORT_PIN3_PORT27_Pos 27 /*!< GPIO_PORT PIN3: PORT27 Position */ -#define GPIO_PORT_PIN3_PORT27_Msk (0x01UL << GPIO_PORT_PIN3_PORT27_Pos) /*!< GPIO_PORT PIN3: PORT27 Mask */ -#define GPIO_PORT_PIN3_PORT28_Pos 28 /*!< GPIO_PORT PIN3: PORT28 Position */ -#define GPIO_PORT_PIN3_PORT28_Msk (0x01UL << GPIO_PORT_PIN3_PORT28_Pos) /*!< GPIO_PORT PIN3: PORT28 Mask */ -#define GPIO_PORT_PIN3_PORT29_Pos 29 /*!< GPIO_PORT PIN3: PORT29 Position */ -#define GPIO_PORT_PIN3_PORT29_Msk (0x01UL << GPIO_PORT_PIN3_PORT29_Pos) /*!< GPIO_PORT PIN3: PORT29 Mask */ -#define GPIO_PORT_PIN3_PORT30_Pos 30 /*!< GPIO_PORT PIN3: PORT30 Position */ -#define GPIO_PORT_PIN3_PORT30_Msk (0x01UL << GPIO_PORT_PIN3_PORT30_Pos) /*!< GPIO_PORT PIN3: PORT30 Mask */ -#define GPIO_PORT_PIN3_PORT31_Pos 31 /*!< GPIO_PORT PIN3: PORT31 Position */ -#define GPIO_PORT_PIN3_PORT31_Msk (0x01UL << GPIO_PORT_PIN3_PORT31_Pos) /*!< GPIO_PORT PIN3: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN4 ----------------------------------------- -#define GPIO_PORT_PIN4_PORT0_Pos 0 /*!< GPIO_PORT PIN4: PORT0 Position */ -#define GPIO_PORT_PIN4_PORT0_Msk (0x01UL << GPIO_PORT_PIN4_PORT0_Pos) /*!< GPIO_PORT PIN4: PORT0 Mask */ -#define GPIO_PORT_PIN4_PORT1_Pos 1 /*!< GPIO_PORT PIN4: PORT1 Position */ -#define GPIO_PORT_PIN4_PORT1_Msk (0x01UL << GPIO_PORT_PIN4_PORT1_Pos) /*!< GPIO_PORT PIN4: PORT1 Mask */ -#define GPIO_PORT_PIN4_PORT2_Pos 2 /*!< GPIO_PORT PIN4: PORT2 Position */ -#define GPIO_PORT_PIN4_PORT2_Msk (0x01UL << GPIO_PORT_PIN4_PORT2_Pos) /*!< GPIO_PORT PIN4: PORT2 Mask */ -#define GPIO_PORT_PIN4_PORT3_Pos 3 /*!< GPIO_PORT PIN4: PORT3 Position */ -#define GPIO_PORT_PIN4_PORT3_Msk (0x01UL << GPIO_PORT_PIN4_PORT3_Pos) /*!< GPIO_PORT PIN4: PORT3 Mask */ -#define GPIO_PORT_PIN4_PORT4_Pos 4 /*!< GPIO_PORT PIN4: PORT4 Position */ -#define GPIO_PORT_PIN4_PORT4_Msk (0x01UL << GPIO_PORT_PIN4_PORT4_Pos) /*!< GPIO_PORT PIN4: PORT4 Mask */ -#define GPIO_PORT_PIN4_PORT5_Pos 5 /*!< GPIO_PORT PIN4: PORT5 Position */ -#define GPIO_PORT_PIN4_PORT5_Msk (0x01UL << GPIO_PORT_PIN4_PORT5_Pos) /*!< GPIO_PORT PIN4: PORT5 Mask */ -#define GPIO_PORT_PIN4_PORT6_Pos 6 /*!< GPIO_PORT PIN4: PORT6 Position */ -#define GPIO_PORT_PIN4_PORT6_Msk (0x01UL << GPIO_PORT_PIN4_PORT6_Pos) /*!< GPIO_PORT PIN4: PORT6 Mask */ -#define GPIO_PORT_PIN4_PORT7_Pos 7 /*!< GPIO_PORT PIN4: PORT7 Position */ -#define GPIO_PORT_PIN4_PORT7_Msk (0x01UL << GPIO_PORT_PIN4_PORT7_Pos) /*!< GPIO_PORT PIN4: PORT7 Mask */ -#define GPIO_PORT_PIN4_PORT8_Pos 8 /*!< GPIO_PORT PIN4: PORT8 Position */ -#define GPIO_PORT_PIN4_PORT8_Msk (0x01UL << GPIO_PORT_PIN4_PORT8_Pos) /*!< GPIO_PORT PIN4: PORT8 Mask */ -#define GPIO_PORT_PIN4_PORT9_Pos 9 /*!< GPIO_PORT PIN4: PORT9 Position */ -#define GPIO_PORT_PIN4_PORT9_Msk (0x01UL << GPIO_PORT_PIN4_PORT9_Pos) /*!< GPIO_PORT PIN4: PORT9 Mask */ -#define GPIO_PORT_PIN4_PORT10_Pos 10 /*!< GPIO_PORT PIN4: PORT10 Position */ -#define GPIO_PORT_PIN4_PORT10_Msk (0x01UL << GPIO_PORT_PIN4_PORT10_Pos) /*!< GPIO_PORT PIN4: PORT10 Mask */ -#define GPIO_PORT_PIN4_PORT11_Pos 11 /*!< GPIO_PORT PIN4: PORT11 Position */ -#define GPIO_PORT_PIN4_PORT11_Msk (0x01UL << GPIO_PORT_PIN4_PORT11_Pos) /*!< GPIO_PORT PIN4: PORT11 Mask */ -#define GPIO_PORT_PIN4_PORT12_Pos 12 /*!< GPIO_PORT PIN4: PORT12 Position */ -#define GPIO_PORT_PIN4_PORT12_Msk (0x01UL << GPIO_PORT_PIN4_PORT12_Pos) /*!< GPIO_PORT PIN4: PORT12 Mask */ -#define GPIO_PORT_PIN4_PORT13_Pos 13 /*!< GPIO_PORT PIN4: PORT13 Position */ -#define GPIO_PORT_PIN4_PORT13_Msk (0x01UL << GPIO_PORT_PIN4_PORT13_Pos) /*!< GPIO_PORT PIN4: PORT13 Mask */ -#define GPIO_PORT_PIN4_PORT14_Pos 14 /*!< GPIO_PORT PIN4: PORT14 Position */ -#define GPIO_PORT_PIN4_PORT14_Msk (0x01UL << GPIO_PORT_PIN4_PORT14_Pos) /*!< GPIO_PORT PIN4: PORT14 Mask */ -#define GPIO_PORT_PIN4_PORT15_Pos 15 /*!< GPIO_PORT PIN4: PORT15 Position */ -#define GPIO_PORT_PIN4_PORT15_Msk (0x01UL << GPIO_PORT_PIN4_PORT15_Pos) /*!< GPIO_PORT PIN4: PORT15 Mask */ -#define GPIO_PORT_PIN4_PORT16_Pos 16 /*!< GPIO_PORT PIN4: PORT16 Position */ -#define GPIO_PORT_PIN4_PORT16_Msk (0x01UL << GPIO_PORT_PIN4_PORT16_Pos) /*!< GPIO_PORT PIN4: PORT16 Mask */ -#define GPIO_PORT_PIN4_PORT17_Pos 17 /*!< GPIO_PORT PIN4: PORT17 Position */ -#define GPIO_PORT_PIN4_PORT17_Msk (0x01UL << GPIO_PORT_PIN4_PORT17_Pos) /*!< GPIO_PORT PIN4: PORT17 Mask */ -#define GPIO_PORT_PIN4_PORT18_Pos 18 /*!< GPIO_PORT PIN4: PORT18 Position */ -#define GPIO_PORT_PIN4_PORT18_Msk (0x01UL << GPIO_PORT_PIN4_PORT18_Pos) /*!< GPIO_PORT PIN4: PORT18 Mask */ -#define GPIO_PORT_PIN4_PORT19_Pos 19 /*!< GPIO_PORT PIN4: PORT19 Position */ -#define GPIO_PORT_PIN4_PORT19_Msk (0x01UL << GPIO_PORT_PIN4_PORT19_Pos) /*!< GPIO_PORT PIN4: PORT19 Mask */ -#define GPIO_PORT_PIN4_PORT20_Pos 20 /*!< GPIO_PORT PIN4: PORT20 Position */ -#define GPIO_PORT_PIN4_PORT20_Msk (0x01UL << GPIO_PORT_PIN4_PORT20_Pos) /*!< GPIO_PORT PIN4: PORT20 Mask */ -#define GPIO_PORT_PIN4_PORT21_Pos 21 /*!< GPIO_PORT PIN4: PORT21 Position */ -#define GPIO_PORT_PIN4_PORT21_Msk (0x01UL << GPIO_PORT_PIN4_PORT21_Pos) /*!< GPIO_PORT PIN4: PORT21 Mask */ -#define GPIO_PORT_PIN4_PORT22_Pos 22 /*!< GPIO_PORT PIN4: PORT22 Position */ -#define GPIO_PORT_PIN4_PORT22_Msk (0x01UL << GPIO_PORT_PIN4_PORT22_Pos) /*!< GPIO_PORT PIN4: PORT22 Mask */ -#define GPIO_PORT_PIN4_PORT23_Pos 23 /*!< GPIO_PORT PIN4: PORT23 Position */ -#define GPIO_PORT_PIN4_PORT23_Msk (0x01UL << GPIO_PORT_PIN4_PORT23_Pos) /*!< GPIO_PORT PIN4: PORT23 Mask */ -#define GPIO_PORT_PIN4_PORT24_Pos 24 /*!< GPIO_PORT PIN4: PORT24 Position */ -#define GPIO_PORT_PIN4_PORT24_Msk (0x01UL << GPIO_PORT_PIN4_PORT24_Pos) /*!< GPIO_PORT PIN4: PORT24 Mask */ -#define GPIO_PORT_PIN4_PORT25_Pos 25 /*!< GPIO_PORT PIN4: PORT25 Position */ -#define GPIO_PORT_PIN4_PORT25_Msk (0x01UL << GPIO_PORT_PIN4_PORT25_Pos) /*!< GPIO_PORT PIN4: PORT25 Mask */ -#define GPIO_PORT_PIN4_PORT26_Pos 26 /*!< GPIO_PORT PIN4: PORT26 Position */ -#define GPIO_PORT_PIN4_PORT26_Msk (0x01UL << GPIO_PORT_PIN4_PORT26_Pos) /*!< GPIO_PORT PIN4: PORT26 Mask */ -#define GPIO_PORT_PIN4_PORT27_Pos 27 /*!< GPIO_PORT PIN4: PORT27 Position */ -#define GPIO_PORT_PIN4_PORT27_Msk (0x01UL << GPIO_PORT_PIN4_PORT27_Pos) /*!< GPIO_PORT PIN4: PORT27 Mask */ -#define GPIO_PORT_PIN4_PORT28_Pos 28 /*!< GPIO_PORT PIN4: PORT28 Position */ -#define GPIO_PORT_PIN4_PORT28_Msk (0x01UL << GPIO_PORT_PIN4_PORT28_Pos) /*!< GPIO_PORT PIN4: PORT28 Mask */ -#define GPIO_PORT_PIN4_PORT29_Pos 29 /*!< GPIO_PORT PIN4: PORT29 Position */ -#define GPIO_PORT_PIN4_PORT29_Msk (0x01UL << GPIO_PORT_PIN4_PORT29_Pos) /*!< GPIO_PORT PIN4: PORT29 Mask */ -#define GPIO_PORT_PIN4_PORT30_Pos 30 /*!< GPIO_PORT PIN4: PORT30 Position */ -#define GPIO_PORT_PIN4_PORT30_Msk (0x01UL << GPIO_PORT_PIN4_PORT30_Pos) /*!< GPIO_PORT PIN4: PORT30 Mask */ -#define GPIO_PORT_PIN4_PORT31_Pos 31 /*!< GPIO_PORT PIN4: PORT31 Position */ -#define GPIO_PORT_PIN4_PORT31_Msk (0x01UL << GPIO_PORT_PIN4_PORT31_Pos) /*!< GPIO_PORT PIN4: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN5 ----------------------------------------- -#define GPIO_PORT_PIN5_PORT0_Pos 0 /*!< GPIO_PORT PIN5: PORT0 Position */ -#define GPIO_PORT_PIN5_PORT0_Msk (0x01UL << GPIO_PORT_PIN5_PORT0_Pos) /*!< GPIO_PORT PIN5: PORT0 Mask */ -#define GPIO_PORT_PIN5_PORT1_Pos 1 /*!< GPIO_PORT PIN5: PORT1 Position */ -#define GPIO_PORT_PIN5_PORT1_Msk (0x01UL << GPIO_PORT_PIN5_PORT1_Pos) /*!< GPIO_PORT PIN5: PORT1 Mask */ -#define GPIO_PORT_PIN5_PORT2_Pos 2 /*!< GPIO_PORT PIN5: PORT2 Position */ -#define GPIO_PORT_PIN5_PORT2_Msk (0x01UL << GPIO_PORT_PIN5_PORT2_Pos) /*!< GPIO_PORT PIN5: PORT2 Mask */ -#define GPIO_PORT_PIN5_PORT3_Pos 3 /*!< GPIO_PORT PIN5: PORT3 Position */ -#define GPIO_PORT_PIN5_PORT3_Msk (0x01UL << GPIO_PORT_PIN5_PORT3_Pos) /*!< GPIO_PORT PIN5: PORT3 Mask */ -#define GPIO_PORT_PIN5_PORT4_Pos 4 /*!< GPIO_PORT PIN5: PORT4 Position */ -#define GPIO_PORT_PIN5_PORT4_Msk (0x01UL << GPIO_PORT_PIN5_PORT4_Pos) /*!< GPIO_PORT PIN5: PORT4 Mask */ -#define GPIO_PORT_PIN5_PORT5_Pos 5 /*!< GPIO_PORT PIN5: PORT5 Position */ -#define GPIO_PORT_PIN5_PORT5_Msk (0x01UL << GPIO_PORT_PIN5_PORT5_Pos) /*!< GPIO_PORT PIN5: PORT5 Mask */ -#define GPIO_PORT_PIN5_PORT6_Pos 6 /*!< GPIO_PORT PIN5: PORT6 Position */ -#define GPIO_PORT_PIN5_PORT6_Msk (0x01UL << GPIO_PORT_PIN5_PORT6_Pos) /*!< GPIO_PORT PIN5: PORT6 Mask */ -#define GPIO_PORT_PIN5_PORT7_Pos 7 /*!< GPIO_PORT PIN5: PORT7 Position */ -#define GPIO_PORT_PIN5_PORT7_Msk (0x01UL << GPIO_PORT_PIN5_PORT7_Pos) /*!< GPIO_PORT PIN5: PORT7 Mask */ -#define GPIO_PORT_PIN5_PORT8_Pos 8 /*!< GPIO_PORT PIN5: PORT8 Position */ -#define GPIO_PORT_PIN5_PORT8_Msk (0x01UL << GPIO_PORT_PIN5_PORT8_Pos) /*!< GPIO_PORT PIN5: PORT8 Mask */ -#define GPIO_PORT_PIN5_PORT9_Pos 9 /*!< GPIO_PORT PIN5: PORT9 Position */ -#define GPIO_PORT_PIN5_PORT9_Msk (0x01UL << GPIO_PORT_PIN5_PORT9_Pos) /*!< GPIO_PORT PIN5: PORT9 Mask */ -#define GPIO_PORT_PIN5_PORT10_Pos 10 /*!< GPIO_PORT PIN5: PORT10 Position */ -#define GPIO_PORT_PIN5_PORT10_Msk (0x01UL << GPIO_PORT_PIN5_PORT10_Pos) /*!< GPIO_PORT PIN5: PORT10 Mask */ -#define GPIO_PORT_PIN5_PORT11_Pos 11 /*!< GPIO_PORT PIN5: PORT11 Position */ -#define GPIO_PORT_PIN5_PORT11_Msk (0x01UL << GPIO_PORT_PIN5_PORT11_Pos) /*!< GPIO_PORT PIN5: PORT11 Mask */ -#define GPIO_PORT_PIN5_PORT12_Pos 12 /*!< GPIO_PORT PIN5: PORT12 Position */ -#define GPIO_PORT_PIN5_PORT12_Msk (0x01UL << GPIO_PORT_PIN5_PORT12_Pos) /*!< GPIO_PORT PIN5: PORT12 Mask */ -#define GPIO_PORT_PIN5_PORT13_Pos 13 /*!< GPIO_PORT PIN5: PORT13 Position */ -#define GPIO_PORT_PIN5_PORT13_Msk (0x01UL << GPIO_PORT_PIN5_PORT13_Pos) /*!< GPIO_PORT PIN5: PORT13 Mask */ -#define GPIO_PORT_PIN5_PORT14_Pos 14 /*!< GPIO_PORT PIN5: PORT14 Position */ -#define GPIO_PORT_PIN5_PORT14_Msk (0x01UL << GPIO_PORT_PIN5_PORT14_Pos) /*!< GPIO_PORT PIN5: PORT14 Mask */ -#define GPIO_PORT_PIN5_PORT15_Pos 15 /*!< GPIO_PORT PIN5: PORT15 Position */ -#define GPIO_PORT_PIN5_PORT15_Msk (0x01UL << GPIO_PORT_PIN5_PORT15_Pos) /*!< GPIO_PORT PIN5: PORT15 Mask */ -#define GPIO_PORT_PIN5_PORT16_Pos 16 /*!< GPIO_PORT PIN5: PORT16 Position */ -#define GPIO_PORT_PIN5_PORT16_Msk (0x01UL << GPIO_PORT_PIN5_PORT16_Pos) /*!< GPIO_PORT PIN5: PORT16 Mask */ -#define GPIO_PORT_PIN5_PORT17_Pos 17 /*!< GPIO_PORT PIN5: PORT17 Position */ -#define GPIO_PORT_PIN5_PORT17_Msk (0x01UL << GPIO_PORT_PIN5_PORT17_Pos) /*!< GPIO_PORT PIN5: PORT17 Mask */ -#define GPIO_PORT_PIN5_PORT18_Pos 18 /*!< GPIO_PORT PIN5: PORT18 Position */ -#define GPIO_PORT_PIN5_PORT18_Msk (0x01UL << GPIO_PORT_PIN5_PORT18_Pos) /*!< GPIO_PORT PIN5: PORT18 Mask */ -#define GPIO_PORT_PIN5_PORT19_Pos 19 /*!< GPIO_PORT PIN5: PORT19 Position */ -#define GPIO_PORT_PIN5_PORT19_Msk (0x01UL << GPIO_PORT_PIN5_PORT19_Pos) /*!< GPIO_PORT PIN5: PORT19 Mask */ -#define GPIO_PORT_PIN5_PORT20_Pos 20 /*!< GPIO_PORT PIN5: PORT20 Position */ -#define GPIO_PORT_PIN5_PORT20_Msk (0x01UL << GPIO_PORT_PIN5_PORT20_Pos) /*!< GPIO_PORT PIN5: PORT20 Mask */ -#define GPIO_PORT_PIN5_PORT21_Pos 21 /*!< GPIO_PORT PIN5: PORT21 Position */ -#define GPIO_PORT_PIN5_PORT21_Msk (0x01UL << GPIO_PORT_PIN5_PORT21_Pos) /*!< GPIO_PORT PIN5: PORT21 Mask */ -#define GPIO_PORT_PIN5_PORT22_Pos 22 /*!< GPIO_PORT PIN5: PORT22 Position */ -#define GPIO_PORT_PIN5_PORT22_Msk (0x01UL << GPIO_PORT_PIN5_PORT22_Pos) /*!< GPIO_PORT PIN5: PORT22 Mask */ -#define GPIO_PORT_PIN5_PORT23_Pos 23 /*!< GPIO_PORT PIN5: PORT23 Position */ -#define GPIO_PORT_PIN5_PORT23_Msk (0x01UL << GPIO_PORT_PIN5_PORT23_Pos) /*!< GPIO_PORT PIN5: PORT23 Mask */ -#define GPIO_PORT_PIN5_PORT24_Pos 24 /*!< GPIO_PORT PIN5: PORT24 Position */ -#define GPIO_PORT_PIN5_PORT24_Msk (0x01UL << GPIO_PORT_PIN5_PORT24_Pos) /*!< GPIO_PORT PIN5: PORT24 Mask */ -#define GPIO_PORT_PIN5_PORT25_Pos 25 /*!< GPIO_PORT PIN5: PORT25 Position */ -#define GPIO_PORT_PIN5_PORT25_Msk (0x01UL << GPIO_PORT_PIN5_PORT25_Pos) /*!< GPIO_PORT PIN5: PORT25 Mask */ -#define GPIO_PORT_PIN5_PORT26_Pos 26 /*!< GPIO_PORT PIN5: PORT26 Position */ -#define GPIO_PORT_PIN5_PORT26_Msk (0x01UL << GPIO_PORT_PIN5_PORT26_Pos) /*!< GPIO_PORT PIN5: PORT26 Mask */ -#define GPIO_PORT_PIN5_PORT27_Pos 27 /*!< GPIO_PORT PIN5: PORT27 Position */ -#define GPIO_PORT_PIN5_PORT27_Msk (0x01UL << GPIO_PORT_PIN5_PORT27_Pos) /*!< GPIO_PORT PIN5: PORT27 Mask */ -#define GPIO_PORT_PIN5_PORT28_Pos 28 /*!< GPIO_PORT PIN5: PORT28 Position */ -#define GPIO_PORT_PIN5_PORT28_Msk (0x01UL << GPIO_PORT_PIN5_PORT28_Pos) /*!< GPIO_PORT PIN5: PORT28 Mask */ -#define GPIO_PORT_PIN5_PORT29_Pos 29 /*!< GPIO_PORT PIN5: PORT29 Position */ -#define GPIO_PORT_PIN5_PORT29_Msk (0x01UL << GPIO_PORT_PIN5_PORT29_Pos) /*!< GPIO_PORT PIN5: PORT29 Mask */ -#define GPIO_PORT_PIN5_PORT30_Pos 30 /*!< GPIO_PORT PIN5: PORT30 Position */ -#define GPIO_PORT_PIN5_PORT30_Msk (0x01UL << GPIO_PORT_PIN5_PORT30_Pos) /*!< GPIO_PORT PIN5: PORT30 Mask */ -#define GPIO_PORT_PIN5_PORT31_Pos 31 /*!< GPIO_PORT PIN5: PORT31 Position */ -#define GPIO_PORT_PIN5_PORT31_Msk (0x01UL << GPIO_PORT_PIN5_PORT31_Pos) /*!< GPIO_PORT PIN5: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN6 ----------------------------------------- -#define GPIO_PORT_PIN6_PORT0_Pos 0 /*!< GPIO_PORT PIN6: PORT0 Position */ -#define GPIO_PORT_PIN6_PORT0_Msk (0x01UL << GPIO_PORT_PIN6_PORT0_Pos) /*!< GPIO_PORT PIN6: PORT0 Mask */ -#define GPIO_PORT_PIN6_PORT1_Pos 1 /*!< GPIO_PORT PIN6: PORT1 Position */ -#define GPIO_PORT_PIN6_PORT1_Msk (0x01UL << GPIO_PORT_PIN6_PORT1_Pos) /*!< GPIO_PORT PIN6: PORT1 Mask */ -#define GPIO_PORT_PIN6_PORT2_Pos 2 /*!< GPIO_PORT PIN6: PORT2 Position */ -#define GPIO_PORT_PIN6_PORT2_Msk (0x01UL << GPIO_PORT_PIN6_PORT2_Pos) /*!< GPIO_PORT PIN6: PORT2 Mask */ -#define GPIO_PORT_PIN6_PORT3_Pos 3 /*!< GPIO_PORT PIN6: PORT3 Position */ -#define GPIO_PORT_PIN6_PORT3_Msk (0x01UL << GPIO_PORT_PIN6_PORT3_Pos) /*!< GPIO_PORT PIN6: PORT3 Mask */ -#define GPIO_PORT_PIN6_PORT4_Pos 4 /*!< GPIO_PORT PIN6: PORT4 Position */ -#define GPIO_PORT_PIN6_PORT4_Msk (0x01UL << GPIO_PORT_PIN6_PORT4_Pos) /*!< GPIO_PORT PIN6: PORT4 Mask */ -#define GPIO_PORT_PIN6_PORT5_Pos 5 /*!< GPIO_PORT PIN6: PORT5 Position */ -#define GPIO_PORT_PIN6_PORT5_Msk (0x01UL << GPIO_PORT_PIN6_PORT5_Pos) /*!< GPIO_PORT PIN6: PORT5 Mask */ -#define GPIO_PORT_PIN6_PORT6_Pos 6 /*!< GPIO_PORT PIN6: PORT6 Position */ -#define GPIO_PORT_PIN6_PORT6_Msk (0x01UL << GPIO_PORT_PIN6_PORT6_Pos) /*!< GPIO_PORT PIN6: PORT6 Mask */ -#define GPIO_PORT_PIN6_PORT7_Pos 7 /*!< GPIO_PORT PIN6: PORT7 Position */ -#define GPIO_PORT_PIN6_PORT7_Msk (0x01UL << GPIO_PORT_PIN6_PORT7_Pos) /*!< GPIO_PORT PIN6: PORT7 Mask */ -#define GPIO_PORT_PIN6_PORT8_Pos 8 /*!< GPIO_PORT PIN6: PORT8 Position */ -#define GPIO_PORT_PIN6_PORT8_Msk (0x01UL << GPIO_PORT_PIN6_PORT8_Pos) /*!< GPIO_PORT PIN6: PORT8 Mask */ -#define GPIO_PORT_PIN6_PORT9_Pos 9 /*!< GPIO_PORT PIN6: PORT9 Position */ -#define GPIO_PORT_PIN6_PORT9_Msk (0x01UL << GPIO_PORT_PIN6_PORT9_Pos) /*!< GPIO_PORT PIN6: PORT9 Mask */ -#define GPIO_PORT_PIN6_PORT10_Pos 10 /*!< GPIO_PORT PIN6: PORT10 Position */ -#define GPIO_PORT_PIN6_PORT10_Msk (0x01UL << GPIO_PORT_PIN6_PORT10_Pos) /*!< GPIO_PORT PIN6: PORT10 Mask */ -#define GPIO_PORT_PIN6_PORT11_Pos 11 /*!< GPIO_PORT PIN6: PORT11 Position */ -#define GPIO_PORT_PIN6_PORT11_Msk (0x01UL << GPIO_PORT_PIN6_PORT11_Pos) /*!< GPIO_PORT PIN6: PORT11 Mask */ -#define GPIO_PORT_PIN6_PORT12_Pos 12 /*!< GPIO_PORT PIN6: PORT12 Position */ -#define GPIO_PORT_PIN6_PORT12_Msk (0x01UL << GPIO_PORT_PIN6_PORT12_Pos) /*!< GPIO_PORT PIN6: PORT12 Mask */ -#define GPIO_PORT_PIN6_PORT13_Pos 13 /*!< GPIO_PORT PIN6: PORT13 Position */ -#define GPIO_PORT_PIN6_PORT13_Msk (0x01UL << GPIO_PORT_PIN6_PORT13_Pos) /*!< GPIO_PORT PIN6: PORT13 Mask */ -#define GPIO_PORT_PIN6_PORT14_Pos 14 /*!< GPIO_PORT PIN6: PORT14 Position */ -#define GPIO_PORT_PIN6_PORT14_Msk (0x01UL << GPIO_PORT_PIN6_PORT14_Pos) /*!< GPIO_PORT PIN6: PORT14 Mask */ -#define GPIO_PORT_PIN6_PORT15_Pos 15 /*!< GPIO_PORT PIN6: PORT15 Position */ -#define GPIO_PORT_PIN6_PORT15_Msk (0x01UL << GPIO_PORT_PIN6_PORT15_Pos) /*!< GPIO_PORT PIN6: PORT15 Mask */ -#define GPIO_PORT_PIN6_PORT16_Pos 16 /*!< GPIO_PORT PIN6: PORT16 Position */ -#define GPIO_PORT_PIN6_PORT16_Msk (0x01UL << GPIO_PORT_PIN6_PORT16_Pos) /*!< GPIO_PORT PIN6: PORT16 Mask */ -#define GPIO_PORT_PIN6_PORT17_Pos 17 /*!< GPIO_PORT PIN6: PORT17 Position */ -#define GPIO_PORT_PIN6_PORT17_Msk (0x01UL << GPIO_PORT_PIN6_PORT17_Pos) /*!< GPIO_PORT PIN6: PORT17 Mask */ -#define GPIO_PORT_PIN6_PORT18_Pos 18 /*!< GPIO_PORT PIN6: PORT18 Position */ -#define GPIO_PORT_PIN6_PORT18_Msk (0x01UL << GPIO_PORT_PIN6_PORT18_Pos) /*!< GPIO_PORT PIN6: PORT18 Mask */ -#define GPIO_PORT_PIN6_PORT19_Pos 19 /*!< GPIO_PORT PIN6: PORT19 Position */ -#define GPIO_PORT_PIN6_PORT19_Msk (0x01UL << GPIO_PORT_PIN6_PORT19_Pos) /*!< GPIO_PORT PIN6: PORT19 Mask */ -#define GPIO_PORT_PIN6_PORT20_Pos 20 /*!< GPIO_PORT PIN6: PORT20 Position */ -#define GPIO_PORT_PIN6_PORT20_Msk (0x01UL << GPIO_PORT_PIN6_PORT20_Pos) /*!< GPIO_PORT PIN6: PORT20 Mask */ -#define GPIO_PORT_PIN6_PORT21_Pos 21 /*!< GPIO_PORT PIN6: PORT21 Position */ -#define GPIO_PORT_PIN6_PORT21_Msk (0x01UL << GPIO_PORT_PIN6_PORT21_Pos) /*!< GPIO_PORT PIN6: PORT21 Mask */ -#define GPIO_PORT_PIN6_PORT22_Pos 22 /*!< GPIO_PORT PIN6: PORT22 Position */ -#define GPIO_PORT_PIN6_PORT22_Msk (0x01UL << GPIO_PORT_PIN6_PORT22_Pos) /*!< GPIO_PORT PIN6: PORT22 Mask */ -#define GPIO_PORT_PIN6_PORT23_Pos 23 /*!< GPIO_PORT PIN6: PORT23 Position */ -#define GPIO_PORT_PIN6_PORT23_Msk (0x01UL << GPIO_PORT_PIN6_PORT23_Pos) /*!< GPIO_PORT PIN6: PORT23 Mask */ -#define GPIO_PORT_PIN6_PORT24_Pos 24 /*!< GPIO_PORT PIN6: PORT24 Position */ -#define GPIO_PORT_PIN6_PORT24_Msk (0x01UL << GPIO_PORT_PIN6_PORT24_Pos) /*!< GPIO_PORT PIN6: PORT24 Mask */ -#define GPIO_PORT_PIN6_PORT25_Pos 25 /*!< GPIO_PORT PIN6: PORT25 Position */ -#define GPIO_PORT_PIN6_PORT25_Msk (0x01UL << GPIO_PORT_PIN6_PORT25_Pos) /*!< GPIO_PORT PIN6: PORT25 Mask */ -#define GPIO_PORT_PIN6_PORT26_Pos 26 /*!< GPIO_PORT PIN6: PORT26 Position */ -#define GPIO_PORT_PIN6_PORT26_Msk (0x01UL << GPIO_PORT_PIN6_PORT26_Pos) /*!< GPIO_PORT PIN6: PORT26 Mask */ -#define GPIO_PORT_PIN6_PORT27_Pos 27 /*!< GPIO_PORT PIN6: PORT27 Position */ -#define GPIO_PORT_PIN6_PORT27_Msk (0x01UL << GPIO_PORT_PIN6_PORT27_Pos) /*!< GPIO_PORT PIN6: PORT27 Mask */ -#define GPIO_PORT_PIN6_PORT28_Pos 28 /*!< GPIO_PORT PIN6: PORT28 Position */ -#define GPIO_PORT_PIN6_PORT28_Msk (0x01UL << GPIO_PORT_PIN6_PORT28_Pos) /*!< GPIO_PORT PIN6: PORT28 Mask */ -#define GPIO_PORT_PIN6_PORT29_Pos 29 /*!< GPIO_PORT PIN6: PORT29 Position */ -#define GPIO_PORT_PIN6_PORT29_Msk (0x01UL << GPIO_PORT_PIN6_PORT29_Pos) /*!< GPIO_PORT PIN6: PORT29 Mask */ -#define GPIO_PORT_PIN6_PORT30_Pos 30 /*!< GPIO_PORT PIN6: PORT30 Position */ -#define GPIO_PORT_PIN6_PORT30_Msk (0x01UL << GPIO_PORT_PIN6_PORT30_Pos) /*!< GPIO_PORT PIN6: PORT30 Mask */ -#define GPIO_PORT_PIN6_PORT31_Pos 31 /*!< GPIO_PORT PIN6: PORT31 Position */ -#define GPIO_PORT_PIN6_PORT31_Msk (0x01UL << GPIO_PORT_PIN6_PORT31_Pos) /*!< GPIO_PORT PIN6: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN7 ----------------------------------------- -#define GPIO_PORT_PIN7_PORT0_Pos 0 /*!< GPIO_PORT PIN7: PORT0 Position */ -#define GPIO_PORT_PIN7_PORT0_Msk (0x01UL << GPIO_PORT_PIN7_PORT0_Pos) /*!< GPIO_PORT PIN7: PORT0 Mask */ -#define GPIO_PORT_PIN7_PORT1_Pos 1 /*!< GPIO_PORT PIN7: PORT1 Position */ -#define GPIO_PORT_PIN7_PORT1_Msk (0x01UL << GPIO_PORT_PIN7_PORT1_Pos) /*!< GPIO_PORT PIN7: PORT1 Mask */ -#define GPIO_PORT_PIN7_PORT2_Pos 2 /*!< GPIO_PORT PIN7: PORT2 Position */ -#define GPIO_PORT_PIN7_PORT2_Msk (0x01UL << GPIO_PORT_PIN7_PORT2_Pos) /*!< GPIO_PORT PIN7: PORT2 Mask */ -#define GPIO_PORT_PIN7_PORT3_Pos 3 /*!< GPIO_PORT PIN7: PORT3 Position */ -#define GPIO_PORT_PIN7_PORT3_Msk (0x01UL << GPIO_PORT_PIN7_PORT3_Pos) /*!< GPIO_PORT PIN7: PORT3 Mask */ -#define GPIO_PORT_PIN7_PORT4_Pos 4 /*!< GPIO_PORT PIN7: PORT4 Position */ -#define GPIO_PORT_PIN7_PORT4_Msk (0x01UL << GPIO_PORT_PIN7_PORT4_Pos) /*!< GPIO_PORT PIN7: PORT4 Mask */ -#define GPIO_PORT_PIN7_PORT5_Pos 5 /*!< GPIO_PORT PIN7: PORT5 Position */ -#define GPIO_PORT_PIN7_PORT5_Msk (0x01UL << GPIO_PORT_PIN7_PORT5_Pos) /*!< GPIO_PORT PIN7: PORT5 Mask */ -#define GPIO_PORT_PIN7_PORT6_Pos 6 /*!< GPIO_PORT PIN7: PORT6 Position */ -#define GPIO_PORT_PIN7_PORT6_Msk (0x01UL << GPIO_PORT_PIN7_PORT6_Pos) /*!< GPIO_PORT PIN7: PORT6 Mask */ -#define GPIO_PORT_PIN7_PORT7_Pos 7 /*!< GPIO_PORT PIN7: PORT7 Position */ -#define GPIO_PORT_PIN7_PORT7_Msk (0x01UL << GPIO_PORT_PIN7_PORT7_Pos) /*!< GPIO_PORT PIN7: PORT7 Mask */ -#define GPIO_PORT_PIN7_PORT8_Pos 8 /*!< GPIO_PORT PIN7: PORT8 Position */ -#define GPIO_PORT_PIN7_PORT8_Msk (0x01UL << GPIO_PORT_PIN7_PORT8_Pos) /*!< GPIO_PORT PIN7: PORT8 Mask */ -#define GPIO_PORT_PIN7_PORT9_Pos 9 /*!< GPIO_PORT PIN7: PORT9 Position */ -#define GPIO_PORT_PIN7_PORT9_Msk (0x01UL << GPIO_PORT_PIN7_PORT9_Pos) /*!< GPIO_PORT PIN7: PORT9 Mask */ -#define GPIO_PORT_PIN7_PORT10_Pos 10 /*!< GPIO_PORT PIN7: PORT10 Position */ -#define GPIO_PORT_PIN7_PORT10_Msk (0x01UL << GPIO_PORT_PIN7_PORT10_Pos) /*!< GPIO_PORT PIN7: PORT10 Mask */ -#define GPIO_PORT_PIN7_PORT11_Pos 11 /*!< GPIO_PORT PIN7: PORT11 Position */ -#define GPIO_PORT_PIN7_PORT11_Msk (0x01UL << GPIO_PORT_PIN7_PORT11_Pos) /*!< GPIO_PORT PIN7: PORT11 Mask */ -#define GPIO_PORT_PIN7_PORT12_Pos 12 /*!< GPIO_PORT PIN7: PORT12 Position */ -#define GPIO_PORT_PIN7_PORT12_Msk (0x01UL << GPIO_PORT_PIN7_PORT12_Pos) /*!< GPIO_PORT PIN7: PORT12 Mask */ -#define GPIO_PORT_PIN7_PORT13_Pos 13 /*!< GPIO_PORT PIN7: PORT13 Position */ -#define GPIO_PORT_PIN7_PORT13_Msk (0x01UL << GPIO_PORT_PIN7_PORT13_Pos) /*!< GPIO_PORT PIN7: PORT13 Mask */ -#define GPIO_PORT_PIN7_PORT14_Pos 14 /*!< GPIO_PORT PIN7: PORT14 Position */ -#define GPIO_PORT_PIN7_PORT14_Msk (0x01UL << GPIO_PORT_PIN7_PORT14_Pos) /*!< GPIO_PORT PIN7: PORT14 Mask */ -#define GPIO_PORT_PIN7_PORT15_Pos 15 /*!< GPIO_PORT PIN7: PORT15 Position */ -#define GPIO_PORT_PIN7_PORT15_Msk (0x01UL << GPIO_PORT_PIN7_PORT15_Pos) /*!< GPIO_PORT PIN7: PORT15 Mask */ -#define GPIO_PORT_PIN7_PORT16_Pos 16 /*!< GPIO_PORT PIN7: PORT16 Position */ -#define GPIO_PORT_PIN7_PORT16_Msk (0x01UL << GPIO_PORT_PIN7_PORT16_Pos) /*!< GPIO_PORT PIN7: PORT16 Mask */ -#define GPIO_PORT_PIN7_PORT17_Pos 17 /*!< GPIO_PORT PIN7: PORT17 Position */ -#define GPIO_PORT_PIN7_PORT17_Msk (0x01UL << GPIO_PORT_PIN7_PORT17_Pos) /*!< GPIO_PORT PIN7: PORT17 Mask */ -#define GPIO_PORT_PIN7_PORT18_Pos 18 /*!< GPIO_PORT PIN7: PORT18 Position */ -#define GPIO_PORT_PIN7_PORT18_Msk (0x01UL << GPIO_PORT_PIN7_PORT18_Pos) /*!< GPIO_PORT PIN7: PORT18 Mask */ -#define GPIO_PORT_PIN7_PORT19_Pos 19 /*!< GPIO_PORT PIN7: PORT19 Position */ -#define GPIO_PORT_PIN7_PORT19_Msk (0x01UL << GPIO_PORT_PIN7_PORT19_Pos) /*!< GPIO_PORT PIN7: PORT19 Mask */ -#define GPIO_PORT_PIN7_PORT20_Pos 20 /*!< GPIO_PORT PIN7: PORT20 Position */ -#define GPIO_PORT_PIN7_PORT20_Msk (0x01UL << GPIO_PORT_PIN7_PORT20_Pos) /*!< GPIO_PORT PIN7: PORT20 Mask */ -#define GPIO_PORT_PIN7_PORT21_Pos 21 /*!< GPIO_PORT PIN7: PORT21 Position */ -#define GPIO_PORT_PIN7_PORT21_Msk (0x01UL << GPIO_PORT_PIN7_PORT21_Pos) /*!< GPIO_PORT PIN7: PORT21 Mask */ -#define GPIO_PORT_PIN7_PORT22_Pos 22 /*!< GPIO_PORT PIN7: PORT22 Position */ -#define GPIO_PORT_PIN7_PORT22_Msk (0x01UL << GPIO_PORT_PIN7_PORT22_Pos) /*!< GPIO_PORT PIN7: PORT22 Mask */ -#define GPIO_PORT_PIN7_PORT23_Pos 23 /*!< GPIO_PORT PIN7: PORT23 Position */ -#define GPIO_PORT_PIN7_PORT23_Msk (0x01UL << GPIO_PORT_PIN7_PORT23_Pos) /*!< GPIO_PORT PIN7: PORT23 Mask */ -#define GPIO_PORT_PIN7_PORT24_Pos 24 /*!< GPIO_PORT PIN7: PORT24 Position */ -#define GPIO_PORT_PIN7_PORT24_Msk (0x01UL << GPIO_PORT_PIN7_PORT24_Pos) /*!< GPIO_PORT PIN7: PORT24 Mask */ -#define GPIO_PORT_PIN7_PORT25_Pos 25 /*!< GPIO_PORT PIN7: PORT25 Position */ -#define GPIO_PORT_PIN7_PORT25_Msk (0x01UL << GPIO_PORT_PIN7_PORT25_Pos) /*!< GPIO_PORT PIN7: PORT25 Mask */ -#define GPIO_PORT_PIN7_PORT26_Pos 26 /*!< GPIO_PORT PIN7: PORT26 Position */ -#define GPIO_PORT_PIN7_PORT26_Msk (0x01UL << GPIO_PORT_PIN7_PORT26_Pos) /*!< GPIO_PORT PIN7: PORT26 Mask */ -#define GPIO_PORT_PIN7_PORT27_Pos 27 /*!< GPIO_PORT PIN7: PORT27 Position */ -#define GPIO_PORT_PIN7_PORT27_Msk (0x01UL << GPIO_PORT_PIN7_PORT27_Pos) /*!< GPIO_PORT PIN7: PORT27 Mask */ -#define GPIO_PORT_PIN7_PORT28_Pos 28 /*!< GPIO_PORT PIN7: PORT28 Position */ -#define GPIO_PORT_PIN7_PORT28_Msk (0x01UL << GPIO_PORT_PIN7_PORT28_Pos) /*!< GPIO_PORT PIN7: PORT28 Mask */ -#define GPIO_PORT_PIN7_PORT29_Pos 29 /*!< GPIO_PORT PIN7: PORT29 Position */ -#define GPIO_PORT_PIN7_PORT29_Msk (0x01UL << GPIO_PORT_PIN7_PORT29_Pos) /*!< GPIO_PORT PIN7: PORT29 Mask */ -#define GPIO_PORT_PIN7_PORT30_Pos 30 /*!< GPIO_PORT PIN7: PORT30 Position */ -#define GPIO_PORT_PIN7_PORT30_Msk (0x01UL << GPIO_PORT_PIN7_PORT30_Pos) /*!< GPIO_PORT PIN7: PORT30 Mask */ -#define GPIO_PORT_PIN7_PORT31_Pos 31 /*!< GPIO_PORT PIN7: PORT31 Position */ -#define GPIO_PORT_PIN7_PORT31_Msk (0x01UL << GPIO_PORT_PIN7_PORT31_Pos) /*!< GPIO_PORT PIN7: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN0 ---------------------------------------- -#define GPIO_PORT_MPIN0_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN0: MPORTP0 Position */ -#define GPIO_PORT_MPIN0_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos) /*!< GPIO_PORT MPIN0: MPORTP0 Mask */ -#define GPIO_PORT_MPIN0_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN0: MPORTP1 Position */ -#define GPIO_PORT_MPIN0_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos) /*!< GPIO_PORT MPIN0: MPORTP1 Mask */ -#define GPIO_PORT_MPIN0_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN0: MPORTP2 Position */ -#define GPIO_PORT_MPIN0_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos) /*!< GPIO_PORT MPIN0: MPORTP2 Mask */ -#define GPIO_PORT_MPIN0_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN0: MPORTP3 Position */ -#define GPIO_PORT_MPIN0_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos) /*!< GPIO_PORT MPIN0: MPORTP3 Mask */ -#define GPIO_PORT_MPIN0_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN0: MPORTP4 Position */ -#define GPIO_PORT_MPIN0_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos) /*!< GPIO_PORT MPIN0: MPORTP4 Mask */ -#define GPIO_PORT_MPIN0_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN0: MPORTP5 Position */ -#define GPIO_PORT_MPIN0_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos) /*!< GPIO_PORT MPIN0: MPORTP5 Mask */ -#define GPIO_PORT_MPIN0_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN0: MPORTP6 Position */ -#define GPIO_PORT_MPIN0_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos) /*!< GPIO_PORT MPIN0: MPORTP6 Mask */ -#define GPIO_PORT_MPIN0_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN0: MPORTP7 Position */ -#define GPIO_PORT_MPIN0_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos) /*!< GPIO_PORT MPIN0: MPORTP7 Mask */ -#define GPIO_PORT_MPIN0_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN0: MPORTP8 Position */ -#define GPIO_PORT_MPIN0_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos) /*!< GPIO_PORT MPIN0: MPORTP8 Mask */ -#define GPIO_PORT_MPIN0_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN0: MPORTP9 Position */ -#define GPIO_PORT_MPIN0_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos) /*!< GPIO_PORT MPIN0: MPORTP9 Mask */ -#define GPIO_PORT_MPIN0_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN0: MPORTP10 Position */ -#define GPIO_PORT_MPIN0_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos) /*!< GPIO_PORT MPIN0: MPORTP10 Mask */ -#define GPIO_PORT_MPIN0_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN0: MPORTP11 Position */ -#define GPIO_PORT_MPIN0_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos) /*!< GPIO_PORT MPIN0: MPORTP11 Mask */ -#define GPIO_PORT_MPIN0_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN0: MPORTP12 Position */ -#define GPIO_PORT_MPIN0_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos) /*!< GPIO_PORT MPIN0: MPORTP12 Mask */ -#define GPIO_PORT_MPIN0_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN0: MPORTP13 Position */ -#define GPIO_PORT_MPIN0_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos) /*!< GPIO_PORT MPIN0: MPORTP13 Mask */ -#define GPIO_PORT_MPIN0_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN0: MPORTP14 Position */ -#define GPIO_PORT_MPIN0_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos) /*!< GPIO_PORT MPIN0: MPORTP14 Mask */ -#define GPIO_PORT_MPIN0_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN0: MPORTP15 Position */ -#define GPIO_PORT_MPIN0_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos) /*!< GPIO_PORT MPIN0: MPORTP15 Mask */ -#define GPIO_PORT_MPIN0_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN0: MPORTP16 Position */ -#define GPIO_PORT_MPIN0_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos) /*!< GPIO_PORT MPIN0: MPORTP16 Mask */ -#define GPIO_PORT_MPIN0_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN0: MPORTP17 Position */ -#define GPIO_PORT_MPIN0_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos) /*!< GPIO_PORT MPIN0: MPORTP17 Mask */ -#define GPIO_PORT_MPIN0_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN0: MPORTP18 Position */ -#define GPIO_PORT_MPIN0_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos) /*!< GPIO_PORT MPIN0: MPORTP18 Mask */ -#define GPIO_PORT_MPIN0_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN0: MPORTP19 Position */ -#define GPIO_PORT_MPIN0_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos) /*!< GPIO_PORT MPIN0: MPORTP19 Mask */ -#define GPIO_PORT_MPIN0_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN0: MPORTP20 Position */ -#define GPIO_PORT_MPIN0_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos) /*!< GPIO_PORT MPIN0: MPORTP20 Mask */ -#define GPIO_PORT_MPIN0_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN0: MPORTP21 Position */ -#define GPIO_PORT_MPIN0_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos) /*!< GPIO_PORT MPIN0: MPORTP21 Mask */ -#define GPIO_PORT_MPIN0_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN0: MPORTP22 Position */ -#define GPIO_PORT_MPIN0_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos) /*!< GPIO_PORT MPIN0: MPORTP22 Mask */ -#define GPIO_PORT_MPIN0_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN0: MPORTP23 Position */ -#define GPIO_PORT_MPIN0_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos) /*!< GPIO_PORT MPIN0: MPORTP23 Mask */ -#define GPIO_PORT_MPIN0_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN0: MPORTP24 Position */ -#define GPIO_PORT_MPIN0_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos) /*!< GPIO_PORT MPIN0: MPORTP24 Mask */ -#define GPIO_PORT_MPIN0_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN0: MPORTP25 Position */ -#define GPIO_PORT_MPIN0_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos) /*!< GPIO_PORT MPIN0: MPORTP25 Mask */ -#define GPIO_PORT_MPIN0_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN0: MPORTP26 Position */ -#define GPIO_PORT_MPIN0_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos) /*!< GPIO_PORT MPIN0: MPORTP26 Mask */ -#define GPIO_PORT_MPIN0_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN0: MPORTP27 Position */ -#define GPIO_PORT_MPIN0_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos) /*!< GPIO_PORT MPIN0: MPORTP27 Mask */ -#define GPIO_PORT_MPIN0_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN0: MPORTP28 Position */ -#define GPIO_PORT_MPIN0_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos) /*!< GPIO_PORT MPIN0: MPORTP28 Mask */ -#define GPIO_PORT_MPIN0_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN0: MPORTP29 Position */ -#define GPIO_PORT_MPIN0_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos) /*!< GPIO_PORT MPIN0: MPORTP29 Mask */ -#define GPIO_PORT_MPIN0_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN0: MPORTP30 Position */ -#define GPIO_PORT_MPIN0_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos) /*!< GPIO_PORT MPIN0: MPORTP30 Mask */ -#define GPIO_PORT_MPIN0_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN0: MPORTP31 Position */ -#define GPIO_PORT_MPIN0_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos) /*!< GPIO_PORT MPIN0: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN1 ---------------------------------------- -#define GPIO_PORT_MPIN1_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN1: MPORTP0 Position */ -#define GPIO_PORT_MPIN1_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos) /*!< GPIO_PORT MPIN1: MPORTP0 Mask */ -#define GPIO_PORT_MPIN1_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN1: MPORTP1 Position */ -#define GPIO_PORT_MPIN1_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos) /*!< GPIO_PORT MPIN1: MPORTP1 Mask */ -#define GPIO_PORT_MPIN1_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN1: MPORTP2 Position */ -#define GPIO_PORT_MPIN1_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos) /*!< GPIO_PORT MPIN1: MPORTP2 Mask */ -#define GPIO_PORT_MPIN1_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN1: MPORTP3 Position */ -#define GPIO_PORT_MPIN1_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos) /*!< GPIO_PORT MPIN1: MPORTP3 Mask */ -#define GPIO_PORT_MPIN1_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN1: MPORTP4 Position */ -#define GPIO_PORT_MPIN1_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos) /*!< GPIO_PORT MPIN1: MPORTP4 Mask */ -#define GPIO_PORT_MPIN1_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN1: MPORTP5 Position */ -#define GPIO_PORT_MPIN1_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos) /*!< GPIO_PORT MPIN1: MPORTP5 Mask */ -#define GPIO_PORT_MPIN1_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN1: MPORTP6 Position */ -#define GPIO_PORT_MPIN1_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos) /*!< GPIO_PORT MPIN1: MPORTP6 Mask */ -#define GPIO_PORT_MPIN1_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN1: MPORTP7 Position */ -#define GPIO_PORT_MPIN1_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos) /*!< GPIO_PORT MPIN1: MPORTP7 Mask */ -#define GPIO_PORT_MPIN1_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN1: MPORTP8 Position */ -#define GPIO_PORT_MPIN1_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos) /*!< GPIO_PORT MPIN1: MPORTP8 Mask */ -#define GPIO_PORT_MPIN1_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN1: MPORTP9 Position */ -#define GPIO_PORT_MPIN1_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos) /*!< GPIO_PORT MPIN1: MPORTP9 Mask */ -#define GPIO_PORT_MPIN1_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN1: MPORTP10 Position */ -#define GPIO_PORT_MPIN1_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos) /*!< GPIO_PORT MPIN1: MPORTP10 Mask */ -#define GPIO_PORT_MPIN1_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN1: MPORTP11 Position */ -#define GPIO_PORT_MPIN1_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos) /*!< GPIO_PORT MPIN1: MPORTP11 Mask */ -#define GPIO_PORT_MPIN1_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN1: MPORTP12 Position */ -#define GPIO_PORT_MPIN1_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos) /*!< GPIO_PORT MPIN1: MPORTP12 Mask */ -#define GPIO_PORT_MPIN1_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN1: MPORTP13 Position */ -#define GPIO_PORT_MPIN1_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos) /*!< GPIO_PORT MPIN1: MPORTP13 Mask */ -#define GPIO_PORT_MPIN1_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN1: MPORTP14 Position */ -#define GPIO_PORT_MPIN1_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos) /*!< GPIO_PORT MPIN1: MPORTP14 Mask */ -#define GPIO_PORT_MPIN1_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN1: MPORTP15 Position */ -#define GPIO_PORT_MPIN1_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos) /*!< GPIO_PORT MPIN1: MPORTP15 Mask */ -#define GPIO_PORT_MPIN1_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN1: MPORTP16 Position */ -#define GPIO_PORT_MPIN1_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos) /*!< GPIO_PORT MPIN1: MPORTP16 Mask */ -#define GPIO_PORT_MPIN1_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN1: MPORTP17 Position */ -#define GPIO_PORT_MPIN1_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos) /*!< GPIO_PORT MPIN1: MPORTP17 Mask */ -#define GPIO_PORT_MPIN1_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN1: MPORTP18 Position */ -#define GPIO_PORT_MPIN1_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos) /*!< GPIO_PORT MPIN1: MPORTP18 Mask */ -#define GPIO_PORT_MPIN1_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN1: MPORTP19 Position */ -#define GPIO_PORT_MPIN1_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos) /*!< GPIO_PORT MPIN1: MPORTP19 Mask */ -#define GPIO_PORT_MPIN1_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN1: MPORTP20 Position */ -#define GPIO_PORT_MPIN1_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos) /*!< GPIO_PORT MPIN1: MPORTP20 Mask */ -#define GPIO_PORT_MPIN1_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN1: MPORTP21 Position */ -#define GPIO_PORT_MPIN1_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos) /*!< GPIO_PORT MPIN1: MPORTP21 Mask */ -#define GPIO_PORT_MPIN1_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN1: MPORTP22 Position */ -#define GPIO_PORT_MPIN1_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos) /*!< GPIO_PORT MPIN1: MPORTP22 Mask */ -#define GPIO_PORT_MPIN1_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN1: MPORTP23 Position */ -#define GPIO_PORT_MPIN1_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos) /*!< GPIO_PORT MPIN1: MPORTP23 Mask */ -#define GPIO_PORT_MPIN1_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN1: MPORTP24 Position */ -#define GPIO_PORT_MPIN1_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos) /*!< GPIO_PORT MPIN1: MPORTP24 Mask */ -#define GPIO_PORT_MPIN1_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN1: MPORTP25 Position */ -#define GPIO_PORT_MPIN1_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos) /*!< GPIO_PORT MPIN1: MPORTP25 Mask */ -#define GPIO_PORT_MPIN1_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN1: MPORTP26 Position */ -#define GPIO_PORT_MPIN1_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos) /*!< GPIO_PORT MPIN1: MPORTP26 Mask */ -#define GPIO_PORT_MPIN1_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN1: MPORTP27 Position */ -#define GPIO_PORT_MPIN1_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos) /*!< GPIO_PORT MPIN1: MPORTP27 Mask */ -#define GPIO_PORT_MPIN1_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN1: MPORTP28 Position */ -#define GPIO_PORT_MPIN1_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos) /*!< GPIO_PORT MPIN1: MPORTP28 Mask */ -#define GPIO_PORT_MPIN1_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN1: MPORTP29 Position */ -#define GPIO_PORT_MPIN1_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos) /*!< GPIO_PORT MPIN1: MPORTP29 Mask */ -#define GPIO_PORT_MPIN1_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN1: MPORTP30 Position */ -#define GPIO_PORT_MPIN1_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos) /*!< GPIO_PORT MPIN1: MPORTP30 Mask */ -#define GPIO_PORT_MPIN1_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN1: MPORTP31 Position */ -#define GPIO_PORT_MPIN1_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos) /*!< GPIO_PORT MPIN1: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN2 ---------------------------------------- -#define GPIO_PORT_MPIN2_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN2: MPORTP0 Position */ -#define GPIO_PORT_MPIN2_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos) /*!< GPIO_PORT MPIN2: MPORTP0 Mask */ -#define GPIO_PORT_MPIN2_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN2: MPORTP1 Position */ -#define GPIO_PORT_MPIN2_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos) /*!< GPIO_PORT MPIN2: MPORTP1 Mask */ -#define GPIO_PORT_MPIN2_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN2: MPORTP2 Position */ -#define GPIO_PORT_MPIN2_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos) /*!< GPIO_PORT MPIN2: MPORTP2 Mask */ -#define GPIO_PORT_MPIN2_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN2: MPORTP3 Position */ -#define GPIO_PORT_MPIN2_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos) /*!< GPIO_PORT MPIN2: MPORTP3 Mask */ -#define GPIO_PORT_MPIN2_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN2: MPORTP4 Position */ -#define GPIO_PORT_MPIN2_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos) /*!< GPIO_PORT MPIN2: MPORTP4 Mask */ -#define GPIO_PORT_MPIN2_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN2: MPORTP5 Position */ -#define GPIO_PORT_MPIN2_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos) /*!< GPIO_PORT MPIN2: MPORTP5 Mask */ -#define GPIO_PORT_MPIN2_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN2: MPORTP6 Position */ -#define GPIO_PORT_MPIN2_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos) /*!< GPIO_PORT MPIN2: MPORTP6 Mask */ -#define GPIO_PORT_MPIN2_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN2: MPORTP7 Position */ -#define GPIO_PORT_MPIN2_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos) /*!< GPIO_PORT MPIN2: MPORTP7 Mask */ -#define GPIO_PORT_MPIN2_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN2: MPORTP8 Position */ -#define GPIO_PORT_MPIN2_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos) /*!< GPIO_PORT MPIN2: MPORTP8 Mask */ -#define GPIO_PORT_MPIN2_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN2: MPORTP9 Position */ -#define GPIO_PORT_MPIN2_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos) /*!< GPIO_PORT MPIN2: MPORTP9 Mask */ -#define GPIO_PORT_MPIN2_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN2: MPORTP10 Position */ -#define GPIO_PORT_MPIN2_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos) /*!< GPIO_PORT MPIN2: MPORTP10 Mask */ -#define GPIO_PORT_MPIN2_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN2: MPORTP11 Position */ -#define GPIO_PORT_MPIN2_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos) /*!< GPIO_PORT MPIN2: MPORTP11 Mask */ -#define GPIO_PORT_MPIN2_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN2: MPORTP12 Position */ -#define GPIO_PORT_MPIN2_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos) /*!< GPIO_PORT MPIN2: MPORTP12 Mask */ -#define GPIO_PORT_MPIN2_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN2: MPORTP13 Position */ -#define GPIO_PORT_MPIN2_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos) /*!< GPIO_PORT MPIN2: MPORTP13 Mask */ -#define GPIO_PORT_MPIN2_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN2: MPORTP14 Position */ -#define GPIO_PORT_MPIN2_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos) /*!< GPIO_PORT MPIN2: MPORTP14 Mask */ -#define GPIO_PORT_MPIN2_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN2: MPORTP15 Position */ -#define GPIO_PORT_MPIN2_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos) /*!< GPIO_PORT MPIN2: MPORTP15 Mask */ -#define GPIO_PORT_MPIN2_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN2: MPORTP16 Position */ -#define GPIO_PORT_MPIN2_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos) /*!< GPIO_PORT MPIN2: MPORTP16 Mask */ -#define GPIO_PORT_MPIN2_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN2: MPORTP17 Position */ -#define GPIO_PORT_MPIN2_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos) /*!< GPIO_PORT MPIN2: MPORTP17 Mask */ -#define GPIO_PORT_MPIN2_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN2: MPORTP18 Position */ -#define GPIO_PORT_MPIN2_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos) /*!< GPIO_PORT MPIN2: MPORTP18 Mask */ -#define GPIO_PORT_MPIN2_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN2: MPORTP19 Position */ -#define GPIO_PORT_MPIN2_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos) /*!< GPIO_PORT MPIN2: MPORTP19 Mask */ -#define GPIO_PORT_MPIN2_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN2: MPORTP20 Position */ -#define GPIO_PORT_MPIN2_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos) /*!< GPIO_PORT MPIN2: MPORTP20 Mask */ -#define GPIO_PORT_MPIN2_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN2: MPORTP21 Position */ -#define GPIO_PORT_MPIN2_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos) /*!< GPIO_PORT MPIN2: MPORTP21 Mask */ -#define GPIO_PORT_MPIN2_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN2: MPORTP22 Position */ -#define GPIO_PORT_MPIN2_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos) /*!< GPIO_PORT MPIN2: MPORTP22 Mask */ -#define GPIO_PORT_MPIN2_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN2: MPORTP23 Position */ -#define GPIO_PORT_MPIN2_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos) /*!< GPIO_PORT MPIN2: MPORTP23 Mask */ -#define GPIO_PORT_MPIN2_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN2: MPORTP24 Position */ -#define GPIO_PORT_MPIN2_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos) /*!< GPIO_PORT MPIN2: MPORTP24 Mask */ -#define GPIO_PORT_MPIN2_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN2: MPORTP25 Position */ -#define GPIO_PORT_MPIN2_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos) /*!< GPIO_PORT MPIN2: MPORTP25 Mask */ -#define GPIO_PORT_MPIN2_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN2: MPORTP26 Position */ -#define GPIO_PORT_MPIN2_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos) /*!< GPIO_PORT MPIN2: MPORTP26 Mask */ -#define GPIO_PORT_MPIN2_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN2: MPORTP27 Position */ -#define GPIO_PORT_MPIN2_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos) /*!< GPIO_PORT MPIN2: MPORTP27 Mask */ -#define GPIO_PORT_MPIN2_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN2: MPORTP28 Position */ -#define GPIO_PORT_MPIN2_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos) /*!< GPIO_PORT MPIN2: MPORTP28 Mask */ -#define GPIO_PORT_MPIN2_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN2: MPORTP29 Position */ -#define GPIO_PORT_MPIN2_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos) /*!< GPIO_PORT MPIN2: MPORTP29 Mask */ -#define GPIO_PORT_MPIN2_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN2: MPORTP30 Position */ -#define GPIO_PORT_MPIN2_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos) /*!< GPIO_PORT MPIN2: MPORTP30 Mask */ -#define GPIO_PORT_MPIN2_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN2: MPORTP31 Position */ -#define GPIO_PORT_MPIN2_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos) /*!< GPIO_PORT MPIN2: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN3 ---------------------------------------- -#define GPIO_PORT_MPIN3_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN3: MPORTP0 Position */ -#define GPIO_PORT_MPIN3_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos) /*!< GPIO_PORT MPIN3: MPORTP0 Mask */ -#define GPIO_PORT_MPIN3_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN3: MPORTP1 Position */ -#define GPIO_PORT_MPIN3_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos) /*!< GPIO_PORT MPIN3: MPORTP1 Mask */ -#define GPIO_PORT_MPIN3_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN3: MPORTP2 Position */ -#define GPIO_PORT_MPIN3_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos) /*!< GPIO_PORT MPIN3: MPORTP2 Mask */ -#define GPIO_PORT_MPIN3_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN3: MPORTP3 Position */ -#define GPIO_PORT_MPIN3_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos) /*!< GPIO_PORT MPIN3: MPORTP3 Mask */ -#define GPIO_PORT_MPIN3_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN3: MPORTP4 Position */ -#define GPIO_PORT_MPIN3_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos) /*!< GPIO_PORT MPIN3: MPORTP4 Mask */ -#define GPIO_PORT_MPIN3_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN3: MPORTP5 Position */ -#define GPIO_PORT_MPIN3_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos) /*!< GPIO_PORT MPIN3: MPORTP5 Mask */ -#define GPIO_PORT_MPIN3_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN3: MPORTP6 Position */ -#define GPIO_PORT_MPIN3_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos) /*!< GPIO_PORT MPIN3: MPORTP6 Mask */ -#define GPIO_PORT_MPIN3_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN3: MPORTP7 Position */ -#define GPIO_PORT_MPIN3_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos) /*!< GPIO_PORT MPIN3: MPORTP7 Mask */ -#define GPIO_PORT_MPIN3_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN3: MPORTP8 Position */ -#define GPIO_PORT_MPIN3_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos) /*!< GPIO_PORT MPIN3: MPORTP8 Mask */ -#define GPIO_PORT_MPIN3_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN3: MPORTP9 Position */ -#define GPIO_PORT_MPIN3_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos) /*!< GPIO_PORT MPIN3: MPORTP9 Mask */ -#define GPIO_PORT_MPIN3_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN3: MPORTP10 Position */ -#define GPIO_PORT_MPIN3_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos) /*!< GPIO_PORT MPIN3: MPORTP10 Mask */ -#define GPIO_PORT_MPIN3_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN3: MPORTP11 Position */ -#define GPIO_PORT_MPIN3_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos) /*!< GPIO_PORT MPIN3: MPORTP11 Mask */ -#define GPIO_PORT_MPIN3_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN3: MPORTP12 Position */ -#define GPIO_PORT_MPIN3_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos) /*!< GPIO_PORT MPIN3: MPORTP12 Mask */ -#define GPIO_PORT_MPIN3_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN3: MPORTP13 Position */ -#define GPIO_PORT_MPIN3_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos) /*!< GPIO_PORT MPIN3: MPORTP13 Mask */ -#define GPIO_PORT_MPIN3_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN3: MPORTP14 Position */ -#define GPIO_PORT_MPIN3_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos) /*!< GPIO_PORT MPIN3: MPORTP14 Mask */ -#define GPIO_PORT_MPIN3_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN3: MPORTP15 Position */ -#define GPIO_PORT_MPIN3_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos) /*!< GPIO_PORT MPIN3: MPORTP15 Mask */ -#define GPIO_PORT_MPIN3_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN3: MPORTP16 Position */ -#define GPIO_PORT_MPIN3_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos) /*!< GPIO_PORT MPIN3: MPORTP16 Mask */ -#define GPIO_PORT_MPIN3_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN3: MPORTP17 Position */ -#define GPIO_PORT_MPIN3_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos) /*!< GPIO_PORT MPIN3: MPORTP17 Mask */ -#define GPIO_PORT_MPIN3_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN3: MPORTP18 Position */ -#define GPIO_PORT_MPIN3_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos) /*!< GPIO_PORT MPIN3: MPORTP18 Mask */ -#define GPIO_PORT_MPIN3_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN3: MPORTP19 Position */ -#define GPIO_PORT_MPIN3_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos) /*!< GPIO_PORT MPIN3: MPORTP19 Mask */ -#define GPIO_PORT_MPIN3_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN3: MPORTP20 Position */ -#define GPIO_PORT_MPIN3_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos) /*!< GPIO_PORT MPIN3: MPORTP20 Mask */ -#define GPIO_PORT_MPIN3_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN3: MPORTP21 Position */ -#define GPIO_PORT_MPIN3_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos) /*!< GPIO_PORT MPIN3: MPORTP21 Mask */ -#define GPIO_PORT_MPIN3_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN3: MPORTP22 Position */ -#define GPIO_PORT_MPIN3_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos) /*!< GPIO_PORT MPIN3: MPORTP22 Mask */ -#define GPIO_PORT_MPIN3_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN3: MPORTP23 Position */ -#define GPIO_PORT_MPIN3_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos) /*!< GPIO_PORT MPIN3: MPORTP23 Mask */ -#define GPIO_PORT_MPIN3_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN3: MPORTP24 Position */ -#define GPIO_PORT_MPIN3_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos) /*!< GPIO_PORT MPIN3: MPORTP24 Mask */ -#define GPIO_PORT_MPIN3_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN3: MPORTP25 Position */ -#define GPIO_PORT_MPIN3_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos) /*!< GPIO_PORT MPIN3: MPORTP25 Mask */ -#define GPIO_PORT_MPIN3_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN3: MPORTP26 Position */ -#define GPIO_PORT_MPIN3_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos) /*!< GPIO_PORT MPIN3: MPORTP26 Mask */ -#define GPIO_PORT_MPIN3_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN3: MPORTP27 Position */ -#define GPIO_PORT_MPIN3_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos) /*!< GPIO_PORT MPIN3: MPORTP27 Mask */ -#define GPIO_PORT_MPIN3_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN3: MPORTP28 Position */ -#define GPIO_PORT_MPIN3_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos) /*!< GPIO_PORT MPIN3: MPORTP28 Mask */ -#define GPIO_PORT_MPIN3_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN3: MPORTP29 Position */ -#define GPIO_PORT_MPIN3_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos) /*!< GPIO_PORT MPIN3: MPORTP29 Mask */ -#define GPIO_PORT_MPIN3_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN3: MPORTP30 Position */ -#define GPIO_PORT_MPIN3_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos) /*!< GPIO_PORT MPIN3: MPORTP30 Mask */ -#define GPIO_PORT_MPIN3_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN3: MPORTP31 Position */ -#define GPIO_PORT_MPIN3_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos) /*!< GPIO_PORT MPIN3: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN4 ---------------------------------------- -#define GPIO_PORT_MPIN4_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN4: MPORTP0 Position */ -#define GPIO_PORT_MPIN4_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos) /*!< GPIO_PORT MPIN4: MPORTP0 Mask */ -#define GPIO_PORT_MPIN4_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN4: MPORTP1 Position */ -#define GPIO_PORT_MPIN4_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos) /*!< GPIO_PORT MPIN4: MPORTP1 Mask */ -#define GPIO_PORT_MPIN4_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN4: MPORTP2 Position */ -#define GPIO_PORT_MPIN4_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos) /*!< GPIO_PORT MPIN4: MPORTP2 Mask */ -#define GPIO_PORT_MPIN4_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN4: MPORTP3 Position */ -#define GPIO_PORT_MPIN4_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos) /*!< GPIO_PORT MPIN4: MPORTP3 Mask */ -#define GPIO_PORT_MPIN4_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN4: MPORTP4 Position */ -#define GPIO_PORT_MPIN4_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos) /*!< GPIO_PORT MPIN4: MPORTP4 Mask */ -#define GPIO_PORT_MPIN4_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN4: MPORTP5 Position */ -#define GPIO_PORT_MPIN4_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos) /*!< GPIO_PORT MPIN4: MPORTP5 Mask */ -#define GPIO_PORT_MPIN4_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN4: MPORTP6 Position */ -#define GPIO_PORT_MPIN4_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos) /*!< GPIO_PORT MPIN4: MPORTP6 Mask */ -#define GPIO_PORT_MPIN4_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN4: MPORTP7 Position */ -#define GPIO_PORT_MPIN4_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos) /*!< GPIO_PORT MPIN4: MPORTP7 Mask */ -#define GPIO_PORT_MPIN4_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN4: MPORTP8 Position */ -#define GPIO_PORT_MPIN4_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos) /*!< GPIO_PORT MPIN4: MPORTP8 Mask */ -#define GPIO_PORT_MPIN4_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN4: MPORTP9 Position */ -#define GPIO_PORT_MPIN4_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos) /*!< GPIO_PORT MPIN4: MPORTP9 Mask */ -#define GPIO_PORT_MPIN4_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN4: MPORTP10 Position */ -#define GPIO_PORT_MPIN4_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos) /*!< GPIO_PORT MPIN4: MPORTP10 Mask */ -#define GPIO_PORT_MPIN4_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN4: MPORTP11 Position */ -#define GPIO_PORT_MPIN4_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos) /*!< GPIO_PORT MPIN4: MPORTP11 Mask */ -#define GPIO_PORT_MPIN4_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN4: MPORTP12 Position */ -#define GPIO_PORT_MPIN4_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos) /*!< GPIO_PORT MPIN4: MPORTP12 Mask */ -#define GPIO_PORT_MPIN4_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN4: MPORTP13 Position */ -#define GPIO_PORT_MPIN4_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos) /*!< GPIO_PORT MPIN4: MPORTP13 Mask */ -#define GPIO_PORT_MPIN4_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN4: MPORTP14 Position */ -#define GPIO_PORT_MPIN4_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos) /*!< GPIO_PORT MPIN4: MPORTP14 Mask */ -#define GPIO_PORT_MPIN4_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN4: MPORTP15 Position */ -#define GPIO_PORT_MPIN4_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos) /*!< GPIO_PORT MPIN4: MPORTP15 Mask */ -#define GPIO_PORT_MPIN4_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN4: MPORTP16 Position */ -#define GPIO_PORT_MPIN4_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos) /*!< GPIO_PORT MPIN4: MPORTP16 Mask */ -#define GPIO_PORT_MPIN4_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN4: MPORTP17 Position */ -#define GPIO_PORT_MPIN4_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos) /*!< GPIO_PORT MPIN4: MPORTP17 Mask */ -#define GPIO_PORT_MPIN4_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN4: MPORTP18 Position */ -#define GPIO_PORT_MPIN4_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos) /*!< GPIO_PORT MPIN4: MPORTP18 Mask */ -#define GPIO_PORT_MPIN4_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN4: MPORTP19 Position */ -#define GPIO_PORT_MPIN4_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos) /*!< GPIO_PORT MPIN4: MPORTP19 Mask */ -#define GPIO_PORT_MPIN4_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN4: MPORTP20 Position */ -#define GPIO_PORT_MPIN4_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos) /*!< GPIO_PORT MPIN4: MPORTP20 Mask */ -#define GPIO_PORT_MPIN4_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN4: MPORTP21 Position */ -#define GPIO_PORT_MPIN4_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos) /*!< GPIO_PORT MPIN4: MPORTP21 Mask */ -#define GPIO_PORT_MPIN4_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN4: MPORTP22 Position */ -#define GPIO_PORT_MPIN4_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos) /*!< GPIO_PORT MPIN4: MPORTP22 Mask */ -#define GPIO_PORT_MPIN4_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN4: MPORTP23 Position */ -#define GPIO_PORT_MPIN4_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos) /*!< GPIO_PORT MPIN4: MPORTP23 Mask */ -#define GPIO_PORT_MPIN4_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN4: MPORTP24 Position */ -#define GPIO_PORT_MPIN4_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos) /*!< GPIO_PORT MPIN4: MPORTP24 Mask */ -#define GPIO_PORT_MPIN4_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN4: MPORTP25 Position */ -#define GPIO_PORT_MPIN4_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos) /*!< GPIO_PORT MPIN4: MPORTP25 Mask */ -#define GPIO_PORT_MPIN4_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN4: MPORTP26 Position */ -#define GPIO_PORT_MPIN4_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos) /*!< GPIO_PORT MPIN4: MPORTP26 Mask */ -#define GPIO_PORT_MPIN4_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN4: MPORTP27 Position */ -#define GPIO_PORT_MPIN4_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos) /*!< GPIO_PORT MPIN4: MPORTP27 Mask */ -#define GPIO_PORT_MPIN4_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN4: MPORTP28 Position */ -#define GPIO_PORT_MPIN4_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos) /*!< GPIO_PORT MPIN4: MPORTP28 Mask */ -#define GPIO_PORT_MPIN4_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN4: MPORTP29 Position */ -#define GPIO_PORT_MPIN4_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos) /*!< GPIO_PORT MPIN4: MPORTP29 Mask */ -#define GPIO_PORT_MPIN4_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN4: MPORTP30 Position */ -#define GPIO_PORT_MPIN4_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos) /*!< GPIO_PORT MPIN4: MPORTP30 Mask */ -#define GPIO_PORT_MPIN4_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN4: MPORTP31 Position */ -#define GPIO_PORT_MPIN4_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos) /*!< GPIO_PORT MPIN4: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN5 ---------------------------------------- -#define GPIO_PORT_MPIN5_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN5: MPORTP0 Position */ -#define GPIO_PORT_MPIN5_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos) /*!< GPIO_PORT MPIN5: MPORTP0 Mask */ -#define GPIO_PORT_MPIN5_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN5: MPORTP1 Position */ -#define GPIO_PORT_MPIN5_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos) /*!< GPIO_PORT MPIN5: MPORTP1 Mask */ -#define GPIO_PORT_MPIN5_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN5: MPORTP2 Position */ -#define GPIO_PORT_MPIN5_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos) /*!< GPIO_PORT MPIN5: MPORTP2 Mask */ -#define GPIO_PORT_MPIN5_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN5: MPORTP3 Position */ -#define GPIO_PORT_MPIN5_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos) /*!< GPIO_PORT MPIN5: MPORTP3 Mask */ -#define GPIO_PORT_MPIN5_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN5: MPORTP4 Position */ -#define GPIO_PORT_MPIN5_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos) /*!< GPIO_PORT MPIN5: MPORTP4 Mask */ -#define GPIO_PORT_MPIN5_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN5: MPORTP5 Position */ -#define GPIO_PORT_MPIN5_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos) /*!< GPIO_PORT MPIN5: MPORTP5 Mask */ -#define GPIO_PORT_MPIN5_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN5: MPORTP6 Position */ -#define GPIO_PORT_MPIN5_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos) /*!< GPIO_PORT MPIN5: MPORTP6 Mask */ -#define GPIO_PORT_MPIN5_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN5: MPORTP7 Position */ -#define GPIO_PORT_MPIN5_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos) /*!< GPIO_PORT MPIN5: MPORTP7 Mask */ -#define GPIO_PORT_MPIN5_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN5: MPORTP8 Position */ -#define GPIO_PORT_MPIN5_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos) /*!< GPIO_PORT MPIN5: MPORTP8 Mask */ -#define GPIO_PORT_MPIN5_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN5: MPORTP9 Position */ -#define GPIO_PORT_MPIN5_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos) /*!< GPIO_PORT MPIN5: MPORTP9 Mask */ -#define GPIO_PORT_MPIN5_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN5: MPORTP10 Position */ -#define GPIO_PORT_MPIN5_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos) /*!< GPIO_PORT MPIN5: MPORTP10 Mask */ -#define GPIO_PORT_MPIN5_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN5: MPORTP11 Position */ -#define GPIO_PORT_MPIN5_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos) /*!< GPIO_PORT MPIN5: MPORTP11 Mask */ -#define GPIO_PORT_MPIN5_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN5: MPORTP12 Position */ -#define GPIO_PORT_MPIN5_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos) /*!< GPIO_PORT MPIN5: MPORTP12 Mask */ -#define GPIO_PORT_MPIN5_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN5: MPORTP13 Position */ -#define GPIO_PORT_MPIN5_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos) /*!< GPIO_PORT MPIN5: MPORTP13 Mask */ -#define GPIO_PORT_MPIN5_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN5: MPORTP14 Position */ -#define GPIO_PORT_MPIN5_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos) /*!< GPIO_PORT MPIN5: MPORTP14 Mask */ -#define GPIO_PORT_MPIN5_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN5: MPORTP15 Position */ -#define GPIO_PORT_MPIN5_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos) /*!< GPIO_PORT MPIN5: MPORTP15 Mask */ -#define GPIO_PORT_MPIN5_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN5: MPORTP16 Position */ -#define GPIO_PORT_MPIN5_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos) /*!< GPIO_PORT MPIN5: MPORTP16 Mask */ -#define GPIO_PORT_MPIN5_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN5: MPORTP17 Position */ -#define GPIO_PORT_MPIN5_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos) /*!< GPIO_PORT MPIN5: MPORTP17 Mask */ -#define GPIO_PORT_MPIN5_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN5: MPORTP18 Position */ -#define GPIO_PORT_MPIN5_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos) /*!< GPIO_PORT MPIN5: MPORTP18 Mask */ -#define GPIO_PORT_MPIN5_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN5: MPORTP19 Position */ -#define GPIO_PORT_MPIN5_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos) /*!< GPIO_PORT MPIN5: MPORTP19 Mask */ -#define GPIO_PORT_MPIN5_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN5: MPORTP20 Position */ -#define GPIO_PORT_MPIN5_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos) /*!< GPIO_PORT MPIN5: MPORTP20 Mask */ -#define GPIO_PORT_MPIN5_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN5: MPORTP21 Position */ -#define GPIO_PORT_MPIN5_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos) /*!< GPIO_PORT MPIN5: MPORTP21 Mask */ -#define GPIO_PORT_MPIN5_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN5: MPORTP22 Position */ -#define GPIO_PORT_MPIN5_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos) /*!< GPIO_PORT MPIN5: MPORTP22 Mask */ -#define GPIO_PORT_MPIN5_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN5: MPORTP23 Position */ -#define GPIO_PORT_MPIN5_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos) /*!< GPIO_PORT MPIN5: MPORTP23 Mask */ -#define GPIO_PORT_MPIN5_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN5: MPORTP24 Position */ -#define GPIO_PORT_MPIN5_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos) /*!< GPIO_PORT MPIN5: MPORTP24 Mask */ -#define GPIO_PORT_MPIN5_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN5: MPORTP25 Position */ -#define GPIO_PORT_MPIN5_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos) /*!< GPIO_PORT MPIN5: MPORTP25 Mask */ -#define GPIO_PORT_MPIN5_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN5: MPORTP26 Position */ -#define GPIO_PORT_MPIN5_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos) /*!< GPIO_PORT MPIN5: MPORTP26 Mask */ -#define GPIO_PORT_MPIN5_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN5: MPORTP27 Position */ -#define GPIO_PORT_MPIN5_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos) /*!< GPIO_PORT MPIN5: MPORTP27 Mask */ -#define GPIO_PORT_MPIN5_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN5: MPORTP28 Position */ -#define GPIO_PORT_MPIN5_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos) /*!< GPIO_PORT MPIN5: MPORTP28 Mask */ -#define GPIO_PORT_MPIN5_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN5: MPORTP29 Position */ -#define GPIO_PORT_MPIN5_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos) /*!< GPIO_PORT MPIN5: MPORTP29 Mask */ -#define GPIO_PORT_MPIN5_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN5: MPORTP30 Position */ -#define GPIO_PORT_MPIN5_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos) /*!< GPIO_PORT MPIN5: MPORTP30 Mask */ -#define GPIO_PORT_MPIN5_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN5: MPORTP31 Position */ -#define GPIO_PORT_MPIN5_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos) /*!< GPIO_PORT MPIN5: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN6 ---------------------------------------- -#define GPIO_PORT_MPIN6_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN6: MPORTP0 Position */ -#define GPIO_PORT_MPIN6_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos) /*!< GPIO_PORT MPIN6: MPORTP0 Mask */ -#define GPIO_PORT_MPIN6_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN6: MPORTP1 Position */ -#define GPIO_PORT_MPIN6_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos) /*!< GPIO_PORT MPIN6: MPORTP1 Mask */ -#define GPIO_PORT_MPIN6_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN6: MPORTP2 Position */ -#define GPIO_PORT_MPIN6_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos) /*!< GPIO_PORT MPIN6: MPORTP2 Mask */ -#define GPIO_PORT_MPIN6_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN6: MPORTP3 Position */ -#define GPIO_PORT_MPIN6_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos) /*!< GPIO_PORT MPIN6: MPORTP3 Mask */ -#define GPIO_PORT_MPIN6_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN6: MPORTP4 Position */ -#define GPIO_PORT_MPIN6_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos) /*!< GPIO_PORT MPIN6: MPORTP4 Mask */ -#define GPIO_PORT_MPIN6_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN6: MPORTP5 Position */ -#define GPIO_PORT_MPIN6_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos) /*!< GPIO_PORT MPIN6: MPORTP5 Mask */ -#define GPIO_PORT_MPIN6_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN6: MPORTP6 Position */ -#define GPIO_PORT_MPIN6_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos) /*!< GPIO_PORT MPIN6: MPORTP6 Mask */ -#define GPIO_PORT_MPIN6_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN6: MPORTP7 Position */ -#define GPIO_PORT_MPIN6_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos) /*!< GPIO_PORT MPIN6: MPORTP7 Mask */ -#define GPIO_PORT_MPIN6_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN6: MPORTP8 Position */ -#define GPIO_PORT_MPIN6_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos) /*!< GPIO_PORT MPIN6: MPORTP8 Mask */ -#define GPIO_PORT_MPIN6_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN6: MPORTP9 Position */ -#define GPIO_PORT_MPIN6_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos) /*!< GPIO_PORT MPIN6: MPORTP9 Mask */ -#define GPIO_PORT_MPIN6_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN6: MPORTP10 Position */ -#define GPIO_PORT_MPIN6_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos) /*!< GPIO_PORT MPIN6: MPORTP10 Mask */ -#define GPIO_PORT_MPIN6_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN6: MPORTP11 Position */ -#define GPIO_PORT_MPIN6_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos) /*!< GPIO_PORT MPIN6: MPORTP11 Mask */ -#define GPIO_PORT_MPIN6_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN6: MPORTP12 Position */ -#define GPIO_PORT_MPIN6_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos) /*!< GPIO_PORT MPIN6: MPORTP12 Mask */ -#define GPIO_PORT_MPIN6_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN6: MPORTP13 Position */ -#define GPIO_PORT_MPIN6_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos) /*!< GPIO_PORT MPIN6: MPORTP13 Mask */ -#define GPIO_PORT_MPIN6_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN6: MPORTP14 Position */ -#define GPIO_PORT_MPIN6_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos) /*!< GPIO_PORT MPIN6: MPORTP14 Mask */ -#define GPIO_PORT_MPIN6_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN6: MPORTP15 Position */ -#define GPIO_PORT_MPIN6_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos) /*!< GPIO_PORT MPIN6: MPORTP15 Mask */ -#define GPIO_PORT_MPIN6_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN6: MPORTP16 Position */ -#define GPIO_PORT_MPIN6_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos) /*!< GPIO_PORT MPIN6: MPORTP16 Mask */ -#define GPIO_PORT_MPIN6_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN6: MPORTP17 Position */ -#define GPIO_PORT_MPIN6_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos) /*!< GPIO_PORT MPIN6: MPORTP17 Mask */ -#define GPIO_PORT_MPIN6_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN6: MPORTP18 Position */ -#define GPIO_PORT_MPIN6_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos) /*!< GPIO_PORT MPIN6: MPORTP18 Mask */ -#define GPIO_PORT_MPIN6_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN6: MPORTP19 Position */ -#define GPIO_PORT_MPIN6_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos) /*!< GPIO_PORT MPIN6: MPORTP19 Mask */ -#define GPIO_PORT_MPIN6_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN6: MPORTP20 Position */ -#define GPIO_PORT_MPIN6_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos) /*!< GPIO_PORT MPIN6: MPORTP20 Mask */ -#define GPIO_PORT_MPIN6_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN6: MPORTP21 Position */ -#define GPIO_PORT_MPIN6_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos) /*!< GPIO_PORT MPIN6: MPORTP21 Mask */ -#define GPIO_PORT_MPIN6_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN6: MPORTP22 Position */ -#define GPIO_PORT_MPIN6_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos) /*!< GPIO_PORT MPIN6: MPORTP22 Mask */ -#define GPIO_PORT_MPIN6_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN6: MPORTP23 Position */ -#define GPIO_PORT_MPIN6_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos) /*!< GPIO_PORT MPIN6: MPORTP23 Mask */ -#define GPIO_PORT_MPIN6_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN6: MPORTP24 Position */ -#define GPIO_PORT_MPIN6_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos) /*!< GPIO_PORT MPIN6: MPORTP24 Mask */ -#define GPIO_PORT_MPIN6_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN6: MPORTP25 Position */ -#define GPIO_PORT_MPIN6_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos) /*!< GPIO_PORT MPIN6: MPORTP25 Mask */ -#define GPIO_PORT_MPIN6_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN6: MPORTP26 Position */ -#define GPIO_PORT_MPIN6_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos) /*!< GPIO_PORT MPIN6: MPORTP26 Mask */ -#define GPIO_PORT_MPIN6_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN6: MPORTP27 Position */ -#define GPIO_PORT_MPIN6_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos) /*!< GPIO_PORT MPIN6: MPORTP27 Mask */ -#define GPIO_PORT_MPIN6_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN6: MPORTP28 Position */ -#define GPIO_PORT_MPIN6_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos) /*!< GPIO_PORT MPIN6: MPORTP28 Mask */ -#define GPIO_PORT_MPIN6_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN6: MPORTP29 Position */ -#define GPIO_PORT_MPIN6_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos) /*!< GPIO_PORT MPIN6: MPORTP29 Mask */ -#define GPIO_PORT_MPIN6_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN6: MPORTP30 Position */ -#define GPIO_PORT_MPIN6_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos) /*!< GPIO_PORT MPIN6: MPORTP30 Mask */ -#define GPIO_PORT_MPIN6_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN6: MPORTP31 Position */ -#define GPIO_PORT_MPIN6_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos) /*!< GPIO_PORT MPIN6: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN7 ---------------------------------------- -#define GPIO_PORT_MPIN7_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN7: MPORTP0 Position */ -#define GPIO_PORT_MPIN7_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos) /*!< GPIO_PORT MPIN7: MPORTP0 Mask */ -#define GPIO_PORT_MPIN7_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN7: MPORTP1 Position */ -#define GPIO_PORT_MPIN7_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos) /*!< GPIO_PORT MPIN7: MPORTP1 Mask */ -#define GPIO_PORT_MPIN7_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN7: MPORTP2 Position */ -#define GPIO_PORT_MPIN7_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos) /*!< GPIO_PORT MPIN7: MPORTP2 Mask */ -#define GPIO_PORT_MPIN7_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN7: MPORTP3 Position */ -#define GPIO_PORT_MPIN7_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos) /*!< GPIO_PORT MPIN7: MPORTP3 Mask */ -#define GPIO_PORT_MPIN7_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN7: MPORTP4 Position */ -#define GPIO_PORT_MPIN7_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos) /*!< GPIO_PORT MPIN7: MPORTP4 Mask */ -#define GPIO_PORT_MPIN7_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN7: MPORTP5 Position */ -#define GPIO_PORT_MPIN7_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos) /*!< GPIO_PORT MPIN7: MPORTP5 Mask */ -#define GPIO_PORT_MPIN7_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN7: MPORTP6 Position */ -#define GPIO_PORT_MPIN7_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos) /*!< GPIO_PORT MPIN7: MPORTP6 Mask */ -#define GPIO_PORT_MPIN7_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN7: MPORTP7 Position */ -#define GPIO_PORT_MPIN7_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos) /*!< GPIO_PORT MPIN7: MPORTP7 Mask */ -#define GPIO_PORT_MPIN7_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN7: MPORTP8 Position */ -#define GPIO_PORT_MPIN7_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos) /*!< GPIO_PORT MPIN7: MPORTP8 Mask */ -#define GPIO_PORT_MPIN7_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN7: MPORTP9 Position */ -#define GPIO_PORT_MPIN7_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos) /*!< GPIO_PORT MPIN7: MPORTP9 Mask */ -#define GPIO_PORT_MPIN7_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN7: MPORTP10 Position */ -#define GPIO_PORT_MPIN7_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos) /*!< GPIO_PORT MPIN7: MPORTP10 Mask */ -#define GPIO_PORT_MPIN7_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN7: MPORTP11 Position */ -#define GPIO_PORT_MPIN7_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos) /*!< GPIO_PORT MPIN7: MPORTP11 Mask */ -#define GPIO_PORT_MPIN7_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN7: MPORTP12 Position */ -#define GPIO_PORT_MPIN7_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos) /*!< GPIO_PORT MPIN7: MPORTP12 Mask */ -#define GPIO_PORT_MPIN7_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN7: MPORTP13 Position */ -#define GPIO_PORT_MPIN7_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos) /*!< GPIO_PORT MPIN7: MPORTP13 Mask */ -#define GPIO_PORT_MPIN7_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN7: MPORTP14 Position */ -#define GPIO_PORT_MPIN7_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos) /*!< GPIO_PORT MPIN7: MPORTP14 Mask */ -#define GPIO_PORT_MPIN7_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN7: MPORTP15 Position */ -#define GPIO_PORT_MPIN7_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos) /*!< GPIO_PORT MPIN7: MPORTP15 Mask */ -#define GPIO_PORT_MPIN7_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN7: MPORTP16 Position */ -#define GPIO_PORT_MPIN7_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos) /*!< GPIO_PORT MPIN7: MPORTP16 Mask */ -#define GPIO_PORT_MPIN7_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN7: MPORTP17 Position */ -#define GPIO_PORT_MPIN7_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos) /*!< GPIO_PORT MPIN7: MPORTP17 Mask */ -#define GPIO_PORT_MPIN7_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN7: MPORTP18 Position */ -#define GPIO_PORT_MPIN7_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos) /*!< GPIO_PORT MPIN7: MPORTP18 Mask */ -#define GPIO_PORT_MPIN7_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN7: MPORTP19 Position */ -#define GPIO_PORT_MPIN7_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos) /*!< GPIO_PORT MPIN7: MPORTP19 Mask */ -#define GPIO_PORT_MPIN7_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN7: MPORTP20 Position */ -#define GPIO_PORT_MPIN7_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos) /*!< GPIO_PORT MPIN7: MPORTP20 Mask */ -#define GPIO_PORT_MPIN7_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN7: MPORTP21 Position */ -#define GPIO_PORT_MPIN7_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos) /*!< GPIO_PORT MPIN7: MPORTP21 Mask */ -#define GPIO_PORT_MPIN7_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN7: MPORTP22 Position */ -#define GPIO_PORT_MPIN7_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos) /*!< GPIO_PORT MPIN7: MPORTP22 Mask */ -#define GPIO_PORT_MPIN7_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN7: MPORTP23 Position */ -#define GPIO_PORT_MPIN7_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos) /*!< GPIO_PORT MPIN7: MPORTP23 Mask */ -#define GPIO_PORT_MPIN7_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN7: MPORTP24 Position */ -#define GPIO_PORT_MPIN7_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos) /*!< GPIO_PORT MPIN7: MPORTP24 Mask */ -#define GPIO_PORT_MPIN7_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN7: MPORTP25 Position */ -#define GPIO_PORT_MPIN7_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos) /*!< GPIO_PORT MPIN7: MPORTP25 Mask */ -#define GPIO_PORT_MPIN7_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN7: MPORTP26 Position */ -#define GPIO_PORT_MPIN7_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos) /*!< GPIO_PORT MPIN7: MPORTP26 Mask */ -#define GPIO_PORT_MPIN7_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN7: MPORTP27 Position */ -#define GPIO_PORT_MPIN7_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos) /*!< GPIO_PORT MPIN7: MPORTP27 Mask */ -#define GPIO_PORT_MPIN7_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN7: MPORTP28 Position */ -#define GPIO_PORT_MPIN7_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos) /*!< GPIO_PORT MPIN7: MPORTP28 Mask */ -#define GPIO_PORT_MPIN7_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN7: MPORTP29 Position */ -#define GPIO_PORT_MPIN7_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos) /*!< GPIO_PORT MPIN7: MPORTP29 Mask */ -#define GPIO_PORT_MPIN7_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN7: MPORTP30 Position */ -#define GPIO_PORT_MPIN7_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos) /*!< GPIO_PORT MPIN7: MPORTP30 Mask */ -#define GPIO_PORT_MPIN7_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN7: MPORTP31 Position */ -#define GPIO_PORT_MPIN7_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos) /*!< GPIO_PORT MPIN7: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET0 ----------------------------------------- -#define GPIO_PORT_SET0_SETP0_Pos 0 /*!< GPIO_PORT SET0: SETP0 Position */ -#define GPIO_PORT_SET0_SETP0_Msk (0x01UL << GPIO_PORT_SET0_SETP0_Pos) /*!< GPIO_PORT SET0: SETP0 Mask */ -#define GPIO_PORT_SET0_SETP1_Pos 1 /*!< GPIO_PORT SET0: SETP1 Position */ -#define GPIO_PORT_SET0_SETP1_Msk (0x01UL << GPIO_PORT_SET0_SETP1_Pos) /*!< GPIO_PORT SET0: SETP1 Mask */ -#define GPIO_PORT_SET0_SETP2_Pos 2 /*!< GPIO_PORT SET0: SETP2 Position */ -#define GPIO_PORT_SET0_SETP2_Msk (0x01UL << GPIO_PORT_SET0_SETP2_Pos) /*!< GPIO_PORT SET0: SETP2 Mask */ -#define GPIO_PORT_SET0_SETP3_Pos 3 /*!< GPIO_PORT SET0: SETP3 Position */ -#define GPIO_PORT_SET0_SETP3_Msk (0x01UL << GPIO_PORT_SET0_SETP3_Pos) /*!< GPIO_PORT SET0: SETP3 Mask */ -#define GPIO_PORT_SET0_SETP4_Pos 4 /*!< GPIO_PORT SET0: SETP4 Position */ -#define GPIO_PORT_SET0_SETP4_Msk (0x01UL << GPIO_PORT_SET0_SETP4_Pos) /*!< GPIO_PORT SET0: SETP4 Mask */ -#define GPIO_PORT_SET0_SETP5_Pos 5 /*!< GPIO_PORT SET0: SETP5 Position */ -#define GPIO_PORT_SET0_SETP5_Msk (0x01UL << GPIO_PORT_SET0_SETP5_Pos) /*!< GPIO_PORT SET0: SETP5 Mask */ -#define GPIO_PORT_SET0_SETP6_Pos 6 /*!< GPIO_PORT SET0: SETP6 Position */ -#define GPIO_PORT_SET0_SETP6_Msk (0x01UL << GPIO_PORT_SET0_SETP6_Pos) /*!< GPIO_PORT SET0: SETP6 Mask */ -#define GPIO_PORT_SET0_SETP7_Pos 7 /*!< GPIO_PORT SET0: SETP7 Position */ -#define GPIO_PORT_SET0_SETP7_Msk (0x01UL << GPIO_PORT_SET0_SETP7_Pos) /*!< GPIO_PORT SET0: SETP7 Mask */ -#define GPIO_PORT_SET0_SETP8_Pos 8 /*!< GPIO_PORT SET0: SETP8 Position */ -#define GPIO_PORT_SET0_SETP8_Msk (0x01UL << GPIO_PORT_SET0_SETP8_Pos) /*!< GPIO_PORT SET0: SETP8 Mask */ -#define GPIO_PORT_SET0_SETP9_Pos 9 /*!< GPIO_PORT SET0: SETP9 Position */ -#define GPIO_PORT_SET0_SETP9_Msk (0x01UL << GPIO_PORT_SET0_SETP9_Pos) /*!< GPIO_PORT SET0: SETP9 Mask */ -#define GPIO_PORT_SET0_SETP10_Pos 10 /*!< GPIO_PORT SET0: SETP10 Position */ -#define GPIO_PORT_SET0_SETP10_Msk (0x01UL << GPIO_PORT_SET0_SETP10_Pos) /*!< GPIO_PORT SET0: SETP10 Mask */ -#define GPIO_PORT_SET0_SETP11_Pos 11 /*!< GPIO_PORT SET0: SETP11 Position */ -#define GPIO_PORT_SET0_SETP11_Msk (0x01UL << GPIO_PORT_SET0_SETP11_Pos) /*!< GPIO_PORT SET0: SETP11 Mask */ -#define GPIO_PORT_SET0_SETP12_Pos 12 /*!< GPIO_PORT SET0: SETP12 Position */ -#define GPIO_PORT_SET0_SETP12_Msk (0x01UL << GPIO_PORT_SET0_SETP12_Pos) /*!< GPIO_PORT SET0: SETP12 Mask */ -#define GPIO_PORT_SET0_SETP13_Pos 13 /*!< GPIO_PORT SET0: SETP13 Position */ -#define GPIO_PORT_SET0_SETP13_Msk (0x01UL << GPIO_PORT_SET0_SETP13_Pos) /*!< GPIO_PORT SET0: SETP13 Mask */ -#define GPIO_PORT_SET0_SETP14_Pos 14 /*!< GPIO_PORT SET0: SETP14 Position */ -#define GPIO_PORT_SET0_SETP14_Msk (0x01UL << GPIO_PORT_SET0_SETP14_Pos) /*!< GPIO_PORT SET0: SETP14 Mask */ -#define GPIO_PORT_SET0_SETP15_Pos 15 /*!< GPIO_PORT SET0: SETP15 Position */ -#define GPIO_PORT_SET0_SETP15_Msk (0x01UL << GPIO_PORT_SET0_SETP15_Pos) /*!< GPIO_PORT SET0: SETP15 Mask */ -#define GPIO_PORT_SET0_SETP16_Pos 16 /*!< GPIO_PORT SET0: SETP16 Position */ -#define GPIO_PORT_SET0_SETP16_Msk (0x01UL << GPIO_PORT_SET0_SETP16_Pos) /*!< GPIO_PORT SET0: SETP16 Mask */ -#define GPIO_PORT_SET0_SETP17_Pos 17 /*!< GPIO_PORT SET0: SETP17 Position */ -#define GPIO_PORT_SET0_SETP17_Msk (0x01UL << GPIO_PORT_SET0_SETP17_Pos) /*!< GPIO_PORT SET0: SETP17 Mask */ -#define GPIO_PORT_SET0_SETP18_Pos 18 /*!< GPIO_PORT SET0: SETP18 Position */ -#define GPIO_PORT_SET0_SETP18_Msk (0x01UL << GPIO_PORT_SET0_SETP18_Pos) /*!< GPIO_PORT SET0: SETP18 Mask */ -#define GPIO_PORT_SET0_SETP19_Pos 19 /*!< GPIO_PORT SET0: SETP19 Position */ -#define GPIO_PORT_SET0_SETP19_Msk (0x01UL << GPIO_PORT_SET0_SETP19_Pos) /*!< GPIO_PORT SET0: SETP19 Mask */ -#define GPIO_PORT_SET0_SETP20_Pos 20 /*!< GPIO_PORT SET0: SETP20 Position */ -#define GPIO_PORT_SET0_SETP20_Msk (0x01UL << GPIO_PORT_SET0_SETP20_Pos) /*!< GPIO_PORT SET0: SETP20 Mask */ -#define GPIO_PORT_SET0_SETP21_Pos 21 /*!< GPIO_PORT SET0: SETP21 Position */ -#define GPIO_PORT_SET0_SETP21_Msk (0x01UL << GPIO_PORT_SET0_SETP21_Pos) /*!< GPIO_PORT SET0: SETP21 Mask */ -#define GPIO_PORT_SET0_SETP22_Pos 22 /*!< GPIO_PORT SET0: SETP22 Position */ -#define GPIO_PORT_SET0_SETP22_Msk (0x01UL << GPIO_PORT_SET0_SETP22_Pos) /*!< GPIO_PORT SET0: SETP22 Mask */ -#define GPIO_PORT_SET0_SETP23_Pos 23 /*!< GPIO_PORT SET0: SETP23 Position */ -#define GPIO_PORT_SET0_SETP23_Msk (0x01UL << GPIO_PORT_SET0_SETP23_Pos) /*!< GPIO_PORT SET0: SETP23 Mask */ -#define GPIO_PORT_SET0_SETP24_Pos 24 /*!< GPIO_PORT SET0: SETP24 Position */ -#define GPIO_PORT_SET0_SETP24_Msk (0x01UL << GPIO_PORT_SET0_SETP24_Pos) /*!< GPIO_PORT SET0: SETP24 Mask */ -#define GPIO_PORT_SET0_SETP25_Pos 25 /*!< GPIO_PORT SET0: SETP25 Position */ -#define GPIO_PORT_SET0_SETP25_Msk (0x01UL << GPIO_PORT_SET0_SETP25_Pos) /*!< GPIO_PORT SET0: SETP25 Mask */ -#define GPIO_PORT_SET0_SETP26_Pos 26 /*!< GPIO_PORT SET0: SETP26 Position */ -#define GPIO_PORT_SET0_SETP26_Msk (0x01UL << GPIO_PORT_SET0_SETP26_Pos) /*!< GPIO_PORT SET0: SETP26 Mask */ -#define GPIO_PORT_SET0_SETP27_Pos 27 /*!< GPIO_PORT SET0: SETP27 Position */ -#define GPIO_PORT_SET0_SETP27_Msk (0x01UL << GPIO_PORT_SET0_SETP27_Pos) /*!< GPIO_PORT SET0: SETP27 Mask */ -#define GPIO_PORT_SET0_SETP28_Pos 28 /*!< GPIO_PORT SET0: SETP28 Position */ -#define GPIO_PORT_SET0_SETP28_Msk (0x01UL << GPIO_PORT_SET0_SETP28_Pos) /*!< GPIO_PORT SET0: SETP28 Mask */ -#define GPIO_PORT_SET0_SETP29_Pos 29 /*!< GPIO_PORT SET0: SETP29 Position */ -#define GPIO_PORT_SET0_SETP29_Msk (0x01UL << GPIO_PORT_SET0_SETP29_Pos) /*!< GPIO_PORT SET0: SETP29 Mask */ -#define GPIO_PORT_SET0_SETP30_Pos 30 /*!< GPIO_PORT SET0: SETP30 Position */ -#define GPIO_PORT_SET0_SETP30_Msk (0x01UL << GPIO_PORT_SET0_SETP30_Pos) /*!< GPIO_PORT SET0: SETP30 Mask */ -#define GPIO_PORT_SET0_SETP31_Pos 31 /*!< GPIO_PORT SET0: SETP31 Position */ -#define GPIO_PORT_SET0_SETP31_Msk (0x01UL << GPIO_PORT_SET0_SETP31_Pos) /*!< GPIO_PORT SET0: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET1 ----------------------------------------- -#define GPIO_PORT_SET1_SETP0_Pos 0 /*!< GPIO_PORT SET1: SETP0 Position */ -#define GPIO_PORT_SET1_SETP0_Msk (0x01UL << GPIO_PORT_SET1_SETP0_Pos) /*!< GPIO_PORT SET1: SETP0 Mask */ -#define GPIO_PORT_SET1_SETP1_Pos 1 /*!< GPIO_PORT SET1: SETP1 Position */ -#define GPIO_PORT_SET1_SETP1_Msk (0x01UL << GPIO_PORT_SET1_SETP1_Pos) /*!< GPIO_PORT SET1: SETP1 Mask */ -#define GPIO_PORT_SET1_SETP2_Pos 2 /*!< GPIO_PORT SET1: SETP2 Position */ -#define GPIO_PORT_SET1_SETP2_Msk (0x01UL << GPIO_PORT_SET1_SETP2_Pos) /*!< GPIO_PORT SET1: SETP2 Mask */ -#define GPIO_PORT_SET1_SETP3_Pos 3 /*!< GPIO_PORT SET1: SETP3 Position */ -#define GPIO_PORT_SET1_SETP3_Msk (0x01UL << GPIO_PORT_SET1_SETP3_Pos) /*!< GPIO_PORT SET1: SETP3 Mask */ -#define GPIO_PORT_SET1_SETP4_Pos 4 /*!< GPIO_PORT SET1: SETP4 Position */ -#define GPIO_PORT_SET1_SETP4_Msk (0x01UL << GPIO_PORT_SET1_SETP4_Pos) /*!< GPIO_PORT SET1: SETP4 Mask */ -#define GPIO_PORT_SET1_SETP5_Pos 5 /*!< GPIO_PORT SET1: SETP5 Position */ -#define GPIO_PORT_SET1_SETP5_Msk (0x01UL << GPIO_PORT_SET1_SETP5_Pos) /*!< GPIO_PORT SET1: SETP5 Mask */ -#define GPIO_PORT_SET1_SETP6_Pos 6 /*!< GPIO_PORT SET1: SETP6 Position */ -#define GPIO_PORT_SET1_SETP6_Msk (0x01UL << GPIO_PORT_SET1_SETP6_Pos) /*!< GPIO_PORT SET1: SETP6 Mask */ -#define GPIO_PORT_SET1_SETP7_Pos 7 /*!< GPIO_PORT SET1: SETP7 Position */ -#define GPIO_PORT_SET1_SETP7_Msk (0x01UL << GPIO_PORT_SET1_SETP7_Pos) /*!< GPIO_PORT SET1: SETP7 Mask */ -#define GPIO_PORT_SET1_SETP8_Pos 8 /*!< GPIO_PORT SET1: SETP8 Position */ -#define GPIO_PORT_SET1_SETP8_Msk (0x01UL << GPIO_PORT_SET1_SETP8_Pos) /*!< GPIO_PORT SET1: SETP8 Mask */ -#define GPIO_PORT_SET1_SETP9_Pos 9 /*!< GPIO_PORT SET1: SETP9 Position */ -#define GPIO_PORT_SET1_SETP9_Msk (0x01UL << GPIO_PORT_SET1_SETP9_Pos) /*!< GPIO_PORT SET1: SETP9 Mask */ -#define GPIO_PORT_SET1_SETP10_Pos 10 /*!< GPIO_PORT SET1: SETP10 Position */ -#define GPIO_PORT_SET1_SETP10_Msk (0x01UL << GPIO_PORT_SET1_SETP10_Pos) /*!< GPIO_PORT SET1: SETP10 Mask */ -#define GPIO_PORT_SET1_SETP11_Pos 11 /*!< GPIO_PORT SET1: SETP11 Position */ -#define GPIO_PORT_SET1_SETP11_Msk (0x01UL << GPIO_PORT_SET1_SETP11_Pos) /*!< GPIO_PORT SET1: SETP11 Mask */ -#define GPIO_PORT_SET1_SETP12_Pos 12 /*!< GPIO_PORT SET1: SETP12 Position */ -#define GPIO_PORT_SET1_SETP12_Msk (0x01UL << GPIO_PORT_SET1_SETP12_Pos) /*!< GPIO_PORT SET1: SETP12 Mask */ -#define GPIO_PORT_SET1_SETP13_Pos 13 /*!< GPIO_PORT SET1: SETP13 Position */ -#define GPIO_PORT_SET1_SETP13_Msk (0x01UL << GPIO_PORT_SET1_SETP13_Pos) /*!< GPIO_PORT SET1: SETP13 Mask */ -#define GPIO_PORT_SET1_SETP14_Pos 14 /*!< GPIO_PORT SET1: SETP14 Position */ -#define GPIO_PORT_SET1_SETP14_Msk (0x01UL << GPIO_PORT_SET1_SETP14_Pos) /*!< GPIO_PORT SET1: SETP14 Mask */ -#define GPIO_PORT_SET1_SETP15_Pos 15 /*!< GPIO_PORT SET1: SETP15 Position */ -#define GPIO_PORT_SET1_SETP15_Msk (0x01UL << GPIO_PORT_SET1_SETP15_Pos) /*!< GPIO_PORT SET1: SETP15 Mask */ -#define GPIO_PORT_SET1_SETP16_Pos 16 /*!< GPIO_PORT SET1: SETP16 Position */ -#define GPIO_PORT_SET1_SETP16_Msk (0x01UL << GPIO_PORT_SET1_SETP16_Pos) /*!< GPIO_PORT SET1: SETP16 Mask */ -#define GPIO_PORT_SET1_SETP17_Pos 17 /*!< GPIO_PORT SET1: SETP17 Position */ -#define GPIO_PORT_SET1_SETP17_Msk (0x01UL << GPIO_PORT_SET1_SETP17_Pos) /*!< GPIO_PORT SET1: SETP17 Mask */ -#define GPIO_PORT_SET1_SETP18_Pos 18 /*!< GPIO_PORT SET1: SETP18 Position */ -#define GPIO_PORT_SET1_SETP18_Msk (0x01UL << GPIO_PORT_SET1_SETP18_Pos) /*!< GPIO_PORT SET1: SETP18 Mask */ -#define GPIO_PORT_SET1_SETP19_Pos 19 /*!< GPIO_PORT SET1: SETP19 Position */ -#define GPIO_PORT_SET1_SETP19_Msk (0x01UL << GPIO_PORT_SET1_SETP19_Pos) /*!< GPIO_PORT SET1: SETP19 Mask */ -#define GPIO_PORT_SET1_SETP20_Pos 20 /*!< GPIO_PORT SET1: SETP20 Position */ -#define GPIO_PORT_SET1_SETP20_Msk (0x01UL << GPIO_PORT_SET1_SETP20_Pos) /*!< GPIO_PORT SET1: SETP20 Mask */ -#define GPIO_PORT_SET1_SETP21_Pos 21 /*!< GPIO_PORT SET1: SETP21 Position */ -#define GPIO_PORT_SET1_SETP21_Msk (0x01UL << GPIO_PORT_SET1_SETP21_Pos) /*!< GPIO_PORT SET1: SETP21 Mask */ -#define GPIO_PORT_SET1_SETP22_Pos 22 /*!< GPIO_PORT SET1: SETP22 Position */ -#define GPIO_PORT_SET1_SETP22_Msk (0x01UL << GPIO_PORT_SET1_SETP22_Pos) /*!< GPIO_PORT SET1: SETP22 Mask */ -#define GPIO_PORT_SET1_SETP23_Pos 23 /*!< GPIO_PORT SET1: SETP23 Position */ -#define GPIO_PORT_SET1_SETP23_Msk (0x01UL << GPIO_PORT_SET1_SETP23_Pos) /*!< GPIO_PORT SET1: SETP23 Mask */ -#define GPIO_PORT_SET1_SETP24_Pos 24 /*!< GPIO_PORT SET1: SETP24 Position */ -#define GPIO_PORT_SET1_SETP24_Msk (0x01UL << GPIO_PORT_SET1_SETP24_Pos) /*!< GPIO_PORT SET1: SETP24 Mask */ -#define GPIO_PORT_SET1_SETP25_Pos 25 /*!< GPIO_PORT SET1: SETP25 Position */ -#define GPIO_PORT_SET1_SETP25_Msk (0x01UL << GPIO_PORT_SET1_SETP25_Pos) /*!< GPIO_PORT SET1: SETP25 Mask */ -#define GPIO_PORT_SET1_SETP26_Pos 26 /*!< GPIO_PORT SET1: SETP26 Position */ -#define GPIO_PORT_SET1_SETP26_Msk (0x01UL << GPIO_PORT_SET1_SETP26_Pos) /*!< GPIO_PORT SET1: SETP26 Mask */ -#define GPIO_PORT_SET1_SETP27_Pos 27 /*!< GPIO_PORT SET1: SETP27 Position */ -#define GPIO_PORT_SET1_SETP27_Msk (0x01UL << GPIO_PORT_SET1_SETP27_Pos) /*!< GPIO_PORT SET1: SETP27 Mask */ -#define GPIO_PORT_SET1_SETP28_Pos 28 /*!< GPIO_PORT SET1: SETP28 Position */ -#define GPIO_PORT_SET1_SETP28_Msk (0x01UL << GPIO_PORT_SET1_SETP28_Pos) /*!< GPIO_PORT SET1: SETP28 Mask */ -#define GPIO_PORT_SET1_SETP29_Pos 29 /*!< GPIO_PORT SET1: SETP29 Position */ -#define GPIO_PORT_SET1_SETP29_Msk (0x01UL << GPIO_PORT_SET1_SETP29_Pos) /*!< GPIO_PORT SET1: SETP29 Mask */ -#define GPIO_PORT_SET1_SETP30_Pos 30 /*!< GPIO_PORT SET1: SETP30 Position */ -#define GPIO_PORT_SET1_SETP30_Msk (0x01UL << GPIO_PORT_SET1_SETP30_Pos) /*!< GPIO_PORT SET1: SETP30 Mask */ -#define GPIO_PORT_SET1_SETP31_Pos 31 /*!< GPIO_PORT SET1: SETP31 Position */ -#define GPIO_PORT_SET1_SETP31_Msk (0x01UL << GPIO_PORT_SET1_SETP31_Pos) /*!< GPIO_PORT SET1: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET2 ----------------------------------------- -#define GPIO_PORT_SET2_SETP0_Pos 0 /*!< GPIO_PORT SET2: SETP0 Position */ -#define GPIO_PORT_SET2_SETP0_Msk (0x01UL << GPIO_PORT_SET2_SETP0_Pos) /*!< GPIO_PORT SET2: SETP0 Mask */ -#define GPIO_PORT_SET2_SETP1_Pos 1 /*!< GPIO_PORT SET2: SETP1 Position */ -#define GPIO_PORT_SET2_SETP1_Msk (0x01UL << GPIO_PORT_SET2_SETP1_Pos) /*!< GPIO_PORT SET2: SETP1 Mask */ -#define GPIO_PORT_SET2_SETP2_Pos 2 /*!< GPIO_PORT SET2: SETP2 Position */ -#define GPIO_PORT_SET2_SETP2_Msk (0x01UL << GPIO_PORT_SET2_SETP2_Pos) /*!< GPIO_PORT SET2: SETP2 Mask */ -#define GPIO_PORT_SET2_SETP3_Pos 3 /*!< GPIO_PORT SET2: SETP3 Position */ -#define GPIO_PORT_SET2_SETP3_Msk (0x01UL << GPIO_PORT_SET2_SETP3_Pos) /*!< GPIO_PORT SET2: SETP3 Mask */ -#define GPIO_PORT_SET2_SETP4_Pos 4 /*!< GPIO_PORT SET2: SETP4 Position */ -#define GPIO_PORT_SET2_SETP4_Msk (0x01UL << GPIO_PORT_SET2_SETP4_Pos) /*!< GPIO_PORT SET2: SETP4 Mask */ -#define GPIO_PORT_SET2_SETP5_Pos 5 /*!< GPIO_PORT SET2: SETP5 Position */ -#define GPIO_PORT_SET2_SETP5_Msk (0x01UL << GPIO_PORT_SET2_SETP5_Pos) /*!< GPIO_PORT SET2: SETP5 Mask */ -#define GPIO_PORT_SET2_SETP6_Pos 6 /*!< GPIO_PORT SET2: SETP6 Position */ -#define GPIO_PORT_SET2_SETP6_Msk (0x01UL << GPIO_PORT_SET2_SETP6_Pos) /*!< GPIO_PORT SET2: SETP6 Mask */ -#define GPIO_PORT_SET2_SETP7_Pos 7 /*!< GPIO_PORT SET2: SETP7 Position */ -#define GPIO_PORT_SET2_SETP7_Msk (0x01UL << GPIO_PORT_SET2_SETP7_Pos) /*!< GPIO_PORT SET2: SETP7 Mask */ -#define GPIO_PORT_SET2_SETP8_Pos 8 /*!< GPIO_PORT SET2: SETP8 Position */ -#define GPIO_PORT_SET2_SETP8_Msk (0x01UL << GPIO_PORT_SET2_SETP8_Pos) /*!< GPIO_PORT SET2: SETP8 Mask */ -#define GPIO_PORT_SET2_SETP9_Pos 9 /*!< GPIO_PORT SET2: SETP9 Position */ -#define GPIO_PORT_SET2_SETP9_Msk (0x01UL << GPIO_PORT_SET2_SETP9_Pos) /*!< GPIO_PORT SET2: SETP9 Mask */ -#define GPIO_PORT_SET2_SETP10_Pos 10 /*!< GPIO_PORT SET2: SETP10 Position */ -#define GPIO_PORT_SET2_SETP10_Msk (0x01UL << GPIO_PORT_SET2_SETP10_Pos) /*!< GPIO_PORT SET2: SETP10 Mask */ -#define GPIO_PORT_SET2_SETP11_Pos 11 /*!< GPIO_PORT SET2: SETP11 Position */ -#define GPIO_PORT_SET2_SETP11_Msk (0x01UL << GPIO_PORT_SET2_SETP11_Pos) /*!< GPIO_PORT SET2: SETP11 Mask */ -#define GPIO_PORT_SET2_SETP12_Pos 12 /*!< GPIO_PORT SET2: SETP12 Position */ -#define GPIO_PORT_SET2_SETP12_Msk (0x01UL << GPIO_PORT_SET2_SETP12_Pos) /*!< GPIO_PORT SET2: SETP12 Mask */ -#define GPIO_PORT_SET2_SETP13_Pos 13 /*!< GPIO_PORT SET2: SETP13 Position */ -#define GPIO_PORT_SET2_SETP13_Msk (0x01UL << GPIO_PORT_SET2_SETP13_Pos) /*!< GPIO_PORT SET2: SETP13 Mask */ -#define GPIO_PORT_SET2_SETP14_Pos 14 /*!< GPIO_PORT SET2: SETP14 Position */ -#define GPIO_PORT_SET2_SETP14_Msk (0x01UL << GPIO_PORT_SET2_SETP14_Pos) /*!< GPIO_PORT SET2: SETP14 Mask */ -#define GPIO_PORT_SET2_SETP15_Pos 15 /*!< GPIO_PORT SET2: SETP15 Position */ -#define GPIO_PORT_SET2_SETP15_Msk (0x01UL << GPIO_PORT_SET2_SETP15_Pos) /*!< GPIO_PORT SET2: SETP15 Mask */ -#define GPIO_PORT_SET2_SETP16_Pos 16 /*!< GPIO_PORT SET2: SETP16 Position */ -#define GPIO_PORT_SET2_SETP16_Msk (0x01UL << GPIO_PORT_SET2_SETP16_Pos) /*!< GPIO_PORT SET2: SETP16 Mask */ -#define GPIO_PORT_SET2_SETP17_Pos 17 /*!< GPIO_PORT SET2: SETP17 Position */ -#define GPIO_PORT_SET2_SETP17_Msk (0x01UL << GPIO_PORT_SET2_SETP17_Pos) /*!< GPIO_PORT SET2: SETP17 Mask */ -#define GPIO_PORT_SET2_SETP18_Pos 18 /*!< GPIO_PORT SET2: SETP18 Position */ -#define GPIO_PORT_SET2_SETP18_Msk (0x01UL << GPIO_PORT_SET2_SETP18_Pos) /*!< GPIO_PORT SET2: SETP18 Mask */ -#define GPIO_PORT_SET2_SETP19_Pos 19 /*!< GPIO_PORT SET2: SETP19 Position */ -#define GPIO_PORT_SET2_SETP19_Msk (0x01UL << GPIO_PORT_SET2_SETP19_Pos) /*!< GPIO_PORT SET2: SETP19 Mask */ -#define GPIO_PORT_SET2_SETP20_Pos 20 /*!< GPIO_PORT SET2: SETP20 Position */ -#define GPIO_PORT_SET2_SETP20_Msk (0x01UL << GPIO_PORT_SET2_SETP20_Pos) /*!< GPIO_PORT SET2: SETP20 Mask */ -#define GPIO_PORT_SET2_SETP21_Pos 21 /*!< GPIO_PORT SET2: SETP21 Position */ -#define GPIO_PORT_SET2_SETP21_Msk (0x01UL << GPIO_PORT_SET2_SETP21_Pos) /*!< GPIO_PORT SET2: SETP21 Mask */ -#define GPIO_PORT_SET2_SETP22_Pos 22 /*!< GPIO_PORT SET2: SETP22 Position */ -#define GPIO_PORT_SET2_SETP22_Msk (0x01UL << GPIO_PORT_SET2_SETP22_Pos) /*!< GPIO_PORT SET2: SETP22 Mask */ -#define GPIO_PORT_SET2_SETP23_Pos 23 /*!< GPIO_PORT SET2: SETP23 Position */ -#define GPIO_PORT_SET2_SETP23_Msk (0x01UL << GPIO_PORT_SET2_SETP23_Pos) /*!< GPIO_PORT SET2: SETP23 Mask */ -#define GPIO_PORT_SET2_SETP24_Pos 24 /*!< GPIO_PORT SET2: SETP24 Position */ -#define GPIO_PORT_SET2_SETP24_Msk (0x01UL << GPIO_PORT_SET2_SETP24_Pos) /*!< GPIO_PORT SET2: SETP24 Mask */ -#define GPIO_PORT_SET2_SETP25_Pos 25 /*!< GPIO_PORT SET2: SETP25 Position */ -#define GPIO_PORT_SET2_SETP25_Msk (0x01UL << GPIO_PORT_SET2_SETP25_Pos) /*!< GPIO_PORT SET2: SETP25 Mask */ -#define GPIO_PORT_SET2_SETP26_Pos 26 /*!< GPIO_PORT SET2: SETP26 Position */ -#define GPIO_PORT_SET2_SETP26_Msk (0x01UL << GPIO_PORT_SET2_SETP26_Pos) /*!< GPIO_PORT SET2: SETP26 Mask */ -#define GPIO_PORT_SET2_SETP27_Pos 27 /*!< GPIO_PORT SET2: SETP27 Position */ -#define GPIO_PORT_SET2_SETP27_Msk (0x01UL << GPIO_PORT_SET2_SETP27_Pos) /*!< GPIO_PORT SET2: SETP27 Mask */ -#define GPIO_PORT_SET2_SETP28_Pos 28 /*!< GPIO_PORT SET2: SETP28 Position */ -#define GPIO_PORT_SET2_SETP28_Msk (0x01UL << GPIO_PORT_SET2_SETP28_Pos) /*!< GPIO_PORT SET2: SETP28 Mask */ -#define GPIO_PORT_SET2_SETP29_Pos 29 /*!< GPIO_PORT SET2: SETP29 Position */ -#define GPIO_PORT_SET2_SETP29_Msk (0x01UL << GPIO_PORT_SET2_SETP29_Pos) /*!< GPIO_PORT SET2: SETP29 Mask */ -#define GPIO_PORT_SET2_SETP30_Pos 30 /*!< GPIO_PORT SET2: SETP30 Position */ -#define GPIO_PORT_SET2_SETP30_Msk (0x01UL << GPIO_PORT_SET2_SETP30_Pos) /*!< GPIO_PORT SET2: SETP30 Mask */ -#define GPIO_PORT_SET2_SETP31_Pos 31 /*!< GPIO_PORT SET2: SETP31 Position */ -#define GPIO_PORT_SET2_SETP31_Msk (0x01UL << GPIO_PORT_SET2_SETP31_Pos) /*!< GPIO_PORT SET2: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET3 ----------------------------------------- -#define GPIO_PORT_SET3_SETP0_Pos 0 /*!< GPIO_PORT SET3: SETP0 Position */ -#define GPIO_PORT_SET3_SETP0_Msk (0x01UL << GPIO_PORT_SET3_SETP0_Pos) /*!< GPIO_PORT SET3: SETP0 Mask */ -#define GPIO_PORT_SET3_SETP1_Pos 1 /*!< GPIO_PORT SET3: SETP1 Position */ -#define GPIO_PORT_SET3_SETP1_Msk (0x01UL << GPIO_PORT_SET3_SETP1_Pos) /*!< GPIO_PORT SET3: SETP1 Mask */ -#define GPIO_PORT_SET3_SETP2_Pos 2 /*!< GPIO_PORT SET3: SETP2 Position */ -#define GPIO_PORT_SET3_SETP2_Msk (0x01UL << GPIO_PORT_SET3_SETP2_Pos) /*!< GPIO_PORT SET3: SETP2 Mask */ -#define GPIO_PORT_SET3_SETP3_Pos 3 /*!< GPIO_PORT SET3: SETP3 Position */ -#define GPIO_PORT_SET3_SETP3_Msk (0x01UL << GPIO_PORT_SET3_SETP3_Pos) /*!< GPIO_PORT SET3: SETP3 Mask */ -#define GPIO_PORT_SET3_SETP4_Pos 4 /*!< GPIO_PORT SET3: SETP4 Position */ -#define GPIO_PORT_SET3_SETP4_Msk (0x01UL << GPIO_PORT_SET3_SETP4_Pos) /*!< GPIO_PORT SET3: SETP4 Mask */ -#define GPIO_PORT_SET3_SETP5_Pos 5 /*!< GPIO_PORT SET3: SETP5 Position */ -#define GPIO_PORT_SET3_SETP5_Msk (0x01UL << GPIO_PORT_SET3_SETP5_Pos) /*!< GPIO_PORT SET3: SETP5 Mask */ -#define GPIO_PORT_SET3_SETP6_Pos 6 /*!< GPIO_PORT SET3: SETP6 Position */ -#define GPIO_PORT_SET3_SETP6_Msk (0x01UL << GPIO_PORT_SET3_SETP6_Pos) /*!< GPIO_PORT SET3: SETP6 Mask */ -#define GPIO_PORT_SET3_SETP7_Pos 7 /*!< GPIO_PORT SET3: SETP7 Position */ -#define GPIO_PORT_SET3_SETP7_Msk (0x01UL << GPIO_PORT_SET3_SETP7_Pos) /*!< GPIO_PORT SET3: SETP7 Mask */ -#define GPIO_PORT_SET3_SETP8_Pos 8 /*!< GPIO_PORT SET3: SETP8 Position */ -#define GPIO_PORT_SET3_SETP8_Msk (0x01UL << GPIO_PORT_SET3_SETP8_Pos) /*!< GPIO_PORT SET3: SETP8 Mask */ -#define GPIO_PORT_SET3_SETP9_Pos 9 /*!< GPIO_PORT SET3: SETP9 Position */ -#define GPIO_PORT_SET3_SETP9_Msk (0x01UL << GPIO_PORT_SET3_SETP9_Pos) /*!< GPIO_PORT SET3: SETP9 Mask */ -#define GPIO_PORT_SET3_SETP10_Pos 10 /*!< GPIO_PORT SET3: SETP10 Position */ -#define GPIO_PORT_SET3_SETP10_Msk (0x01UL << GPIO_PORT_SET3_SETP10_Pos) /*!< GPIO_PORT SET3: SETP10 Mask */ -#define GPIO_PORT_SET3_SETP11_Pos 11 /*!< GPIO_PORT SET3: SETP11 Position */ -#define GPIO_PORT_SET3_SETP11_Msk (0x01UL << GPIO_PORT_SET3_SETP11_Pos) /*!< GPIO_PORT SET3: SETP11 Mask */ -#define GPIO_PORT_SET3_SETP12_Pos 12 /*!< GPIO_PORT SET3: SETP12 Position */ -#define GPIO_PORT_SET3_SETP12_Msk (0x01UL << GPIO_PORT_SET3_SETP12_Pos) /*!< GPIO_PORT SET3: SETP12 Mask */ -#define GPIO_PORT_SET3_SETP13_Pos 13 /*!< GPIO_PORT SET3: SETP13 Position */ -#define GPIO_PORT_SET3_SETP13_Msk (0x01UL << GPIO_PORT_SET3_SETP13_Pos) /*!< GPIO_PORT SET3: SETP13 Mask */ -#define GPIO_PORT_SET3_SETP14_Pos 14 /*!< GPIO_PORT SET3: SETP14 Position */ -#define GPIO_PORT_SET3_SETP14_Msk (0x01UL << GPIO_PORT_SET3_SETP14_Pos) /*!< GPIO_PORT SET3: SETP14 Mask */ -#define GPIO_PORT_SET3_SETP15_Pos 15 /*!< GPIO_PORT SET3: SETP15 Position */ -#define GPIO_PORT_SET3_SETP15_Msk (0x01UL << GPIO_PORT_SET3_SETP15_Pos) /*!< GPIO_PORT SET3: SETP15 Mask */ -#define GPIO_PORT_SET3_SETP16_Pos 16 /*!< GPIO_PORT SET3: SETP16 Position */ -#define GPIO_PORT_SET3_SETP16_Msk (0x01UL << GPIO_PORT_SET3_SETP16_Pos) /*!< GPIO_PORT SET3: SETP16 Mask */ -#define GPIO_PORT_SET3_SETP17_Pos 17 /*!< GPIO_PORT SET3: SETP17 Position */ -#define GPIO_PORT_SET3_SETP17_Msk (0x01UL << GPIO_PORT_SET3_SETP17_Pos) /*!< GPIO_PORT SET3: SETP17 Mask */ -#define GPIO_PORT_SET3_SETP18_Pos 18 /*!< GPIO_PORT SET3: SETP18 Position */ -#define GPIO_PORT_SET3_SETP18_Msk (0x01UL << GPIO_PORT_SET3_SETP18_Pos) /*!< GPIO_PORT SET3: SETP18 Mask */ -#define GPIO_PORT_SET3_SETP19_Pos 19 /*!< GPIO_PORT SET3: SETP19 Position */ -#define GPIO_PORT_SET3_SETP19_Msk (0x01UL << GPIO_PORT_SET3_SETP19_Pos) /*!< GPIO_PORT SET3: SETP19 Mask */ -#define GPIO_PORT_SET3_SETP20_Pos 20 /*!< GPIO_PORT SET3: SETP20 Position */ -#define GPIO_PORT_SET3_SETP20_Msk (0x01UL << GPIO_PORT_SET3_SETP20_Pos) /*!< GPIO_PORT SET3: SETP20 Mask */ -#define GPIO_PORT_SET3_SETP21_Pos 21 /*!< GPIO_PORT SET3: SETP21 Position */ -#define GPIO_PORT_SET3_SETP21_Msk (0x01UL << GPIO_PORT_SET3_SETP21_Pos) /*!< GPIO_PORT SET3: SETP21 Mask */ -#define GPIO_PORT_SET3_SETP22_Pos 22 /*!< GPIO_PORT SET3: SETP22 Position */ -#define GPIO_PORT_SET3_SETP22_Msk (0x01UL << GPIO_PORT_SET3_SETP22_Pos) /*!< GPIO_PORT SET3: SETP22 Mask */ -#define GPIO_PORT_SET3_SETP23_Pos 23 /*!< GPIO_PORT SET3: SETP23 Position */ -#define GPIO_PORT_SET3_SETP23_Msk (0x01UL << GPIO_PORT_SET3_SETP23_Pos) /*!< GPIO_PORT SET3: SETP23 Mask */ -#define GPIO_PORT_SET3_SETP24_Pos 24 /*!< GPIO_PORT SET3: SETP24 Position */ -#define GPIO_PORT_SET3_SETP24_Msk (0x01UL << GPIO_PORT_SET3_SETP24_Pos) /*!< GPIO_PORT SET3: SETP24 Mask */ -#define GPIO_PORT_SET3_SETP25_Pos 25 /*!< GPIO_PORT SET3: SETP25 Position */ -#define GPIO_PORT_SET3_SETP25_Msk (0x01UL << GPIO_PORT_SET3_SETP25_Pos) /*!< GPIO_PORT SET3: SETP25 Mask */ -#define GPIO_PORT_SET3_SETP26_Pos 26 /*!< GPIO_PORT SET3: SETP26 Position */ -#define GPIO_PORT_SET3_SETP26_Msk (0x01UL << GPIO_PORT_SET3_SETP26_Pos) /*!< GPIO_PORT SET3: SETP26 Mask */ -#define GPIO_PORT_SET3_SETP27_Pos 27 /*!< GPIO_PORT SET3: SETP27 Position */ -#define GPIO_PORT_SET3_SETP27_Msk (0x01UL << GPIO_PORT_SET3_SETP27_Pos) /*!< GPIO_PORT SET3: SETP27 Mask */ -#define GPIO_PORT_SET3_SETP28_Pos 28 /*!< GPIO_PORT SET3: SETP28 Position */ -#define GPIO_PORT_SET3_SETP28_Msk (0x01UL << GPIO_PORT_SET3_SETP28_Pos) /*!< GPIO_PORT SET3: SETP28 Mask */ -#define GPIO_PORT_SET3_SETP29_Pos 29 /*!< GPIO_PORT SET3: SETP29 Position */ -#define GPIO_PORT_SET3_SETP29_Msk (0x01UL << GPIO_PORT_SET3_SETP29_Pos) /*!< GPIO_PORT SET3: SETP29 Mask */ -#define GPIO_PORT_SET3_SETP30_Pos 30 /*!< GPIO_PORT SET3: SETP30 Position */ -#define GPIO_PORT_SET3_SETP30_Msk (0x01UL << GPIO_PORT_SET3_SETP30_Pos) /*!< GPIO_PORT SET3: SETP30 Mask */ -#define GPIO_PORT_SET3_SETP31_Pos 31 /*!< GPIO_PORT SET3: SETP31 Position */ -#define GPIO_PORT_SET3_SETP31_Msk (0x01UL << GPIO_PORT_SET3_SETP31_Pos) /*!< GPIO_PORT SET3: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET4 ----------------------------------------- -#define GPIO_PORT_SET4_SETP0_Pos 0 /*!< GPIO_PORT SET4: SETP0 Position */ -#define GPIO_PORT_SET4_SETP0_Msk (0x01UL << GPIO_PORT_SET4_SETP0_Pos) /*!< GPIO_PORT SET4: SETP0 Mask */ -#define GPIO_PORT_SET4_SETP1_Pos 1 /*!< GPIO_PORT SET4: SETP1 Position */ -#define GPIO_PORT_SET4_SETP1_Msk (0x01UL << GPIO_PORT_SET4_SETP1_Pos) /*!< GPIO_PORT SET4: SETP1 Mask */ -#define GPIO_PORT_SET4_SETP2_Pos 2 /*!< GPIO_PORT SET4: SETP2 Position */ -#define GPIO_PORT_SET4_SETP2_Msk (0x01UL << GPIO_PORT_SET4_SETP2_Pos) /*!< GPIO_PORT SET4: SETP2 Mask */ -#define GPIO_PORT_SET4_SETP3_Pos 3 /*!< GPIO_PORT SET4: SETP3 Position */ -#define GPIO_PORT_SET4_SETP3_Msk (0x01UL << GPIO_PORT_SET4_SETP3_Pos) /*!< GPIO_PORT SET4: SETP3 Mask */ -#define GPIO_PORT_SET4_SETP4_Pos 4 /*!< GPIO_PORT SET4: SETP4 Position */ -#define GPIO_PORT_SET4_SETP4_Msk (0x01UL << GPIO_PORT_SET4_SETP4_Pos) /*!< GPIO_PORT SET4: SETP4 Mask */ -#define GPIO_PORT_SET4_SETP5_Pos 5 /*!< GPIO_PORT SET4: SETP5 Position */ -#define GPIO_PORT_SET4_SETP5_Msk (0x01UL << GPIO_PORT_SET4_SETP5_Pos) /*!< GPIO_PORT SET4: SETP5 Mask */ -#define GPIO_PORT_SET4_SETP6_Pos 6 /*!< GPIO_PORT SET4: SETP6 Position */ -#define GPIO_PORT_SET4_SETP6_Msk (0x01UL << GPIO_PORT_SET4_SETP6_Pos) /*!< GPIO_PORT SET4: SETP6 Mask */ -#define GPIO_PORT_SET4_SETP7_Pos 7 /*!< GPIO_PORT SET4: SETP7 Position */ -#define GPIO_PORT_SET4_SETP7_Msk (0x01UL << GPIO_PORT_SET4_SETP7_Pos) /*!< GPIO_PORT SET4: SETP7 Mask */ -#define GPIO_PORT_SET4_SETP8_Pos 8 /*!< GPIO_PORT SET4: SETP8 Position */ -#define GPIO_PORT_SET4_SETP8_Msk (0x01UL << GPIO_PORT_SET4_SETP8_Pos) /*!< GPIO_PORT SET4: SETP8 Mask */ -#define GPIO_PORT_SET4_SETP9_Pos 9 /*!< GPIO_PORT SET4: SETP9 Position */ -#define GPIO_PORT_SET4_SETP9_Msk (0x01UL << GPIO_PORT_SET4_SETP9_Pos) /*!< GPIO_PORT SET4: SETP9 Mask */ -#define GPIO_PORT_SET4_SETP10_Pos 10 /*!< GPIO_PORT SET4: SETP10 Position */ -#define GPIO_PORT_SET4_SETP10_Msk (0x01UL << GPIO_PORT_SET4_SETP10_Pos) /*!< GPIO_PORT SET4: SETP10 Mask */ -#define GPIO_PORT_SET4_SETP11_Pos 11 /*!< GPIO_PORT SET4: SETP11 Position */ -#define GPIO_PORT_SET4_SETP11_Msk (0x01UL << GPIO_PORT_SET4_SETP11_Pos) /*!< GPIO_PORT SET4: SETP11 Mask */ -#define GPIO_PORT_SET4_SETP12_Pos 12 /*!< GPIO_PORT SET4: SETP12 Position */ -#define GPIO_PORT_SET4_SETP12_Msk (0x01UL << GPIO_PORT_SET4_SETP12_Pos) /*!< GPIO_PORT SET4: SETP12 Mask */ -#define GPIO_PORT_SET4_SETP13_Pos 13 /*!< GPIO_PORT SET4: SETP13 Position */ -#define GPIO_PORT_SET4_SETP13_Msk (0x01UL << GPIO_PORT_SET4_SETP13_Pos) /*!< GPIO_PORT SET4: SETP13 Mask */ -#define GPIO_PORT_SET4_SETP14_Pos 14 /*!< GPIO_PORT SET4: SETP14 Position */ -#define GPIO_PORT_SET4_SETP14_Msk (0x01UL << GPIO_PORT_SET4_SETP14_Pos) /*!< GPIO_PORT SET4: SETP14 Mask */ -#define GPIO_PORT_SET4_SETP15_Pos 15 /*!< GPIO_PORT SET4: SETP15 Position */ -#define GPIO_PORT_SET4_SETP15_Msk (0x01UL << GPIO_PORT_SET4_SETP15_Pos) /*!< GPIO_PORT SET4: SETP15 Mask */ -#define GPIO_PORT_SET4_SETP16_Pos 16 /*!< GPIO_PORT SET4: SETP16 Position */ -#define GPIO_PORT_SET4_SETP16_Msk (0x01UL << GPIO_PORT_SET4_SETP16_Pos) /*!< GPIO_PORT SET4: SETP16 Mask */ -#define GPIO_PORT_SET4_SETP17_Pos 17 /*!< GPIO_PORT SET4: SETP17 Position */ -#define GPIO_PORT_SET4_SETP17_Msk (0x01UL << GPIO_PORT_SET4_SETP17_Pos) /*!< GPIO_PORT SET4: SETP17 Mask */ -#define GPIO_PORT_SET4_SETP18_Pos 18 /*!< GPIO_PORT SET4: SETP18 Position */ -#define GPIO_PORT_SET4_SETP18_Msk (0x01UL << GPIO_PORT_SET4_SETP18_Pos) /*!< GPIO_PORT SET4: SETP18 Mask */ -#define GPIO_PORT_SET4_SETP19_Pos 19 /*!< GPIO_PORT SET4: SETP19 Position */ -#define GPIO_PORT_SET4_SETP19_Msk (0x01UL << GPIO_PORT_SET4_SETP19_Pos) /*!< GPIO_PORT SET4: SETP19 Mask */ -#define GPIO_PORT_SET4_SETP20_Pos 20 /*!< GPIO_PORT SET4: SETP20 Position */ -#define GPIO_PORT_SET4_SETP20_Msk (0x01UL << GPIO_PORT_SET4_SETP20_Pos) /*!< GPIO_PORT SET4: SETP20 Mask */ -#define GPIO_PORT_SET4_SETP21_Pos 21 /*!< GPIO_PORT SET4: SETP21 Position */ -#define GPIO_PORT_SET4_SETP21_Msk (0x01UL << GPIO_PORT_SET4_SETP21_Pos) /*!< GPIO_PORT SET4: SETP21 Mask */ -#define GPIO_PORT_SET4_SETP22_Pos 22 /*!< GPIO_PORT SET4: SETP22 Position */ -#define GPIO_PORT_SET4_SETP22_Msk (0x01UL << GPIO_PORT_SET4_SETP22_Pos) /*!< GPIO_PORT SET4: SETP22 Mask */ -#define GPIO_PORT_SET4_SETP23_Pos 23 /*!< GPIO_PORT SET4: SETP23 Position */ -#define GPIO_PORT_SET4_SETP23_Msk (0x01UL << GPIO_PORT_SET4_SETP23_Pos) /*!< GPIO_PORT SET4: SETP23 Mask */ -#define GPIO_PORT_SET4_SETP24_Pos 24 /*!< GPIO_PORT SET4: SETP24 Position */ -#define GPIO_PORT_SET4_SETP24_Msk (0x01UL << GPIO_PORT_SET4_SETP24_Pos) /*!< GPIO_PORT SET4: SETP24 Mask */ -#define GPIO_PORT_SET4_SETP25_Pos 25 /*!< GPIO_PORT SET4: SETP25 Position */ -#define GPIO_PORT_SET4_SETP25_Msk (0x01UL << GPIO_PORT_SET4_SETP25_Pos) /*!< GPIO_PORT SET4: SETP25 Mask */ -#define GPIO_PORT_SET4_SETP26_Pos 26 /*!< GPIO_PORT SET4: SETP26 Position */ -#define GPIO_PORT_SET4_SETP26_Msk (0x01UL << GPIO_PORT_SET4_SETP26_Pos) /*!< GPIO_PORT SET4: SETP26 Mask */ -#define GPIO_PORT_SET4_SETP27_Pos 27 /*!< GPIO_PORT SET4: SETP27 Position */ -#define GPIO_PORT_SET4_SETP27_Msk (0x01UL << GPIO_PORT_SET4_SETP27_Pos) /*!< GPIO_PORT SET4: SETP27 Mask */ -#define GPIO_PORT_SET4_SETP28_Pos 28 /*!< GPIO_PORT SET4: SETP28 Position */ -#define GPIO_PORT_SET4_SETP28_Msk (0x01UL << GPIO_PORT_SET4_SETP28_Pos) /*!< GPIO_PORT SET4: SETP28 Mask */ -#define GPIO_PORT_SET4_SETP29_Pos 29 /*!< GPIO_PORT SET4: SETP29 Position */ -#define GPIO_PORT_SET4_SETP29_Msk (0x01UL << GPIO_PORT_SET4_SETP29_Pos) /*!< GPIO_PORT SET4: SETP29 Mask */ -#define GPIO_PORT_SET4_SETP30_Pos 30 /*!< GPIO_PORT SET4: SETP30 Position */ -#define GPIO_PORT_SET4_SETP30_Msk (0x01UL << GPIO_PORT_SET4_SETP30_Pos) /*!< GPIO_PORT SET4: SETP30 Mask */ -#define GPIO_PORT_SET4_SETP31_Pos 31 /*!< GPIO_PORT SET4: SETP31 Position */ -#define GPIO_PORT_SET4_SETP31_Msk (0x01UL << GPIO_PORT_SET4_SETP31_Pos) /*!< GPIO_PORT SET4: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET5 ----------------------------------------- -#define GPIO_PORT_SET5_SETP0_Pos 0 /*!< GPIO_PORT SET5: SETP0 Position */ -#define GPIO_PORT_SET5_SETP0_Msk (0x01UL << GPIO_PORT_SET5_SETP0_Pos) /*!< GPIO_PORT SET5: SETP0 Mask */ -#define GPIO_PORT_SET5_SETP1_Pos 1 /*!< GPIO_PORT SET5: SETP1 Position */ -#define GPIO_PORT_SET5_SETP1_Msk (0x01UL << GPIO_PORT_SET5_SETP1_Pos) /*!< GPIO_PORT SET5: SETP1 Mask */ -#define GPIO_PORT_SET5_SETP2_Pos 2 /*!< GPIO_PORT SET5: SETP2 Position */ -#define GPIO_PORT_SET5_SETP2_Msk (0x01UL << GPIO_PORT_SET5_SETP2_Pos) /*!< GPIO_PORT SET5: SETP2 Mask */ -#define GPIO_PORT_SET5_SETP3_Pos 3 /*!< GPIO_PORT SET5: SETP3 Position */ -#define GPIO_PORT_SET5_SETP3_Msk (0x01UL << GPIO_PORT_SET5_SETP3_Pos) /*!< GPIO_PORT SET5: SETP3 Mask */ -#define GPIO_PORT_SET5_SETP4_Pos 4 /*!< GPIO_PORT SET5: SETP4 Position */ -#define GPIO_PORT_SET5_SETP4_Msk (0x01UL << GPIO_PORT_SET5_SETP4_Pos) /*!< GPIO_PORT SET5: SETP4 Mask */ -#define GPIO_PORT_SET5_SETP5_Pos 5 /*!< GPIO_PORT SET5: SETP5 Position */ -#define GPIO_PORT_SET5_SETP5_Msk (0x01UL << GPIO_PORT_SET5_SETP5_Pos) /*!< GPIO_PORT SET5: SETP5 Mask */ -#define GPIO_PORT_SET5_SETP6_Pos 6 /*!< GPIO_PORT SET5: SETP6 Position */ -#define GPIO_PORT_SET5_SETP6_Msk (0x01UL << GPIO_PORT_SET5_SETP6_Pos) /*!< GPIO_PORT SET5: SETP6 Mask */ -#define GPIO_PORT_SET5_SETP7_Pos 7 /*!< GPIO_PORT SET5: SETP7 Position */ -#define GPIO_PORT_SET5_SETP7_Msk (0x01UL << GPIO_PORT_SET5_SETP7_Pos) /*!< GPIO_PORT SET5: SETP7 Mask */ -#define GPIO_PORT_SET5_SETP8_Pos 8 /*!< GPIO_PORT SET5: SETP8 Position */ -#define GPIO_PORT_SET5_SETP8_Msk (0x01UL << GPIO_PORT_SET5_SETP8_Pos) /*!< GPIO_PORT SET5: SETP8 Mask */ -#define GPIO_PORT_SET5_SETP9_Pos 9 /*!< GPIO_PORT SET5: SETP9 Position */ -#define GPIO_PORT_SET5_SETP9_Msk (0x01UL << GPIO_PORT_SET5_SETP9_Pos) /*!< GPIO_PORT SET5: SETP9 Mask */ -#define GPIO_PORT_SET5_SETP10_Pos 10 /*!< GPIO_PORT SET5: SETP10 Position */ -#define GPIO_PORT_SET5_SETP10_Msk (0x01UL << GPIO_PORT_SET5_SETP10_Pos) /*!< GPIO_PORT SET5: SETP10 Mask */ -#define GPIO_PORT_SET5_SETP11_Pos 11 /*!< GPIO_PORT SET5: SETP11 Position */ -#define GPIO_PORT_SET5_SETP11_Msk (0x01UL << GPIO_PORT_SET5_SETP11_Pos) /*!< GPIO_PORT SET5: SETP11 Mask */ -#define GPIO_PORT_SET5_SETP12_Pos 12 /*!< GPIO_PORT SET5: SETP12 Position */ -#define GPIO_PORT_SET5_SETP12_Msk (0x01UL << GPIO_PORT_SET5_SETP12_Pos) /*!< GPIO_PORT SET5: SETP12 Mask */ -#define GPIO_PORT_SET5_SETP13_Pos 13 /*!< GPIO_PORT SET5: SETP13 Position */ -#define GPIO_PORT_SET5_SETP13_Msk (0x01UL << GPIO_PORT_SET5_SETP13_Pos) /*!< GPIO_PORT SET5: SETP13 Mask */ -#define GPIO_PORT_SET5_SETP14_Pos 14 /*!< GPIO_PORT SET5: SETP14 Position */ -#define GPIO_PORT_SET5_SETP14_Msk (0x01UL << GPIO_PORT_SET5_SETP14_Pos) /*!< GPIO_PORT SET5: SETP14 Mask */ -#define GPIO_PORT_SET5_SETP15_Pos 15 /*!< GPIO_PORT SET5: SETP15 Position */ -#define GPIO_PORT_SET5_SETP15_Msk (0x01UL << GPIO_PORT_SET5_SETP15_Pos) /*!< GPIO_PORT SET5: SETP15 Mask */ -#define GPIO_PORT_SET5_SETP16_Pos 16 /*!< GPIO_PORT SET5: SETP16 Position */ -#define GPIO_PORT_SET5_SETP16_Msk (0x01UL << GPIO_PORT_SET5_SETP16_Pos) /*!< GPIO_PORT SET5: SETP16 Mask */ -#define GPIO_PORT_SET5_SETP17_Pos 17 /*!< GPIO_PORT SET5: SETP17 Position */ -#define GPIO_PORT_SET5_SETP17_Msk (0x01UL << GPIO_PORT_SET5_SETP17_Pos) /*!< GPIO_PORT SET5: SETP17 Mask */ -#define GPIO_PORT_SET5_SETP18_Pos 18 /*!< GPIO_PORT SET5: SETP18 Position */ -#define GPIO_PORT_SET5_SETP18_Msk (0x01UL << GPIO_PORT_SET5_SETP18_Pos) /*!< GPIO_PORT SET5: SETP18 Mask */ -#define GPIO_PORT_SET5_SETP19_Pos 19 /*!< GPIO_PORT SET5: SETP19 Position */ -#define GPIO_PORT_SET5_SETP19_Msk (0x01UL << GPIO_PORT_SET5_SETP19_Pos) /*!< GPIO_PORT SET5: SETP19 Mask */ -#define GPIO_PORT_SET5_SETP20_Pos 20 /*!< GPIO_PORT SET5: SETP20 Position */ -#define GPIO_PORT_SET5_SETP20_Msk (0x01UL << GPIO_PORT_SET5_SETP20_Pos) /*!< GPIO_PORT SET5: SETP20 Mask */ -#define GPIO_PORT_SET5_SETP21_Pos 21 /*!< GPIO_PORT SET5: SETP21 Position */ -#define GPIO_PORT_SET5_SETP21_Msk (0x01UL << GPIO_PORT_SET5_SETP21_Pos) /*!< GPIO_PORT SET5: SETP21 Mask */ -#define GPIO_PORT_SET5_SETP22_Pos 22 /*!< GPIO_PORT SET5: SETP22 Position */ -#define GPIO_PORT_SET5_SETP22_Msk (0x01UL << GPIO_PORT_SET5_SETP22_Pos) /*!< GPIO_PORT SET5: SETP22 Mask */ -#define GPIO_PORT_SET5_SETP23_Pos 23 /*!< GPIO_PORT SET5: SETP23 Position */ -#define GPIO_PORT_SET5_SETP23_Msk (0x01UL << GPIO_PORT_SET5_SETP23_Pos) /*!< GPIO_PORT SET5: SETP23 Mask */ -#define GPIO_PORT_SET5_SETP24_Pos 24 /*!< GPIO_PORT SET5: SETP24 Position */ -#define GPIO_PORT_SET5_SETP24_Msk (0x01UL << GPIO_PORT_SET5_SETP24_Pos) /*!< GPIO_PORT SET5: SETP24 Mask */ -#define GPIO_PORT_SET5_SETP25_Pos 25 /*!< GPIO_PORT SET5: SETP25 Position */ -#define GPIO_PORT_SET5_SETP25_Msk (0x01UL << GPIO_PORT_SET5_SETP25_Pos) /*!< GPIO_PORT SET5: SETP25 Mask */ -#define GPIO_PORT_SET5_SETP26_Pos 26 /*!< GPIO_PORT SET5: SETP26 Position */ -#define GPIO_PORT_SET5_SETP26_Msk (0x01UL << GPIO_PORT_SET5_SETP26_Pos) /*!< GPIO_PORT SET5: SETP26 Mask */ -#define GPIO_PORT_SET5_SETP27_Pos 27 /*!< GPIO_PORT SET5: SETP27 Position */ -#define GPIO_PORT_SET5_SETP27_Msk (0x01UL << GPIO_PORT_SET5_SETP27_Pos) /*!< GPIO_PORT SET5: SETP27 Mask */ -#define GPIO_PORT_SET5_SETP28_Pos 28 /*!< GPIO_PORT SET5: SETP28 Position */ -#define GPIO_PORT_SET5_SETP28_Msk (0x01UL << GPIO_PORT_SET5_SETP28_Pos) /*!< GPIO_PORT SET5: SETP28 Mask */ -#define GPIO_PORT_SET5_SETP29_Pos 29 /*!< GPIO_PORT SET5: SETP29 Position */ -#define GPIO_PORT_SET5_SETP29_Msk (0x01UL << GPIO_PORT_SET5_SETP29_Pos) /*!< GPIO_PORT SET5: SETP29 Mask */ -#define GPIO_PORT_SET5_SETP30_Pos 30 /*!< GPIO_PORT SET5: SETP30 Position */ -#define GPIO_PORT_SET5_SETP30_Msk (0x01UL << GPIO_PORT_SET5_SETP30_Pos) /*!< GPIO_PORT SET5: SETP30 Mask */ -#define GPIO_PORT_SET5_SETP31_Pos 31 /*!< GPIO_PORT SET5: SETP31 Position */ -#define GPIO_PORT_SET5_SETP31_Msk (0x01UL << GPIO_PORT_SET5_SETP31_Pos) /*!< GPIO_PORT SET5: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET6 ----------------------------------------- -#define GPIO_PORT_SET6_SETP0_Pos 0 /*!< GPIO_PORT SET6: SETP0 Position */ -#define GPIO_PORT_SET6_SETP0_Msk (0x01UL << GPIO_PORT_SET6_SETP0_Pos) /*!< GPIO_PORT SET6: SETP0 Mask */ -#define GPIO_PORT_SET6_SETP1_Pos 1 /*!< GPIO_PORT SET6: SETP1 Position */ -#define GPIO_PORT_SET6_SETP1_Msk (0x01UL << GPIO_PORT_SET6_SETP1_Pos) /*!< GPIO_PORT SET6: SETP1 Mask */ -#define GPIO_PORT_SET6_SETP2_Pos 2 /*!< GPIO_PORT SET6: SETP2 Position */ -#define GPIO_PORT_SET6_SETP2_Msk (0x01UL << GPIO_PORT_SET6_SETP2_Pos) /*!< GPIO_PORT SET6: SETP2 Mask */ -#define GPIO_PORT_SET6_SETP3_Pos 3 /*!< GPIO_PORT SET6: SETP3 Position */ -#define GPIO_PORT_SET6_SETP3_Msk (0x01UL << GPIO_PORT_SET6_SETP3_Pos) /*!< GPIO_PORT SET6: SETP3 Mask */ -#define GPIO_PORT_SET6_SETP4_Pos 4 /*!< GPIO_PORT SET6: SETP4 Position */ -#define GPIO_PORT_SET6_SETP4_Msk (0x01UL << GPIO_PORT_SET6_SETP4_Pos) /*!< GPIO_PORT SET6: SETP4 Mask */ -#define GPIO_PORT_SET6_SETP5_Pos 5 /*!< GPIO_PORT SET6: SETP5 Position */ -#define GPIO_PORT_SET6_SETP5_Msk (0x01UL << GPIO_PORT_SET6_SETP5_Pos) /*!< GPIO_PORT SET6: SETP5 Mask */ -#define GPIO_PORT_SET6_SETP6_Pos 6 /*!< GPIO_PORT SET6: SETP6 Position */ -#define GPIO_PORT_SET6_SETP6_Msk (0x01UL << GPIO_PORT_SET6_SETP6_Pos) /*!< GPIO_PORT SET6: SETP6 Mask */ -#define GPIO_PORT_SET6_SETP7_Pos 7 /*!< GPIO_PORT SET6: SETP7 Position */ -#define GPIO_PORT_SET6_SETP7_Msk (0x01UL << GPIO_PORT_SET6_SETP7_Pos) /*!< GPIO_PORT SET6: SETP7 Mask */ -#define GPIO_PORT_SET6_SETP8_Pos 8 /*!< GPIO_PORT SET6: SETP8 Position */ -#define GPIO_PORT_SET6_SETP8_Msk (0x01UL << GPIO_PORT_SET6_SETP8_Pos) /*!< GPIO_PORT SET6: SETP8 Mask */ -#define GPIO_PORT_SET6_SETP9_Pos 9 /*!< GPIO_PORT SET6: SETP9 Position */ -#define GPIO_PORT_SET6_SETP9_Msk (0x01UL << GPIO_PORT_SET6_SETP9_Pos) /*!< GPIO_PORT SET6: SETP9 Mask */ -#define GPIO_PORT_SET6_SETP10_Pos 10 /*!< GPIO_PORT SET6: SETP10 Position */ -#define GPIO_PORT_SET6_SETP10_Msk (0x01UL << GPIO_PORT_SET6_SETP10_Pos) /*!< GPIO_PORT SET6: SETP10 Mask */ -#define GPIO_PORT_SET6_SETP11_Pos 11 /*!< GPIO_PORT SET6: SETP11 Position */ -#define GPIO_PORT_SET6_SETP11_Msk (0x01UL << GPIO_PORT_SET6_SETP11_Pos) /*!< GPIO_PORT SET6: SETP11 Mask */ -#define GPIO_PORT_SET6_SETP12_Pos 12 /*!< GPIO_PORT SET6: SETP12 Position */ -#define GPIO_PORT_SET6_SETP12_Msk (0x01UL << GPIO_PORT_SET6_SETP12_Pos) /*!< GPIO_PORT SET6: SETP12 Mask */ -#define GPIO_PORT_SET6_SETP13_Pos 13 /*!< GPIO_PORT SET6: SETP13 Position */ -#define GPIO_PORT_SET6_SETP13_Msk (0x01UL << GPIO_PORT_SET6_SETP13_Pos) /*!< GPIO_PORT SET6: SETP13 Mask */ -#define GPIO_PORT_SET6_SETP14_Pos 14 /*!< GPIO_PORT SET6: SETP14 Position */ -#define GPIO_PORT_SET6_SETP14_Msk (0x01UL << GPIO_PORT_SET6_SETP14_Pos) /*!< GPIO_PORT SET6: SETP14 Mask */ -#define GPIO_PORT_SET6_SETP15_Pos 15 /*!< GPIO_PORT SET6: SETP15 Position */ -#define GPIO_PORT_SET6_SETP15_Msk (0x01UL << GPIO_PORT_SET6_SETP15_Pos) /*!< GPIO_PORT SET6: SETP15 Mask */ -#define GPIO_PORT_SET6_SETP16_Pos 16 /*!< GPIO_PORT SET6: SETP16 Position */ -#define GPIO_PORT_SET6_SETP16_Msk (0x01UL << GPIO_PORT_SET6_SETP16_Pos) /*!< GPIO_PORT SET6: SETP16 Mask */ -#define GPIO_PORT_SET6_SETP17_Pos 17 /*!< GPIO_PORT SET6: SETP17 Position */ -#define GPIO_PORT_SET6_SETP17_Msk (0x01UL << GPIO_PORT_SET6_SETP17_Pos) /*!< GPIO_PORT SET6: SETP17 Mask */ -#define GPIO_PORT_SET6_SETP18_Pos 18 /*!< GPIO_PORT SET6: SETP18 Position */ -#define GPIO_PORT_SET6_SETP18_Msk (0x01UL << GPIO_PORT_SET6_SETP18_Pos) /*!< GPIO_PORT SET6: SETP18 Mask */ -#define GPIO_PORT_SET6_SETP19_Pos 19 /*!< GPIO_PORT SET6: SETP19 Position */ -#define GPIO_PORT_SET6_SETP19_Msk (0x01UL << GPIO_PORT_SET6_SETP19_Pos) /*!< GPIO_PORT SET6: SETP19 Mask */ -#define GPIO_PORT_SET6_SETP20_Pos 20 /*!< GPIO_PORT SET6: SETP20 Position */ -#define GPIO_PORT_SET6_SETP20_Msk (0x01UL << GPIO_PORT_SET6_SETP20_Pos) /*!< GPIO_PORT SET6: SETP20 Mask */ -#define GPIO_PORT_SET6_SETP21_Pos 21 /*!< GPIO_PORT SET6: SETP21 Position */ -#define GPIO_PORT_SET6_SETP21_Msk (0x01UL << GPIO_PORT_SET6_SETP21_Pos) /*!< GPIO_PORT SET6: SETP21 Mask */ -#define GPIO_PORT_SET6_SETP22_Pos 22 /*!< GPIO_PORT SET6: SETP22 Position */ -#define GPIO_PORT_SET6_SETP22_Msk (0x01UL << GPIO_PORT_SET6_SETP22_Pos) /*!< GPIO_PORT SET6: SETP22 Mask */ -#define GPIO_PORT_SET6_SETP23_Pos 23 /*!< GPIO_PORT SET6: SETP23 Position */ -#define GPIO_PORT_SET6_SETP23_Msk (0x01UL << GPIO_PORT_SET6_SETP23_Pos) /*!< GPIO_PORT SET6: SETP23 Mask */ -#define GPIO_PORT_SET6_SETP24_Pos 24 /*!< GPIO_PORT SET6: SETP24 Position */ -#define GPIO_PORT_SET6_SETP24_Msk (0x01UL << GPIO_PORT_SET6_SETP24_Pos) /*!< GPIO_PORT SET6: SETP24 Mask */ -#define GPIO_PORT_SET6_SETP25_Pos 25 /*!< GPIO_PORT SET6: SETP25 Position */ -#define GPIO_PORT_SET6_SETP25_Msk (0x01UL << GPIO_PORT_SET6_SETP25_Pos) /*!< GPIO_PORT SET6: SETP25 Mask */ -#define GPIO_PORT_SET6_SETP26_Pos 26 /*!< GPIO_PORT SET6: SETP26 Position */ -#define GPIO_PORT_SET6_SETP26_Msk (0x01UL << GPIO_PORT_SET6_SETP26_Pos) /*!< GPIO_PORT SET6: SETP26 Mask */ -#define GPIO_PORT_SET6_SETP27_Pos 27 /*!< GPIO_PORT SET6: SETP27 Position */ -#define GPIO_PORT_SET6_SETP27_Msk (0x01UL << GPIO_PORT_SET6_SETP27_Pos) /*!< GPIO_PORT SET6: SETP27 Mask */ -#define GPIO_PORT_SET6_SETP28_Pos 28 /*!< GPIO_PORT SET6: SETP28 Position */ -#define GPIO_PORT_SET6_SETP28_Msk (0x01UL << GPIO_PORT_SET6_SETP28_Pos) /*!< GPIO_PORT SET6: SETP28 Mask */ -#define GPIO_PORT_SET6_SETP29_Pos 29 /*!< GPIO_PORT SET6: SETP29 Position */ -#define GPIO_PORT_SET6_SETP29_Msk (0x01UL << GPIO_PORT_SET6_SETP29_Pos) /*!< GPIO_PORT SET6: SETP29 Mask */ -#define GPIO_PORT_SET6_SETP30_Pos 30 /*!< GPIO_PORT SET6: SETP30 Position */ -#define GPIO_PORT_SET6_SETP30_Msk (0x01UL << GPIO_PORT_SET6_SETP30_Pos) /*!< GPIO_PORT SET6: SETP30 Mask */ -#define GPIO_PORT_SET6_SETP31_Pos 31 /*!< GPIO_PORT SET6: SETP31 Position */ -#define GPIO_PORT_SET6_SETP31_Msk (0x01UL << GPIO_PORT_SET6_SETP31_Pos) /*!< GPIO_PORT SET6: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET7 ----------------------------------------- -#define GPIO_PORT_SET7_SETP0_Pos 0 /*!< GPIO_PORT SET7: SETP0 Position */ -#define GPIO_PORT_SET7_SETP0_Msk (0x01UL << GPIO_PORT_SET7_SETP0_Pos) /*!< GPIO_PORT SET7: SETP0 Mask */ -#define GPIO_PORT_SET7_SETP1_Pos 1 /*!< GPIO_PORT SET7: SETP1 Position */ -#define GPIO_PORT_SET7_SETP1_Msk (0x01UL << GPIO_PORT_SET7_SETP1_Pos) /*!< GPIO_PORT SET7: SETP1 Mask */ -#define GPIO_PORT_SET7_SETP2_Pos 2 /*!< GPIO_PORT SET7: SETP2 Position */ -#define GPIO_PORT_SET7_SETP2_Msk (0x01UL << GPIO_PORT_SET7_SETP2_Pos) /*!< GPIO_PORT SET7: SETP2 Mask */ -#define GPIO_PORT_SET7_SETP3_Pos 3 /*!< GPIO_PORT SET7: SETP3 Position */ -#define GPIO_PORT_SET7_SETP3_Msk (0x01UL << GPIO_PORT_SET7_SETP3_Pos) /*!< GPIO_PORT SET7: SETP3 Mask */ -#define GPIO_PORT_SET7_SETP4_Pos 4 /*!< GPIO_PORT SET7: SETP4 Position */ -#define GPIO_PORT_SET7_SETP4_Msk (0x01UL << GPIO_PORT_SET7_SETP4_Pos) /*!< GPIO_PORT SET7: SETP4 Mask */ -#define GPIO_PORT_SET7_SETP5_Pos 5 /*!< GPIO_PORT SET7: SETP5 Position */ -#define GPIO_PORT_SET7_SETP5_Msk (0x01UL << GPIO_PORT_SET7_SETP5_Pos) /*!< GPIO_PORT SET7: SETP5 Mask */ -#define GPIO_PORT_SET7_SETP6_Pos 6 /*!< GPIO_PORT SET7: SETP6 Position */ -#define GPIO_PORT_SET7_SETP6_Msk (0x01UL << GPIO_PORT_SET7_SETP6_Pos) /*!< GPIO_PORT SET7: SETP6 Mask */ -#define GPIO_PORT_SET7_SETP7_Pos 7 /*!< GPIO_PORT SET7: SETP7 Position */ -#define GPIO_PORT_SET7_SETP7_Msk (0x01UL << GPIO_PORT_SET7_SETP7_Pos) /*!< GPIO_PORT SET7: SETP7 Mask */ -#define GPIO_PORT_SET7_SETP8_Pos 8 /*!< GPIO_PORT SET7: SETP8 Position */ -#define GPIO_PORT_SET7_SETP8_Msk (0x01UL << GPIO_PORT_SET7_SETP8_Pos) /*!< GPIO_PORT SET7: SETP8 Mask */ -#define GPIO_PORT_SET7_SETP9_Pos 9 /*!< GPIO_PORT SET7: SETP9 Position */ -#define GPIO_PORT_SET7_SETP9_Msk (0x01UL << GPIO_PORT_SET7_SETP9_Pos) /*!< GPIO_PORT SET7: SETP9 Mask */ -#define GPIO_PORT_SET7_SETP10_Pos 10 /*!< GPIO_PORT SET7: SETP10 Position */ -#define GPIO_PORT_SET7_SETP10_Msk (0x01UL << GPIO_PORT_SET7_SETP10_Pos) /*!< GPIO_PORT SET7: SETP10 Mask */ -#define GPIO_PORT_SET7_SETP11_Pos 11 /*!< GPIO_PORT SET7: SETP11 Position */ -#define GPIO_PORT_SET7_SETP11_Msk (0x01UL << GPIO_PORT_SET7_SETP11_Pos) /*!< GPIO_PORT SET7: SETP11 Mask */ -#define GPIO_PORT_SET7_SETP12_Pos 12 /*!< GPIO_PORT SET7: SETP12 Position */ -#define GPIO_PORT_SET7_SETP12_Msk (0x01UL << GPIO_PORT_SET7_SETP12_Pos) /*!< GPIO_PORT SET7: SETP12 Mask */ -#define GPIO_PORT_SET7_SETP13_Pos 13 /*!< GPIO_PORT SET7: SETP13 Position */ -#define GPIO_PORT_SET7_SETP13_Msk (0x01UL << GPIO_PORT_SET7_SETP13_Pos) /*!< GPIO_PORT SET7: SETP13 Mask */ -#define GPIO_PORT_SET7_SETP14_Pos 14 /*!< GPIO_PORT SET7: SETP14 Position */ -#define GPIO_PORT_SET7_SETP14_Msk (0x01UL << GPIO_PORT_SET7_SETP14_Pos) /*!< GPIO_PORT SET7: SETP14 Mask */ -#define GPIO_PORT_SET7_SETP15_Pos 15 /*!< GPIO_PORT SET7: SETP15 Position */ -#define GPIO_PORT_SET7_SETP15_Msk (0x01UL << GPIO_PORT_SET7_SETP15_Pos) /*!< GPIO_PORT SET7: SETP15 Mask */ -#define GPIO_PORT_SET7_SETP16_Pos 16 /*!< GPIO_PORT SET7: SETP16 Position */ -#define GPIO_PORT_SET7_SETP16_Msk (0x01UL << GPIO_PORT_SET7_SETP16_Pos) /*!< GPIO_PORT SET7: SETP16 Mask */ -#define GPIO_PORT_SET7_SETP17_Pos 17 /*!< GPIO_PORT SET7: SETP17 Position */ -#define GPIO_PORT_SET7_SETP17_Msk (0x01UL << GPIO_PORT_SET7_SETP17_Pos) /*!< GPIO_PORT SET7: SETP17 Mask */ -#define GPIO_PORT_SET7_SETP18_Pos 18 /*!< GPIO_PORT SET7: SETP18 Position */ -#define GPIO_PORT_SET7_SETP18_Msk (0x01UL << GPIO_PORT_SET7_SETP18_Pos) /*!< GPIO_PORT SET7: SETP18 Mask */ -#define GPIO_PORT_SET7_SETP19_Pos 19 /*!< GPIO_PORT SET7: SETP19 Position */ -#define GPIO_PORT_SET7_SETP19_Msk (0x01UL << GPIO_PORT_SET7_SETP19_Pos) /*!< GPIO_PORT SET7: SETP19 Mask */ -#define GPIO_PORT_SET7_SETP20_Pos 20 /*!< GPIO_PORT SET7: SETP20 Position */ -#define GPIO_PORT_SET7_SETP20_Msk (0x01UL << GPIO_PORT_SET7_SETP20_Pos) /*!< GPIO_PORT SET7: SETP20 Mask */ -#define GPIO_PORT_SET7_SETP21_Pos 21 /*!< GPIO_PORT SET7: SETP21 Position */ -#define GPIO_PORT_SET7_SETP21_Msk (0x01UL << GPIO_PORT_SET7_SETP21_Pos) /*!< GPIO_PORT SET7: SETP21 Mask */ -#define GPIO_PORT_SET7_SETP22_Pos 22 /*!< GPIO_PORT SET7: SETP22 Position */ -#define GPIO_PORT_SET7_SETP22_Msk (0x01UL << GPIO_PORT_SET7_SETP22_Pos) /*!< GPIO_PORT SET7: SETP22 Mask */ -#define GPIO_PORT_SET7_SETP23_Pos 23 /*!< GPIO_PORT SET7: SETP23 Position */ -#define GPIO_PORT_SET7_SETP23_Msk (0x01UL << GPIO_PORT_SET7_SETP23_Pos) /*!< GPIO_PORT SET7: SETP23 Mask */ -#define GPIO_PORT_SET7_SETP24_Pos 24 /*!< GPIO_PORT SET7: SETP24 Position */ -#define GPIO_PORT_SET7_SETP24_Msk (0x01UL << GPIO_PORT_SET7_SETP24_Pos) /*!< GPIO_PORT SET7: SETP24 Mask */ -#define GPIO_PORT_SET7_SETP25_Pos 25 /*!< GPIO_PORT SET7: SETP25 Position */ -#define GPIO_PORT_SET7_SETP25_Msk (0x01UL << GPIO_PORT_SET7_SETP25_Pos) /*!< GPIO_PORT SET7: SETP25 Mask */ -#define GPIO_PORT_SET7_SETP26_Pos 26 /*!< GPIO_PORT SET7: SETP26 Position */ -#define GPIO_PORT_SET7_SETP26_Msk (0x01UL << GPIO_PORT_SET7_SETP26_Pos) /*!< GPIO_PORT SET7: SETP26 Mask */ -#define GPIO_PORT_SET7_SETP27_Pos 27 /*!< GPIO_PORT SET7: SETP27 Position */ -#define GPIO_PORT_SET7_SETP27_Msk (0x01UL << GPIO_PORT_SET7_SETP27_Pos) /*!< GPIO_PORT SET7: SETP27 Mask */ -#define GPIO_PORT_SET7_SETP28_Pos 28 /*!< GPIO_PORT SET7: SETP28 Position */ -#define GPIO_PORT_SET7_SETP28_Msk (0x01UL << GPIO_PORT_SET7_SETP28_Pos) /*!< GPIO_PORT SET7: SETP28 Mask */ -#define GPIO_PORT_SET7_SETP29_Pos 29 /*!< GPIO_PORT SET7: SETP29 Position */ -#define GPIO_PORT_SET7_SETP29_Msk (0x01UL << GPIO_PORT_SET7_SETP29_Pos) /*!< GPIO_PORT SET7: SETP29 Mask */ -#define GPIO_PORT_SET7_SETP30_Pos 30 /*!< GPIO_PORT SET7: SETP30 Position */ -#define GPIO_PORT_SET7_SETP30_Msk (0x01UL << GPIO_PORT_SET7_SETP30_Pos) /*!< GPIO_PORT SET7: SETP30 Mask */ -#define GPIO_PORT_SET7_SETP31_Pos 31 /*!< GPIO_PORT SET7: SETP31 Position */ -#define GPIO_PORT_SET7_SETP31_Msk (0x01UL << GPIO_PORT_SET7_SETP31_Pos) /*!< GPIO_PORT SET7: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_CLR0 ----------------------------------------- -#define GPIO_PORT_CLR0_CLRP00_Pos 0 /*!< GPIO_PORT CLR0: CLRP00 Position */ -#define GPIO_PORT_CLR0_CLRP00_Msk (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos) /*!< GPIO_PORT CLR0: CLRP00 Mask */ -#define GPIO_PORT_CLR0_CLRP01_Pos 1 /*!< GPIO_PORT CLR0: CLRP01 Position */ -#define GPIO_PORT_CLR0_CLRP01_Msk (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos) /*!< GPIO_PORT CLR0: CLRP01 Mask */ -#define GPIO_PORT_CLR0_CLRP02_Pos 2 /*!< GPIO_PORT CLR0: CLRP02 Position */ -#define GPIO_PORT_CLR0_CLRP02_Msk (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos) /*!< GPIO_PORT CLR0: CLRP02 Mask */ -#define GPIO_PORT_CLR0_CLRP03_Pos 3 /*!< GPIO_PORT CLR0: CLRP03 Position */ -#define GPIO_PORT_CLR0_CLRP03_Msk (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos) /*!< GPIO_PORT CLR0: CLRP03 Mask */ -#define GPIO_PORT_CLR0_CLRP04_Pos 4 /*!< GPIO_PORT CLR0: CLRP04 Position */ -#define GPIO_PORT_CLR0_CLRP04_Msk (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos) /*!< GPIO_PORT CLR0: CLRP04 Mask */ -#define GPIO_PORT_CLR0_CLRP05_Pos 5 /*!< GPIO_PORT CLR0: CLRP05 Position */ -#define GPIO_PORT_CLR0_CLRP05_Msk (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos) /*!< GPIO_PORT CLR0: CLRP05 Mask */ -#define GPIO_PORT_CLR0_CLRP06_Pos 6 /*!< GPIO_PORT CLR0: CLRP06 Position */ -#define GPIO_PORT_CLR0_CLRP06_Msk (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos) /*!< GPIO_PORT CLR0: CLRP06 Mask */ -#define GPIO_PORT_CLR0_CLRP07_Pos 7 /*!< GPIO_PORT CLR0: CLRP07 Position */ -#define GPIO_PORT_CLR0_CLRP07_Msk (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos) /*!< GPIO_PORT CLR0: CLRP07 Mask */ -#define GPIO_PORT_CLR0_CLRP08_Pos 8 /*!< GPIO_PORT CLR0: CLRP08 Position */ -#define GPIO_PORT_CLR0_CLRP08_Msk (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos) /*!< GPIO_PORT CLR0: CLRP08 Mask */ -#define GPIO_PORT_CLR0_CLRP09_Pos 9 /*!< GPIO_PORT CLR0: CLRP09 Position */ -#define GPIO_PORT_CLR0_CLRP09_Msk (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos) /*!< GPIO_PORT CLR0: CLRP09 Mask */ -#define GPIO_PORT_CLR0_CLRP010_Pos 10 /*!< GPIO_PORT CLR0: CLRP010 Position */ -#define GPIO_PORT_CLR0_CLRP010_Msk (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos) /*!< GPIO_PORT CLR0: CLRP010 Mask */ -#define GPIO_PORT_CLR0_CLRP011_Pos 11 /*!< GPIO_PORT CLR0: CLRP011 Position */ -#define GPIO_PORT_CLR0_CLRP011_Msk (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos) /*!< GPIO_PORT CLR0: CLRP011 Mask */ -#define GPIO_PORT_CLR0_CLRP012_Pos 12 /*!< GPIO_PORT CLR0: CLRP012 Position */ -#define GPIO_PORT_CLR0_CLRP012_Msk (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos) /*!< GPIO_PORT CLR0: CLRP012 Mask */ -#define GPIO_PORT_CLR0_CLRP013_Pos 13 /*!< GPIO_PORT CLR0: CLRP013 Position */ -#define GPIO_PORT_CLR0_CLRP013_Msk (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos) /*!< GPIO_PORT CLR0: CLRP013 Mask */ -#define GPIO_PORT_CLR0_CLRP014_Pos 14 /*!< GPIO_PORT CLR0: CLRP014 Position */ -#define GPIO_PORT_CLR0_CLRP014_Msk (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos) /*!< GPIO_PORT CLR0: CLRP014 Mask */ -#define GPIO_PORT_CLR0_CLRP015_Pos 15 /*!< GPIO_PORT CLR0: CLRP015 Position */ -#define GPIO_PORT_CLR0_CLRP015_Msk (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos) /*!< GPIO_PORT CLR0: CLRP015 Mask */ -#define GPIO_PORT_CLR0_CLRP016_Pos 16 /*!< GPIO_PORT CLR0: CLRP016 Position */ -#define GPIO_PORT_CLR0_CLRP016_Msk (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos) /*!< GPIO_PORT CLR0: CLRP016 Mask */ -#define GPIO_PORT_CLR0_CLRP017_Pos 17 /*!< GPIO_PORT CLR0: CLRP017 Position */ -#define GPIO_PORT_CLR0_CLRP017_Msk (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos) /*!< GPIO_PORT CLR0: CLRP017 Mask */ -#define GPIO_PORT_CLR0_CLRP018_Pos 18 /*!< GPIO_PORT CLR0: CLRP018 Position */ -#define GPIO_PORT_CLR0_CLRP018_Msk (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos) /*!< GPIO_PORT CLR0: CLRP018 Mask */ -#define GPIO_PORT_CLR0_CLRP019_Pos 19 /*!< GPIO_PORT CLR0: CLRP019 Position */ -#define GPIO_PORT_CLR0_CLRP019_Msk (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos) /*!< GPIO_PORT CLR0: CLRP019 Mask */ -#define GPIO_PORT_CLR0_CLRP020_Pos 20 /*!< GPIO_PORT CLR0: CLRP020 Position */ -#define GPIO_PORT_CLR0_CLRP020_Msk (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos) /*!< GPIO_PORT CLR0: CLRP020 Mask */ -#define GPIO_PORT_CLR0_CLRP021_Pos 21 /*!< GPIO_PORT CLR0: CLRP021 Position */ -#define GPIO_PORT_CLR0_CLRP021_Msk (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos) /*!< GPIO_PORT CLR0: CLRP021 Mask */ -#define GPIO_PORT_CLR0_CLRP022_Pos 22 /*!< GPIO_PORT CLR0: CLRP022 Position */ -#define GPIO_PORT_CLR0_CLRP022_Msk (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos) /*!< GPIO_PORT CLR0: CLRP022 Mask */ -#define GPIO_PORT_CLR0_CLRP023_Pos 23 /*!< GPIO_PORT CLR0: CLRP023 Position */ -#define GPIO_PORT_CLR0_CLRP023_Msk (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos) /*!< GPIO_PORT CLR0: CLRP023 Mask */ -#define GPIO_PORT_CLR0_CLRP024_Pos 24 /*!< GPIO_PORT CLR0: CLRP024 Position */ -#define GPIO_PORT_CLR0_CLRP024_Msk (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos) /*!< GPIO_PORT CLR0: CLRP024 Mask */ -#define GPIO_PORT_CLR0_CLRP025_Pos 25 /*!< GPIO_PORT CLR0: CLRP025 Position */ -#define GPIO_PORT_CLR0_CLRP025_Msk (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos) /*!< GPIO_PORT CLR0: CLRP025 Mask */ -#define GPIO_PORT_CLR0_CLRP026_Pos 26 /*!< GPIO_PORT CLR0: CLRP026 Position */ -#define GPIO_PORT_CLR0_CLRP026_Msk (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos) /*!< GPIO_PORT CLR0: CLRP026 Mask */ -#define GPIO_PORT_CLR0_CLRP027_Pos 27 /*!< GPIO_PORT CLR0: CLRP027 Position */ -#define GPIO_PORT_CLR0_CLRP027_Msk (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos) /*!< GPIO_PORT CLR0: CLRP027 Mask */ -#define GPIO_PORT_CLR0_CLRP028_Pos 28 /*!< GPIO_PORT CLR0: CLRP028 Position */ -#define GPIO_PORT_CLR0_CLRP028_Msk (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos) /*!< GPIO_PORT CLR0: CLRP028 Mask */ -#define GPIO_PORT_CLR0_CLRP029_Pos 29 /*!< GPIO_PORT CLR0: CLRP029 Position */ -#define GPIO_PORT_CLR0_CLRP029_Msk (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos) /*!< GPIO_PORT CLR0: CLRP029 Mask */ -#define GPIO_PORT_CLR0_CLRP030_Pos 30 /*!< GPIO_PORT CLR0: CLRP030 Position */ -#define GPIO_PORT_CLR0_CLRP030_Msk (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos) /*!< GPIO_PORT CLR0: CLRP030 Mask */ -#define GPIO_PORT_CLR0_CLRP031_Pos 31 /*!< GPIO_PORT CLR0: CLRP031 Position */ -#define GPIO_PORT_CLR0_CLRP031_Msk (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos) /*!< GPIO_PORT CLR0: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR1 ----------------------------------------- -#define GPIO_PORT_CLR1_CLRP00_Pos 0 /*!< GPIO_PORT CLR1: CLRP00 Position */ -#define GPIO_PORT_CLR1_CLRP00_Msk (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos) /*!< GPIO_PORT CLR1: CLRP00 Mask */ -#define GPIO_PORT_CLR1_CLRP01_Pos 1 /*!< GPIO_PORT CLR1: CLRP01 Position */ -#define GPIO_PORT_CLR1_CLRP01_Msk (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos) /*!< GPIO_PORT CLR1: CLRP01 Mask */ -#define GPIO_PORT_CLR1_CLRP02_Pos 2 /*!< GPIO_PORT CLR1: CLRP02 Position */ -#define GPIO_PORT_CLR1_CLRP02_Msk (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos) /*!< GPIO_PORT CLR1: CLRP02 Mask */ -#define GPIO_PORT_CLR1_CLRP03_Pos 3 /*!< GPIO_PORT CLR1: CLRP03 Position */ -#define GPIO_PORT_CLR1_CLRP03_Msk (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos) /*!< GPIO_PORT CLR1: CLRP03 Mask */ -#define GPIO_PORT_CLR1_CLRP04_Pos 4 /*!< GPIO_PORT CLR1: CLRP04 Position */ -#define GPIO_PORT_CLR1_CLRP04_Msk (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos) /*!< GPIO_PORT CLR1: CLRP04 Mask */ -#define GPIO_PORT_CLR1_CLRP05_Pos 5 /*!< GPIO_PORT CLR1: CLRP05 Position */ -#define GPIO_PORT_CLR1_CLRP05_Msk (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos) /*!< GPIO_PORT CLR1: CLRP05 Mask */ -#define GPIO_PORT_CLR1_CLRP06_Pos 6 /*!< GPIO_PORT CLR1: CLRP06 Position */ -#define GPIO_PORT_CLR1_CLRP06_Msk (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos) /*!< GPIO_PORT CLR1: CLRP06 Mask */ -#define GPIO_PORT_CLR1_CLRP07_Pos 7 /*!< GPIO_PORT CLR1: CLRP07 Position */ -#define GPIO_PORT_CLR1_CLRP07_Msk (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos) /*!< GPIO_PORT CLR1: CLRP07 Mask */ -#define GPIO_PORT_CLR1_CLRP08_Pos 8 /*!< GPIO_PORT CLR1: CLRP08 Position */ -#define GPIO_PORT_CLR1_CLRP08_Msk (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos) /*!< GPIO_PORT CLR1: CLRP08 Mask */ -#define GPIO_PORT_CLR1_CLRP09_Pos 9 /*!< GPIO_PORT CLR1: CLRP09 Position */ -#define GPIO_PORT_CLR1_CLRP09_Msk (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos) /*!< GPIO_PORT CLR1: CLRP09 Mask */ -#define GPIO_PORT_CLR1_CLRP010_Pos 10 /*!< GPIO_PORT CLR1: CLRP010 Position */ -#define GPIO_PORT_CLR1_CLRP010_Msk (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos) /*!< GPIO_PORT CLR1: CLRP010 Mask */ -#define GPIO_PORT_CLR1_CLRP011_Pos 11 /*!< GPIO_PORT CLR1: CLRP011 Position */ -#define GPIO_PORT_CLR1_CLRP011_Msk (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos) /*!< GPIO_PORT CLR1: CLRP011 Mask */ -#define GPIO_PORT_CLR1_CLRP012_Pos 12 /*!< GPIO_PORT CLR1: CLRP012 Position */ -#define GPIO_PORT_CLR1_CLRP012_Msk (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos) /*!< GPIO_PORT CLR1: CLRP012 Mask */ -#define GPIO_PORT_CLR1_CLRP013_Pos 13 /*!< GPIO_PORT CLR1: CLRP013 Position */ -#define GPIO_PORT_CLR1_CLRP013_Msk (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos) /*!< GPIO_PORT CLR1: CLRP013 Mask */ -#define GPIO_PORT_CLR1_CLRP014_Pos 14 /*!< GPIO_PORT CLR1: CLRP014 Position */ -#define GPIO_PORT_CLR1_CLRP014_Msk (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos) /*!< GPIO_PORT CLR1: CLRP014 Mask */ -#define GPIO_PORT_CLR1_CLRP015_Pos 15 /*!< GPIO_PORT CLR1: CLRP015 Position */ -#define GPIO_PORT_CLR1_CLRP015_Msk (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos) /*!< GPIO_PORT CLR1: CLRP015 Mask */ -#define GPIO_PORT_CLR1_CLRP016_Pos 16 /*!< GPIO_PORT CLR1: CLRP016 Position */ -#define GPIO_PORT_CLR1_CLRP016_Msk (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos) /*!< GPIO_PORT CLR1: CLRP016 Mask */ -#define GPIO_PORT_CLR1_CLRP017_Pos 17 /*!< GPIO_PORT CLR1: CLRP017 Position */ -#define GPIO_PORT_CLR1_CLRP017_Msk (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos) /*!< GPIO_PORT CLR1: CLRP017 Mask */ -#define GPIO_PORT_CLR1_CLRP018_Pos 18 /*!< GPIO_PORT CLR1: CLRP018 Position */ -#define GPIO_PORT_CLR1_CLRP018_Msk (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos) /*!< GPIO_PORT CLR1: CLRP018 Mask */ -#define GPIO_PORT_CLR1_CLRP019_Pos 19 /*!< GPIO_PORT CLR1: CLRP019 Position */ -#define GPIO_PORT_CLR1_CLRP019_Msk (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos) /*!< GPIO_PORT CLR1: CLRP019 Mask */ -#define GPIO_PORT_CLR1_CLRP020_Pos 20 /*!< GPIO_PORT CLR1: CLRP020 Position */ -#define GPIO_PORT_CLR1_CLRP020_Msk (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos) /*!< GPIO_PORT CLR1: CLRP020 Mask */ -#define GPIO_PORT_CLR1_CLRP021_Pos 21 /*!< GPIO_PORT CLR1: CLRP021 Position */ -#define GPIO_PORT_CLR1_CLRP021_Msk (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos) /*!< GPIO_PORT CLR1: CLRP021 Mask */ -#define GPIO_PORT_CLR1_CLRP022_Pos 22 /*!< GPIO_PORT CLR1: CLRP022 Position */ -#define GPIO_PORT_CLR1_CLRP022_Msk (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos) /*!< GPIO_PORT CLR1: CLRP022 Mask */ -#define GPIO_PORT_CLR1_CLRP023_Pos 23 /*!< GPIO_PORT CLR1: CLRP023 Position */ -#define GPIO_PORT_CLR1_CLRP023_Msk (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos) /*!< GPIO_PORT CLR1: CLRP023 Mask */ -#define GPIO_PORT_CLR1_CLRP024_Pos 24 /*!< GPIO_PORT CLR1: CLRP024 Position */ -#define GPIO_PORT_CLR1_CLRP024_Msk (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos) /*!< GPIO_PORT CLR1: CLRP024 Mask */ -#define GPIO_PORT_CLR1_CLRP025_Pos 25 /*!< GPIO_PORT CLR1: CLRP025 Position */ -#define GPIO_PORT_CLR1_CLRP025_Msk (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos) /*!< GPIO_PORT CLR1: CLRP025 Mask */ -#define GPIO_PORT_CLR1_CLRP026_Pos 26 /*!< GPIO_PORT CLR1: CLRP026 Position */ -#define GPIO_PORT_CLR1_CLRP026_Msk (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos) /*!< GPIO_PORT CLR1: CLRP026 Mask */ -#define GPIO_PORT_CLR1_CLRP027_Pos 27 /*!< GPIO_PORT CLR1: CLRP027 Position */ -#define GPIO_PORT_CLR1_CLRP027_Msk (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos) /*!< GPIO_PORT CLR1: CLRP027 Mask */ -#define GPIO_PORT_CLR1_CLRP028_Pos 28 /*!< GPIO_PORT CLR1: CLRP028 Position */ -#define GPIO_PORT_CLR1_CLRP028_Msk (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos) /*!< GPIO_PORT CLR1: CLRP028 Mask */ -#define GPIO_PORT_CLR1_CLRP029_Pos 29 /*!< GPIO_PORT CLR1: CLRP029 Position */ -#define GPIO_PORT_CLR1_CLRP029_Msk (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos) /*!< GPIO_PORT CLR1: CLRP029 Mask */ -#define GPIO_PORT_CLR1_CLRP030_Pos 30 /*!< GPIO_PORT CLR1: CLRP030 Position */ -#define GPIO_PORT_CLR1_CLRP030_Msk (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos) /*!< GPIO_PORT CLR1: CLRP030 Mask */ -#define GPIO_PORT_CLR1_CLRP031_Pos 31 /*!< GPIO_PORT CLR1: CLRP031 Position */ -#define GPIO_PORT_CLR1_CLRP031_Msk (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos) /*!< GPIO_PORT CLR1: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR2 ----------------------------------------- -#define GPIO_PORT_CLR2_CLRP00_Pos 0 /*!< GPIO_PORT CLR2: CLRP00 Position */ -#define GPIO_PORT_CLR2_CLRP00_Msk (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos) /*!< GPIO_PORT CLR2: CLRP00 Mask */ -#define GPIO_PORT_CLR2_CLRP01_Pos 1 /*!< GPIO_PORT CLR2: CLRP01 Position */ -#define GPIO_PORT_CLR2_CLRP01_Msk (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos) /*!< GPIO_PORT CLR2: CLRP01 Mask */ -#define GPIO_PORT_CLR2_CLRP02_Pos 2 /*!< GPIO_PORT CLR2: CLRP02 Position */ -#define GPIO_PORT_CLR2_CLRP02_Msk (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos) /*!< GPIO_PORT CLR2: CLRP02 Mask */ -#define GPIO_PORT_CLR2_CLRP03_Pos 3 /*!< GPIO_PORT CLR2: CLRP03 Position */ -#define GPIO_PORT_CLR2_CLRP03_Msk (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos) /*!< GPIO_PORT CLR2: CLRP03 Mask */ -#define GPIO_PORT_CLR2_CLRP04_Pos 4 /*!< GPIO_PORT CLR2: CLRP04 Position */ -#define GPIO_PORT_CLR2_CLRP04_Msk (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos) /*!< GPIO_PORT CLR2: CLRP04 Mask */ -#define GPIO_PORT_CLR2_CLRP05_Pos 5 /*!< GPIO_PORT CLR2: CLRP05 Position */ -#define GPIO_PORT_CLR2_CLRP05_Msk (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos) /*!< GPIO_PORT CLR2: CLRP05 Mask */ -#define GPIO_PORT_CLR2_CLRP06_Pos 6 /*!< GPIO_PORT CLR2: CLRP06 Position */ -#define GPIO_PORT_CLR2_CLRP06_Msk (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos) /*!< GPIO_PORT CLR2: CLRP06 Mask */ -#define GPIO_PORT_CLR2_CLRP07_Pos 7 /*!< GPIO_PORT CLR2: CLRP07 Position */ -#define GPIO_PORT_CLR2_CLRP07_Msk (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos) /*!< GPIO_PORT CLR2: CLRP07 Mask */ -#define GPIO_PORT_CLR2_CLRP08_Pos 8 /*!< GPIO_PORT CLR2: CLRP08 Position */ -#define GPIO_PORT_CLR2_CLRP08_Msk (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos) /*!< GPIO_PORT CLR2: CLRP08 Mask */ -#define GPIO_PORT_CLR2_CLRP09_Pos 9 /*!< GPIO_PORT CLR2: CLRP09 Position */ -#define GPIO_PORT_CLR2_CLRP09_Msk (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos) /*!< GPIO_PORT CLR2: CLRP09 Mask */ -#define GPIO_PORT_CLR2_CLRP010_Pos 10 /*!< GPIO_PORT CLR2: CLRP010 Position */ -#define GPIO_PORT_CLR2_CLRP010_Msk (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos) /*!< GPIO_PORT CLR2: CLRP010 Mask */ -#define GPIO_PORT_CLR2_CLRP011_Pos 11 /*!< GPIO_PORT CLR2: CLRP011 Position */ -#define GPIO_PORT_CLR2_CLRP011_Msk (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos) /*!< GPIO_PORT CLR2: CLRP011 Mask */ -#define GPIO_PORT_CLR2_CLRP012_Pos 12 /*!< GPIO_PORT CLR2: CLRP012 Position */ -#define GPIO_PORT_CLR2_CLRP012_Msk (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos) /*!< GPIO_PORT CLR2: CLRP012 Mask */ -#define GPIO_PORT_CLR2_CLRP013_Pos 13 /*!< GPIO_PORT CLR2: CLRP013 Position */ -#define GPIO_PORT_CLR2_CLRP013_Msk (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos) /*!< GPIO_PORT CLR2: CLRP013 Mask */ -#define GPIO_PORT_CLR2_CLRP014_Pos 14 /*!< GPIO_PORT CLR2: CLRP014 Position */ -#define GPIO_PORT_CLR2_CLRP014_Msk (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos) /*!< GPIO_PORT CLR2: CLRP014 Mask */ -#define GPIO_PORT_CLR2_CLRP015_Pos 15 /*!< GPIO_PORT CLR2: CLRP015 Position */ -#define GPIO_PORT_CLR2_CLRP015_Msk (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos) /*!< GPIO_PORT CLR2: CLRP015 Mask */ -#define GPIO_PORT_CLR2_CLRP016_Pos 16 /*!< GPIO_PORT CLR2: CLRP016 Position */ -#define GPIO_PORT_CLR2_CLRP016_Msk (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos) /*!< GPIO_PORT CLR2: CLRP016 Mask */ -#define GPIO_PORT_CLR2_CLRP017_Pos 17 /*!< GPIO_PORT CLR2: CLRP017 Position */ -#define GPIO_PORT_CLR2_CLRP017_Msk (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos) /*!< GPIO_PORT CLR2: CLRP017 Mask */ -#define GPIO_PORT_CLR2_CLRP018_Pos 18 /*!< GPIO_PORT CLR2: CLRP018 Position */ -#define GPIO_PORT_CLR2_CLRP018_Msk (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos) /*!< GPIO_PORT CLR2: CLRP018 Mask */ -#define GPIO_PORT_CLR2_CLRP019_Pos 19 /*!< GPIO_PORT CLR2: CLRP019 Position */ -#define GPIO_PORT_CLR2_CLRP019_Msk (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos) /*!< GPIO_PORT CLR2: CLRP019 Mask */ -#define GPIO_PORT_CLR2_CLRP020_Pos 20 /*!< GPIO_PORT CLR2: CLRP020 Position */ -#define GPIO_PORT_CLR2_CLRP020_Msk (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos) /*!< GPIO_PORT CLR2: CLRP020 Mask */ -#define GPIO_PORT_CLR2_CLRP021_Pos 21 /*!< GPIO_PORT CLR2: CLRP021 Position */ -#define GPIO_PORT_CLR2_CLRP021_Msk (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos) /*!< GPIO_PORT CLR2: CLRP021 Mask */ -#define GPIO_PORT_CLR2_CLRP022_Pos 22 /*!< GPIO_PORT CLR2: CLRP022 Position */ -#define GPIO_PORT_CLR2_CLRP022_Msk (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos) /*!< GPIO_PORT CLR2: CLRP022 Mask */ -#define GPIO_PORT_CLR2_CLRP023_Pos 23 /*!< GPIO_PORT CLR2: CLRP023 Position */ -#define GPIO_PORT_CLR2_CLRP023_Msk (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos) /*!< GPIO_PORT CLR2: CLRP023 Mask */ -#define GPIO_PORT_CLR2_CLRP024_Pos 24 /*!< GPIO_PORT CLR2: CLRP024 Position */ -#define GPIO_PORT_CLR2_CLRP024_Msk (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos) /*!< GPIO_PORT CLR2: CLRP024 Mask */ -#define GPIO_PORT_CLR2_CLRP025_Pos 25 /*!< GPIO_PORT CLR2: CLRP025 Position */ -#define GPIO_PORT_CLR2_CLRP025_Msk (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos) /*!< GPIO_PORT CLR2: CLRP025 Mask */ -#define GPIO_PORT_CLR2_CLRP026_Pos 26 /*!< GPIO_PORT CLR2: CLRP026 Position */ -#define GPIO_PORT_CLR2_CLRP026_Msk (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos) /*!< GPIO_PORT CLR2: CLRP026 Mask */ -#define GPIO_PORT_CLR2_CLRP027_Pos 27 /*!< GPIO_PORT CLR2: CLRP027 Position */ -#define GPIO_PORT_CLR2_CLRP027_Msk (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos) /*!< GPIO_PORT CLR2: CLRP027 Mask */ -#define GPIO_PORT_CLR2_CLRP028_Pos 28 /*!< GPIO_PORT CLR2: CLRP028 Position */ -#define GPIO_PORT_CLR2_CLRP028_Msk (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos) /*!< GPIO_PORT CLR2: CLRP028 Mask */ -#define GPIO_PORT_CLR2_CLRP029_Pos 29 /*!< GPIO_PORT CLR2: CLRP029 Position */ -#define GPIO_PORT_CLR2_CLRP029_Msk (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos) /*!< GPIO_PORT CLR2: CLRP029 Mask */ -#define GPIO_PORT_CLR2_CLRP030_Pos 30 /*!< GPIO_PORT CLR2: CLRP030 Position */ -#define GPIO_PORT_CLR2_CLRP030_Msk (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos) /*!< GPIO_PORT CLR2: CLRP030 Mask */ -#define GPIO_PORT_CLR2_CLRP031_Pos 31 /*!< GPIO_PORT CLR2: CLRP031 Position */ -#define GPIO_PORT_CLR2_CLRP031_Msk (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos) /*!< GPIO_PORT CLR2: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR3 ----------------------------------------- -#define GPIO_PORT_CLR3_CLRP00_Pos 0 /*!< GPIO_PORT CLR3: CLRP00 Position */ -#define GPIO_PORT_CLR3_CLRP00_Msk (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos) /*!< GPIO_PORT CLR3: CLRP00 Mask */ -#define GPIO_PORT_CLR3_CLRP01_Pos 1 /*!< GPIO_PORT CLR3: CLRP01 Position */ -#define GPIO_PORT_CLR3_CLRP01_Msk (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos) /*!< GPIO_PORT CLR3: CLRP01 Mask */ -#define GPIO_PORT_CLR3_CLRP02_Pos 2 /*!< GPIO_PORT CLR3: CLRP02 Position */ -#define GPIO_PORT_CLR3_CLRP02_Msk (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos) /*!< GPIO_PORT CLR3: CLRP02 Mask */ -#define GPIO_PORT_CLR3_CLRP03_Pos 3 /*!< GPIO_PORT CLR3: CLRP03 Position */ -#define GPIO_PORT_CLR3_CLRP03_Msk (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos) /*!< GPIO_PORT CLR3: CLRP03 Mask */ -#define GPIO_PORT_CLR3_CLRP04_Pos 4 /*!< GPIO_PORT CLR3: CLRP04 Position */ -#define GPIO_PORT_CLR3_CLRP04_Msk (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos) /*!< GPIO_PORT CLR3: CLRP04 Mask */ -#define GPIO_PORT_CLR3_CLRP05_Pos 5 /*!< GPIO_PORT CLR3: CLRP05 Position */ -#define GPIO_PORT_CLR3_CLRP05_Msk (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos) /*!< GPIO_PORT CLR3: CLRP05 Mask */ -#define GPIO_PORT_CLR3_CLRP06_Pos 6 /*!< GPIO_PORT CLR3: CLRP06 Position */ -#define GPIO_PORT_CLR3_CLRP06_Msk (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos) /*!< GPIO_PORT CLR3: CLRP06 Mask */ -#define GPIO_PORT_CLR3_CLRP07_Pos 7 /*!< GPIO_PORT CLR3: CLRP07 Position */ -#define GPIO_PORT_CLR3_CLRP07_Msk (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos) /*!< GPIO_PORT CLR3: CLRP07 Mask */ -#define GPIO_PORT_CLR3_CLRP08_Pos 8 /*!< GPIO_PORT CLR3: CLRP08 Position */ -#define GPIO_PORT_CLR3_CLRP08_Msk (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos) /*!< GPIO_PORT CLR3: CLRP08 Mask */ -#define GPIO_PORT_CLR3_CLRP09_Pos 9 /*!< GPIO_PORT CLR3: CLRP09 Position */ -#define GPIO_PORT_CLR3_CLRP09_Msk (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos) /*!< GPIO_PORT CLR3: CLRP09 Mask */ -#define GPIO_PORT_CLR3_CLRP010_Pos 10 /*!< GPIO_PORT CLR3: CLRP010 Position */ -#define GPIO_PORT_CLR3_CLRP010_Msk (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos) /*!< GPIO_PORT CLR3: CLRP010 Mask */ -#define GPIO_PORT_CLR3_CLRP011_Pos 11 /*!< GPIO_PORT CLR3: CLRP011 Position */ -#define GPIO_PORT_CLR3_CLRP011_Msk (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos) /*!< GPIO_PORT CLR3: CLRP011 Mask */ -#define GPIO_PORT_CLR3_CLRP012_Pos 12 /*!< GPIO_PORT CLR3: CLRP012 Position */ -#define GPIO_PORT_CLR3_CLRP012_Msk (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos) /*!< GPIO_PORT CLR3: CLRP012 Mask */ -#define GPIO_PORT_CLR3_CLRP013_Pos 13 /*!< GPIO_PORT CLR3: CLRP013 Position */ -#define GPIO_PORT_CLR3_CLRP013_Msk (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos) /*!< GPIO_PORT CLR3: CLRP013 Mask */ -#define GPIO_PORT_CLR3_CLRP014_Pos 14 /*!< GPIO_PORT CLR3: CLRP014 Position */ -#define GPIO_PORT_CLR3_CLRP014_Msk (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos) /*!< GPIO_PORT CLR3: CLRP014 Mask */ -#define GPIO_PORT_CLR3_CLRP015_Pos 15 /*!< GPIO_PORT CLR3: CLRP015 Position */ -#define GPIO_PORT_CLR3_CLRP015_Msk (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos) /*!< GPIO_PORT CLR3: CLRP015 Mask */ -#define GPIO_PORT_CLR3_CLRP016_Pos 16 /*!< GPIO_PORT CLR3: CLRP016 Position */ -#define GPIO_PORT_CLR3_CLRP016_Msk (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos) /*!< GPIO_PORT CLR3: CLRP016 Mask */ -#define GPIO_PORT_CLR3_CLRP017_Pos 17 /*!< GPIO_PORT CLR3: CLRP017 Position */ -#define GPIO_PORT_CLR3_CLRP017_Msk (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos) /*!< GPIO_PORT CLR3: CLRP017 Mask */ -#define GPIO_PORT_CLR3_CLRP018_Pos 18 /*!< GPIO_PORT CLR3: CLRP018 Position */ -#define GPIO_PORT_CLR3_CLRP018_Msk (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos) /*!< GPIO_PORT CLR3: CLRP018 Mask */ -#define GPIO_PORT_CLR3_CLRP019_Pos 19 /*!< GPIO_PORT CLR3: CLRP019 Position */ -#define GPIO_PORT_CLR3_CLRP019_Msk (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos) /*!< GPIO_PORT CLR3: CLRP019 Mask */ -#define GPIO_PORT_CLR3_CLRP020_Pos 20 /*!< GPIO_PORT CLR3: CLRP020 Position */ -#define GPIO_PORT_CLR3_CLRP020_Msk (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos) /*!< GPIO_PORT CLR3: CLRP020 Mask */ -#define GPIO_PORT_CLR3_CLRP021_Pos 21 /*!< GPIO_PORT CLR3: CLRP021 Position */ -#define GPIO_PORT_CLR3_CLRP021_Msk (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos) /*!< GPIO_PORT CLR3: CLRP021 Mask */ -#define GPIO_PORT_CLR3_CLRP022_Pos 22 /*!< GPIO_PORT CLR3: CLRP022 Position */ -#define GPIO_PORT_CLR3_CLRP022_Msk (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos) /*!< GPIO_PORT CLR3: CLRP022 Mask */ -#define GPIO_PORT_CLR3_CLRP023_Pos 23 /*!< GPIO_PORT CLR3: CLRP023 Position */ -#define GPIO_PORT_CLR3_CLRP023_Msk (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos) /*!< GPIO_PORT CLR3: CLRP023 Mask */ -#define GPIO_PORT_CLR3_CLRP024_Pos 24 /*!< GPIO_PORT CLR3: CLRP024 Position */ -#define GPIO_PORT_CLR3_CLRP024_Msk (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos) /*!< GPIO_PORT CLR3: CLRP024 Mask */ -#define GPIO_PORT_CLR3_CLRP025_Pos 25 /*!< GPIO_PORT CLR3: CLRP025 Position */ -#define GPIO_PORT_CLR3_CLRP025_Msk (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos) /*!< GPIO_PORT CLR3: CLRP025 Mask */ -#define GPIO_PORT_CLR3_CLRP026_Pos 26 /*!< GPIO_PORT CLR3: CLRP026 Position */ -#define GPIO_PORT_CLR3_CLRP026_Msk (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos) /*!< GPIO_PORT CLR3: CLRP026 Mask */ -#define GPIO_PORT_CLR3_CLRP027_Pos 27 /*!< GPIO_PORT CLR3: CLRP027 Position */ -#define GPIO_PORT_CLR3_CLRP027_Msk (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos) /*!< GPIO_PORT CLR3: CLRP027 Mask */ -#define GPIO_PORT_CLR3_CLRP028_Pos 28 /*!< GPIO_PORT CLR3: CLRP028 Position */ -#define GPIO_PORT_CLR3_CLRP028_Msk (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos) /*!< GPIO_PORT CLR3: CLRP028 Mask */ -#define GPIO_PORT_CLR3_CLRP029_Pos 29 /*!< GPIO_PORT CLR3: CLRP029 Position */ -#define GPIO_PORT_CLR3_CLRP029_Msk (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos) /*!< GPIO_PORT CLR3: CLRP029 Mask */ -#define GPIO_PORT_CLR3_CLRP030_Pos 30 /*!< GPIO_PORT CLR3: CLRP030 Position */ -#define GPIO_PORT_CLR3_CLRP030_Msk (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos) /*!< GPIO_PORT CLR3: CLRP030 Mask */ -#define GPIO_PORT_CLR3_CLRP031_Pos 31 /*!< GPIO_PORT CLR3: CLRP031 Position */ -#define GPIO_PORT_CLR3_CLRP031_Msk (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos) /*!< GPIO_PORT CLR3: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR4 ----------------------------------------- -#define GPIO_PORT_CLR4_CLRP00_Pos 0 /*!< GPIO_PORT CLR4: CLRP00 Position */ -#define GPIO_PORT_CLR4_CLRP00_Msk (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos) /*!< GPIO_PORT CLR4: CLRP00 Mask */ -#define GPIO_PORT_CLR4_CLRP01_Pos 1 /*!< GPIO_PORT CLR4: CLRP01 Position */ -#define GPIO_PORT_CLR4_CLRP01_Msk (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos) /*!< GPIO_PORT CLR4: CLRP01 Mask */ -#define GPIO_PORT_CLR4_CLRP02_Pos 2 /*!< GPIO_PORT CLR4: CLRP02 Position */ -#define GPIO_PORT_CLR4_CLRP02_Msk (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos) /*!< GPIO_PORT CLR4: CLRP02 Mask */ -#define GPIO_PORT_CLR4_CLRP03_Pos 3 /*!< GPIO_PORT CLR4: CLRP03 Position */ -#define GPIO_PORT_CLR4_CLRP03_Msk (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos) /*!< GPIO_PORT CLR4: CLRP03 Mask */ -#define GPIO_PORT_CLR4_CLRP04_Pos 4 /*!< GPIO_PORT CLR4: CLRP04 Position */ -#define GPIO_PORT_CLR4_CLRP04_Msk (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos) /*!< GPIO_PORT CLR4: CLRP04 Mask */ -#define GPIO_PORT_CLR4_CLRP05_Pos 5 /*!< GPIO_PORT CLR4: CLRP05 Position */ -#define GPIO_PORT_CLR4_CLRP05_Msk (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos) /*!< GPIO_PORT CLR4: CLRP05 Mask */ -#define GPIO_PORT_CLR4_CLRP06_Pos 6 /*!< GPIO_PORT CLR4: CLRP06 Position */ -#define GPIO_PORT_CLR4_CLRP06_Msk (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos) /*!< GPIO_PORT CLR4: CLRP06 Mask */ -#define GPIO_PORT_CLR4_CLRP07_Pos 7 /*!< GPIO_PORT CLR4: CLRP07 Position */ -#define GPIO_PORT_CLR4_CLRP07_Msk (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos) /*!< GPIO_PORT CLR4: CLRP07 Mask */ -#define GPIO_PORT_CLR4_CLRP08_Pos 8 /*!< GPIO_PORT CLR4: CLRP08 Position */ -#define GPIO_PORT_CLR4_CLRP08_Msk (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos) /*!< GPIO_PORT CLR4: CLRP08 Mask */ -#define GPIO_PORT_CLR4_CLRP09_Pos 9 /*!< GPIO_PORT CLR4: CLRP09 Position */ -#define GPIO_PORT_CLR4_CLRP09_Msk (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos) /*!< GPIO_PORT CLR4: CLRP09 Mask */ -#define GPIO_PORT_CLR4_CLRP010_Pos 10 /*!< GPIO_PORT CLR4: CLRP010 Position */ -#define GPIO_PORT_CLR4_CLRP010_Msk (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos) /*!< GPIO_PORT CLR4: CLRP010 Mask */ -#define GPIO_PORT_CLR4_CLRP011_Pos 11 /*!< GPIO_PORT CLR4: CLRP011 Position */ -#define GPIO_PORT_CLR4_CLRP011_Msk (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos) /*!< GPIO_PORT CLR4: CLRP011 Mask */ -#define GPIO_PORT_CLR4_CLRP012_Pos 12 /*!< GPIO_PORT CLR4: CLRP012 Position */ -#define GPIO_PORT_CLR4_CLRP012_Msk (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos) /*!< GPIO_PORT CLR4: CLRP012 Mask */ -#define GPIO_PORT_CLR4_CLRP013_Pos 13 /*!< GPIO_PORT CLR4: CLRP013 Position */ -#define GPIO_PORT_CLR4_CLRP013_Msk (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos) /*!< GPIO_PORT CLR4: CLRP013 Mask */ -#define GPIO_PORT_CLR4_CLRP014_Pos 14 /*!< GPIO_PORT CLR4: CLRP014 Position */ -#define GPIO_PORT_CLR4_CLRP014_Msk (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos) /*!< GPIO_PORT CLR4: CLRP014 Mask */ -#define GPIO_PORT_CLR4_CLRP015_Pos 15 /*!< GPIO_PORT CLR4: CLRP015 Position */ -#define GPIO_PORT_CLR4_CLRP015_Msk (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos) /*!< GPIO_PORT CLR4: CLRP015 Mask */ -#define GPIO_PORT_CLR4_CLRP016_Pos 16 /*!< GPIO_PORT CLR4: CLRP016 Position */ -#define GPIO_PORT_CLR4_CLRP016_Msk (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos) /*!< GPIO_PORT CLR4: CLRP016 Mask */ -#define GPIO_PORT_CLR4_CLRP017_Pos 17 /*!< GPIO_PORT CLR4: CLRP017 Position */ -#define GPIO_PORT_CLR4_CLRP017_Msk (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos) /*!< GPIO_PORT CLR4: CLRP017 Mask */ -#define GPIO_PORT_CLR4_CLRP018_Pos 18 /*!< GPIO_PORT CLR4: CLRP018 Position */ -#define GPIO_PORT_CLR4_CLRP018_Msk (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos) /*!< GPIO_PORT CLR4: CLRP018 Mask */ -#define GPIO_PORT_CLR4_CLRP019_Pos 19 /*!< GPIO_PORT CLR4: CLRP019 Position */ -#define GPIO_PORT_CLR4_CLRP019_Msk (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos) /*!< GPIO_PORT CLR4: CLRP019 Mask */ -#define GPIO_PORT_CLR4_CLRP020_Pos 20 /*!< GPIO_PORT CLR4: CLRP020 Position */ -#define GPIO_PORT_CLR4_CLRP020_Msk (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos) /*!< GPIO_PORT CLR4: CLRP020 Mask */ -#define GPIO_PORT_CLR4_CLRP021_Pos 21 /*!< GPIO_PORT CLR4: CLRP021 Position */ -#define GPIO_PORT_CLR4_CLRP021_Msk (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos) /*!< GPIO_PORT CLR4: CLRP021 Mask */ -#define GPIO_PORT_CLR4_CLRP022_Pos 22 /*!< GPIO_PORT CLR4: CLRP022 Position */ -#define GPIO_PORT_CLR4_CLRP022_Msk (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos) /*!< GPIO_PORT CLR4: CLRP022 Mask */ -#define GPIO_PORT_CLR4_CLRP023_Pos 23 /*!< GPIO_PORT CLR4: CLRP023 Position */ -#define GPIO_PORT_CLR4_CLRP023_Msk (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos) /*!< GPIO_PORT CLR4: CLRP023 Mask */ -#define GPIO_PORT_CLR4_CLRP024_Pos 24 /*!< GPIO_PORT CLR4: CLRP024 Position */ -#define GPIO_PORT_CLR4_CLRP024_Msk (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos) /*!< GPIO_PORT CLR4: CLRP024 Mask */ -#define GPIO_PORT_CLR4_CLRP025_Pos 25 /*!< GPIO_PORT CLR4: CLRP025 Position */ -#define GPIO_PORT_CLR4_CLRP025_Msk (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos) /*!< GPIO_PORT CLR4: CLRP025 Mask */ -#define GPIO_PORT_CLR4_CLRP026_Pos 26 /*!< GPIO_PORT CLR4: CLRP026 Position */ -#define GPIO_PORT_CLR4_CLRP026_Msk (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos) /*!< GPIO_PORT CLR4: CLRP026 Mask */ -#define GPIO_PORT_CLR4_CLRP027_Pos 27 /*!< GPIO_PORT CLR4: CLRP027 Position */ -#define GPIO_PORT_CLR4_CLRP027_Msk (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos) /*!< GPIO_PORT CLR4: CLRP027 Mask */ -#define GPIO_PORT_CLR4_CLRP028_Pos 28 /*!< GPIO_PORT CLR4: CLRP028 Position */ -#define GPIO_PORT_CLR4_CLRP028_Msk (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos) /*!< GPIO_PORT CLR4: CLRP028 Mask */ -#define GPIO_PORT_CLR4_CLRP029_Pos 29 /*!< GPIO_PORT CLR4: CLRP029 Position */ -#define GPIO_PORT_CLR4_CLRP029_Msk (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos) /*!< GPIO_PORT CLR4: CLRP029 Mask */ -#define GPIO_PORT_CLR4_CLRP030_Pos 30 /*!< GPIO_PORT CLR4: CLRP030 Position */ -#define GPIO_PORT_CLR4_CLRP030_Msk (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos) /*!< GPIO_PORT CLR4: CLRP030 Mask */ -#define GPIO_PORT_CLR4_CLRP031_Pos 31 /*!< GPIO_PORT CLR4: CLRP031 Position */ -#define GPIO_PORT_CLR4_CLRP031_Msk (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos) /*!< GPIO_PORT CLR4: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR5 ----------------------------------------- -#define GPIO_PORT_CLR5_CLRP00_Pos 0 /*!< GPIO_PORT CLR5: CLRP00 Position */ -#define GPIO_PORT_CLR5_CLRP00_Msk (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos) /*!< GPIO_PORT CLR5: CLRP00 Mask */ -#define GPIO_PORT_CLR5_CLRP01_Pos 1 /*!< GPIO_PORT CLR5: CLRP01 Position */ -#define GPIO_PORT_CLR5_CLRP01_Msk (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos) /*!< GPIO_PORT CLR5: CLRP01 Mask */ -#define GPIO_PORT_CLR5_CLRP02_Pos 2 /*!< GPIO_PORT CLR5: CLRP02 Position */ -#define GPIO_PORT_CLR5_CLRP02_Msk (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos) /*!< GPIO_PORT CLR5: CLRP02 Mask */ -#define GPIO_PORT_CLR5_CLRP03_Pos 3 /*!< GPIO_PORT CLR5: CLRP03 Position */ -#define GPIO_PORT_CLR5_CLRP03_Msk (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos) /*!< GPIO_PORT CLR5: CLRP03 Mask */ -#define GPIO_PORT_CLR5_CLRP04_Pos 4 /*!< GPIO_PORT CLR5: CLRP04 Position */ -#define GPIO_PORT_CLR5_CLRP04_Msk (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos) /*!< GPIO_PORT CLR5: CLRP04 Mask */ -#define GPIO_PORT_CLR5_CLRP05_Pos 5 /*!< GPIO_PORT CLR5: CLRP05 Position */ -#define GPIO_PORT_CLR5_CLRP05_Msk (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos) /*!< GPIO_PORT CLR5: CLRP05 Mask */ -#define GPIO_PORT_CLR5_CLRP06_Pos 6 /*!< GPIO_PORT CLR5: CLRP06 Position */ -#define GPIO_PORT_CLR5_CLRP06_Msk (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos) /*!< GPIO_PORT CLR5: CLRP06 Mask */ -#define GPIO_PORT_CLR5_CLRP07_Pos 7 /*!< GPIO_PORT CLR5: CLRP07 Position */ -#define GPIO_PORT_CLR5_CLRP07_Msk (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos) /*!< GPIO_PORT CLR5: CLRP07 Mask */ -#define GPIO_PORT_CLR5_CLRP08_Pos 8 /*!< GPIO_PORT CLR5: CLRP08 Position */ -#define GPIO_PORT_CLR5_CLRP08_Msk (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos) /*!< GPIO_PORT CLR5: CLRP08 Mask */ -#define GPIO_PORT_CLR5_CLRP09_Pos 9 /*!< GPIO_PORT CLR5: CLRP09 Position */ -#define GPIO_PORT_CLR5_CLRP09_Msk (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos) /*!< GPIO_PORT CLR5: CLRP09 Mask */ -#define GPIO_PORT_CLR5_CLRP010_Pos 10 /*!< GPIO_PORT CLR5: CLRP010 Position */ -#define GPIO_PORT_CLR5_CLRP010_Msk (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos) /*!< GPIO_PORT CLR5: CLRP010 Mask */ -#define GPIO_PORT_CLR5_CLRP011_Pos 11 /*!< GPIO_PORT CLR5: CLRP011 Position */ -#define GPIO_PORT_CLR5_CLRP011_Msk (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos) /*!< GPIO_PORT CLR5: CLRP011 Mask */ -#define GPIO_PORT_CLR5_CLRP012_Pos 12 /*!< GPIO_PORT CLR5: CLRP012 Position */ -#define GPIO_PORT_CLR5_CLRP012_Msk (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos) /*!< GPIO_PORT CLR5: CLRP012 Mask */ -#define GPIO_PORT_CLR5_CLRP013_Pos 13 /*!< GPIO_PORT CLR5: CLRP013 Position */ -#define GPIO_PORT_CLR5_CLRP013_Msk (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos) /*!< GPIO_PORT CLR5: CLRP013 Mask */ -#define GPIO_PORT_CLR5_CLRP014_Pos 14 /*!< GPIO_PORT CLR5: CLRP014 Position */ -#define GPIO_PORT_CLR5_CLRP014_Msk (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos) /*!< GPIO_PORT CLR5: CLRP014 Mask */ -#define GPIO_PORT_CLR5_CLRP015_Pos 15 /*!< GPIO_PORT CLR5: CLRP015 Position */ -#define GPIO_PORT_CLR5_CLRP015_Msk (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos) /*!< GPIO_PORT CLR5: CLRP015 Mask */ -#define GPIO_PORT_CLR5_CLRP016_Pos 16 /*!< GPIO_PORT CLR5: CLRP016 Position */ -#define GPIO_PORT_CLR5_CLRP016_Msk (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos) /*!< GPIO_PORT CLR5: CLRP016 Mask */ -#define GPIO_PORT_CLR5_CLRP017_Pos 17 /*!< GPIO_PORT CLR5: CLRP017 Position */ -#define GPIO_PORT_CLR5_CLRP017_Msk (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos) /*!< GPIO_PORT CLR5: CLRP017 Mask */ -#define GPIO_PORT_CLR5_CLRP018_Pos 18 /*!< GPIO_PORT CLR5: CLRP018 Position */ -#define GPIO_PORT_CLR5_CLRP018_Msk (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos) /*!< GPIO_PORT CLR5: CLRP018 Mask */ -#define GPIO_PORT_CLR5_CLRP019_Pos 19 /*!< GPIO_PORT CLR5: CLRP019 Position */ -#define GPIO_PORT_CLR5_CLRP019_Msk (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos) /*!< GPIO_PORT CLR5: CLRP019 Mask */ -#define GPIO_PORT_CLR5_CLRP020_Pos 20 /*!< GPIO_PORT CLR5: CLRP020 Position */ -#define GPIO_PORT_CLR5_CLRP020_Msk (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos) /*!< GPIO_PORT CLR5: CLRP020 Mask */ -#define GPIO_PORT_CLR5_CLRP021_Pos 21 /*!< GPIO_PORT CLR5: CLRP021 Position */ -#define GPIO_PORT_CLR5_CLRP021_Msk (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos) /*!< GPIO_PORT CLR5: CLRP021 Mask */ -#define GPIO_PORT_CLR5_CLRP022_Pos 22 /*!< GPIO_PORT CLR5: CLRP022 Position */ -#define GPIO_PORT_CLR5_CLRP022_Msk (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos) /*!< GPIO_PORT CLR5: CLRP022 Mask */ -#define GPIO_PORT_CLR5_CLRP023_Pos 23 /*!< GPIO_PORT CLR5: CLRP023 Position */ -#define GPIO_PORT_CLR5_CLRP023_Msk (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos) /*!< GPIO_PORT CLR5: CLRP023 Mask */ -#define GPIO_PORT_CLR5_CLRP024_Pos 24 /*!< GPIO_PORT CLR5: CLRP024 Position */ -#define GPIO_PORT_CLR5_CLRP024_Msk (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos) /*!< GPIO_PORT CLR5: CLRP024 Mask */ -#define GPIO_PORT_CLR5_CLRP025_Pos 25 /*!< GPIO_PORT CLR5: CLRP025 Position */ -#define GPIO_PORT_CLR5_CLRP025_Msk (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos) /*!< GPIO_PORT CLR5: CLRP025 Mask */ -#define GPIO_PORT_CLR5_CLRP026_Pos 26 /*!< GPIO_PORT CLR5: CLRP026 Position */ -#define GPIO_PORT_CLR5_CLRP026_Msk (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos) /*!< GPIO_PORT CLR5: CLRP026 Mask */ -#define GPIO_PORT_CLR5_CLRP027_Pos 27 /*!< GPIO_PORT CLR5: CLRP027 Position */ -#define GPIO_PORT_CLR5_CLRP027_Msk (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos) /*!< GPIO_PORT CLR5: CLRP027 Mask */ -#define GPIO_PORT_CLR5_CLRP028_Pos 28 /*!< GPIO_PORT CLR5: CLRP028 Position */ -#define GPIO_PORT_CLR5_CLRP028_Msk (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos) /*!< GPIO_PORT CLR5: CLRP028 Mask */ -#define GPIO_PORT_CLR5_CLRP029_Pos 29 /*!< GPIO_PORT CLR5: CLRP029 Position */ -#define GPIO_PORT_CLR5_CLRP029_Msk (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos) /*!< GPIO_PORT CLR5: CLRP029 Mask */ -#define GPIO_PORT_CLR5_CLRP030_Pos 30 /*!< GPIO_PORT CLR5: CLRP030 Position */ -#define GPIO_PORT_CLR5_CLRP030_Msk (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos) /*!< GPIO_PORT CLR5: CLRP030 Mask */ -#define GPIO_PORT_CLR5_CLRP031_Pos 31 /*!< GPIO_PORT CLR5: CLRP031 Position */ -#define GPIO_PORT_CLR5_CLRP031_Msk (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos) /*!< GPIO_PORT CLR5: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR6 ----------------------------------------- -#define GPIO_PORT_CLR6_CLRP00_Pos 0 /*!< GPIO_PORT CLR6: CLRP00 Position */ -#define GPIO_PORT_CLR6_CLRP00_Msk (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos) /*!< GPIO_PORT CLR6: CLRP00 Mask */ -#define GPIO_PORT_CLR6_CLRP01_Pos 1 /*!< GPIO_PORT CLR6: CLRP01 Position */ -#define GPIO_PORT_CLR6_CLRP01_Msk (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos) /*!< GPIO_PORT CLR6: CLRP01 Mask */ -#define GPIO_PORT_CLR6_CLRP02_Pos 2 /*!< GPIO_PORT CLR6: CLRP02 Position */ -#define GPIO_PORT_CLR6_CLRP02_Msk (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos) /*!< GPIO_PORT CLR6: CLRP02 Mask */ -#define GPIO_PORT_CLR6_CLRP03_Pos 3 /*!< GPIO_PORT CLR6: CLRP03 Position */ -#define GPIO_PORT_CLR6_CLRP03_Msk (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos) /*!< GPIO_PORT CLR6: CLRP03 Mask */ -#define GPIO_PORT_CLR6_CLRP04_Pos 4 /*!< GPIO_PORT CLR6: CLRP04 Position */ -#define GPIO_PORT_CLR6_CLRP04_Msk (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos) /*!< GPIO_PORT CLR6: CLRP04 Mask */ -#define GPIO_PORT_CLR6_CLRP05_Pos 5 /*!< GPIO_PORT CLR6: CLRP05 Position */ -#define GPIO_PORT_CLR6_CLRP05_Msk (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos) /*!< GPIO_PORT CLR6: CLRP05 Mask */ -#define GPIO_PORT_CLR6_CLRP06_Pos 6 /*!< GPIO_PORT CLR6: CLRP06 Position */ -#define GPIO_PORT_CLR6_CLRP06_Msk (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos) /*!< GPIO_PORT CLR6: CLRP06 Mask */ -#define GPIO_PORT_CLR6_CLRP07_Pos 7 /*!< GPIO_PORT CLR6: CLRP07 Position */ -#define GPIO_PORT_CLR6_CLRP07_Msk (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos) /*!< GPIO_PORT CLR6: CLRP07 Mask */ -#define GPIO_PORT_CLR6_CLRP08_Pos 8 /*!< GPIO_PORT CLR6: CLRP08 Position */ -#define GPIO_PORT_CLR6_CLRP08_Msk (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos) /*!< GPIO_PORT CLR6: CLRP08 Mask */ -#define GPIO_PORT_CLR6_CLRP09_Pos 9 /*!< GPIO_PORT CLR6: CLRP09 Position */ -#define GPIO_PORT_CLR6_CLRP09_Msk (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos) /*!< GPIO_PORT CLR6: CLRP09 Mask */ -#define GPIO_PORT_CLR6_CLRP010_Pos 10 /*!< GPIO_PORT CLR6: CLRP010 Position */ -#define GPIO_PORT_CLR6_CLRP010_Msk (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos) /*!< GPIO_PORT CLR6: CLRP010 Mask */ -#define GPIO_PORT_CLR6_CLRP011_Pos 11 /*!< GPIO_PORT CLR6: CLRP011 Position */ -#define GPIO_PORT_CLR6_CLRP011_Msk (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos) /*!< GPIO_PORT CLR6: CLRP011 Mask */ -#define GPIO_PORT_CLR6_CLRP012_Pos 12 /*!< GPIO_PORT CLR6: CLRP012 Position */ -#define GPIO_PORT_CLR6_CLRP012_Msk (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos) /*!< GPIO_PORT CLR6: CLRP012 Mask */ -#define GPIO_PORT_CLR6_CLRP013_Pos 13 /*!< GPIO_PORT CLR6: CLRP013 Position */ -#define GPIO_PORT_CLR6_CLRP013_Msk (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos) /*!< GPIO_PORT CLR6: CLRP013 Mask */ -#define GPIO_PORT_CLR6_CLRP014_Pos 14 /*!< GPIO_PORT CLR6: CLRP014 Position */ -#define GPIO_PORT_CLR6_CLRP014_Msk (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos) /*!< GPIO_PORT CLR6: CLRP014 Mask */ -#define GPIO_PORT_CLR6_CLRP015_Pos 15 /*!< GPIO_PORT CLR6: CLRP015 Position */ -#define GPIO_PORT_CLR6_CLRP015_Msk (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos) /*!< GPIO_PORT CLR6: CLRP015 Mask */ -#define GPIO_PORT_CLR6_CLRP016_Pos 16 /*!< GPIO_PORT CLR6: CLRP016 Position */ -#define GPIO_PORT_CLR6_CLRP016_Msk (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos) /*!< GPIO_PORT CLR6: CLRP016 Mask */ -#define GPIO_PORT_CLR6_CLRP017_Pos 17 /*!< GPIO_PORT CLR6: CLRP017 Position */ -#define GPIO_PORT_CLR6_CLRP017_Msk (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos) /*!< GPIO_PORT CLR6: CLRP017 Mask */ -#define GPIO_PORT_CLR6_CLRP018_Pos 18 /*!< GPIO_PORT CLR6: CLRP018 Position */ -#define GPIO_PORT_CLR6_CLRP018_Msk (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos) /*!< GPIO_PORT CLR6: CLRP018 Mask */ -#define GPIO_PORT_CLR6_CLRP019_Pos 19 /*!< GPIO_PORT CLR6: CLRP019 Position */ -#define GPIO_PORT_CLR6_CLRP019_Msk (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos) /*!< GPIO_PORT CLR6: CLRP019 Mask */ -#define GPIO_PORT_CLR6_CLRP020_Pos 20 /*!< GPIO_PORT CLR6: CLRP020 Position */ -#define GPIO_PORT_CLR6_CLRP020_Msk (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos) /*!< GPIO_PORT CLR6: CLRP020 Mask */ -#define GPIO_PORT_CLR6_CLRP021_Pos 21 /*!< GPIO_PORT CLR6: CLRP021 Position */ -#define GPIO_PORT_CLR6_CLRP021_Msk (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos) /*!< GPIO_PORT CLR6: CLRP021 Mask */ -#define GPIO_PORT_CLR6_CLRP022_Pos 22 /*!< GPIO_PORT CLR6: CLRP022 Position */ -#define GPIO_PORT_CLR6_CLRP022_Msk (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos) /*!< GPIO_PORT CLR6: CLRP022 Mask */ -#define GPIO_PORT_CLR6_CLRP023_Pos 23 /*!< GPIO_PORT CLR6: CLRP023 Position */ -#define GPIO_PORT_CLR6_CLRP023_Msk (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos) /*!< GPIO_PORT CLR6: CLRP023 Mask */ -#define GPIO_PORT_CLR6_CLRP024_Pos 24 /*!< GPIO_PORT CLR6: CLRP024 Position */ -#define GPIO_PORT_CLR6_CLRP024_Msk (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos) /*!< GPIO_PORT CLR6: CLRP024 Mask */ -#define GPIO_PORT_CLR6_CLRP025_Pos 25 /*!< GPIO_PORT CLR6: CLRP025 Position */ -#define GPIO_PORT_CLR6_CLRP025_Msk (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos) /*!< GPIO_PORT CLR6: CLRP025 Mask */ -#define GPIO_PORT_CLR6_CLRP026_Pos 26 /*!< GPIO_PORT CLR6: CLRP026 Position */ -#define GPIO_PORT_CLR6_CLRP026_Msk (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos) /*!< GPIO_PORT CLR6: CLRP026 Mask */ -#define GPIO_PORT_CLR6_CLRP027_Pos 27 /*!< GPIO_PORT CLR6: CLRP027 Position */ -#define GPIO_PORT_CLR6_CLRP027_Msk (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos) /*!< GPIO_PORT CLR6: CLRP027 Mask */ -#define GPIO_PORT_CLR6_CLRP028_Pos 28 /*!< GPIO_PORT CLR6: CLRP028 Position */ -#define GPIO_PORT_CLR6_CLRP028_Msk (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos) /*!< GPIO_PORT CLR6: CLRP028 Mask */ -#define GPIO_PORT_CLR6_CLRP029_Pos 29 /*!< GPIO_PORT CLR6: CLRP029 Position */ -#define GPIO_PORT_CLR6_CLRP029_Msk (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos) /*!< GPIO_PORT CLR6: CLRP029 Mask */ -#define GPIO_PORT_CLR6_CLRP030_Pos 30 /*!< GPIO_PORT CLR6: CLRP030 Position */ -#define GPIO_PORT_CLR6_CLRP030_Msk (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos) /*!< GPIO_PORT CLR6: CLRP030 Mask */ -#define GPIO_PORT_CLR6_CLRP031_Pos 31 /*!< GPIO_PORT CLR6: CLRP031 Position */ -#define GPIO_PORT_CLR6_CLRP031_Msk (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos) /*!< GPIO_PORT CLR6: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR7 ----------------------------------------- -#define GPIO_PORT_CLR7_CLRP00_Pos 0 /*!< GPIO_PORT CLR7: CLRP00 Position */ -#define GPIO_PORT_CLR7_CLRP00_Msk (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos) /*!< GPIO_PORT CLR7: CLRP00 Mask */ -#define GPIO_PORT_CLR7_CLRP01_Pos 1 /*!< GPIO_PORT CLR7: CLRP01 Position */ -#define GPIO_PORT_CLR7_CLRP01_Msk (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos) /*!< GPIO_PORT CLR7: CLRP01 Mask */ -#define GPIO_PORT_CLR7_CLRP02_Pos 2 /*!< GPIO_PORT CLR7: CLRP02 Position */ -#define GPIO_PORT_CLR7_CLRP02_Msk (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos) /*!< GPIO_PORT CLR7: CLRP02 Mask */ -#define GPIO_PORT_CLR7_CLRP03_Pos 3 /*!< GPIO_PORT CLR7: CLRP03 Position */ -#define GPIO_PORT_CLR7_CLRP03_Msk (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos) /*!< GPIO_PORT CLR7: CLRP03 Mask */ -#define GPIO_PORT_CLR7_CLRP04_Pos 4 /*!< GPIO_PORT CLR7: CLRP04 Position */ -#define GPIO_PORT_CLR7_CLRP04_Msk (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos) /*!< GPIO_PORT CLR7: CLRP04 Mask */ -#define GPIO_PORT_CLR7_CLRP05_Pos 5 /*!< GPIO_PORT CLR7: CLRP05 Position */ -#define GPIO_PORT_CLR7_CLRP05_Msk (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos) /*!< GPIO_PORT CLR7: CLRP05 Mask */ -#define GPIO_PORT_CLR7_CLRP06_Pos 6 /*!< GPIO_PORT CLR7: CLRP06 Position */ -#define GPIO_PORT_CLR7_CLRP06_Msk (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos) /*!< GPIO_PORT CLR7: CLRP06 Mask */ -#define GPIO_PORT_CLR7_CLRP07_Pos 7 /*!< GPIO_PORT CLR7: CLRP07 Position */ -#define GPIO_PORT_CLR7_CLRP07_Msk (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos) /*!< GPIO_PORT CLR7: CLRP07 Mask */ -#define GPIO_PORT_CLR7_CLRP08_Pos 8 /*!< GPIO_PORT CLR7: CLRP08 Position */ -#define GPIO_PORT_CLR7_CLRP08_Msk (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos) /*!< GPIO_PORT CLR7: CLRP08 Mask */ -#define GPIO_PORT_CLR7_CLRP09_Pos 9 /*!< GPIO_PORT CLR7: CLRP09 Position */ -#define GPIO_PORT_CLR7_CLRP09_Msk (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos) /*!< GPIO_PORT CLR7: CLRP09 Mask */ -#define GPIO_PORT_CLR7_CLRP010_Pos 10 /*!< GPIO_PORT CLR7: CLRP010 Position */ -#define GPIO_PORT_CLR7_CLRP010_Msk (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos) /*!< GPIO_PORT CLR7: CLRP010 Mask */ -#define GPIO_PORT_CLR7_CLRP011_Pos 11 /*!< GPIO_PORT CLR7: CLRP011 Position */ -#define GPIO_PORT_CLR7_CLRP011_Msk (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos) /*!< GPIO_PORT CLR7: CLRP011 Mask */ -#define GPIO_PORT_CLR7_CLRP012_Pos 12 /*!< GPIO_PORT CLR7: CLRP012 Position */ -#define GPIO_PORT_CLR7_CLRP012_Msk (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos) /*!< GPIO_PORT CLR7: CLRP012 Mask */ -#define GPIO_PORT_CLR7_CLRP013_Pos 13 /*!< GPIO_PORT CLR7: CLRP013 Position */ -#define GPIO_PORT_CLR7_CLRP013_Msk (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos) /*!< GPIO_PORT CLR7: CLRP013 Mask */ -#define GPIO_PORT_CLR7_CLRP014_Pos 14 /*!< GPIO_PORT CLR7: CLRP014 Position */ -#define GPIO_PORT_CLR7_CLRP014_Msk (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos) /*!< GPIO_PORT CLR7: CLRP014 Mask */ -#define GPIO_PORT_CLR7_CLRP015_Pos 15 /*!< GPIO_PORT CLR7: CLRP015 Position */ -#define GPIO_PORT_CLR7_CLRP015_Msk (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos) /*!< GPIO_PORT CLR7: CLRP015 Mask */ -#define GPIO_PORT_CLR7_CLRP016_Pos 16 /*!< GPIO_PORT CLR7: CLRP016 Position */ -#define GPIO_PORT_CLR7_CLRP016_Msk (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos) /*!< GPIO_PORT CLR7: CLRP016 Mask */ -#define GPIO_PORT_CLR7_CLRP017_Pos 17 /*!< GPIO_PORT CLR7: CLRP017 Position */ -#define GPIO_PORT_CLR7_CLRP017_Msk (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos) /*!< GPIO_PORT CLR7: CLRP017 Mask */ -#define GPIO_PORT_CLR7_CLRP018_Pos 18 /*!< GPIO_PORT CLR7: CLRP018 Position */ -#define GPIO_PORT_CLR7_CLRP018_Msk (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos) /*!< GPIO_PORT CLR7: CLRP018 Mask */ -#define GPIO_PORT_CLR7_CLRP019_Pos 19 /*!< GPIO_PORT CLR7: CLRP019 Position */ -#define GPIO_PORT_CLR7_CLRP019_Msk (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos) /*!< GPIO_PORT CLR7: CLRP019 Mask */ -#define GPIO_PORT_CLR7_CLRP020_Pos 20 /*!< GPIO_PORT CLR7: CLRP020 Position */ -#define GPIO_PORT_CLR7_CLRP020_Msk (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos) /*!< GPIO_PORT CLR7: CLRP020 Mask */ -#define GPIO_PORT_CLR7_CLRP021_Pos 21 /*!< GPIO_PORT CLR7: CLRP021 Position */ -#define GPIO_PORT_CLR7_CLRP021_Msk (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos) /*!< GPIO_PORT CLR7: CLRP021 Mask */ -#define GPIO_PORT_CLR7_CLRP022_Pos 22 /*!< GPIO_PORT CLR7: CLRP022 Position */ -#define GPIO_PORT_CLR7_CLRP022_Msk (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos) /*!< GPIO_PORT CLR7: CLRP022 Mask */ -#define GPIO_PORT_CLR7_CLRP023_Pos 23 /*!< GPIO_PORT CLR7: CLRP023 Position */ -#define GPIO_PORT_CLR7_CLRP023_Msk (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos) /*!< GPIO_PORT CLR7: CLRP023 Mask */ -#define GPIO_PORT_CLR7_CLRP024_Pos 24 /*!< GPIO_PORT CLR7: CLRP024 Position */ -#define GPIO_PORT_CLR7_CLRP024_Msk (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos) /*!< GPIO_PORT CLR7: CLRP024 Mask */ -#define GPIO_PORT_CLR7_CLRP025_Pos 25 /*!< GPIO_PORT CLR7: CLRP025 Position */ -#define GPIO_PORT_CLR7_CLRP025_Msk (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos) /*!< GPIO_PORT CLR7: CLRP025 Mask */ -#define GPIO_PORT_CLR7_CLRP026_Pos 26 /*!< GPIO_PORT CLR7: CLRP026 Position */ -#define GPIO_PORT_CLR7_CLRP026_Msk (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos) /*!< GPIO_PORT CLR7: CLRP026 Mask */ -#define GPIO_PORT_CLR7_CLRP027_Pos 27 /*!< GPIO_PORT CLR7: CLRP027 Position */ -#define GPIO_PORT_CLR7_CLRP027_Msk (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos) /*!< GPIO_PORT CLR7: CLRP027 Mask */ -#define GPIO_PORT_CLR7_CLRP028_Pos 28 /*!< GPIO_PORT CLR7: CLRP028 Position */ -#define GPIO_PORT_CLR7_CLRP028_Msk (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos) /*!< GPIO_PORT CLR7: CLRP028 Mask */ -#define GPIO_PORT_CLR7_CLRP029_Pos 29 /*!< GPIO_PORT CLR7: CLRP029 Position */ -#define GPIO_PORT_CLR7_CLRP029_Msk (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos) /*!< GPIO_PORT CLR7: CLRP029 Mask */ -#define GPIO_PORT_CLR7_CLRP030_Pos 30 /*!< GPIO_PORT CLR7: CLRP030 Position */ -#define GPIO_PORT_CLR7_CLRP030_Msk (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos) /*!< GPIO_PORT CLR7: CLRP030 Mask */ -#define GPIO_PORT_CLR7_CLRP031_Pos 31 /*!< GPIO_PORT CLR7: CLRP031 Position */ -#define GPIO_PORT_CLR7_CLRP031_Msk (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos) /*!< GPIO_PORT CLR7: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_NOT0 ----------------------------------------- -#define GPIO_PORT_NOT0_NOTP0_Pos 0 /*!< GPIO_PORT NOT0: NOTP0 Position */ -#define GPIO_PORT_NOT0_NOTP0_Msk (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos) /*!< GPIO_PORT NOT0: NOTP0 Mask */ -#define GPIO_PORT_NOT0_NOTP1_Pos 1 /*!< GPIO_PORT NOT0: NOTP1 Position */ -#define GPIO_PORT_NOT0_NOTP1_Msk (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos) /*!< GPIO_PORT NOT0: NOTP1 Mask */ -#define GPIO_PORT_NOT0_NOTP2_Pos 2 /*!< GPIO_PORT NOT0: NOTP2 Position */ -#define GPIO_PORT_NOT0_NOTP2_Msk (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos) /*!< GPIO_PORT NOT0: NOTP2 Mask */ -#define GPIO_PORT_NOT0_NOTP3_Pos 3 /*!< GPIO_PORT NOT0: NOTP3 Position */ -#define GPIO_PORT_NOT0_NOTP3_Msk (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos) /*!< GPIO_PORT NOT0: NOTP3 Mask */ -#define GPIO_PORT_NOT0_NOTP4_Pos 4 /*!< GPIO_PORT NOT0: NOTP4 Position */ -#define GPIO_PORT_NOT0_NOTP4_Msk (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos) /*!< GPIO_PORT NOT0: NOTP4 Mask */ -#define GPIO_PORT_NOT0_NOTP5_Pos 5 /*!< GPIO_PORT NOT0: NOTP5 Position */ -#define GPIO_PORT_NOT0_NOTP5_Msk (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos) /*!< GPIO_PORT NOT0: NOTP5 Mask */ -#define GPIO_PORT_NOT0_NOTP6_Pos 6 /*!< GPIO_PORT NOT0: NOTP6 Position */ -#define GPIO_PORT_NOT0_NOTP6_Msk (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos) /*!< GPIO_PORT NOT0: NOTP6 Mask */ -#define GPIO_PORT_NOT0_NOTP7_Pos 7 /*!< GPIO_PORT NOT0: NOTP7 Position */ -#define GPIO_PORT_NOT0_NOTP7_Msk (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos) /*!< GPIO_PORT NOT0: NOTP7 Mask */ -#define GPIO_PORT_NOT0_NOTP8_Pos 8 /*!< GPIO_PORT NOT0: NOTP8 Position */ -#define GPIO_PORT_NOT0_NOTP8_Msk (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos) /*!< GPIO_PORT NOT0: NOTP8 Mask */ -#define GPIO_PORT_NOT0_NOTP9_Pos 9 /*!< GPIO_PORT NOT0: NOTP9 Position */ -#define GPIO_PORT_NOT0_NOTP9_Msk (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos) /*!< GPIO_PORT NOT0: NOTP9 Mask */ -#define GPIO_PORT_NOT0_NOTP10_Pos 10 /*!< GPIO_PORT NOT0: NOTP10 Position */ -#define GPIO_PORT_NOT0_NOTP10_Msk (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos) /*!< GPIO_PORT NOT0: NOTP10 Mask */ -#define GPIO_PORT_NOT0_NOTP11_Pos 11 /*!< GPIO_PORT NOT0: NOTP11 Position */ -#define GPIO_PORT_NOT0_NOTP11_Msk (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos) /*!< GPIO_PORT NOT0: NOTP11 Mask */ -#define GPIO_PORT_NOT0_NOTP12_Pos 12 /*!< GPIO_PORT NOT0: NOTP12 Position */ -#define GPIO_PORT_NOT0_NOTP12_Msk (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos) /*!< GPIO_PORT NOT0: NOTP12 Mask */ -#define GPIO_PORT_NOT0_NOTP13_Pos 13 /*!< GPIO_PORT NOT0: NOTP13 Position */ -#define GPIO_PORT_NOT0_NOTP13_Msk (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos) /*!< GPIO_PORT NOT0: NOTP13 Mask */ -#define GPIO_PORT_NOT0_NOTP14_Pos 14 /*!< GPIO_PORT NOT0: NOTP14 Position */ -#define GPIO_PORT_NOT0_NOTP14_Msk (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos) /*!< GPIO_PORT NOT0: NOTP14 Mask */ -#define GPIO_PORT_NOT0_NOTP15_Pos 15 /*!< GPIO_PORT NOT0: NOTP15 Position */ -#define GPIO_PORT_NOT0_NOTP15_Msk (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos) /*!< GPIO_PORT NOT0: NOTP15 Mask */ -#define GPIO_PORT_NOT0_NOTP16_Pos 16 /*!< GPIO_PORT NOT0: NOTP16 Position */ -#define GPIO_PORT_NOT0_NOTP16_Msk (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos) /*!< GPIO_PORT NOT0: NOTP16 Mask */ -#define GPIO_PORT_NOT0_NOTP17_Pos 17 /*!< GPIO_PORT NOT0: NOTP17 Position */ -#define GPIO_PORT_NOT0_NOTP17_Msk (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos) /*!< GPIO_PORT NOT0: NOTP17 Mask */ -#define GPIO_PORT_NOT0_NOTP18_Pos 18 /*!< GPIO_PORT NOT0: NOTP18 Position */ -#define GPIO_PORT_NOT0_NOTP18_Msk (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos) /*!< GPIO_PORT NOT0: NOTP18 Mask */ -#define GPIO_PORT_NOT0_NOTP19_Pos 19 /*!< GPIO_PORT NOT0: NOTP19 Position */ -#define GPIO_PORT_NOT0_NOTP19_Msk (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos) /*!< GPIO_PORT NOT0: NOTP19 Mask */ -#define GPIO_PORT_NOT0_NOTP20_Pos 20 /*!< GPIO_PORT NOT0: NOTP20 Position */ -#define GPIO_PORT_NOT0_NOTP20_Msk (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos) /*!< GPIO_PORT NOT0: NOTP20 Mask */ -#define GPIO_PORT_NOT0_NOTP21_Pos 21 /*!< GPIO_PORT NOT0: NOTP21 Position */ -#define GPIO_PORT_NOT0_NOTP21_Msk (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos) /*!< GPIO_PORT NOT0: NOTP21 Mask */ -#define GPIO_PORT_NOT0_NOTP22_Pos 22 /*!< GPIO_PORT NOT0: NOTP22 Position */ -#define GPIO_PORT_NOT0_NOTP22_Msk (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos) /*!< GPIO_PORT NOT0: NOTP22 Mask */ -#define GPIO_PORT_NOT0_NOTP23_Pos 23 /*!< GPIO_PORT NOT0: NOTP23 Position */ -#define GPIO_PORT_NOT0_NOTP23_Msk (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos) /*!< GPIO_PORT NOT0: NOTP23 Mask */ -#define GPIO_PORT_NOT0_NOTP24_Pos 24 /*!< GPIO_PORT NOT0: NOTP24 Position */ -#define GPIO_PORT_NOT0_NOTP24_Msk (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos) /*!< GPIO_PORT NOT0: NOTP24 Mask */ -#define GPIO_PORT_NOT0_NOTP25_Pos 25 /*!< GPIO_PORT NOT0: NOTP25 Position */ -#define GPIO_PORT_NOT0_NOTP25_Msk (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos) /*!< GPIO_PORT NOT0: NOTP25 Mask */ -#define GPIO_PORT_NOT0_NOTP26_Pos 26 /*!< GPIO_PORT NOT0: NOTP26 Position */ -#define GPIO_PORT_NOT0_NOTP26_Msk (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos) /*!< GPIO_PORT NOT0: NOTP26 Mask */ -#define GPIO_PORT_NOT0_NOTP27_Pos 27 /*!< GPIO_PORT NOT0: NOTP27 Position */ -#define GPIO_PORT_NOT0_NOTP27_Msk (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos) /*!< GPIO_PORT NOT0: NOTP27 Mask */ -#define GPIO_PORT_NOT0_NOTP28_Pos 28 /*!< GPIO_PORT NOT0: NOTP28 Position */ -#define GPIO_PORT_NOT0_NOTP28_Msk (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos) /*!< GPIO_PORT NOT0: NOTP28 Mask */ -#define GPIO_PORT_NOT0_NOTP29_Pos 29 /*!< GPIO_PORT NOT0: NOTP29 Position */ -#define GPIO_PORT_NOT0_NOTP29_Msk (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos) /*!< GPIO_PORT NOT0: NOTP29 Mask */ -#define GPIO_PORT_NOT0_NOTP30_Pos 30 /*!< GPIO_PORT NOT0: NOTP30 Position */ -#define GPIO_PORT_NOT0_NOTP30_Msk (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos) /*!< GPIO_PORT NOT0: NOTP30 Mask */ -#define GPIO_PORT_NOT0_NOTP31_Pos 31 /*!< GPIO_PORT NOT0: NOTP31 Position */ -#define GPIO_PORT_NOT0_NOTP31_Msk (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos) /*!< GPIO_PORT NOT0: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT1 ----------------------------------------- -#define GPIO_PORT_NOT1_NOTP0_Pos 0 /*!< GPIO_PORT NOT1: NOTP0 Position */ -#define GPIO_PORT_NOT1_NOTP0_Msk (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos) /*!< GPIO_PORT NOT1: NOTP0 Mask */ -#define GPIO_PORT_NOT1_NOTP1_Pos 1 /*!< GPIO_PORT NOT1: NOTP1 Position */ -#define GPIO_PORT_NOT1_NOTP1_Msk (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos) /*!< GPIO_PORT NOT1: NOTP1 Mask */ -#define GPIO_PORT_NOT1_NOTP2_Pos 2 /*!< GPIO_PORT NOT1: NOTP2 Position */ -#define GPIO_PORT_NOT1_NOTP2_Msk (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos) /*!< GPIO_PORT NOT1: NOTP2 Mask */ -#define GPIO_PORT_NOT1_NOTP3_Pos 3 /*!< GPIO_PORT NOT1: NOTP3 Position */ -#define GPIO_PORT_NOT1_NOTP3_Msk (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos) /*!< GPIO_PORT NOT1: NOTP3 Mask */ -#define GPIO_PORT_NOT1_NOTP4_Pos 4 /*!< GPIO_PORT NOT1: NOTP4 Position */ -#define GPIO_PORT_NOT1_NOTP4_Msk (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos) /*!< GPIO_PORT NOT1: NOTP4 Mask */ -#define GPIO_PORT_NOT1_NOTP5_Pos 5 /*!< GPIO_PORT NOT1: NOTP5 Position */ -#define GPIO_PORT_NOT1_NOTP5_Msk (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos) /*!< GPIO_PORT NOT1: NOTP5 Mask */ -#define GPIO_PORT_NOT1_NOTP6_Pos 6 /*!< GPIO_PORT NOT1: NOTP6 Position */ -#define GPIO_PORT_NOT1_NOTP6_Msk (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos) /*!< GPIO_PORT NOT1: NOTP6 Mask */ -#define GPIO_PORT_NOT1_NOTP7_Pos 7 /*!< GPIO_PORT NOT1: NOTP7 Position */ -#define GPIO_PORT_NOT1_NOTP7_Msk (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos) /*!< GPIO_PORT NOT1: NOTP7 Mask */ -#define GPIO_PORT_NOT1_NOTP8_Pos 8 /*!< GPIO_PORT NOT1: NOTP8 Position */ -#define GPIO_PORT_NOT1_NOTP8_Msk (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos) /*!< GPIO_PORT NOT1: NOTP8 Mask */ -#define GPIO_PORT_NOT1_NOTP9_Pos 9 /*!< GPIO_PORT NOT1: NOTP9 Position */ -#define GPIO_PORT_NOT1_NOTP9_Msk (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos) /*!< GPIO_PORT NOT1: NOTP9 Mask */ -#define GPIO_PORT_NOT1_NOTP10_Pos 10 /*!< GPIO_PORT NOT1: NOTP10 Position */ -#define GPIO_PORT_NOT1_NOTP10_Msk (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos) /*!< GPIO_PORT NOT1: NOTP10 Mask */ -#define GPIO_PORT_NOT1_NOTP11_Pos 11 /*!< GPIO_PORT NOT1: NOTP11 Position */ -#define GPIO_PORT_NOT1_NOTP11_Msk (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos) /*!< GPIO_PORT NOT1: NOTP11 Mask */ -#define GPIO_PORT_NOT1_NOTP12_Pos 12 /*!< GPIO_PORT NOT1: NOTP12 Position */ -#define GPIO_PORT_NOT1_NOTP12_Msk (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos) /*!< GPIO_PORT NOT1: NOTP12 Mask */ -#define GPIO_PORT_NOT1_NOTP13_Pos 13 /*!< GPIO_PORT NOT1: NOTP13 Position */ -#define GPIO_PORT_NOT1_NOTP13_Msk (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos) /*!< GPIO_PORT NOT1: NOTP13 Mask */ -#define GPIO_PORT_NOT1_NOTP14_Pos 14 /*!< GPIO_PORT NOT1: NOTP14 Position */ -#define GPIO_PORT_NOT1_NOTP14_Msk (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos) /*!< GPIO_PORT NOT1: NOTP14 Mask */ -#define GPIO_PORT_NOT1_NOTP15_Pos 15 /*!< GPIO_PORT NOT1: NOTP15 Position */ -#define GPIO_PORT_NOT1_NOTP15_Msk (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos) /*!< GPIO_PORT NOT1: NOTP15 Mask */ -#define GPIO_PORT_NOT1_NOTP16_Pos 16 /*!< GPIO_PORT NOT1: NOTP16 Position */ -#define GPIO_PORT_NOT1_NOTP16_Msk (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos) /*!< GPIO_PORT NOT1: NOTP16 Mask */ -#define GPIO_PORT_NOT1_NOTP17_Pos 17 /*!< GPIO_PORT NOT1: NOTP17 Position */ -#define GPIO_PORT_NOT1_NOTP17_Msk (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos) /*!< GPIO_PORT NOT1: NOTP17 Mask */ -#define GPIO_PORT_NOT1_NOTP18_Pos 18 /*!< GPIO_PORT NOT1: NOTP18 Position */ -#define GPIO_PORT_NOT1_NOTP18_Msk (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos) /*!< GPIO_PORT NOT1: NOTP18 Mask */ -#define GPIO_PORT_NOT1_NOTP19_Pos 19 /*!< GPIO_PORT NOT1: NOTP19 Position */ -#define GPIO_PORT_NOT1_NOTP19_Msk (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos) /*!< GPIO_PORT NOT1: NOTP19 Mask */ -#define GPIO_PORT_NOT1_NOTP20_Pos 20 /*!< GPIO_PORT NOT1: NOTP20 Position */ -#define GPIO_PORT_NOT1_NOTP20_Msk (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos) /*!< GPIO_PORT NOT1: NOTP20 Mask */ -#define GPIO_PORT_NOT1_NOTP21_Pos 21 /*!< GPIO_PORT NOT1: NOTP21 Position */ -#define GPIO_PORT_NOT1_NOTP21_Msk (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos) /*!< GPIO_PORT NOT1: NOTP21 Mask */ -#define GPIO_PORT_NOT1_NOTP22_Pos 22 /*!< GPIO_PORT NOT1: NOTP22 Position */ -#define GPIO_PORT_NOT1_NOTP22_Msk (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos) /*!< GPIO_PORT NOT1: NOTP22 Mask */ -#define GPIO_PORT_NOT1_NOTP23_Pos 23 /*!< GPIO_PORT NOT1: NOTP23 Position */ -#define GPIO_PORT_NOT1_NOTP23_Msk (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos) /*!< GPIO_PORT NOT1: NOTP23 Mask */ -#define GPIO_PORT_NOT1_NOTP24_Pos 24 /*!< GPIO_PORT NOT1: NOTP24 Position */ -#define GPIO_PORT_NOT1_NOTP24_Msk (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos) /*!< GPIO_PORT NOT1: NOTP24 Mask */ -#define GPIO_PORT_NOT1_NOTP25_Pos 25 /*!< GPIO_PORT NOT1: NOTP25 Position */ -#define GPIO_PORT_NOT1_NOTP25_Msk (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos) /*!< GPIO_PORT NOT1: NOTP25 Mask */ -#define GPIO_PORT_NOT1_NOTP26_Pos 26 /*!< GPIO_PORT NOT1: NOTP26 Position */ -#define GPIO_PORT_NOT1_NOTP26_Msk (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos) /*!< GPIO_PORT NOT1: NOTP26 Mask */ -#define GPIO_PORT_NOT1_NOTP27_Pos 27 /*!< GPIO_PORT NOT1: NOTP27 Position */ -#define GPIO_PORT_NOT1_NOTP27_Msk (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos) /*!< GPIO_PORT NOT1: NOTP27 Mask */ -#define GPIO_PORT_NOT1_NOTP28_Pos 28 /*!< GPIO_PORT NOT1: NOTP28 Position */ -#define GPIO_PORT_NOT1_NOTP28_Msk (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos) /*!< GPIO_PORT NOT1: NOTP28 Mask */ -#define GPIO_PORT_NOT1_NOTP29_Pos 29 /*!< GPIO_PORT NOT1: NOTP29 Position */ -#define GPIO_PORT_NOT1_NOTP29_Msk (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos) /*!< GPIO_PORT NOT1: NOTP29 Mask */ -#define GPIO_PORT_NOT1_NOTP30_Pos 30 /*!< GPIO_PORT NOT1: NOTP30 Position */ -#define GPIO_PORT_NOT1_NOTP30_Msk (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos) /*!< GPIO_PORT NOT1: NOTP30 Mask */ -#define GPIO_PORT_NOT1_NOTP31_Pos 31 /*!< GPIO_PORT NOT1: NOTP31 Position */ -#define GPIO_PORT_NOT1_NOTP31_Msk (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos) /*!< GPIO_PORT NOT1: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT2 ----------------------------------------- -#define GPIO_PORT_NOT2_NOTP0_Pos 0 /*!< GPIO_PORT NOT2: NOTP0 Position */ -#define GPIO_PORT_NOT2_NOTP0_Msk (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos) /*!< GPIO_PORT NOT2: NOTP0 Mask */ -#define GPIO_PORT_NOT2_NOTP1_Pos 1 /*!< GPIO_PORT NOT2: NOTP1 Position */ -#define GPIO_PORT_NOT2_NOTP1_Msk (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos) /*!< GPIO_PORT NOT2: NOTP1 Mask */ -#define GPIO_PORT_NOT2_NOTP2_Pos 2 /*!< GPIO_PORT NOT2: NOTP2 Position */ -#define GPIO_PORT_NOT2_NOTP2_Msk (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos) /*!< GPIO_PORT NOT2: NOTP2 Mask */ -#define GPIO_PORT_NOT2_NOTP3_Pos 3 /*!< GPIO_PORT NOT2: NOTP3 Position */ -#define GPIO_PORT_NOT2_NOTP3_Msk (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos) /*!< GPIO_PORT NOT2: NOTP3 Mask */ -#define GPIO_PORT_NOT2_NOTP4_Pos 4 /*!< GPIO_PORT NOT2: NOTP4 Position */ -#define GPIO_PORT_NOT2_NOTP4_Msk (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos) /*!< GPIO_PORT NOT2: NOTP4 Mask */ -#define GPIO_PORT_NOT2_NOTP5_Pos 5 /*!< GPIO_PORT NOT2: NOTP5 Position */ -#define GPIO_PORT_NOT2_NOTP5_Msk (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos) /*!< GPIO_PORT NOT2: NOTP5 Mask */ -#define GPIO_PORT_NOT2_NOTP6_Pos 6 /*!< GPIO_PORT NOT2: NOTP6 Position */ -#define GPIO_PORT_NOT2_NOTP6_Msk (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos) /*!< GPIO_PORT NOT2: NOTP6 Mask */ -#define GPIO_PORT_NOT2_NOTP7_Pos 7 /*!< GPIO_PORT NOT2: NOTP7 Position */ -#define GPIO_PORT_NOT2_NOTP7_Msk (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos) /*!< GPIO_PORT NOT2: NOTP7 Mask */ -#define GPIO_PORT_NOT2_NOTP8_Pos 8 /*!< GPIO_PORT NOT2: NOTP8 Position */ -#define GPIO_PORT_NOT2_NOTP8_Msk (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos) /*!< GPIO_PORT NOT2: NOTP8 Mask */ -#define GPIO_PORT_NOT2_NOTP9_Pos 9 /*!< GPIO_PORT NOT2: NOTP9 Position */ -#define GPIO_PORT_NOT2_NOTP9_Msk (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos) /*!< GPIO_PORT NOT2: NOTP9 Mask */ -#define GPIO_PORT_NOT2_NOTP10_Pos 10 /*!< GPIO_PORT NOT2: NOTP10 Position */ -#define GPIO_PORT_NOT2_NOTP10_Msk (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos) /*!< GPIO_PORT NOT2: NOTP10 Mask */ -#define GPIO_PORT_NOT2_NOTP11_Pos 11 /*!< GPIO_PORT NOT2: NOTP11 Position */ -#define GPIO_PORT_NOT2_NOTP11_Msk (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos) /*!< GPIO_PORT NOT2: NOTP11 Mask */ -#define GPIO_PORT_NOT2_NOTP12_Pos 12 /*!< GPIO_PORT NOT2: NOTP12 Position */ -#define GPIO_PORT_NOT2_NOTP12_Msk (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos) /*!< GPIO_PORT NOT2: NOTP12 Mask */ -#define GPIO_PORT_NOT2_NOTP13_Pos 13 /*!< GPIO_PORT NOT2: NOTP13 Position */ -#define GPIO_PORT_NOT2_NOTP13_Msk (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos) /*!< GPIO_PORT NOT2: NOTP13 Mask */ -#define GPIO_PORT_NOT2_NOTP14_Pos 14 /*!< GPIO_PORT NOT2: NOTP14 Position */ -#define GPIO_PORT_NOT2_NOTP14_Msk (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos) /*!< GPIO_PORT NOT2: NOTP14 Mask */ -#define GPIO_PORT_NOT2_NOTP15_Pos 15 /*!< GPIO_PORT NOT2: NOTP15 Position */ -#define GPIO_PORT_NOT2_NOTP15_Msk (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos) /*!< GPIO_PORT NOT2: NOTP15 Mask */ -#define GPIO_PORT_NOT2_NOTP16_Pos 16 /*!< GPIO_PORT NOT2: NOTP16 Position */ -#define GPIO_PORT_NOT2_NOTP16_Msk (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos) /*!< GPIO_PORT NOT2: NOTP16 Mask */ -#define GPIO_PORT_NOT2_NOTP17_Pos 17 /*!< GPIO_PORT NOT2: NOTP17 Position */ -#define GPIO_PORT_NOT2_NOTP17_Msk (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos) /*!< GPIO_PORT NOT2: NOTP17 Mask */ -#define GPIO_PORT_NOT2_NOTP18_Pos 18 /*!< GPIO_PORT NOT2: NOTP18 Position */ -#define GPIO_PORT_NOT2_NOTP18_Msk (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos) /*!< GPIO_PORT NOT2: NOTP18 Mask */ -#define GPIO_PORT_NOT2_NOTP19_Pos 19 /*!< GPIO_PORT NOT2: NOTP19 Position */ -#define GPIO_PORT_NOT2_NOTP19_Msk (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos) /*!< GPIO_PORT NOT2: NOTP19 Mask */ -#define GPIO_PORT_NOT2_NOTP20_Pos 20 /*!< GPIO_PORT NOT2: NOTP20 Position */ -#define GPIO_PORT_NOT2_NOTP20_Msk (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos) /*!< GPIO_PORT NOT2: NOTP20 Mask */ -#define GPIO_PORT_NOT2_NOTP21_Pos 21 /*!< GPIO_PORT NOT2: NOTP21 Position */ -#define GPIO_PORT_NOT2_NOTP21_Msk (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos) /*!< GPIO_PORT NOT2: NOTP21 Mask */ -#define GPIO_PORT_NOT2_NOTP22_Pos 22 /*!< GPIO_PORT NOT2: NOTP22 Position */ -#define GPIO_PORT_NOT2_NOTP22_Msk (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos) /*!< GPIO_PORT NOT2: NOTP22 Mask */ -#define GPIO_PORT_NOT2_NOTP23_Pos 23 /*!< GPIO_PORT NOT2: NOTP23 Position */ -#define GPIO_PORT_NOT2_NOTP23_Msk (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos) /*!< GPIO_PORT NOT2: NOTP23 Mask */ -#define GPIO_PORT_NOT2_NOTP24_Pos 24 /*!< GPIO_PORT NOT2: NOTP24 Position */ -#define GPIO_PORT_NOT2_NOTP24_Msk (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos) /*!< GPIO_PORT NOT2: NOTP24 Mask */ -#define GPIO_PORT_NOT2_NOTP25_Pos 25 /*!< GPIO_PORT NOT2: NOTP25 Position */ -#define GPIO_PORT_NOT2_NOTP25_Msk (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos) /*!< GPIO_PORT NOT2: NOTP25 Mask */ -#define GPIO_PORT_NOT2_NOTP26_Pos 26 /*!< GPIO_PORT NOT2: NOTP26 Position */ -#define GPIO_PORT_NOT2_NOTP26_Msk (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos) /*!< GPIO_PORT NOT2: NOTP26 Mask */ -#define GPIO_PORT_NOT2_NOTP27_Pos 27 /*!< GPIO_PORT NOT2: NOTP27 Position */ -#define GPIO_PORT_NOT2_NOTP27_Msk (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos) /*!< GPIO_PORT NOT2: NOTP27 Mask */ -#define GPIO_PORT_NOT2_NOTP28_Pos 28 /*!< GPIO_PORT NOT2: NOTP28 Position */ -#define GPIO_PORT_NOT2_NOTP28_Msk (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos) /*!< GPIO_PORT NOT2: NOTP28 Mask */ -#define GPIO_PORT_NOT2_NOTP29_Pos 29 /*!< GPIO_PORT NOT2: NOTP29 Position */ -#define GPIO_PORT_NOT2_NOTP29_Msk (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos) /*!< GPIO_PORT NOT2: NOTP29 Mask */ -#define GPIO_PORT_NOT2_NOTP30_Pos 30 /*!< GPIO_PORT NOT2: NOTP30 Position */ -#define GPIO_PORT_NOT2_NOTP30_Msk (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos) /*!< GPIO_PORT NOT2: NOTP30 Mask */ -#define GPIO_PORT_NOT2_NOTP31_Pos 31 /*!< GPIO_PORT NOT2: NOTP31 Position */ -#define GPIO_PORT_NOT2_NOTP31_Msk (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos) /*!< GPIO_PORT NOT2: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT3 ----------------------------------------- -#define GPIO_PORT_NOT3_NOTP0_Pos 0 /*!< GPIO_PORT NOT3: NOTP0 Position */ -#define GPIO_PORT_NOT3_NOTP0_Msk (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos) /*!< GPIO_PORT NOT3: NOTP0 Mask */ -#define GPIO_PORT_NOT3_NOTP1_Pos 1 /*!< GPIO_PORT NOT3: NOTP1 Position */ -#define GPIO_PORT_NOT3_NOTP1_Msk (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos) /*!< GPIO_PORT NOT3: NOTP1 Mask */ -#define GPIO_PORT_NOT3_NOTP2_Pos 2 /*!< GPIO_PORT NOT3: NOTP2 Position */ -#define GPIO_PORT_NOT3_NOTP2_Msk (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos) /*!< GPIO_PORT NOT3: NOTP2 Mask */ -#define GPIO_PORT_NOT3_NOTP3_Pos 3 /*!< GPIO_PORT NOT3: NOTP3 Position */ -#define GPIO_PORT_NOT3_NOTP3_Msk (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos) /*!< GPIO_PORT NOT3: NOTP3 Mask */ -#define GPIO_PORT_NOT3_NOTP4_Pos 4 /*!< GPIO_PORT NOT3: NOTP4 Position */ -#define GPIO_PORT_NOT3_NOTP4_Msk (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos) /*!< GPIO_PORT NOT3: NOTP4 Mask */ -#define GPIO_PORT_NOT3_NOTP5_Pos 5 /*!< GPIO_PORT NOT3: NOTP5 Position */ -#define GPIO_PORT_NOT3_NOTP5_Msk (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos) /*!< GPIO_PORT NOT3: NOTP5 Mask */ -#define GPIO_PORT_NOT3_NOTP6_Pos 6 /*!< GPIO_PORT NOT3: NOTP6 Position */ -#define GPIO_PORT_NOT3_NOTP6_Msk (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos) /*!< GPIO_PORT NOT3: NOTP6 Mask */ -#define GPIO_PORT_NOT3_NOTP7_Pos 7 /*!< GPIO_PORT NOT3: NOTP7 Position */ -#define GPIO_PORT_NOT3_NOTP7_Msk (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos) /*!< GPIO_PORT NOT3: NOTP7 Mask */ -#define GPIO_PORT_NOT3_NOTP8_Pos 8 /*!< GPIO_PORT NOT3: NOTP8 Position */ -#define GPIO_PORT_NOT3_NOTP8_Msk (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos) /*!< GPIO_PORT NOT3: NOTP8 Mask */ -#define GPIO_PORT_NOT3_NOTP9_Pos 9 /*!< GPIO_PORT NOT3: NOTP9 Position */ -#define GPIO_PORT_NOT3_NOTP9_Msk (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos) /*!< GPIO_PORT NOT3: NOTP9 Mask */ -#define GPIO_PORT_NOT3_NOTP10_Pos 10 /*!< GPIO_PORT NOT3: NOTP10 Position */ -#define GPIO_PORT_NOT3_NOTP10_Msk (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos) /*!< GPIO_PORT NOT3: NOTP10 Mask */ -#define GPIO_PORT_NOT3_NOTP11_Pos 11 /*!< GPIO_PORT NOT3: NOTP11 Position */ -#define GPIO_PORT_NOT3_NOTP11_Msk (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos) /*!< GPIO_PORT NOT3: NOTP11 Mask */ -#define GPIO_PORT_NOT3_NOTP12_Pos 12 /*!< GPIO_PORT NOT3: NOTP12 Position */ -#define GPIO_PORT_NOT3_NOTP12_Msk (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos) /*!< GPIO_PORT NOT3: NOTP12 Mask */ -#define GPIO_PORT_NOT3_NOTP13_Pos 13 /*!< GPIO_PORT NOT3: NOTP13 Position */ -#define GPIO_PORT_NOT3_NOTP13_Msk (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos) /*!< GPIO_PORT NOT3: NOTP13 Mask */ -#define GPIO_PORT_NOT3_NOTP14_Pos 14 /*!< GPIO_PORT NOT3: NOTP14 Position */ -#define GPIO_PORT_NOT3_NOTP14_Msk (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos) /*!< GPIO_PORT NOT3: NOTP14 Mask */ -#define GPIO_PORT_NOT3_NOTP15_Pos 15 /*!< GPIO_PORT NOT3: NOTP15 Position */ -#define GPIO_PORT_NOT3_NOTP15_Msk (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos) /*!< GPIO_PORT NOT3: NOTP15 Mask */ -#define GPIO_PORT_NOT3_NOTP16_Pos 16 /*!< GPIO_PORT NOT3: NOTP16 Position */ -#define GPIO_PORT_NOT3_NOTP16_Msk (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos) /*!< GPIO_PORT NOT3: NOTP16 Mask */ -#define GPIO_PORT_NOT3_NOTP17_Pos 17 /*!< GPIO_PORT NOT3: NOTP17 Position */ -#define GPIO_PORT_NOT3_NOTP17_Msk (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos) /*!< GPIO_PORT NOT3: NOTP17 Mask */ -#define GPIO_PORT_NOT3_NOTP18_Pos 18 /*!< GPIO_PORT NOT3: NOTP18 Position */ -#define GPIO_PORT_NOT3_NOTP18_Msk (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos) /*!< GPIO_PORT NOT3: NOTP18 Mask */ -#define GPIO_PORT_NOT3_NOTP19_Pos 19 /*!< GPIO_PORT NOT3: NOTP19 Position */ -#define GPIO_PORT_NOT3_NOTP19_Msk (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos) /*!< GPIO_PORT NOT3: NOTP19 Mask */ -#define GPIO_PORT_NOT3_NOTP20_Pos 20 /*!< GPIO_PORT NOT3: NOTP20 Position */ -#define GPIO_PORT_NOT3_NOTP20_Msk (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos) /*!< GPIO_PORT NOT3: NOTP20 Mask */ -#define GPIO_PORT_NOT3_NOTP21_Pos 21 /*!< GPIO_PORT NOT3: NOTP21 Position */ -#define GPIO_PORT_NOT3_NOTP21_Msk (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos) /*!< GPIO_PORT NOT3: NOTP21 Mask */ -#define GPIO_PORT_NOT3_NOTP22_Pos 22 /*!< GPIO_PORT NOT3: NOTP22 Position */ -#define GPIO_PORT_NOT3_NOTP22_Msk (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos) /*!< GPIO_PORT NOT3: NOTP22 Mask */ -#define GPIO_PORT_NOT3_NOTP23_Pos 23 /*!< GPIO_PORT NOT3: NOTP23 Position */ -#define GPIO_PORT_NOT3_NOTP23_Msk (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos) /*!< GPIO_PORT NOT3: NOTP23 Mask */ -#define GPIO_PORT_NOT3_NOTP24_Pos 24 /*!< GPIO_PORT NOT3: NOTP24 Position */ -#define GPIO_PORT_NOT3_NOTP24_Msk (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos) /*!< GPIO_PORT NOT3: NOTP24 Mask */ -#define GPIO_PORT_NOT3_NOTP25_Pos 25 /*!< GPIO_PORT NOT3: NOTP25 Position */ -#define GPIO_PORT_NOT3_NOTP25_Msk (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos) /*!< GPIO_PORT NOT3: NOTP25 Mask */ -#define GPIO_PORT_NOT3_NOTP26_Pos 26 /*!< GPIO_PORT NOT3: NOTP26 Position */ -#define GPIO_PORT_NOT3_NOTP26_Msk (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos) /*!< GPIO_PORT NOT3: NOTP26 Mask */ -#define GPIO_PORT_NOT3_NOTP27_Pos 27 /*!< GPIO_PORT NOT3: NOTP27 Position */ -#define GPIO_PORT_NOT3_NOTP27_Msk (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos) /*!< GPIO_PORT NOT3: NOTP27 Mask */ -#define GPIO_PORT_NOT3_NOTP28_Pos 28 /*!< GPIO_PORT NOT3: NOTP28 Position */ -#define GPIO_PORT_NOT3_NOTP28_Msk (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos) /*!< GPIO_PORT NOT3: NOTP28 Mask */ -#define GPIO_PORT_NOT3_NOTP29_Pos 29 /*!< GPIO_PORT NOT3: NOTP29 Position */ -#define GPIO_PORT_NOT3_NOTP29_Msk (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos) /*!< GPIO_PORT NOT3: NOTP29 Mask */ -#define GPIO_PORT_NOT3_NOTP30_Pos 30 /*!< GPIO_PORT NOT3: NOTP30 Position */ -#define GPIO_PORT_NOT3_NOTP30_Msk (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos) /*!< GPIO_PORT NOT3: NOTP30 Mask */ -#define GPIO_PORT_NOT3_NOTP31_Pos 31 /*!< GPIO_PORT NOT3: NOTP31 Position */ -#define GPIO_PORT_NOT3_NOTP31_Msk (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos) /*!< GPIO_PORT NOT3: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT4 ----------------------------------------- -#define GPIO_PORT_NOT4_NOTP0_Pos 0 /*!< GPIO_PORT NOT4: NOTP0 Position */ -#define GPIO_PORT_NOT4_NOTP0_Msk (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos) /*!< GPIO_PORT NOT4: NOTP0 Mask */ -#define GPIO_PORT_NOT4_NOTP1_Pos 1 /*!< GPIO_PORT NOT4: NOTP1 Position */ -#define GPIO_PORT_NOT4_NOTP1_Msk (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos) /*!< GPIO_PORT NOT4: NOTP1 Mask */ -#define GPIO_PORT_NOT4_NOTP2_Pos 2 /*!< GPIO_PORT NOT4: NOTP2 Position */ -#define GPIO_PORT_NOT4_NOTP2_Msk (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos) /*!< GPIO_PORT NOT4: NOTP2 Mask */ -#define GPIO_PORT_NOT4_NOTP3_Pos 3 /*!< GPIO_PORT NOT4: NOTP3 Position */ -#define GPIO_PORT_NOT4_NOTP3_Msk (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos) /*!< GPIO_PORT NOT4: NOTP3 Mask */ -#define GPIO_PORT_NOT4_NOTP4_Pos 4 /*!< GPIO_PORT NOT4: NOTP4 Position */ -#define GPIO_PORT_NOT4_NOTP4_Msk (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos) /*!< GPIO_PORT NOT4: NOTP4 Mask */ -#define GPIO_PORT_NOT4_NOTP5_Pos 5 /*!< GPIO_PORT NOT4: NOTP5 Position */ -#define GPIO_PORT_NOT4_NOTP5_Msk (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos) /*!< GPIO_PORT NOT4: NOTP5 Mask */ -#define GPIO_PORT_NOT4_NOTP6_Pos 6 /*!< GPIO_PORT NOT4: NOTP6 Position */ -#define GPIO_PORT_NOT4_NOTP6_Msk (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos) /*!< GPIO_PORT NOT4: NOTP6 Mask */ -#define GPIO_PORT_NOT4_NOTP7_Pos 7 /*!< GPIO_PORT NOT4: NOTP7 Position */ -#define GPIO_PORT_NOT4_NOTP7_Msk (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos) /*!< GPIO_PORT NOT4: NOTP7 Mask */ -#define GPIO_PORT_NOT4_NOTP8_Pos 8 /*!< GPIO_PORT NOT4: NOTP8 Position */ -#define GPIO_PORT_NOT4_NOTP8_Msk (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos) /*!< GPIO_PORT NOT4: NOTP8 Mask */ -#define GPIO_PORT_NOT4_NOTP9_Pos 9 /*!< GPIO_PORT NOT4: NOTP9 Position */ -#define GPIO_PORT_NOT4_NOTP9_Msk (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos) /*!< GPIO_PORT NOT4: NOTP9 Mask */ -#define GPIO_PORT_NOT4_NOTP10_Pos 10 /*!< GPIO_PORT NOT4: NOTP10 Position */ -#define GPIO_PORT_NOT4_NOTP10_Msk (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos) /*!< GPIO_PORT NOT4: NOTP10 Mask */ -#define GPIO_PORT_NOT4_NOTP11_Pos 11 /*!< GPIO_PORT NOT4: NOTP11 Position */ -#define GPIO_PORT_NOT4_NOTP11_Msk (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos) /*!< GPIO_PORT NOT4: NOTP11 Mask */ -#define GPIO_PORT_NOT4_NOTP12_Pos 12 /*!< GPIO_PORT NOT4: NOTP12 Position */ -#define GPIO_PORT_NOT4_NOTP12_Msk (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos) /*!< GPIO_PORT NOT4: NOTP12 Mask */ -#define GPIO_PORT_NOT4_NOTP13_Pos 13 /*!< GPIO_PORT NOT4: NOTP13 Position */ -#define GPIO_PORT_NOT4_NOTP13_Msk (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos) /*!< GPIO_PORT NOT4: NOTP13 Mask */ -#define GPIO_PORT_NOT4_NOTP14_Pos 14 /*!< GPIO_PORT NOT4: NOTP14 Position */ -#define GPIO_PORT_NOT4_NOTP14_Msk (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos) /*!< GPIO_PORT NOT4: NOTP14 Mask */ -#define GPIO_PORT_NOT4_NOTP15_Pos 15 /*!< GPIO_PORT NOT4: NOTP15 Position */ -#define GPIO_PORT_NOT4_NOTP15_Msk (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos) /*!< GPIO_PORT NOT4: NOTP15 Mask */ -#define GPIO_PORT_NOT4_NOTP16_Pos 16 /*!< GPIO_PORT NOT4: NOTP16 Position */ -#define GPIO_PORT_NOT4_NOTP16_Msk (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos) /*!< GPIO_PORT NOT4: NOTP16 Mask */ -#define GPIO_PORT_NOT4_NOTP17_Pos 17 /*!< GPIO_PORT NOT4: NOTP17 Position */ -#define GPIO_PORT_NOT4_NOTP17_Msk (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos) /*!< GPIO_PORT NOT4: NOTP17 Mask */ -#define GPIO_PORT_NOT4_NOTP18_Pos 18 /*!< GPIO_PORT NOT4: NOTP18 Position */ -#define GPIO_PORT_NOT4_NOTP18_Msk (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos) /*!< GPIO_PORT NOT4: NOTP18 Mask */ -#define GPIO_PORT_NOT4_NOTP19_Pos 19 /*!< GPIO_PORT NOT4: NOTP19 Position */ -#define GPIO_PORT_NOT4_NOTP19_Msk (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos) /*!< GPIO_PORT NOT4: NOTP19 Mask */ -#define GPIO_PORT_NOT4_NOTP20_Pos 20 /*!< GPIO_PORT NOT4: NOTP20 Position */ -#define GPIO_PORT_NOT4_NOTP20_Msk (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos) /*!< GPIO_PORT NOT4: NOTP20 Mask */ -#define GPIO_PORT_NOT4_NOTP21_Pos 21 /*!< GPIO_PORT NOT4: NOTP21 Position */ -#define GPIO_PORT_NOT4_NOTP21_Msk (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos) /*!< GPIO_PORT NOT4: NOTP21 Mask */ -#define GPIO_PORT_NOT4_NOTP22_Pos 22 /*!< GPIO_PORT NOT4: NOTP22 Position */ -#define GPIO_PORT_NOT4_NOTP22_Msk (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos) /*!< GPIO_PORT NOT4: NOTP22 Mask */ -#define GPIO_PORT_NOT4_NOTP23_Pos 23 /*!< GPIO_PORT NOT4: NOTP23 Position */ -#define GPIO_PORT_NOT4_NOTP23_Msk (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos) /*!< GPIO_PORT NOT4: NOTP23 Mask */ -#define GPIO_PORT_NOT4_NOTP24_Pos 24 /*!< GPIO_PORT NOT4: NOTP24 Position */ -#define GPIO_PORT_NOT4_NOTP24_Msk (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos) /*!< GPIO_PORT NOT4: NOTP24 Mask */ -#define GPIO_PORT_NOT4_NOTP25_Pos 25 /*!< GPIO_PORT NOT4: NOTP25 Position */ -#define GPIO_PORT_NOT4_NOTP25_Msk (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos) /*!< GPIO_PORT NOT4: NOTP25 Mask */ -#define GPIO_PORT_NOT4_NOTP26_Pos 26 /*!< GPIO_PORT NOT4: NOTP26 Position */ -#define GPIO_PORT_NOT4_NOTP26_Msk (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos) /*!< GPIO_PORT NOT4: NOTP26 Mask */ -#define GPIO_PORT_NOT4_NOTP27_Pos 27 /*!< GPIO_PORT NOT4: NOTP27 Position */ -#define GPIO_PORT_NOT4_NOTP27_Msk (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos) /*!< GPIO_PORT NOT4: NOTP27 Mask */ -#define GPIO_PORT_NOT4_NOTP28_Pos 28 /*!< GPIO_PORT NOT4: NOTP28 Position */ -#define GPIO_PORT_NOT4_NOTP28_Msk (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos) /*!< GPIO_PORT NOT4: NOTP28 Mask */ -#define GPIO_PORT_NOT4_NOTP29_Pos 29 /*!< GPIO_PORT NOT4: NOTP29 Position */ -#define GPIO_PORT_NOT4_NOTP29_Msk (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos) /*!< GPIO_PORT NOT4: NOTP29 Mask */ -#define GPIO_PORT_NOT4_NOTP30_Pos 30 /*!< GPIO_PORT NOT4: NOTP30 Position */ -#define GPIO_PORT_NOT4_NOTP30_Msk (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos) /*!< GPIO_PORT NOT4: NOTP30 Mask */ -#define GPIO_PORT_NOT4_NOTP31_Pos 31 /*!< GPIO_PORT NOT4: NOTP31 Position */ -#define GPIO_PORT_NOT4_NOTP31_Msk (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos) /*!< GPIO_PORT NOT4: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT5 ----------------------------------------- -#define GPIO_PORT_NOT5_NOTP0_Pos 0 /*!< GPIO_PORT NOT5: NOTP0 Position */ -#define GPIO_PORT_NOT5_NOTP0_Msk (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos) /*!< GPIO_PORT NOT5: NOTP0 Mask */ -#define GPIO_PORT_NOT5_NOTP1_Pos 1 /*!< GPIO_PORT NOT5: NOTP1 Position */ -#define GPIO_PORT_NOT5_NOTP1_Msk (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos) /*!< GPIO_PORT NOT5: NOTP1 Mask */ -#define GPIO_PORT_NOT5_NOTP2_Pos 2 /*!< GPIO_PORT NOT5: NOTP2 Position */ -#define GPIO_PORT_NOT5_NOTP2_Msk (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos) /*!< GPIO_PORT NOT5: NOTP2 Mask */ -#define GPIO_PORT_NOT5_NOTP3_Pos 3 /*!< GPIO_PORT NOT5: NOTP3 Position */ -#define GPIO_PORT_NOT5_NOTP3_Msk (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos) /*!< GPIO_PORT NOT5: NOTP3 Mask */ -#define GPIO_PORT_NOT5_NOTP4_Pos 4 /*!< GPIO_PORT NOT5: NOTP4 Position */ -#define GPIO_PORT_NOT5_NOTP4_Msk (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos) /*!< GPIO_PORT NOT5: NOTP4 Mask */ -#define GPIO_PORT_NOT5_NOTP5_Pos 5 /*!< GPIO_PORT NOT5: NOTP5 Position */ -#define GPIO_PORT_NOT5_NOTP5_Msk (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos) /*!< GPIO_PORT NOT5: NOTP5 Mask */ -#define GPIO_PORT_NOT5_NOTP6_Pos 6 /*!< GPIO_PORT NOT5: NOTP6 Position */ -#define GPIO_PORT_NOT5_NOTP6_Msk (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos) /*!< GPIO_PORT NOT5: NOTP6 Mask */ -#define GPIO_PORT_NOT5_NOTP7_Pos 7 /*!< GPIO_PORT NOT5: NOTP7 Position */ -#define GPIO_PORT_NOT5_NOTP7_Msk (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos) /*!< GPIO_PORT NOT5: NOTP7 Mask */ -#define GPIO_PORT_NOT5_NOTP8_Pos 8 /*!< GPIO_PORT NOT5: NOTP8 Position */ -#define GPIO_PORT_NOT5_NOTP8_Msk (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos) /*!< GPIO_PORT NOT5: NOTP8 Mask */ -#define GPIO_PORT_NOT5_NOTP9_Pos 9 /*!< GPIO_PORT NOT5: NOTP9 Position */ -#define GPIO_PORT_NOT5_NOTP9_Msk (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos) /*!< GPIO_PORT NOT5: NOTP9 Mask */ -#define GPIO_PORT_NOT5_NOTP10_Pos 10 /*!< GPIO_PORT NOT5: NOTP10 Position */ -#define GPIO_PORT_NOT5_NOTP10_Msk (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos) /*!< GPIO_PORT NOT5: NOTP10 Mask */ -#define GPIO_PORT_NOT5_NOTP11_Pos 11 /*!< GPIO_PORT NOT5: NOTP11 Position */ -#define GPIO_PORT_NOT5_NOTP11_Msk (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos) /*!< GPIO_PORT NOT5: NOTP11 Mask */ -#define GPIO_PORT_NOT5_NOTP12_Pos 12 /*!< GPIO_PORT NOT5: NOTP12 Position */ -#define GPIO_PORT_NOT5_NOTP12_Msk (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos) /*!< GPIO_PORT NOT5: NOTP12 Mask */ -#define GPIO_PORT_NOT5_NOTP13_Pos 13 /*!< GPIO_PORT NOT5: NOTP13 Position */ -#define GPIO_PORT_NOT5_NOTP13_Msk (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos) /*!< GPIO_PORT NOT5: NOTP13 Mask */ -#define GPIO_PORT_NOT5_NOTP14_Pos 14 /*!< GPIO_PORT NOT5: NOTP14 Position */ -#define GPIO_PORT_NOT5_NOTP14_Msk (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos) /*!< GPIO_PORT NOT5: NOTP14 Mask */ -#define GPIO_PORT_NOT5_NOTP15_Pos 15 /*!< GPIO_PORT NOT5: NOTP15 Position */ -#define GPIO_PORT_NOT5_NOTP15_Msk (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos) /*!< GPIO_PORT NOT5: NOTP15 Mask */ -#define GPIO_PORT_NOT5_NOTP16_Pos 16 /*!< GPIO_PORT NOT5: NOTP16 Position */ -#define GPIO_PORT_NOT5_NOTP16_Msk (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos) /*!< GPIO_PORT NOT5: NOTP16 Mask */ -#define GPIO_PORT_NOT5_NOTP17_Pos 17 /*!< GPIO_PORT NOT5: NOTP17 Position */ -#define GPIO_PORT_NOT5_NOTP17_Msk (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos) /*!< GPIO_PORT NOT5: NOTP17 Mask */ -#define GPIO_PORT_NOT5_NOTP18_Pos 18 /*!< GPIO_PORT NOT5: NOTP18 Position */ -#define GPIO_PORT_NOT5_NOTP18_Msk (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos) /*!< GPIO_PORT NOT5: NOTP18 Mask */ -#define GPIO_PORT_NOT5_NOTP19_Pos 19 /*!< GPIO_PORT NOT5: NOTP19 Position */ -#define GPIO_PORT_NOT5_NOTP19_Msk (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos) /*!< GPIO_PORT NOT5: NOTP19 Mask */ -#define GPIO_PORT_NOT5_NOTP20_Pos 20 /*!< GPIO_PORT NOT5: NOTP20 Position */ -#define GPIO_PORT_NOT5_NOTP20_Msk (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos) /*!< GPIO_PORT NOT5: NOTP20 Mask */ -#define GPIO_PORT_NOT5_NOTP21_Pos 21 /*!< GPIO_PORT NOT5: NOTP21 Position */ -#define GPIO_PORT_NOT5_NOTP21_Msk (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos) /*!< GPIO_PORT NOT5: NOTP21 Mask */ -#define GPIO_PORT_NOT5_NOTP22_Pos 22 /*!< GPIO_PORT NOT5: NOTP22 Position */ -#define GPIO_PORT_NOT5_NOTP22_Msk (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos) /*!< GPIO_PORT NOT5: NOTP22 Mask */ -#define GPIO_PORT_NOT5_NOTP23_Pos 23 /*!< GPIO_PORT NOT5: NOTP23 Position */ -#define GPIO_PORT_NOT5_NOTP23_Msk (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos) /*!< GPIO_PORT NOT5: NOTP23 Mask */ -#define GPIO_PORT_NOT5_NOTP24_Pos 24 /*!< GPIO_PORT NOT5: NOTP24 Position */ -#define GPIO_PORT_NOT5_NOTP24_Msk (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos) /*!< GPIO_PORT NOT5: NOTP24 Mask */ -#define GPIO_PORT_NOT5_NOTP25_Pos 25 /*!< GPIO_PORT NOT5: NOTP25 Position */ -#define GPIO_PORT_NOT5_NOTP25_Msk (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos) /*!< GPIO_PORT NOT5: NOTP25 Mask */ -#define GPIO_PORT_NOT5_NOTP26_Pos 26 /*!< GPIO_PORT NOT5: NOTP26 Position */ -#define GPIO_PORT_NOT5_NOTP26_Msk (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos) /*!< GPIO_PORT NOT5: NOTP26 Mask */ -#define GPIO_PORT_NOT5_NOTP27_Pos 27 /*!< GPIO_PORT NOT5: NOTP27 Position */ -#define GPIO_PORT_NOT5_NOTP27_Msk (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos) /*!< GPIO_PORT NOT5: NOTP27 Mask */ -#define GPIO_PORT_NOT5_NOTP28_Pos 28 /*!< GPIO_PORT NOT5: NOTP28 Position */ -#define GPIO_PORT_NOT5_NOTP28_Msk (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos) /*!< GPIO_PORT NOT5: NOTP28 Mask */ -#define GPIO_PORT_NOT5_NOTP29_Pos 29 /*!< GPIO_PORT NOT5: NOTP29 Position */ -#define GPIO_PORT_NOT5_NOTP29_Msk (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos) /*!< GPIO_PORT NOT5: NOTP29 Mask */ -#define GPIO_PORT_NOT5_NOTP30_Pos 30 /*!< GPIO_PORT NOT5: NOTP30 Position */ -#define GPIO_PORT_NOT5_NOTP30_Msk (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos) /*!< GPIO_PORT NOT5: NOTP30 Mask */ -#define GPIO_PORT_NOT5_NOTP31_Pos 31 /*!< GPIO_PORT NOT5: NOTP31 Position */ -#define GPIO_PORT_NOT5_NOTP31_Msk (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos) /*!< GPIO_PORT NOT5: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT6 ----------------------------------------- -#define GPIO_PORT_NOT6_NOTP0_Pos 0 /*!< GPIO_PORT NOT6: NOTP0 Position */ -#define GPIO_PORT_NOT6_NOTP0_Msk (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos) /*!< GPIO_PORT NOT6: NOTP0 Mask */ -#define GPIO_PORT_NOT6_NOTP1_Pos 1 /*!< GPIO_PORT NOT6: NOTP1 Position */ -#define GPIO_PORT_NOT6_NOTP1_Msk (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos) /*!< GPIO_PORT NOT6: NOTP1 Mask */ -#define GPIO_PORT_NOT6_NOTP2_Pos 2 /*!< GPIO_PORT NOT6: NOTP2 Position */ -#define GPIO_PORT_NOT6_NOTP2_Msk (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos) /*!< GPIO_PORT NOT6: NOTP2 Mask */ -#define GPIO_PORT_NOT6_NOTP3_Pos 3 /*!< GPIO_PORT NOT6: NOTP3 Position */ -#define GPIO_PORT_NOT6_NOTP3_Msk (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos) /*!< GPIO_PORT NOT6: NOTP3 Mask */ -#define GPIO_PORT_NOT6_NOTP4_Pos 4 /*!< GPIO_PORT NOT6: NOTP4 Position */ -#define GPIO_PORT_NOT6_NOTP4_Msk (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos) /*!< GPIO_PORT NOT6: NOTP4 Mask */ -#define GPIO_PORT_NOT6_NOTP5_Pos 5 /*!< GPIO_PORT NOT6: NOTP5 Position */ -#define GPIO_PORT_NOT6_NOTP5_Msk (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos) /*!< GPIO_PORT NOT6: NOTP5 Mask */ -#define GPIO_PORT_NOT6_NOTP6_Pos 6 /*!< GPIO_PORT NOT6: NOTP6 Position */ -#define GPIO_PORT_NOT6_NOTP6_Msk (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos) /*!< GPIO_PORT NOT6: NOTP6 Mask */ -#define GPIO_PORT_NOT6_NOTP7_Pos 7 /*!< GPIO_PORT NOT6: NOTP7 Position */ -#define GPIO_PORT_NOT6_NOTP7_Msk (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos) /*!< GPIO_PORT NOT6: NOTP7 Mask */ -#define GPIO_PORT_NOT6_NOTP8_Pos 8 /*!< GPIO_PORT NOT6: NOTP8 Position */ -#define GPIO_PORT_NOT6_NOTP8_Msk (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos) /*!< GPIO_PORT NOT6: NOTP8 Mask */ -#define GPIO_PORT_NOT6_NOTP9_Pos 9 /*!< GPIO_PORT NOT6: NOTP9 Position */ -#define GPIO_PORT_NOT6_NOTP9_Msk (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos) /*!< GPIO_PORT NOT6: NOTP9 Mask */ -#define GPIO_PORT_NOT6_NOTP10_Pos 10 /*!< GPIO_PORT NOT6: NOTP10 Position */ -#define GPIO_PORT_NOT6_NOTP10_Msk (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos) /*!< GPIO_PORT NOT6: NOTP10 Mask */ -#define GPIO_PORT_NOT6_NOTP11_Pos 11 /*!< GPIO_PORT NOT6: NOTP11 Position */ -#define GPIO_PORT_NOT6_NOTP11_Msk (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos) /*!< GPIO_PORT NOT6: NOTP11 Mask */ -#define GPIO_PORT_NOT6_NOTP12_Pos 12 /*!< GPIO_PORT NOT6: NOTP12 Position */ -#define GPIO_PORT_NOT6_NOTP12_Msk (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos) /*!< GPIO_PORT NOT6: NOTP12 Mask */ -#define GPIO_PORT_NOT6_NOTP13_Pos 13 /*!< GPIO_PORT NOT6: NOTP13 Position */ -#define GPIO_PORT_NOT6_NOTP13_Msk (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos) /*!< GPIO_PORT NOT6: NOTP13 Mask */ -#define GPIO_PORT_NOT6_NOTP14_Pos 14 /*!< GPIO_PORT NOT6: NOTP14 Position */ -#define GPIO_PORT_NOT6_NOTP14_Msk (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos) /*!< GPIO_PORT NOT6: NOTP14 Mask */ -#define GPIO_PORT_NOT6_NOTP15_Pos 15 /*!< GPIO_PORT NOT6: NOTP15 Position */ -#define GPIO_PORT_NOT6_NOTP15_Msk (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos) /*!< GPIO_PORT NOT6: NOTP15 Mask */ -#define GPIO_PORT_NOT6_NOTP16_Pos 16 /*!< GPIO_PORT NOT6: NOTP16 Position */ -#define GPIO_PORT_NOT6_NOTP16_Msk (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos) /*!< GPIO_PORT NOT6: NOTP16 Mask */ -#define GPIO_PORT_NOT6_NOTP17_Pos 17 /*!< GPIO_PORT NOT6: NOTP17 Position */ -#define GPIO_PORT_NOT6_NOTP17_Msk (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos) /*!< GPIO_PORT NOT6: NOTP17 Mask */ -#define GPIO_PORT_NOT6_NOTP18_Pos 18 /*!< GPIO_PORT NOT6: NOTP18 Position */ -#define GPIO_PORT_NOT6_NOTP18_Msk (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos) /*!< GPIO_PORT NOT6: NOTP18 Mask */ -#define GPIO_PORT_NOT6_NOTP19_Pos 19 /*!< GPIO_PORT NOT6: NOTP19 Position */ -#define GPIO_PORT_NOT6_NOTP19_Msk (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos) /*!< GPIO_PORT NOT6: NOTP19 Mask */ -#define GPIO_PORT_NOT6_NOTP20_Pos 20 /*!< GPIO_PORT NOT6: NOTP20 Position */ -#define GPIO_PORT_NOT6_NOTP20_Msk (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos) /*!< GPIO_PORT NOT6: NOTP20 Mask */ -#define GPIO_PORT_NOT6_NOTP21_Pos 21 /*!< GPIO_PORT NOT6: NOTP21 Position */ -#define GPIO_PORT_NOT6_NOTP21_Msk (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos) /*!< GPIO_PORT NOT6: NOTP21 Mask */ -#define GPIO_PORT_NOT6_NOTP22_Pos 22 /*!< GPIO_PORT NOT6: NOTP22 Position */ -#define GPIO_PORT_NOT6_NOTP22_Msk (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos) /*!< GPIO_PORT NOT6: NOTP22 Mask */ -#define GPIO_PORT_NOT6_NOTP23_Pos 23 /*!< GPIO_PORT NOT6: NOTP23 Position */ -#define GPIO_PORT_NOT6_NOTP23_Msk (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos) /*!< GPIO_PORT NOT6: NOTP23 Mask */ -#define GPIO_PORT_NOT6_NOTP24_Pos 24 /*!< GPIO_PORT NOT6: NOTP24 Position */ -#define GPIO_PORT_NOT6_NOTP24_Msk (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos) /*!< GPIO_PORT NOT6: NOTP24 Mask */ -#define GPIO_PORT_NOT6_NOTP25_Pos 25 /*!< GPIO_PORT NOT6: NOTP25 Position */ -#define GPIO_PORT_NOT6_NOTP25_Msk (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos) /*!< GPIO_PORT NOT6: NOTP25 Mask */ -#define GPIO_PORT_NOT6_NOTP26_Pos 26 /*!< GPIO_PORT NOT6: NOTP26 Position */ -#define GPIO_PORT_NOT6_NOTP26_Msk (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos) /*!< GPIO_PORT NOT6: NOTP26 Mask */ -#define GPIO_PORT_NOT6_NOTP27_Pos 27 /*!< GPIO_PORT NOT6: NOTP27 Position */ -#define GPIO_PORT_NOT6_NOTP27_Msk (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos) /*!< GPIO_PORT NOT6: NOTP27 Mask */ -#define GPIO_PORT_NOT6_NOTP28_Pos 28 /*!< GPIO_PORT NOT6: NOTP28 Position */ -#define GPIO_PORT_NOT6_NOTP28_Msk (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos) /*!< GPIO_PORT NOT6: NOTP28 Mask */ -#define GPIO_PORT_NOT6_NOTP29_Pos 29 /*!< GPIO_PORT NOT6: NOTP29 Position */ -#define GPIO_PORT_NOT6_NOTP29_Msk (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos) /*!< GPIO_PORT NOT6: NOTP29 Mask */ -#define GPIO_PORT_NOT6_NOTP30_Pos 30 /*!< GPIO_PORT NOT6: NOTP30 Position */ -#define GPIO_PORT_NOT6_NOTP30_Msk (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos) /*!< GPIO_PORT NOT6: NOTP30 Mask */ -#define GPIO_PORT_NOT6_NOTP31_Pos 31 /*!< GPIO_PORT NOT6: NOTP31 Position */ -#define GPIO_PORT_NOT6_NOTP31_Msk (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos) /*!< GPIO_PORT NOT6: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT7 ----------------------------------------- -#define GPIO_PORT_NOT7_NOTP0_Pos 0 /*!< GPIO_PORT NOT7: NOTP0 Position */ -#define GPIO_PORT_NOT7_NOTP0_Msk (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos) /*!< GPIO_PORT NOT7: NOTP0 Mask */ -#define GPIO_PORT_NOT7_NOTP1_Pos 1 /*!< GPIO_PORT NOT7: NOTP1 Position */ -#define GPIO_PORT_NOT7_NOTP1_Msk (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos) /*!< GPIO_PORT NOT7: NOTP1 Mask */ -#define GPIO_PORT_NOT7_NOTP2_Pos 2 /*!< GPIO_PORT NOT7: NOTP2 Position */ -#define GPIO_PORT_NOT7_NOTP2_Msk (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos) /*!< GPIO_PORT NOT7: NOTP2 Mask */ -#define GPIO_PORT_NOT7_NOTP3_Pos 3 /*!< GPIO_PORT NOT7: NOTP3 Position */ -#define GPIO_PORT_NOT7_NOTP3_Msk (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos) /*!< GPIO_PORT NOT7: NOTP3 Mask */ -#define GPIO_PORT_NOT7_NOTP4_Pos 4 /*!< GPIO_PORT NOT7: NOTP4 Position */ -#define GPIO_PORT_NOT7_NOTP4_Msk (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos) /*!< GPIO_PORT NOT7: NOTP4 Mask */ -#define GPIO_PORT_NOT7_NOTP5_Pos 5 /*!< GPIO_PORT NOT7: NOTP5 Position */ -#define GPIO_PORT_NOT7_NOTP5_Msk (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos) /*!< GPIO_PORT NOT7: NOTP5 Mask */ -#define GPIO_PORT_NOT7_NOTP6_Pos 6 /*!< GPIO_PORT NOT7: NOTP6 Position */ -#define GPIO_PORT_NOT7_NOTP6_Msk (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos) /*!< GPIO_PORT NOT7: NOTP6 Mask */ -#define GPIO_PORT_NOT7_NOTP7_Pos 7 /*!< GPIO_PORT NOT7: NOTP7 Position */ -#define GPIO_PORT_NOT7_NOTP7_Msk (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos) /*!< GPIO_PORT NOT7: NOTP7 Mask */ -#define GPIO_PORT_NOT7_NOTP8_Pos 8 /*!< GPIO_PORT NOT7: NOTP8 Position */ -#define GPIO_PORT_NOT7_NOTP8_Msk (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos) /*!< GPIO_PORT NOT7: NOTP8 Mask */ -#define GPIO_PORT_NOT7_NOTP9_Pos 9 /*!< GPIO_PORT NOT7: NOTP9 Position */ -#define GPIO_PORT_NOT7_NOTP9_Msk (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos) /*!< GPIO_PORT NOT7: NOTP9 Mask */ -#define GPIO_PORT_NOT7_NOTP10_Pos 10 /*!< GPIO_PORT NOT7: NOTP10 Position */ -#define GPIO_PORT_NOT7_NOTP10_Msk (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos) /*!< GPIO_PORT NOT7: NOTP10 Mask */ -#define GPIO_PORT_NOT7_NOTP11_Pos 11 /*!< GPIO_PORT NOT7: NOTP11 Position */ -#define GPIO_PORT_NOT7_NOTP11_Msk (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos) /*!< GPIO_PORT NOT7: NOTP11 Mask */ -#define GPIO_PORT_NOT7_NOTP12_Pos 12 /*!< GPIO_PORT NOT7: NOTP12 Position */ -#define GPIO_PORT_NOT7_NOTP12_Msk (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos) /*!< GPIO_PORT NOT7: NOTP12 Mask */ -#define GPIO_PORT_NOT7_NOTP13_Pos 13 /*!< GPIO_PORT NOT7: NOTP13 Position */ -#define GPIO_PORT_NOT7_NOTP13_Msk (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos) /*!< GPIO_PORT NOT7: NOTP13 Mask */ -#define GPIO_PORT_NOT7_NOTP14_Pos 14 /*!< GPIO_PORT NOT7: NOTP14 Position */ -#define GPIO_PORT_NOT7_NOTP14_Msk (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos) /*!< GPIO_PORT NOT7: NOTP14 Mask */ -#define GPIO_PORT_NOT7_NOTP15_Pos 15 /*!< GPIO_PORT NOT7: NOTP15 Position */ -#define GPIO_PORT_NOT7_NOTP15_Msk (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos) /*!< GPIO_PORT NOT7: NOTP15 Mask */ -#define GPIO_PORT_NOT7_NOTP16_Pos 16 /*!< GPIO_PORT NOT7: NOTP16 Position */ -#define GPIO_PORT_NOT7_NOTP16_Msk (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos) /*!< GPIO_PORT NOT7: NOTP16 Mask */ -#define GPIO_PORT_NOT7_NOTP17_Pos 17 /*!< GPIO_PORT NOT7: NOTP17 Position */ -#define GPIO_PORT_NOT7_NOTP17_Msk (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos) /*!< GPIO_PORT NOT7: NOTP17 Mask */ -#define GPIO_PORT_NOT7_NOTP18_Pos 18 /*!< GPIO_PORT NOT7: NOTP18 Position */ -#define GPIO_PORT_NOT7_NOTP18_Msk (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos) /*!< GPIO_PORT NOT7: NOTP18 Mask */ -#define GPIO_PORT_NOT7_NOTP19_Pos 19 /*!< GPIO_PORT NOT7: NOTP19 Position */ -#define GPIO_PORT_NOT7_NOTP19_Msk (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos) /*!< GPIO_PORT NOT7: NOTP19 Mask */ -#define GPIO_PORT_NOT7_NOTP20_Pos 20 /*!< GPIO_PORT NOT7: NOTP20 Position */ -#define GPIO_PORT_NOT7_NOTP20_Msk (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos) /*!< GPIO_PORT NOT7: NOTP20 Mask */ -#define GPIO_PORT_NOT7_NOTP21_Pos 21 /*!< GPIO_PORT NOT7: NOTP21 Position */ -#define GPIO_PORT_NOT7_NOTP21_Msk (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos) /*!< GPIO_PORT NOT7: NOTP21 Mask */ -#define GPIO_PORT_NOT7_NOTP22_Pos 22 /*!< GPIO_PORT NOT7: NOTP22 Position */ -#define GPIO_PORT_NOT7_NOTP22_Msk (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos) /*!< GPIO_PORT NOT7: NOTP22 Mask */ -#define GPIO_PORT_NOT7_NOTP23_Pos 23 /*!< GPIO_PORT NOT7: NOTP23 Position */ -#define GPIO_PORT_NOT7_NOTP23_Msk (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos) /*!< GPIO_PORT NOT7: NOTP23 Mask */ -#define GPIO_PORT_NOT7_NOTP24_Pos 24 /*!< GPIO_PORT NOT7: NOTP24 Position */ -#define GPIO_PORT_NOT7_NOTP24_Msk (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos) /*!< GPIO_PORT NOT7: NOTP24 Mask */ -#define GPIO_PORT_NOT7_NOTP25_Pos 25 /*!< GPIO_PORT NOT7: NOTP25 Position */ -#define GPIO_PORT_NOT7_NOTP25_Msk (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos) /*!< GPIO_PORT NOT7: NOTP25 Mask */ -#define GPIO_PORT_NOT7_NOTP26_Pos 26 /*!< GPIO_PORT NOT7: NOTP26 Position */ -#define GPIO_PORT_NOT7_NOTP26_Msk (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos) /*!< GPIO_PORT NOT7: NOTP26 Mask */ -#define GPIO_PORT_NOT7_NOTP27_Pos 27 /*!< GPIO_PORT NOT7: NOTP27 Position */ -#define GPIO_PORT_NOT7_NOTP27_Msk (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos) /*!< GPIO_PORT NOT7: NOTP27 Mask */ -#define GPIO_PORT_NOT7_NOTP28_Pos 28 /*!< GPIO_PORT NOT7: NOTP28 Position */ -#define GPIO_PORT_NOT7_NOTP28_Msk (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos) /*!< GPIO_PORT NOT7: NOTP28 Mask */ -#define GPIO_PORT_NOT7_NOTP29_Pos 29 /*!< GPIO_PORT NOT7: NOTP29 Position */ -#define GPIO_PORT_NOT7_NOTP29_Msk (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos) /*!< GPIO_PORT NOT7: NOTP29 Mask */ -#define GPIO_PORT_NOT7_NOTP30_Pos 30 /*!< GPIO_PORT NOT7: NOTP30 Position */ -#define GPIO_PORT_NOT7_NOTP30_Msk (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos) /*!< GPIO_PORT NOT7: NOTP30 Mask */ -#define GPIO_PORT_NOT7_NOTP31_Pos 31 /*!< GPIO_PORT NOT7: NOTP31 Position */ -#define GPIO_PORT_NOT7_NOTP31_Msk (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos) /*!< GPIO_PORT NOT7: NOTP31 Mask */ - -#endif - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral memory map ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_SCT_BASE 0x40000000 -#define LPC_GPDMA_BASE 0x40002000 -#define LPC_SDMMC_BASE 0x40004000 -#define LPC_EMC_BASE 0x40005000 -#define LPC_USB0_BASE 0x40006000 -#define LPC_USB1_BASE 0x40007000 -#define LPC_LCD_BASE 0x40008000 -#define LPC_ETHERNET_BASE 0x40010000 -#define LPC_ATIMER_BASE 0x40040000 -#define LPC_REGFILE_BASE 0x40041000 -#define LPC_PMC_BASE 0x40042000 -#define LPC_CREG_BASE 0x40043000 -#define LPC_EVENTROUTER_BASE 0x40044000 -#define LPC_RTC_BASE 0x40046000 -#define LPC_CGU_BASE 0x40050000 -#define LPC_CCU1_BASE 0x40051000 -#define LPC_CCU2_BASE 0x40052000 -#define LPC_RGU_BASE 0x40053000 -#define LPC_WWDT_BASE 0x40080000 -#define LPC_USART0_BASE 0x40081000 -#define LPC_USART2_BASE 0x400C1000 -#define LPC_USART3_BASE 0x400C2000 -#define LPC_UART1_BASE 0x40082000 -#define LPC_SSP0_BASE 0x40083000 -#define LPC_SSP1_BASE 0x400C5000 -#define LPC_TIMER0_BASE 0x40084000 -#define LPC_TIMER1_BASE 0x40085000 -#define LPC_TIMER2_BASE 0x400C3000 -#define LPC_TIMER3_BASE 0x400C4000 -#define LPC_SCU_BASE 0x40086000 -#define LPC_GPIO_PIN_INT_BASE 0x40087000 -#define LPC_GPIO_GROUP_INTn_BASE 0x40088000 -#define LPC_GPIO_GROUP_INT1_BASE 0x40089000 -#define LPC_MCPWM_BASE 0x400A0000 -#define LPC_I2C0_BASE 0x400A1000 -#define LPC_I2C1_BASE 0x400E0000 -#define LPC_I2S0_BASE 0x400A2000 -#define LPC_I2S1_BASE 0x400A3000 -#define LPC_C_CAN1_BASE 0x400A4000 -#define LPC_RITIMER_BASE 0x400C0000 -#define LPC_QEI_BASE 0x400C6000 -#define LPC_GIMA_BASE 0x400C7000 -#define LPC_DAC_BASE 0x400E1000 -#define LPC_C_CAN0_BASE 0x400E2000 -#define LPC_ADC0_BASE 0x400E3000 -#define LPC_ADC1_BASE 0x400E4000 -#define LPC_GPIO_PORT_BASE 0x400F4000 - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral declaration ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE) -#define LPC_GPDMA ((LPC_GPDMA_Type *) LPC_GPDMA_BASE) -#define LPC_SDMMC ((LPC_SDMMC_Type *) LPC_SDMMC_BASE) -#define LPC_EMC ((LPC_EMC_Type *) LPC_EMC_BASE) -#define LPC_USB0 ((LPC_USB0_Type *) LPC_USB0_BASE) -#define LPC_USB1 ((LPC_USB1_Type *) LPC_USB1_BASE) -#define LPC_LCD ((LPC_LCD_Type *) LPC_LCD_BASE) -#define LPC_ETHERNET ((LPC_ETHERNET_Type *) LPC_ETHERNET_BASE) -#define LPC_ATIMER ((LPC_ATIMER_Type *) LPC_ATIMER_BASE) -#define LPC_REGFILE ((LPC_REGFILE_Type *) LPC_REGFILE_BASE) -#define LPC_PMC ((LPC_PMC_Type *) LPC_PMC_BASE) -#define LPC_CREG ((LPC_CREG_Type *) LPC_CREG_BASE) -#define LPC_EVENTROUTER ((LPC_EVENTROUTER_Type *) LPC_EVENTROUTER_BASE) -#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE) -#define LPC_CGU ((LPC_CGU_Type *) LPC_CGU_BASE) -#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE) -#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE) -#define LPC_RGU ((LPC_RGU_Type *) LPC_RGU_BASE) -#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) -#define LPC_USART0 ((LPC_USARTn_Type *) LPC_USART0_BASE) -#define LPC_USART2 ((LPC_USARTn_Type *) LPC_USART2_BASE) -#define LPC_USART3 ((LPC_USARTn_Type *) LPC_USART3_BASE) -#define LPC_UART1 ((LPC_UART1_Type *) LPC_UART1_BASE) -#define LPC_SSP0 ((LPC_SSPn_Type *) LPC_SSP0_BASE) -#define LPC_SSP1 ((LPC_SSPn_Type *) LPC_SSP1_BASE) -#define LPC_TIMER0 ((LPC_TIMERn_Type *) LPC_TIMER0_BASE) -#define LPC_TIMER1 ((LPC_TIMERn_Type *) LPC_TIMER1_BASE) -#define LPC_TIMER2 ((LPC_TIMERn_Type *) LPC_TIMER2_BASE) -#define LPC_TIMER3 ((LPC_TIMERn_Type *) LPC_TIMER3_BASE) -#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE) -#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) -#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE) -#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE) -#define LPC_MCPWM ((LPC_MCPWM_Type *) LPC_MCPWM_BASE) -#define LPC_I2C0 ((LPC_I2Cn_Type *) LPC_I2C0_BASE) -#define LPC_I2C1 ((LPC_I2Cn_Type *) LPC_I2C1_BASE) -#define LPC_I2S0 ((LPC_I2Sn_Type *) LPC_I2S0_BASE) -#define LPC_I2S1 ((LPC_I2Sn_Type *) LPC_I2S1_BASE) -#define LPC_C_CAN1 ((LPC_C_CANn_Type *) LPC_C_CAN1_BASE) -#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE) -#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE) -#define LPC_GIMA ((LPC_GIMA_Type *) LPC_GIMA_BASE) -#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE) -#define LPC_C_CAN0 ((LPC_C_CANn_Type *) LPC_C_CAN0_BASE) -#define LPC_ADC0 ((LPC_ADCn_Type *) LPC_ADC0_BASE) -#define LPC_ADC1 ((LPC_ADCn_Type *) LPC_ADC1_BASE) -#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE) - - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group LPC18xx */ -/** @} */ /* End of group (null) */ - -#ifdef __cplusplus -} -#endif - - -#endif // __LPC18XX_H__ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cm3.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cm3.h deleted file mode 100644 index c15e10ae2..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cm3.h +++ /dev/null @@ -1,1236 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - - -/** \mainpage CMSIS Cortex-M3 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmFunc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmFunc.h deleted file mode 100644 index c999b1c83..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmFunc.h +++ /dev/null @@ -1,609 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.10 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmInstr.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmInstr.h deleted file mode 100644 index ceb4f8756..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmInstr.h +++ /dev/null @@ -1,585 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/debug_frmwrk.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/debug_frmwrk.h deleted file mode 100644 index ac4618cf2..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/debug_frmwrk.h +++ /dev/null @@ -1,90 +0,0 @@ -/********************************************************************** -* $Id$ debug_frmwrk.h 2011-06-02 -*//** -* @file debug_frmwrk.h -* @brief Contains some utilities that used for debugging through UART -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup DEBUG_FRMWRK DEBUG FRAMEWORK - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef DEBUG_FRMWRK_H_ -#define DEBUG_FRMWRK_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_uart.h" - -#define VCOM_DEBUG_MESSEGES -//#define UART_DEBUG_MESSEGES - -#define USED_UART_DEBUG_PORT 1 - -#if (USED_UART_DEBUG_PORT==0) -#define DEBUG_UART_PORT LPC_UART0 -#elif (USED_UART_DEBUG_PORT==1) -#define DEBUG_UART_PORT LPC_UART1 -#endif - -#define _DBG(x) _db_msg((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DBG_(x) _db_msg_((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DBC(x) _db_char((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DBD(x) _db_dec((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DBD16(x) _db_dec_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DBD32(x) _db_dec_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DBH(x) _db_hex((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DBH16(x) _db_hex_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DBH32(x) _db_hex_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x) -#define _DG _db_get_char((LPC_USARTn_Type*)DEBUG_UART_PORT) -void lpc_printf (const char *format, ...); - -extern void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s); -extern void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s); -extern void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch); -extern void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn); -extern void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn); -extern void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn); -extern void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn); -extern void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn); -extern void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn); -extern uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx); - -void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch); -void UARTPuts(LPC_USARTn_Type *UARTx, const void *str); -void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str); -void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum); -void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum); -void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum); -void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum); -void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum); -void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum); -uint8_t UARTGetChar (LPC_USARTn_Type *UARTx); -void debug_frmwrk_init(void); - -#endif /* DEBUG_FRMWRK_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_adc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_adc.h deleted file mode 100644 index 55d5c86b9..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_adc.h +++ /dev/null @@ -1,295 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_adc.h 2011-06-02 -*//** -* @file lpc18xx_adc.h -* @brief Contains all macro definitions and function prototypes -* support for ADC firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup ADC ADC (Analog to Digital Converter) - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC18XX_ADC_H_ -#define LPC18XX_ADC_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private macros ------------------------------------------------------------- */ -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ - -/* -------------------------- BIT DEFINITIONS ----------------------------------- */ -/*********************************************************************//** - * Macro defines for ADC control register - **********************************************************************/ -/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */ -#define ADC_CR_CH_SEL(n) ((1UL << n)) -/** The APB clock (PCLK) is divided by (this value plus one) -* to produce the clock for the A/D */ -#define ADC_CR_CLKDIV(n) ((n<<8)) -/** Repeated conversions A/D enable bit */ -#define ADC_CR_BURST ((1UL<<16)) -/** number of accuracy bits */ -#define ADC_CR_BITACC(n) (((n)<<17)) -/** ADC convert in power down mode */ -#define ADC_CR_PDN ((1UL<<21)) -/** Start mask bits */ -#define ADC_CR_START_MASK ((7UL<<24)) -/** Select Start Mode */ -#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24)) -/** Start conversion now */ -#define ADC_CR_START_NOW ((1UL<<24)) -/** Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */ -#define ADC_CR_START_CTOUT15 ((2UL<<24)) -/** Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */ -#define ADC_CR_START_CTOUT8 ((3UL<<24)) -/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */ -#define ADC_CR_START_ADCTRIG0 ((4UL<<24)) -/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */ -#define ADC_CR_START_ADCTRIG1 ((5UL<<24)) -/** Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */ -#define ADC_CR_START_MCOA2 ((6UL<<24)) -/** Start conversion on a falling edge on the selected CAP/MAT signal */ -#define ADC_CR_EDGE ((1UL<<27)) - -/*********************************************************************//** - * Macro defines for ADC Global Data register - **********************************************************************/ -/** When DONE is 1, this field contains result value of ADC conversion */ -#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF)) -/** These bits contain the channel from which the LS bits were converted */ -#define ADC_GDR_CH(n) (((n>>24)&0x7)) -/** This bit is 1 in burst mode if the results of one or - * more conversions was (were) lost */ -#define ADC_GDR_OVERRUN_FLAG ((1UL<<30)) -/** This bit is set to 1 when an A/D conversion completes */ -#define ADC_GDR_DONE_FLAG ((1UL<<31)) - -/** This bits is used to mask for Channel */ -#define ADC_GDR_CH_MASK ((7UL<<24)) -/*********************************************************************//** - * Macro defines for ADC Interrupt register - **********************************************************************/ -/** These bits allow control over which A/D channels generate - * interrupts for conversion completion */ -#define ADC_INTEN_CH(n) ((1UL<>6)&0x3FF)) -/** These bits mirror the OVERRRUN status flags that appear in the - * result register for each A/D channel */ -#define ADC_DR_OVERRUN_FLAG ((1UL<<30)) -/** This bit is set to 1 when an A/D conversion completes. It is cleared - * when this register is read */ -#define ADC_DR_DONE_FLAG ((1UL<<31)) - -/*********************************************************************//** - * Macro defines for ADC Status register -**********************************************************************/ -/** These bits mirror the DONE status flags that appear in the result - * register for each A/D channel */ -#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF)) -/** These bits mirror the OVERRRUN status flags that appear in the - * result register for each A/D channel */ -#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF)) -/** This bit is the A/D interrupt flag */ -#define ADC_STAT_INT_FLAG ((1UL<<16)) - -/*********************************************************************//** - * Macro defines for ADC Trim register -**********************************************************************/ -/** Offset trim bits for ADC operation */ -#define ADC_ADCOFFS(n) (((n&0xF)<<4)) -/** Written to boot code*/ -#define ADC_TRIM(n) (((n&0xF)<<8)) - -/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */ -/** Check ADC parameter */ -#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC0) || ((uint32_t *)n)==((uint32_t *)LPC_ADC1)) - -/** Check ADC state parameter */ -#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING)) - -/** Check ADC state parameter */ -#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE)) - -/** Check ADC rate parameter */ -#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000)) - -/** Check ADC bits accuracy parameter */ -#define PARAM_ADC_BITSACC(x) ((x>=3)&&(x<=10)) - -/** Check ADC channel selection parameter */ -#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\ -||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\ -||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\ -||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7)) - -/** Check ADC start option parameter */ -#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\ -||(OPT == ADC_START_ON_CTOUT15)||(OPT == ADC_START_ON_CTOUT8)\ -||(OPT == ADC_START_ON_ADCTRIG0)||(OPT == ADC_START_ON_ADCTRIG1)\ -||(OPT == ADC_START_ON_MCOA2)) - -/** Check ADC interrupt type parameter */ -#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\ -||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\ -||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\ -||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\ -||(OPT == ADC_ADGINTEN)) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup ADC_Public_Types ADC Public Types - * @{ - */ - -/*********************************************************************//** - * @brief ADC enumeration - **********************************************************************/ -/** @brief Channel Selection */ -typedef enum -{ - ADC_CHANNEL_0 = 0, /*!< Channel 0 */ - ADC_CHANNEL_1, /*!< Channel 1 */ - ADC_CHANNEL_2, /*!< Channel 2 */ - ADC_CHANNEL_3, /*!< Channel 3 */ - ADC_CHANNEL_4, /*!< Channel 4 */ - ADC_CHANNEL_5, /*!< Channel 5 */ - ADC_CHANNEL_6, /*!< Channel 6 */ - ADC_CHANNEL_7 /*!< Channel 7 */ -}ADC_CHANNEL_SELECTION; - -/** @brief Type of start option */ -typedef enum -{ - ADC_START_CONTINUOUS =0, /*!< Continuous mode */ - ADC_START_NOW, /*!< Start conversion now */ - ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected - * by bit 27 occurs on CTOUT_15 */ - ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected - * by bit 27 occurs on CTOUT_8 */ - ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected - * by bit 27 occurs on ADCTRIG0 */ - ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected - * by bit 27 occurs on ADCTRIG1 */ - ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected - * by bit 27 occurs on Motocon PWM output MCOA2 */ -} ADC_START_OPT; - - -/** @brief Type of edge when start conversion on the selected CAP/MAT signal */ -typedef enum -{ - ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge - *on the selected CAP/MAT signal */ - ADC_START_ON_FALLING /*!< Start conversion on a falling edge - *on the selected CAP/MAT signal */ -} ADC_START_ON_EDGE_OPT; - -/** @brief* ADC type interrupt enum */ -typedef enum -{ - ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */ - ADC_ADINTEN1, /*!< Interrupt channel 1 */ - ADC_ADINTEN2, /*!< Interrupt channel 2 */ - ADC_ADINTEN3, /*!< Interrupt channel 3 */ - ADC_ADINTEN4, /*!< Interrupt channel 4 */ - ADC_ADINTEN5, /*!< Interrupt channel 5 */ - ADC_ADINTEN6, /*!< Interrupt channel 6 */ - ADC_ADINTEN7, /*!< Interrupt channel 7 */ - ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */ -}ADC_TYPE_INT_OPT; - -/** @brief ADC Data status */ -typedef enum -{ - ADC_DATA_BURST = 0, /*Burst bit*/ - ADC_DATA_DONE /*Done bit*/ -}ADC_DATA_STATUS; - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup ADC_Public_Functions ADC Public Functions - * @{ - */ -/* Init/DeInit ADC peripheral ----------------*/ -void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy); -void ADC_DeInit(LPC_ADCn_Type *ADCx); - -/* Enable/Disable ADC functions --------------*/ -void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState); -void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState); -void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode); -void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState); - -/* Configure ADC functions -------------------*/ -void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption); -void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState); - -/* Get ADC information functions -------------------*/ -uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel); -FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType); -uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx); -FlagStatus ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* LPC18XX_ADC_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_atimer.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_atimer.h deleted file mode 100644 index 68f0e9789..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_atimer.h +++ /dev/null @@ -1,93 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_atimer.h 2011-06-02 -*//** -* @file lpc18xx_atimer.h -* @brief Contains all functions support for Alarm Timer firmware -* library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup ATIMER ATIMER (Alarm Timer) - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC18XX_ATIMER_H_ -#define __LPC18XX_ATIMER_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" -#include "lpc_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup ATIMER_Private_Macros ALARM Timer Private Macros - * @{ - */ - -/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ -/** Macro to determine if it is valid ALARM TIMER peripheral */ -#define PARAM_ATIMERx(n) (((uint32_t *)n)==((uint32_t *)LPC_ATIMER)) - - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup ATIMER_Public_Functions ATIMER Public Functions - * @{ - */ - - -/* Init/DeInit ATIMER functions -----------*/ -void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue); -void ATIMER_DeInit(LPC_ATIMER_Type *ATIMERx); - -/* ATIMER interrupt functions -------------*/ -void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx); -void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx); -void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx); -void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx); - -/* ATIMER configuration functions --------*/ -void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue); -uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx); - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __LPC18XX_ATIMER_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_can.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_can.h deleted file mode 100644 index e1d7f48b5..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_can.h +++ /dev/null @@ -1,241 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_can.h 2011-06-02 -*//** -* @file lpc18xx_can.h -* @brief Contains all macro definitions and function prototypes -* support for CAN firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup C_CAN C_CAN (Controller Area Network) - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC18XX_CAN_H -#define __LPC18XX_CAN_H - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup C_CAN_Public_Macros C_CAN Public Macros - * @{ - */ - -/** In BASIC_MODE IF1 registers are used directly as TX buffer, IF2 registers are used as RX buffer. - * If not BASIC_MODE use message objects and IF registers to communicate with message buffers - */ -#define BASIC_MODE 0 - -/** In Silent Mode, the CAN controller is able to receive valid data frames and valid remote - * frames, but it sends only recessive bits on the CAN bus, and it cannot start a transmission - */ -#define SILENT_MODE 0 - -/** In Loop-back Mode, the CAN Core treats its own transmitted messages as received messages - * and stores them (if they pass acceptance filtering) into a Receive Buffer. - */ -#define LOOPBACK_MODE 0 - -/** Enables receiving remote frame requests */ -#define REMOTE_ENABLE 1 - -/** - * @} - */ - -/* Private Macros -------------------------------------------------------------- */ -/** @defgroup C_CAN_Private_Macros C_CAN Private Macros - * @{ - */ - -/** MAX CAN message obj */ -#define CAN_MSG_OBJ_MAX 0x0020 -/** MAX data length */ -#define CAN_DLC_MAX 8 - -/********************************************************************//** - * BRP+1 = Fpclk/(CANBitRate * QUANTAValue) - * QUANTAValue = 1 + (Tseg1+1) + (Tseg2+1) - * QUANTA value varies based on the Fpclk and sample point - * e.g. (1) sample point is 87.5%, Fpclk is 48Mhz - * the QUANTA should be 16 - * (2) sample point is 90%, Fpclk is 12.5Mhz - * the QUANTA should be 10 - * Fpclk = Fclk /APBDIV - * or - * BitRate = Fcclk/(APBDIV * (BRP+1) * ((Tseg1+1)+(Tseg2+1)+1)) - */ - -/*********************************************************************//** - * @brief CAN Bit Timing Values definitions at 8Mhz - **********************************************************************/ -/** Bitrate: 100K */ -#define CAN_BITRATE100K12MHZ 0x00004509 -/** Bitrate: 125K */ -#define CAN_BITRATE125K12MHZ 0x00004507 -/** Bitrate: 250K */ -#define CAN_BITRATE250K12MHZ 0x00004503 -/** Bitrate: 500K */ -#define CAN_BITRATE500K12MHZ 0x00004501 -/** Bitrate: 1000K */ -#define CAN_BITRATE1000K12MHZ 0x00004500 - -/*********************************************************************//** - * @brief CAN Bit Timing Values definitions at 16Mhz - **********************************************************************/ -/** Bitrate: 100K */ -#define CAN_BITRATE100K16MHZ 0x00005809 -/** Bitrate: 125K */ -#define CAN_BITRATE125K16MHZ 0x00005807 -/** Bitrate: 250K */ -#define CAN_BITRATE250K16MHZ 0x00005803 -/** Bitrate: 500K */ -#define CAN_BITRATE500K16MHZ 0x00005801 - - -/*********************************************************************//** - * @brief CAN Bit Timing Values definitions at 24Mhz - **********************************************************************/ -/** Bitrate: 100K */ -#define CAN_BITRATE100K24MHZ 0x00007E09 -/** Bitrate: 125K */ -#define CAN_BITRATE125K24MHZ 0x0000450F -/** Bitrate: 250K */ -#define CAN_BITRATE250K24MHZ 0x00004507 -/** Bitrate: 500K */ -#define CAN_BITRATE500K24MHZ 0x00004503 -/** Bitrate: 1000K */ -#define CAN_BITRATE1000K24MHZ 0x00004501 - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup CAN_Public_Types CAN Public Types - * @{ - */ - -/*********************************************************************//** - * @brief CAN enumeration - **********************************************************************/ - -/** - * @brief CAN interface register type definition - */ -typedef enum CCAN_IFREG -{ - CMDREQ = 0, /**< Command request */ - CMDMSK = 1, /**< Command mask */ - MSK1 = 2, /**< Mask 1 */ - MSK2 = 3, /**< Mask 2 */ - ARB1 = 4, /**< Arbitration 1 */ - ARB2 = 5, /**< Arbitration 2 */ - MCTRL = 6, /**< Message control */ - DA1 = 7, /**< Data A1 */ - DA2 = 8, /**< Data A2 */ - DB1 = 9, /**< Data B1 */ - DB2 = 10 /**< Data B2 */ -}CCAN_IFREG_Type; - -/** - * @brief CAN Clock division rate type definition - */ -typedef enum CCAN_CLKDIV -{ - CLKDIV1 = 0, - CLKDIV2 = 1, - CLKDIV3 = 2, - CLKDIV5 = 3, - CLKDIV9 = 4, - CLKDIV17 = 5, - CLKDIV33 = 6, - CLKDIV65 = 7 -}CCAN_CLKDIV_Type; - - -/********************************************************************//** -* @brief Data structure definition for a CAN message -**********************************************************************/ -/** - * @brief CAN message object structure - */ -typedef struct -{ - uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */ - uint32_t dlc; /**< Message data length */ - uint8_t data[8]; /**< Message data */ -} message_object; - -/** - * @brief CAN call-back function - */ -typedef void (*MSG_CB)(uint32_t msg_no); - -/** - * @} - */ - - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup CAN_Public_Functions CAN Public Functions - * @{ - */ - -void CAN_IRQHandler (void); -void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb); - -void CAN_ConfigureRxMessageObjects( void ); -void CAN_RxInt_MessageProcess( uint8_t MsgObjNo ); -void CAN_TxInt_MessageProcess( uint8_t MsgObjNo ); - -void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr ); -void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable); -void CAN_ReadMsg(uint32_t msg_no, message_object* buff); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __LPC18XX_CAN_H */ - -/** - * @} - */ -/***************************************************************************** -** End Of File -******************************************************************************/ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_cgu.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_cgu.h deleted file mode 100644 index 93fc16194..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_cgu.h +++ /dev/null @@ -1,271 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_cgu.h 2011-06-02 -*//** -* @file llpc18xx_cgu.h -* @brief Contains all macro definitions and function prototypes -* support for Clock Generation and Clock Control firmware -* library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup CGU CGU (Clock Generation Unit) - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC18XX_CGU_H_ -#define LPC18XX_CGU_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" -#include "lpc_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private Macros -------------------------------------------------------------- */ -/** @defgroup CGU_Private_Macros CGU Private Macros - * @{ - */ - -/** Branch clocks from CGU_BASE_SAFE */ -#define CGU_ENTITY_NONE CGU_ENTITY_NUM - -/** Check bit at specific position is clear or not */ -#define ISBITCLR(x,bit) ((x&(1<=8000)&&(freq <= 96000)) -/* Macro check I2S word width type */ -#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\ -||(n==I2S_WORDWIDTH_32)) -/* Macro check I2S channel type */ -#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO)) -/* Macro check I2S master/slave mode */ -#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE)) -/* Macro check I2S stop mode */ -#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE)) -/* Macro check I2S reset mode */ -#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE)) -/* Macro check I2S reset mode */ -#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE)) -/* Macro check I2S transmit/receive mode */ -#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE)) -/* Macro check I2S clock select mode */ -#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK)) -/* Macro check I2S 4-pin mode */ -#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE)) -/* Macro check I2S MCLK mode */ -#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE)) -/* Macro check I2S DMA mode */ -#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2)) -/* Macro check I2S DMA depth value */ -#define PARAM_I2S_DMA_DEPTH(n) ((n<=31)) -/* Macro check I2S irq level value */ -#define PARAM_I2S_IRQ_LEVEL(n) ((n<=31)) -/* Macro check I2S half-period value */ -#define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512)) -/* Macro check I2S bit-rate value */ -#define PARAM_I2S_BITRATE(n) ((n<=63)) -/** - * @} - */ - - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup I2S_Public_Types I2S Public Types - * @{ - */ - -/** - * @brief I2S configuration structure definition - */ -typedef struct { - uint8_t wordwidth; /** the number of bytes in data as follow: - -I2S_WORDWIDTH_8: 8 bit data - -I2S_WORDWIDTH_16: 16 bit data - -I2S_WORDWIDTH_32: 32 bit data */ - uint8_t mono; /** Set mono/stereo mode, should be: - - I2S_STEREO: stereo mode - - I2S_MONO: mono mode */ - uint8_t stop; /** Disables accesses on FIFOs, should be: - - I2S_STOP_ENABLE: enable stop mode - - I2S_STOP_DISABLE: disable stop mode */ - uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be: - - I2S_RESET_ENABLE: enable reset mode - - I2S_RESET_DISABLE: disable reset mode */ - uint8_t ws_sel; /** Set Master/Slave mode, should be: - - I2S_MASTER_MODE: I2S master mode - - I2S_SLAVE_MODE: I2S slave mode */ - uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be: - - I2S_MUTE_ENABLE: enable mute mode - - I2S_MUTE_DISABLE: disable mute mode */ - uint8_t Reserved0[2]; -} I2S_CFG_Type; - -/** - * @brief I2S DMA configuration structure definition - */ -typedef struct { - uint8_t DMAIndex; /** Select DMA1 or DMA2, should be: - - I2S_DMA_1: DMA1 - - I2S_DMA_2: DMA2 */ - uint8_t depth; /** FIFO level that triggers a DMA request */ - uint8_t Reserved0[2]; -}I2S_DMAConf_Type; - -/** - * @brief I2S mode configuration structure definition - */ -typedef struct{ - uint8_t clksel; /** Clock source selection, should be: - - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output - - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */ - uint8_t fpin; /** Select four pin mode, should be: - - I2S_4PIN_ENABLE: 4-pin enable - - I2S_4PIN_DISABLE: 4-pin disable */ - uint8_t mcena; /** Select MCLK mode, should be: - - I2S_MCLK_ENABLE: MCLK enable for output - - I2S_MCLK_DISABLE: MCLK disable for output */ - uint8_t Reserved; -}I2S_MODEConf_Type; - - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup I2S_Public_Functions I2S Public Functions - * @{ - */ -/* I2S Init/DeInit functions ---------*/ -void I2S_Init(LPC_I2Sn_Type *I2Sx); -void I2S_DeInit(LPC_I2Sn_Type *I2Sx); - -/* I2S configuration functions --------*/ -void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct); -Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode); -void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode); -void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode); -uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode); - -/* I2S operate functions -------------*/ -void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData); -uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx); -void I2S_Start(LPC_I2Sn_Type *I2Sx); -void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode); -void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode); -void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode); - -/* I2S DMA functions ----------------*/ -void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode); -void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState); - -/* I2S IRQ functions ----------------*/ -void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx,uint8_t TRMode, FunctionalState NewState); -void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level); -FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode); -uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* LPC18XX_I2S_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_lcd.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_lcd.h deleted file mode 100644 index f57015fa4..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_lcd.h +++ /dev/null @@ -1,224 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_lcd.h 2011-06-02 -*//** -* @file lpc18xx_lcd.h -* @brief Contains all macro definitions and function prototypes -* support for LCD Driver -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup LCD LCD - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC18XX_LCD_H_ -#define __LPC18XX_LCD_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" -#include "lpc_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup LCD_Private_Macros LCD Private Macros - * @{ - */ - -/* --------------------- BIT DEFINITIONS -------------------------------------- */ -/* LCD control enable bit */ -#define CLCDC_LCDCTRL_ENABLE _BIT(0) -/* LCD control power enable bit */ -#define CLCDC_LCDCTRL_PWR _BIT(11) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup LCD_Public_Types LCD Public Types - * @{ - */ - -/*********************************************************************//** - * @brief LCD enumeration - **********************************************************************/ - -/** @brief LCD Interrupt Source */ -typedef enum{ - LCD_INT_FUF = _BIT(1), /* FIFO underflow bit */ - LCD_INT_LNBU = _BIT(2), /* LCD next base address update bit */ - LCD_INT_VCOMP = _BIT(3), /* vertical compare bit */ - LCD_INT_BER = _BIT(4) /* AHB master error interrupt bit */ -} LCD_INT_SRC; - -/** @brief LCD signal polarity */ -typedef enum { - LCD_SIGNAL_ACTIVE_HIGH = 0, - LCD_SIGNAL_ACTIVE_LOW = 1 -} LCD_SIGNAL_POLARITY_OPT; - -/** @brief LCD clock edge polarity */ -typedef enum { - LCD_CLK_RISING = 0, - LCD_CLK_FALLING= 1 -} LCD_CLK_EDGE_OPT; - -/** @brief LCD bits per pixel and pixel format */ -typedef enum { - LCD_BPP1 = 0, - LCD_BPP2, - LCD_BPP4, - LCD_BPP8, - LCD_BPP16, - LCD_BPP24, - LCD_BPP16_565, - LCD_BPP12_444 -}LCD_PIXEL_FORMAT_OPT; - -/** @brief LCD color format */ -typedef enum { - LCD_COLOR_FORMAT_RGB = 0, - LCD_COLOR_FORMAT_BGR -}LCD_COLOR_FORMAT_OPT; - - -/*********************************************************************//** - * @brief LCD structure definitions - **********************************************************************/ -/** @brief LCD Palette entry format */ -typedef struct -{ - uint32_t Rl:5; - uint32_t Gl:5; - uint32_t Bl:5; - uint32_t Il:1; - uint32_t Ru:5; - uint32_t Gu:5; - uint32_t Bu:5; - uint32_t Iu:1; -} LCD_PALETTE_ENTRY_Type; - -/** @brief LCD cursor format in 1 byte LBBP */ -typedef struct -{ - uint8_t Pixel3:2; - uint8_t Pixel2:2; - uint8_t Pixel1:2; - uint8_t Pixel0:2; -} LCD_CURSOR_PIXEL_Type; - -/** @brief LCD cursor size */ -typedef enum -{ - LCD_CURSOR_32x32 = 0, - LCD_CURSOR_64x64 -} LCD_CURSOR_SIZE_OPT; - -/** @brief LCD panel type */ -typedef enum -{ - LCD_TFT = 0x02, /* standard TFT */ - LCD_MONO_4 = 0x01, /* 4-bit STN mono */ - LCD_MONO_8 = 0x05, /* 8-bit STN mono */ - LCD_CSTN = 0x00 /* color STN */ -} LCD_PANEL_OPT; - -/** @brief LCD porch configuration structure */ -typedef struct { - uint16_t front; /* front porch setting in clocks */ - uint16_t back; /* back porch setting in clocks */ -}LCD_PORCHCFG_Type; - -/** @brief LCD configuration structure */ -typedef struct { - uint16_t screen_width; /* Pixels per line */ - uint16_t screen_height; /* Lines per panel */ - LCD_PORCHCFG_Type horizontal_porch; /* porch setting for horizontal */ - LCD_PORCHCFG_Type vertical_porch; /* porch setting for vertical */ - uint16_t HSync_pulse_width; /* HSYNC pulse width in clocks */ - uint16_t VSync_pulse_width; /* VSYNC pulse width in clocks */ - uint8_t ac_bias_frequency; /* AC bias frequency in clocks */ - LCD_SIGNAL_POLARITY_OPT HSync_pol; /* HSYNC polarity */ - LCD_SIGNAL_POLARITY_OPT VSync_pol; /* VSYNC polarity */ - LCD_CLK_EDGE_OPT panel_clk_edge; /* Panel Clock Edge Polarity */ - LCD_SIGNAL_POLARITY_OPT OE_pol; /* Output Enable polarity */ - uint32_t line_end_delay; /* 0 if not use */ - LCD_PIXEL_FORMAT_OPT bits_per_pixel; /* Maximum bits per pixel the display supports */ - LCD_PANEL_OPT lcd_panel_type; /* LCD panel type */ - LCD_COLOR_FORMAT_OPT color_format; /* BGR or RGB */ - Bool dual_panel; /* Dual panel, TRUE = dual panel display */ - uint16_t pcd; -} LCD_CFG_Type; - -/** - * @} - */ - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup LCD_Public_Functions LCD Public Functions - * @{ - */ - -void LCD_Init(LPC_LCD_Type *LCDx, LCD_CFG_Type *LCD_ConfigStruct); -void LCD_DeInit(LPC_LCD_Type *LCDx); - -void LCD_Power(LPC_LCD_Type *LCDx, FunctionalState OnOff); -void LCD_Enable(LPC_LCD_Type *LCDx, FunctionalState EnDis); -void LCD_SetFrameBuffer(LPC_LCD_Type *LCDx, void* buffer); -void LCD_SetLPFrameBuffer(LPC_LCD_Type *LCDx, void* buffer); -void LCD_LoadPalette(LPC_LCD_Type *LCDx, void* palette); -void LCD_SetInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int); -void LCD_ClrInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int); -LCD_INT_SRC LCD_GetInterrupt(LPC_LCD_Type *LCDx); - -void LCD_Cursor_Config(LPC_LCD_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, Bool sync); -void LCD_Cursor_WriteImage(LPC_LCD_Type *LCDx, uint8_t cursor_num, void* Image); -void* LCD_Cursor_GetImageBufferAddress(LPC_LCD_Type *LCDx, uint8_t cursor_num); -void LCD_Cursor_Enable(LPC_LCD_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff); -void LCD_Cursor_LoadPalette0(LPC_LCD_Type *LCDx, uint32_t palette_color); -void LCD_Cursor_LoadPalette1(LPC_LCD_Type *LCDx, uint32_t palette_color); -void LCD_Cursor_SetInterrupt(LPC_LCD_Type *LCDx); -void LCD_Cursor_ClrInterrupt(LPC_LCD_Type *LCDx); -void LCD_Cursor_SetPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y); -void LCD_Cursor_SetClipPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC18XX_LCD_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_libcfg_default.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_libcfg_default.h deleted file mode 100644 index a3411a058..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_libcfg_default.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Modified for Code Red tools to prevent redefinition of DEBUG macro - * 2011/12/29 - */ -/********************************************************************** -* $Id$ lpc18xx_libcfg_default.h 2011-06-02 -*//** -* @file lpc18xx_libcfg_default.h -* @brief Default Library configuration header file -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Library Configuration group ----------------------------------------------------------- */ -/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC18XX_LIBCFG_DEFAULT_H_ -#define LPC18XX_LIBCFG_DEFAULT_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_types.h" - - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros - * @{ - */ - -/************************** DEBUG MODE DEFINITIONS *********************************/ -/* Un-comment the line below to compile the library in DEBUG mode, this will expanse - the "CHECK_PARAM" macro in the FW library code */ - -#ifndef __CODE_RED -#define DEBUG -#endif - - -/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/ - -/* Comment the line below to disable the specific peripheral inclusion */ - -/* GPIO ------------------------------- */ -#define _GPIO - -/* EXTI ------------------------------- */ -#define _EXTI - -/* UART ------------------------------- */ -#define _UART -#define _UART0 -#define _UART1 -#define _UART2 -#define _UART3 - -/* SPI ------------------------------- */ -#define _SPI - -/* SYSTICK --------------------------- */ -#define _SYSTICK - -/* SSP ------------------------------- */ -#define _SSP -#define _SSP0 -#define _SSP1 - - -/* I2C ------------------------------- */ -#define _I2C -#define _I2C0 -#define _I2C1 -#define _I2C2 - -/* TIMER ------------------------------- */ -#define _TIM - -/* WWDT ------------------------------- */ -#define _WWDT - - -/* GPDMA ------------------------------- */ -#define _GPDMA - - -/* DAC ------------------------------- */ -#define _DAC - -/* DAC ------------------------------- */ -#define _ADC - - -/* PWM ------------------------------- */ -#define _PWM -#define _PWM1 - -/* RTC ------------------------------- */ -#define _RTC - -/* I2S ------------------------------- */ -#define _I2S - -/* USB device ------------------------------- */ -#define _USBDEV -#define _USB_DMA - -/* QEI ------------------------------- */ -#define _QEI - -/* MCPWM ------------------------------- */ -#define _MCPWM - -/* CAN--------------------------------*/ -#define _C_CAN - -/* RIT ------------------------------- */ -#define _RIT - -/* EMAC ------------------------------ */ -#define _EMAC - -/* SCT ------------------------------ */ -#define _SCT - -/* LCD ------------------------------ */ -#define _LCD - -/* ATIMER ------------------------------ */ -#define _ATIMER - -/* RGU ------------------------------ */ -#define _RGU - -/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/ - -#ifdef DEBUG -/******************************************************************************* -* @brief The CHECK_PARAM macro is used for function's parameters check. -* It is used only if the library is compiled in DEBUG mode. -* @param[in] expr - If expr is false, it calls check_failed() function -* which reports the name of the source file and the source -* line number of the call that failed. -* - If expr is true, it returns no value. -* @return None -*******************************************************************************/ -#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) -#else -#define CHECK_PARAM(expr) -#endif /* DEBUG */ - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions - * @{ - */ - -#ifdef DEBUG -void check_failed(uint8_t *file, uint32_t line); -#endif - -/** - * @} - */ - -#endif /* LPC18XX_LIBCFG_DEFAULT_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_mcpwm.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_mcpwm.h deleted file mode 100644 index 7a8c68b92..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_mcpwm.h +++ /dev/null @@ -1,338 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_mcpwm.h 2011-06-02 -*//** -* @file lpc18xx_mcpwm.h -* @brief Contains all macro definitions and function prototypes -* support for Motor Control PWM firmware library on LPC18XX -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup MCPWM MCPWM (Motor Control PWM) - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC18XX_MCPWM_H_ -#define LPC18XX_MCPWM_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" -#include "lpc_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup MCPWM_Private_Macros MCPWM Private Macros - * @{ - */ -/** Edge aligned mode for channel in MCPWM */ -#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0)) -/** Center aligned mode for channel in MCPWM */ -#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1)) - -/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */ -#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0)) -/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */ -#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1)) - -/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of - * the six output pins under the control of the bits in this register */ -#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ -#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ -#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ -#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ -#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ -#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ - -/* Interrupt type in MCPWM */ -/** Limit interrupt for channel (0) */ -#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0) -/** Match interrupt for channel (0) */ -#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0) -/** Capture interrupt for channel (0) */ -#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0) - -/** Limit interrupt for channel (1) */ -#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1) -/** Match interrupt for channel (1) */ -#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1) -/** Capture interrupt for channel (1) */ -#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1) - -/** Limit interrupt for channel (2) */ -#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2) -/** Match interrupt for channel (2) */ -#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2) -/** Capture interrupt for channel (2) */ -#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2) - -/** Fast abort interrupt */ -#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT - -/*********************************************************************//** - * Macro defines for MCPWM Control register - **********************************************************************/ -/* MCPWM Control register, these macro definitions below can be applied for these - * register type: - * - MCPWM Control read address - * - MCPWM Control set address - * - MCPWM Control clear address - */ -/**< Stops/starts timer channel n */ -#define MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0)) -/**< Edge/center aligned operation for channel n */ -#define MCPWM_CON_CENTER(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0)) -/**< Select polarity of the MCOAn and MCOBn pin */ -#define MCPWM_CON_POLAR(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0)) -/**< Control the dead-time feature for channel n */ -#define MCPWM_CON_DTE(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0)) -/**< Enable/Disable update of functional register for channel n */ -#define MCPWM_CON_DISUP(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0)) -/**< Control the polarity for all 3 channels */ -#define MCPWM_CON_INVBDC ((uint32_t)(1<<29)) -/**< 3-phase AC mode select */ -#define MCPWM_CON_ACMODE ((uint32_t)(1<<30)) -/**< 3-phase DC mode select */ -#define MCPWM_CON_DCMODE (((uint32_t)1<<31)) - -/*********************************************************************//** - * Macro defines for MCPWM Capture Control register - **********************************************************************/ -/* Capture Control register, these macro definitions below can be applied for these - * register type: - * - MCPWM Capture Control read address - * - MCPWM Capture Control set address - * - MCPWM Capture control clear address - */ -/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */ -#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0)) -/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */ -#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0)) -/** TC(n) is reset by channel (n) capture event */ -#define MCPWM_CAPCON_RT(n) (((n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0)) -/** Hardware noise filter: channel (n) capture events are delayed */ -#define MCPWM_CAPCON_HNFCAP(n) (((n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0)) - -/*********************************************************************//** - * Macro defines for MCPWM Interrupt register - **********************************************************************/ -/* Interrupt registers, these macro definitions below can be applied for these - * register type: - * - MCPWM Interrupt Enable read address - * - MCPWM Interrupt Enable set address - * - MCPWM Interrupt Enable clear address - * - MCPWM Interrupt Flags read address - * - MCPWM Interrupt Flags set address - * - MCPWM Interrupt Flags clear address - */ -/** Limit interrupt for channel (n) */ -#define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0)) -/** Match interrupt for channel (n) */ -#define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0)) -/** Capture interrupt for channel (n) */ -#define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0)) -/** Fast abort interrupt */ -#define MCPWM_INT_ABORT ((uint32_t)(1<<15)) - -/*********************************************************************//** - * Macro defines for MCPWM Count Control register - **********************************************************************/ -/* MCPWM Count Control register, these macro definitions below can be applied for these - * register type: - * - MCPWM Count Control read address - * - MCPWM Count Control set address - * - MCPWM Count Control clear address - */ -/** Counter(tc) advances on a rising edge on MCI(mci) pin */ -#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0)) -/** Counter(cnt) advances on a falling edge on MCI(mci) pin */ -#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0)) -/** Channel (n) is in counter mode */ -#define MCPWM_CNTCON_CNTR(n) (((n<=2)) ? ((uint32_t)(1<<(29+n))) : (0)) - -/*********************************************************************//** - * Macro defines for MCPWM Dead-time register - **********************************************************************/ -/** Dead time value x for channel n */ -#define MCPWM_DT(n,x) (((n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0)) - -/*********************************************************************//** - * Macro defines for MCPWM Communication Pattern register - **********************************************************************/ -#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ -#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ -#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ -#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ -#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ -#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ - -/*********************************************************************//** - * Macro defines for MCPWM Capture clear address register - **********************************************************************/ -/** Clear the MCCAP (n) register */ -#define MCPWM_CAPCLR_CAP(n) (((n<=2)) ? ((uint32_t)(1<> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */ - -/*********************************************************************//** - * Macro defines for Macro defines for UART interrupt enable register - **********************************************************************/ -#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/ -#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/ -#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/ -#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */ -#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */ -#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */ -#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */ -#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */ -#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */ - -/*********************************************************************//** - * Macro defines for Macro defines for UART interrupt identification register - **********************************************************************/ -#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */ -#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */ - - -/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ - -/** Macro to check the input UART_DATABIT parameters */ -#define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\ -|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8)) - -/** Macro to check the input UART_STOPBIT parameters */ -#define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2)) - -/** Macro to check the input UART_PARITY parameters */ -#define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \ -|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \ -|| (parity==UART_PARITY_SP_0)) - -/** Macro to check the input UART_FIFO parameters */ -#define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \ -|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \ -|| (fifo==UART_FIFO_TRGLEV3)) - -/** Macro to check the input UART_INTCFG parameters */ -#define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \ -|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \ -|| (IntCfg==UART_INTCFG_ABTO)) - -/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */ -#define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS)) - -/** Macro to check the input UART_AUTOBAUD_MODE parameters */ -#define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1)) - -/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */ -#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \ - (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO)) - -/** Macro to check the input UART_IrDA_PULSEDIV parameters */ -#define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \ -|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \ -|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \ -|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256)) - -/* Macro to check the input UART1_SignalState parameters */ -#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE)) - -/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */ -#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS)) - -/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */ -#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \ -|| (x==UART1_MODEM_MODE_AUTO_CTS)) - -/** Macro to check the direction control pin type */ -#define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART_RS485_DIRCTRL_RTS) || (x==UART_RS485_DIRCTRL_DTR)|| (x==UART_RS485_DIRCTRL_DIR)) - -/* Macro to determine if it is valid UART port number */ -#define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_USART0)) \ -|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \ -|| (((uint32_t *)x)==((uint32_t *)LPC_USART2)) \ -|| (((uint32_t *)x)==((uint32_t *)LPC_USART3))) -#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_USART3)) -#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1)) - -/** Macro to check the input value for UART_RS485_CFG_MATCHADDRVALUE parameter */ -#define PARAM_UART_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF)) - -/** Macro to check the input value for UART_RS485_CFG_DELAYVALUE parameter */ -#define PARAM_UART_RS485_CFG_DELAYVALUE(x) ((x<0xFF)) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup UART_Public_Types UART Public Types - * @{ - */ - -/*********************************************************************** - * @brief UART enumeration -**********************************************************************/ -/** - * @brief UART Databit type definitions - */ -typedef enum { - UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ - UART_DATABIT_6, /*!< UART 6 bit data mode */ - UART_DATABIT_7, /*!< UART 7 bit data mode */ - UART_DATABIT_8 /*!< UART 8 bit data mode */ -} UART_DATABIT_Type; - -/** - * @brief UART Stop bit type definitions - */ -typedef enum { - UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ - UART_STOPBIT_2 /*!< UART Two Stop Bits Select */ -} UART_STOPBIT_Type; - -/** - * @brief UART Parity type definitions - */ -typedef enum { - UART_PARITY_NONE = 0, /*!< No parity */ - UART_PARITY_ODD, /*!< Odd parity */ - UART_PARITY_EVEN, /*!< Even parity */ - UART_PARITY_SP_1, /*!< Forced "1" stick parity */ - UART_PARITY_SP_0 /*!< Forced "0" stick parity */ -} UART_PARITY_Type; - -/** - * @brief FIFO Level type definitions - */ -typedef enum { - UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ - UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ - UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ - UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ -} UART_FITO_LEVEL_Type; - - -/********************************************************************//** -* @brief UART Interrupt Type definitions -**********************************************************************/ -typedef enum { - UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ - UART_INTCFG_THRE, /*!< THR Interrupt enable*/ - UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ - UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ - UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ - UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ - UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ -} UART_INT_Type; - -/** - * @brief UART Line Status Type definition - */ -typedef enum { - UART_LINESTAT_RDR = UART_LSR_RDR, /*! the Reset bit is enabled */ - uint8_t wdtProtect; /**< if ENABLE -> the Protect bit is enabled */ - uint32_t wdtTmrConst; /**< Set the constant value to timeout the WDT (us) */ - uint32_t wdtWarningVal; /**< Set the value to warn the WDT with interrupt (us) */ - uint32_t wdtWindowVal; /**< Set a window vaule for WDT (us) */ -}st_Wdt_Config; - -/** - * @} - */ - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup WWDT_Public_Functions WWDT Public Functions - * @{ - */ - -void WWDT_Init(void); -void WWDT_UpdateTimeOut(uint32_t TimeOut); -void WWDT_Feed (void); -void WWDT_SetWarning(uint32_t WarnTime); -void WWDT_SetWindow(uint32_t WindowedTime); -void WWDT_Configure(st_Wdt_Config wdtCfg); -void WWDT_Start(void); -FlagStatus WWDT_GetStatus (uint8_t Status); -void WWDT_ClearStatusFlag (uint8_t flag); -uint32_t WWDT_GetCurrentCount(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* LPC18XX_WWDT_H_ */ - -/** - * @} - */ -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc_types.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc_types.h deleted file mode 100644 index bbe56e2cc..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc_types.h +++ /dev/null @@ -1,211 +0,0 @@ -/********************************************************************** -* $Id$ lpc_types.h 2011-06-02 -*//** -* @file lpc_types.h -* @brief Contains the NXP ABL typedefs for C standard types. -* It is intended to be used in ISO C conforming development -* environments and checks for this insofar as it is possible -* to do so. -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Type group ----------------------------------------------------------- */ -/** @defgroup LPC_Types LPC_Types - * @ingroup LPC1800CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC_TYPES_H -#define LPC_TYPES_H - -/* Includes ------------------------------------------------------------------- */ -#include - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup LPC_Types_Public_Types LPC_Types Public Types - * @{ - */ - -/** - * @brief Boolean Type definition - */ -typedef enum {FALSE = 0, TRUE = !FALSE} Bool; - -/** - * @brief Flag Status and Interrupt Flag Status type definition - */ -typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; -#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET)) - -/** - * @brief Functional State Definition - */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE)) - -/** - * @ Status type definition - */ -typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; - - -/** - * Read/Write transfer type mode (Block or non-block) - */ -typedef enum -{ - NONE_BLOCKING = 0, /**< None Blocking type */ - BLOCKING, /**< Blocking type */ -} TRANSFER_BLOCK_Type; - - -/** Pointer to Function returning Void (any number of parameters) */ -typedef void (*PFV)(); - -/** Pointer to Function returning int32_t (any number of parameters) */ -typedef int32_t(*PFI)(); - -/** - * @} - */ - - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros - * @{ - */ - -/* _BIT(n) sets the bit at position "n" - * _BIT(n) is intended to be used in "OR" and "AND" expressions: - * e.g., "(_BIT(3) | _BIT(7))". - */ -#undef _BIT -/* Set bit macro */ -#define _BIT(n) (1<<(n)) - -/* _SBF(f,v) sets the bit field starting at position "f" to value "v". - * _SBF(f,v) is intended to be used in "OR" and "AND" expressions: - * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)" - */ -#undef _SBF -/* Set bit field macro */ -#define _SBF(f,v) ((v)<<(f)) - -/* _BITMASK constructs a symbol with 'field_width' least significant - * bits set. - * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF - * The symbol is intended to be used to limit the bit field width - * thusly: - * = (any_expression) & _BITMASK(x), where 0 < x <= 32. - * If "any_expression" results in a value that is larger than can be - * contained in 'x' bits, the bits above 'x - 1' are masked off. When - * used with the _SBF example above, the example would be written: - * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) - * This ensures that the value written to a_reg is no wider than - * 16 bits, and makes the code easier to read and understand. - */ -#undef _BITMASK -/* Bitmask creation macro */ -#define _BITMASK(field_width) ( _BIT(field_width) - 1) - -/* NULL pointer */ -#ifndef NULL -#define NULL ((void*) 0) -#endif - -/* Number of elements in an array */ -#define NELEMENTS(array) (sizeof (array) / sizeof (array[0])) - -/* Static data/function define */ -#define STATIC static -/* External data/function define */ -#define EXTERN extern - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -/** - * @} - */ - - -/* Old Type Definition compatibility ------------------------------------------ */ -/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types - * @{ - */ - -/** SMA type for character type */ -typedef char CHAR; - -/** SMA type for 8 bit unsigned value */ -typedef uint8_t UNS_8; - -/** SMA type for 8 bit signed value */ -typedef int8_t INT_8; - -/** SMA type for 16 bit unsigned value */ -typedef uint16_t UNS_16; - -/** SMA type for 16 bit signed value */ -typedef int16_t INT_16; - -/** SMA type for 32 bit unsigned value */ -typedef uint32_t UNS_32; - -/** SMA type for 32 bit signed value */ -typedef int32_t INT_32; - -/** SMA type for 64 bit signed value */ -typedef int64_t INT_64; - -/** SMA type for 64 bit unsigned value */ -typedef uint64_t UNS_64; - -/** 32 bit boolean type */ -typedef Bool BOOL_32; - -/** 16 bit boolean type */ -typedef Bool BOOL_16; - -/** 8 bit boolean type */ -typedef Bool BOOL_8; - -#ifdef __CC_ARM -#define INLINE __inline -#else -#define INLINE inline -#endif -/** - * @} - */ - - -#endif /* LPC_TYPES_H */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/spifi_rom_api.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/spifi_rom_api.h deleted file mode 100644 index 041fd63b2..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/spifi_rom_api.h +++ /dev/null @@ -1,248 +0,0 @@ -/*********************************************************************** -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#ifndef SPIFI_ROM_API_H -#define SPIFI_ROM_API_H - -#include -/* define the symbol TESTING in the environment if test output desired */ - -/* maintain LONGEST_PROT >= the length (in bytes) of the largest - protection block of any serial flash that this driver handles */ -#define LONGEST_PROT 68 - -typedef uint8_t uc; - -#ifndef NULL -#define NULL ((void *)0) -#endif - -/* protection/sector descriptors */ -typedef struct { - uint32_t base; - uc flags; - int8_t log2; - uint16_t rept; -} protEnt; -/* bits in the flags byte */ -enum {RWPROT=1}; - -/* overall data structure includes # sectors, length of protection reg, - array of descriptors -typedef struct { - uint16_t sectors; - uint16_t protBytes; - protEnt *entries; -} protDesc; */ - -typedef union { - uint16_t hw; - uc byte[2]; -}stat_t; -/* the object that init returns, and other routines use as an operand */ -typedef struct { - uint32_t base, regbase, devSize, memSize; - uc mfger, devType, devID, busy; - stat_t stat; - uint16_t reserved; - uint16_t set_prot, write_prot; - uint32_t mem_cmd, prog_cmd; - uint16_t sectors, protBytes; - uint32_t opts, errCheck; - uc erase_shifts[4], erase_ops[4]; - protEnt *protEnts; - char prot[LONGEST_PROT]; -} SPIFIobj; - -/* operands of program and erase */ -typedef struct { - char *dest; - uint32_t length; - char *scratch; - int32_t protect; - uint32_t options; -} SPIFIopers; - -/* instruction classes for wait_busy */ -typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type; - -/* bits in options operands (MODE3, RCVCLK, and FULLCLK - have the same relationship as in the Control register) */ -#define S_MODE3 1 -#define S_MODE0 0 -#define S_MINIMAL 2 -#define S_MAXIMAL 0 -#define S_FORCE_ERASE 4 -#define S_ERASE_NOT_REQD 8 -#define S_CALLER_ERASE 8 -#define S_ERASE_AS_REQD 0 -#define S_VERIFY_PROG 0x10 -#define S_VERIFY_ERASE 0x20 -#define S_NO_VERIFY 0 -#define S_RCVCLK 0x80 -#define S_INTCLK 0 -#define S_FULLCLK 0x40 -#define S_HALFCLK 0 -#define S_DUAL 0x100 -#define S_CALLER_PROT 0x200 -#define S_DRIVER_PROT 0 - -/* the following values in the first post-address memory command byte work - for all known quad devices that support "no opcode" operation */ -#define NO_OPCODE_FOLLOWS 0xA5 -#define OPCODE_FOLLOWS 0xFF - -/* basic SPI commands for serial flash */ -#define BASE_READ_CMD (CMD_RD<opts (mostly for setMulti) */ -/* used by Winbond: send 0xA3 command so hardware can read faster */ -#define OPT_SEND_A3 1 -/* used by SST: send 0x38 command to enable quad and allow full command set */ -#define OPT_SEND_38 2 -/* used by Winbond and others: read status reg 2, check it, - if necessary write it back with Quad Enable set */ -#define OPT_35_OR02_01 4 -/* used by Atmel: read Configuration register, if necessary set Quad Enable */ -#define OPT_3F_OR80_3E 8 -/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */ -#define OPT_65_CLR_C0_61 0x10 -/* used by Numonyx: send 0x81 command to write Volatile Configuration Register - to set # dummy bytes and allow XIP mode */ -#define OPT_81 0x20 -/* set for devices without full device erase command (Numonyx type 0x40) */ -#define OPT_NO_DEV_ERASE 0x40 -/* used by Macronix: status reg 2 includes selection between write-protect - in status reg and command-based */ -#define OPT_WPSEL 0x80 -/* set when protection data has been read into the SPIFI object */ -#define OPT_PROT_READ 0x100 -/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */ -#define OPT_4BAD 0x200 -/* set if setMulti should set the Dual bit in Control reg */ -#define OPT_DUAL 0x400 -/* send "# dummy bits" in C0 command to Winbond */ -#define OPT_C0 0x800 -/* set QE for Chingis */ -#define OPT_05_OR40_01 0x1000 -/* write status does not go busy */ -#define OPT_01_NO_BUSY 0x2000 -/* protection mode bits moved from protMode byte to opts Fri May 13 2011 */ -#define OPT_PROT_STAT 0x4000 -#define OPT_PROT_REG 0x8000 -#define OPT_PROT_CMD3 0x10000 -#define OPT_PROT_CMDE 0x20000 -#define OPT_PROT_MASK 0x3C000 - -#define OPT_ALL_QUAD 0x40000 - -#ifndef OMIT_ROM_TABLE -/* interface to ROM API */ -typedef struct { - int32_t (*spifi_init) (SPIFIobj *obj, uint32_t csHigh, uint32_t options, - uint32_t mhz); - int32_t (*spifi_program) (SPIFIobj *obj, char *source, SPIFIopers *opers); - int32_t (*spifi_erase) (SPIFIobj *obj, SPIFIopers *opers); - /* mode switching */ - void (*cancel_mem_mode)(SPIFIobj *obj); - void (*set_mem_mode) (SPIFIobj *obj); - - /* mid level functions */ - int32_t (*checkAd) (SPIFIobj *obj, SPIFIopers *opers); - int32_t (*setProt) (SPIFIobj *obj, SPIFIopers *opers, char *change, - char *saveProt); - int32_t (*check_block) (SPIFIobj *obj, char *source, SPIFIopers *opers, - uint32_t check_program); - int32_t (*send_erase_cmd) (SPIFIobj *obj, uint8_t op, uint32_t addr); - uint32_t (*ck_erase) (SPIFIobj *obj, uint32_t *addr, uint32_t length); - int32_t (*prog_block) (SPIFIobj *obj, char *source, SPIFIopers *opers, - uint32_t *left_in_page); - uint32_t (*ck_prog) (SPIFIobj *obj, char *source, char *dest, uint32_t length); - - /* low level functions */ - void(*setSize) (SPIFIobj *obj, int32_t value); - int32_t (*setDev) (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, - uint32_t prog_cmd); - uint32_t (*cmd) (uc op, uc addrLen, uc intLen, uint16_t len); - uint32_t (*readAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr); - void (*send04) (SPIFIobj *obj, uc op, uc len, uint32_t value); - void (*wren_sendAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value); - int32_t (*write_stat) (SPIFIobj *obj, uc len, uint16_t value); - int32_t (*wait_busy) (SPIFIobj *obj, uc prog_or_erase); -} SPIFI_RTNS; - -#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR) -#endif /* OMIT_ROM_TABLE */ - -#ifdef USE_SPIFI_LIB -extern SPIFI_RTNS spifi_table; -#endif /* USE_SPIFI_LIB */ - -/* example of using this interface: -#include "spifi_rom_api.h" -#define CSHIGH 4 -#define SPIFI_MHZ 80 -#define source_data_ad (char *)1234 - - int32_t rc; - SPIFIopers opers; - - define_spifi_romPtr(spifi); - SPIFIobj *obj = malloc(sizeof(SPIFIobj)); - if (!obj) { can't allocate memory } - - rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ); - if (rc) { investigate init error rc } - printf ("the serial flash contains %d bytes\n", obj->devSize); - - opers.dest = where_to_program; - opers.length = how_many_bytes; - opers.scratch = NULL; // unprogrammed data is not saved/restored - opers.protect = -1; // save & restore protection - opers.options = S_VERIFY_PROG; - - rc = spifi->spifi_program (obj, source_data_ad, &opers); - if (rc) { investigate program error rc } -*/ - -/* these are for normal users, including boot code */ -int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz); -int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers); -int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers); - -/* these are used by the manufacturer-specific init functions */ -void setSize (SPIFIobj *obj, int32_t value); -int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd); -uint32_t read04(SPIFIobj *obj, uc op, uc len); -int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value); -void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen); - -/* needs to be defined for each platform */ -void pullMISO(int high); - -#ifdef TESTING -/* used by testing code */ -unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors); -/* predeclare a debug routine */ -void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value); -#endif - -#endif /* SPIFI_ROM_API_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/system_LPC18xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/system_LPC18xx.h deleted file mode 100644 index 80c3c7384..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/system_LPC18xx.h +++ /dev/null @@ -1,50 +0,0 @@ -/********************************************************************** -* $Id$ system_LPC18xx.h 2011-06-02 -*//** -* @file system_LPC18xx.h -* @brief Cortex-M3 Device System Header File for NXP LPC18xx Series. -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#ifndef __SYSTEM_LPC18xx_H -#define __SYSTEM_LPC18xx_H - -#ifdef __cplusplus -extern "C" { -#endif -#include -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC18xx_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/debug_frmwrk.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/debug_frmwrk.c deleted file mode 100644 index a50358ed6..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/debug_frmwrk.c +++ /dev/null @@ -1,326 +0,0 @@ -/********************************************************************** -* $Id$ debug_frmwrk.c 2011-06-02 -*//** -* @file debug_frmwrk.c -* @brief Contains some utilities that used for debugging through UART -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup DEBUG_FRMWRK - * @{ - */ - -#ifndef _DEBUG_FRMWRK_ -#define _DEBUG_FRMWRK_ - -/* Includes ------------------------------------------------------------------- */ -#include "debug_frmwrk.h" -#include "lpc18xx_scu.h" -#include -#include - -#ifdef CDC_DEBUG_MESSEGES -#include "usbhw.h" -#include "cdcuser.h" -#include "CDCdemo.h" -#include "lpc18xx_utils.h" -#include -#endif - -/* Debug framework */ - -void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s); -void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s); -void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch); -void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn); -void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn); -void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn); -void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn); -void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn); -void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn); -uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx); - - - -/*********************************************************************//** - * @brief Puts a character to UART port - * @param[in] UARTx Pointer to UART peripheral - * @param[in] ch Character to put - * @return None - **********************************************************************/ -void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch) -{ - UART_Send(UARTx, &ch, 1, BLOCKING); -} - - -/*********************************************************************//** - * @brief Get a character to UART port - * @param[in] UARTx Pointer to UART peripheral - * @return character value that returned - **********************************************************************/ -uint8_t UARTGetChar (LPC_USARTn_Type *UARTx) -{ - uint8_t tmp = 0; - UART_Receive(UARTx, &tmp, 1, BLOCKING); - return(tmp); -} - - -/*********************************************************************//** - * @brief Puts a string to UART port - * @param[in] UARTx Pointer to UART peripheral - * @param[in] str string to put - * @return None - **********************************************************************/ -void UARTPuts(LPC_USARTn_Type *UARTx, const void *str) -{ -#ifdef CDC_DEBUG_MESSEGES - int num_of_bytes=0; - num_of_bytes = strlen(str); - timer_delay_us(num_of_bytes); - - USB_WriteEP (CDC_DEP_IN, (unsigned char *)str, num_of_bytes); -#else - uint8_t *s = (uint8_t *) str; - - while (*s) - { - UARTPutChar(UARTx, *s++); - } -#endif -} - - -/*********************************************************************//** - * @brief Puts a string to UART port and print new line - * @param[in] UARTx Pointer to UART peripheral - * @param[in] str String to put - * @return None - **********************************************************************/ -void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str) -{ - UARTPuts (UARTx, str); - UARTPuts (UARTx, "\n\r"); -} - - -/*********************************************************************//** - * @brief Puts a decimal number to UART port - * @param[in] UARTx Pointer to UART peripheral - * @param[in] decnum Decimal number (8-bit long) - * @return None - **********************************************************************/ -void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum) -{ - uint8_t c1=decnum%10; - uint8_t c2=(decnum/10)%10; - uint8_t c3=(decnum/100)%10; - UARTPutChar(UARTx, '0'+c3); - UARTPutChar(UARTx, '0'+c2); - UARTPutChar(UARTx, '0'+c1); -} - -/*********************************************************************//** - * @brief Puts a decimal number to UART port - * @param[in] UARTx Pointer to UART peripheral - * @param[in] decnum Decimal number (8-bit long) - * @return None - **********************************************************************/ -void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum) -{ - uint8_t c1=decnum%10; - uint8_t c2=(decnum/10)%10; - uint8_t c3=(decnum/100)%10; - uint8_t c4=(decnum/1000)%10; - uint8_t c5=(decnum/10000)%10; - UARTPutChar(UARTx, '0'+c5); - UARTPutChar(UARTx, '0'+c4); - UARTPutChar(UARTx, '0'+c3); - UARTPutChar(UARTx, '0'+c2); - UARTPutChar(UARTx, '0'+c1); -} - -/*********************************************************************//** - * @brief Puts a decimal number to UART port - * @param[in] UARTx Pointer to UART peripheral - * @param[in] decnum Decimal number (8-bit long) - * @return None - **********************************************************************/ -void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum) -{ - uint8_t c1=decnum%10; - uint8_t c2=(decnum/10)%10; - uint8_t c3=(decnum/100)%10; - uint8_t c4=(decnum/1000)%10; - uint8_t c5=(decnum/10000)%10; - uint8_t c6=(decnum/100000)%10; - uint8_t c7=(decnum/1000000)%10; - uint8_t c8=(decnum/10000000)%10; - uint8_t c9=(decnum/100000000)%10; - uint8_t c10=(decnum/1000000000)%10; - UARTPutChar(UARTx, '0'+c10); - UARTPutChar(UARTx, '0'+c9); - UARTPutChar(UARTx, '0'+c8); - UARTPutChar(UARTx, '0'+c7); - UARTPutChar(UARTx, '0'+c6); - UARTPutChar(UARTx, '0'+c5); - UARTPutChar(UARTx, '0'+c4); - UARTPutChar(UARTx, '0'+c3); - UARTPutChar(UARTx, '0'+c2); - UARTPutChar(UARTx, '0'+c1); -} - -/*********************************************************************//** - * @brief Puts a hex number to UART port - * @param[in] UARTx Pointer to UART peripheral - * @param[in] hexnum Hex number (8-bit long) - * @return None - **********************************************************************/ -void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum) -{ - uint8_t nibble, i; - - UARTPuts(UARTx, "0x"); - i = 1; - do { - nibble = (hexnum >> (4*i)) & 0x0F; - UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble)); - } while (i--); -} - - -/*********************************************************************//** - * @brief Puts a hex number to UART port - * @param[in] UARTx Pointer to UART peripheral - * @param[in] hexnum Hex number (16-bit long) - * @return None - **********************************************************************/ -void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum) -{ - uint8_t nibble, i; - - UARTPuts(UARTx, "0x"); - i = 3; - do { - nibble = (hexnum >> (4*i)) & 0x0F; - UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble)); - } while (i--); -} - -/*********************************************************************//** - * @brief Puts a hex number to UART port - * @param[in] UARTx Pointer to UART peripheral - * @param[in] hexnum Hex number (32-bit long) - * @return None - **********************************************************************/ -void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum) -{ - uint8_t nibble, i; - - UARTPuts(UARTx, "0x"); - i = 7; - do { - nibble = (hexnum >> (4*i)) & 0x0F; - UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble)); - } while (i--); -} - -/*********************************************************************//** - * @brief print function that supports format as same as printf() - * function of library - * @param[in] format formated string to be print - * @return None - **********************************************************************/ -void lpc_printf (const char *format, ...) -{ - char buffer[512 + 1]; - va_list vArgs; - va_start(vArgs, format); - vsprintf((char *)buffer, (char const *)format, vArgs); - va_end(vArgs); - - _DBG(buffer); -} - -/*********************************************************************//** - * @brief Initialize Debug frame work through initializing UART port - * @param[in] None - * @return None - **********************************************************************/ -void debug_frmwrk_init(void) -{ -#ifdef UART_DEBUG_MESSEGES - - UART_CFG_Type UARTConfigStruct; - -#if (USED_UART_DEBUG_PORT==0) - /* - * Initialize UART0 pin connect NGX board - */ - scu_pinmux(0xF ,10 , MD_PDN|MD_EZI, FUNC1); // P6.4 UART0_TXD - scu_pinmux(0xF ,11 , MD_PDN|MD_EZI, FUNC1); // P6.5 UART0_RXD -#elif (USED_UART_DEBUG_PORT==1) - /* - * Initialize UART1 pin connect - */ - scu_pinmux(0x1 ,13 , MD_PDN, FUNC1); // PC.13 : UART1_TXD - scu_pinmux(0x1 ,14 , MD_PLN|MD_EZI|MD_ZI, FUNC1); // PC.14 : UART1_RXD -#endif - - /* Initialize UART Configuration parameter structure to default state: - * Baudrate = 9600bps - * 8 data bit - * 1 Stop bit - * None parity - */ - UART_ConfigStructInit(&UARTConfigStruct); - - // Initialize DEBUG_UART_PORT peripheral with given to corresponding parameter - UART_Init((LPC_USARTn_Type*)DEBUG_UART_PORT, &UARTConfigStruct); - - // Enable UART Transmit - UART_TxCmd((LPC_USARTn_Type*)DEBUG_UART_PORT, ENABLE); -#endif -#ifdef CDC_DEBUG_MESSEGES - CDC_init(); //wait for usb enumeration - -#endif - - _db_msg = UARTPuts; - _db_msg_ = UARTPuts_; - _db_char = UARTPutChar; - _db_hex = UARTPutHex; - _db_hex_16 = UARTPutHex16; - _db_hex_32 = UARTPutHex32; - _db_dec = UARTPutDec; - _db_dec_16 = UARTPutDec16; - _db_dec_32 = UARTPutDec32; - _db_get_char = UARTGetChar; -} - -#endif /* _DEBUG_FRMWRK_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_adc.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_adc.c deleted file mode 100644 index ded86e7dd..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_adc.c +++ /dev/null @@ -1,353 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_adc.c 2011-06-02 -*//** -* @file lpc18xx_adc.c -* @brief Contains all functions support for ADC firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup ADC - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_adc.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _ADC -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup ADC_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Initial for ADC - * + Set bit PCADC - * + Set clock for ADC - * + Set Clock Frequency - * @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC - * @param[in] rate ADC conversion rate, should be <=200KHz - * @param[in] bits_accuracy number of bits accuracy, should be <=10 bits and >=3bits - * @return None - **********************************************************************/ -void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy) -{ - uint32_t temp, tmpreg, ADCbitrate; - - CHECK_PARAM(PARAM_ADCx(ADCx)); - CHECK_PARAM(PARAM_ADC_RATE(rate)); - - // Turn on power and clock - //CGU_ConfigPPWR (CGU_PCONP_PCAD, ENABLE); - - ADCx->CR = 0; - - //Enable PDN bit - tmpreg = ADC_CR_PDN; - // Set clock frequency - if(ADCx == LPC_ADC0) - temp = CGU_GetPCLKFrequency(CGU_PERIPHERAL_ADC0); - else if(ADCx == LPC_ADC1) - temp = CGU_GetPCLKFrequency(CGU_PERIPHERAL_ADC1); - /* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for - * A/D converter, which should be less than or equal to 13MHz. - * A fully conversion requires (bits_accuracy+1) of these clocks. - * ADC clock = PCLK_ADC0 / (CLKDIV + 1); - * ADC rate = ADC clock / (bits_accuracy+1); - */ - ADCbitrate = (rate * (bits_accuracy+1)); - temp = ((temp*2 + ADCbitrate) / (ADCbitrate*2)) - 1;//get the round value by fomular: (2*A + B)/(2*B) - tmpreg |= ADC_CR_CLKDIV(temp) | ADC_CR_BITACC(10 - bits_accuracy); - - ADCx->CR = tmpreg; -} - - -/*********************************************************************//** -* @brief Close ADC -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @return None -**********************************************************************/ -void ADC_DeInit(LPC_ADCn_Type *ADCx) -{ - CHECK_PARAM(PARAM_ADCx(ADCx)); - - // Clear PDN bit - ADCx->CR &= ~ADC_CR_PDN; - // Turn on power and clock - //CGU_ConfigPPWR (CGU_PCONP_PCAD, DISABLE); -} - - -///*********************************************************************//** -//* @brief Get Result conversion from A/D data register -//* @param[in] channel number which want to read back the result -//* @return Result of conversion -//*********************************************************************/ -//uint32_t ADC_GetData(uint32_t channel) -//{ -// uint32_t adc_value; -// -// CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel)); -// -// adc_value = *(uint32_t *)((&LPC_ADC->DR0) + channel); -// return ADC_GDR_RESULT(adc_value); -//} - -/*********************************************************************//** -* @brief Set start mode for ADC -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] start_mode Start mode choose one of modes in -* 'ADC_START_OPT' enumeration type definition, should be: -* - ADC_START_CONTINUOUS -* - ADC_START_NOW -* - ADC_START_ON_EINT0 -* - ADC_START_ON_CAP01 -* - ADC_START_ON_MAT01 -* - ADC_START_ON_MAT03 -* - ADC_START_ON_MAT10 -* - ADC_START_ON_MAT11 -* @return None -*********************************************************************/ -void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode) -{ - CHECK_PARAM(PARAM_ADCx(ADCx)); - CHECK_PARAM(PARAM_ADC_START_OPT(start_mode)); - - ADCx->CR &= ~ADC_CR_START_MASK; - ADCx->CR |=ADC_CR_START_MODE_SEL((uint32_t)start_mode); -} - - -/*********************************************************************//** -* @brief ADC Burst mode setting -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] NewState -* - 1: Set Burst mode -* - 0: reset Burst mode -* @return None -**********************************************************************/ -void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_ADCx(ADCx)); - - ADCx->CR &= ~ADC_CR_BURST; - if (NewState){ - ADCx->CR |= ADC_CR_BURST; - } -} - -/*********************************************************************//** -* @brief Set AD conversion in power mode -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] NewState -* - 1: AD converter is optional -* - 0: AD Converter is in power down mode -* @return None -**********************************************************************/ -void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_ADCx(ADCx)); - - ADCx->CR &= ~ADC_CR_PDN; - if (NewState){ - ADCx->CR |= ADC_CR_PDN; - } -} - -/*********************************************************************//** -* @brief Set Edge start configuration -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] EdgeOption is ADC_START_ON_RISING and ADC_START_ON_FALLING -* - 0: ADC_START_ON_RISING -* - 1: ADC_START_ON_FALLING -* @return None -**********************************************************************/ -void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption) -{ - CHECK_PARAM(PARAM_ADCx(ADCx)); - CHECK_PARAM(PARAM_ADC_START_ON_EDGE_OPT(EdgeOption)); - - ADCx->CR &= ~ADC_CR_EDGE; - if (EdgeOption){ - ADCx->CR |= ADC_CR_EDGE; - } -} - -/*********************************************************************//** -* @brief ADC interrupt configuration -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] IntType: type of interrupt, should be: -* - ADC_ADINTEN0: Interrupt channel 0 -* - ADC_ADINTEN1: Interrupt channel 1 -* ... -* - ADC_ADINTEN7: Interrupt channel 7 -* - ADC_ADGINTEN: Individual channel/global flag done generate an interrupt -* @param[in] NewState: -* - SET : enable ADC interrupt -* - RESET: disable ADC interrupt -* @return None -**********************************************************************/ -void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_ADCx(ADCx)); - CHECK_PARAM(PARAM_ADC_TYPE_INT_OPT(IntType)); - - ADCx->INTEN &= ~ADC_INTEN_CH(IntType); - if (NewState){ - ADCx->INTEN |= ADC_INTEN_CH(IntType); - } -} - -/*********************************************************************//** -* @brief Enable/Disable ADC channel number -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] Channel channel number -* @param[in] NewState New state, should be: -* - ENABLE -* - DISABLE -* @return None -**********************************************************************/ -void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_ADCx(ADCx)); - CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(Channel)); - - if (NewState == ENABLE) { - ADCx->CR |= ADC_CR_CH_SEL(Channel); - } else { - ADCx->CR &= ~ADC_CR_CH_SEL(Channel); - } -} - -/*********************************************************************//** -* @brief Get ADC result -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] channel channel number, should be 0...7 -* @return Converted data -**********************************************************************/ -uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel) -{ - uint32_t adc_value; - - CHECK_PARAM(PARAM_ADCx(ADCx)); - CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel)); - - adc_value = *(uint32_t *) ((&(ADCx->DR[0])) + channel); - return ADC_DR_RESULT(adc_value); -} - -/*********************************************************************//** -* @brief Get ADC Channel status from ADC data register -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] channel: channel number, should be 0..7 -* @param[in] StatusType -* - 0: Burst status -* - 1: Done status -* @return Channel status, could be: -* - SET -* - RESET -**********************************************************************/ -FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType) -{ - uint32_t temp; - - CHECK_PARAM(PARAM_ADCx(ADCx)); - CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel)); - CHECK_PARAM(PARAM_ADC_DATA_STATUS(StatusType)); - - temp = *(uint32_t *) ((&ADCx->DR[0]) + channel); - if (StatusType) { - temp &= ADC_DR_DONE_FLAG; - }else{ - temp &= ADC_DR_OVERRUN_FLAG; - } - if (temp) { - return SET; - } else { - return RESET; - } - -} - -/*********************************************************************//** -* @brief Get ADC Data from AD Global register -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @return Result of conversion -**********************************************************************/ -uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx) -{ - CHECK_PARAM(PARAM_ADCx(ADCx)); - - return ((uint32_t)(ADCx->GDR)); -} - -/*********************************************************************//** -* @brief Get ADC Chanel status from AD global data register -* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC -* @param[in] StatusType -* - 0: Burst status -* - 1: Done status -* @return SET / RESET -**********************************************************************/ -FlagStatus ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType) -{ - uint32_t temp; - - CHECK_PARAM(PARAM_ADCx(ADCx)); - CHECK_PARAM(PARAM_ADC_DATA_STATUS(StatusType)); - - temp = ADCx->GDR; - if (StatusType){ - temp &= ADC_DR_DONE_FLAG; - }else{ - temp &= ADC_DR_OVERRUN_FLAG; - } - if (temp){ - return SET; - }else{ - return RESET; - } -} - -/** - * @} - */ - -#endif /* _ADC */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_atimer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_atimer.c deleted file mode 100644 index d6123dea4..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_atimer.c +++ /dev/null @@ -1,170 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_atimer.c 2011-06-02 -*//** -* @file lpc18xx_atimer.c -* @brief Contains all functions support for Alarm Timer firmware -* library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup ATIMER - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_atimer.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _ATIMER - -/* Private Functions ---------------------------------------------------------- */ - -/*********************************************************************//** - * @brief Initial Alarm Timer device - * @param[in] ATIMERx Timer selection, should be: LPC_ATIMER - * @param[in] PresetValue Count of 1/1024s for Alarm - * @return None - **********************************************************************/ -void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue) -{ - CHECK_PARAM(PARAM_ATIMERx(ATIMERx)); - - //set power - if (ATIMERx== LPC_ATIMER) - { - /*Set Clock Here */ - CGU_EnableEntity(CGU_CLKSRC_32KHZ_OSC, ENABLE); - } - - ATIMER_UpdatePresetValue(ATIMERx, PresetValue); - // Clear interrupt pending - ATIMER_ClearIntStatus(ATIMERx); - -} - -/*********************************************************************//** - * @brief Close ATIMER device - * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER - * @return None - **********************************************************************/ -void ATIMER_DeInit (LPC_ATIMER_Type *ATIMERx) -{ - CHECK_PARAM(PARAM_ATIMERx(ATIMERx)); - // Disable atimer - ATIMER_ClearIntStatus(ATIMERx); - ATIMER_IntDisable(ATIMERx); - - // Disable power -// if (ATIMERx== LPC_ATIMER0) -// CGU_ConfigPPWR (CGU_PCONP_PCATIMER0, DISABLE); - -} - -/*********************************************************************//** - * @brief Clear ATIMER Interrupt Status - * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER - * @return None - **********************************************************************/ -void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx) -{ - CHECK_PARAM(PARAM_ATIMERx(ATIMERx)); - ATIMERx->CLR_STAT = 1; - while((ATIMERx->STATUS & 1) == 1); -} - -/*********************************************************************//** - * @brief Set ATIMER Interrupt Status - * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER - * @return None - **********************************************************************/ -void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx) -{ - CHECK_PARAM(PARAM_ATIMERx(ATIMERx)); - ATIMERx->SET_STAT = 1; - while((ATIMERx->STATUS & 1) == 0); -} - -/*********************************************************************//** - * @brief Enable ATIMER Interrupt - * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER - * @return None - **********************************************************************/ -void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx) -{ - CHECK_PARAM(PARAM_ATIMERx(ATIMERx)); - ATIMERx->SET_EN = 1; - while((ATIMERx->ENABLE & 1) == 0); -} - -/*********************************************************************//** - * @brief Disable ATIMER Interrupt - * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER - * @return None - **********************************************************************/ -void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx) -{ - CHECK_PARAM(PARAM_ATIMERx(ATIMERx)); - ATIMERx->CLR_EN = 1; - while((ATIMERx->ENABLE & 1) == 1); -} -/*********************************************************************//** - * @brief Update Preset value - * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER - * @param[in] PresetValue updated preset value - * @return None - **********************************************************************/ -void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue) -{ - CHECK_PARAM(PARAM_ATIMERx(ATIMERx)); - ATIMERx->PRESET = PresetValue; -} - -/*********************************************************************//** - * @brief Read value of preset register - * @param[in] ATIMERx Pointer to timer/counter device, should be: LPC_ATIMER - * @return Value of capture register - **********************************************************************/ -uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx) -{ - CHECK_PARAM(PARAM_ATIMERx(ATIMERx)); - return ATIMERx->PRESET; -} -/** - * @} - */ - -#endif /* _ATIMER */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_can.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_can.c deleted file mode 100644 index 4aa586539..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_can.c +++ /dev/null @@ -1,561 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_can.c 2011-06-02 -*//** -* @file lpc18xx_can.c -* @brief Contains all functions support for C CAN firmware library -* on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup C_CAN - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" -#include "lpc18xx_can.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _C_CAN - -/* Private Macros ---------------------------------------------------------- */ -#ifndef __GNUC__ -/* Macro for reading and writing to CCAN IF registers */ -#define CAN_IF_Read(reg, IFsel) (LPC_C_CAN0->##IFsel##_##reg) -#define CAN_IF_Write(reg, IFsel, val) (LPC_C_CAN0->##IFsel##_##reg=val) - -/* Macro for writing IF to specific RAM message object */ -#define CAN_IF_readBuf(IFsel,msg) \ - LPC_C_CAN0->##IFsel##_##CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \ - LPC_C_CAN0->##IFsel##_##CMDREQ=msg; \ - while (LPC_C_CAN0->##IFsel##_##CMDREQ & IFCREQ_BUSY ); - -/* Macro for reading specific RAM message object to IF */ -#define CAN_IF_writeBuf(IFsel,msg) \ - LPC_C_CAN0->##IFsel##_##CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \ - LPC_C_CAN0->##IFsel##_##CMDREQ=msg; \ - while (LPC_C_CAN0->##IFsel##_##CMDREQ & IFCREQ_BUSY ); -#else -#define CAN_IF_Read(reg, IFsel) (LPC_C_CAN0->IFsel##_##reg) -#define CAN_IF_Write(reg, IFsel, val) (LPC_C_CAN0->IFsel ## _ ## reg = val) - -/* Macro for writing IF to specific RAM message object */ -#define CAN_IF_readBuf(IFsel,msg) \ - LPC_C_CAN0->IFsel##_##CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \ - LPC_C_CAN0->IFsel##_##CMDREQ=msg; \ - while (LPC_C_CAN0->IFsel##_##CMDREQ & IFCREQ_BUSY ); - -/* Macro for reading specific RAM message object to IF */ -#define CAN_IF_writeBuf(IFsel,msg) \ - LPC_C_CAN0->IFsel##_##CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \ - LPC_C_CAN0->IFsel##_##CMDREQ=msg; \ - while (LPC_C_CAN0->IFsel##_##CMDREQ & IFCREQ_BUSY ); -#endif - -#define IF1 0 -#define IF2 1 - -#define CAN_STATUS_INTERRUPT 0x8000 /* 0x0001-0x0020 are the # of the message - object */ - /* 0x8000 is the status interrupt */ - -/* CAN Message interface register definitions */ -/* bit field of IF command request n register */ -#define IFCREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when - RD/WR done */ -/* CAN CTRL register */ -#define CTRL_INIT (1 << 0) -#define CTRL_IE (1 << 1) -#define CTRL_SIE (1 << 2) -#define CTRL_EIE (1 << 3) -#define CTRL_DAR (1 << 5) -#define CTRL_CCE (1 << 6) -#define CTRL_TEST (1 << 7) - -/* CAN Test register */ -#define TEST_BASIC (1 << 2) -#define TEST_SILENT (1 << 3) -#define TEST_LBACK (1 << 4) - -/* CAN Status register */ -#define STAT_LEC (0x7 << 0) -#define STAT_TXOK (1 << 3) -#define STAT_RXOK (1 << 4) -#define STAT_EPASS (1 << 5) -#define STAT_EWARN (1 << 6) -#define STAT_BOFF (1 << 7) - -#define NO_ERR 0 // No Error -#define STUFF_ERR 1 // Stuff Error : More than 5 equal bits in a sequence have occurred in a part - // of a received message where this is not allowed. -#define FORM_ERR 2 // Form Error : A fixed format part of a received frame has the wrong format. -#define ACK_ERR 3 // AckError : The message this CAN Core transmitted was not acknowledged - // by another node. -#define BIT1_ERR 4 // Bit1Error : During the transmission of a message (with the exception of - // the arbitration field), the device wanted to send a recessive level (bit of - // logical value �1�), but the monitored bus value was dominant. -#define BIT0_ERR 5 // Bit0Error : During the transmission of a message (or acknowledge bit, - // or active error flag, or overload flag), the device wanted to send a - // LOW/dominant level (data or identifier bit logical value �0�), but the - // monitored Bus value was HIGH/recessive. During busoff recovery this - // status is set each time a - // sequence of 11 HIGH/recessive bits has been monitored. This enables - // the CPU to monitor the proceeding of the busoff recovery sequence - // (indicating the bus is not stuck at LOW/dominant or continuously - // disturbed). -#define CRC_ERR 6 // CRCError: The CRC checksum was incorrect in the message received. - - -/* bit field of IF command mask register */ -#define DATAB (1 << 0) /* 1 is transfer data byte 4-7 to message object, 0 is not */ -#define DATAA (1 << 1) /* 1 is transfer data byte 0-3 to message object, 0 is not */ -#define NEWDAT (1 << 2) /* Clear NEWDAT bit in the message object */ -#define CLRINTPND (1 << 3) -#define CTRL (1 << 4) /* 1 is transfer the CTRL bit to the message object, 0 is not */ -#define ARB (1 << 5) /* 1 is transfer the ARB bits to the message object, 0 is not */ -#define MASK (1 << 6) /* 1 is transfer the MASK bit to the message object, 0 is not */ -#define WR (1 << 7) /* 0 is READ, 1 is WRITE */ -#define RD 0x0000 - -/* bit field of IF mask 2 register */ -#define MASK_MXTD (1 << 15) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */ -#define MASK_MDIR (1 << 14) /* 1 direction bit is used in the RX filter unit, 0 is not */ - -/* bit field of IF identifier 2 register */ -#define ID_MVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */ -#define ID_MTD (1 << 14) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */ -#define ID_DIR (1 << 13) /* 1 direction bit is used in the RX filter unit, 0 is not */ - -/* bit field of IF message control register */ -#define NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */ -#define MLST (1 << 14) /* 1 indicates a message loss. */ -#define INTP (1 << 13) /* 1 indicates message object is an interrupt source */ -#define UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */ -#define TXIE (1 << 11) /* 1 is TX interrupt enabled */ -#define RXIE (1 << 10) /* 1 is RX interrupt enabled */ - -#if REMOTE_ENABLE - #define RMTEN (1 << 9) /* 1 is remote frame enabled */ -#else - #define RMTEN 0 -#endif - -#define TXRQ (1 << 8) /* 1 is TxRqst enabled */ -#define EOB (1 << 7) /* End of buffer, always write to 1 */ -#define DLC 0x000F /* bit mask for DLC */ - -#define ID_STD_MASK 0x07FF -#define ID_EXT_MASK 0x1FFFFFFF -#define DLC_MASK 0x0F - -/* Private Variables ---------------------------------------------------------- */ -/* Statistics of all the interrupts */ -/* Buss off status counter */ -volatile uint32_t BOffCnt = 0; -/* Warning status counter. At least one of the error counters - in the EML has reached the error warning limit of 96 */ -volatile uint32_t EWarnCnt = 0; -/* More than 5 equal bits in a sequence in received message */ -volatile uint32_t StuffErrCnt = 0; -/* Wrong format of fixed format part of a received frame */ -volatile uint32_t FormErrCnt = 0; -/* Transmitted message not acknowledged. */ -volatile uint32_t AckErrCnt = 0; -/* Send a HIGH/recessive level, but monitored LOW/dominant */ -volatile uint32_t Bit1ErrCnt = 0; -/* Send a LOW/dominant level, but monitored HIGH/recessive */ -volatile uint32_t Bit0ErrCnt = 0; -/* The CRC checksum was incorrect in the message received */ -volatile uint32_t CRCErrCnt = 0; -/* Message object new data error counter */ -volatile uint32_t ND1ErrCnt = 0; - -MSG_CB TX_cb, RX_cb; - -message_object can_buff[CAN_MSG_OBJ_MAX]; -message_object recv_buff; - -#if CAN_DEBUG -uint32_t CANStatusLog[100]; -uint32_t CANStatusLogCount = 0; -#endif - -//#ifdef __GNUC__ -//uint32_t CAN_IF_Read(uint32_t reg,uint32_t IFsel){ -// if(IFsel == IF1){ -// return (LPC_C_CAN0->IF1_reg); -// }else{ -// return (LPC_C_CAN0->IF2_reg); -// } -//} -//void CAN_IF_Write(uint32_t reg, uint32_t IFsel,uint32_t val){ -// if(IFsel == IF1){ -// (LPC_C_CAN0->IF1_reg=val); -// }else{ -// (LPC_C_CAN0->IF2_reg=val); -// } -//} -// -///* Macro for writing IF to specific RAM message object */ -//void CAN_IF_readBuf(uint32_t IFsel,uint32_t msg){ -// if(IFsel == IF1){ -// LPC_C_CAN0->IF1_CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; -// LPC_C_CAN0->IF1_CMDREQ=msg; -// while (LPC_C_CAN0->IF1_CMDREQ & IFCREQ_BUSY ); -// }else{ -// LPC_C_CAN0->IF2_CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; -// LPC_C_CAN0->IF2_CMDREQ=msg; -// while (LPC_C_CAN0->IF2_CMDREQ & IFCREQ_BUSY ); -// } -// -//} -// -///* Macro for reading specific RAM message object to IF */ -//void CAN_IF_writeBuf(uint32_t IFsel,uint32_t msg){ -// if(IFsel == IF1){ -// LPC_C_CAN0->IF1_CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; -// LPC_C_CAN0->IF1_CMDREQ=msg; -// while (LPC_C_CAN0->IF1_CMDREQ & IFCREQ_BUSY ); -// }else{ -// LPC_C_CAN0->IF2_CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; -// LPC_C_CAN0->IF2_CMDREQ=msg; -// while (LPC_C_CAN0->IF2_CMDREQ & IFCREQ_BUSY ); -// } -//} -//#endif - -/*********************************************************************//** - * @brief Handle valid received message - * @param[in] msg_no Message Object number - * @return None - **********************************************************************/ -void CAN_RxInt_MessageProcess( uint8_t msg_no ) -{ - uint32_t msg_id; - uint32_t *p_add; - uint32_t reg1, reg2; - - /* Import message object to IF2 */ - CAN_IF_readBuf(IF2, msg_no); /* Read the message into the IF registers */ - - p_add = (uint32_t *)&recv_buff; - - if( CAN_IF_Read(ARB2, IF2) & ID_MTD ) /* bit 28-0 is 29 bit extended frame */ - { - /* mask off MsgVal and Dir */ - reg1 = CAN_IF_Read(ARB1, IF2); - reg2 = CAN_IF_Read(ARB2, IF2); - msg_id = (reg1|(reg2<<16)); - } - else - { - /* bit 28-18 is 11-bit standard frame */ - msg_id = (CAN_IF_Read(ARB2, IF2) &0x1FFF) >> 2; - } - - p_add[0] = msg_id; - p_add[1] = CAN_IF_Read(MCTRL, IF2) & 0x000F; /* Get Msg Obj Data length */ - p_add[2] = (CAN_IF_Read(DA2, IF2)<<16) | CAN_IF_Read(DA1, IF2); - p_add[3] = (CAN_IF_Read(DB2, IF2)<<16) | CAN_IF_Read(DB1, IF2); - - /* Clear interrupt pending bit */ - CAN_IF_Write(MCTRL, IF2, UMSK|RXIE|EOB|CAN_DLC_MAX); - /* Save changes to message RAM */ - CAN_IF_writeBuf(IF2, msg_no); - - return; -} -/*********************************************************************//** - * @brief Handle valid transmit message - * @param[in] msg_no Message Object number - * @return None - **********************************************************************/ -void CAN_TxInt_MessageProcess( uint8_t msg_no ) -{ - /* Clear interrupt pending bit */ - CAN_IF_Write(MCTRL, IF2, UMSK|RXIE|EOB|CAN_DLC_MAX); - /* Save changes to message RAM */ - CAN_IF_writeBuf(IF2,msg_no); - return; -} - -/*********************************************************************//** - * @brief CAN interrupt handler - * @param[in] None - * @return None - **********************************************************************/ -volatile uint32_t nd_tmp; -void CAN_IRQHandler(void) -{ - uint32_t canstat = 0; - uint32_t can_int, msg_no; - - while ( (can_int = LPC_C_CAN0->INT) != 0 ) /* While interrupt is pending */ - { - canstat = LPC_C_CAN0->STAT; /* Read CAN status register */ - - if ( can_int & CAN_STATUS_INTERRUPT ) - { - /* Passive state monitored frequently in main. */ - - if ( canstat & STAT_EWARN ) - { - EWarnCnt++; - return; - } - if ( canstat & STAT_BOFF ) - { - BOffCnt++; - return; - } - - switch (canstat&STAT_LEC) /* LEC Last Error Code (Type of the last error to occur on the CAN bus) */ - { - case NO_ERR: - break; - case STUFF_ERR: - StuffErrCnt++; - break; - case FORM_ERR: - FormErrCnt++; - break; - case ACK_ERR: - AckErrCnt++; - break; - case BIT1_ERR: - Bit1ErrCnt++; - break; - case BIT0_ERR: - Bit0ErrCnt++; - break; - case CRC_ERR: - CRCErrCnt++; - break; - default: - break; - } - - /* Clear all warning/error states except RXOK/TXOK */ - LPC_C_CAN0->STAT &= STAT_RXOK|STAT_TXOK; - } - else - { - if ( (canstat & STAT_LEC) == 0 ) /* NO ERROR */ - { - msg_no = can_int & 0x7FFF; - if((msg_no >= 1 ) && (msg_no <= 16)) - { - LPC_C_CAN0->STAT &= ~STAT_RXOK; - /* Check if message number is correct by reading NEWDAT registers. - By reading out the NEWDAT bits, the CPU can check for which Message - Object the data portion was updated - Only first 16 message object used for receive : only use ND1 */ - if((1<<(msg_no-1)) != LPC_C_CAN0->ND1) - { - /* message object does not contain new data! */ - ND1ErrCnt++; - break; - } - CAN_RxInt_MessageProcess(msg_no); - RX_cb(msg_no); - } - else - { - LPC_C_CAN0->STAT &= ~STAT_TXOK; - CAN_TxInt_MessageProcess(msg_no); - TX_cb(msg_no); - } - } - } - } - return; -} - -/*********************************************************************//** - * @brief Initialize CAN peripheral - * @param[in] BitClk CAN bit clock setting - * @param[in] ClkDiv CAN bit clock setting - * @param[in] Tx_cb point to call-back function when transmitted - * @param[in] Rx_cb point to call-back function when received - * @return None - **********************************************************************/ -void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb) -{ - - RX_cb = Rx_cb; - TX_cb = Tx_cb; - if ( !(LPC_C_CAN0->CNTL & CTRL_INIT) ) - { - /* If it's in normal operation already, stop it, reconfigure - everything first, then restart. */ - LPC_C_CAN0->CNTL |= CTRL_INIT; /* Default state */ - } - - LPC_C_CAN0->CLKDIV = ClkDiv; /* Divider for CAN VPB3 clock */ - LPC_C_CAN0->CNTL |= CTRL_CCE; /* Start configuring bit timing */ - LPC_C_CAN0->BT = BitClk; - LPC_C_CAN0->BRPE = 0x0000; - LPC_C_CAN0->CNTL &= ~CTRL_CCE; /* Stop configuring bit timing */ - - LPC_C_CAN0->CNTL &= ~CTRL_INIT; /* Initialization finished, normal operation now. */ - while ( LPC_C_CAN0->CNTL & CTRL_INIT ); - - /* By default, auto TX is enabled, enable all related interrupts */ - LPC_C_CAN0->CNTL |= (CTRL_IE|CTRL_SIE|CTRL_EIE); - return; -} - -/*********************************************************************//** - * @brief Send a message to the CAN port - * @param[in] msg_no message object number - * @param[in] msg_ptr msg buffer pointer - * @return None - **********************************************************************/ -void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr ) -{ - uint32_t tx_id, Length; - - if(msg_ptr == NULL) return; - - /* first is the ID, second is length, the next four are data */ - tx_id = *msg_ptr++; - Length = *msg_ptr++; - - if(Length>CAN_DLC_MAX)Length = CAN_DLC_MAX; - CAN_IF_Write(MCTRL, IF1, UMSK|TXIE|TXRQ|EOB|RMTEN|(Length & DLC_MASK)); - CAN_IF_Write(DA1, IF1, *msg_ptr); /* Lower two bytes of message pointer */ - CAN_IF_Write(DA2, IF1, (*msg_ptr++)>>16); /* Upper two bytes of message pointer */ - CAN_IF_Write(DB1, IF1, *msg_ptr); /* Lower two bytes of message pointer */ - CAN_IF_Write(DB2, IF1, (*msg_ptr)>>16); /* Upper two bytes of message pointer */ - - /* Configure arbitration */ - if(!(tx_id & (0x1<<30))) /* bit 30 is 0, standard frame */ - { - /* Mxtd: 0, Mdir: 1, Mask is 0x7FF */ - CAN_IF_Write(MSK2, IF1, MASK_MDIR | (ID_STD_MASK << 2)); - CAN_IF_Write(MSK1, IF1, 0x0000); - - /* MsgVal: 1, Mtd: 0, Dir: 1, ID = 0x200 */ - CAN_IF_Write(ARB1, IF1, 0x0000); - CAN_IF_Write(ARB2, IF1, ID_MVAL| ID_DIR | (tx_id << 2)); - } - else /* Extended frame */ - { - /* Mxtd: 1, Mdir: 1, Mask is 0x7FF */ - CAN_IF_Write(MSK2, IF1, MASK_MXTD | MASK_MDIR | (ID_EXT_MASK >> 16)); - CAN_IF_Write(MSK1, IF1, ID_EXT_MASK & 0x0000FFFF); - - /* MsgVal: 1, Mtd: 1, Dir: 1, ID = 0x200000 */ - CAN_IF_Write(ARB1, IF1, tx_id & 0x0000FFFF); - CAN_IF_Write(ARB2, IF1, ID_MVAL|ID_MTD | ID_DIR | (tx_id >> 16)); - } - - /* Write changes to message RAM */ - CAN_IF_writeBuf(IF1, msg_no); - - return; -} - -/*********************************************************************//** - * @brief Listen for a message on CAN bus - * @param[in] msg_no message object number - * @param[in] msg_ptr msg buffer pointer - * @param[in] RemoteEnable Enable/disable remote frame support, should be: - * - TRUE: enable - * - FALSE: disable - * @return None - **********************************************************************/ -void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable) -{ - uint32_t rx_id = *msg_ptr; - uint32_t rmten = 0; - if(RemoteEnable){ - rmten = 1<<8; - } - if(!(rx_id & (0x1<<30))){ /* standard frame */ - - /* Mxtd: 0, Mdir: 0, Mask is 0x7FF */ - CAN_IF_Write(MSK1, IF1, 0x0000); - CAN_IF_Write(MSK2, IF1, ID_STD_MASK << 2); - /* MsgVal: 1, Mtd: 0, Dir: 0 */ - CAN_IF_Write(ARB1, IF1, 0x0000); - CAN_IF_Write(MCTRL, IF1, rmten|UMSK|RXIE|EOB|CAN_DLC_MAX); - CAN_IF_Write(DA1, IF1, 0x0000); - CAN_IF_Write(DA2, IF1, 0x0000); - CAN_IF_Write(DB1, IF1, 0x0000); - CAN_IF_Write(DB2, IF1, 0x0000); - CAN_IF_Write(ARB2, IF1, ID_MVAL | ((rx_id) << 2)); - /* Transfer data to message RAM */ - CAN_IF_writeBuf(IF1, msg_no); - } - - else{ - rx_id &= (0x1<<30)-1 ; /* Mask ID bit */ - /* Mxtd: 1, Mdir: 0, Mask is 0x1FFFFFFF */ - CAN_IF_Write(MSK1, IF1, ID_EXT_MASK & 0xFFFF); - CAN_IF_Write(MSK2, IF1, MASK_MXTD | (ID_EXT_MASK >> 16)); - /* MsgVal: 1, Mtd: 1, Dir: 0 */ - CAN_IF_Write(ARB1, IF1, (rx_id) & 0xFFFF); - CAN_IF_Write(MCTRL, IF1, rmten|UMSK|RXIE|EOB|CAN_DLC_MAX); - CAN_IF_Write(DA1, IF1, 0x0000); - CAN_IF_Write(DA2, IF1, 0x0000); - CAN_IF_Write(DB1, IF1, 0x0000); - CAN_IF_Write(DB2, IF1, 0x0000); - CAN_IF_Write(ARB2, IF1, ID_MVAL | ID_MTD | ((rx_id) >> 16)); - /* Transfer data to message RAM */ - CAN_IF_writeBuf(IF1, msg_no); - } - return; -} - -/*********************************************************************//** - * @brief Read a message from Message RAM to buffer - * @param[in] msg_no message object number - * @param[in] buff msg buffer pointer - * @return None - **********************************************************************/ -void CAN_ReadMsg(uint32_t msg_no, message_object* buff){ - int i; - buff->id = recv_buff.id; - buff->dlc = recv_buff.dlc; - if(recv_buff.dlc>CAN_DLC_MAX) recv_buff.dlc = CAN_DLC_MAX; - for(i=0;idata[i] = recv_buff.data[i]; -} - -#endif /* _C_CAN*/ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_cgu.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_cgu.c deleted file mode 100644 index a2076474d..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_cgu.c +++ /dev/null @@ -1,916 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_cgu.c 2011-06-02 -*//** -* @file lpc18xx_cgu.c -* @brief Contains all functions support for Clock Generation and Control -* firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup CGU - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_types.h" -#include "lpc18xx_scu.h" -#include "lpc18xx_cgu.h" - -/** This define used to fix mistake when run with IAR compiler */ -#ifdef __ICCARM__ -#define CGU_BRANCH_STATUS_ENABLE_MASK 0x80000001 -#else -#define CGU_BRANCH_STATUS_ENABLE_MASK 0x01 -#endif - -/*TODO List: - * SET PLL0 - * UPDATE Clock from PLL0 - * SetDIV uncheck value - * GetBaseStatus BASE_SAFE - * */ -/* Local definition */ -#define CGU_ADDRESS32(x,y) (*(uint32_t*)((uint32_t)x+y)) - -/* Local Variable */ -const int16_t CGU_Entity_ControlReg_Offset[CGU_ENTITY_NUM] = { - -1, //CGU_CLKSRC_32KHZ_OSC, - -1, //CGU_CLKSRC_IRC, - -1, //CGU_CLKSRC_ENET_RX_CLK, - -1, //CGU_CLKSRC_ENET_TX_CLK, - -1, //CGU_CLKSRC_GP_CLKIN, - -1, //CGU_CLKSRC_TCK, - 0x18, //CGU_CLKSRC_XTAL_OSC, - 0x20, //CGU_CLKSRC_PLL0, - 0x30, //CGU_CLKSRC_PLL0_AUDIO **REV A** - 0x44, //CGU_CLKSRC_PLL1, - -1, //CGU_CLKSRC_RESERVE, - -1, //CGU_CLKSRC_RESERVE, - 0x48, //CGU_CLKSRC_IDIVA,, - 0x4C, //CGU_CLKSRC_IDIVB, - 0x50, //CGU_CLKSRC_IDIVC, - 0x54, //CGU_CLKSRC_IDIVD, - 0x58, //CGU_CLKSRC_IDIVE, - - 0x5C, //CGU_BASE_SAFE, - 0x60, //CGU_BASE_USB0, - -1, //CGU_BASE_RESERVE, - 0x68, //CGU_BASE_USB1, - 0x6C, //CGU_BASE_M3, - 0x70, //CGU_BASE_SPIFI, - -1, //CGU_BASE_RESERVE, - 0x78, //CGU_BASE_PHY_RX, - 0x7C, //CGU_BASE_PHY_TX, - 0x80, //CGU_BASE_APB1, - 0x84, //CGU_BASE_APB3, - 0x88, //CGU_BASE_LCD, - 0X8C, //CGU_BASE_ENET_CSR, **REV A** - 0x90, //CGU_BASE_SDIO, - 0x94, //CGU_BASE_SSP0, - 0x98, //CGU_BASE_SSP1, - 0x9C, //CGU_BASE_UART0, - 0xA0, //CGU_BASE_UART1, - 0xA4, //CGU_BASE_UART2, - 0xA8, //CGU_BASE_UART3, - 0xAC, //CGU_BASE_CLKOUT - -1, - -1, - -1, - -1, - 0xC0, //CGU_BASE_APLL - 0xC4, //CGU_BASE_OUT0 - 0xC8 //CGU_BASE_OUT1 -}; - -const uint8_t CGU_ConnectAlloc_Tbl[CGU_CLKSRC_NUM][CGU_ENTITY_NUM] = { -// 3 I E E G T X P P P x x D D D D D S U x U M S x P P A A L E S S S U U U U C x x x x A O O -// 2 R R T P C T L L L I I I I I A S S 3 P H H P P C N D S S R R R R O P U U -// C X X I K A 0 A 1 A B C D E F B B F RxTx1 3 D T I 0 1 0 1 2 3 L T T - {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_32KHZ_OSC = 0,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,1,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IRC,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_RX_CLK,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_TX_CLK,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_GP_CLKIN,*/ - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0},/*CGU_CLKSRC_TCK,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_XTAL_OSC,*/ - {0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,1},/*CGU_CLKSRC_PLL0,*/ - {0,0,0,0,0,0,0,0,0,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL0_AUDIO,*/ - {0,0,0,0,0,0,0,1,1,0,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL1,*/ - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,0,0,0,0,0,0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVB,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVC,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVD,*/ - {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1}/*CGU_CLKSRC_IDIVE,*/ -}; - -const CGU_PERIPHERAL_S CGU_PERIPHERAL_Info[CGU_PERIPHERAL_NUM] = { - /* Register Clock | Peripheral Clock - | BASE | BRANCH | BASE | BRANCH */ - {CGU_BASE_APB3, 0x1118, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC0, - {CGU_BASE_APB3, 0x1120, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC1, - {CGU_BASE_M3, 0x1460, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_AES, - //// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC, - {CGU_BASE_APB1, 0x1200, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB1_BUS, - {CGU_BASE_APB3, 0x1100, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB3_BUS, - {CGU_BASE_APB3, 0x1128, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CAN0, - {CGU_BASE_M3, 0x1538, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CREG, - {CGU_BASE_APB3, 0x1110, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DAC, - {CGU_BASE_M3, 0x1440, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DMA, - {CGU_BASE_M3, 0x1430, CGU_BASE_M3, 0x1478, 0},//CGU_PERIPHERAL_EMC, - {CGU_BASE_M3, 0x1420, CGU_BASE_PHY_RX, 0x0000, CGU_PERIPHERAL_ETHERNET_TX},//CGU_PERIPHERAL_ETHERNET, - {CGU_ENTITY_NONE,0x0000, CGU_BASE_PHY_TX, 0x0000, 0},//CGU_PERIPHERAL_ETHERNET_TX - {CGU_BASE_M3, 0x1410, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_GPIO, - {CGU_BASE_APB1, 0x1210, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C0, - {CGU_BASE_APB3, 0x1108, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C1, - {CGU_BASE_APB1, 0x1218, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2S, - {CGU_BASE_M3, 0x1418, CGU_BASE_LCD, 0x0000, 0},//CGU_PERIPHERAL_LCD, - {CGU_BASE_M3, 0x1448, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3CORE, - {CGU_BASE_M3, 0x1400, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3_BUS, - {CGU_BASE_APB1, 0x1208, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_MOTOCON, - {CGU_BASE_M3, 0x1630, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_QEI, - {CGU_BASE_M3, 0x1600, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_RITIMER, - {CGU_BASE_M3, 0x1468, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCT, - {CGU_BASE_M3, 0x1530, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCU, - {CGU_BASE_M3, 0x1438, CGU_BASE_SDIO, 0x2800, 0},//CGU_PERIPHERAL_SDIO, - {CGU_BASE_M3, 0x1408, CGU_BASE_SPIFI, 0x1300, 0},//CGU_PERIPHERAL_SPIFI, - {CGU_BASE_M3, 0x1518, CGU_BASE_SSP0, 0x2700, 0},//CGU_PERIPHERAL_SSP0, - {CGU_BASE_M3, 0x1628, CGU_BASE_SSP1, 0x2600, 0},//CGU_PERIPHERAL_SSP1, - {CGU_BASE_M3, 0x1520, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER0, - {CGU_BASE_M3, 0x1528, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER1, - {CGU_BASE_M3, 0x1618, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER2, - {CGU_BASE_M3, 0x1620, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER3, - {CGU_BASE_M3, 0x1508, CGU_BASE_UART0, 0x2500, 0},//CGU_PERIPHERAL_UART0, - {CGU_BASE_M3, 0x1510, CGU_BASE_UART1, 0x2400, 0},//CGU_PERIPHERAL_UART1, - {CGU_BASE_M3, 0x1608, CGU_BASE_UART2, 0x2300, 0},//CGU_PERIPHERAL_UART2, - {CGU_BASE_M3, 0x1610, CGU_BASE_UART3, 0x2200, 0},//CGU_PERIPHERAL_UART3, - {CGU_BASE_M3, 0x1428, CGU_BASE_USB0, 0x1800, 0},//CGU_PERIPHERAL_USB0, - {CGU_BASE_M3, 0x1470, CGU_BASE_USB1, 0x1900, 0},//CGU_PERIPHERAL_USB1, - {CGU_BASE_M3, 0x1500, CGU_BASE_SAFE, 0x0000, 0},//CGU_PERIPHERAL_WWDT, -}; - -uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM] = {0,12000000,0,0,0,0, 0, 480000000,0,0,0,0,0,0,0,0,0}; - -#define CGU_CGU_ADDR ((uint32_t)LPC_CGU) -#define CGU_REG_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].RegBaseEntity])) -#define CGU_REG_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset)) -#define CGU_REG_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4)) - -#define CGU_PER_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].PerBaseEntity])) -#define CGU_PER_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset)) -#define CGU_PER_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4)) - - -/*********************************************************************//** - * @brief Initialize default clock for LPC1800 Eval board - * @param[in] None - * @return Initialize status, could be: - * - CGU_ERROR_SUCCESS: successful - * - Other: error - **********************************************************************/ -uint32_t CGU_Init(void){ - CGU_SetXTALOSC(12000000); - CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); - CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1); - // Disable PLL1 CPU hang??? - //CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE); - CGU_SetPLL1(10); - CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE); - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3); - CGU_UpdateClock(); - return 0; -} - -/*********************************************************************//** - * @brief Configure power for individual peripheral - * @param[in] PPType peripheral type, should be: - * - CGU_PERIPHERAL_ADC0 :ADC0 - * - CGU_PERIPHERAL_ADC1 :ADC1 - * - CGU_PERIPHERAL_AES :AES - * - CGU_PERIPHERAL_APB1_BUS :APB1 bus - * - CGU_PERIPHERAL_APB3_BUS :APB3 bus - * - CGU_PERIPHERAL_CAN :CAN - * - CGU_PERIPHERAL_CREG :CREG - * - CGU_PERIPHERAL_DAC :DAC - * - CGU_PERIPHERAL_DMA :DMA - * - CGU_PERIPHERAL_EMC :EMC - * - CGU_PERIPHERAL_ETHERNET :ETHERNET - * - CGU_PERIPHERAL_GPIO :GPIO - * - CGU_PERIPHERAL_I2C0 :I2C0 - * - CGU_PERIPHERAL_I2C1 :I2C1 - * - CGU_PERIPHERAL_I2S :I2S - * - CGU_PERIPHERAL_LCD :LCD - * - CGU_PERIPHERAL_M3CORE :M3 core - * - CGU_PERIPHERAL_M3_BUS :M3 bus - * - CGU_PERIPHERAL_MOTOCON :Motor control - * - CGU_PERIPHERAL_QEI :QEI - * - CGU_PERIPHERAL_RITIMER :RIT timer - * - CGU_PERIPHERAL_SCT :SCT - * - CGU_PERIPHERAL_SCU :SCU - * - CGU_PERIPHERAL_SDIO :SDIO - * - CGU_PERIPHERAL_SPIFI :SPIFI - * - CGU_PERIPHERAL_SSP0 :SSP0 - * - CGU_PERIPHERAL_SSP1 :SSP1 - * - CGU_PERIPHERAL_TIMER0 :TIMER0 - * - CGU_PERIPHERAL_TIMER1 :TIMER1 - * - CGU_PERIPHERAL_TIMER2 :TIMER2 - * - CGU_PERIPHERAL_TIMER3 :TIMER3 - * - CGU_PERIPHERAL_UART0 :UART0 - * - CGU_PERIPHERAL_UART1 :UART1 - * - CGU_PERIPHERAL_UART2 :UART2 - * - CGU_PERIPHERAL_UART3 :UART3 - * - CGU_PERIPHERAL_USB0 :USB0 - * - CGU_PERIPHERAL_USB1 :USB1 - * - CGU_PERIPHERAL_WWDT :WWDT - * @param[in] en status, should be: - * - ENABLE: Enable power - * - DISABLE: Disable power - * @return Configure status, could be: - * - CGU_ERROR_SUCCESS: successful - * - Other: error - **********************************************************************/ -uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en){ - if(PPType >= CGU_PERIPHERAL_WWDT && PPType <= CGU_PERIPHERAL_ADC0) - return CGU_ERROR_INVALID_PARAM; - if(en == DISABLE){/* Going to disable clock */ - /*Get Reg branch status */ - if(CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0 && - CGU_REG_BRANCH_STATUS(PPType) & 1){ - CGU_REG_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */ - while(CGU_REG_BRANCH_STATUS(PPType) & 1); - } - /* GetBase Status*/ - if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) && - CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity) == 0){ - /* Disable Base */ - CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity,0); - } - - /* Same for Peripheral */ - if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){ - CGU_PER_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */ - while(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK); - } - /* GetBase Status*/ - if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity!=CGU_ENTITY_NONE) && - CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity) == 0){ - /* Disable Base */ - CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity,0); - } - }else{ - /* enable */ - /* GetBase Status*/ - if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) && CGU_REG_BASE_CTRL(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK){ - /* Enable Base */ - CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 1); - } - /*Get Reg branch status */ - if((CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){ - CGU_REG_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */ - while(!(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)); - } - - /* Same for Peripheral */ - /* GetBase Status*/ - if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) && - (CGU_PER_BASE_CTRL(PPType) & 1)){ - /* Enable Base */ - CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 1); - } - /*Get Reg branch status */ - if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){ - CGU_PER_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */ - while(!(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)); - } - - } - - if(CGU_PERIPHERAL_Info[PPType].next){ - return CGU_ConfigPWR((CGU_PERIPHERAL_T)CGU_PERIPHERAL_Info[PPType].next, en); - } - return CGU_ERROR_SUCCESS; -} - - -/*********************************************************************//** - * @brief Get peripheral clock frequency - * @param[in] Clock Peripheral type, should be: - * - CGU_PERIPHERAL_ADC0 :ADC0 - * - CGU_PERIPHERAL_ADC1 :ADC1 - * - CGU_PERIPHERAL_AES :AES - * - CGU_PERIPHERAL_APB1_BUS :APB1 bus - * - CGU_PERIPHERAL_APB3_BUS :APB3 bus - * - CGU_PERIPHERAL_CAN :CAN - * - CGU_PERIPHERAL_CREG :CREG - * - CGU_PERIPHERAL_DAC :DAC - * - CGU_PERIPHERAL_DMA :DMA - * - CGU_PERIPHERAL_EMC :EMC - * - CGU_PERIPHERAL_ETHERNET :ETHERNET - * - CGU_PERIPHERAL_GPIO :GPIO - * - CGU_PERIPHERAL_I2C0 :I2C0 - * - CGU_PERIPHERAL_I2C1 :I2C1 - * - CGU_PERIPHERAL_I2S :I2S - * - CGU_PERIPHERAL_LCD :LCD - * - CGU_PERIPHERAL_M3CORE :M3 core - * - CGU_PERIPHERAL_M3_BUS :M3 bus - * - CGU_PERIPHERAL_MOTOCON :Motor control - * - CGU_PERIPHERAL_QEI :QEI - * - CGU_PERIPHERAL_RITIMER :RIT timer - * - CGU_PERIPHERAL_SCT :SCT - * - CGU_PERIPHERAL_SCU :SCU - * - CGU_PERIPHERAL_SDIO :SDIO - * - CGU_PERIPHERAL_SPIFI :SPIFI - * - CGU_PERIPHERAL_SSP0 :SSP0 - * - CGU_PERIPHERAL_SSP1 :SSP1 - * - CGU_PERIPHERAL_TIMER0 :TIMER0 - * - CGU_PERIPHERAL_TIMER1 :TIMER1 - * - CGU_PERIPHERAL_TIMER2 :TIMER2 - * - CGU_PERIPHERAL_TIMER3 :TIMER3 - * - CGU_PERIPHERAL_UART0 :UART0 - * - CGU_PERIPHERAL_UART1 :UART1 - * - CGU_PERIPHERAL_UART2 :UART2 - * - CGU_PERIPHERAL_UART3 :UART3 - * - CGU_PERIPHERAL_USB0 :USB0 - * - CGU_PERIPHERAL_USB1 :USB1 - * - CGU_PERIPHERAL_WWDT :WWDT - * @return Return frequently value - **********************************************************************/ -uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock){ - uint32_t ClkSrc; - if(Clock >= CGU_PERIPHERAL_WWDT && Clock <= CGU_PERIPHERAL_ADC0) - return CGU_ERROR_INVALID_PARAM; - - if(CGU_PERIPHERAL_Info[Clock].PerBaseEntity != CGU_ENTITY_NONE){ - /* Get Base Clock Source */ - ClkSrc = (CGU_PER_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24; - /* GetBase Status*/ - if(CGU_PER_BASE_CTRL(Clock) & 1) - return 0; - /* check Branch if it is enabled */ - if((CGU_PERIPHERAL_Info[Clock].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0; - }else{ - if(CGU_REG_BASE_CTRL(Clock) & 1) return 0; - ClkSrc = (CGU_REG_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24; - /* check Branch if it is enabled */ - if((CGU_PERIPHERAL_Info[Clock].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0; - } - return CGU_ClockSourceFrequency[ClkSrc]; -} - - -/*********************************************************************//** - * @brief Update clock - * @param[in] None - * @return None - **********************************************************************/ -void CGU_UpdateClock(void){ - uint32_t ClkSrc; - uint32_t div; - uint32_t divisor; - int32_t RegOffset; - /* 32OSC */ - if(ISBITSET(LPC_CREG->CREG0,1) && ISBITCLR(LPC_CREG->CREG0,3)) - CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 32768; - else - CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 0; - /*PLL0*/ - /* PLL1 */ - if(ISBITCLR(LPC_CGU->PLL1_CTRL,1) /* Enabled */ - && (LPC_CGU->PLL1_STAT&1)){ /* Locked? */ - ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24; - CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = CGU_ClockSourceFrequency[ClkSrc] * - (((LPC_CGU->PLL1_CTRL>>16)&0xFF)+1); - }else - CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 0; - - /* DIV */ - for(div = CGU_CLKSRC_IDIVA; div <= CGU_CLKSRC_IDIVE; div++){ - RegOffset = CGU_Entity_ControlReg_Offset[div]; - if(ISBITCLR(CGU_ADDRESS32(LPC_CGU,RegOffset),1)){ - ClkSrc = (CGU_ADDRESS32(LPC_CGU,RegOffset) & CGU_CTRL_SRC_MASK) >> 24; - divisor = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>2) & 0xFF; - divisor ++; - CGU_ClockSourceFrequency[div] = CGU_ClockSourceFrequency[ClkSrc] / divisor; - }else - CGU_ClockSourceFrequency[div] = 0; - } -} - -/*********************************************************************//** - * @brief Set XTAL oscillator value - * @param[in] ClockFrequency XTAL Frequency value - * @return Setting status, could be: - * - CGU_ERROR_SUCCESS: successful - * - CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range - **********************************************************************/ -uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency){ - if(ClockFrequency < 15000000){ - LPC_CGU->XTAL_OSC_CTRL &= ~(1<<2); - }else if(ClockFrequency < 25000000){ - LPC_CGU->XTAL_OSC_CTRL |= (1<<2); - }else - return CGU_ERROR_FREQ_OUTOF_RANGE; - - CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = ClockFrequency; - return CGU_ERROR_SUCCESS; -} - - -/*********************************************************************//** - * @brief Set clock divider - * @param[in] SelectDivider Clock source, should be: - * - CGU_CLKSRC_IDIVA :Integer divider register A - * - CGU_CLKSRC_IDIVB :Integer divider register B - * - CGU_CLKSRC_IDIVC :Integer divider register C - * - CGU_CLKSRC_IDIVD :Integer divider register D - * - CGU_CLKSRC_IDIVE :Integer divider register E - * @param[in] divisor Divisor value, should be: 0..255 - * @return Setting status, could be: - * - CGU_ERROR_SUCCESS: successful - * - CGU_ERROR_INVALID_ENTITY: Invalid entity - **********************************************************************/ -/* divisor number must >=1*/ -uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor){ - int32_t RegOffset; - uint32_t tempReg; - if(SelectDivider>=CGU_CLKSRC_IDIVA && SelectDivider<=CGU_CLKSRC_IDIVE){ - RegOffset = CGU_Entity_ControlReg_Offset[SelectDivider]; - if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY; - tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset); - tempReg &= ~(0xFF<<2); - tempReg |= ((divisor-1)&0xFF)<<2; - CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg; - return CGU_ERROR_SUCCESS; - } - return CGU_ERROR_INVALID_ENTITY; -} - -/*********************************************************************//** - * @brief Enable clock entity - * @param[in] ClockEntity Clock entity, should be: - * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator - * - CGU_CLKSRC_IRC :IRC clock - * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock - * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock - * - CGU_CLKSRC_GP_CLKIN :General purpose input clock - * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator - * - CGU_CLKSRC_PLL0 :PLL0 clock - * - CGU_CLKSRC_PLL1 :PLL1 clock - * - CGU_CLKSRC_IDIVA :Integer divider register A - * - CGU_CLKSRC_IDIVB :Integer divider register B - * - CGU_CLKSRC_IDIVC :Integer divider register C - * - CGU_CLKSRC_IDIVD :Integer divider register D - * - CGU_CLKSRC_IDIVE :Integer divider register E - * - CGU_BASE_SAFE :Base safe clock (always on)for WDT - * - CGU_BASE_USB0 :Base clock for USB0 - * - CGU_BASE_USB1 :Base clock for USB1 - * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core - * and APB peripheral blocks #0 and #2 - * - CGU_BASE_SPIFI :Base clock for SPIFI - * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx - * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx - * - CGU_BASE_APB1 :Base clock for APB peripheral block #1 - * - CGU_BASE_APB3 :Base clock for APB peripheral block #3 - * - CGU_BASE_LCD :Base clock for LCD - * - CGU_BASE_SDIO :Base clock for SDIO card reader - * - CGU_BASE_SSP0 :Base clock for SSP0 - * - CGU_BASE_SSP1 :Base clock for SSP1 - * - CGU_BASE_UART0 :Base clock for UART0 - * - CGU_BASE_UART1 :Base clock for UART1 - * - CGU_BASE_UART2 :Base clock for UART2 - * - CGU_BASE_UART3 :Base clock for UART3 - * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin - * @param[in] en status, should be: - * - ENABLE: Enable power - * - DISABLE: Disable power - * @return Setting status, could be: - * - CGU_ERROR_SUCCESS: successful - * - CGU_ERROR_INVALID_ENTITY: Invalid entity - **********************************************************************/ -uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en){ - int32_t RegOffset; - int32_t i; - if(ClockEntity == CGU_CLKSRC_32KHZ_OSC){ - if(en){ - LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); - LPC_CREG->CREG0 |= (1<<1)|(1<<0); - }else{ - LPC_CREG->CREG0 &= ~((1<<1)|(1<<0)); - LPC_CREG->CREG0 |= (1<<3); - } - for(i = 0;i<1000000;i++); - - }else if(ClockEntity == CGU_CLKSRC_ENET_RX_CLK){ - scu_pinmux(0xC ,0 , MD_PLN, FUNC3); - - }else if(ClockEntity == CGU_CLKSRC_ENET_TX_CLK){ - scu_pinmux(0x1 ,19 , MD_PLN, FUNC0); - - }else if(ClockEntity == CGU_CLKSRC_GP_CLKIN){ - - }else if(ClockEntity == CGU_CLKSRC_TCK){ - - }else if(ClockEntity == CGU_CLKSRC_XTAL_OSC){ - if(!en) - LPC_CGU->XTAL_OSC_CTRL |= CGU_CTRL_EN_MASK; - else - LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK; - /*Delay for stable clock*/ - for(i = 0;i<1000000;i++); - - }else{ - RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity]; - if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY; - if(!en){ - CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) |= CGU_CTRL_EN_MASK; - }else{ - CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) &= ~CGU_CTRL_EN_MASK; - /*if PLL is selected check if it is locked */ - if(ClockEntity == CGU_CLKSRC_PLL0){ - while((LPC_CGU->PLL0USB_STAT&1) == 0x0); - } - if(ClockEntity == CGU_CLKSRC_PLL1){ - while((LPC_CGU->PLL1_STAT&1) == 0x0); - /*post check lock status */ - if(!(LPC_CGU->PLL1_STAT&1)) - while(1); - } - } - } - return CGU_ERROR_SUCCESS; -} - -/*********************************************************************//** - * @brief Connect entity clock source - * @param[in] ClockSource Clock source, should be: - * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator - * - CGU_CLKSRC_IRC :IRC clock - * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock - * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock - * - CGU_CLKSRC_GP_CLKIN :General purpose input clock - * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator - * - CGU_CLKSRC_PLL0 :PLL0 clock - * - CGU_CLKSRC_PLL1 :PLL1 clock - * - CGU_CLKSRC_IDIVA :Integer divider register A - * - CGU_CLKSRC_IDIVB :Integer divider register B - * - CGU_CLKSRC_IDIVC :Integer divider register C - * - CGU_CLKSRC_IDIVD :Integer divider register D - * - CGU_CLKSRC_IDIVE :Integer divider register E - * @param[in] ClockEntity Clock entity, should be: - * - CGU_CLKSRC_PLL0 :PLL0 clock - * - CGU_CLKSRC_PLL1 :PLL1 clock - * - CGU_CLKSRC_IDIVA :Integer divider register A - * - CGU_CLKSRC_IDIVB :Integer divider register B - * - CGU_CLKSRC_IDIVC :Integer divider register C - * - CGU_CLKSRC_IDIVD :Integer divider register D - * - CGU_CLKSRC_IDIVE :Integer divider register E - * - CGU_BASE_SAFE :Base safe clock (always on)for WDT - * - CGU_BASE_USB0 :Base clock for USB0 - * - CGU_BASE_USB1 :Base clock for USB1 - * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core - * and APB peripheral blocks #0 and #2 - * - CGU_BASE_SPIFI :Base clock for SPIFI - * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx - * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx - * - CGU_BASE_APB1 :Base clock for APB peripheral block #1 - * - CGU_BASE_APB3 :Base clock for APB peripheral block #3 - * - CGU_BASE_LCD :Base clock for LCD - * - CGU_BASE_SDIO :Base clock for SDIO card reader - * - CGU_BASE_SSP0 :Base clock for SSP0 - * - CGU_BASE_SSP1 :Base clock for SSP1 - * - CGU_BASE_UART0 :Base clock for UART0 - * - CGU_BASE_UART1 :Base clock for UART1 - * - CGU_BASE_UART2 :Base clock for UART2 - * - CGU_BASE_UART3 :Base clock for UART3 - * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin - * @return Setting status, could be: - * - CGU_ERROR_SUCCESS: successful - * - CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together - * - CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error - * - CGU_ERROR_INVALID_ENTITY: Invalid entity error - **********************************************************************/ -/* Connect one entity into clock source */ -uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity){ - int32_t RegOffset; - uint32_t tempReg; - - if(ClockSource > CGU_CLKSRC_IDIVE) - return CGU_ERROR_INVALID_CLOCK_SOURCE; - - if(ClockEntity >= CGU_CLKSRC_PLL0 && ClockEntity <= CGU_BASE_CLKOUT){ - if(CGU_ConnectAlloc_Tbl[ClockSource][ClockEntity]){ - RegOffset = CGU_Entity_ControlReg_Offset[ClockSource]; - if(RegOffset != -1){ - if(ClockEntity<=CGU_CLKSRC_IDIVE && - ClockEntity>=CGU_CLKSRC_PLL0) - { - //RegOffset = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)&0xF; - if(((CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)& 0xF) == ClockEntity) - return CGU_ERROR_CONNECT_TOGETHER; - } - } - RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity]; - if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY; - tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset); - tempReg &= ~CGU_CTRL_SRC_MASK; - tempReg |= ClockSource<<24 | CGU_CTRL_AUTOBLOCK_MASK; - CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg; - return CGU_ERROR_SUCCESS; - }else - return CGU_ERROR_INVALID_CLOCK_SOURCE; - }else - return CGU_ERROR_INVALID_ENTITY; -} - - -/*********************************************************************//** - * @brief Get current USB PLL clock from XTAL - * @param[in] None - * @return Returned clock value - **********************************************************************/ -uint32_t CGU_SetPLL0(void){ - // Setup PLL550 to generate 480MHz from 12 MHz crystal - LPC_CGU->PLL0USB_CTRL |= 1; // Power down PLL - // P N - LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12); - // SELP SELI SELR MDEC - LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0); - LPC_CGU->PLL0USB_CTRL =(CGU_CLKSRC_XTAL_OSC<<24) | (0x3<<2) | (1<<4); - return CGU_ERROR_SUCCESS; -} - - -/*********************************************************************//** - * @brief Setting PLL1 - * @param[in] mult Multiple value - * @return Setting status, could be: - * - CGU_ERROR_SUCCESS: successful - * - CGU_ERROR_INVALID_PARAM: Invalid parameter error - **********************************************************************/ -uint32_t CGU_SetPLL1(uint32_t mult){ - uint32_t msel=0, nsel=0, psel=0, pval=1; - uint32_t freq; - uint32_t ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24; - freq = CGU_ClockSourceFrequency[ClkSrc]; - freq *= mult; - msel = mult-1; - - LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK | - CGU_PLL1_BYPASS_MASK | - CGU_PLL1_DIRECT_MASK | - (0x03<<8) | (0xFF<<16) | (0x03<<12)); - - if(freq<156000000){ - //psel is encoded such that 0=1, 1=2, 2=4, 3=8 - while(2*(pval)*freq < 156000000) { - psel++; - pval*=2; - } -// if(2*(pval)*freq > 320000000) { -// //THIS IS OUT OF RANGE!!! -// //HOW DO WE ASSERT IN SAMPLE CODE? -// //__breakpoint(0); -// return CGU_ERROR_INVALID_PARAM; -// } - LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) | CGU_PLL1_FBSEL_MASK; - }else if(freq<320000000){ - LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) |CGU_PLL1_DIRECT_MASK | CGU_PLL1_FBSEL_MASK; - }else - return CGU_ERROR_INVALID_PARAM; - - return CGU_ERROR_SUCCESS; -} - - -/*********************************************************************//** - * @brief Get current base status - * @param[in] Base Base type, should be: - * - CGU_BASE_USB0 :Base clock for USB0 - * - CGU_BASE_USB1 :Base clock for USB1 - * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core - * and APB peripheral blocks #0 and #2 - * - CGU_BASE_SPIFI :Base clock for SPIFI - * - CGU_BASE_APB1 :Base clock for APB peripheral block #1 - * - CGU_BASE_APB3 :Base clock for APB peripheral block #3 - * - CGU_BASE_SDIO :Base clock for SDIO card reader - * - CGU_BASE_SSP0 :Base clock for SSP0 - * - CGU_BASE_SSP1 :Base clock for SSP1 - * - CGU_BASE_UART0 :Base clock for UART0 - * - CGU_BASE_UART1 :Base clock for UART1 - * - CGU_BASE_UART2 :Base clock for UART2 - * - CGU_BASE_UART3 :Base clock for UART3 - * @return Always return 0 - **********************************************************************/ -uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base){ - switch(Base){ - /*CCU1*/ - case CGU_BASE_APB3: - return LPC_CCU1->BASE_STAT & 1; - - case CGU_BASE_APB1: - return (LPC_CCU1->BASE_STAT>>1) & 1; - - case CGU_BASE_SPIFI: - return (LPC_CCU1->BASE_STAT>>2) & 1; - - case CGU_BASE_M3: - return (LPC_CCU1->BASE_STAT>>3) & 1; - - case CGU_BASE_USB0: - return (LPC_CCU1->BASE_STAT>>7) & 1; - - case CGU_BASE_USB1: - return (LPC_CCU1->BASE_STAT>>8) & 1; - - /*CCU2*/ - case CGU_BASE_UART3: - return (LPC_CCU2->BASE_STAT>>1) & 1; - - case CGU_BASE_UART2: - return (LPC_CCU2->BASE_STAT>>2) & 1; - - case CGU_BASE_UART1: - return (LPC_CCU2->BASE_STAT>>3) & 1; - - case CGU_BASE_UART0: - return (LPC_CCU2->BASE_STAT>>4) & 1; - - case CGU_BASE_SSP1: - return (LPC_CCU2->BASE_STAT>>5) & 1; - - case CGU_BASE_SSP0: - return (LPC_CCU2->BASE_STAT>>6) & 1; - - case CGU_BASE_SDIO: - return (LPC_CCU2->BASE_STAT>>7) & 1; - - /*BASE SAFE is used by WWDT and RGU*/ - case CGU_BASE_SAFE: - break; - default: - break; - } - return 0; -} - - -/*********************************************************************//** - * @brief Compare one source clock to IRC clock - * @param[in] Clock Clock entity that will be compared to IRC, should be: - * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator - * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock - * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock - * - CGU_CLKSRC_GP_CLKIN :General purpose input clock - * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator - * - CGU_CLKSRC_PLL0 :PLL0 clock - * - CGU_CLKSRC_PLL1 :PLL1 clock - * - CGU_CLKSRC_IDIVA :Integer divider register A - * - CGU_CLKSRC_IDIVB :Integer divider register B - * - CGU_CLKSRC_IDIVC :Integer divider register C - * - CGU_CLKSRC_IDIVD :Integer divider register D - * - CGU_CLKSRC_IDIVE :Integer divider register E - * - CGU_BASE_SAFE :Base safe clock (always on)for WDT - * - CGU_BASE_USB0 :Base clock for USB0 - * - CGU_BASE_USB1 :Base clock for USB1 - * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core - * and APB peripheral blocks #0 and #2 - * - CGU_BASE_SPIFI :Base clock for SPIFI - * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx - * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx - * - CGU_BASE_APB1 :Base clock for APB peripheral block #1 - * - CGU_BASE_APB3 :Base clock for APB peripheral block #3 - * - CGU_BASE_LCD :Base clock for LCD - * - CGU_BASE_SDIO :Base clock for SDIO card reader - * - CGU_BASE_SSP0 :Base clock for SSP0 - * - CGU_BASE_SSP1 :Base clock for SSP1 - * - CGU_BASE_UART0 :Base clock for UART0 - * - CGU_BASE_UART1 :Base clock for UART1 - * - CGU_BASE_UART2 :Base clock for UART2 - * - CGU_BASE_UART3 :Base clock for UART3 - * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin - * @param[in] m Multiple value pointer - * @param[in] d Divider value pointer - * @return Compare status, could be: - * - (-1): fail - * - 0: successful - * @note Formula used to compare: - * FClock = F_IRC* m / d - **********************************************************************/ -int CGU_FrequencyMonitor(CGU_ENTITY_T Clock, uint32_t *m, uint32_t *d){ - uint32_t n,c,temp; - int i; - - /* Maximum allow RCOUNT number */ - c= 511; - /* Check Source Clock Freq is larger or smaller */ - LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c; - while(LPC_CGU->FREQ_MON & (1 <<23)); - for(i=0;i<10000;i++); - temp = (LPC_CGU->FREQ_MON >>9) & 0x3FFF; - - if(temp == 0) /* too low F < 12000000/511*/ - return -1; - if(temp > 511){ /* larger */ - - c = 511 - (LPC_CGU->FREQ_MON&0x1FF); - }else{ - do{ - c--; - LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c; - while(LPC_CGU->FREQ_MON & (1 <<23)); - for(i=0;i<10000;i++); - n = (LPC_CGU->FREQ_MON >>9) & 0x3FFF; - }while(n==temp); - c++; - } - *m = temp; - *d = c; - return 0; -} - -/*********************************************************************//** - * @brief Compare one source clock to another source clock - * @param[in] Clock Clock entity that will be compared to second source, should be: - * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator - * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock - * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock - * - CGU_CLKSRC_GP_CLKIN :General purpose input clock - * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator - * - CGU_CLKSRC_PLL0 :PLL0 clock - * - CGU_CLKSRC_PLL1 :PLL1 clock - * - CGU_CLKSRC_IDIVA :Integer divider register A - * - CGU_CLKSRC_IDIVB :Integer divider register B - * - CGU_CLKSRC_IDIVC :Integer divider register C - * - CGU_CLKSRC_IDIVD :Integer divider register D - * - CGU_CLKSRC_IDIVE :Integer divider register E - * - CGU_BASE_SAFE :Base safe clock (always on)for WDT - * - CGU_BASE_USB0 :Base clock for USB0 - * - CGU_BASE_USB1 :Base clock for USB1 - * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core - * and APB peripheral blocks #0 and #2 - * - CGU_BASE_SPIFI :Base clock for SPIFI - * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx - * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx - * - CGU_BASE_APB1 :Base clock for APB peripheral block #1 - * - CGU_BASE_APB3 :Base clock for APB peripheral block #3 - * - CGU_BASE_LCD :Base clock for LCD - * - CGU_BASE_SDIO :Base clock for SDIO card reader - * - CGU_BASE_SSP0 :Base clock for SSP0 - * - CGU_BASE_SSP1 :Base clock for SSP1 - * - CGU_BASE_UART0 :Base clock for UART0 - * - CGU_BASE_UART1 :Base clock for UART1 - * - CGU_BASE_UART2 :Base clock for UART2 - * - CGU_BASE_UART3 :Base clock for UART3 - * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin - * @param[in] CompareToClock Clock source that to be compared to first source, should be different - * to first source. - * @param[in] m Multiple value pointer - * @param[in] d Divider value pointer - * @return Compare status, could be: - * - (-1): fail - * - 0: successful - * @note Formula used to compare: - * FClock = m*FCompareToClock/d - **********************************************************************/ -uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d){ - uint32_t m1,m2,d1,d2; - /* Check Parameter */ - if((Clock>CGU_CLKSRC_IDIVE) || (CompareToClock>CGU_CLKSRC_IDIVE)) - return CGU_ERROR_INVALID_PARAM; - /* Check for Clock Enable - Not yet implement - * The Comparator will hang if Clock has not been set*/ - CGU_FrequencyMonitor(Clock, &m1, &d1); - CGU_FrequencyMonitor(CompareToClock, &m2, &d2); - *m= m1*d2; - *d= d1*m2; - return 0; - -} -/** - * @} - */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_dac.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_dac.c deleted file mode 100644 index 11e86d91f..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_dac.c +++ /dev/null @@ -1,147 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_dac.c 2011-06-02 -*//** -* @file lpc18xx_dac.c -* @brief Contains all functions support for DAC firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup DAC - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_dac.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _DAC - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup DAC_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Initial ADC configuration - * - Maximum current is 700 uA - * - Value to AOUT is 0 - * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC - * @return None - ***********************************************************************/ -void DAC_Init(LPC_DAC_Type *DACx) -{ - CHECK_PARAM(PARAM_DACx(DACx)); - /* Set default clock divider for DAC */ - //LPC_CGU->BASE_VPB3_CLK = (SRC_PL160M_0<<24) | (1<<11); // ABP3 base clock use PLL1 and auto block - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB3); - //Set maximum current output - DAC_SetBias(LPC_DAC,DAC_MAX_CURRENT_700uA); -} - -/*********************************************************************//** - * @brief Update value to DAC - * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC - * @param[in] dac_value value 10 bit to be converted to output - * @return None - ***********************************************************************/ -void DAC_UpdateValue (LPC_DAC_Type *DACx,uint32_t dac_value) -{ - uint32_t tmp; - CHECK_PARAM(PARAM_DACx(DACx)); - tmp = DACx->CR & DAC_BIAS_EN; - tmp |= DAC_VALUE(dac_value); - // Update value - DACx->CR = tmp; -} - -/*********************************************************************//** - * @brief Set Maximum current for DAC - * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC - * @param[in] bias Using Bias value, should be: - * - 0 is 700 uA - * - 1 is 350 uA - * @return None - ***********************************************************************/ -void DAC_SetBias (LPC_DAC_Type *DACx,uint32_t bias) -{ - CHECK_PARAM(PARAM_DAC_CURRENT_OPT(bias)); - DACx->CR &=~DAC_BIAS_EN; - if (bias == DAC_MAX_CURRENT_350uA) - { - DACx->CR |= DAC_BIAS_EN; - } -} - -/*********************************************************************//** - * @brief To enable the DMA operation and control DMA timer - * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC - * @param[in] DAC_ConverterConfigStruct pointer to DAC_CONVERTER_CFG_Type - * - DBLBUF_ENA :enable/disable DACR double buffering feature - * - CNT_ENA :enable/disable timer out counter - * - DMA_ENA :enable/disable DMA access - * @return None - ***********************************************************************/ -void DAC_ConfigDAConverterControl (LPC_DAC_Type *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct) -{ - CHECK_PARAM(PARAM_DACx(DACx)); - DACx->CTRL &= ~DAC_DACCTRL_MASK; - if (DAC_ConverterConfigStruct->DBLBUF_ENA) - DACx->CTRL |= DAC_DBLBUF_ENA; - if (DAC_ConverterConfigStruct->CNT_ENA) - DACx->CTRL |= DAC_CNT_ENA; - if (DAC_ConverterConfigStruct->DMA_ENA) - DACx->CTRL |= DAC_DMA_ENA; -} - -/*********************************************************************//** - * @brief Set reload value for interrupt/DMA counter - * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC - * @param[in] time_out time out to reload for interrupt/DMA counter - * @return None - ***********************************************************************/ -void DAC_SetDMATimeOut(LPC_DAC_Type *DACx, uint32_t time_out) -{ - CHECK_PARAM(PARAM_DACx(DACx)); - DACx->CNTVAL = DAC_CCNT_VALUE(time_out); -} - -/** - * @} - */ - -#endif /* _DAC */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_emc.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_emc.c deleted file mode 100644 index 88dadbf2e..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_emc.c +++ /dev/null @@ -1,233 +0,0 @@ -/********************************************************************** -* $Id: lpc18xx_emc.c 8765 2011-12-08 00:51:21Z nxp21346 $ lpc18xx_emc.c 2011-12-07 -*//** -* @file lpc18xx_emc.c -* @brief Contains all functions support for Clock Generation and Control -* firmware library on lpc18xx -* @version 1.0 -* @date 07. December. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#include "LPC18xx.h" -#include "lpc18xx_emc.h" -#include "lpc18xx_scu.h" - -#define M32(x) *((uint32_t *)x) -#define DELAYCYCLES(ns) (ns / ((1.0 / __EMCHZ) * 1E9)) - -void emc_WaitUS(volatile uint32_t us) -{ - us *= (SystemCoreClock / 1000000) / 3; - while(us--); -} - -void emc_WaitMS(uint32_t ms) -{ - emc_WaitUS(ms * 1000); -} - -void MemoryPinInit(void) -{ - /* select correct functions on the GPIOs */ - -#if 1 - /* DATA LINES 0..31 > D0..D31 */ - /* P1_7 - EXTBUS_D0 — External memory data line 0 */ - scu_pinmux(0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_7: D0 (function 0) errata */ - scu_pinmux(0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_8: D1 (function 0) errata */ - scu_pinmux(0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_9: D2 (function 0) errata */ - scu_pinmux(0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_10: D3 (function 0) errata */ - scu_pinmux(0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_11: D4 (function 0) errata */ - scu_pinmux(0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_12: D5 (function 0) errata */ - scu_pinmux(0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_13: D6 (function 0) errata */ - scu_pinmux(0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_14: D7 (function 0) errata */ - scu_pinmux(0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_4: D8 (function 0) errata */ - scu_pinmux(0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_5: D9 (function 0) errata */ - scu_pinmux(0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_6: D10 (function 0) errata */ - scu_pinmux(0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_7: D11 (function 0) errata */ - scu_pinmux(0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_0: D12 (function 0) errata */ - scu_pinmux(0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_1: D13 (function 0) errata */ - scu_pinmux(0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_2: D14 (function 0) errata */ - scu_pinmux(0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_3: D15 (function 0) errata */ -#if 0 - scu_pinmux(0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_2: D16 (function 0) errata */ - scu_pinmux(0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_3: D17 (function 0) errata */ - scu_pinmux(0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_4: D18 (function 0) errata */ - scu_pinmux(0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_5: D19 (function 0) errata */ - scu_pinmux(0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_6: D20 (function 0) errata */ - scu_pinmux(0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_7: D21 (function 0) errata */ - scu_pinmux(0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_8: D22 (function 0) errata */ - scu_pinmux(0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_9: D23 (function 0) errata */ - scu_pinmux(0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_5: D24 (function 0) errata */ - scu_pinmux(0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_6: D25 (function 0) errata */ - scu_pinmux(0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_7: D26 (function 0) errata */ - scu_pinmux(0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_8: D27 (function 0) errata */ - scu_pinmux(0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_9: D28 (function 0) errata */ - scu_pinmux(0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_10: D29 (function 0) errata */ - scu_pinmux(0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_11: D30 (function 0) errata */ - scu_pinmux(0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_12: D31 (function 0) errata */ -#endif - - /* ADDRESS LINES A0..A11 > A0..A11 */ - scu_pinmux(0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_9 - EXTBUS_A0 — External memory address line 0 */ - scu_pinmux(0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_10 - EXTBUS_A1 — External memory address line 1 */ - scu_pinmux(0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_11 - EXTBUS_A2 — External memory address line 2 */ - scu_pinmux(0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_12 - EXTBUS_A3 — External memory address line 3 */ - scu_pinmux(0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_13 - EXTBUS_A4 — External memory address line 4 */ - scu_pinmux(0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_0 - EXTBUS_A5 — External memory address line 5 */ - scu_pinmux(0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_1 - EXTBUS_A6 — External memory address line 6 */ - scu_pinmux(0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_2 - EXTBUS_A7 — External memory address line 7 */ - scu_pinmux(0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_8 - EXTBUS_A8 — External memory address line 8 */ - scu_pinmux(0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_7 - EXTBUS_A9 — External memory address line 9 */ - scu_pinmux(0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_6 - EXTBUS_A10 — External memory address line 10 */ - scu_pinmux(0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_2 - EXTBUS_A11 — External memory address line 11 */ - scu_pinmux(0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_1 - EXTBUS_A12 — External memory address line 12 */ - scu_pinmux(0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_0 - EXTBUS_A13 — External memory address line 13 */ - scu_pinmux(0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_8 - EXTBUS_A14 — External memory address line 14 */ - scu_pinmux(0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_7 - EXTBUS_A15 — External memory address line 15 */ - scu_pinmux(0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_16 - EXTBUS_A16 — External memory address line 16 */ - scu_pinmux(0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_15 - EXTBUS_A17 — External memory address line 17 */ - scu_pinmux(0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_0 - EXTBUS_A18 — External memory address line 18 */ - scu_pinmux(0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_1 - EXTBUS_A19 — External memory address line 19 */ - scu_pinmux(0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_2 - EXTBUS_A20 — External memory address line 20 */ - scu_pinmux(0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_3 - EXTBUS_A21 — External memory address line 21 */ - scu_pinmux(0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_4 - EXTBUS_A22 — External memory address line 22 */ - scu_pinmux(0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PA_4 - EXTBUS_A23 — External memory address line 23 */ - - /* BYTE ENABLES */ - scu_pinmux(0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_4 - EXTBUS_BLS0 — LOW active Byte Lane select signal 0 */ - scu_pinmux(0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_6 - EXTBUS_BLS1 — LOW active Byte Lane select signal 1 */ - scu_pinmux(0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_13 - EXTBUS_BLS2 — LOW active Byte Lane select signal 2 */ - scu_pinmux(0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_10 - EXTBUS_BLS3 — LOW active Byte Lane select signal 3 */ - - scu_pinmux(0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_9: EXTBUS_DYCS0 (function 0) > CS# errata */ - scu_pinmux(0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_6: WE (function 0) errata */ - scu_pinmux(0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_4: CAS (function 0) > CAS# errata */ - scu_pinmux(0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_5: RAS (function 0) > RAS# errata */ - - LPC_SCU_CLK(0) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK0: EXTBUS_CLK0 (function 0, from datasheet) > CLK ds */ - LPC_SCU_CLK(1) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK1: EXTBUS_CLK1 (function 2, from datasheet) */ - LPC_SCU_CLK(2) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK2: EXTBUS_CLK2 (function 2, from datasheet) */ - LPC_SCU_CLK(3) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK3: EXTBUS_CLK3 (function 2, from datasheet) */ - - scu_pinmux(0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_11: CKEOUT0 (function 0) > CKE errata */ - scu_pinmux(0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_12: DQMOUT0 (function 0) > DQM0 errata */ - scu_pinmux(0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_10: DQMOUT1 (function 0) > DQM1 errata */ - scu_pinmux(0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_0: DQMOUT2 (function 2, from datasheet) > DQM2 errata */ - scu_pinmux(0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_13: DQMOUT3 (function 3, from datasheet) > DQM3 errata */ - - scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 ); //OE - scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 ); //BLS0 - scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 ); //CS0 - scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 ); //WE - -#endif -} - -void EMCFlashInit(void) -{ - // Hitex board SST39VF3201B Flash - // Read Cycle Time 70 nS minimum - // Chip Enable Access Time 70 ns maximum - // Address Access Time 70 ns max - // Toe 35 ns max - // CE/OE high to inactive output 16 ns - - /* Set up EMC Controller */ - LPC_EMC->STATICWAITRD0 = DELAYCYCLES(70)+1; - - LPC_EMC->STATICWAITPAG0 = DELAYCYCLES(70)+1; - - - LPC_EMC->CONTROL = 0x01; - LPC_EMC->STATICCONFIG0 = (1UL<<7) | (1UL); - LPC_EMC->STATICWAITOEN0 = DELAYCYCLES(35)+1; - - /*Enable Buffer for External Flash*/ - LPC_EMC->STATICCONFIG0 |= 1<<19; -} - -/* SDRAM refresh time to 16 clock num */ -#define EMC_SDRAM_REFRESH(freq,time) \ - (((uint64_t)((uint64_t)time * freq)/16000000000ull)+1) - -void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits) -{ - // adjust the CCU delaye for EMI (default to zero) - //LPC_SCU->EMCCLKDELAY = (CLK0_DELAY | (CLKE0_DELAY << 16)); - // Move all clock delays together - LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) - | (CLK0_DELAY << 4) - | (CLK0_DELAY << 8) - | (CLK0_DELAY << 12)); - - /* Initialize EMC to interface with SDRAM */ - LPC_EMC->CONTROL = 0x00000001; /* Enable the external memory controller */ - LPC_EMC->CONFIG = 0; - - LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)); - LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)); - - LPC_EMC->DYNAMICRASCAS0 = (3 << 0) | (3 << 8); // aem - LPC_EMC->DYNAMICRASCAS2 = (3 << 0) | (3 << 8); // aem - - LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; - - LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet - LPC_EMC->DYNAMICRAS = 3; - LPC_EMC->DYNAMICSREX = 5; - LPC_EMC->DYNAMICAPR = 0; - LPC_EMC->DYNAMICDAL = 4; - LPC_EMC->DYNAMICWR = 1; - LPC_EMC->DYNAMICRC = 5; - LPC_EMC->DYNAMICRFC = 5; - LPC_EMC->DYNAMICXSR = 5; - LPC_EMC->DYNAMICRRD = 1; - LPC_EMC->DYNAMICMRD = 1; - - LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP); - emc_WaitUS(100); - - LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL); - - LPC_EMC->DYNAMICREFRESH = 2; - emc_WaitUS(100); - - LPC_EMC->DYNAMICREFRESH = 50; - - LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE); - - if(u32DataBus == 0) - { - /* burst size 8 */ - *((volatile uint32_t *)(u32BaseAddr | ((3 | (3 << 4)) << (u32ColAddrBits + 1)))); - } - else - { - /* burst size 4 */ - *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2)))); - } - - LPC_EMC->DYNAMICCONTROL = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE; - LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE; - LPC_EMC->DYNAMICCONFIG1 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE; - LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE; - LPC_EMC->DYNAMICCONFIG3 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE; -} - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_evrt.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_evrt.c deleted file mode 100644 index 56ba72b3a..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_evrt.c +++ /dev/null @@ -1,258 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_evrt.c 2011-06-02 -*//** -* @file lpc18xx_evrt.c -* @brief Contains all functions support for Event Router firmware -* library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup EVRT - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_evrt.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup EVRT_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initializes the EVRT peripheral. - * @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT - * @return None - *********************************************************************/ -void EVRT_Init (LPC_EVENTROUTER_Type *EVRTx) -{ - uint8_t i=0; - - CHECK_PARAM(PARAM_EVRTx(EVRTx)); - - // Clear all register to be default - EVRTx->HILO = 0x0000; - EVRTx->EDGE = 0x0000; - EVRTx->CLR_EN = 0xFFFF; - do - { - i++; - EVRTx->CLR_STAT = 0xFFFFF; - }while((EVRTx->STATUS != 0)&&(i<10)); -} - -/*********************************************************************//** - * @brief De-initializes the EVRT peripheral registers to their -* default reset values. - * @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT - * @return None - **********************************************************************/ -void EVRT_DeInit(LPC_EVENTROUTER_Type *EVRTx) -{ - CHECK_PARAM(PARAM_EVRTx(EVRTx)); - - EVRTx->CLR_EN = 0xFFFF; - EVRTx->CLR_STAT = 0xFFFF; -} - -/*********************************************************************//** - * @brief Setting up the type of interrupt sources to EVRT - * @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT - * @param[in] EVRT_Src EVRT source, should be: - * - EVRT_SRC_WAKEUP0 :WAKEUP0 event - * - EVRT_SRC_WAKEUP1 :WAKEUP1 event - * - EVRT_SRC_WAKEUP2 :WAKEUP2 event - * - EVRT_SRC_WAKEUP3 :WAKEUP3 event - * - EVRT_SRC_ATIMER :Alarm timer eveny - * - EVRT_SRC_RTC :RTC event - * - EVRT_SRC_BOD :BOD event - * - EVRT_SRC_WWDT :WWDT event - * - EVRT_SRC_ETHERNET :ETHERNET event - * - EVRT_SRC_USB0 :USB0 event - * - EVRT_SRC_USB1 :USB1 event - * - EVRT_SRC_CCAN :CCAN event - * - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event - * - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event - * - EVRT_SRC_QEI :QEI event - * - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event - * - EVRT_SRC_RESET :RESET event - * type Active type, should be: - * - EVRT_SRC_ACTIVE_LOW_LEVEL :Active low level - * - EVRT_SRC_ACTIVE_HIGH_LEVEL :Active high level - * - EVRT_SRC_ACTIVE_FALLING_EDGE :Active falling edge - * - EVRT_SRC_ACTIVE_RISING_EDGE :Active rising edge - * @param[in] type EVRT source active type, should be: - * - EVRT_SRC_ACTIVE_LOW_LEVEL :Active low level - * - EVRT_SRC_ACTIVE_HIGH_LEVEL :Active high level - * - EVRT_SRC_ACTIVE_FALLING_EDGE :Active falling edge - * - EVRT_SRC_ACTIVE_RISING_EDGE :Active rising edge - * @return None - **********************************************************************/ -void EVRT_ConfigIntSrcActiveType(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type) -{ - CHECK_PARAM(PARAM_EVRTx(EVRTx)); - CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src)); - CHECK_PARAM(PARAM_EVRT_SOURCE_ACTIVE_TYPE(type)); - - switch (type) - { - case EVRT_SRC_ACTIVE_LOW_LEVEL: - EVRTx->HILO &= ~(1<<(uint8_t)EVRT_Src); - EVRTx->EDGE &= ~(1<<(uint8_t)EVRT_Src); - break; - case EVRT_SRC_ACTIVE_HIGH_LEVEL: - EVRTx->HILO |= (1<<(uint8_t)EVRT_Src); - EVRTx->EDGE &= ~(1<<(uint8_t)EVRT_Src); - break; - case EVRT_SRC_ACTIVE_FALLING_EDGE: - EVRTx->HILO &= ~(1<<(uint8_t)EVRT_Src); - EVRTx->EDGE |= (1<<(uint8_t)EVRT_Src); - break; - case EVRT_SRC_ACTIVE_RISING_EDGE: - EVRTx->HILO |= (1<<(uint8_t)EVRT_Src); - EVRTx->EDGE |= (1<<(uint8_t)EVRT_Src); - break; - default: - break; - } -} - -/*********************************************************************//** - * @brief Enable or disable interrupt sources to EVRT - * @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT - * @param[in] EVRT_Src EVRT source, should be: - * - EVRT_SRC_WAKEUP0 :WAKEUP0 event - * - EVRT_SRC_WAKEUP1 :WAKEUP1 event - * - EVRT_SRC_WAKEUP2 :WAKEUP2 event - * - EVRT_SRC_WAKEUP3 :WAKEUP3 event - * - EVRT_SRC_ATIMER :Alarm timer eveny - * - EVRT_SRC_RTC :RTC event - * - EVRT_SRC_BOD :BOD event - * - EVRT_SRC_WWDT :WWDT event - * - EVRT_SRC_ETHERNET :ETHERNET event - * - EVRT_SRC_USB0 :USB0 event - * - EVRT_SRC_USB1 :USB1 event - * - EVRT_SRC_CCAN :CCAN event - * - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event - * - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event - * - EVRT_SRC_QEI :QEI event - * - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event - * - EVRT_SRC_RESET :RESET event - * @param[in] state ENABLE or DISABLE - * @return None - **********************************************************************/ -void EVRT_SetUpIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, FunctionalState state) -{ - CHECK_PARAM(PARAM_EVRTx(EVRTx)); - CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src)); - - if(state == ENABLE) - EVRTx->SET_EN = (1<<(uint8_t)EVRT_Src); - else - EVRTx->CLR_EN = (1<<(uint8_t)EVRT_Src); -} - -/*********************************************************************//** - * @brief Check if a source is sending interrupt to EVRT - * @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT - * @param[in] EVRT_Src EVRT source, should be: - * - EVRT_SRC_WAKEUP0 :WAKEUP0 event - * - EVRT_SRC_WAKEUP1 :WAKEUP1 event - * - EVRT_SRC_WAKEUP2 :WAKEUP2 event - * - EVRT_SRC_WAKEUP3 :WAKEUP3 event - * - EVRT_SRC_ATIMER :Alarm timer eveny - * - EVRT_SRC_RTC :RTC event - * - EVRT_SRC_BOD :BOD event - * - EVRT_SRC_WWDT :WWDT event - * - EVRT_SRC_ETHERNET :ETHERNET event - * - EVRT_SRC_USB0 :USB0 event - * - EVRT_SRC_USB1 :USB1 event - * - EVRT_SRC_CCAN :CCAN event - * - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event - * - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event - * - EVRT_SRC_QEI :QEI event - * - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event - * - EVRT_SRC_RESET :RESET event - * @return TRUE or FALSE - **********************************************************************/ -Bool EVRT_IsSourceInterrupting(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src) -{ - CHECK_PARAM(PARAM_EVRTx(EVRTx)); - CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src)); - - if(EVRTx->STATUS & (1<<(uint8_t)EVRT_Src)) - return TRUE; - else return FALSE; -} - -/*********************************************************************//** - * @brief Clear pending interrupt EVRT source - * @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT - * @param[in] EVRT_Src EVRT source, should be: - * - EVRT_SRC_WAKEUP0 :WAKEUP0 event - * - EVRT_SRC_WAKEUP1 :WAKEUP1 event - * - EVRT_SRC_WAKEUP2 :WAKEUP2 event - * - EVRT_SRC_WAKEUP3 :WAKEUP3 event - * - EVRT_SRC_ATIMER :Alarm timer eveny - * - EVRT_SRC_RTC :RTC event - * - EVRT_SRC_BOD :BOD event - * - EVRT_SRC_WWDT :WWDT event - * - EVRT_SRC_ETHERNET :ETHERNET event - * - EVRT_SRC_USB0 :USB0 event - * - EVRT_SRC_USB1 :USB1 event - * - EVRT_SRC_CCAN :CCAN event - * - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event - * - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event - * - EVRT_SRC_QEI :QEI event - * - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event - * - EVRT_SRC_RESET :RESET event - * @return none - **********************************************************************/ -void EVRT_ClrPendIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src) -{ - CHECK_PARAM(PARAM_EVRTx(EVRTx)); - CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src)); - - EVRTx->CLR_STAT = (1<<(uint8_t)EVRT_Src); -} - -/** - * @} - */ - - - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpdma.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpdma.c deleted file mode 100644 index 82fbf7147..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpdma.c +++ /dev/null @@ -1,567 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_gpdma.c 2011-06-02 -*//** -* @file lpc18xx_gpdma.c -* @brief Contains all functions support for GPDMA firmware library -* on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup GPDMA - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_gpdma.h" -//#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _GPDMA - -/** GPDMA Mux definitions */ -#define DMAMUX_ADDRESS 0x4004311C - -/* Private Functions ----------------------------------------------------------- */ -/** @ - * @{ - */ -uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number); -/** - * @} - */ - -/* Private Variables ---------------------------------------------------------- */ -/** @defgroup GPDMA_Private_Variables GPDMA Private Variables - * @{ - */ - -/** - * @brief Lookup Table of Connection Type matched with - * Peripheral Data (FIFO) register base address - */ -#ifdef __ICCARM__ -volatile const void *GPDMA_LUTPerAddr[] = { - (&LPC_SPIFI->DAT), // SPIFI - (&LPC_TIMER0->MR), // MAT0.0 - (&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx - ((uint32_t*)&LPC_TIMER0->MR + 1), // MAT0.1 - (&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx - (&LPC_TIMER1->MR), // MAT1.0 - (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx - ((uint32_t*)&LPC_TIMER1->MR + 1), // MAT1.1 - (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx - (&LPC_TIMER2->MR), // MAT2.0 - (&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx - ((uint32_t*)&LPC_TIMER2->MR + 1), // MAT2.1 - (&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx - (&LPC_TIMER3->MR), // MAT3.0 - (&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx - 0, // to be defined: SCT DMA request 0 - ((uint32_t*)&LPC_TIMER3->MR + 1), // MAT3.1 - (&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx - 0, // to be defined: SCT DMA request 1 - (&LPC_SSP0->DR), // SSP0 Rx - (&LPC_I2S0->TXFIFO), // I2S channel 0 - (&LPC_SSP0->DR), // SSP0 Tx - (&LPC_I2S0->RXFIFO), // I2S channel 1 - (&LPC_SSP1->DR), // SSP1 Rx - (&LPC_SSP1->DR), // SSP1 Tx - (&LPC_ADC0->GDR), // ADC 0 - (&LPC_ADC1->GDR), // ADC 1 - (&LPC_DAC->CR) // DAC -}; -#else -const uint32_t GPDMA_LUTPerAddr[] = { -// ((uint32_t)&LPC_SPIFI->DAT), // SPIFI - ((uint32_t)0), // SPIFI - ((uint32_t)&LPC_TIMER0->MR[0]), // MAT0.0 - ((uint32_t)&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx - ((uint32_t)&LPC_TIMER0->MR[1]), // MAT0.1 - ((uint32_t)&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx - ((uint32_t)&LPC_TIMER1->MR[0]), // MAT1.0 - ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx - ((uint32_t)&LPC_TIMER1->MR[1]), // MAT1.1 - ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx - ((uint32_t)&LPC_TIMER2->MR[0]), // MAT2.0 - ((uint32_t)&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx - ((uint32_t)&LPC_TIMER2->MR[1]), // MAT2.1 - ((uint32_t)&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx - ((uint32_t)&LPC_TIMER3->MR[0]), // MAT3.0 - ((uint32_t)&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx - 0, // to be defined: SCT DMA request 0 - ((uint32_t)&LPC_TIMER3->MR[1]), // MAT3.1 - ((uint32_t)&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx - 0, // to be defined: SCT DMA request 1 - ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx - ((uint32_t)&LPC_I2S0->TXFIFO), // I2S channel 0 - ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx - ((uint32_t)&LPC_I2S0->RXFIFO), // I2S channel 1 - ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx - ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx - ((uint32_t)&LPC_ADC0->GDR), // ADC 0 - ((uint32_t)&LPC_ADC1->GDR), // ADC 1 - ((uint32_t)&LPC_DAC->CR) // DAC -}; -#endif -/** - * @brief Lookup Table of GPDMA Channel Number matched with - * GPDMA channel pointer - */ -const LPC_GPDMACH_TypeDef *pGPDMACh[8] = { - LPC_GPDMACH0, // GPDMA Channel 0 - LPC_GPDMACH1, // GPDMA Channel 1 - LPC_GPDMACH2, // GPDMA Channel 2 - LPC_GPDMACH3, // GPDMA Channel 3 - LPC_GPDMACH4, // GPDMA Channel 4 - LPC_GPDMACH5, // GPDMA Channel 5 - LPC_GPDMACH6, // GPDMA Channel 6 - LPC_GPDMACH7, // GPDMA Channel 7 -}; -/** - * @brief Optimized Peripheral Source and Destination burst size - */ -const uint8_t GPDMA_LUTPerBurst[] = { - GPDMA_BSIZE_4, // SPIFI - GPDMA_BSIZE_1, // MAT0.0 - GPDMA_BSIZE_1, // UART0 Tx - GPDMA_BSIZE_1, // MAT0.1 - GPDMA_BSIZE_1, // UART0 Rx - GPDMA_BSIZE_1, // MAT1.0 - GPDMA_BSIZE_1, // UART1 Tx - GPDMA_BSIZE_1, // MAT1.1 - GPDMA_BSIZE_1, // UART1 Rx - GPDMA_BSIZE_1, // MAT2.0 - GPDMA_BSIZE_1, // UART2 Tx - GPDMA_BSIZE_1, // MAT2.1 - GPDMA_BSIZE_1, // UART2 Rx - GPDMA_BSIZE_1, // MAT3.0 - GPDMA_BSIZE_1, // UART3 Tx - 0, // to be defined: SCT DMA request 0 - GPDMA_BSIZE_1, // MAT3.1 - GPDMA_BSIZE_1, // UART3 Rx - 0, // to be defined: SCT DMA request 1 - GPDMA_BSIZE_4, // SSP0 Rx - GPDMA_BSIZE_32, // I2S channel 0 - GPDMA_BSIZE_4, // SSP0 Tx - GPDMA_BSIZE_32, // I2S channel 1 - GPDMA_BSIZE_4, // SSP1 Rx - GPDMA_BSIZE_4, // SSP1 Tx - GPDMA_BSIZE_4, // ADC 0 - GPDMA_BSIZE_4, // ADC 1 - GPDMA_BSIZE_1, // DAC -}; -/** - * @brief Optimized Peripheral Source and Destination transfer width - */ -const uint8_t GPDMA_LUTPerWid[] = { - GPDMA_WIDTH_WORD, // SPIFI - GPDMA_WIDTH_WORD, // MAT0.0 - GPDMA_WIDTH_BYTE, // UART0 Tx - GPDMA_WIDTH_WORD, // MAT0.1 - GPDMA_WIDTH_BYTE, // UART0 Rx - GPDMA_WIDTH_WORD, // MAT1.0 - GPDMA_WIDTH_BYTE, // UART1 Tx - GPDMA_WIDTH_WORD, // MAT1.1 - GPDMA_WIDTH_BYTE, // UART1 Rx - GPDMA_WIDTH_WORD, // MAT2.0 - GPDMA_WIDTH_BYTE, // UART2 Tx - GPDMA_WIDTH_WORD, // MAT2.1 - GPDMA_WIDTH_BYTE, // UART2 Rx - GPDMA_WIDTH_WORD, // MAT3.0 - GPDMA_WIDTH_BYTE, // UART3 Tx - 0, // to be defined: SCT DMA request 0 - GPDMA_WIDTH_WORD, // MAT3.1 - GPDMA_WIDTH_BYTE, // UART3 Rx - 0, // to be defined: SCT DMA request 1 - GPDMA_WIDTH_BYTE, // SSP0 Rx - GPDMA_WIDTH_WORD, // I2S channel 0 - GPDMA_WIDTH_BYTE, // SSP0 Tx - GPDMA_WIDTH_WORD, // I2S channel 1 - GPDMA_WIDTH_BYTE, // SSP1 Rx - GPDMA_WIDTH_BYTE, // SSP1 Tx - GPDMA_WIDTH_WORD, // ADC 0 - GPDMA_WIDTH_WORD, // ADC 1 - GPDMA_WIDTH_WORD, // DAC -}; - -/** - * @} - */ - -/* Private Functions ----------------------------------------------------------- */ -/** @ - * @{ - */ - -/********************************************************************//** - * @brief Control which set of peripherals is connected to the - * DMA controller - * @param[in] gpdma_peripheral_connection_number GPDMA peripheral - * connection number, should be: - * - GPDMA_CONN_SPIFI :SPIFI - * - GPDMA_CONN_MAT0_0 :Timer 0, match channel 0 - * - GPDMA_CONN_MAT0_1 :Timer 0, match channel 1 - * - GPDMA_CONN_MAT1_0 :Timer 1, match channel 0 - * - GPDMA_CONN_MAT1_1 :Timer 1, match channel 1 - * - GPDMA_CONN_MAT2_0 :Timer 2, match channel 0 - * - GPDMA_CONN_MAT2_1 :Timer 2, match channel 1 - * - GPDMA_CONN_MAT3_0 :Timer 3, match channel 0 - * - GPDMA_CONN_MAT3_1 :Timer 3, match channel 1 - * - GPDMA_CONN_UART0_Tx :USART 0 transmit - * - GPDMA_CONN_UART0_Rx :USART 0 receive - * - GPDMA_CONN_UART1_Tx :USART 1 transmit - * - GPDMA_CONN_UART1_Rx :USART 1 receive - * - GPDMA_CONN_UART2_Tx :USART 2 transmit - * - GPDMA_CONN_UART2_Rx :USART 2 receive - * - GPDMA_CONN_UART3_Tx :USART 3 transmit - * - GPDMA_CONN_UART3_Rx :USART 3 receive - * - GPDMA_CONN_SCT_0 :SCT output 0 - * - GPDMA_CONN_SCT_1 :SCT output 1 - * - GPDMA_CONN_I2S_Channel_0 :I2S channel 0 - * - GPDMA_CONN_I2S_Channel_1 :I2S channel 1 - * - GPDMA_CONN_SSP0_Tx :SSP0 transmit - * - GPDMA_CONN_SSP0_Rx :SSP0 receive - * - GPDMA_CONN_SSP1_Tx :SSP1 transmit - * - GPDMA_CONN_SSP1_Rx :SSP1 receive - * - GPDMA_CONN_ADC_0 :ADC0 - * - GPDMA_CONN_ADC_1 :ADC1 - * - GPDMA_CONN_DAC :DAC - * @return channel number, could be in range: 0..16 - *********************************************************************/ -uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number) -{ - uint32_t *dmamux_reg = (uint32_t*)DMAMUX_ADDRESS; - uint8_t function, channel; - - switch(gpdma_peripheral_connection_number) - { - case GPDMA_CONN_SPIFI: function = 0; channel = 0; break; - case GPDMA_CONN_MAT0_0: function = 0; channel = 1; break; - case GPDMA_CONN_UART0_Tx: function = 1; channel = 1; break; - case GPDMA_CONN_MAT0_1: function = 0; channel = 2; break; - case GPDMA_CONN_UART0_Rx: function = 1; channel = 2; break; - case GPDMA_CONN_MAT1_0: function = 0; channel = 3; break; - case GPDMA_CONN_UART1_Tx: function = 1; channel = 3; break; - case GPDMA_CONN_MAT1_1: function = 0; channel = 4; break; - case GPDMA_CONN_UART1_Rx: function = 1; channel = 4; break; - case GPDMA_CONN_MAT2_0: function = 0; channel = 5; break; - case GPDMA_CONN_UART2_Tx: function = 1; channel = 5; break; - case GPDMA_CONN_MAT2_1: function = 0; channel = 6; break; - case GPDMA_CONN_UART2_Rx: function = 1; channel = 6; break; - case GPDMA_CONN_MAT3_0: function = 0; channel = 7; break; - case GPDMA_CONN_UART3_Tx: function = 1; channel = 7; break; - case GPDMA_CONN_SCT_0: function = 2; channel = 7; break; - case GPDMA_CONN_MAT3_1: function = 0; channel = 8; break; - case GPDMA_CONN_UART3_Rx: function = 1; channel = 8; break; - case GPDMA_CONN_SCT_1: function = 2; channel = 8; break; - case GPDMA_CONN_SSP0_Rx: function = 0; channel = 9; break; - case GPDMA_CONN_I2S_Channel_0:function = 1; channel = 9; break; - case GPDMA_CONN_SSP0_Tx: function = 0; channel = 10; break; - case GPDMA_CONN_I2S_Channel_1:function = 1; channel = 10; break; - case GPDMA_CONN_SSP1_Rx: function = 0; channel = 11; break; - case GPDMA_CONN_SSP1_Tx: function = 0; channel = 12; break; - case GPDMA_CONN_ADC_0: function = 0; channel = 13; break; - case GPDMA_CONN_ADC_1: function = 0; channel = 14; break; - case GPDMA_CONN_DAC: function = 0; channel = 15; break; - default: function = 3; channel = 15; break; - } - //Set select function to dmamux register - *dmamux_reg &= ~(0x03<<(2*channel)); - *dmamux_reg |= (function<<(2*channel)); - - return channel; -} -/** - * @} - */ - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup GPDMA_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initialize GPDMA controller - * @param[in] None - * @return None - *********************************************************************/ -void GPDMA_Init(void) -{ - /* to be defined Enable GPDMA clock */ - // enabled default on reset - - // Reset all channel configuration register - LPC_GPDMACH0->CConfig = 0; - LPC_GPDMACH1->CConfig = 0; - LPC_GPDMACH2->CConfig = 0; - LPC_GPDMACH3->CConfig = 0; - LPC_GPDMACH4->CConfig = 0; - LPC_GPDMACH5->CConfig = 0; - LPC_GPDMACH6->CConfig = 0; - LPC_GPDMACH7->CConfig = 0; - - /* Clear all DMA interrupt and error flag */ - LPC_GPDMA->INTTCCLEAR = 0xFF; - LPC_GPDMA->INTERRCLR = 0xFF; -} - -/********************************************************************//** - * @brief Setup GPDMA channel peripheral according to the specified - * parameters in the GPDMAChannelConfig. - * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type structure - * that contains the configuration information for the specified - * GPDMA channel peripheral. - * @return Setup status, could be: - * - ERROR :if selected channel is enabled before - * - SUCCESS :if channel is configured successfully - *********************************************************************/ -Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig) -{ - LPC_GPDMACH_TypeDef *pDMAch; - uint8_t SrcPeripheral=0, DestPeripheral=0; - - if (LPC_GPDMA->ENBLDCHNS & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) { - // This channel is enabled, return ERROR, need to release this channel first - return ERROR; - } - - // Get Channel pointer - pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum]; - - // Reset the Interrupt status - LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum); - LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum); - - // Clear DMA configure - pDMAch->CControl = 0x00; - pDMAch->CConfig = 0x00; - - /* Assign Linker List Item value */ - pDMAch->CLLI = GPDMAChannelConfig->DMALLI; - - /* Set value to Channel Control Registers */ - switch (GPDMAChannelConfig->TransferType) - { - // Memory to memory - case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: - // Assign physical source and destination address - pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr; - pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr; - pDMAch->CControl - = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \ - | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \ - | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \ - | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \ - | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \ - | GPDMA_DMACCxControl_SI \ - | GPDMA_DMACCxControl_DI \ - | GPDMA_DMACCxControl_I; - break; - // Memory to peripheral - case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: - // Assign physical source - pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr; - // Assign peripheral destination address - pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; - pDMAch->CControl - = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ - | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_DestTransUseAHBMaster1 \ - | GPDMA_DMACCxControl_SI \ - | GPDMA_DMACCxControl_I; - DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn); - break; - // Peripheral to memory - case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: - // Assign peripheral source address - pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; - // Assign memory destination address - pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr; - pDMAch->CControl - = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ - | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \ - | GPDMA_DMACCxControl_DI \ - | GPDMA_DMACCxControl_I; - SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn); - break; - // Peripheral to peripheral - case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: - // Assign peripheral source address - pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; - // Assign peripheral destination address - pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; - pDMAch->CControl - = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ - | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ - | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ - | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \ - | GPDMA_DMACCxControl_DestTransUseAHBMaster1 \ - | GPDMA_DMACCxControl_I; - SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn); - DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn); - break; - - case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: - case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: - case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: - case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: - //to be defined - // Do not support any more transfer type, return ERROR - default: - return ERROR; - } - - /* Enable DMA channels, little endian */ - LPC_GPDMA->CONFIG = GPDMA_DMACConfig_E; - while (!(LPC_GPDMA->CONFIG & GPDMA_DMACConfig_E)); - - // Configure DMA Channel, enable Error Counter and Terminate counter - pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \ - | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \ - | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) \ - | GPDMA_DMACCxConfig_DestPeripheral(DestPeripheral); - - return SUCCESS; -} - - -/*********************************************************************//** - * @brief Enable/Disable DMA channel - * @param[in] channelNum GPDMA channel, should be in range from 0 to 15 - * @param[in] NewState New State of this command, should be: - * - ENABLE. - * - DISABLE. - * @return None - **********************************************************************/ -void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState) -{ - LPC_GPDMACH_TypeDef *pDMAch; - - // Get Channel pointer - pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum]; - - if (NewState == ENABLE) { - pDMAch->CConfig |= GPDMA_DMACCxConfig_E; - } else { - pDMAch->CConfig &= ~GPDMA_DMACCxConfig_E; - } -} - - -/*********************************************************************//** - * @brief Check if corresponding channel does have an active interrupt - * request or not - * @param[in] type type of status, should be: - * - GPDMA_STAT_INT :GPDMA Interrupt Status - * - GPDMA_STAT_INTTC :GPDMA Interrupt Terminal Count Request Status - * - GPDMA_STAT_INTERR :GPDMA Interrupt Error Status - * - GPDMA_STAT_RAWINTTC :GPDMA Raw Interrupt Terminal Count Status - * - GPDMA_STAT_RAWINTERR :GPDMA Raw Error Interrupt Status - * - GPDMA_STAT_ENABLED_CH :GPDMA Enabled Channel Status - * @param[in] channel GPDMA channel, should be in range from 0 to 7 - * @return IntStatus status of DMA channel interrupt after masking - * Should be: - * - SET :the corresponding channel has no active interrupt request - * - RESET :the corresponding channel does have an active interrupt request - **********************************************************************/ -IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel) -{ - CHECK_PARAM(PARAM_GPDMA_STAT(type)); - CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); - - switch (type) - { - case GPDMA_STAT_INT: //check status of DMA channel interrupts - if (LPC_GPDMA->INTSTAT & (GPDMA_DMACIntStat_Ch(channel))) - return SET; - return RESET; - case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA - if (LPC_GPDMA->INTTCSTAT & GPDMA_DMACIntTCStat_Ch(channel)) - return SET; - return RESET; - case GPDMA_STAT_INTERR: //check interrupt status for DMA channels - if (LPC_GPDMA->INTERRSTAT & GPDMA_DMACIntTCClear_Ch(channel)) - return SET; - return RESET; - case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels - if (LPC_GPDMA->RAWINTERRSTAT & GPDMA_DMACRawIntTCStat_Ch(channel)) - return SET; - return RESET; - case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels - if (LPC_GPDMA->RAWINTTCSTAT & GPDMA_DMACRawIntErrStat_Ch(channel)) - return SET; - return RESET; - default: //check enable status for DMA channels - if (LPC_GPDMA->ENBLDCHNS & GPDMA_DMACEnbldChns_Ch(channel)) - return SET; - return RESET; - } -} - -/*********************************************************************//** - * @brief Clear one or more interrupt requests on DMA channels - * @param[in] type type of interrupt request, should be: - * - GPDMA_STATCLR_INTTC :GPDMA Interrupt Terminal Count Request Clear - * - GPDMA_STATCLR_INTERR :GPDMA Interrupt Error Clear - * @param[in] channel GPDMA channel, should be in range from 0 to 15 - * @return None - **********************************************************************/ -void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel) -{ - CHECK_PARAM(PARAM_GPDMA_STATCLR(type)); - CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); - - if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel - LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(channel); - else // clear the error interrupt request - LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(channel); -} - -/** - * @} - */ - -#endif /* _GPDMA */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpio.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpio.c deleted file mode 100644 index 1477c07fd..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpio.c +++ /dev/null @@ -1,816 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_gpio.c 2011-06-02 -*//** -* @file lpc18xx_gpio.c -* @brief Contains all functions support for GPIO firmware library -* on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup GPIO - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_gpio.h" -#include "lpc_types.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _GPIO - -/* Private Functions ---------------------------------------------------------- */ - -//static LPC_GPIOn_Type *GPIO_GetPointer(uint8_t portNum); -//static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum); -//static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum); - -#if 0 -/*********************************************************************//** - * @brief Get pointer to GPIO peripheral due to GPIO port - * @param[in] portNum Port Number value, should be in range from 0 to 4. - * @return Pointer to GPIO peripheral - **********************************************************************/ -static LPC_GPIOn_Type *GPIO_GetPointer(uint8_t portNum) -{ - LPC_GPIOn_Type *pGPIO = NULL; - - switch (portNum) - { - case 0: - pGPIO = LPC_GPIO0; - break; - - case 1: - pGPIO = LPC_GPIO1; - break; - - case 2: - pGPIO = LPC_GPIO2; - break; - - case 3: - pGPIO = LPC_GPIO3; - break; - - case 4: - pGPIO = LPC_GPIO4; - break; - - default: - break; - } - - return pGPIO; -} - -/*********************************************************************//** - * @brief Get pointer to FIO peripheral in halfword accessible style - * due to FIO port - * @param[in] portNum Port Number value, should be in range from 0 to 4. - * @return Pointer to FIO peripheral - **********************************************************************/ -static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum) -{ - GPIO_HalfWord_TypeDef *pFIO = NULL; - - switch (portNum) - { - case 0: - pFIO = GPIO0_HalfWord; - break; - - case 1: - pFIO = GPIO1_HalfWord; - break; - - case 2: - pFIO = GPIO2_HalfWord; - break; - - case 3: - pFIO = GPIO3_HalfWord; - break; - - case 4: - pFIO = GPIO4_HalfWord; - break; - default: - break; - } - - return pFIO; -} - -/*********************************************************************//** - * @brief Get pointer to FIO peripheral in byte accessible style - * due to FIO port - * @param[in] portNum Port Number value, should be in range from 0 to 4. - * @return Pointer to FIO peripheral - **********************************************************************/ -static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum) -{ - GPIO_Byte_TypeDef *pFIO = NULL; - - switch (portNum) - { - case 0: - pFIO = GPIO0_Byte; - break; - - case 1: - pFIO = GPIO1_Byte; - break; - - case 2: - pFIO = GPIO2_Byte; - break; - - case 3: - pFIO = GPIO3_Byte; - break; - - case 4: - pFIO = GPIO4_Byte; - break; - - default: - break; - } - - return pFIO; -} -#endif - -/* End of Private Functions --------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup GPIO_Public_Functions - * @{ - */ - - -/* GPIO ------------------------------------------------------------------------------ */ - -/*********************************************************************//** - * @brief Set Direction for GPIO port. - * @param[in] portNum Port Number value, should be in range from 0 to 4 - * @param[in] bitValue Value that contains all bits to set direction, - * in range from 0 to 0xFFFFFFFF. - * example: value 0x5 to set direction for bit 0 and bit 1. - * @param[in] dir Direction value, should be: - * - 0: Input. - * - 1: Output. - * @return None - * - * Note: - * All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir) -{ - if (dir) - { - LPC_GPIO_PORT->DIR[portNum] |= bitValue; - } else - { - LPC_GPIO_PORT->DIR[portNum] &= ~bitValue; - } -} - - -/*********************************************************************//** - * @brief Set Value for bits that have output direction on GPIO port. - * @param[in] portNum Port number value, should be in range from 0 to 4 - * @param[in] bitValue Value that contains all bits on GPIO to set, should - * be in range from 0 to 0xFFFFFFFF. - * example: value 0x5 to set bit 0 and bit 1. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void GPIO_SetValue(uint8_t portNum, uint32_t bitValue) -{ - LPC_GPIO_PORT->SET[portNum] = bitValue; -} - - -/*********************************************************************//** - * @brief Clear Value for bits that have output direction on GPIO port. - * @param[in] portNum Port number value, should be in range from 0 to 4 - * @param[in] bitValue Value that contains all bits on GPIO to clear, should - * be in range from 0 to 0xFFFFFFFF. - * example: value 0x5 to clear bit 0 and bit 1. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue) -{ - LPC_GPIO_PORT->CLR[portNum] = bitValue; -} - - -/*********************************************************************//** - * @brief Read Current state on port pin that have input direction of GPIO - * @param[in] portNum Port number to read value, in range from 0 to 4 - * @return Current value of GPIO port. - * - * Note: Return value contain state of each port pin (bit) on that GPIO regardless - * its direction is input or output. - **********************************************************************/ -uint32_t GPIO_ReadValue(uint8_t portNum) -{ - return LPC_GPIO_PORT->PIN[portNum]; -} - - -#ifdef GPIO_INT -/*********************************************************************//** - * @brief Enable GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13) - * @param[in] portNum Port number to read value, should be: 0 or 2 - * @param[in] bitValue Value that contains all bits on GPIO to enable, - * should be in range from 0 to 0xFFFFFFFF. - * @param[in] edgeState state of edge, should be: - * - 0: Rising edge - * - 1: Falling edge - * @return None - **********************************************************************/ -void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState) -{ - if((portNum == 0)&&(edgeState == 0)) - LPC_GPIOINT->IO0IntEnR = bitValue; - else if ((portNum == 2)&&(edgeState == 0)) - LPC_GPIOINT->IO2IntEnR = bitValue; - else if ((portNum == 0)&&(edgeState == 1)) - LPC_GPIOINT->IO0IntEnF = bitValue; - else if ((portNum == 2)&&(edgeState == 1)) - LPC_GPIOINT->IO2IntEnF = bitValue; - else - //Error - while(1); -} - - -/*********************************************************************//** - * @brief Get GPIO Interrupt Status (just used for P0.0-P0.30, P2.0-P2.13) - * @param[in] portNum Port number to read value, should be: 0 or 2 - * @param[in] pinNum Pin number, should be: 0..30(with port 0) and 0..13 - * (with port 2) - * @param[in] edgeState state of edge, should be: - * - 0 :Rising edge - * - 1 :Falling edge - * @return Function status, could be: - * - ENABLE :Interrupt has been generated due to a rising edge on P0.0 - * - DISABLE :A rising edge has not been detected on P0.0 - **********************************************************************/ -FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState) -{ - if((portNum == 0) && (edgeState == 0))//Rising Edge - return (((LPC_GPIOINT->IO0IntStatR)>>pinNum)& 0x1); - else if ((portNum == 2) && (edgeState == 0)) - return (((LPC_GPIOINT->IO2IntStatR)>>pinNum)& 0x1); - else if ((portNum == 0) && (edgeState == 1))//Falling Edge - return (((LPC_GPIOINT->IO0IntStatF)>>pinNum)& 0x1); - else if ((portNum == 2) && (edgeState == 1)) - return (((LPC_GPIOINT->IO2IntStatF)>>pinNum)& 0x1); - else - //Error - while(1); -} - - -/*********************************************************************//** - * @brief Clear GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13) - * @param[in] portNum Port number to read value, should be: 0 or 2 - * @param[in] bitValue Value that contains all bits on GPIO to enable, - * should be in range from 0 to 0xFFFFFFFF. - * @return None - **********************************************************************/ -void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue) -{ - if(portNum == 0) - LPC_GPIOINT->IO0IntClr = bitValue; - else if (portNum == 2) - LPC_GPIOINT->IO2IntClr = bitValue; - else - //Invalid portNum - while(1); -} -#endif - - -/* FIO word accessible ----------------------------------------------------------------- */ -/* Stub function for FIO (word-accessible) style */ - -/** - * @brief The same with GPIO_SetDir() - */ -void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir) -{ - GPIO_SetDir(portNum, bitValue, dir); -} - -/** - * @brief The same with GPIO_SetValue() - */ -void FIO_SetValue(uint8_t portNum, uint32_t bitValue) -{ - GPIO_SetValue(portNum, bitValue); -} - -/** - * @brief The same with GPIO_ClearValue() - */ -void FIO_ClearValue(uint8_t portNum, uint32_t bitValue) -{ - GPIO_ClearValue(portNum, bitValue); -} - -/** - * @brief The same with GPIO_ReadValue() - */ -uint32_t FIO_ReadValue(uint8_t portNum) -{ - return (GPIO_ReadValue(portNum)); -} - - -#ifdef GPIO_INT -/** - * @brief The same with GPIO_IntCmd() - */ -void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState) -{ - GPIO_IntCmd(portNum, bitValue, edgeState); -} - -/** - * @brief The same with GPIO_GetIntStatus() - */ -FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState) -{ - return (GPIO_GetIntStatus(portNum, pinNum, edgeState)); -} - -/** - * @brief The same with GPIO_ClearInt() - */ -void FIO_ClearInt(uint8_t portNum, uint32_t bitValue) -{ - GPIO_ClearInt(portNum, bitValue); -} -#endif - - -/*********************************************************************//** - * @brief Set mask value for bits in FIO port - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] bitValue Value that contains all bits in to set, should be - * in range from 0 to 0xFFFFFFFF. - * @param[in] maskValue Mask value contains state value for each bit: - * - 0 :not mask. - * - 1 :mask. - * @return None - * - * Note: - * - All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - * - After executing this function, in mask register, value '0' on each bit - * enables an access to the corresponding physical pin via a read or write access, - * while value '1' on bit (masked) that corresponding pin will not be changed - * with write access and if read, will not be reflected in the updated pin. - **********************************************************************/ -void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue) -{ - if (maskValue) - { - LPC_GPIO_PORT->MASK[portNum] |= bitValue; - } else - { - LPC_GPIO_PORT->MASK[portNum] &= ~bitValue; - } -} - - -/* FIO halfword accessible ------------------------------------------------------------- */ -#if 0 -/*********************************************************************//** - * @brief Set direction for FIO port in halfword accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @param[in] bitValue Value that contains all bits in to set direction, - * in range from 0 to 0xFFFF. - * @param[in] dir Direction value, should be: - * - 0 :Input. - * - 1 :Output. - * @return None - * - * Note: All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Output direction - if (dir) - { - // Upper - if(halfwordNum) - { - pFIO->FIODIRU |= bitValue; - } - // lower - else - { - pFIO->FIODIRL |= bitValue; - } - } - // Input direction - else - { - // Upper - if(halfwordNum) - { - pFIO->FIODIRU &= ~bitValue; - } - // lower - else - { - pFIO->FIODIRL &= ~bitValue; - } - } - } -} - - -/*********************************************************************//** - * @brief Set mask value for bits in FIO port in halfword accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @param[in] bitValue Value that contains all bits in to set, - * in range from 0 to 0xFFFF. - * @param[in] maskValue Mask value contains state value for each bit: - * - 0: not mask. - * - 1: mask. - * @return None - * - * Note: - * - All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - * - After executing this function, in mask register, value '0' on each bit - * enables an access to the corresponding physical pin via a read or write access, - * while value '1' on bit (masked) that corresponding pin will not be changed - * with write access and if read, will not be reflected in the updated pin. - **********************************************************************/ -void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Mask - if (maskValue) - { - // Upper - if(halfwordNum) - { - pFIO->FIOMASKU |= bitValue; - } - // lower - else - { - pFIO->FIOMASKL |= bitValue; - } - } - // Un-mask - else - { - // Upper - if(halfwordNum) - { - pFIO->FIOMASKU &= ~bitValue; - } - // lower - else - { - pFIO->FIOMASKL &= ~bitValue; - } - } - } -} - - -/*********************************************************************//** - * @brief Set bits for FIO port in halfword accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @param[in] bitValue Value that contains all bits in to set, should be - * in range from 0 to 0xFFFF. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Upper - if(halfwordNum) - { - pFIO->FIOSETU = bitValue; - } - // lower - else - { - pFIO->FIOSETL = bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Clear bits for FIO port in halfword accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @param[in] bitValue Value that contains all bits in to clear, should be - * in range from 0 to 0xFFFF. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Upper - if(halfwordNum) - { - pFIO->FIOCLRU = bitValue; - } - // lower - else - { - pFIO->FIOCLRL = bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Read Current state on port pin that have input direction of GPIO - * in halfword accessible style. - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper) - * @return Current value of FIO port pin of specified halfword. - * Note: Return value contain state of each port pin (bit) on that FIO regardless - * its direction is input or output. - **********************************************************************/ -uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum) -{ - GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum); - - if(pFIO != NULL) - { - // Upper - if(halfwordNum) - { - return (pFIO->FIOPINU); - } - // lower - else - { - return (pFIO->FIOPINL); - } - } - - return (0); -} - - -/* FIO Byte accessible ------------------------------------------------------------ */ - -/*********************************************************************//** - * @brief Set direction for FIO port in byte accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @param[in] bitValue Value that contains all bits in to set direction, - * in range from 0 to 0xFF. - * @param[in] dir Direction value, should be: - * - 0: Input. - * - 1: Output. - * @return None - * - * Note: All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if(pFIO != NULL) - { - // Output direction - if (dir) - { - if (byteNum <= 3) - { - pFIO->FIODIR[byteNum] |= bitValue; - } - } - // Input direction - else - { - if (byteNum <= 3) - { - pFIO->FIODIR[byteNum] &= ~bitValue; - } - } - } -} - -/*********************************************************************//** - * @brief Set mask value for bits in FIO port in byte accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @param[in] bitValue Value that contains all bits in to set mask, should - * be in range from 0 to 0xFF. - * @param[in] maskValue Mask value contains state value for each bit: - * - 0: not mask. - * - 1: mask. - * @return None - * - * Note: - * - All remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - * - After executing this function, in mask register, value '0' on each bit - * enables an access to the corresponding physical pin via a read or write access, - * while value '1' on bit (masked) that corresponding pin will not be changed - * with write access and if read, will not be reflected in the updated pin. - **********************************************************************/ -void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if(pFIO != NULL) - { - // Mask - if (maskValue) - { - if (byteNum <= 3) - { - pFIO->FIOMASK[byteNum] |= bitValue; - } - } - // Un-mask - else { - if (byteNum <= 3) - { - pFIO->FIOMASK[byteNum] &= ~bitValue; - } - } - } -} - - -/*********************************************************************//** - * @brief Set bits for FIO port in byte accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @param[in] bitValue Value that contains all bits in to set, should - * be in range from 0 to 0xFF. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if (pFIO != NULL) { - if (byteNum <= 3) - { - pFIO->FIOSET[byteNum] = bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Clear bits for FIO port in byte accessible style - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @param[in] bitValue Value that contains all bits in to clear, should - * be in range from 0 to 0xFF. - * @return None - * - * Note: - * - For all bits that has been set as input direction, this function will - * not effect. - * - For all remaining bits that are not activated in bitValue (value '0') - * will not be effected by this function. - **********************************************************************/ -void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if (pFIO != NULL) - { - if (byteNum <= 3) - { - pFIO->FIOCLR[byteNum] = bitValue; - } - } -} - - -/*********************************************************************//** - * @brief Read Current state on port pin that have input direction of GPIO - * in byte accessible style. - * @param[in] portNum Port number, in range from 0 to 4 - * @param[in] byteNum Byte part number, should be in range from 0 to 3 - * @return Current value of FIO port pin of specified byte part. - * Note: Return value contain state of each port pin (bit) on that FIO regardless - * its direction is input or output. - **********************************************************************/ -uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum) -{ - GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum); - - if (pFIO != NULL) - { - if (byteNum <= 3) - { - return (pFIO->FIOPIN[byteNum]); - } - } - return (0); -} -#endif - -/** - * @} - */ - -#endif /* _GPIO */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2c.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2c.c deleted file mode 100644 index d309b1eec..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2c.c +++ /dev/null @@ -1,1329 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_i2c.c 2011-06-02 -*//** -* @file lpc18xx_i2c.c -* @brief Contains all functions support for I2C firmware library -* on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup I2C - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_i2c.h" -#include "lpc18xx_cgu.h" -#include "lpc18xx_scu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _I2C - - -/* Private Types -------------------------------------------------------------- */ -/** @defgroup I2C_Private_Types I2C Private Types - * @{ - */ -#define SFSP2_3_CONFIGURE_I2C1_SDA (0x00000001 | MD_ZI | MD_EZI) -#define SFSP2_4_CONFIGURE_I2C1_SCL (0x00000001 | MD_ZI | MD_EZI) -#define SFSI2C0_CONFIGURE_STANDARD_FAST_MODE (1<<3 | 1<<11) -#define SFSI2C0_CONFIGURE_FASTPLUS_HIGHSPEED_MODE (2<<1 | 1<<3 | 1<<7 | 1<<10 | 1<<11) - -/** - * @brief I2C device configuration structure type - */ -typedef struct -{ - uint32_t txrx_setup; /* Transmission setup */ - int32_t dir; /* Current direction phase, 0 - write, 1 - read */ -} I2C_CFG_T; - -/** - * @} - */ - -/* Private Variables ---------------------------------------------------------- */ -/** - * @brief II2C driver data for I2C0, I2C1 - */ -static I2C_CFG_T i2cdat[3]; - -static uint32_t I2C_MasterComplete[3]; -static uint32_t I2C_SlaveComplete[3]; - -static uint32_t I2C_MonitorBufferIndex; - -/* Private Functions ---------------------------------------------------------- */ - -/* Get I2C number */ -static int32_t I2C_getNum(LPC_I2Cn_Type *I2Cx); - -/* Generate a start condition on I2C bus (in master mode only) */ -static uint32_t I2C_Start (LPC_I2Cn_Type *I2Cx); - -/* Generate a stop condition on I2C bus (in master mode only) */ -static void I2C_Stop (LPC_I2Cn_Type *I2Cx); - -/* I2C send byte subroutine */ -static uint32_t I2C_SendByte (LPC_I2Cn_Type *I2Cx, uint8_t databyte); - -/* I2C get byte subroutine */ -static uint32_t I2C_GetByte (LPC_I2Cn_Type *I2Cx, uint8_t *retdat, Bool ack); - -/*--------------------------------------------------------------------------------*/ -/********************************************************************//** - * @brief Convert from I2C peripheral to number - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return I2C number or error code, could be: - * - 0 :I2C0 - * - 1 :I2C1 - * - (-1) :Error - *********************************************************************/ -static int32_t I2C_getNum(LPC_I2Cn_Type *I2Cx){ - if (I2Cx == LPC_I2C0) { - return (0); - } else if (I2Cx == LPC_I2C1) { - return (1); - } - return (-1); -} - - -/********************************************************************//** - * @brief Generate a start condition on I2C bus (in master mode only) - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return value of I2C status register after generate a start condition - *********************************************************************/ -static uint32_t I2C_Start (LPC_I2Cn_Type *I2Cx) -{ - I2Cx->CONSET = I2C_I2CONSET_STA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - // Wait for complete - while (!(I2Cx->CONSET & I2C_I2CONSET_SI)); - I2Cx->CONCLR = I2C_I2CONCLR_STAC; - return (I2Cx->STAT & I2C_STAT_CODE_BITMASK); -} - - -/********************************************************************//** - * @brief Generate a stop condition on I2C bus (in master mode only) - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return None - *********************************************************************/ -static void I2C_Stop (LPC_I2Cn_Type *I2Cx) -{ - - /* Make sure start bit is not active */ - if (I2Cx->CONSET & I2C_I2CONSET_STA) - { - I2Cx->CONCLR = I2C_I2CONCLR_STAC; - } - I2Cx->CONSET = I2C_I2CONSET_STO; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; -} - - -/********************************************************************//** - * @brief Send a byte - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] databyte sent data - * @return value of I2C status register after sending - *********************************************************************/ -static uint32_t I2C_SendByte (LPC_I2Cn_Type *I2Cx, uint8_t databyte) -{ - /* Make sure start bit is not active */ - if (I2Cx->CONSET & I2C_I2CONSET_STA) - { - I2Cx->CONCLR = I2C_I2CONCLR_STAC; - } - I2Cx->DAT = databyte & I2C_I2DAT_BITMASK; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - while (!(I2Cx->CONSET & I2C_I2CONSET_SI)); - return (I2Cx->STAT & I2C_STAT_CODE_BITMASK); -} - - -/********************************************************************//** - * @brief Get a byte - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[out] retdat pointer to return data - * @param[in] ack assert acknowledge or not, should be: TRUE/FALSE - * @return value of I2C status register after sending - *********************************************************************/ -static uint32_t I2C_GetByte (LPC_I2Cn_Type *I2Cx, uint8_t *retdat, Bool ack) -{ - if (ack == TRUE) - { - I2Cx->CONSET = I2C_I2CONSET_AA; - } - else - { - I2Cx->CONCLR = I2C_I2CONCLR_AAC; - } - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - while (!(I2Cx->CONSET & I2C_I2CONSET_SI)); - *retdat = (uint8_t) (I2Cx->DAT & I2C_I2DAT_BITMASK); - return (I2Cx->STAT & I2C_STAT_CODE_BITMASK); -} - -/* End of Private Functions --------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup I2C_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initializes the I2Cx peripheral with specified parameter. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] clockrate Target clock rate value to initialized I2C - * peripheral (Hz) - * @return None - *********************************************************************/ -void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate) -{ - uint32_t tem; - - CHECK_PARAM(PARAM_I2Cx(I2Cx)); - - if (I2Cx==LPC_I2C0) - { - /* Set up clock for I2C0 module */ - //LPC_CGU->BASE_VPB1_CLK = (SRC_PL160M_0<<24) | (1<<11); - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1); - /* Select weather standard, fast, fast plus mode*/ - if(clockrate>=1000000)// Fast mode plus: 1MHz, high speed 3.4MHz - LPC_SCU->SFSI2C0 = SFSI2C0_CONFIGURE_FASTPLUS_HIGHSPEED_MODE; - else // standard 100KHz, fast 400KHz - LPC_SCU->SFSI2C0 = SFSI2C0_CONFIGURE_STANDARD_FAST_MODE; - } - else if (I2Cx==LPC_I2C1) - { - /* Set up clock for I2C1 module */ - //LPC_CGU->BASE_VPB3_CLK = (SRC_PL160M_0<<24) | (1<<11); - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB3); - /* Configure pin function for I2C1*/ - LPC_SCU->SFSP2_3 = SFSP2_3_CONFIGURE_I2C1_SDA; /* SDA */ - LPC_SCU->SFSP2_4 = SFSP2_4_CONFIGURE_I2C1_SCL; /* SCL */ - /* Check if I2C1 run fast mode*/ - if(clockrate != 400000) - return; - } - else { - // Up-Support this device - return; - } - - /* Set clock rate */ - if(clockrate<1000) //make sure SCLH,SCLL not exceed its 16bit value - return; - tem = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE) / clockrate; - I2Cx->SCLH = (uint32_t)(tem / 2); - I2Cx->SCLL = (uint32_t)(tem - I2Cx->SCLH); - /* Set I2C operation to default */ - I2Cx->CONCLR = (I2C_I2CONCLR_AAC |I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC); -} - - -/*********************************************************************//** - * @brief De-initializes the I2C peripheral registers to their - * default reset values. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return None - **********************************************************************/ -void I2C_DeInit(LPC_I2Cn_Type* I2Cx) -{ - CHECK_PARAM(PARAM_I2Cx(I2Cx)); - - /* Disable I2C control */ - I2Cx->CONCLR = I2C_I2CONCLR_I2ENC; - -} - - -/*********************************************************************//** - * @brief Enable or disable I2C peripheral's operation - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] NewState New State of I2Cx peripheral's operation, should be: - * - ENABLE :enable I2C operation - * - DISABLE :disable I2C operation - * @return none - **********************************************************************/ -void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - CHECK_PARAM(PARAM_I2Cx(I2Cx)); - - if (NewState == ENABLE) - { - I2Cx->CONSET = I2C_I2CONSET_I2EN; - } - else - { - I2Cx->CONCLR = I2C_I2CONCLR_I2ENC; - } -} - - -/*********************************************************************//** - * @brief Enable/Disable interrupt for I2C peripheral - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] NewState New State of I2C peripheral interrupt in NVIC core - * should be: - * - ENABLE: enable interrupt for this I2C peripheral - * - DISABLE: disable interrupt for this I2C peripheral - * @return None - **********************************************************************/ -void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState) -{ - if (NewState) - { - if(I2Cx == LPC_I2C0) - { - NVIC_EnableIRQ(I2C0_IRQn); - } - else if (I2Cx == LPC_I2C1) - { - NVIC_EnableIRQ(I2C1_IRQn); - } - } - else - { - if(I2Cx == LPC_I2C0) - { - NVIC_DisableIRQ(I2C0_IRQn); - } - else if (I2Cx == LPC_I2C1) - { - NVIC_DisableIRQ(I2C1_IRQn); - } - } - return; -} - - -/*********************************************************************//** - * @brief General Master Interrupt handler for I2C peripheral - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return None - **********************************************************************/ -void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx) -{ - int32_t tmp; - uint8_t returnCode; - I2C_M_SETUP_Type *txrx_setup; - - tmp = I2C_getNum(I2Cx); - txrx_setup = (I2C_M_SETUP_Type *) i2cdat[tmp].txrx_setup; - - returnCode = (I2Cx->STAT & I2C_STAT_CODE_BITMASK); - // Save current status - txrx_setup->status = returnCode; - // there's no relevant information - if (returnCode == I2C_I2STAT_NO_INF){ - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - return; - } - - /* ----------------------------- TRANSMIT PHASE --------------------------*/ - if (i2cdat[tmp].dir == 0){ - switch (returnCode) - { - /* A start/repeat start condition has been transmitted -------------------*/ - case I2C_I2STAT_M_TX_START: - case I2C_I2STAT_M_TX_RESTART: - I2Cx->CONCLR = I2C_I2CONCLR_STAC; - /* - * If there's any transmit data, then start to - * send SLA+W right now, otherwise check whether if there's - * any receive data for next state. - */ - if ((txrx_setup->tx_data != NULL) && (txrx_setup->tx_length != 0)){ - I2Cx->DAT = (txrx_setup->sl_addr7bit << 1); - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - } else { - goto next_stage; - } - break; - - /* SLA+W has been transmitted, ACK has been received ----------------------*/ - case I2C_I2STAT_M_TX_SLAW_ACK: - /* Data has been transmitted, ACK has been received */ - case I2C_I2STAT_M_TX_DAT_ACK: - /* Send more data */ - if ((txrx_setup->tx_count < txrx_setup->tx_length) \ - && (txrx_setup->tx_data != NULL)){ - I2Cx->DAT = *(uint8_t *)(txrx_setup->tx_data + txrx_setup->tx_count); - txrx_setup->tx_count++; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - } - // no more data, switch to next stage - else { -next_stage: - // change direction - i2cdat[tmp].dir = 1; - // Check if any data to receive - if ((txrx_setup->rx_length != 0) && (txrx_setup->rx_data != NULL)){ - // check whether if we need to issue an repeat start - if ((txrx_setup->tx_length != 0) && (txrx_setup->tx_data != NULL)){ - // Send out an repeat start command - I2Cx->CONSET = I2C_I2CONSET_STA; - I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC; - } - // Don't need issue an repeat start, just goto send SLA+R - else { - goto send_slar; - } - } - // no more data send, the go to end stage now - else { - // success, goto end stage - txrx_setup->status |= I2C_SETUP_STATUS_DONE; - goto end_stage; - } - } - break; - - /* SLA+W has been transmitted, NACK has been received ----------------------*/ - case I2C_I2STAT_M_TX_SLAW_NACK: - /* Data has been transmitted, NACK has been received -----------------------*/ - case I2C_I2STAT_M_TX_DAT_NACK: - // update status - txrx_setup->status |= I2C_SETUP_STATUS_NOACKF; - goto retry; - /* Arbitration lost in SLA+R/W or Data bytes -------------------------------*/ - case I2C_I2STAT_M_TX_ARB_LOST: - // update status - txrx_setup->status |= I2C_SETUP_STATUS_ARBF; - default: - goto retry; - } - } - - /* ----------------------------- RECEIVE PHASE --------------------------*/ - else if (i2cdat[tmp].dir == 1){ - switch (returnCode){ - /* A start/repeat start condition has been transmitted ---------------------*/ - case I2C_I2STAT_M_RX_START: - case I2C_I2STAT_M_RX_RESTART: - I2Cx->CONCLR = I2C_I2CONCLR_STAC; - /* - * If there's any receive data, then start to - * send SLA+R right now, otherwise check whether if there's - * any receive data for end of state. - */ - if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_length != 0)){ -send_slar: - I2Cx->DAT = (txrx_setup->sl_addr7bit << 1) | 0x01; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - } else { - // Success, goto end stage - txrx_setup->status |= I2C_SETUP_STATUS_DONE; - goto end_stage; - } - break; - - /* SLA+R has been transmitted, ACK has been received -----------------*/ - case I2C_I2STAT_M_RX_SLAR_ACK: - if (txrx_setup->rx_count < (txrx_setup->rx_length - 1)) { - /*Data will be received, ACK will be return*/ - I2Cx->CONSET = I2C_I2CONSET_AA; - } - else { - /*Last data will be received, NACK will be return*/ - I2Cx->CONCLR = I2C_I2CONSET_AA; - } - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Data has been received, ACK has been returned ----------------------*/ - case I2C_I2STAT_M_RX_DAT_ACK: - // Note save data and increase counter first, then check later - /* Save data */ - if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_count < txrx_setup->rx_length)){ - *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (I2Cx->DAT & I2C_I2DAT_BITMASK); - txrx_setup->rx_count++; - } - if (txrx_setup->rx_count < (txrx_setup->rx_length - 1)) { - /*Data will be received, ACK will be return*/ - I2Cx->CONSET = I2C_I2CONSET_AA; - } - else { - /*Last data will be received, NACK will be return*/ - I2Cx->CONCLR = I2C_I2CONSET_AA; - } - - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Data has been received, NACK has been return -------------------------*/ - case I2C_I2STAT_M_RX_DAT_NACK: - /* Save the last data */ - if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_count < txrx_setup->rx_length)){ - *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (I2Cx->DAT & I2C_I2DAT_BITMASK); - txrx_setup->rx_count++; - } - // success, go to end stage - txrx_setup->status |= I2C_SETUP_STATUS_DONE; - goto end_stage; - - /* SLA+R has been transmitted, NACK has been received ------------------*/ - case I2C_I2STAT_M_RX_SLAR_NACK: - // update status - txrx_setup->status |= I2C_SETUP_STATUS_NOACKF; - goto retry; - - /* Arbitration lost ----------------------------------------------------*/ - case I2C_I2STAT_M_RX_ARB_LOST: - // update status - txrx_setup->status |= I2C_SETUP_STATUS_ARBF; - default: -retry: - // check if retransmission is available - if (txrx_setup->retransmissions_count < txrx_setup->retransmissions_max){ - // Clear tx count - txrx_setup->tx_count = 0; - I2Cx->CONSET = I2C_I2CONSET_STA; - I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC; - txrx_setup->retransmissions_count++; - } - // End of stage - else { -end_stage: - // Disable interrupt - I2C_IntCmd(I2Cx, FALSE); - // Send stop - I2C_Stop(I2Cx); - - I2C_MasterComplete[tmp] = TRUE; - } - break; - } - } -} - - -/*********************************************************************//** - * @brief General Slave Interrupt handler for I2C peripheral - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return None - **********************************************************************/ -void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx) -{ - int32_t tmp; - uint8_t returnCode; - I2C_S_SETUP_Type *txrx_setup; - uint32_t timeout; - - tmp = I2C_getNum(I2Cx); - txrx_setup = (I2C_S_SETUP_Type *) i2cdat[tmp].txrx_setup; - - returnCode = (I2Cx->STAT & I2C_STAT_CODE_BITMASK); - // Save current status - txrx_setup->status = returnCode; - // there's no relevant information - if (returnCode == I2C_I2STAT_NO_INF){ - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - return; - } - - - switch (returnCode) - { - - /* No status information */ - case I2C_I2STAT_NO_INF: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Reading phase -------------------------------------------------------- */ - /* Own SLA+R has been received, ACK has been returned */ - case I2C_I2STAT_S_RX_SLAW_ACK: - /* General call address has been received, ACK has been returned */ - case I2C_I2STAT_S_RX_GENCALL_ACK: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Previously addressed with own SLA; - * DATA byte has been received; - * ACK has been returned */ - case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK: - /* DATA has been received, ACK hasn been return */ - case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK: - /* - * All data bytes that over-flow the specified receive - * data length, just ignore them. - */ - if ((txrx_setup->rx_count < txrx_setup->rx_length) \ - && (txrx_setup->rx_data != NULL)){ - *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (uint8_t)I2Cx->DAT; - txrx_setup->rx_count++; - } - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Previously addressed with own SLA; - * DATA byte has been received; - * NOT ACK has been returned */ - case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK: - /* DATA has been received, NOT ACK has been returned */ - case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK: - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* - * Note that: Return code only let us know a stop condition mixed - * with a repeat start condition in the same code value. - * So we should provide a time-out. In case this is really a stop - * condition, this will return back after time out condition. Otherwise, - * next session that is slave receive data will be completed. - */ - - /* A Stop or a repeat start condition */ - case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX: - // Temporally lock the interrupt for timeout condition - I2C_IntCmd(I2Cx, FALSE); - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - // enable time out - timeout = I2C_SLAVE_TIME_OUT; - while(1){ - if (I2Cx->CONSET & I2C_I2CONSET_SI){ - // re-Enable interrupt - I2C_IntCmd(I2Cx, TRUE); - break; - } else { - timeout--; - if (timeout == 0){ - // timeout occur, it's really a stop condition - txrx_setup->status |= I2C_SETUP_STATUS_DONE; - goto s_int_end; - } - } - } - break; - - /* Writing phase -------------------------------------------------------- */ - /* Own SLA+R has been received, ACK has been returned */ - case I2C_I2STAT_S_TX_SLAR_ACK: - /* Data has been transmitted, ACK has been received */ - case I2C_I2STAT_S_TX_DAT_ACK: - /* - * All data bytes that over-flow the specified receive - * data length, just ignore them. - */ - if ((txrx_setup->tx_count < txrx_setup->tx_length) \ - && (txrx_setup->tx_data != NULL)){ - I2Cx->DAT = *(uint8_t *) (txrx_setup->tx_data + txrx_setup->tx_count); - txrx_setup->tx_count++; - } - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Data has been transmitted, NACK has been received, - * that means there's no more data to send, exit now */ - /* - * Note: Don't wait for stop event since in slave transmit mode, - * since there no proof lets us know when a stop signal has been received - * on slave side. - */ - case I2C_I2STAT_S_TX_DAT_NACK: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - txrx_setup->status |= I2C_SETUP_STATUS_DONE; - goto s_int_end; - - // Other status must be captured - default: -s_int_end: - // Disable interrupt - I2C_IntCmd(I2Cx, FALSE); - I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; - I2C_SlaveComplete[tmp] = TRUE; - break; - } -} - - -/*********************************************************************//** - * @brief Transmit and Receive data in master mode - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] TransferCfg Pointer to a I2C_M_SETUP_Type structure that - * contains specified information about the configuration - * for master transfer. - * @param[in] Opt a I2C_TRANSFER_OPT_Type type that selected for interrupt - * or polling mode. - * @return Transmit/receive status, should be: - * - SUCCESS - * - ERROR - * - * Note: - * - In case of using I2C to transmit data only, either transmit length set to 0 - * or transmit data pointer set to NULL. - * - In case of using I2C to receive data only, either receive length set to 0 - * or receive data pointer set to NULL. - * - In case of using I2C to transmit followed by receive data, transmit length, - * transmit data pointer, receive length and receive data pointer should be set - * corresponding. - **********************************************************************/ -Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, \ - I2C_TRANSFER_OPT_Type Opt) -{ - uint8_t *txdat; - uint8_t *rxdat; - uint32_t CodeStatus; - uint8_t tmp; - - // reset all default state - txdat = (uint8_t *) TransferCfg->tx_data; - rxdat = (uint8_t *) TransferCfg->rx_data; - // Reset I2C setup value to default state - TransferCfg->tx_count = 0; - TransferCfg->rx_count = 0; - TransferCfg->status = 0; - - if (Opt == I2C_TRANSFER_POLLING){ - - /* First Start condition -------------------------------------------------------------- */ - TransferCfg->retransmissions_count = 0; -retry: - // reset all default state - txdat = (uint8_t *) TransferCfg->tx_data; - rxdat = (uint8_t *) TransferCfg->rx_data; - // Reset I2C setup value to default state - TransferCfg->tx_count = 0; - TransferCfg->rx_count = 0; - CodeStatus = 0; - - // Start command - CodeStatus = I2C_Start(I2Cx); - if ((CodeStatus != I2C_I2STAT_M_TX_START) \ - && (CodeStatus != I2C_I2STAT_M_TX_RESTART)){ - TransferCfg->retransmissions_count++; - if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){ - // save status - TransferCfg->status = CodeStatus; - goto error; - } else { - goto retry; - } - } - - /* In case of sending data first --------------------------------------------------- */ - if ((TransferCfg->tx_length != 0) && (TransferCfg->tx_data != NULL)){ - - /* Send slave address + WR direction bit = 0 ----------------------------------- */ - CodeStatus = I2C_SendByte(I2Cx, (TransferCfg->sl_addr7bit << 1)); - if (CodeStatus != I2C_I2STAT_M_TX_SLAW_ACK){ - TransferCfg->retransmissions_count++; - if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){ - // save status - TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF; - goto error; - } else { - goto retry; - } - } - - /* Send a number of data bytes ---------------------------------------- */ - while (TransferCfg->tx_count < TransferCfg->tx_length) - { - CodeStatus = I2C_SendByte(I2Cx, *txdat); - if (CodeStatus != I2C_I2STAT_M_TX_DAT_ACK){ - TransferCfg->retransmissions_count++; - if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){ - // save status - TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF; - goto error; - } else { - goto retry; - } - } - - txdat++; - TransferCfg->tx_count++; - } - } - - /* Second Start condition (Repeat Start) ------------------------------------------- */ - if ((TransferCfg->tx_length != 0) && (TransferCfg->tx_data != NULL) \ - && (TransferCfg->rx_length != 0) && (TransferCfg->rx_data != NULL)){ - - CodeStatus = I2C_Start(I2Cx); - if ((CodeStatus != I2C_I2STAT_M_RX_START) \ - && (CodeStatus != I2C_I2STAT_M_RX_RESTART)){ - TransferCfg->retransmissions_count++; - if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){ - // Update status - TransferCfg->status = CodeStatus; - goto error; - } else { - goto retry; - } - } - } - - /* Then, start reading after sending data -------------------------------------- */ - if ((TransferCfg->rx_length != 0) && (TransferCfg->rx_data != NULL)){ - /* Send slave address + RD direction bit = 1 ----------------------------------- */ - - CodeStatus = I2C_SendByte(I2Cx, ((TransferCfg->sl_addr7bit << 1) | 0x01)); - if (CodeStatus != I2C_I2STAT_M_RX_SLAR_ACK){ - TransferCfg->retransmissions_count++; - if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){ - // update status - TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF; - goto error; - } else { - goto retry; - } - } - - /* Receive a number of data bytes ------------------------------------------------- */ - while (TransferCfg->rx_count < TransferCfg->rx_length){ - - /* - * Note that: if data length is only one, the master should not - * issue an ACK signal on bus after reading to avoid of next data frame - * on slave side - */ - if (TransferCfg->rx_count < (TransferCfg->rx_length - 1)){ - // Issue an ACK signal for next data frame - CodeStatus = I2C_GetByte(I2Cx, &tmp, TRUE); - if (CodeStatus != I2C_I2STAT_M_RX_DAT_ACK){ - TransferCfg->retransmissions_count++; - if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){ - // update status - TransferCfg->status = CodeStatus; - goto error; - } else { - goto retry; - } - } - } else { - // Do not issue an ACK signal - CodeStatus = I2C_GetByte(I2Cx, &tmp, FALSE); - if (CodeStatus != I2C_I2STAT_M_RX_DAT_NACK){ - TransferCfg->retransmissions_count++; - if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){ - // update status - TransferCfg->status = CodeStatus; - goto error; - } else { - goto retry; - } - } - } - *rxdat++ = tmp; - TransferCfg->rx_count++; - } - } - - /* Send STOP condition ------------------------------------------------- */ - I2C_Stop(I2Cx); - return SUCCESS; - -error: - // Send stop condition - I2C_Stop(I2Cx); - return ERROR; - } - - else if (Opt == I2C_TRANSFER_INTERRUPT){ - // Setup tx_rx data, callback and interrupt handler - tmp = I2C_getNum(I2Cx); - i2cdat[tmp].txrx_setup = (uint32_t) TransferCfg; - // Set direction phase, write first - i2cdat[tmp].dir = 0; - - /* First Start condition -------------------------------------------------------------- */ - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - I2Cx->CONSET = I2C_I2CONSET_STA; - I2C_IntCmd(I2Cx, TRUE); - - return (SUCCESS); - } - - return ERROR; -} - - -/*********************************************************************//** - * @brief Receive and Transmit data in slave mode - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that - * contains specified information about the configuration for - * master transfer. - * @param[in] Opt I2C_TRANSFER_OPT_Type type that selected for interrupt - * or polling mode. - * @return Transmit/receive status, could be: - * - SUCCESS - * - ERRRO - * - * Note: - * The mode of slave's operation depends on the command sent from master on - * the I2C bus. If the master send a SLA+W command, this sub-routine will - * use receive data length and receive data pointer. If the master send a SLA+R - * command, this sub-routine will use transmit data length and transmit data - * pointer. - * If the master issue an repeat start command or a stop command, the slave will - * enable an time out condition, during time out condition, if there's no activity - * on I2C bus, the slave will exit, otherwise (i.e. the master send a SLA+R/W), - * the slave then switch to relevant operation mode. The time out should be used - * because the return status code can not show difference from stop and repeat - * start command in slave operation. - * In case of the expected data length from master is greater than data length - * that slave can support: - * - In case of reading operation (from master): slave will return I2C_I2DAT_IDLE_CHAR - * value. - * - In case of writing operation (from master): slave will ignore remain data from master. - **********************************************************************/ -Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, \ - I2C_TRANSFER_OPT_Type Opt) -{ - uint8_t *txdat; - uint8_t *rxdat; - uint32_t CodeStatus; - uint32_t timeout; - int32_t time_en; - int32_t tmp; - - // reset all default state - txdat = (uint8_t *) TransferCfg->tx_data; - rxdat = (uint8_t *) TransferCfg->rx_data; - // Reset I2C setup value to default state - TransferCfg->tx_count = 0; - TransferCfg->rx_count = 0; - TransferCfg->status = 0; - - - // Polling option - if (Opt == I2C_TRANSFER_POLLING){ - - /* Set AA bit to ACK command on I2C bus */ - I2Cx->CONSET = I2C_I2CONSET_AA; - /* Clear SI bit to be ready ... */ - I2Cx->CONCLR = (I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC); - - time_en = 0; - timeout = 0; - - while (1) - { - /* Check SI flag ready */ - if (I2Cx->CONSET & I2C_I2CONSET_SI) - { - time_en = 0; - - switch (CodeStatus = (I2Cx->STAT & I2C_STAT_CODE_BITMASK)) - { - - /* No status information */ - case I2C_I2STAT_NO_INF: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Reading phase -------------------------------------------------------- */ - /* Own SLA+R has been received, ACK has been returned */ - case I2C_I2STAT_S_RX_SLAW_ACK: - /* General call address has been received, ACK has been returned */ - case I2C_I2STAT_S_RX_GENCALL_ACK: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Previously addressed with own SLA; - * DATA byte has been received; - * ACK has been returned */ - case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK: - /* DATA has been received, ACK hasn been return */ - case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK: - /* - * All data bytes that over-flow the specified receive - * data length, just ignore them. - */ - if ((TransferCfg->rx_count < TransferCfg->rx_length) \ - && (TransferCfg->rx_data != NULL)){ - *rxdat++ = (uint8_t)I2Cx->DAT; - TransferCfg->rx_count++; - } - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Previously addressed with own SLA; - * DATA byte has been received; - * NOT ACK has been returned */ - case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK: - /* DATA has been received, NOT ACK has been returned */ - case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK: - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* - * Note that: Return code only let us know a stop condition mixed - * with a repeat start condition in the same code value. - * So we should provide a time-out. In case this is really a stop - * condition, this will return back after time out condition. Otherwise, - * next session that is slave receive data will be completed. - */ - - /* A Stop or a repeat start condition */ - case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX: - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - // enable time out - time_en = 1; - timeout = 0; - break; - - /* Writing phase -------------------------------------------------------- */ - /* Own SLA+R has been received, ACK has been returned */ - case I2C_I2STAT_S_TX_SLAR_ACK: - /* Data has been transmitted, ACK has been received */ - case I2C_I2STAT_S_TX_DAT_ACK: - /* - * All data bytes that over-flow the specified receive - * data length, just ignore them. - */ - if ((TransferCfg->tx_count < TransferCfg->tx_length) \ - && (TransferCfg->tx_data != NULL)){ - I2Cx->DAT = *txdat++; - TransferCfg->tx_count++; - } - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - break; - - /* Data has been transmitted, NACK has been received, - * that means there's no more data to send, exit now */ - /* - * Note: Don't wait for stop event since in slave transmit mode, - * since there no proof lets us know when a stop signal has been received - * on slave side. - */ - case I2C_I2STAT_S_TX_DAT_NACK: - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - // enable time out - time_en = 1; - timeout = 0; - break; - - // Other status must be captured - default: - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - goto s_error; - } - } else if (time_en){ - if (timeout++ > I2C_SLAVE_TIME_OUT){ - // it's really a stop condition, goto end stage - goto s_end_stage; - } - } - } - -s_end_stage: - /* Clear AA bit to disable ACK on I2C bus */ - I2Cx->CONCLR = I2C_I2CONCLR_AAC; - // Check if there's no error during operation - // Update status - TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_DONE; - return SUCCESS; - -s_error: - /* Clear AA bit to disable ACK on I2C bus */ - I2Cx->CONCLR = I2C_I2CONCLR_AAC; - // Update status - TransferCfg->status = CodeStatus; - return ERROR; - } - - else if (Opt == I2C_TRANSFER_INTERRUPT){ - // Setup tx_rx data, callback and interrupt handler - tmp = I2C_getNum(I2Cx); - i2cdat[tmp].txrx_setup = (uint32_t) TransferCfg; - // Set direction phase, read first - i2cdat[tmp].dir = 1; - - // Enable AA - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; - I2C_IntCmd(I2Cx, TRUE); - - return (SUCCESS); - } - - return ERROR; -} - -/*********************************************************************//** - * @brief Set Own slave address in I2C peripheral corresponding to - * parameter specified in OwnSlaveAddrConfigStruct. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] OwnSlaveAddrConfigStruct Pointer to a I2C_OWNSLAVEADDR_CFG_Type - * structure that contains the configuration information for the - * specified I2C slave address. - * @return None - **********************************************************************/ -void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct) -{ - uint32_t tmp; - CHECK_PARAM(PARAM_I2Cx(I2Cx)); - CHECK_PARAM(PARAM_I2C_SLAVEADDR_CH(OwnSlaveAddrConfigStruct->SlaveAddrChannel)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(OwnSlaveAddrConfigStruct->GeneralCallState)); - - tmp = (((uint32_t)(OwnSlaveAddrConfigStruct->SlaveAddr_7bit << 1)) \ - | ((OwnSlaveAddrConfigStruct->GeneralCallState == ENABLE) ? 0x01 : 0x00))& I2C_I2ADR_BITMASK; - switch (OwnSlaveAddrConfigStruct->SlaveAddrChannel) - { - case 0: - I2Cx->ADR0 = tmp; - I2Cx->MASK[0] = I2C_I2MASK_MASK((uint32_t) \ - (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); - break; - case 1: - I2Cx->ADR1 = tmp; - I2Cx->MASK[1] = I2C_I2MASK_MASK((uint32_t) \ - (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); - break; - case 2: - I2Cx->ADR2 = tmp; - I2Cx->MASK[2] = I2C_I2MASK_MASK((uint32_t) \ - (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); - break; - case 3: - I2Cx->ADR3 = tmp; - I2Cx->MASK[3] = I2C_I2MASK_MASK((uint32_t) \ - (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); - break; - } -} - - -/*********************************************************************//** - * @brief Configures functionality in I2C monitor mode - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] MonitorCfgType Monitor Configuration type, should be: - * - I2C_MONITOR_CFG_SCL_OUTPUT :I2C module can 'stretch' - * the clock line (hold it low) until it has had time to respond - * to an I2C interrupt. - * - I2C_MONITOR_CFG_MATCHALL :When this bit is set to '1' - * and the I2C is in monitor mode, an interrupt will be generated - * on ANY address received. - * @param[in] NewState New State of this function, should be: - * - ENABLE :Enable this function. - * - DISABLE :Disable this function. - * @return None - **********************************************************************/ -void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_I2Cx(I2Cx)); - CHECK_PARAM(PARAM_I2C_MONITOR_CFG(MonitorCfgType)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - I2Cx->MMCTRL |= MonitorCfgType; - } - else - { - I2Cx->MMCTRL &= (~MonitorCfgType) & I2C_I2MMCTRL_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Enable/Disable I2C monitor mode - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @param[in] NewState New State of this function, should be: - * - ENABLE :Enable monitor mode. - * - DISABLE :Disable monitor mode. - * @return None - **********************************************************************/ -void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_I2Cx(I2Cx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - I2Cx->MMCTRL |= I2C_I2MMCTRL_MM_ENA; - I2Cx->CONSET = I2C_I2CONSET_AA; - I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; - } - else - { - I2Cx->MMCTRL &= (~I2C_I2MMCTRL_MM_ENA) & I2C_I2MMCTRL_BITMASK; - I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_AAC; - } - I2C_MonitorBufferIndex = 0; -} - - -/*********************************************************************//** - * @brief Get data from I2C data buffer in monitor mode. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return None - * Note: In monitor mode, the I2C module may lose the ability to stretch - * the clock (stall the bus) if the ENA_SCL bit is not set. This means that - * the processor will have a limited amount of time to read the contents of - * the data received on the bus. If the processor reads the I2DAT shift - * register, as it ordinarily would, it could have only one bit-time to - * respond to the interrupt before the received data is overwritten by - * new data. - **********************************************************************/ -uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx) -{ - CHECK_PARAM(PARAM_I2Cx(I2Cx)); - return ((uint8_t)(I2Cx->DATA_BUFFER)); -} - - -/*********************************************************************//** - * @brief Get data from I2C data buffer in monitor mode. - * @param[in] I2Cx I2C peripheral selected, should be - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return None - * Note: In monitor mode, the I2C module may lose the ability to stretch - * the clock (stall the bus) if the ENA_SCL bit is not set. This means that - * the processor will have a limited amount of time to read the contents of - * the data received on the bus. If the processor reads the I2DAT shift - * register, as it ordinarily would, it could have only one bit-time to - * respond to the interrupt before the received data is overwritten by - * new data. - **********************************************************************/ -BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size) -{ - BOOL_8 ret=FALSE; - - I2Cx->CONCLR = I2C_I2CONCLR_SIC; - - buffer[I2C_MonitorBufferIndex] = (uint8_t)(I2Cx->DATA_BUFFER); - I2C_MonitorBufferIndex++; - if(I2C_MonitorBufferIndex >= size) - { - ret = TRUE; - } - return ret; -} - - -/*********************************************************************//** - * @brief Get status of Master Transfer - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return Master transfer status, could be: - * - TRUE :master transfer completed - * - FALSE :master transfer have not completed yet - **********************************************************************/ -uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx) -{ - uint32_t retval, tmp; - tmp = I2C_getNum(I2Cx); - retval = I2C_MasterComplete[tmp]; - I2C_MasterComplete[tmp] = FALSE; - return retval; -} - - -/*********************************************************************//** - * @brief Get status of Slave Transfer - * @param[in] I2Cx I2C peripheral selected, should be: - * - LPC_I2C0 :I2C0 peripheral - * - LPC_I2C1 :I2C1 peripheral - * @return Complete status, could be: TRUE/FALSE - **********************************************************************/ -uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx) -{ - uint32_t retval, tmp; - tmp = I2C_getNum(I2Cx); - retval = I2C_SlaveComplete[tmp]; - I2C_SlaveComplete[tmp] = FALSE; - return retval; -} - - - -/** - * @} - */ - -#endif /* _I2C */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2s.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2s.c deleted file mode 100644 index 3bb7a5440..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2s.c +++ /dev/null @@ -1,663 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_i2s.c 2011-06-02 -*//** -* @file lpc18xx_i2s.c -* @brief Contains all functions support for I2S firmware library -* on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup I2S - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_i2s.h" -#include "lpc18xx_cgu.h" - - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _I2S - -/* Private Functions ---------------------------------------------------------- */ - -static uint8_t i2s_GetWordWidth(LPC_I2Sn_Type *I2Sx, uint8_t TRMode); -static uint8_t i2s_GetChannel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode); - -/********************************************************************//** - * @brief Get I2S wordwidth value - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is the I2S mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return The wordwidth value, should be: 8,16 or 32 - *********************************************************************/ -static uint8_t i2s_GetWordWidth(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) { - uint8_t value; - - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if (TRMode == I2S_TX_MODE) { - value = (I2Sx->DAO) & 0x03; /* get wordwidth bit */ - } else { - value = (I2Sx->DAI) & 0x03; /* get wordwidth bit */ - } - switch (value) { - case I2S_WORDWIDTH_8: - return 8; - case I2S_WORDWIDTH_16: - return 16; - default: - return 32; - } -} - -/********************************************************************//** - * @brief Get I2S channel value - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is the I2S mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return The channel value, should be: 1(mono) or 2(stereo) - *********************************************************************/ -static uint8_t i2s_GetChannel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) { - uint8_t value; - - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if (TRMode == I2S_TX_MODE) { - value = (I2Sx->DAO) & 0x04; /* get bit[2] */ - } else { - value = (I2Sx->DAI) & 0x04; /* get bit[2] */ - } - value >>= 2; - if(value == I2S_MONO) return 1; - return 2; -} - -/* End of Private Functions --------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup I2S_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initialize I2S - * - Turn on power and clock - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @return none - *********************************************************************/ -void I2S_Init(LPC_I2Sn_Type *I2Sx) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - - // Turn on power and clock - //CGU_ConfigPPWR(CGU_PCONP_PCI2S, ENABLE); - I2Sx->DAI = I2Sx->DAO = 0x00; -} - -/********************************************************************//** - * @brief Configuration I2S, setting: - * - master/slave mode - * - wordwidth value - * - channel mode - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @param[in] ConfigStruct pointer to I2S_CFG_Type structure - * which will be initialized. - * @return none - *********************************************************************/ -void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct) -{ - uint32_t bps, config; - - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - - CHECK_PARAM(PARAM_I2S_WORDWIDTH(ConfigStruct->wordwidth)); - CHECK_PARAM(PARAM_I2S_CHANNEL(ConfigStruct->mono)); - CHECK_PARAM(PARAM_I2S_STOP(ConfigStruct->stop)); - CHECK_PARAM(PARAM_I2S_RESET(ConfigStruct->reset)); - CHECK_PARAM(PARAM_I2S_WS_SEL(ConfigStruct->ws_sel)); - CHECK_PARAM(PARAM_I2S_MUTE(ConfigStruct->mute)); - - /* Setup clock */ - bps = (ConfigStruct->wordwidth +1)*8; - - /* Calculate audio config */ - config = (bps - 1)<<6 | (ConfigStruct->ws_sel)<<5 | (ConfigStruct->reset)<<4 | - (ConfigStruct->stop)<<3 | (ConfigStruct->mono)<<2 | (ConfigStruct->wordwidth); - - if(TRMode == I2S_RX_MODE){ - I2Sx->DAI = config; - }else{ - I2Sx->DAO = config; - } -} - -/********************************************************************//** - * @brief DeInitial both I2S transmit or receive - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @return none - *********************************************************************/ -void I2S_DeInit(LPC_I2Sn_Type *I2Sx) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - - // Turn off power and clock - //CGU_ConfigPPWR(CGU_PCONP_PCI2S, DISABLE); -} - -/********************************************************************//** - * @brief Get I2S Buffer Level - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode Transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return current level of Transmit/Receive Buffer - *********************************************************************/ -uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) -{ - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if(TRMode == I2S_TX_MODE) - { - return ((I2Sx->STATE >> 16) & 0xFF); - } - else - { - return ((I2Sx->STATE >> 8) & 0xFF); - } -} - -/********************************************************************//** - * @brief I2S Start: clear all STOP,RESET and MUTE bit, ready to operate - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @return none - *********************************************************************/ -void I2S_Start(LPC_I2Sn_Type *I2Sx) -{ - //Clear STOP,RESET and MUTE bit - I2Sx->DAO &= ~I2S_DAI_RESET; - I2Sx->DAI &= ~I2S_DAI_RESET; - I2Sx->DAO &= ~I2S_DAI_STOP; - I2Sx->DAI &= ~I2S_DAI_STOP; - I2Sx->DAO &= ~I2S_DAI_MUTE; -} - -/********************************************************************//** - * @brief I2S Send data - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] BufferData pointer to uint32_t is the data will be send - * @return none - *********************************************************************/ -void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - - I2Sx->TXFIFO = BufferData; -} - -/********************************************************************//** - * @brief I2S Receive Data - * @param[in] I2Sx pointer to LPC_I2Sn_Type, should be: LPC_I2S - * @return received value - *********************************************************************/ -uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - - return (I2Sx->RXFIFO); - -} - -/********************************************************************//** - * @brief I2S Pause - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return none - *********************************************************************/ -void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if (TRMode == I2S_TX_MODE) //Transmit mode - { - I2Sx->DAO |= I2S_DAO_STOP; - } else //Receive mode - { - I2Sx->DAI |= I2S_DAI_STOP; - } -} - -/********************************************************************//** - * @brief I2S Mute - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return none - *********************************************************************/ -void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if (TRMode == I2S_TX_MODE) //Transmit mode - { - I2Sx->DAO |= I2S_DAO_MUTE; - } else //Receive mode - { - I2Sx->DAI |= I2S_DAI_MUTE; - } -} - -/********************************************************************//** - * @brief I2S Stop - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return none - *********************************************************************/ -void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if (TRMode == I2S_TX_MODE) //Transmit mode - { - I2Sx->DAO &= ~I2S_DAO_MUTE; - I2Sx->DAO |= I2S_DAO_STOP; - I2Sx->DAO |= I2S_DAO_RESET; - } else //Receive mode - { - I2Sx->DAI |= I2S_DAI_STOP; - I2Sx->DAI |= I2S_DAI_RESET; - } -} - -/********************************************************************//** - * @brief Set frequency for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] Freq is the frequency for I2S will be set. It can range - * from 16-96 kHz(16, 22.05, 32, 44.1, 48, 96kHz) - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return Status: ERROR or SUCCESS - *********************************************************************/ -Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode) { - - /* Calculate bit rate - * The formula is: - * bit_rate = channel*wordwidth - 1 - * 48kHz sample rate for 16 bit stereo date requires - * a bit rate of 48000*16*2=1536MHz (MCLK) - */ - uint32_t i2sPclk; - uint64_t divider; - uint8_t bitrate, channel, wordwidth; - uint32_t x, y; - uint16_t dif; - uint16_t error; - uint16_t x_divide, y_divide; - uint16_t ErrorOptimal = 0xFFFF; - uint32_t N; - - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PRAM_I2S_FREQ(Freq)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - //LPC_CGU->BASE_VPB1_CLK = 0x08<<24 | AUTO_BLOCK; - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1); - i2sPclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_I2S); - if(TRMode == I2S_TX_MODE) - { - channel = i2s_GetChannel(I2Sx,I2S_TX_MODE); - wordwidth = i2s_GetWordWidth(I2Sx,I2S_TX_MODE); - } - else - { - channel = i2s_GetChannel(I2Sx,I2S_RX_MODE); - wordwidth = i2s_GetWordWidth(I2Sx,I2S_RX_MODE); - } - bitrate = 2 * wordwidth - 1; - - /* Calculate X and Y divider - * The MCLK rate for the I2S transmitter is determined by the value - * in the I2STXRATE/I2SRXRATE register. The required I2STXRATE/I2SRXRATE - * setting depends on the desired audio sample rate desired, the format - * (stereo/mono) used, and the data size. - * The formula is: - * I2S_MCLK = PCLK * (X/Y) / 2 - * We have: - * I2S_MCLK = Freq * bit_rate * I2Sx->TXBITRATE; - * So: (X/Y) = (Freq * bit_rate * I2Sx->TXBITRATE)/PCLK*2 - * We use a loop function to chose the most suitable X,Y value - */ - - /* divider is a fixed point number with 16 fractional bits */ - divider = ((uint64_t)(Freq *( bitrate+1) * 2)<<16) / i2sPclk; - - /* find N that make x/y <= 1 -> divider <= 2^16 */ - for(N=64;N>=0;N--){ - if((divider*N) < (1<<16)) break; - } - - if(N == 0) return ERROR; - - divider *= N; - - for (y = 255; y > 0; y--) { - x = y * divider; - if(x & (0xFF000000)) continue; - dif = x & 0xFFFF; - if(dif>0x8000) error = 0x10000-dif; - else error = dif; - if (error == 0) - { - y_divide = y; - break; - } - else if (error < ErrorOptimal) - { - ErrorOptimal = error; - y_divide = y; - } - } - x_divide = ((uint64_t)y_divide * Freq *( bitrate+1)* N * 2)/i2sPclk; - if(x_divide >= 256) x_divide = 0xFF; - if(x_divide == 0) x_divide = 1; - if (TRMode == I2S_TX_MODE)// Transmitter - { - I2Sx->TXBITRATE = N; - I2Sx->TXRATE = y_divide | (x_divide << 8); - } else //Receiver - { - I2Sx->RXBITRATE = N; - I2Sx->RXRATE = y_divide | (x_divide << 8); - } - return SUCCESS; -} - -/********************************************************************//** - * @brief I2S set bitrate - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] bitrate value will be set, it can be calculate as follows: - * bitrate = channel * wordwidth - 1 - * bitrate value should be in range: 0 .. 63 - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return none - *********************************************************************/ -void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode) -{ - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_BITRATE(bitrate)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if(TRMode == I2S_TX_MODE) - { - I2Sx->TXBITRATE = bitrate; - } - else - { - I2Sx->RXBITRATE = bitrate; - } -} - -/********************************************************************//** - * @brief Configuration operating mode for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] ModeConfig pointer to I2S_MODEConf_Type will be used to - * configure - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return none - *********************************************************************/ -void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig, - uint8_t TRMode) -{ - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_CLKSEL(ModeConfig->clksel)); - CHECK_PARAM(PARAM_I2S_4PIN(ModeConfig->fpin)); - CHECK_PARAM(PARAM_I2S_MCLK(ModeConfig->mcena)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if (TRMode == I2S_TX_MODE) { - I2Sx->TXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register - if (ModeConfig->clksel == I2S_CLKSEL_MCLK) { - I2Sx->TXMODE |= 0x02; - } - if (ModeConfig->fpin == I2S_4PIN_ENABLE) { - I2Sx->TXMODE |= (1 << 2); - } - if (ModeConfig->mcena == I2S_MCLK_ENABLE) { - I2Sx->TXMODE |= (1 << 3); - } - } else { - I2Sx->RXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register - if (ModeConfig->clksel == I2S_CLKSEL_MCLK) { - I2Sx->RXMODE |= 0x02; - } - if (ModeConfig->fpin == I2S_4PIN_ENABLE) { - I2Sx->RXMODE |= (1 << 2); - } - if (ModeConfig->mcena == I2S_MCLK_ENABLE) { - I2Sx->RXMODE |= (1 << 3); - } - } -} - -/********************************************************************//** - * @brief Configure DMA operation for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] DMAConfig pointer to I2S_DMAConf_Type will be used to configure - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return none - *********************************************************************/ -void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig, - uint8_t TRMode) -{ - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_DMA(DMAConfig->DMAIndex)); - CHECK_PARAM(PARAM_I2S_DMA_DEPTH(DMAConfig->depth)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if (TRMode == I2S_RX_MODE) { - if (DMAConfig->DMAIndex == I2S_DMA_1) { - I2Sx->DMA1 = (DMAConfig->depth) << 8; - } else { - I2Sx->DMA2 = (DMAConfig->depth) << 8; - } - } else { - if (DMAConfig->DMAIndex == I2S_DMA_1) { - I2Sx->DMA1 = (DMAConfig->depth) << 16; - } else { - I2Sx->DMA2 = (DMAConfig->depth) << 16; - } - } -} - -/********************************************************************//** - * @brief Enable/Disable DMA operation for I2S - * @param[in] I2Sx: I2S peripheral selected, should be: LPC_I2S - * @param[in] DMAIndex chose what DMA is used, should be: - * - I2S_DMA_1 = 0 :DMA1 - * - I2S_DMA_2 = 1 :DMA2 - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @param[in] NewState is new state of DMA operation, should be: - * - ENABLE - * - DISABLE - * @return none - *********************************************************************/ -void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex, uint8_t TRMode, - FunctionalState NewState) -{ - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - CHECK_PARAM(PARAM_I2S_DMA(DMAIndex)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - - if (TRMode == I2S_RX_MODE) { - if (DMAIndex == I2S_DMA_1) { - if (NewState == ENABLE) - I2Sx->DMA1 |= 0x01; - else - I2Sx->DMA1 &= ~0x01; - } else { - if (NewState == ENABLE) - I2Sx->DMA2 |= 0x01; - else - I2Sx->DMA2 &= ~0x01; - } - } else { - if (DMAIndex == I2S_DMA_1) { - if (NewState == ENABLE) - I2Sx->DMA1 |= 0x02; - else - I2Sx->DMA1 &= ~0x02; - } else { - if (NewState == ENABLE) - I2Sx->DMA2 |= 0x02; - else - I2Sx->DMA2 &= ~0x02; - } - } -} - -/********************************************************************//** - * @brief Configure IRQ for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @param[in] level is the FIFO level that triggers IRQ request - * @return none - *********************************************************************/ -void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_I2S_TRX(TRMode)); - CHECK_PARAM(PARAM_I2S_IRQ_LEVEL(level)); - - if (TRMode == I2S_RX_MODE) { - I2Sx->IRQ |= (level << 8); - } else { - I2Sx->IRQ |= (level << 16); - } -} - -/********************************************************************//** - * @brief Enable/Disable IRQ for I2S - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @param[in] NewState is new state of DMA operation, should be: - * - ENABLE - * - DISABLE - * @return none - *********************************************************************/ -void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, FunctionalState NewState) { - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (TRMode == I2S_RX_MODE) { - if (NewState == ENABLE) - I2Sx->IRQ |= 0x01; - else - I2Sx->IRQ &= ~0x01; - //Enable DMA - - } else { - if (NewState == ENABLE) - I2Sx->IRQ |= 0x02; - else - I2Sx->IRQ &= ~0x02; - } -} - -/********************************************************************//** - * @brief Get I2S interrupt status - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return FunctionState should be: - * - ENABLE :interrupt is enable - * - DISABLE :interrupt is disable - *********************************************************************/ -FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode) -{ - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - if(TRMode == I2S_TX_MODE) - return (FunctionalState)((I2Sx->IRQ >> 1)&0x01); - else - return (FunctionalState)((I2Sx->IRQ)&0x01); -} - -/********************************************************************//** - * @brief Get I2S interrupt depth - * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S - * @param[in] TRMode is transmit/receive mode, should be: - * - I2S_TX_MODE = 0 :transmit mode - * - I2S_RX_MODE = 1 :receive mode - * @return depth of FIFO level on which to create an irq request - *********************************************************************/ -uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode) -{ - CHECK_PARAM(PARAM_I2Sx(I2Sx)); - if(TRMode == I2S_TX_MODE) - return (((I2Sx->IRQ)>>16)&0xFF); - else - return (((I2Sx->IRQ)>>8)&0xFF); -} -/** - * @} - */ - -#endif /* _I2S */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_lcd.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_lcd.c deleted file mode 100644 index 878af9b09..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_lcd.c +++ /dev/null @@ -1,467 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_lcd.c 2011-06-02 -*//** -* @file lpc18xx_lcd.c -* @brief Contains all function support for LCD Driver -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup LCD - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" -#include "lpc18xx_lcd.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _LCD - -LCD_CURSOR_SIZE_OPT LCD_Cursor_Size = LCD_CURSOR_64x64; - -/* Private Functions ---------------------------------------------------------- */ - -/*********************************************************************//** - * @brief Init the LPC18xx LCD Controller - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] LCD_ConfigStruct point to LCD_CFG_Type that describe the LCD Panel - * @return None - **********************************************************************/ -void LCD_Init(LPC_LCD_Type *LCDx, LCD_CFG_Type *LCD_ConfigStruct){ - uint32_t i, regValue, *pPal; - uint32_t pcd; - /* disable the display */ - LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE; - - /* Setting LCD_TIMH register */ - regValue= ( ((((LCD_ConfigStruct->screen_width/16)-1)&0x3F) << 2) - | (( (LCD_ConfigStruct->HSync_pulse_width-1) &0xFF) << 8) - | (( (LCD_ConfigStruct->horizontal_porch.front-1) &0xFF) << 16) - | (( (LCD_ConfigStruct->horizontal_porch.back-1) &0xFF) << 24) ); - - LCDx->TIMH = regValue; - - /* Setting LCD_TIMV register */ - regValue =((((LCD_ConfigStruct->screen_height-1) &0x3FF) << 0) - | (((LCD_ConfigStruct->VSync_pulse_width-1) &0x03F) << 10) - | (((LCD_ConfigStruct->vertical_porch.front-1) &0x0FF) << 16) - | (((LCD_ConfigStruct->vertical_porch.back-1) &0x0FF) << 24) ); - - LCDx->TIMV = regValue; - - /* Generate the clock and signal polarity control word */ - regValue = 0; - regValue = (((LCD_ConfigStruct->ac_bias_frequency-1) & 0x1F) << 6); - - regValue |= (LCD_ConfigStruct->OE_pol & 1)<< 14; - - regValue |= (LCD_ConfigStruct->panel_clk_edge & 1)<< 13; - - regValue |= (LCD_ConfigStruct->HSync_pol & 1)<< 12; - - regValue |= (LCD_ConfigStruct->VSync_pol & 1)<< 11; - - /* Compute clocks per line based on panel type */ - - switch(LCD_ConfigStruct->lcd_panel_type) - { - case LCD_MONO_4: - regValue |= ((((LCD_ConfigStruct->screen_width / 4)-1) & 0x3FF) << 16); - break; - case LCD_MONO_8: - regValue |= ((((LCD_ConfigStruct->screen_width / 8)-1) & 0x3FF) << 16); - break; - case LCD_CSTN: - regValue |= (((((LCD_ConfigStruct->screen_width * 3)/8)-1) & 0x3FF) << 16); - break; - case LCD_TFT: - default: - regValue |= 1<<26 | (((LCD_ConfigStruct->screen_width-1) & 0x3FF) << 16); - } - - /* panel clock divisor */ - pcd = LCD_ConfigStruct->pcd; // TODO: should be calculated from LCDDCLK - pcd &= 0x3FF; - regValue |= ((pcd>>5)<<27) | ((pcd)&0x1F); - - LCDx->POL = regValue; - - /* configure line end control */ - CHECK_PARAM(LCD_ConfigStruct->line_end_delay<=(1<<7)); - if(LCD_ConfigStruct->line_end_delay) - LCDx->LE = (LCD_ConfigStruct->line_end_delay-1) | 1<<16; - else - LCDx->LE = 0; - - /* disable interrupts */ - LCDx->INTMSK = 0; - - /* set bits per pixel */ - regValue = LCD_ConfigStruct->bits_per_pixel << 1; - - /* set color format BGR or RGB */ - regValue |= LCD_ConfigStruct->color_format << 8; - - regValue |= LCD_ConfigStruct->lcd_panel_type << 4; - - if(LCD_ConfigStruct->dual_panel == 1) - { - regValue |= 1 << 7; - } - LCDx->CTRL = regValue; - /* clear palette */ - pPal = (uint32_t*) (&(LCDx->PAL)); - - for(i = 0; i < 128; i++) - { - *pPal = 0; - pPal++; - } -} - - -/*********************************************************************//** - * @brief Deinit LCD controller - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @return None - **********************************************************************/ -void LCD_DeInit(LPC_LCD_Type *LCDx); - - -/*********************************************************************//** - * @brief Power the LCD Panel - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] OnOff Turn on/off LCD - * - TRUE :Turn on - * - FALSE :Turn off - * @return None - **********************************************************************/ -void LCD_Power(LPC_LCD_Type *LCDx, FunctionalState OnOff){ -int i; - if(OnOff){ - LPC_LCD->CTRL |= CLCDC_LCDCTRL_PWR; - for(i=0;i<100000;i++); - LPC_LCD->CTRL |= CLCDC_LCDCTRL_ENABLE; - }else{ - LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_PWR; - for(i=0;i<100000;i++); - LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE; - } -} - - -/*********************************************************************//** - * @brief Enable/Disable the LCD Controller - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] EnDis Enable/disable status - * - TRUE :Enable - * - FALSE :Disable - * @return None - **********************************************************************/ -void LCD_Enable(LPC_LCD_Type *LCDx, FunctionalState EnDis){ - if (EnDis) - { - LCDx->CTRL |= CLCDC_LCDCTRL_ENABLE; - } - else - { - LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE; - } -} - - -/*********************************************************************//** - * @brief Set LCD Frame Buffer for Single Panel or Upper Panel Frame - * Buffer for Dual Panel - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] buffer address of buffer - * @return None - **********************************************************************/ -void LCD_SetFrameBuffer(LPC_LCD_Type *LCDx, void* buffer){ - LCDx->UPBASE = (uint32_t)buffer; -} - - -/*********************************************************************//** - * @brief Set LCD Lower Panel Frame Buffer for Dual Panel - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] buffer address of buffer - * @return None - **********************************************************************/ -void LCD_SetLPFrameBuffer(LPC_LCD_Type *LCDx, void* buffer){ - LCDx->LPBASE = (uint32_t)buffer; -} - - -/*********************************************************************//** - * @brief Configure Cursor - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] cursor_size specify size of cursor - * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels - * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels - * @param[in] sync cursor sync mode - * - TRUE :cursor sync to the frame sync pulse - * - FALSE :cursor async mode - * @return None - **********************************************************************/ -void LCD_Cursor_Config(LPC_LCD_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, Bool sync){ - LCD_Cursor_Size = cursor_size; - LCDx->CRSR_CFG = ((sync?1:0)<<1) | cursor_size; -} - - -/*********************************************************************//** - * @brief Write Cursor Image into Internal Cursor Image Buffer - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] cursor_num specify number of cursor is going to be written - * this param must < 4 - * @param[in] Image point to Cursor Image Buffer - * @return None - **********************************************************************/ -void LCD_Cursor_WriteImage(LPC_LCD_Type *LCDx, uint8_t cursor_num, void* Image){ - int i,j; - uint8_t *fifoptr, *crsr_ptr = (uint8_t *)Image; - - CHECK_PARAM(cursor_num<4); - /* Check if Cursor Size was configured as 32x32 or 64x64*/ - if(LCD_Cursor_Size == LCD_CURSOR_32x32){ - i = cursor_num * 256; - j = i + 256; - }else{ - i = 0; - j = 1024; - } - fifoptr = (uint8_t*)&(LCDx->CRSR_IMG[0]); - /* Copy Cursor Image content to FIFO */ - for(; i < j; i++) - { - fifoptr[i] = *(uint8_t *)crsr_ptr; - crsr_ptr++; - } -} - - -/*********************************************************************//** - * @brief Get Internal Cursor Image Buffer Address - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] cursor_num specify number of cursor is going to be written - * this param must < 4 - * @return Cursor Image Buffer Address - **********************************************************************/ -void* LCD_Cursor_GetImageBufferAddress(LPC_LCD_Type *LCDx, uint8_t cursor_num){ - CHECK_PARAM(cursor_num<4); - return (void*)&(LCDx->CRSR_IMG[cursor_num*64]); -} - - -/*********************************************************************//** - * @brief Enable Cursor - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] cursor_num specify number of cursor is going to be written - * this param must < 4 - * @param[in] OnOff Turn on/off LCD - * - TRUE :Enable - * - FALSE :Disable - * @return None - **********************************************************************/ -void LCD_Cursor_Enable(LPC_LCD_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff){ - CHECK_PARAM(cursor_num<4); - if (OnOff) - { - LCDx->CRSR_CTRL = (cursor_num<<4) | 1; - } - else - { - LCDx->CRSR_CTRL = (cursor_num<<4); - } -} - - -/*********************************************************************//** - * @brief Load LCD Palette - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] palette point to palette address - * @return None - **********************************************************************/ -void LCD_LoadPalette(LPC_LCD_Type *LCDx, void* palette){ - LCD_PALETTE_ENTRY_Type pal_entry, *ptr_pal_entry; - uint8_t i, *pal_ptr; - /* This function supports loading of the color palette from - the C file generated by the bmp2c utility. It expects the - palette to be passed as an array of 32-bit BGR entries having - the following format: - 2:0 - Not used - 7:3 - Blue - 10:8 - Not used - 15:11 - Green - 18:16 - Not used - 23:19 - Red - 31:24 - Not used - arg = pointer to input palette table address */ - ptr_pal_entry = &pal_entry; - pal_ptr = (uint8_t *) palette; - - /* 256 entry in the palette table */ - for(i = 0; i < 256/2; i++) - { - pal_entry.Bl = (*pal_ptr++) >> 3; /* blue first */ - pal_entry.Gl = (*pal_ptr++) >> 3; /* get green */ - pal_entry.Rl = (*pal_ptr++) >> 3; /* get red */ - pal_ptr++; /* skip over the unused byte */ - /* do the most significant halfword of the palette */ - pal_entry.Bu = (*pal_ptr++) >> 3; /* blue first */ - pal_entry.Gu = (*pal_ptr++) >> 3; /* get green */ - pal_entry.Ru = (*pal_ptr++) >> 3; /* get red */ - pal_ptr++; /* skip over the unused byte */ - - LCDx->PAL[i] = *(uint32_t *)ptr_pal_entry; - } -} - - -/*********************************************************************//** - * @brief Load Cursor Palette - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] palette_color cursor palette 0 value - * @return None - **********************************************************************/ -void LCD_Cursor_LoadPalette0(LPC_LCD_Type *LCDx, uint32_t palette_color){ - /* 7:0 - Red - 15:8 - Green - 23:16 - Blue - 31:24 - Not used*/ - LCDx->CRSR_PAL0 = (uint32_t)palette_color; -} - - -/*********************************************************************//** - * @brief Load Cursor Palette - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] palette_color cursor palette 1 value - * @return None - **********************************************************************/ -void LCD_Cursor_LoadPalette1(LPC_LCD_Type *LCDx, uint32_t palette_color){ - /* 7:0 - Red - 15:8 - Green - 23:16 - Blue - 31:24 - Not used*/ - LCDx->CRSR_PAL1 = (uint32_t)palette_color; -} - - -/*********************************************************************//** - * @brief Set Interrupt - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] Int LCD Interrupt Source, should be: - * - LCD_INT_FUF :FIFO underflow - * - LCD_INT_LNBU :LCD next base address update bit - * - LCD_INT_VCOMP :Vertical compare bit - * - LCD_INT_BER :AHB master error interrupt bit - * @return None - **********************************************************************/ -void LCD_SetInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int){ - LCDx->INTMSK |= Int; -} - - -/*********************************************************************//** - * @brief Clear Interrupt - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] Int LCD Interrupt Source, should be: - * - LCD_INT_FUF :FIFO underflow - * - LCD_INT_LNBU :LCD next base address update bit - * - LCD_INT_VCOMP :Vertical compare bit - * - LCD_INT_BER :AHB master error interrupt bit - * @return None - **********************************************************************/ -void LCD_ClrInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int){ - LCDx->INTCLR |= Int; -} - - -/*********************************************************************//** - * @brief Get LCD Interrupt Status - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @return None - **********************************************************************/ -LCD_INT_SRC LCD_GetInterrupt(LPC_LCD_Type *LCDx){ - return (LCD_INT_SRC)LCDx->INTRAW; -} - - -/*********************************************************************//** - * @brief Enable Cursor Interrupt - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @return None - **********************************************************************/ -void LCD_Cursor_SetInterrupt(LPC_LCD_Type *LCDx){ - LCDx->CRSR_INTMSK |= 1; -} - - -/*********************************************************************//** - * @brief Clear Cursor Interrupt - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @return None - **********************************************************************/ -void LCD_Cursor_ClrInterrupt(LPC_LCD_Type *LCDx){ - LCDx->CRSR_INTCLR |= 1; -} - - -/*********************************************************************//** - * @brief Set Cursor Position - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] x horizontal position - * @param[in] y vertical position - * @return None - **********************************************************************/ -void LCD_Cursor_SetPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y){ - LCDx->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16); -} - - -/*********************************************************************//** - * @brief Set Cursor Clipping Position - * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD - * @param[in] x horizontal position, should be in range: 0..63 - * @param[in] y vertical position, should be in range: 0..63 - * @return None - **********************************************************************/ -void LCD_Cursor_SetClip(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y){ - LCDx->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8); -} -#endif /* _LCD */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_libcfg_default.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_libcfg_default.c deleted file mode 100644 index 6955587fa..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_libcfg_default.c +++ /dev/null @@ -1,64 +0,0 @@ -/***********************************************************************//** - * @file lpc18xx_libcfg_default.c - * @brief Library configuration source file (default), - * used to build library without examples. - * @version 2.0 - * @date 21. May. 2010 - * @author NXP MCU SW Application Team - ************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - **************************************************************************/ - -/* Library group ----------------------------------------------------------- */ -/** @addtogroup LIBCFG_DEFAULT - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_libcfg_default.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup LIBCFG_DEFAULT_Public_Functions - * @{ - */ - -#ifndef __BUILD_WITH_EXAMPLE__ - -#ifdef DEBUG -/******************************************************************************* -* @brief Reports the name of the source file and the source line number -* where the CHECK_PARAM error has occurred. -* @param[in] file Pointer to the source file name -* @param[in] line assert_param error line source number -* @return None -*******************************************************************************/ -void check_failed(uint8_t *file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - - /* Infinite loop */ - while(1); -} -#endif /* DEBUG */ - -#endif /* __BUILD_WITH_EXAMPLE__ */ - -/** - * @} - */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_mcpwm.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_mcpwm.c deleted file mode 100644 index f24fae497..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_mcpwm.c +++ /dev/null @@ -1,555 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_mcpwm.c 2011-06-02 -*//** -* @file lpc18xx_mcpwm.c -* @brief Contains all functions support for Motor Control PWM firmware -* library on LPC18XX -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup MCPWM - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_mcpwm.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _MCPWM - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup MCPWM_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Initializes the MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @return None - **********************************************************************/ -void MCPWM_Init(LPC_MCPWM_Type *MCPWMx) -{ - /* Turn On MCPWM PCLK */ - //LPC_CGU->BASE_VPB1_CLK = (SRC_PL160M_0<<24) | (1<<11); - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1); - - MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(0) | MCPWM_CAPCLR_CAP(1) | MCPWM_CAPCLR_CAP(2); - - MCPWMx->INTF_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \ - | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \ - | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2); - - MCPWMx->INTEN_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \ - | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \ - | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2); -} - - -/*********************************************************************//** - * @brief Configures each channel in MCPWM peripheral according to the - * specified parameters in the MCPWM_CHANNEL_CFG_Type. - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] channelNum Channel number, should be: 0..2. - * @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure - * that contains the configuration information for the specified - * MCPWM channel. - * @return None - **********************************************************************/ -void MCPWM_ConfigChannel(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum, - MCPWM_CHANNEL_CFG_Type * channelSetup) -{ - if (channelNum <= 2) - { - if (channelNum == MCPWM_CHANNEL_0) - { - MCPWMx->TC[0] = channelSetup->channelTimercounterValue; - MCPWMx->LIM[0] = channelSetup->channelPeriodValue; - MCPWMx->MAT[0] = channelSetup->channelPulsewidthValue; - } - else if (channelNum == MCPWM_CHANNEL_1) - { - MCPWMx->TC[1] = channelSetup->channelTimercounterValue; - MCPWMx->LIM[1] = channelSetup->channelPeriodValue; - MCPWMx->MAT[1] = channelSetup->channelPulsewidthValue; - } - else if (channelNum == MCPWM_CHANNEL_2) - { - MCPWMx->TC[2] = channelSetup->channelTimercounterValue; - MCPWMx->LIM[2] = channelSetup->channelPeriodValue; - MCPWMx->MAT[2] = channelSetup->channelPulsewidthValue; - } - else - { - return; - } - - if (channelSetup->channelType == MCPWM_CHANNEL_CENTER_MODE) - { - MCPWMx->CON_SET = MCPWM_CON_CENTER(channelNum); - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_CENTER(channelNum); - } - - if (channelSetup->channelPolarity == MCPWM_CHANNEL_PASSIVE_HI) - { - MCPWMx->CON_SET = MCPWM_CON_POLAR(channelNum); - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_POLAR(channelNum); - } - - if (channelSetup->channelDeadtimeEnable == ENABLE) - { - MCPWMx->CON_SET = MCPWM_CON_DTE(channelNum); - - MCPWMx->DT &= ~(MCPWM_DT(channelNum, 0x3FF)); - - MCPWMx->DT |= MCPWM_DT(channelNum, channelSetup->channelDeadtimeValue); - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_DTE(channelNum); - } - - if (channelSetup->channelUpdateEnable == ENABLE) - { - MCPWMx->CON_CLR = MCPWM_CON_DISUP(channelNum); - } - else - { - MCPWMx->CON_SET = MCPWM_CON_DISUP(channelNum); - } - } -} - - -/*********************************************************************//** - * @brief Write to MCPWM shadow registers - Update the value for period - * and pulse width in MCPWM peripheral. - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] channelNum Channel Number, should be: 0..2. - * @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure - * that contains the configuration information for the specified - * MCPWM channel. - * @return None - **********************************************************************/ -void MCPWM_WriteToShadow(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum, - MCPWM_CHANNEL_CFG_Type *channelSetup) -{ - if (channelNum == MCPWM_CHANNEL_0) - { - MCPWMx->LIM[0] = channelSetup->channelPeriodValue; - MCPWMx->MAT[0] = channelSetup->channelPulsewidthValue; - } - else if (channelNum == MCPWM_CHANNEL_1) - { - MCPWMx->LIM[1] = channelSetup->channelPeriodValue; - MCPWMx->MAT[1] = channelSetup->channelPulsewidthValue; - } - else if (channelNum == MCPWM_CHANNEL_2) - { - MCPWMx->LIM[2] = channelSetup->channelPeriodValue; - MCPWMx->MAT[2] = channelSetup->channelPulsewidthValue; - } -} - - - -/*********************************************************************//** - * @brief Configures capture function in MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] channelNum MCI (Motor Control Input pin) number, should be: 0..2 - * @param[in] captureConfig Pointer to a MCPWM_CAPTURE_CFG_Type structure - * that contains the configuration information for the - * specified MCPWM capture. - * @return - **********************************************************************/ -void MCPWM_ConfigCapture(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum, - MCPWM_CAPTURE_CFG_Type *captureConfig) -{ - if ((channelNum <= MCPWM_CHANNEL_2)) - { - - if (captureConfig->captureFalling == ENABLE) - { - MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum); - } - else - { - MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum); - } - - if (captureConfig->captureRising == ENABLE) - { - MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum); - } - else - { - MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum); - } - - if (captureConfig->timerReset == ENABLE) - { - MCPWMx->CAPCON_SET = MCPWM_CAPCON_RT(captureConfig->captureChannel); - } - else - { - MCPWMx->CAPCON_CLR = MCPWM_CAPCON_RT(captureConfig->captureChannel); - } - - if (captureConfig->hnfEnable == ENABLE) - { - MCPWMx->CAPCON_SET = MCPWM_CAPCON_HNFCAP(channelNum); - } - else - { - MCPWMx->CAPCON_CLR = MCPWM_CAPCON_HNFCAP(channelNum); - } - } -} - - -/*********************************************************************//** - * @brief Clears current captured value in specified capture channel - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] captureChannel Capture channel number, should be: 0..2 - * @return None - **********************************************************************/ -void MCPWM_ClearCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel) -{ - MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(captureChannel); -} - -/*********************************************************************//** - * @brief Get current captured value in specified capture channel - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] captureChannel Capture channel number, should be: 0..2 - * @return None - **********************************************************************/ -uint32_t MCPWM_GetCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel) -{ - if (captureChannel == MCPWM_CHANNEL_0) - { - return (MCPWMx->CAP[0]); - } - else if (captureChannel == MCPWM_CHANNEL_1) - { - return (MCPWMx->CAP[1]); - } - else if (captureChannel == MCPWM_CHANNEL_2) - { - return (MCPWMx->CAP[2]); - } - return (0); -} - - -/*********************************************************************//** - * @brief Configures Count control in MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] channelNum Channel number, should be: 0..2 - * @param[in] countMode Count mode, should be: - * - ENABLE: Enables count mode. - * - DISABLE: Disable count mode, the channel is in timer mode. - * @param[in] countConfig Pointer to a MCPWM_COUNT_CFG_Type structure - * that contains the configuration information for the - * specified MCPWM count control. - * @return None - **********************************************************************/ -void MCPWM_CountConfig(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum, - uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig) -{ - if ((channelNum <= 2)) - { - if (countMode == ENABLE) - { - MCPWMx->CNTCON_SET = MCPWM_CNTCON_CNTR(channelNum); - - if (countConfig->countFalling == ENABLE) - { - MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum); - } - else - { - MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum); - } - - if (countConfig->countRising == ENABLE) - { - MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum); - } - else - { - MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum); - } - } - else - { - MCPWMx->CNTCON_CLR = MCPWM_CNTCON_CNTR(channelNum); - } - } -} - - -/*********************************************************************//** - * @brief Start MCPWM activity for each MCPWM channel - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] channel0 State of this command on channel 0: - * - ENABLE: 'Start' command will effect on channel 0 - * - DISABLE: 'Start' command will not effect on channel 0 - * @param[in] channel1 State of this command on channel 1: - * - ENABLE: 'Start' command will effect on channel 1 - * - DISABLE: 'Start' command will not effect on channel 1 - * @param[in] channel2 State of this command on channel 2: - * - ENABLE: 'Start' command will effect on channel 2 - * - DISABLE: 'Start' command will not effect on channel 2 - * @return None - **********************************************************************/ -void MCPWM_Start(LPC_MCPWM_Type *MCPWMx, uint32_t channel0, - uint32_t channel1, uint32_t channel2) -{ - uint32_t regVal = 0; - - regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \ - | (channel2 ? MCPWM_CON_RUN(2) : 0); - - MCPWMx->CON_SET = regVal; -} - - -/*********************************************************************//** - * @brief Stop MCPWM activity for each MCPWM channel - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] channel0 State of this command on channel 0: - * - ENABLE: 'Stop' command will effect on channel 0 - * - DISABLE: 'Stop' command will not effect on channel 0 - * @param[in] channel1 State of this command on channel 1: - * - ENABLE: 'Stop' command will effect on channel 1 - * - DISABLE: 'Stop' command will not effect on channel 1 - * @param[in] channel2 State of this command on channel 2: - * - ENABLE: 'Stop' command will effect on channel 2 - * - DISABLE: 'Stop' command will not effect on channel 2 - * @return None - **********************************************************************/ -void MCPWM_Stop(LPC_MCPWM_Type *MCPWMx, uint32_t channel0, - uint32_t channel1, uint32_t channel2) -{ - uint32_t regVal = 0; - - regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \ - | (channel2 ? MCPWM_CON_RUN(2) : 0); - - MCPWMx->CON_CLR = regVal; -} - - -/*********************************************************************//** - * @brief Enables/Disables 3-phase AC motor mode on MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] acMode State of this command, should be: - * - ENABLE. - * - DISABLE. - * @return None - **********************************************************************/ -void MCPWM_ACMode(LPC_MCPWM_Type *MCPWMx, uint32_t acMode) -{ - if (acMode) - { - MCPWMx->CON_SET = MCPWM_CON_ACMODE; - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_ACMODE; - } -} - - -/*********************************************************************//** - * @brief Enables/Disables 3-phase DC motor mode on MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] dcMode State of this command, should be: - * - ENABLE. - * - DISABLE. - * @param[in] outputInvered Polarity of the MCOB outputs for all 3 channels, - * should be: - * - ENABLE :The MCOB outputs have opposite polarity from the MCOA outputs. - * - DISABLE :The MCOB outputs have the same basic polarity as the MCOA outputs. - * @param[in] outputPattern A value contains bits that enables/disables the specified - * output pins route to the internal MCOA0 signal, should be: - * - MCPWM_PATENT_A0 :MCOA0 tracks internal MCOA0 - * - MCPWM_PATENT_B0 :MCOB0 tracks internal MCOA0 - * - MCPWM_PATENT_A1 :MCOA1 tracks internal MCOA0 - * - MCPWM_PATENT_B1 :MCOB1 tracks internal MCOA0 - * - MCPWM_PATENT_A2 :MCOA2 tracks internal MCOA0 - * - MCPWM_PATENT_B2 :MCOB2 tracks internal MCOA0 - * @return None - * - * Note: all these outputPatent values above can be ORed together for using as input parameter. - **********************************************************************/ -void MCPWM_DCMode(LPC_MCPWM_Type *MCPWMx, uint32_t dcMode, - uint32_t outputInvered, uint32_t outputPattern) -{ - if (dcMode) - { - MCPWMx->CON_SET = MCPWM_CON_DCMODE; - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_DCMODE; - } - - if (outputInvered) - { - MCPWMx->CON_SET = MCPWM_CON_INVBDC; - } - else - { - MCPWMx->CON_CLR = MCPWM_CON_INVBDC; - } - - MCPWMx->CCP = outputPattern; -} - - -/*********************************************************************//** - * @brief Configures the specified interrupt in MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] ulIntType Interrupt type, should be: - * - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0) - * - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0) - * - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0) - * - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1) - * - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1) - * - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1) - * - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2) - * - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2) - * - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2) - * - MCPWM_INTFLAG_ABORT :Fast abort interrupt - * @param[in] NewState New State of this command, should be: - * - ENABLE. - * - DISABLE. - * @return None - * - * Note: all these ulIntType values above can be ORed together for using as input parameter. - **********************************************************************/ -void MCPWM_IntConfig(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType, FunctionalState NewState) -{ - if (NewState) - { - MCPWMx->INTEN_SET = ulIntType; - } - else - { - MCPWMx->INTEN_CLR = ulIntType; - } -} - - -/*********************************************************************//** - * @brief Sets/Forces the specified interrupt for MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] ulIntType Interrupt type, should be: - * - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0) - * - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0) - * - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0) - * - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1) - * - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1) - * - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1) - * - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2) - * - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2) - * - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2) - * - MCPWM_INTFLAG_ABORT :Fast abort interrupt - * @return None - * Note: all these ulIntType values above can be ORed together for using as input parameter. - **********************************************************************/ -void MCPWM_IntSet(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType) -{ - MCPWMx->INTF_SET = ulIntType; -} - - -/*********************************************************************//** - * @brief Clear the specified interrupt pending for MCPWM peripheral - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] ulIntType Interrupt type, should be: - * - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0) - * - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0) - * - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0) - * - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1) - * - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1) - * - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1) - * - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2) - * - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2) - * - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2) - * - MCPWM_INTFLAG_ABORT :Fast abort interrupt - * @return None - * Note: all these ulIntType values above can be ORed together for using as input parameter. - **********************************************************************/ -void MCPWM_IntClear(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType) -{ - MCPWMx->INTF_CLR = ulIntType; -} - - -/*********************************************************************//** - * @brief Check whether if the specified interrupt in MCPWM is set or not - * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM - * @param[in] ulIntType Interrupt type, should be: - * - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0) - * - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0) - * - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0) - * - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1) - * - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1) - * - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1) - * - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2) - * - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2) - * - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2) - * - MCPWM_INTFLAG_ABORT :Fast abort interrupt - * @return None - **********************************************************************/ -FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType) -{ - return ((MCPWMx->INTF & ulIntType) ? SET : RESET); -} - -/** - * @} - */ - -#endif /* _MCPWM */ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_nvic.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_nvic.c deleted file mode 100644 index 6e24ce3a9..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_nvic.c +++ /dev/null @@ -1,74 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_nvic.c 2011-06-02 -*//** -* @file lpc18xx_nvic.c -* @brief Contains all expansion functions support for NVIC firmware -* library on LPC18XX. The main NVIC functions are defined in -* core_cm3.h -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup NVIC - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_nvic.h" - - -/* Private Macros ------------------------------------------------------------- */ -/** @addtogroup NVIC_Private_Macros - * @{ - */ - -/* Vector table offset bit mask */ -#define NVIC_VTOR_MASK 0x3FFFFF80 - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup NVIC_Public_Functions - * @{ - */ - -/*****************************************************************************//** - * @brief Set Vector Table Offset value - * @param offset Offset value - * @return None - *******************************************************************************/ -void NVIC_SetVTOR(uint32_t offset) -{ -// SCB->VTOR = (offset & NVIC_VTOR_MASK); - SCB->VTOR = offset; -} - -/** - * @} - */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_pwr.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_pwr.c deleted file mode 100644 index fd84a58ab..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_pwr.c +++ /dev/null @@ -1,102 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_pwr.c 2011-06-02 -*//** -* @file lpc18xx_pwr.c -* @brief Contains all functions support for Power Control -* firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup PWR - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_types.h" -#include "lpc18xx_scu.h" -#include "lpc18xx_pwr.h" - -/*********************************************************************//** - * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void PWR_Sleep(void) -{ - //LPC_PMC->SLEEP0_MODE = 0x00; - /* Sleep Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void PWR_DeepSleep(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_DEEP_SLEEP; - /* Deep Sleep Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void PWR_PowerDown(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_POWER_DOWN; - /* Power Down Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void PWR_DeepPowerDown(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_DEEP_POWER_DOWN; - /* Deep Power Down Mode*/ - __WFI(); -} - -/** - * @} - */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_qei.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_qei.c deleted file mode 100644 index fd7f67093..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_qei.c +++ /dev/null @@ -1,540 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_qei.c 2011-06-02 -*//** -* @file lpc18xx_pwr.c -* @brief Contains all functions support for QEI firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup QEI - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_qei.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _QEI - -/* Private Types -------------------------------------------------------------- */ -/** @defgroup QEI_Private_Types QEI Private Types - * @{ - */ - -/** - * @brief QEI configuration union type definition - */ -typedef union { - QEI_CFG_Type bmQEIConfig; - uint32_t ulQEIConfig; -} QEI_CFGOPT_Type; - -/** - * @} - */ - -LPC_QEI_Type* QEI_GetPointer(uint8_t qeiId); - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup QEI_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Get the point to typedef of QEI component - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @return None - **********************************************************************/ -LPC_QEI_Type* QEI_GetPointer(uint8_t qeiId) -{ - LPC_QEI_Type* pQei = NULL; - - if(qeiId == 0) - { - pQei = LPC_QEI; - } - - return pQei; -} - - -/*********************************************************************//** - * @brief Resets value for each type of QEI value, such as velocity, - * counter, position, etc.. - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulResetType QEI Reset Type, should be one of the following: - * - QEI_RESET_POS :Reset Position Counter - * - QEI_RESET_POSOnIDX :Reset Position Counter on Index signal - * - QEI_RESET_VEL :Reset Velocity - * - QEI_RESET_IDX :Reset Index Counter - * @return None - **********************************************************************/ -void QEI_Reset(uint8_t qeiId, uint32_t ulResetType) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - pQei->CON = ulResetType; -} - -/*********************************************************************//** - * @brief Initializes the QEI peripheral according to the specified -* parameters in the QEI_ConfigStruct. -* @param[in] qeiId The Id of the expected QEI component, should be: 0 -* @param[in] QEI_ConfigStruct Pointer to a QEI_CFG_Type structure -* that contains the configuration information for the -* specified QEI peripheral - * @return None - **********************************************************************/ -void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - /* Set up clock and power for QEI module */ - // Already enabled by BASE_M3_CLK - - // Reset all remaining value in QEI peripheral - - pQei->MAXPOS = 0x00; - pQei->CMPOS0 = 0x00; - pQei->CMPOS1 = 0x00; - pQei->CMPOS2 = 0x00; - pQei->INXCMP0 = 0x00; - pQei->VELCOMP = 0x00; - - pQei->LOAD = 0x00; - pQei->CON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI; - - pQei->FILTERPHA = 0x00; - pQei->FILTERPHB = 0x00; - pQei->FILTERINX = 0x00; - - // Disable all Interrupt - pQei->IEC = QEI_IECLR_BITMASK; - - // Clear all Interrupt pending - pQei->CLR = QEI_INTCLR_BITMASK; - - // Set QEI configuration value corresponding to its setting up value - pQei->CONF = ((QEI_CFGOPT_Type *)QEI_ConfigStruct)->ulQEIConfig; -} - - -/*********************************************************************//** - * @brief De-Initalize QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @return None - **********************************************************************/ -void QEI_DeInit(uint8_t qeiId) -{ - /* Turn off clock and power for QEI module */ - -} - - -/*****************************************************************************//** -* @brief Fills each QIE_InitStruct member with its default value: -* - DirectionInvert = QEI_DIRINV_NONE -* - SignalMode = QEI_SIGNALMODE_QUAD -* - CaptureMode = QEI_CAPMODE_4X -* - InvertIndex = QEI_INVINX_NONE -* @param[in] QIE_InitStruct Pointer to a QEI_CFG_Type structure which will be -* initialized. -* @return None -*******************************************************************************/ -void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct) -{ - QIE_InitStruct->CaptureMode = QEI_CAPMODE_4X; - QIE_InitStruct->DirectionInvert = QEI_DIRINV_NONE; - QIE_InitStruct->InvertIndex = QEI_INVINX_NONE; - QIE_InitStruct->SignalMode = QEI_SIGNALMODE_QUAD; -} - - -/*********************************************************************//** - * @brief Check whether if specified flag status is set or not - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulFlagType Status Flag Type, should be one of the following: - * - QEI_STATUS_DIR: Direction Status - * @return New Status of this status flag (SET or RESET) - **********************************************************************/ -FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - return ((pQei->STAT & ulFlagType) ? SET : RESET); -} - - -/*********************************************************************//** - * @brief Get current position value in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @return Current position value of QEI peripheral - **********************************************************************/ -uint32_t QEI_GetPosition(uint8_t qeiId) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - return (pQei->POS); -} - -/*********************************************************************//** - * @brief Set max position value for QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulMaxPos Max position value to set - * @return None - **********************************************************************/ -void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - pQei->MAXPOS = ulMaxPos; -} - -/*********************************************************************//** - * @brief Set position compare value for QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] bPosCompCh Compare Position channel, should be: - * - QEI_COMPPOS_CH_0 :QEI compare position channel 0 - * - QEI_COMPPOS_CH_1 :QEI compare position channel 1 - * - QEI_COMPPOS_CH_2 :QEI compare position channel 2 - * @param[in] ulPosComp Compare Position value to set - * @return None - **********************************************************************/ -void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - uint32_t *tmp; - - tmp = (uint32_t *) (&(pQei->CMPOS0) + bPosCompCh * 4); - *tmp = ulPosComp; -} - -/*********************************************************************//** - * @brief Get current index counter of QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @return Current value of QEI index counter - **********************************************************************/ -uint32_t QEI_GetIndex(uint8_t qeiId) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - return (pQei->INXCNT); -} - -/*********************************************************************//** - * @brief Set value for index compare in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulIndexComp Compare Index Value to set - * @return None - **********************************************************************/ -void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - pQei->INXCMP0 = ulIndexComp; -} - -/*********************************************************************//** - * @brief Set timer reload value for QEI peripheral. When the velocity timer is - * over-flow, the value that set for Timer Reload register will be loaded - * into the velocity timer for next period. The calculated velocity in RPM - * therefore will be affect by this value. - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] QEIReloadStruct QEI reload structure - * @return None - **********************************************************************/ -void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - uint64_t pclk; - - if (QEIReloadStruct->ReloadOption == QEI_TIMERRELOAD_TICKVAL) - { - pQei->LOAD = QEIReloadStruct->ReloadValue - 1; - } - else - { -#if 1 - pclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE); - - pclk = (pclk /(1000000/QEIReloadStruct->ReloadValue)) - 1; - - pQei->LOAD = (uint32_t)pclk; -#else - ld = M3Frequency; - - if (ld/1000000 > 0) - { - ld /= 1000000; - ld *= QEIReloadStruct->ReloadValue; - ld -= 1; - } - else - { - ld *= QEIReloadStruct->ReloadValue; - ld /= 1000000; - ld -= 1; - } - - pQei->LOAD = ld; -#endif - } -} - -/*********************************************************************//** - * @brief Get current timer counter in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @return Current timer counter in QEI peripheral - **********************************************************************/ -uint32_t QEI_GetTimer(uint8_t qeiId) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - return (pQei->TIME); -} - -/*********************************************************************//** - * @brief Get current velocity pulse counter in current time period - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @return Current velocity pulse counter value - **********************************************************************/ -uint32_t QEI_GetVelocity(uint8_t qeiId) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - return (pQei->VEL); -} - -/*********************************************************************//** - * @brief Get the most recently measured velocity of the QEI. When - * the Velocity timer in QEI is over-flow, the current velocity - * value will be loaded into Velocity Capture register. - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @return The most recently measured velocity value - **********************************************************************/ -uint32_t QEI_GetVelocityCap(uint8_t qeiId) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - return (pQei->CAP); -} - -/*********************************************************************//** - * @brief Set Velocity Compare value for QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulVelComp Compare Velocity value to set - * @return None - **********************************************************************/ -void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - pQei->VELCOMP = ulVelComp; -} - -/*********************************************************************//** - * @brief Set value of sampling count for the digital filter in - * QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulSamplingPulse Value of sampling count to set - * @return None - **********************************************************************/ -void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - pQei->FILTERPHA = FilterVal.PHA_FilterVal; - pQei->FILTERPHB = FilterVal.PHB_FilterVal; - pQei->FILTERINX = FilterVal.INX_FilterVal; -} - -/*********************************************************************//** - * @brief Check whether if specified interrupt flag status in QEI - * peripheral is set or not - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulIntType Interrupt Flag Status type, should be: - * - QEI_INTFLAG_INX_Int : index pulse was detected interrupt - * - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt - * - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt - * - QEI_INTFLAG_DIR_Int : Change of direction interrupt - * - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt - * - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt - * - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt - * - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt - * - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt - * - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt - * - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt - * - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt - * - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt - * @return New State of specified interrupt flag status (SET or RESET) - **********************************************************************/ -FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - return((pQei->INTSTAT & ulIntType) ? SET : RESET); -} - -/*********************************************************************//** - * @brief Enable/Disable specified interrupt in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulIntType Interrupt Flag Status type, should be: - * - QEI_INTFLAG_INX_Int : index pulse was detected interrupt - * - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt - * - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt - * - QEI_INTFLAG_DIR_Int : Change of direction interrupt - * - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt - * - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt - * - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt - * - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt - * - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt - * - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt - * - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt - * - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt - * - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt - * @param[in] NewState New function state, should be: - * - DISABLE - * - ENABLE - * @return None - **********************************************************************/ -void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - if (NewState == ENABLE) - { - pQei->IES = ulIntType; - } - else - { - pQei->IEC = ulIntType; - } -} - - -/*********************************************************************//** - * @brief Sets (forces) specified interrupt in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulIntType Interrupt Flag Status type, should be: - * - QEI_INTFLAG_INX_Int : index pulse was detected interrupt - * - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt - * - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt - * - QEI_INTFLAG_DIR_Int : Change of direction interrupt - * - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt - * - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt - * - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt - * - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt - * - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt - * - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt - * - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt - * - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt - * - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt - * @return None - **********************************************************************/ -void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - pQei->SET = ulIntType; -} - -/*********************************************************************//** - * @brief Clear (force) specified interrupt (pending) in QEI peripheral - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulIntType Interrupt Flag Status type, should be: - * - QEI_INTFLAG_INX_Int : index pulse was detected interrupt - * - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt - * - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt - * - QEI_INTFLAG_DIR_Int : Change of direction interrupt - * - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt - * - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt - * - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt - * - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt - * - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt - * - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt - * - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt - * - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt - * - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt - * @return None - **********************************************************************/ -void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - pQei->CLR = ulIntType; -} - - -/*********************************************************************//** - * @brief Calculates the actual velocity in RPM passed via velocity - * capture value and Pulse Per Round (of the encoder) value - * parameter input. - * @param[in] qeiId The Id of the expected QEI component, should be: 0 - * @param[in] ulVelCapValue Velocity capture input value that can be - * got from QEI_GetVelocityCap() function - * @param[in] ulPPR Pulse per round of encoder - * @return The actual value of velocity in RPM (Round per minute) - **********************************************************************/ -uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR) -{ - LPC_QEI_Type* pQei = QEI_GetPointer(qeiId); - - uint64_t rpm, clock, Load, edges; - - // Get current Clock rate for timer input - clock = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE); - - // Get Timer load value (velocity capture period) - Load = (uint64_t)(pQei->LOAD + 1); - - // Get Edge - edges = (uint64_t)((pQei->CONF & QEI_CONF_CAPMODE) ? 4 : 2); - - // Calculate RPM - rpm = ((clock * ulVelCapValue * 60) / (Load * ulPPR * edges)); - - return (uint32_t)(rpm); -} - - -/** - * @} - */ - -#endif /* _QEI */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rgu.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rgu.c deleted file mode 100644 index 58470534f..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rgu.c +++ /dev/null @@ -1,253 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_rgu.c 2011-06-02 -*//** -* @file lpc18xx_rgu.c -* @brief Contains all functions support for RGU firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup RGU - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_rgu.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _RGU -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup RGU_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Soft Reset a Signal - * @param[in] ResetSignal indicates which signal will be reset, should be: - * - RGU_SIG_CORE :Core - * - RGU_SIG_PERIPH :Peripheral - * - RGU_SIG_MASTER :Master - * - RGU_SIG_WWDT :WWDT - * - RGU_SIG_CREG :Configuration register block - * - RGU_SIG_BUS :Buses - * - RGU_SIG_SCU :System control unit - * - RGU_SIG_PINMUX :Pin mux - * - RGU_SIG_M3 :Cortex-M3 system - * - RGU_SIG_LCD :LCD controller - * - RGU_SIG_USB0 :USB0 - * - RGU_SIG_USB1 :USB1 - * - RGU_SIG_DMA :DMA - * - RGU_SIG_SDIO :SDIO - * - RGU_SIG_EMC :External memory controller - * - RGU_SIG_ETHERNET :Ethernet - * - RGU_SIG_AES :AES - * - RGU_SIG_GPIO :GPIO - * - RGU_SIG_TIMER0 :Timer 0 - * - RGU_SIG_TIMER1 :Timer 1 - * - RGU_SIG_TIMER2 :Timer 2 - * - RGU_SIG_TIMER3 :Timer 3 - * - RGU_SIG_RITIMER :Repetitive Interrupt Timer - * - RGU_SIG_SCT :State Configurable Timer - * - RGU_SIG_MOTOCONPWM:Motor Control PWM - * - RGU_SIG_QEI :QEI - * - RGU_SIG_ADC0 :ADC0 - * - RGU_SIG_ADC1 :ADC1 - * - RGU_SIG_DAC :DAC - * - RGU_SIG_UART0 :UART0 - * - RGU_SIG_UART1 :UART1 - * - RGU_SIG_UART2 :UART2 - * - RGU_SIG_UART3 :UART3 - * - RGU_SIG_I2C0 :I2C0 - * - RGU_SIG_I2C1 :I2C1 - * - RGU_SIG_SSP0 :SSP0 - * - RGU_SIG_SSP1 :SSP1 - * - RGU_SIG_I2S :I2S - * - RGU_SIG_SPIFI :SPIFI - * - RGU_SIG_CAN :CAN - * @return None - **********************************************************************/ -void RGU_SoftReset(RGU_SIG ResetSignal) -{ - if(ResetSignal < 32){ - LPC_RGU->RESET_CTRL0 = 1 << ResetSignal; - LPC_RGU->RESET_CTRL0 = 0; - }else{ - LPC_RGU->RESET_CTRL1 = 1 << (ResetSignal - 32); - LPC_RGU->RESET_CTRL1 = 0; - } -} - -/*********************************************************************//** - * @brief Get source cause of a signal - * @param[in] ResetSignal reset signal, should be: - * - RGU_SIG_CORE :Core - * - RGU_SIG_PERIPH :Peripheral - * - RGU_SIG_MASTER :Master - * - RGU_SIG_WWDT :WWDT - * - RGU_SIG_CREG :Configuration register block - * - RGU_SIG_BUS :Buses - * - RGU_SIG_SCU :System control unit - * - RGU_SIG_PINMUX :Pin mux - * - RGU_SIG_M3 :Cortex-M3 system - * - RGU_SIG_LCD :LCD controller - * - RGU_SIG_USB0 :USB0 - * - RGU_SIG_USB1 :USB1 - * - RGU_SIG_DMA :DMA - * - RGU_SIG_SDIO :SDIO - * - RGU_SIG_EMC :External memory controller - * - RGU_SIG_ETHERNET :Ethernet - * - RGU_SIG_AES :AES - * - RGU_SIG_GPIO :GPIO - * - RGU_SIG_TIMER0 :Timer 0 - * - RGU_SIG_TIMER1 :Timer 1 - * - RGU_SIG_TIMER2 :Timer 2 - * - RGU_SIG_TIMER3 :Timer 3 - * - RGU_SIG_RITIMER :Repetitive Interrupt Timer - * - RGU_SIG_SCT :State Configurable Timer - * - RGU_SIG_MOTOCONPWM:Motor Control PWM - * - RGU_SIG_QEI :QEI - * - RGU_SIG_ADC0 :ADC0 - * - RGU_SIG_ADC1 :ADC1 - * - RGU_SIG_DAC :DAC - * - RGU_SIG_UART0 :UART0 - * - RGU_SIG_UART1 :UART1 - * - RGU_SIG_UART2 :UART2 - * - RGU_SIG_UART3 :UART3 - * - RGU_SIG_I2C0 :I2C0 - * - RGU_SIG_I2C1 :I2C1 - * - RGU_SIG_SSP0 :SSP0 - * - RGU_SIG_SSP1 :SSP1 - * - RGU_SIG_I2S :I2S - * - RGU_SIG_SPIFI :SPIFI - * - RGU_SIG_CAN :CAN - * @return Source cause of reset, could be: - * - RGU_SRC_NONE :No source - * - RGU_SRC_SOFT :Software reset source - * - RGU_SRC_EXT :External reset source - * - RGU_SRC_CORE :Core reset source - * - RGU_SRC_PERIPH :Peripheral reset source - * - RGU_SRC_MASTER :Master reset source - * - RGU_SRC_BOD :BOD reset source - * - RGU_SRC_WWDT :WWDT reset source - **********************************************************************/ -RGU_SRC RGU_GetSource(RGU_SIG ResetSignal) -{ - uint32_t i, temp, registercache; - if(ResetSignal < 16) - temp = 3 & (LPC_RGU->RESET_STATUS0 >> ResetSignal); - else if(ResetSignal < 32) - temp = 3 & (LPC_RGU->RESET_STATUS1 >> (ResetSignal - 16)); - else if(ResetSignal < 48) - temp = 3 & (LPC_RGU->RESET_STATUS2 >> (ResetSignal - 32)); - else - temp = 3 & (LPC_RGU->RESET_STATUS3 >> (ResetSignal - 48)); - - if(temp == 0) return RGU_SRC_NONE; - else if(temp == 3) return RGU_SRC_SOFT; - else if(temp == 1){ - registercache = (((uint32_t*)&LPC_RGU->RESET_EXT_STAT0)[ResetSignal]); - for(i = 0; i < 6; i++){ - if(registercache & (1<RESET_ACTIVE_STATUS0 | (1 << ResetSignal)); - else - return (Bool)!(LPC_RGU->RESET_ACTIVE_STATUS1 | (1 << (ResetSignal - 32))); -} - - -/** - * @} - */ - -#endif /* _RGU */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rit.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rit.c deleted file mode 100644 index f203f9592..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rit.c +++ /dev/null @@ -1,196 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_rit.c 2011-06-02 -*//** -* @file lpc18xx_rit.c -* @brief Contains all functions support for RIT firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup RIT - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_rit.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _RIT - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup RIT_Public_Functions - * @{ - */ - -/******************************************************************************//* - * @brief Initial for RIT - * - Turn on power and clock - * - Setup default register values - * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT - * @return None - *******************************************************************************/ -void RIT_Init(LPC_RITIMER_Type *RITx) -{ - CHECK_PARAM(PARAM_RITx(RITx)); - //CGU_ConfigPPWR (CGU_PCONP_PCRIT, ENABLE); - //Set up default register values - RITx->COMPVAL = 0xFFFFFFFF; - RITx->MASK = 0x00000000; - RITx->CTRL = 0x0C; - RITx->COUNTER = 0x00000000; - // Turn on power and clock - -} -/******************************************************************************//* - * @brief DeInitial for RIT - * - Turn off power and clock - * - ReSetup default register values - * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT - * @return None - *******************************************************************************/ -void RIT_DeInit(LPC_RITIMER_Type *RITx) -{ - CHECK_PARAM(PARAM_RITx(RITx)); - - // Turn off power and clock - //CGU_ConfigPPWR (CGU_PCONP_PCRIT, DISABLE); - //ReSetup default register values - RITx->COMPVAL = 0xFFFFFFFF; - RITx->MASK = 0x00000000; - RITx->CTRL = 0x0C; - RITx->COUNTER = 0x00000000; -} - -/******************************************************************************//* - * @brief Set compare value, mask value and time counter value - * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT - * @param[in] time_interval timer interval value (ms) - * @return None - *******************************************************************************/ - -void RIT_TimerConfig(LPC_RITIMER_Type *RITx, uint32_t time_interval) -{ - uint32_t clock_rate, cmp_value; - CHECK_PARAM(PARAM_RITx(RITx)); - - // Get PCLK value of RIT - clock_rate = /*CGU_GetPCLK(CGU_PCLKSEL_RIT)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE); - - /* calculate compare value for RIT to generate interrupt at - * specified time interval - * COMPVAL = (RIT_PCLK * time_interval)/1000 - * (with time_interval unit is millisecond) - */ - cmp_value = (clock_rate /1000) * time_interval; - RITx->COMPVAL = cmp_value; - - /* Set timer enable clear bit to clear timer to 0 whenever - * counter value equals the contents of RICOMPVAL - */ - RITx->CTRL |= (1<<1); -} - - -/******************************************************************************//* - * @brief Enable/Disable Timer - * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT - * @param[in] NewState New State of this function - * -ENABLE :Enable Timer - * -DISABLE :Disable Timer - * @return None - *******************************************************************************/ -void RIT_Cmd(LPC_RITIMER_Type *RITx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_RITx(RITx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - //Enable or Disable Timer - if(NewState==ENABLE) - { - RITx->CTRL |= RIT_CTRL_TEN; - } - else - { - RITx->CTRL &= ~RIT_CTRL_TEN; - } -} - -/******************************************************************************//* - * @brief Timer Enable/Disable on debug - * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT - * @param[in] NewState New State of this function - * -ENABLE :The timer is halted whenever a hardware break condition occurs - * -DISABLE :Hardware break has no effect on the timer operation - * @return None - *******************************************************************************/ -void RIT_TimerDebugCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_RITx(RITx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - //Timer Enable/Disable on break - if(NewState==ENABLE) - { - RITx->CTRL |= RIT_CTRL_ENBR; - } - else - { - RITx->CTRL &= ~RIT_CTRL_ENBR; - } -} -/******************************************************************************//* - * @brief Check whether interrupt flag is set or not - * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT - * @return Current interrupt status, could be - * - SET - * - RESET - *******************************************************************************/ -IntStatus RIT_GetIntStatus(LPC_RITIMER_Type *RITx) -{ - uint8_t result; - CHECK_PARAM(PARAM_RITx(RITx)); - if((RITx->CTRL&RIT_CTRL_INTEN)==1) result= SET; - else return RESET; - //clear interrupt flag - RITx->CTRL |= RIT_CTRL_INTEN; - return (IntStatus)result; -} - -/** - * @} - */ - -#endif /* _RIT */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rtc.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rtc.c deleted file mode 100644 index aabd6007f..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rtc.c +++ /dev/null @@ -1,760 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_rtc.c 2011-06-02 -*//** -* @file lpc18xx_rtc.c -* @brief Contains all functions support for RTC firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup RTC - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_rtc.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _RTC - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup RTC_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initializes the RTC peripheral. - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @return None - *********************************************************************/ -void RTC_Init (LPC_RTC_Type *RTCx) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - - // Configure clock to RTC - LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Reset 32Khz oscillator - LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k and release reset - LPC_SCU->SFSCLK_0 = 1 | (0x3<<2); // function 1; CGU clk out, pull down - LPC_CGU->BASE_OUT_CLK = (CGU_CLKSRC_32KHZ_OSC<<24) |(1<<11); // base clock out use 32KHz crystal and auto block - do - { - /* Reset RTC clock*/ - RTCx->CCR = RTC_CCR_CTCRST | RTC_CCR_CCALEN; - } - while(RTCx->CCR!=(RTC_CCR_CTCRST | RTC_CCR_CCALEN)); - do - { - /* Finish resetting RTC clock*/ - RTCx->CCR = RTC_CCR_CCALEN; - } - while(RTCx->CCR != RTC_CCR_CCALEN); - /* Clear counter increment and alarm interrupt */ - RTCx->ILR = RTC_IRL_RTCCIF | RTC_IRL_RTCALF; - while(RTCx->ILR!=0); - // Clear all register to be default - RTCx->CIIR = 0x00; - RTCx->AMR = 0xFF; - RTCx->CALIBRATION = 0x00; -} - - -/*********************************************************************//** - * @brief De-initializes the RTC peripheral registers to their -* default reset values. - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @return None - **********************************************************************/ -void RTC_DeInit(LPC_RTC_Type *RTCx) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - - RTCx->CCR = 0x00; -} - -/*********************************************************************//** - * @brief Reset clock tick counter in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @return None - **********************************************************************/ -void RTC_ResetClockTickCounter(LPC_RTC_Type *RTCx) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - - RTCx->CCR |= RTC_CCR_CTCRST; - RTCx->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK; -} - -/*********************************************************************//** - * @brief Start/Stop RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] NewState New State of this function, should be: - * - ENABLE :The time counters are enabled - * - DISABLE :The time counters are disabled - * @return None - **********************************************************************/ -void RTC_Cmd (LPC_RTC_Type *RTCx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - do - { - RTCx->CCR |= RTC_CCR_CLKEN; - } - while((RTCx->CCR&RTC_CCR_CLKEN)==0); - } - else - { - RTCx->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Enable/Disable Counter increment interrupt for each time type - * in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] CntIncrIntType: Counter Increment Interrupt type, - * an increment of this type value below will generates - * an interrupt, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @param[in] NewState New State of this function, should be: - * - ENABLE: Counter Increment interrupt for this time type are enabled - * - DISABLE: Counter Increment interrupt for this time type are disabled - * @return None - **********************************************************************/ -void RTC_CntIncrIntConfig (LPC_RTC_Type *RTCx, uint32_t CntIncrIntType, \ - FunctionalState NewState) -{ - uint32_t tem; - - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - CHECK_PARAM(PARAM_RTC_TIMETYPE(CntIncrIntType)); - - switch (CntIncrIntType) - { - case RTC_TIMETYPE_SECOND: - tem = RTC_CIIR_IMSEC; - break; - case RTC_TIMETYPE_MINUTE: - tem = RTC_CIIR_IMMIN; - break; - case RTC_TIMETYPE_HOUR: - tem = RTC_CIIR_IMHOUR; - break; - case RTC_TIMETYPE_DAYOFWEEK: - tem = RTC_CIIR_IMDOW; - break; - case RTC_TIMETYPE_DAYOFMONTH: - tem = RTC_CIIR_IMDOM; - break; - case RTC_TIMETYPE_DAYOFYEAR: - tem = RTC_CIIR_IMDOY; - break; - case RTC_TIMETYPE_MONTH: - tem = RTC_CIIR_IMMON; - break; - case RTC_TIMETYPE_YEAR: - tem = RTC_CIIR_IMYEAR; - break; - } - if (NewState == ENABLE) - { - //do - { - RTCx->CIIR |= tem; - } - //while((RTCx->CIIR & tem)== 0); - } - else - { - //do - { - RTCx->CIIR &= (~tem) & RTC_CIIR_BITMASK; - } - //while(RTCx->CIIR & tem); - } -} - - -/*********************************************************************//** - * @brief Enable/Disable Alarm interrupt for each time type - * in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] AlarmTimeType: Alarm Time Interrupt type, - * an matching of this type value below with current time - * in RTC will generates an interrupt, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @param[in] NewState New State of this function, should be: - * - ENABLE: Alarm interrupt for this time type are enabled - * - DISABLE: Alarm interrupt for this time type are disabled - * @return None - **********************************************************************/ -void RTC_AlarmIntConfig (LPC_RTC_Type *RTCx, uint32_t AlarmTimeType, \ - FunctionalState NewState) -{ - uint32_t tem; - - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - CHECK_PARAM(PARAM_RTC_TIMETYPE(AlarmTimeType)); - - switch (AlarmTimeType) - { - case RTC_TIMETYPE_SECOND: - tem = (RTC_AMR_AMRSEC); - break; - case RTC_TIMETYPE_MINUTE: - tem = (RTC_AMR_AMRMIN); - break; - case RTC_TIMETYPE_HOUR: - tem = (RTC_AMR_AMRHOUR); - break; - case RTC_TIMETYPE_DAYOFWEEK: - tem = (RTC_AMR_AMRDOW); - break; - case RTC_TIMETYPE_DAYOFMONTH: - tem = (RTC_AMR_AMRDOM); - break; - case RTC_TIMETYPE_DAYOFYEAR: - tem = (RTC_AMR_AMRDOY); - break; - case RTC_TIMETYPE_MONTH: - tem = (RTC_AMR_AMRMON); - break; - case RTC_TIMETYPE_YEAR: - tem = (RTC_AMR_AMRYEAR); - break; - } - if (NewState == ENABLE) - { - //do - { - RTCx->AMR &= (~tem) & RTC_AMR_BITMASK; - } - //while(RTCx->AMR & tem); - } - else - { - //do - { - RTCx->AMR |= (tem); - } - //while((RTCx->AMR & tem)== 0); - } -} - - -/*********************************************************************//** - * @brief Set current time value for each time type in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Timetype Time Type, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @param[in] TimeValue Time value to set - * @return None - **********************************************************************/ -void RTC_SetTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t TimeValue) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_RTC_TIMETYPE(Timetype)); - - switch ( Timetype) - { - case RTC_TIMETYPE_SECOND: - CHECK_PARAM(TimeValue <= RTC_SECOND_MAX); - - RTCx->SEC = TimeValue & RTC_SEC_MASK; - break; - - case RTC_TIMETYPE_MINUTE: - CHECK_PARAM(TimeValue <= RTC_MINUTE_MAX); - - RTCx->MIN = TimeValue & RTC_MIN_MASK; - break; - - case RTC_TIMETYPE_HOUR: - CHECK_PARAM(TimeValue <= RTC_HOUR_MAX); - - RTCx->HRS = TimeValue & RTC_HOUR_MASK; - break; - - case RTC_TIMETYPE_DAYOFWEEK: - CHECK_PARAM(TimeValue <= RTC_DAYOFWEEK_MAX); - - RTCx->DOW = TimeValue & RTC_DOW_MASK; - break; - - case RTC_TIMETYPE_DAYOFMONTH: - CHECK_PARAM((TimeValue <= RTC_DAYOFMONTH_MAX) \ - && (TimeValue >= RTC_DAYOFMONTH_MIN)); - - RTCx->DOM = TimeValue & RTC_DOM_MASK; - break; - - case RTC_TIMETYPE_DAYOFYEAR: - CHECK_PARAM((TimeValue >= RTC_DAYOFYEAR_MIN) \ - && (TimeValue <= RTC_DAYOFYEAR_MAX)); - - RTCx->DOY = TimeValue & RTC_DOY_MASK; - break; - - case RTC_TIMETYPE_MONTH: - CHECK_PARAM((TimeValue >= RTC_MONTH_MIN) \ - && (TimeValue <= RTC_MONTH_MAX)); - - RTCx->MONTH = TimeValue & RTC_MONTH_MASK; - break; - - case RTC_TIMETYPE_YEAR: - CHECK_PARAM(TimeValue <= RTC_YEAR_MAX); - - RTCx->YEAR = TimeValue & RTC_YEAR_MASK; - break; - } -} - -/*********************************************************************//** - * @brief Get current time value for each type time type - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Timetype Time Type, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @return Value of time according to specified time type - **********************************************************************/ -uint32_t RTC_GetTime(LPC_RTC_Type *RTCx, uint32_t Timetype) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_RTC_TIMETYPE(Timetype)); - - switch (Timetype) - { - case RTC_TIMETYPE_SECOND: - return (RTCx->SEC & RTC_SEC_MASK); - case RTC_TIMETYPE_MINUTE: - return (RTCx->MIN & RTC_MIN_MASK); - case RTC_TIMETYPE_HOUR: - return (RTCx->HRS & RTC_HOUR_MASK); - case RTC_TIMETYPE_DAYOFWEEK: - return (RTCx->DOW & RTC_DOW_MASK); - case RTC_TIMETYPE_DAYOFMONTH: - return (RTCx->DOM & RTC_DOM_MASK); - case RTC_TIMETYPE_DAYOFYEAR: - return (RTCx->DOY & RTC_DOY_MASK); - case RTC_TIMETYPE_MONTH: - return (RTCx->MONTH & RTC_MONTH_MASK); - case RTC_TIMETYPE_YEAR: - return (RTCx->YEAR & RTC_YEAR_MASK); - default: - return (0); - } -} - - -/*********************************************************************//** - * @brief Set full of time in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that - * contains time value in full. - * @return None - **********************************************************************/ -void RTC_SetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - - RTCx->DOM = pFullTime->DOM & RTC_DOM_MASK; - RTCx->DOW = pFullTime->DOW & RTC_DOW_MASK; - RTCx->DOY = pFullTime->DOY & RTC_DOY_MASK; - RTCx->HRS = pFullTime->HOUR & RTC_HOUR_MASK; - RTCx->MIN = pFullTime->MIN & RTC_MIN_MASK; - RTCx->SEC = pFullTime->SEC & RTC_SEC_MASK; - RTCx->MONTH = pFullTime->MONTH & RTC_MONTH_MASK; - RTCx->YEAR = pFullTime->YEAR & RTC_YEAR_MASK; -} - - -/*********************************************************************//** - * @brief Get full of time in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that - * will be stored time in full. - * @return None - **********************************************************************/ -void RTC_GetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - - pFullTime->DOM = RTCx->DOM & RTC_DOM_MASK; - pFullTime->DOW = RTCx->DOW & RTC_DOW_MASK; - pFullTime->DOY = RTCx->DOY & RTC_DOY_MASK; - pFullTime->HOUR = RTCx->HRS & RTC_HOUR_MASK; - pFullTime->MIN = RTCx->MIN & RTC_MIN_MASK; - pFullTime->SEC = RTCx->SEC & RTC_SEC_MASK; - pFullTime->MONTH = RTCx->MONTH & RTC_MONTH_MASK; - pFullTime->YEAR = RTCx->YEAR & RTC_YEAR_MASK; -} - - -/*********************************************************************//** - * @brief Set alarm time value for each time type - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Timetype Time Type, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @param[in] ALValue Alarm time value to set - * @return None - **********************************************************************/ -void RTC_SetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t ALValue) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - - switch (Timetype) - { - case RTC_TIMETYPE_SECOND: - CHECK_PARAM(ALValue <= RTC_SECOND_MAX); - - RTCx->ASEC = ALValue & RTC_SEC_MASK; - break; - - case RTC_TIMETYPE_MINUTE: - CHECK_PARAM(ALValue <= RTC_MINUTE_MAX); - - RTCx->AMIN = ALValue & RTC_MIN_MASK; - break; - - case RTC_TIMETYPE_HOUR: - CHECK_PARAM(ALValue <= RTC_HOUR_MAX); - - RTCx->AHRS = ALValue & RTC_HOUR_MASK; - break; - - case RTC_TIMETYPE_DAYOFWEEK: - CHECK_PARAM(ALValue <= RTC_DAYOFWEEK_MAX); - - RTCx->ADOW = ALValue & RTC_DOW_MASK; - break; - - case RTC_TIMETYPE_DAYOFMONTH: - CHECK_PARAM((ALValue <= RTC_DAYOFMONTH_MAX) \ - && (ALValue >= RTC_DAYOFMONTH_MIN)); - - RTCx->ADOM = ALValue & RTC_DOM_MASK; - break; - - case RTC_TIMETYPE_DAYOFYEAR: - CHECK_PARAM((ALValue >= RTC_DAYOFYEAR_MIN) \ - && (ALValue <= RTC_DAYOFYEAR_MAX)); - - RTCx->ADOY = ALValue & RTC_DOY_MASK; - break; - - case RTC_TIMETYPE_MONTH: - CHECK_PARAM((ALValue >= RTC_MONTH_MIN) \ - && (ALValue <= RTC_MONTH_MAX)); - - RTCx->AMON = ALValue & RTC_MONTH_MASK; - break; - - case RTC_TIMETYPE_YEAR: - CHECK_PARAM(ALValue <= RTC_YEAR_MAX); - - RTCx->AYRS = ALValue & RTC_YEAR_MASK; - break; - } -} - - - -/*********************************************************************//** - * @brief Get alarm time value for each time type - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Timetype Time Type, should be: - * - RTC_TIMETYPE_SECOND - * - RTC_TIMETYPE_MINUTE - * - RTC_TIMETYPE_HOUR - * - RTC_TIMETYPE_DAYOFWEEK - * - RTC_TIMETYPE_DAYOFMONTH - * - RTC_TIMETYPE_DAYOFYEAR - * - RTC_TIMETYPE_MONTH - * - RTC_TIMETYPE_YEAR - * @return Value of Alarm time according to specified time type - **********************************************************************/ -uint32_t RTC_GetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype) -{ - switch (Timetype) - { - case RTC_TIMETYPE_SECOND: - return (RTCx->ASEC & RTC_SEC_MASK); - case RTC_TIMETYPE_MINUTE: - return (RTCx->AMIN & RTC_MIN_MASK); - case RTC_TIMETYPE_HOUR: - return (RTCx->AHRS & RTC_HOUR_MASK); - case RTC_TIMETYPE_DAYOFWEEK: - return (RTCx->ADOW & RTC_DOW_MASK); - case RTC_TIMETYPE_DAYOFMONTH: - return (RTCx->ADOM & RTC_DOM_MASK); - case RTC_TIMETYPE_DAYOFYEAR: - return (RTCx->ADOY & RTC_DOY_MASK); - case RTC_TIMETYPE_MONTH: - return (RTCx->AMON & RTC_MONTH_MASK); - case RTC_TIMETYPE_YEAR: - return (RTCx->AYRS & RTC_YEAR_MASK); - default: - return (0); - } -} - - -/*********************************************************************//** - * @brief Set full of alarm time in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that - * contains alarm time value in full. - * @return None - **********************************************************************/ -void RTC_SetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - - RTCx->ADOM = pFullTime->DOM & RTC_DOM_MASK; - RTCx->ADOW = pFullTime->DOW & RTC_DOW_MASK; - RTCx->ADOY = pFullTime->DOY & RTC_DOY_MASK; - RTCx->AHRS = pFullTime->HOUR & RTC_HOUR_MASK; - RTCx->AMIN = pFullTime->MIN & RTC_MIN_MASK; - RTCx->ASEC = pFullTime->SEC & RTC_SEC_MASK; - RTCx->AMON = pFullTime->MONTH & RTC_MONTH_MASK; - RTCx->AYRS = pFullTime->YEAR & RTC_YEAR_MASK; -} - - -/*********************************************************************//** - * @brief Get full of alarm time in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that - * will be stored alarm time in full. - * @return None - **********************************************************************/ -void RTC_GetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - - pFullTime->DOM = RTCx->ADOM & RTC_DOM_MASK; - pFullTime->DOW = RTCx->ADOW & RTC_DOW_MASK; - pFullTime->DOY = RTCx->ADOY & RTC_DOY_MASK; - pFullTime->HOUR = RTCx->AHRS & RTC_HOUR_MASK; - pFullTime->MIN = RTCx->AMIN & RTC_MIN_MASK; - pFullTime->SEC = RTCx->ASEC & RTC_SEC_MASK; - pFullTime->MONTH = RTCx->AMON & RTC_MONTH_MASK; - pFullTime->YEAR = RTCx->AYRS & RTC_YEAR_MASK; -} - - -/*********************************************************************//** - * @brief Check whether if specified Location interrupt in - * RTC peripheral is set or not - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] IntType Interrupt location type, should be: - * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt. - * - RTC_INT_ALARM: Alarm generated an interrupt. - * @return New state of specified Location interrupt in RTC peripheral - * - SET - * - RESET - **********************************************************************/ -IntStatus RTC_GetIntPending (LPC_RTC_Type *RTCx, uint32_t IntType) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_RTC_INT(IntType)); - - return ((RTCx->ILR & IntType) ? SET : RESET); -} - - -/*********************************************************************//** - * @brief Clear specified Location interrupt pending in - * RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] IntType Interrupt location type, should be: - * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending. - * - RTC_INT_ALARM :Clear alarm interrupt pending - * @return None - **********************************************************************/ -void RTC_ClearIntPending (LPC_RTC_Type *RTCx, uint32_t IntType) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_RTC_INT(IntType)); - - RTCx->ILR = IntType; -} - -/*********************************************************************//** - * @brief Enable/Disable calibration counter in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] NewState New State of this function, should be: - * - ENABLE :The calibration counter is enabled and counting - * - DISABLE :The calibration counter is disabled and reset to zero - * @return None - **********************************************************************/ -void RTC_CalibCounterCmd(LPC_RTC_Type *RTCx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - do - { - RTCx->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK; - }while(RTCx->CCR&RTC_CCR_CCALEN); - } - else - { - RTCx->CCR |= RTC_CCR_CCALEN; - } -} - - -/*********************************************************************//** - * @brief Configures Calibration in RTC peripheral - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] CalibValue Calibration value, should be in range from - * 0 to 131,072 - * @param[in] CalibDir Calibration Direction, should be: - * - RTC_CALIB_DIR_FORWARD :Forward calibration - * - RTC_CALIB_DIR_BACKWARD :Backward calibration - * @return None - **********************************************************************/ -void RTC_CalibConfig(LPC_RTC_Type *RTCx, uint32_t CalibValue, uint8_t CalibDir) -{ - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_RTC_CALIB_DIR(CalibDir)); - CHECK_PARAM(CalibValue < RTC_CALIBRATION_MAX); - - RTCx->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK) \ - | ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0); -} - - -/*********************************************************************//** - * @brief Write value to General purpose registers - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Channel General purpose registers Channel number, - * should be in range from 0 to 63. - * @param[in] Value Value to write - * @return None - * Note: These General purpose registers can be used to store important - * information when the main power supply is off. The value in these - * registers is not affected by chip reset. - **********************************************************************/ -void RTC_WriteGPREG (LPC_RTC_Type *RTCx, uint8_t Channel, uint32_t Value) -{ - uint32_t *preg; - - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_RTC_GPREG_CH(Channel)); - - preg = (uint32_t *)RTC_GPREG_BASE; - preg += Channel; - *preg = Value; -} - - -/*********************************************************************//** - * @brief Read value from General purpose registers - * @param[in] RTCx RTC peripheral selected, should be LPC_RTC - * @param[in] Channel General purpose registers Channel number, - * should be in range from 0 to 4. - * @return Read Value - * Note: These General purpose registers can be used to store important - * information when the main power supply is off. The value in these - * registers is not affected by chip reset. - **********************************************************************/ -uint32_t RTC_ReadGPREG (LPC_RTC_Type *RTCx, uint8_t Channel) -{ - uint32_t *preg; - uint32_t value; - - CHECK_PARAM(PARAM_RTCx(RTCx)); - CHECK_PARAM(PARAM_RTC_GPREG_CH(Channel)); - - preg = (uint32_t *)RTC_GPREG_BASE; - preg += Channel; - value = *preg; - return (value); -} - -/** - * @} - */ - -#endif /* _RTC */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_sct.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_sct.c deleted file mode 100644 index be01f67a5..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_sct.c +++ /dev/null @@ -1,140 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_sct.c 2011-06-02 -*//** -* @file lpc18xx_sct.c -* @brief Contains all functions support for SCT firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup SCT - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_sct.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _SCT - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup SCT_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Select 16/32 bit SCT counter - * @param[in] value configuration value for SCT - * - SCT_CONFIG_16BIT_COUNTER :16-bit counter - * - SCT_CONFIG_32BIT_COUNTER :32-bit counter - * @return None - **********************************************************************/ -void SCT_Config(uint32_t value) -{ - CHECK_PARAM(PARAM_SCT_CONFIG_COUNTER_TYPE(value)); - - LPC_SCT->CONFIG = value; -} - -/*********************************************************************//** -* @brief Setting SCT control -* @param[in] value setting value -* @param[in] ena Enable/disable status -* - ENABLE -* - DISABLE -* @return None -**********************************************************************/ -void SCT_ControlSet(uint32_t value, FunctionalState ena) -{ - uint32_t tem; - - CHECK_PARAM(PARAM_FUNCTIONALSTATE(ena)); - - tem = LPC_SCT->CTRL_U; - - if(ena == ENABLE) - { - tem |= value; - } - else - { - tem &= (~value); - } - - LPC_SCT->CTRL_U = tem; - -} - -/*********************************************************************//** -* @brief Set start mode for ADC -* @param[in] outnum number of SCT output, should be: 0..15 -* @param[in] value solution value, should be -* - SCT_RES_NOCHANGE :No change -* - SCT_RES_SET_OUTPUT :Set output -* - SCT_RES_CLEAR_OUTPUT :Clear output -* - SCT_RES_TOGGLE_OUTPUT :Toggle output -* @return None -*********************************************************************/ -void SCT_ConflictResolutionSet(uint8_t outnum, uint8_t value) -{ - uint32_t tem; - - CHECK_PARAM(PARAM_SCT_OUTPUT_NUM(outnum)); - CHECK_PARAM(PARAM_SCT_RES(value)); - - tem = LPC_SCT->RES; - tem &= ~(0x03 << (2*outnum)); - tem |= (value << (2*outnum)); - LPC_SCT->RES = tem; -} - -/*********************************************************************//** -* @brief Clear SCT event generating interrupt request -* @param[in] even_num SCT event number, should be: 0..15 -* @return None -*********************************************************************/ -void SCT_EventFlagClear(uint8_t even_num) -{ - CHECK_PARAM(PARAM_SCT_EVENT(even_num)); - - LPC_SCT->EVFLAG = (1 << (even_num)); -} -/** - * @} - */ - -#endif /* _SCT */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_scu.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_scu.c deleted file mode 100644 index a6da21db7..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_scu.c +++ /dev/null @@ -1,62 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_scu.c 2011-06-02 -*//** -* @file lpc18xx_scu.c -* @brief Contains all functions support for SCU firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup SCU - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" /* LPC18xx definitions */ -#include "lpc_types.h" -#include "lpc18xx_scu.h" - - -/*********************************************************************//** - * @brief Configure pin function - * @param[in] port Port number, should be: 0..15 - * @param[in] pin Pin number, should be: 0..31 - * @param[in] mode Pin mode, should be: - * - MD_PUP :Pull-up enabled - * - MD_BUK :Plain input - * - MD_PLN :Repeater mode - * - MD_PDN :Pull-down enabled - * @param[in] func Function mode, should be: - * - FUNC0 :Function 0 - * - FUNC1 :Function 1 - * - FUNC2 :Function 2 - * - FUNC3 :Function 3 - * @return None - **********************************************************************/ -void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func) -{ - uint32_t * scu_base=(uint32_t*)(LPC_SCU_BASE); - scu_base[(PORT_OFFSET*port+PIN_OFFSET*pin)/4]=mode+func; -} /* scu_pinmux */ - -/** - * @} - */ -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_ssp.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_ssp.c deleted file mode 100644 index 2c278fc82..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_ssp.c +++ /dev/null @@ -1,644 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_ssp.c 2011-06-02 -*//** -* @file lpc18xx_ssp.c -* @brief Contains all functions support for SSP firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup SSP - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_ssp.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _SSP - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup SSP_Private_Functions - * @{ - */ - -/** - * @} - */ - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup SSP_Public_Functions - * @{ - */ - -/********************************************************************//** - * @brief Initializes the SSPx peripheral according to the specified - * parameters in the SSP_ConfigStruct. - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] SSP_ConfigStruct Pointer to a SSP_CFG_Type structure that - * contains the configuration information for the specified - * SSP peripheral. - * @return None - *********************************************************************/ -void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct) -{ - uint32_t tmp; - uint32_t prescale, cr0_div, cmp_clk, ssp_clk; - - CHECK_PARAM(PARAM_SSPx(SSPx)); - - if(SSPx == LPC_SSP0) { - /* Set up clock and power for SSP0 module */ - //LPC_CGU->BASE_SSP0_CLK = (SRC_PL160M_0<<24) | (1<<11); - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_SSP0); - } else if(SSPx == LPC_SSP1) { - /* Set up clock and power for SSP1 module */ - //LPC_CGU->BASE_SSP1_CLK = (SRC_PL160M_0<<24) | (1<<11); - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_SSP1); - } else { - return; - } - - /* Configure SSP, interrupt is disable, LoopBack mode is disable, - * SSP is disable, Slave output is disable as default - */ - tmp = ((SSP_ConfigStruct->CPHA) | (SSP_ConfigStruct->CPOL) \ - | (SSP_ConfigStruct->FrameFormat) | (SSP_ConfigStruct->Databit)) - & SSP_CR0_BITMASK; - // write back to SSP control register - SSPx->CR0 = tmp; - - tmp = SSP_ConfigStruct->Mode & SSP_CR1_BITMASK; - // Write back to CR1 - SSPx->CR1 = tmp; - - // Set clock rate for SSP peripheral - if(SSPx == LPC_SSP0) - ssp_clk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_SSP0); - else - ssp_clk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_SSP1); - cr0_div = 0; - cmp_clk = 0xFFFFFFFF; - prescale = 2; - while (cmp_clk > SSP_ConfigStruct->ClockRate) - { - cmp_clk = ssp_clk / ((cr0_div + 1) * prescale); - if (cmp_clk > SSP_ConfigStruct->ClockRate) - { - cr0_div++; - if (cr0_div > 0xFF) - { - cr0_div = 0; - prescale += 2; - } - } - } - - /* Write computed prescaler and divider back to register */ - SSPx->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK; - SSPx->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK; - SSPx->CPSR = prescale & SSP_CPSR_BITMASK; -} - -/*********************************************************************//** - * @brief De-initializes the SSPx peripheral registers to their - * default reset values. - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @return None - **********************************************************************/ -void SSP_DeInit(LPC_SSPn_Type* SSPx) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - - /* Disable SSP operation*/ - SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK; -} - -/*****************************************************************************//** - * @brief Get data size bit selected - * @param[in] SSPx pointer to LPC_SSPn_Type structure, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @return Data size, could be: - * - SSP_DATABIT_4 :4 bit transfer - * - SSP_DATABIT_5 :5 bit transfer - * ... - * - SSP_DATABIT_16 :16 bit transfer -*******************************************************************************/ -uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - return (SSPx->CR0 & (0xF)); -} - -/*****************************************************************************//** - * @brief Fills each SSP_InitStruct member with its default value: - * - CPHA = SSP_CPHA_FIRST - * - CPOL = SSP_CPOL_HI - * - ClockRate = 1000000 - * - Databit = SSP_DATABIT_8 - * - Mode = SSP_MASTER_MODE - * - FrameFormat = SSP_FRAME_SSP - * @param[in] SSP_InitStruct Pointer to a SSP_CFG_Type structure which will be - * initialized. - * @return None - *******************************************************************************/ -void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct) -{ - SSP_InitStruct->CPHA = SSP_CPHA_FIRST; - SSP_InitStruct->CPOL = SSP_CPOL_HI; - SSP_InitStruct->ClockRate = 100000; - SSP_InitStruct->Databit = SSP_DATABIT_8; - SSP_InitStruct->Mode = SSP_MASTER_MODE; - SSP_InitStruct->FrameFormat = SSP_FRAME_SPI; -} - - -/*********************************************************************//** - * @brief Enable or disable SSP peripheral's operation - * @param[in] SSPx SSP peripheral, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] NewState New State of SSPx peripheral's operation, should be: - * - ENABLE - * - DISABLE - * @return none - **********************************************************************/ -void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - SSPx->CR1 |= SSP_CR1_SSP_EN; - } - else - { - SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK; - } -} - -/*********************************************************************//** - * @brief Enable or disable Loop Back mode function in SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] NewState New State of Loop Back mode, should be: - * - ENABLE - * - DISABLE - * @return None - **********************************************************************/ -void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - SSPx->CR1 |= SSP_CR1_LBM_EN; - } - else - { - SSPx->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK; - } -} - -/*********************************************************************//** - * @brief Enable or disable Slave Output function in SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] NewState New State of Slave Output function, should be: - * - ENABLE :Slave Output in normal operation - * - DISABLE :Slave Output is disabled. This blocks - * SSP controller from driving the transmit data line (MISO) - * Note: This function is available when SSP peripheral in Slave mode - * @return None - **********************************************************************/ -void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - SSPx->CR1 &= (~SSP_CR1_SO_DISABLE) & SSP_CR1_BITMASK; - } - else - { - SSPx->CR1 |= SSP_CR1_SO_DISABLE; - } -} - -/*********************************************************************//** - * @brief Transmit a single data through SSPx peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] Data Data to transmit (must be 16 or 8-bit long, this - * depend on SSP data bit number configured) - * @return none - **********************************************************************/ -void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - - SSPx->DR = SSP_DR_BITMASK(Data); -} - - - -/*********************************************************************//** - * @brief Receive a single data from SSPx peripheral - * @param[in] SSPx SSP peripheral selected, should be - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @return Data received (16-bit long) - **********************************************************************/ -uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - - return ((uint16_t) (SSP_DR_BITMASK(SSPx->DR))); -} - -/*********************************************************************//** - * @brief SSP Read write data function - * @param[in] SSPx Pointer to SSP peripheral, should be - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] dataCfg Pointer to a SSP_DATA_SETUP_Type structure that - * contains specified information about transmit data - * configuration. - * @param[in] xfType Transfer type, should be: - * - SSP_TRANSFER_POLLING :Polling mode - * - SSP_TRANSFER_INTERRUPT :Interrupt mode - * @return Actual Data length has been transferred in polling mode. - * In interrupt mode, always return (0) - * Return (-1) if error. - * Note: This function can be used in both master and slave mode. - ***********************************************************************/ -int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \ - SSP_TRANSFER_Type xfType) -{ - uint8_t *rdata8; - uint8_t *wdata8; - uint16_t *rdata16; - uint16_t *wdata16; - uint32_t stat; - uint32_t tmp; - int32_t dataword; - - dataCfg->rx_cnt = 0; - dataCfg->tx_cnt = 0; - dataCfg->status = 0; - - - /* Clear all remaining data in RX FIFO */ - while (SSPx->SR & SSP_SR_RNE){ - tmp = (uint32_t) SSP_ReceiveData(SSPx); - } - - // Clear status - SSPx->ICR = SSP_ICR_BITMASK; - if(SSP_GetDataSize(SSPx)>8) - dataword = 1; - else dataword = 0; - - // Polling mode ---------------------------------------------------------------------- - if (xfType == SSP_TRANSFER_POLLING){ - if (dataword == 0){ - rdata8 = (uint8_t *)dataCfg->rx_data; - wdata8 = (uint8_t *)dataCfg->tx_data; - } else { - rdata16 = (uint16_t *)dataCfg->rx_data; - wdata16 = (uint16_t *)dataCfg->tx_data; - } - while ((dataCfg->tx_cnt < dataCfg->length) || (dataCfg->rx_cnt < dataCfg->length)){ - if ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt != dataCfg->length)){ - // Write data to buffer - if(dataCfg->tx_data == NULL){ - if (dataword == 0){ - SSP_SendData(SSPx, 0xFF); - dataCfg->tx_cnt++; - } else { - SSP_SendData(SSPx, 0xFFFF); - dataCfg->tx_cnt += 2; - } - } else { - if (dataword == 0){ - SSP_SendData(SSPx, *wdata8); - wdata8++; - dataCfg->tx_cnt++; - } else { - SSP_SendData(SSPx, *wdata16); - wdata16++; - dataCfg->tx_cnt += 2; - } - } - } - - // Check overrun error - if ((stat = SSPx->RIS) & SSP_RIS_ROR){ - // save status and return - dataCfg->status = stat | SSP_STAT_ERROR; - return (-1); - } - - // Check for any data available in RX FIFO - while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){ - // Read data from SSP data - tmp = SSP_ReceiveData(SSPx); - - // Store data to destination - if (dataCfg->rx_data != NULL) - { - if (dataword == 0){ - *(rdata8) = (uint8_t) tmp; - rdata8++; - } else { - *(rdata16) = (uint16_t) tmp; - rdata16++; - } - } - // Increase counter - if (dataword == 0){ - dataCfg->rx_cnt++; - } else { - dataCfg->rx_cnt += 2; - } - } - } - - // save status - dataCfg->status = SSP_STAT_DONE; - - if (dataCfg->tx_data != NULL){ - return dataCfg->tx_cnt; - } else if (dataCfg->rx_data != NULL){ - return dataCfg->rx_cnt; - } else { - return (0); - } - } - - // Interrupt mode ---------------------------------------------------------------------- - else if (xfType == SSP_TRANSFER_INTERRUPT){ - - while ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){ - // Write data to buffer - if(dataCfg->tx_data == NULL){ - if (dataword == 0){ - SSP_SendData(SSPx, 0xFF); - dataCfg->tx_cnt++; - } else { - SSP_SendData(SSPx, 0xFFFF); - dataCfg->tx_cnt += 2; - } - } else { - if (dataword == 0){ - SSP_SendData(SSPx, (*(uint8_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt))); - dataCfg->tx_cnt++; - } else { - SSP_SendData(SSPx, (*(uint16_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt))); - dataCfg->tx_cnt += 2; - } - } - - // Check error - if ((stat = SSPx->RIS) & SSP_RIS_ROR){ - // save status and return - dataCfg->status = stat | SSP_STAT_ERROR; - return (-1); - } - - // Check for any data available in RX FIFO - while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){ - // Read data from SSP data - tmp = SSP_ReceiveData(SSPx); - - // Store data to destination - if (dataCfg->rx_data != NULL) - { - if (dataword == 0){ - *(uint8_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint8_t) tmp; - } else { - *(uint16_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint16_t) tmp; - } - } - // Increase counter - if (dataword == 0){ - dataCfg->rx_cnt++; - } else { - dataCfg->rx_cnt += 2; - } - } - } - - // If there more data to sent or receive - if ((dataCfg->rx_cnt != dataCfg->length) || (dataCfg->tx_cnt < dataCfg->length)){ - // Enable all interrupt - SSPx->IMSC = SSP_IMSC_BITMASK; - } else { - // Save status - dataCfg->status = SSP_STAT_DONE; - } - return (0); - } - - return (-1); -} - -/*********************************************************************//** - * @brief Checks whether the specified SSP status flag is set or not - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] FlagType Type of flag to check status, should be: - * - SSP_STAT_TXFIFO_EMPTY :TX FIFO is empty - * - SSP_STAT_TXFIFO_NOTFULL :TX FIFO is not full - * - SSP_STAT_RXFIFO_NOTEMPTY :RX FIFO is not empty - * - SSP_STAT_RXFIFO_FULL :RX FIFO is full - * - SSP_STAT_BUSY :SSP peripheral is busy - * @return New State of specified SSP status flag - **********************************************************************/ -FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_SSP_STAT(FlagType)); - - return ((SSPx->SR & FlagType) ? SET : RESET); -} - -/*********************************************************************//** - * @brief Enable or disable specified interrupt type in SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] IntType Interrupt type in SSP peripheral, should be: - * - SSP_INTCFG_ROR :Receive Overrun interrupt - * - SSP_INTCFG_RT :Receive Time out interrupt - * - SSP_INTCFG_RX :RX FIFO is at least half full interrupt - * - SSP_INTCFG_TX :TX FIFO is at least half empty interrupt - * @param[in] NewState New State of specified interrupt type, should be: - * - ENABLE :Enable this interrupt type - * - DISABLE :Disable this interrupt type - * @return None - **********************************************************************/ -void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_SSP_INTCFG(IntType)); - - if (NewState == ENABLE) - { - SSPx->IMSC |= IntType; - } - else - { - SSPx->IMSC &= (~IntType) & SSP_IMSC_BITMASK; - } -} - -/*********************************************************************//** - * @brief Check whether the specified Raw interrupt status flag is - * set or not - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] RawIntType Raw Interrupt Type, should be: - * - SSP_INTSTAT_RAW_ROR :Receive Overrun interrupt - * - SSP_INTSTAT_RAW_RT :Receive Time out interrupt - * - SSP_INTSTAT_RAW_RX :RX FIFO is at least half full interrupt - * - SSP_INTSTAT_RAW_TX :TX FIFO is at least half empty interrupt - * @return New State of specified Raw interrupt status flag in SSP peripheral - * Note: Enabling/Disabling specified interrupt in SSP peripheral does not - * effect to Raw Interrupt Status flag. - **********************************************************************/ -IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_SSP_INTSTAT_RAW(RawIntType)); - - return ((SSPx->RIS & RawIntType) ? SET : RESET); -} - - -/*********************************************************************//** - * @brief Check whether the specified interrupt status flag is - * set or not - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] IntType Raw Interrupt Type, should be: - * - SSP_INTSTAT_ROR :Receive Overrun interrupt - * - SSP_INTSTAT_RT :Receive Time out interrupt - * - SSP_INTSTAT_RX :RX FIFO is at least half full interrupt - * - SSP_INTSTAT_TX :TX FIFO is at least half empty interrupt - * @return New State of specified interrupt status flag in SSP peripheral - * Note: Enabling/Disabling specified interrupt in SSP peripheral effects - * to Interrupt Status flag. - **********************************************************************/ -IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_SSP_INTSTAT(IntType)); - - return ((SSPx->MIS & IntType) ? SET :RESET); -} - -/*********************************************************************//** - * @brief Clear specified interrupt pending in SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] IntType Interrupt pending to clear, should be: - * - SSP_INTCLR_ROR :clears the "frame was received when - * RxFIFO was full" interrupt. - * - SSP_INTCLR_RT :clears the "Rx FIFO was not empty and - * has not been read for a timeout period" interrupt. - * @return None - **********************************************************************/ -void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_SSP_INTCLR(IntType)); - - SSPx->ICR = IntType; -} - -/*********************************************************************//** - * @brief Enable/Disable DMA function for SSP peripheral - * @param[in] SSPx SSP peripheral selected, should be: - * - LPC_SSP0 :SSP0 peripheral - * - LPC_SSP1 :SSP1 peripheral - * @param[in] DMAMode Type of DMA, should be: - * - SSP_DMA_TX :DMA for the transmit FIFO - * - SSP_DMA_RX :DMA for the Receive FIFO - * @param[in] NewState New State of DMA function on SSP peripheral, - * should be: - * - ENALBE :Enable this function - * - DISABLE :Disable this function - * @return None - **********************************************************************/ -void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_SSPx(SSPx)); - CHECK_PARAM(PARAM_SSP_DMA(DMAMode)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - SSPx->DMACR |= DMAMode; - } - else - { - SSPx->DMACR &= (~DMAMode) & SSP_DMA_BITMASK; - } -} - -/** - * @} - */ - -#endif /* _SSP */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_timer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_timer.c deleted file mode 100644 index 1cf4ff265..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_timer.c +++ /dev/null @@ -1,611 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_timer.c 2011-06-02 -*//** -* @file lpc18xx_timer.c -* @brief Contains all functions support for Timer firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup TIMER - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_timer.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _TIM - -/* Private Functions ---------------------------------------------------------- */ - -static uint32_t getPClock (uint32_t timernum); -static uint32_t converUSecToVal (uint32_t timernum, uint32_t usec); -static uint32_t converPtrToTimeNum (LPC_TIMERn_Type *TIMx); - - -/*********************************************************************//** - * @brief Get peripheral clock of each timer controller - * @param[in] timernum Timer number, should be: 0..3 - * @return Peripheral clock of timer - **********************************************************************/ -extern uint32_t M3Frequency; -static uint32_t getPClock (uint32_t timernum) -{ - uint32_t clkdlycnt; - switch (timernum) - { - case 0: - clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER0)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER0); - break; - - case 1: - clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER1)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER1); - break; - - case 2: - clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER2)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER2); - break; - - case 3: - clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER3)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER3); - break; - } - return clkdlycnt; -} - - -/*********************************************************************//** - * @brief Convert a time to a timer count value - * @param[in] timernum Timer number, should be: 0..3 - * @param[in] usec Time in microseconds - * @return The number of required clock ticks to give the time delay - **********************************************************************/ -uint32_t converUSecToVal (uint32_t timernum, uint32_t usec) -{ - uint64_t clkdlycnt; - - // Get Pclock of timer - clkdlycnt = (uint64_t) getPClock(timernum); - - clkdlycnt = (clkdlycnt * usec) / 1000000; - return (uint32_t) clkdlycnt; -} - - -/*********************************************************************//** - * @brief Convert a timer register pointer to a timer number - * @param[in] TIMx Pointer to LPC_TIMERn_Type, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @return The timer number (0 to 3) or -1 if register pointer is bad - **********************************************************************/ -uint32_t converPtrToTimeNum (LPC_TIMERn_Type *TIMx) -{ - uint32_t tnum = 0xFFFFFFFF; - - if (TIMx == LPC_TIMER0) - { - tnum = 0; - } - else if (TIMx == LPC_TIMER1) - { - tnum = 1; - } - else if (TIMx == LPC_TIMER2) - { - tnum = 2; - } - else if (TIMx == LPC_TIMER3) - { - tnum = 3; - } - - return tnum; -} - -/* End of Private Functions ---------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup TIM_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Get Interrupt Status - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] IntFlag: interrupt type, should be: - * - TIM_MR0_INT :Interrupt for Match channel 0 - * - TIM_MR1_INT :Interrupt for Match channel 1 - * - TIM_MR2_INT :Interrupt for Match channel 2 - * - TIM_MR3_INT :Interrupt for Match channel 3 - * - TIM_CR0_INT :Interrupt for Capture channel 0 - * - TIM_CR1_INT :Interrupt for Capture channel 1 - * @return FlagStatus - * - SET :interrupt - * - RESET :no interrupt - **********************************************************************/ -FlagStatus TIM_GetIntStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag) -{ - uint8_t temp; - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag)); - temp = (TIMx->IR)& TIM_IR_CLR(IntFlag); - if (temp) - return SET; - - return RESET; - -} -/*********************************************************************//** - * @brief Get Capture Interrupt Status - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] IntFlag: interrupt type, should be: - * - TIM_MR0_INT :Interrupt for Match channel 0 - * - TIM_MR1_INT :Interrupt for Match channel 1 - * - TIM_MR2_INT :Interrupt for Match channel 2 - * - TIM_MR3_INT :Interrupt for Match channel 3 - * - TIM_CR0_INT :Interrupt for Capture channel 0 - * - TIM_CR1_INT :Interrupt for Capture channel 1 - * @return FlagStatus - * - SET :interrupt - * - RESET :no interrupt - **********************************************************************/ -FlagStatus TIM_GetIntCaptureStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag) -{ - uint8_t temp; - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag)); - temp = (TIMx->IR) & (1<<(4+IntFlag)); - if(temp) - return SET; - return RESET; -} -/*********************************************************************//** - * @brief Clear Interrupt pending - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] IntFlag: interrupt type, should be: - * - TIM_MR0_INT :Interrupt for Match channel 0 - * - TIM_MR1_INT :Interrupt for Match channel 1 - * - TIM_MR2_INT :Interrupt for Match channel 2 - * - TIM_MR3_INT :Interrupt for Match channel 3 - * - TIM_CR0_INT :Interrupt for Capture channel 0 - * - TIM_CR1_INT :Interrupt for Capture channel 1 - * @return None - **********************************************************************/ -void TIM_ClearIntPending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag)); - TIMx->IR = TIM_IR_CLR(IntFlag); -} - -/*********************************************************************//** - * @brief Clear Capture Interrupt pending - * @param[in] TIMx Timer selection, should be - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] IntFlag interrupt type, should be: - * - TIM_MR0_INT :Interrupt for Match channel 0 - * - TIM_MR1_INT :Interrupt for Match channel 1 - * - TIM_MR2_INT :Interrupt for Match channel 2 - * - TIM_MR3_INT :Interrupt for Match channel 3 - * - TIM_CR0_INT :Interrupt for Capture channel 0 - * - TIM_CR1_INT :Interrupt for Capture channel 1 - * @return None - **********************************************************************/ -void TIM_ClearIntCapturePending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag)); - TIMx->IR = (1<<(4+IntFlag)); -} - -/*********************************************************************//** - * @brief Configuration for Timer at initial time - * @param[in] TimerCounterMode timer counter mode, should be: - * - TIM_TIMER_MODE :Timer mode - * - TIM_COUNTER_RISING_MODE :Counter rising mode - * - TIM_COUNTER_FALLING_MODE :Counter falling mode - * - TIM_COUNTER_ANY_MODE :Counter on both edges - * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type or - * TIM_COUNTERCFG_Type - * @return None - **********************************************************************/ -void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct) -{ - if (TimerCounterMode == TIM_TIMER_MODE ) - { - TIM_TIMERCFG_Type * pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct; - pTimeCfg->PrescaleOption = TIM_PRESCALE_USVAL; - pTimeCfg->PrescaleValue = 1; - } - else - { - TIM_COUNTERCFG_Type * pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct; - pCounterCfg->CountInputSelect = TIM_COUNTER_INCAP0; - } -} - -/*********************************************************************//** - * @brief Initial Timer/Counter device - * Set Clock frequency for Timer - * Set initial configuration for Timer - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] TimerCounterMode Timer counter mode, should be: - * - TIM_TIMER_MODE :Timer mode - * - TIM_COUNTER_RISING_MODE :Counter rising mode - * - TIM_COUNTER_FALLING_MODE :Counter falling mode - * - TIM_COUNTER_ANY_MODE :Counter on both edges - * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type - * that contains the configuration information for the - * specified Timer peripheral. - * @return None - **********************************************************************/ -void TIM_Init(LPC_TIMERn_Type *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct) -{ - TIM_TIMERCFG_Type *pTimeCfg; - TIM_COUNTERCFG_Type *pCounterCfg; - - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_MODE_OPT(TimerCounterMode)); - - //set power - if (TIMx== LPC_TIMER0) - { - - } - else if (TIMx== LPC_TIMER1) - { - - } - - else if (TIMx== LPC_TIMER2) - { - - } - else if (TIMx== LPC_TIMER3) - { - - } - - TIMx->CCR &= ~TIM_CTCR_MODE_MASK; - TIMx->CCR |= TIM_TIMER_MODE; - - TIMx->TC =0; - TIMx->PC =0; - TIMx->PR =0; - TIMx->TCR |= (1<<1); //Reset Counter - TIMx->TCR &= ~(1<<1); //release reset - if (TimerCounterMode == TIM_TIMER_MODE ) - { - pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct; - if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL) - { - TIMx->PR = pTimeCfg->PrescaleValue -1 ; - } - else - { - TIMx->PR = converUSecToVal (converPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1; - } - } - else - { - - pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct; - TIMx->CCR &= ~TIM_CTCR_INPUT_MASK; - if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1) - TIMx->CCR |= _BIT(2); - } - - // Clear interrupt pending - TIMx->IR = 0xFFFFFFFF; - -} - -/*********************************************************************//** - * @brief Close Timer/Counter device - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @return None - **********************************************************************/ -void TIM_DeInit (LPC_TIMERn_Type *TIMx) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - // Disable timer/counter - TIMx->TCR = 0x00; - -} - -/*********************************************************************//** - * @brief Start/Stop Timer/Counter device - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] NewState - * - ENABLE :Set timer enable - * - DISABLE :Disable timer - * @return None - **********************************************************************/ -void TIM_Cmd(LPC_TIMERn_Type *TIMx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - if (NewState == ENABLE) - { - TIMx->TCR |= TIM_ENABLE; - } - else - { - TIMx->TCR &= ~TIM_ENABLE; - } -} - -/*********************************************************************//** - * @brief Reset Timer/Counter device, - * Make TC and PC are synchronously reset on the next - * positive edge of PCLK - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @return None - **********************************************************************/ -void TIM_ResetCounter(LPC_TIMERn_Type *TIMx) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - TIMx->TCR |= TIM_RESET; - TIMx->TCR &= ~TIM_RESET; -} - -/*********************************************************************//** - * @brief Configuration for Match register - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] TIM_MatchConfigStruct Pointer to TIM_MATCHCFG_Type - * - MatchChannel : choose channel 0 or 1 - * - IntOnMatch : if SET, interrupt will be generated when MRxx match - * the value in TC - * - StopOnMatch : if SET, TC and PC will be stopped whenM Rxx match - * the value in TC - * - ResetOnMatch : if SET, Reset on MR0 when MRxx match - * the value in TC - * -ExtMatchOutputType: Select output for external match - * + 0: Do nothing for external output pin if match - * + 1: Force external output pin to low if match - * + 2: Force external output pin to high if match - * + 3: Toggle external output pin if match - * MatchValue: Set the value to be compared with TC value - * @return None - **********************************************************************/ -void TIM_ConfigMatch(LPC_TIMERn_Type *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct) -{ - - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_EXTMATCH_OPT(TIM_MatchConfigStruct->ExtMatchOutputType)); - - switch(TIM_MatchConfigStruct->MatchChannel) - { - case 0: - TIMx->MR[0] = TIM_MatchConfigStruct->MatchValue; - break; - case 1: - TIMx->MR[1] = TIM_MatchConfigStruct->MatchValue; - break; - case 2: - TIMx->MR[2] = TIM_MatchConfigStruct->MatchValue; - break; - case 3: - TIMx->MR[3] = TIM_MatchConfigStruct->MatchValue; - break; - default: - //Error match value - //Error loop - while(1); - } - //interrupt on MRn - TIMx->MCR &=~TIM_MCR_CHANNEL_MASKBIT(TIM_MatchConfigStruct->MatchChannel); - - if (TIM_MatchConfigStruct->IntOnMatch) - TIMx->MCR |= TIM_INT_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - //reset on MRn - if (TIM_MatchConfigStruct->ResetOnMatch) - TIMx->MCR |= TIM_RESET_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - //stop on MRn - if (TIM_MatchConfigStruct->StopOnMatch) - TIMx->MCR |= TIM_STOP_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - // match output type - - TIMx->EMR &= ~TIM_EM_MASK(TIM_MatchConfigStruct->MatchChannel); - TIMx->EMR |= TIM_EM_SET(TIM_MatchConfigStruct->MatchChannel,TIM_MatchConfigStruct->ExtMatchOutputType); -} -/*********************************************************************//** - * @brief Update Match value - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] MatchChannel Match channel, should be: 0..3 - * @param[in] MatchValue updated match value - * @return None - **********************************************************************/ -void TIM_UpdateMatchValue(LPC_TIMERn_Type *TIMx,uint8_t MatchChannel, uint32_t MatchValue) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - switch(MatchChannel) - { - case 0: - TIMx->MR[0] = MatchValue; - break; - case 1: - TIMx->MR[1] = MatchValue; - break; - case 2: - TIMx->MR[2] = MatchValue; - break; - case 3: - TIMx->MR[3] = MatchValue; - break; - default: - //Error Loop - while(1); - } - -} -/*********************************************************************//** - * @brief Configuration for Capture register - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] TIM_CaptureConfigStruct Pointer to TIM_CAPTURECFG_Type - * @return None - **********************************************************************/ -void TIM_ConfigCapture(LPC_TIMERn_Type *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct) -{ - - CHECK_PARAM(PARAM_TIMx(TIMx)); - TIMx->CCR &= ~TIM_CCR_CHANNEL_MASKBIT(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->RisingEdge) - TIMx->CCR |= TIM_CAP_RISING(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->FallingEdge) - TIMx->CCR |= TIM_CAP_FALLING(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->IntOnCaption) - TIMx->CCR |= TIM_INT_ON_CAP(TIM_CaptureConfigStruct->CaptureChannel); -} - -/*********************************************************************//** - * @brief Read value of capture register in timer/counter device - * @param[in] TIMx Pointer to timer/counter device, should be: - * - LPC_TIM0 :TIMER0 peripheral - * - LPC_TIM1 :TIMER1 peripheral - * - LPC_TIM2 :TIMER2 peripheral - * - LPC_TIM3 :TIMER3 peripheral - * @param[in] CaptureChannel: capture channel number, should be: - * - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn - * - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn - * - TIM_COUNTER_INCAP1: CAPn.2 input pin for TIMERn - * - TIM_COUNTER_INCAP1: CAPn.3 input pin for TIMERn - * @return Value of capture register - **********************************************************************/ -uint32_t TIM_GetCaptureValue(LPC_TIMERn_Type *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_COUNTER_INPUT_OPT(CaptureChannel)); - - switch(CaptureChannel){ - case 0: return TIMx->CR[0]; - case 1: return TIMx->CR[1]; - case 2: return TIMx->CR[2]; - case 3: return TIMx->CR[3]; - } - return 0; -} -/*---------------Advanced TIMER functions -----------------------------------------*/ -/*********************************************************************//** - * @brief Timer wait (microseconds) - * @param[in] time number of microseconds waiting - * @return None - **********************************************************************/ -void TIM_Waitus(uint32_t time) -{ - TIM_MATCHCFG_Type MatchConfigStruct; - LPC_TIMER0->IR = 0xFFFFFFFF; - - MatchConfigStruct.MatchChannel = 0; - MatchConfigStruct.IntOnMatch = ENABLE; - MatchConfigStruct.ResetOnMatch = ENABLE; - MatchConfigStruct.StopOnMatch = ENABLE; - MatchConfigStruct.ExtMatchOutputType = 0; - MatchConfigStruct.MatchValue = time; - - TIM_ConfigMatch(LPC_TIMER0, &MatchConfigStruct); - TIM_Cmd(LPC_TIMER0,ENABLE); - //wait until interrupt flag occur - while(!(LPC_TIMER0->IR & 0x01)); - TIM_ResetCounter(LPC_TIMER0); -} -/*********************************************************************//** - * @brief Timer wait (milliseconds) - * @param[in] time number of millisecond waiting - * @return None - **********************************************************************/ -void TIM_Waitms(uint32_t time) -{ - TIM_Waitus(time * 1000); -} -/** - * @} - */ - -#endif /* _TIMER */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_uart.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_uart.c deleted file mode 100644 index 1e518e832..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_uart.c +++ /dev/null @@ -1,1438 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_uart.c 2011-06-02 -*//** -* @file lpc18xx_uart.c -* @brief Contains all functions support for UART firmware library on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup UART - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_uart.h" -#include "lpc18xx_cgu.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _UART - -/* Private Functions ---------------------------------------------------------- */ - -static Status uart_set_divisors(LPC_USARTn_Type *UARTx, uint32_t baudrate); - - -/*********************************************************************//** - * @brief Determines best dividers to get a target clock rate - * @param[in] UARTx Pointer to selected UART peripheral, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] baudrate Desired UART baud rate. - * @return Error status, could be: - * - SUCCESS - * - ERROR - **********************************************************************/ -static Status uart_set_divisors(LPC_USARTn_Type *UARTx, uint32_t baudrate) -{ - Status errorStatus = ERROR; - - uint32_t uClk; - uint32_t d, m, bestd, bestm, tmp; - uint64_t best_divisor, divisor; - uint32_t current_error, best_error; - uint32_t recalcbaud; - - /* get UART block clock */ - //to be defined uClk = CGU_GetCLK(CGU_CLKTYPE_PER); -#ifdef _UART0 - if(UARTx == LPC_USART0) - { - uClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_UART0); - } -#endif - -#ifdef _UART1 - if(((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - uClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_UART1); - } -#endif - -#ifdef _UART2 - if(UARTx == LPC_USART2) - { - uClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_UART2); - } -#endif - -#ifdef _UART3 - if(UARTx == LPC_USART3) - { - uClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_UART3); - } -#endif - - /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers - * The formula is : - * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL) - * It involves floating point calculations. That's the reason the formulae are adjusted with - * Multiply and divide method.*/ - /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions: - * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */ - best_error = 0xFFFFFFFF; /* Worst case */ - bestd = 0; - bestm = 0; - best_divisor = 0; - for (m = 1 ; m <= 15 ;m++) - { - for (d = 0 ; d < m ; d++) - { - divisor = ((uint64_t)uClk<<28)*m/(baudrate*(m+d)); - current_error = divisor & 0xFFFFFFFF; - - tmp = divisor>>32; - - /* Adjust error */ - if(current_error > ((uint32_t)1<<31)){ - current_error = -current_error; - tmp++; - } - - if(tmp<1 || tmp>65536) /* Out of range */ - continue; - - if( current_error < best_error){ - best_error = current_error; - best_divisor = tmp; - bestd = d; - bestm = m; - if(best_error == 0) break; - } - } /* end of inner for loop */ - - if (best_error == 0) - break; - } /* end of outer for loop */ - - if(best_divisor == 0) return ERROR; /* can not find best match */ - - recalcbaud = (uClk>>4) * bestm/(best_divisor * (bestm + bestd)); - - /* reuse best_error to evaluate baud error*/ - if(baudrate>recalcbaud) best_error = baudrate - recalcbaud; - else best_error = recalcbaud -baudrate; - - best_error = best_error * 100 / baudrate; - - if (best_error < UART_ACCEPTED_BAUDRATE_ERROR) - { - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->LCR |= UART_LCR_DLAB_EN; - ((LPC_UART1_Type *)UARTx)->/*DLIER.*/DLM = UART_LOAD_DLM(best_divisor); - ((LPC_UART1_Type *)UARTx)->/*RBTHDLR.*/DLL = UART_LOAD_DLL(best_divisor); - /* Then reset DLAB bit */ - ((LPC_UART1_Type *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; - ((LPC_UART1_Type *)UARTx)->FDR = (UART_FDR_MULVAL(bestm) \ - | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; - } - else - { - UARTx->LCR |= UART_LCR_DLAB_EN; - UARTx->/*DLIER.*/DLM = UART_LOAD_DLM(best_divisor); - UARTx->/*RBTHDLR.*/DLL = UART_LOAD_DLL(best_divisor); - /* Then reset DLAB bit */ - UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; - UARTx->FDR = (UART_FDR_MULVAL(bestm) \ - | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; - } - errorStatus = SUCCESS; - } - - return errorStatus; -} - -/* End of Private Functions ---------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup UART_Public_Functions - * @{ - */ -/* UART Init/DeInit functions -------------------------------------------------*/ -/********************************************************************//** - * @brief Initializes the UARTx peripheral according to the specified - * parameters in the UART_ConfigStruct. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure - * that contains the configuration information for the - * specified UART peripheral. - * @return None - *********************************************************************/ -void UART_Init(LPC_USARTn_Type *UARTx, UART_CFG_Type *UART_ConfigStruct) -{ - uint32_t tmp; - - // For debug mode - CHECK_PARAM(PARAM_UARTx(UARTx)); - CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits)); - CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits)); - CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity)); - -#ifdef _UART0 - if(UARTx == LPC_USART0) - { - /* Set up peripheral clock for UART0 module */ - //LPC_CGU->BASE_UART0_CLK = (SRC_PL160M_0<<24) | (1<<11); // Use PLL1 and auto block - CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART0); - } -#endif - -#ifdef _UART1 - if(((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - /* Set up peripheral clock for UART1 module */ - //LPC_CGU->BASE_UART1_CLK = (SRC_PL160M_0<<24) | (1<<11); // Use PLL1 and auto block - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_UART1); - } -#endif - -#ifdef _UART2 - if(UARTx == LPC_USART2) - { - /* Set up peripheral clock for UART2 module */ - //LPC_CGU->BASE_UART2_CLK = (SRC_PL160M_0<<24) | (1<<11); // Use PLL1 and auto block - CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART2); - } -#endif - -#ifdef _UART3 - if(UARTx == LPC_USART3) - { - /* Set up peripheral clock for UART3 module */ - //LPC_CGU->BASE_UART3_CLK = (SRC_PL160M_0<<24) | (1<<11); // Use PLL1 and auto block - CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART3); - } -#endif - - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - /* FIFOs are empty */ - ((LPC_UART1_Type *)UARTx)->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN \ - | UART_FCR_RX_RS | UART_FCR_TX_RS); - // Disable FIFO - ((LPC_UART1_Type *)UARTx)->/*IIFCR.*/FCR = 0; - - // Dummy reading - while (((LPC_UART1_Type *)UARTx)->LSR & UART_LSR_RDR) - { - tmp = ((LPC_UART1_Type *)UARTx)->/*RBTHDLR.*/RBR; - } - - ((LPC_UART1_Type *)UARTx)->TER = UART1_TER_TXEN; - // Wait for current transmit complete - while (!(((LPC_UART1_Type *)UARTx)->LSR & UART_LSR_THRE)); - // Disable Tx - ((LPC_UART1_Type *)UARTx)->TER = 0; - - // Disable interrupt - ((LPC_UART1_Type *)UARTx)->/*DLIER.*/IER = 0; - // Set LCR to default state - ((LPC_UART1_Type *)UARTx)->LCR = 0; - // Set ACR to default state - ((LPC_UART1_Type *)UARTx)->ACR = 0; - // Set Modem Control to default state - ((LPC_UART1_Type *)UARTx)->MCR = 0; - // Set RS485 control to default state - ((LPC_UART1_Type *)UARTx)->RS485CTRL = 0; - // Set RS485 delay timer to default state - ((LPC_UART1_Type *)UARTx)->RS485DLY = 0; - // Set RS485 addr match to default state - ((LPC_UART1_Type *)UARTx)->RS485ADRMATCH = 0; - //Dummy Reading to Clear Status - tmp = ((LPC_UART1_Type *)UARTx)->MSR; - tmp = ((LPC_UART1_Type *)UARTx)->LSR; - } - else - { - /* FIFOs are empty */ - UARTx->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); - // Disable FIFO - UARTx->/*IIFCR.*/FCR = 0; - - // Dummy reading - while (UARTx->LSR & UART_LSR_RDR) - { - tmp = UARTx->/*RBTHDLR.*/RBR; - } - - UARTx->TER = UART0_2_3_TER_TXEN; - // Wait for current transmit complete - while (!(UARTx->LSR & UART_LSR_THRE)); - // Disable Tx - UARTx->TER = 0; - - // Disable interrupt - UARTx->/*DLIER.*/IER = 0; - // Set LCR to default state - UARTx->LCR = 0; - // Set ACR to default state - UARTx->ACR = 0; - // set HDEN to default state - UARTx->HDEN = 0; - // set SCICTRL to default state - UARTx->SCICTRL = 0; - // set SYNCCTRL to default state - UARTx->SYNCCTRL =0; - // Set RS485 control to default state - UARTx->RS485CTRL = 0; - // Set RS485 delay timer to default state - UARTx->RS485DLY = 0; - // Set RS485 addr match to default state - UARTx->RS485ADRMATCH = 0; - // Dummy reading - tmp = UARTx->LSR; - } - - if (UARTx == LPC_USART3) - { - // Set IrDA to default state - UARTx->ICR = 0; - } - - // Set Line Control register ---------------------------- - - uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate)); - - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - tmp = (((LPC_UART1_Type *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \ - & UART_LCR_BITMASK; - } - else - { - tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK; - } - - switch (UART_ConfigStruct->Databits){ - case UART_DATABIT_5: - tmp |= UART_LCR_WLEN5; - break; - case UART_DATABIT_6: - tmp |= UART_LCR_WLEN6; - break; - case UART_DATABIT_7: - tmp |= UART_LCR_WLEN7; - break; - case UART_DATABIT_8: - default: - tmp |= UART_LCR_WLEN8; - break; - } - - if (UART_ConfigStruct->Parity == UART_PARITY_NONE) - { - // Do nothing... - } - else - { - tmp |= UART_LCR_PARITY_EN; - switch (UART_ConfigStruct->Parity) - { - case UART_PARITY_ODD: - tmp |= UART_LCR_PARITY_ODD; - break; - - case UART_PARITY_EVEN: - tmp |= UART_LCR_PARITY_EVEN; - break; - - case UART_PARITY_SP_1: - tmp |= UART_LCR_PARITY_F_1; - break; - - case UART_PARITY_SP_0: - tmp |= UART_LCR_PARITY_F_0; - break; - default: - break; - } - } - - switch (UART_ConfigStruct->Stopbits){ - case UART_STOPBIT_2: - tmp |= UART_LCR_STOPBIT_SEL; - break; - case UART_STOPBIT_1: - default: - // Do no thing - break; - } - - - // Write back to LCR, configure FIFO and Disable Tx - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); - } - else - { - UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); - } -} - -/*********************************************************************//** - * @brief De-initializes the UARTx peripheral registers to their - * default reset values. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @return None - **********************************************************************/ -void UART_DeInit(LPC_USARTn_Type* UARTx) -{ - // For debug mode - CHECK_PARAM(PARAM_UARTx(UARTx)); - - UART_TxCmd(UARTx, DISABLE); - -#ifdef _UART0 - if (UARTx == LPC_USART0) - { - /* Set up peripheral clock for UART0 module */ - //LPC_CGU->BASE_UART0_CLK = (SRC_PL160M_1<<24) | (1<<11); // base SRC_PL160M_1 is not configured, so no clk out - } -#endif - -#ifdef _UART1 - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - /* Set up peripheral clock for UART1 module */ - //LPC_CGU->BASE_UART1_CLK = (SRC_PL160M_1<<24) | (1<<11); // base SRC_PL160M_1 is not configured, so no clk out - } -#endif - -#ifdef _UART2 - if (UARTx == LPC_USART2) - { - /* Set up peripheral clock for UART2 module */ - //LPC_CGU->BASE_UART2_CLK = (SRC_PL160M_1<<24) | (1<<11); // base SRC_PL160M_1 is not configured, so no clk out - } -#endif - -#ifdef _UART3 - if (UARTx == LPC_USART3) - { - /* Set up peripheral clock for UART3 module */ - //LPC_CGU->BASE_UART3_CLK = (SRC_PL160M_1<<24) | (1<<11); // base SRC_PL160M_1 is not configured, so no clk out - } -#endif -} - -/*****************************************************************************//** - * @brief Fills each UART_InitStruct member with its default value: - * - 9600 bps - * - 8-bit data - * - 1 Stopbit - * - None Parity - * @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure which will - * be initialized. - * @return None - *******************************************************************************/ -void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct) -{ - UART_InitStruct->Baud_rate = 9600; - UART_InitStruct->Databits = UART_DATABIT_8; - UART_InitStruct->Parity = UART_PARITY_NONE; - UART_InitStruct->Stopbits = UART_STOPBIT_1; -} - -/* UART Send/Recieve functions -------------------------------------------------*/ -/*********************************************************************//** - * @brief Transmit a single data through UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] Data Data to transmit (must be 8-bit long) - * @return None - **********************************************************************/ -void UART_SendByte(LPC_USARTn_Type* UARTx, uint8_t Data) -{ - CHECK_PARAM(PARAM_UARTx(UARTx)); - - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT; - } - else - { - UARTx->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT; - } - -} - - -/*********************************************************************//** - * @brief Receive a single data from UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @return Data received - **********************************************************************/ -uint8_t UART_ReceiveByte(LPC_USARTn_Type* UARTx) -{ - CHECK_PARAM(PARAM_UARTx(UARTx)); - - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - return (((LPC_UART1_Type *)UARTx)->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT); - } - else - { - return (UARTx->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT); - } -} - -/*********************************************************************//** - * @brief Send a block of data via UART peripheral - * @param[in] UARTx Selected UART peripheral used to send data, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] txbuf Pointer to Transmit buffer - * @param[in] buflen Length of Transmit buffer - * @param[in] flag Flag used in UART transfer, should be - * - NONE_BLOCKING - * - BLOCKING - * @return Number of bytes sent. - * - * Note: when using UART in BLOCKING mode, a time-out condition is used - * via defined symbol UART_BLOCKING_TIMEOUT. - **********************************************************************/ -uint32_t UART_Send(LPC_USARTn_Type *UARTx, uint8_t *txbuf, - uint32_t buflen, TRANSFER_BLOCK_Type flag) -{ - uint32_t bToSend, bSent, timeOut, fifo_cnt; - uint8_t *pChar = txbuf; - - bToSend = buflen; - - // blocking mode - if (flag == BLOCKING) { - bSent = 0; - while (bToSend){ - timeOut = UART_BLOCKING_TIMEOUT; - // Wait for THR empty with timeout - while (!(UARTx->LSR & UART_LSR_THRE)) { - if (timeOut == 0) break; - timeOut--; - } - // Time out! - if(timeOut == 0) break; - fifo_cnt = UART_TX_FIFO_SIZE; - while (fifo_cnt && bToSend){ - UART_SendByte(UARTx, (*pChar++)); - fifo_cnt--; - bToSend--; - bSent++; - } - } - } - // None blocking mode - else { - bSent = 0; - while (bToSend) { - if (!(UARTx->LSR & UART_LSR_THRE)){ - break; - } - fifo_cnt = UART_TX_FIFO_SIZE; - while (fifo_cnt && bToSend) { - UART_SendByte(UARTx, (*pChar++)); - bToSend--; - fifo_cnt--; - bSent++; - } - } - } - return bSent; -} - -/*********************************************************************//** - * @brief Receive a block of data via UART peripheral - * @param[in] UARTx Selected UART peripheral used to send data, - * should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[out] rxbuf Pointer to Received buffer - * @param[in] buflen Length of Received buffer - * @param[in] flag Flag mode, should be: - * - NONE_BLOCKING - * - BLOCKING - * @return Number of bytes received - * - * Note: when using UART in BLOCKING mode, a time-out condition is used - * via defined symbol UART_BLOCKING_TIMEOUT. - **********************************************************************/ -uint32_t UART_Receive(LPC_USARTn_Type *UARTx, uint8_t *rxbuf, \ - uint32_t buflen, TRANSFER_BLOCK_Type flag) -{ - uint32_t bToRecv, bRecv, timeOut; - uint8_t *pChar = rxbuf; - - bToRecv = buflen; - - // Blocking mode - if (flag == BLOCKING) { - bRecv = 0; - while (bToRecv){ - timeOut = UART_BLOCKING_TIMEOUT; - while (!(UARTx->LSR & UART_LSR_RDR)){ - if (timeOut == 0) break; - timeOut--; - } - // Time out! - if(timeOut == 0) break; - // Get data from the buffer - (*pChar++) = UART_ReceiveByte(UARTx); - bToRecv--; - bRecv++; - } - } - // None blocking mode - else { - bRecv = 0; - while (bToRecv) { - if (!(UARTx->LSR & UART_LSR_RDR)) { - break; - } else { - (*pChar++) = UART_ReceiveByte(UARTx); - bRecv++; - bToRecv--; - } - } - } - return bRecv; -} - -/*********************************************************************//** - * @brief Force BREAK character on UART line, output pin UARTx TXD is - forced to logic 0. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @return None - **********************************************************************/ -void UART_ForceBreak(LPC_USARTn_Type* UARTx) -{ - CHECK_PARAM(PARAM_UARTx(UARTx)); - - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->LCR |= UART_LCR_BREAK_EN; - } - else - { - UARTx->LCR |= UART_LCR_BREAK_EN; - } -} - - -/********************************************************************//** - * @brief Enable or disable specified UART interrupt. - * @param[in] UARTx UART peripheral selected, should be - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] UARTIntCfg Specifies the interrupt flag, - * should be one of the following: - * - UART_INTCFG_RBR :RBR Interrupt enable - * - UART_INTCFG_THRE :THR Interrupt enable - * - UART_INTCFG_RLS :RX line status interrupt enable - * - UART1_INTCFG_MS :Modem status interrupt enable (UART1 only) - * - UART1_INTCFG_CTS :CTS1 signal transition interrupt enable (UART1 only) - * - UART_INTCFG_ABEO :Enables the end of auto-baud interrupt - * - UART_INTCFG_ABTO :Enables the auto-baud time-out interrupt - * @param[in] NewState New state of specified UART interrupt type, - * should be: - * - ENALBE :Enable this UART interrupt type. - * - DISALBE :Disable this UART interrupt type. - * @return None - *********************************************************************/ -void UART_IntConfig(LPC_USARTn_Type *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState) -{ - uint32_t tmp; - - CHECK_PARAM(PARAM_UARTx(UARTx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - switch(UARTIntCfg){ - case UART_INTCFG_RBR: - tmp = UART_IER_RBRINT_EN; - break; - case UART_INTCFG_THRE: - tmp = UART_IER_THREINT_EN; - break; - case UART_INTCFG_RLS: - tmp = UART_IER_RLSINT_EN; - break; - case UART1_INTCFG_MS: - tmp = UART1_IER_MSINT_EN; - break; - case UART1_INTCFG_CTS: - tmp = UART1_IER_CTSINT_EN; - break; - case UART_INTCFG_ABEO: - tmp = UART_IER_ABEOINT_EN; - break; - case UART_INTCFG_ABTO: - tmp = UART_IER_ABTOINT_EN; - break; - } - - if ((LPC_UART1_Type *) UARTx == LPC_UART1) - { - CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) || (PARAM_UART1_INTCFG(UARTIntCfg))); - } - else - { - CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg)); - } - - if (NewState == ENABLE) - { - if ((LPC_UART1_Type *) UARTx == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->/*DLIER.*/IER |= tmp; - } - else - { - UARTx->/*DLIER.*/IER |= tmp; - } - } - else - { - if ((LPC_UART1_Type *) UARTx == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->/*DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK; - } - else - { - UARTx->/*DLIER.*/IER &= (~tmp) & UART_IER_BITMASK; - } - } -} - - -/********************************************************************//** - * @brief Get current value of Line Status register in UART peripheral. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @return Current value of Line Status register in UART peripheral. - * Note: The return value of this function must be ANDed with each member in - * UART_LS_Type enumeration to determine current flag status - * corresponding to each Line status type. Because some flags in - * Line Status register will be cleared after reading, the next reading - * Line Status register could not be correct. So this function used to - * read Line status register in one time only, then the return value - * used to check all flags. - *********************************************************************/ -uint8_t UART_GetLineStatus(LPC_USARTn_Type* UARTx) -{ - CHECK_PARAM(PARAM_UARTx(UARTx)); - - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - return ((((LPC_UART1_Type *)LPC_UART1)->LSR) & UART_LSR_BITMASK); - } - else - { - return ((UARTx->LSR) & UART_LSR_BITMASK); - } -} - -/*********************************************************************//** - * @brief Check whether if UART is busy or not - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @return RESET if UART is not busy, otherwise return SET. - **********************************************************************/ -FlagStatus UART_CheckBusy(LPC_USARTn_Type *UARTx) -{ - if (UARTx->LSR & UART_LSR_TEMT){ - return RESET; - } else { - return SET; - } -} - - -/*********************************************************************//** - * @brief Configure FIFO function on selected UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that - * contains specified information about FIFO configuration - * @return none - **********************************************************************/ -void UART_FIFOConfig(LPC_USARTn_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg) -{ - uint8_t tmp = 0; - - CHECK_PARAM(PARAM_UARTx(UARTx)); - CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf)); - - tmp |= UART_FCR_FIFO_EN; - switch (FIFOCfg->FIFO_Level){ - case UART_FIFO_TRGLEV0: - tmp |= UART_FCR_TRG_LEV0; - break; - case UART_FIFO_TRGLEV1: - tmp |= UART_FCR_TRG_LEV1; - break; - case UART_FIFO_TRGLEV2: - tmp |= UART_FCR_TRG_LEV2; - break; - case UART_FIFO_TRGLEV3: - default: - tmp |= UART_FCR_TRG_LEV3; - break; - } - - if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) - { - tmp |= UART_FCR_TX_RS; - } - if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) - { - tmp |= UART_FCR_RX_RS; - } - if (FIFOCfg->FIFO_DMAMode == ENABLE) - { - tmp |= UART_FCR_DMAMODE_SEL; - } - - - //write to FIFO control register - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK; - } - else - { - UARTx->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK; - } -} - -/*****************************************************************************//** - * @brief Fills each UART_FIFOInitStruct member with its default value: - * - FIFO_DMAMode = DISABLE - * - FIFO_Level = UART_FIFO_TRGLEV0 - * - FIFO_ResetRxBuf = ENABLE - * - FIFO_ResetTxBuf = ENABLE - * - FIFO_State = ENABLE - * - * @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure - * which will be initialized. - * @return None - *******************************************************************************/ -void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct) -{ - UART_FIFOInitStruct->FIFO_DMAMode = DISABLE; - UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0; - UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE; - UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE; -} - - -/*********************************************************************//** - * @brief Start/Stop Auto Baudrate activity - * @param[in] UARTx UART peripheral selected, should be - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that - * contains specified information about UART auto baudrate configuration - * @param[in] NewState New State of Auto baudrate activity, should be: - * - ENABLE :Start this activity - * - DISABLE :Stop this activity - * Note: Auto-baudrate mode enable bit will be cleared once this mode - * completed. - * @return none - **********************************************************************/ -void UART_ABCmd(LPC_USARTn_Type *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ - FunctionalState NewState) -{ - uint32_t tmp; - - CHECK_PARAM(PARAM_UARTx(UARTx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - tmp = 0; - if (NewState == ENABLE) { - if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){ - tmp |= UART_ACR_MODE; - } - if (ABConfigStruct->AutoRestart == ENABLE){ - tmp |= UART_ACR_AUTO_RESTART; - } - } - - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - if (NewState == ENABLE) - { - // Clear DLL and DLM value - ((LPC_UART1_Type *)UARTx)->LCR |= UART_LCR_DLAB_EN; - ((LPC_UART1_Type *)UARTx)->DLL = 0; - ((LPC_UART1_Type *)UARTx)->DLM = 0; - ((LPC_UART1_Type *)UARTx)->LCR &= ~UART_LCR_DLAB_EN; - // FDR value must be reset to default value - ((LPC_UART1_Type *)UARTx)->FDR = 0x10; - ((LPC_UART1_Type *)UARTx)->ACR = UART_ACR_START | tmp; - } - else - { - ((LPC_UART1_Type *)UARTx)->ACR = 0; - } - } - else - { - if (NewState == ENABLE) - { - // Clear DLL and DLM value - UARTx->LCR |= UART_LCR_DLAB_EN; - UARTx->DLL = 0; - UARTx->DLM = 0; - UARTx->LCR &= ~UART_LCR_DLAB_EN; - // FDR value must be reset to default value - UARTx->FDR = 0x10; - UARTx->ACR = UART_ACR_START | tmp; - } - else - { - UARTx->ACR = 0; - } - } -} - - -/*********************************************************************//** - * @brief Enable/Disable transmission on UART TxD pin - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] NewState New State of Tx transmission function, should be: - * - ENABLE :Enable this function - - DISABLE :Disable this function - * @return none - **********************************************************************/ -void UART_TxCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_UARTx(UARTx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->TER |= UART1_TER_TXEN; - } - else - { - UARTx->TER |= UART0_2_3_TER_TXEN; - } - } - else - { - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->TER &= (~UART1_TER_TXEN) & UART1_TER_BITMASK; - } - else - { - UARTx->TER &= (~UART0_2_3_TER_TXEN) & UART0_2_3_TER_BITMASK; - } - } -} - -/* UART IrDA functions ---------------------------------------------------*/ - -#ifdef _UART3 - -/*********************************************************************//** - * @brief Enable or disable inverting serial input function of IrDA - * on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) - * @param[in] NewState New state of inverting serial input, should be: - * - ENABLE :Enable this function. - * - DISABLE :Disable this function. - * @return none - **********************************************************************/ -void UART_IrDAInvtInputCmd(LPC_USARTn_Type* UARTx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_UART_IrDA(UARTx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - UARTx->ICR |= UART_ICR_IRDAINV; - } - else if (NewState == DISABLE) - { - UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Enable or disable IrDA function on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) - * @param[in] NewState New state of IrDA function, should be: - * - ENABLE :Enable this function. - * - DISABLE :Disable this function. - * @return none - **********************************************************************/ -void UART_IrDACmd(LPC_USARTn_Type* UARTx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_UART_IrDA(UARTx)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - if (NewState == ENABLE) - { - UARTx->ICR |= UART_ICR_IRDAEN; - } - else - { - UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Configure Pulse divider for IrDA function on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) - * @param[in] PulseDiv Pulse Divider value from Peripheral clock, - * should be one of the following: - * - UART_IrDA_PULSEDIV2 :Pulse width = 2 * Tpclk - * - UART_IrDA_PULSEDIV4 :Pulse width = 4 * Tpclk - * - UART_IrDA_PULSEDIV8 :Pulse width = 8 * Tpclk - * - UART_IrDA_PULSEDIV16 :Pulse width = 16 * Tpclk - * - UART_IrDA_PULSEDIV32 :Pulse width = 32 * Tpclk - * - UART_IrDA_PULSEDIV64 :Pulse width = 64 * Tpclk - * - UART_IrDA_PULSEDIV128 :Pulse width = 128 * Tpclk - * - UART_IrDA_PULSEDIV256 :Pulse width = 256 * Tpclk - * @return None - **********************************************************************/ -void UART_IrDAPulseDivConfig(LPC_USARTn_Type *UARTx, UART_IrDA_PULSE_Type PulseDiv) -{ - uint32_t tmp, tmp1; - CHECK_PARAM(PARAM_UART_IrDA(UARTx)); - CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv)); - - tmp1 = UART_ICR_PULSEDIV(PulseDiv); - tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7)); - tmp |= tmp1 | UART_ICR_FIXPULSE_EN; - UARTx->ICR = tmp & UART_ICR_BITMASK; -} - -#endif - - -/* UART1 FullModem function ---------------------------------------------*/ - -#ifdef _UART1 - -/*********************************************************************//** - * @brief Force pin DTR/RTS corresponding to given state (Full modem mode) - * @param[in] UARTx LPC_UART1 (only) - * @param[in] Pin Pin that NewState will be applied to, should be: - * - UART1_MODEM_PIN_DTR :DTR pin. - * - UART1_MODEM_PIN_RTS :RTS pin. - * @param[in] NewState New State of DTR/RTS pin, should be: - * - INACTIVE :Force the pin to inactive signal. - - ACTIVE :Force the pin to active signal. - * @return none - **********************************************************************/ -void UART_FullModemForcePinState(LPC_UART1_Type *UARTx, UART_MODEM_PIN_Type Pin, \ - UART1_SignalState NewState) -{ - uint8_t tmp = 0; - - CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); - CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin)); - CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState)); - - switch (Pin){ - case UART1_MODEM_PIN_DTR: - tmp = UART1_MCR_DTR_CTRL; - break; - case UART1_MODEM_PIN_RTS: - tmp = UART1_MCR_RTS_CTRL; - break; - default: - break; - } - - if (NewState == ACTIVE){ - UARTx->MCR |= tmp; - } else { - UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Configure Full Modem mode for UART peripheral - * @param[in] UARTx LPC_UART1 (only) - * @param[in] Mode Full Modem mode, should be: - * - UART1_MODEM_MODE_LOOPBACK :Loop back mode. - * - UART1_MODEM_MODE_AUTO_RTS :Auto-RTS mode. - * - UART1_MODEM_MODE_AUTO_CTS :Auto-CTS mode. - * @param[in] NewState New State of this mode, should be: - * - ENABLE :Enable this mode. - - DISABLE :Disable this mode. - * @return none - **********************************************************************/ -void UART_FullModemConfigMode(LPC_UART1_Type *UARTx, UART_MODEM_MODE_Type Mode, \ - FunctionalState NewState) -{ - uint8_t tmp; - - CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); - CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); - - switch(Mode){ - case UART1_MODEM_MODE_LOOPBACK: - tmp = UART1_MCR_LOOPB_EN; - break; - case UART1_MODEM_MODE_AUTO_RTS: - tmp = UART1_MCR_AUTO_RTS_EN; - break; - case UART1_MODEM_MODE_AUTO_CTS: - tmp = UART1_MCR_AUTO_CTS_EN; - break; - default: - break; - } - - if (NewState == ENABLE) - { - UARTx->MCR |= tmp; - } - else - { - UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Get current status of modem status register - * @param[in] UARTx LPC_UART1 (only) - * @return Current value of modem status register - * Note: The return value of this function must be ANDed with each member - * UART_MODEM_STAT_type enumeration to determine current flag status - * corresponding to each modem flag status. Because some flags in - * modem status register will be cleared after reading, the next reading - * modem register could not be correct. So this function used to - * read modem status register in one time only, then the return value - * used to check all flags. - **********************************************************************/ -uint8_t UART_FullModemGetStatus(LPC_UART1_Type *UARTx) -{ - CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); - return ((UARTx->MSR) & UART1_MSR_BITMASK); -} - -#endif /* _UART1 */ -/* UART RS485 functions --------------------------------------------------------------*/ - -/*********************************************************************//** -* @brief Configure UART peripheral in RS485 mode according to the specified - * parameters in the RS485ConfigStruct. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] RS485ConfigStruct Pointer to a UART_RS485_CTRLCFG_Type structure - * that contains the configuration information for specified UART - * in RS485 mode. - * @return None - **********************************************************************/ -void UART_RS485Config(LPC_USARTn_Type *UARTx, UART_RS485_CTRLCFG_Type *RS485ConfigStruct) -{ - uint32_t tmp; - - CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State)); - CHECK_PARAM(PARAM_UART_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue)); - CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level)); - CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin)); - CHECK_PARAM(PARAM_UART_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State)); - CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State)); - - tmp = 0; - // If Auto Direction Control is enabled - This function is used in Master mode - if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE) - { - tmp |= UART_RS485CTRL_DCTRL_EN; - - // Set polar - if (RS485ConfigStruct->DirCtrlPol_Level == SET) - { - tmp |= UART_RS485CTRL_OINV_1; - } - - // Set pin according to - if (RS485ConfigStruct->DirCtrlPin == UART_RS485_DIRCTRL_DTR) - { - tmp |= UART_RS485CTRL_SEL_DTR; - } - - // Fill delay time - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->RS485DLY = RS485ConfigStruct->DelayValue & UART_RS485DLY_BITMASK; - } - else - { - UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART_RS485DLY_BITMASK; - } - } - - // MultiDrop mode is enable - if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE) - { - tmp |= UART_RS485CTRL_NMM_EN; - } - - // Auto Address Detect function - if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE) - { - tmp |= UART_RS485CTRL_AADEN; - // Fill Match Address - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->RS485ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART_RS485ADRMATCH_BITMASK; - } - else - { - UARTx->RS485ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART_RS485ADRMATCH_BITMASK; - } - } - - - // Receiver is disable - if (RS485ConfigStruct->Rx_State == DISABLE) - { - tmp |= UART_RS485CTRL_RX_DIS; - } - - // write back to RS485 control register - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->RS485CTRL = tmp & UART_RS485CTRL_BITMASK; - } - else - { - UARTx->RS485CTRL = tmp & UART_RS485CTRL_BITMASK; - } - - // Enable Parity function and leave parity in stick '0' parity as default - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - ((LPC_UART1_Type *)UARTx)->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN); - } - else - { - UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN); - } -} - -/*********************************************************************//** - * @brief Enable/Disable receiver in RS485 module in UART - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] NewState New State of command, should be: - * - ENABLE :Enable this function. - * - DISABLE :Disable this function. - * @return None - **********************************************************************/ -void UART_RS485ReceiverCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState) -{ - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - if (NewState == ENABLE){ - ((LPC_UART1_Type *)UARTx)->RS485CTRL &= ~UART_RS485CTRL_RX_DIS; - } else { - ((LPC_UART1_Type *)UARTx)->RS485CTRL |= UART_RS485CTRL_RX_DIS; - } - } - else - { - if (NewState == ENABLE){ - UARTx->RS485CTRL &= ~UART_RS485CTRL_RX_DIS; - } else { - UARTx->RS485CTRL |= UART_RS485CTRL_RX_DIS; - } - } -} - -/*********************************************************************//** - * @brief Send data on RS485 bus with specified parity stick value (9-bit mode). - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] pDatFrm Pointer to data frame. - * @param[in] size Size of data. - * @param[in] ParityStick Parity Stick value, should be 0 or 1. - * @return None - **********************************************************************/ -uint32_t UART_RS485Send(LPC_USARTn_Type *UARTx, uint8_t *pDatFrm, \ - uint32_t size, uint8_t ParityStick) -{ - uint8_t tmp, save; - uint32_t cnt; - if (((LPC_UART1_Type *)UARTx) == LPC_UART1) - { - if (ParityStick){ - save = tmp = ((LPC_UART1_Type *)UARTx)->LCR & UART_LCR_BITMASK; - tmp &= ~(UART_LCR_PARITY_EVEN); - ((LPC_UART1_Type *)UARTx)->LCR = tmp; - cnt = UART_Send((LPC_USARTn_Type *)UARTx, pDatFrm, size, BLOCKING); - while (!(((LPC_UART1_Type *)UARTx)->LSR & UART_LSR_TEMT)); - ((LPC_UART1_Type *)UARTx)->LCR = save; - } else { - cnt = UART_Send((LPC_USARTn_Type *)UARTx, pDatFrm, size, BLOCKING); - while (!(((LPC_UART1_Type *)UARTx)->LSR & UART_LSR_TEMT)); - } - } - else - { - if (ParityStick){ - save = tmp = UARTx->LCR & UART_LCR_BITMASK; - tmp &= ~(UART_LCR_PARITY_EVEN); - UARTx->LCR = tmp; - cnt = UART_Send((LPC_USARTn_Type *)UARTx, pDatFrm, size, BLOCKING); - while (!(UARTx->LSR & UART_LSR_TEMT)); - UARTx->LCR = save; - } else { - cnt = UART_Send((LPC_USARTn_Type *)UARTx, pDatFrm, size, BLOCKING); - while (!(UARTx->LSR & UART_LSR_TEMT)); - } - } - return cnt; -} - -/*********************************************************************//** - * @brief Send Slave address frames on RS485 bus. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] SlvAddr Slave Address. - * @return None - **********************************************************************/ -void UART_RS485SendSlvAddr(LPC_USARTn_Type *UARTx, uint8_t SlvAddr) -{ - UART_RS485Send(UARTx, &SlvAddr, 1, 1); -} - -/*********************************************************************//** - * @brief Send Data frames on RS485 bus. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0 :UART0 peripheral - * - LPC_UART1 :UART1 peripheral - * - LPC_UART2 :UART2 peripheral - * - LPC_UART3 :UART3 peripheral - * @param[in] pData Pointer to data to be sent. - * @param[in] size Size of data frame to be sent. - * @return None - **********************************************************************/ -uint32_t UART_RS485SendData(LPC_USARTn_Type *UARTx, uint8_t *pData, uint32_t size) -{ - return (UART_RS485Send(UARTx, pData, size, 0)); -} - - -#endif /* _UART */ - -/** - * @} - */ - -/** - * @} - */ -/* --------------------------------- End Of File ------------------------------ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_utils.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_utils.c deleted file mode 100644 index bb9414be8..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_utils.c +++ /dev/null @@ -1,79 +0,0 @@ -#include "lpc18xx_utils.h" -#include "lpc18xx_timer.h" - -//timer init -TIM_TIMERCFG_Type TIM_ConfigStruct; -TIM_MATCHCFG_Type TIM_MatchConfigStruct; - - -/*********************************************************************//** - * @brief Main TIMER program body - * @param[in] None - * @return int - **********************************************************************/ -int timer_delay_us( int cnt) -{ - - // Initialize timer 0, prescale count time of 1uS - TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL; - TIM_ConfigStruct.PrescaleValue = 20; - - // use channel 0, MR0 - TIM_MatchConfigStruct.MatchChannel = 0; - // Disable interrupt when MR0 matches the value in TC register - TIM_MatchConfigStruct.IntOnMatch = TRUE; - //Enable reset on MR0: TIMER will reset if MR0 matches it - TIM_MatchConfigStruct.ResetOnMatch = TRUE; - //Stop on MR0 if MR0 matches it - TIM_MatchConfigStruct.StopOnMatch = TRUE; - - TIM_MatchConfigStruct.ExtMatchOutputType =TIM_EXTMATCH_NOTHING; - - TIM_MatchConfigStruct.MatchValue = cnt; - - // Set configuration for Tim_config and Tim_MatchConfig - TIM_Init(LPC_TIMER0, TIM_TIMER_MODE,&TIM_ConfigStruct); - TIM_ConfigMatch(LPC_TIMER0,&TIM_MatchConfigStruct); - TIM_Cmd(LPC_TIMER0,ENABLE); - - while ( !(TIM_GetIntStatus(LPC_TIMER0,TIM_MR0_INT))); - TIM_ClearIntPending(LPC_TIMER0,(TIM_INT_TYPE)0); - - return 0; -} - -/*********************************************************************//** - * @brief Main TIMER program body - * @param[in] None - * @return int - **********************************************************************/ -int timer_delay_ms( int cnt) -{ - - // Initialize timer 0, prescale count time of 1uS - TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL; - TIM_ConfigStruct.PrescaleValue = 1000; - - // use channel 0, MR0 - TIM_MatchConfigStruct.MatchChannel = 1; - // Disable interrupt when MR0 matches the value in TC register - TIM_MatchConfigStruct.IntOnMatch = TRUE; - //Enable reset on MR0: TIMER will reset if MR0 matches it - TIM_MatchConfigStruct.ResetOnMatch = TRUE; - //Stop on MR0 if MR0 matches it - TIM_MatchConfigStruct.StopOnMatch = TRUE; - - TIM_MatchConfigStruct.ExtMatchOutputType =TIM_EXTMATCH_NOTHING; - - TIM_MatchConfigStruct.MatchValue = cnt; - - // Set configuration for Tim_config and Tim_MatchConfig - TIM_Init(LPC_TIMER1, TIM_TIMER_MODE,&TIM_ConfigStruct); - TIM_ConfigMatch(LPC_TIMER1,&TIM_MatchConfigStruct); - TIM_Cmd(LPC_TIMER1,ENABLE); - - while ( !(TIM_GetIntStatus(LPC_TIMER1,TIM_MR1_INT))); - TIM_ClearIntPending(LPC_TIMER1,(TIM_INT_TYPE)1); - - return 0; -} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_wwdt.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_wwdt.c deleted file mode 100644 index 737cf2240..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_wwdt.c +++ /dev/null @@ -1,268 +0,0 @@ -/********************************************************************** -* $Id$ lpc18xx_wwdt.c 2011-06-02 -*//** -* @file lpc18xx_wwdt.c -* @brief Contains all functions support for WDT firmware library -* on LPC18xx -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup WWDT - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc18xx_wwdt.h" - -/* If this source file built with example, the LPC18xx FW library configuration - * file in each example directory ("lpc18xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc18xx_libcfg.h" -#else -#include "lpc18xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - - -#ifdef _WWDT - -void WWDT_SetTimeOut(uint32_t timeout); - -/*********************************************************************//** - * @brief Update WDT timeout value and feed - * @param[in] timeout WDT timeout (us) - * @return none - **********************************************************************/ -void WWDT_SetTimeOut(uint32_t timeout) -{ - uint32_t timeoutVal; - - timeoutVal = WDT_GET_FROM_USEC(timeout); - - if(timeoutVal < WWDT_TIMEOUT_MIN) - { - timeoutVal = WWDT_TIMEOUT_MIN; - } - else if (timeoutVal > WWDT_TIMEOUT_MAX) - { - timeoutVal = WWDT_TIMEOUT_MAX; - } - - LPC_WWDT->TC = timeoutVal; -} -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup WDT_Public_Functions - * @{ - */ - -/*********************************************************************//** -* @brief Initial for Watchdog function -* @param[in] none -* @return None - **********************************************************************/ -void WWDT_Init(void) -{ - LPC_WWDT->MOD = 0; // Clear time out and interrupt flags - LPC_WWDT->TC = WWDT_TIMEOUT_MIN; // Reset time out - LPC_WWDT->WARNINT= 0; // Reset warning value - LPC_WWDT->WINDOW = WWDT_WINDOW_MAX; // Reset window value -} - -/********************************************************************//** - * @brief Update WDT timeout value and feed - * @param[in] TimeOut TimeOut value to be updated, should be in range: - * 2048 .. 134217728 - * @return None - *********************************************************************/ -void WDT_UpdateTimeOut(uint32_t TimeOut) -{ - /* check WDPROTECT, - * if it is enable, wait until the counter is below the value of - * WDWARNINT and WDWINDOW - */ - if(LPC_WWDT->MOD & (1<<4)) - { - while((LPC_WWDT->TV <(LPC_WWDT->WARNINT & WWDT_WDWARNINT_MASK))\ - &&(LPC_WWDT->TV <(LPC_WWDT->WINDOW & WWDT_WDTC_MASK))); - } - - WWDT_SetTimeOut(TimeOut); -} -/********************************************************************//** - * @brief After set WDTEN, call this function to start Watchdog - * or reload the Watchdog timer - * @param[in] None - * @return None - *********************************************************************/ -void WWDT_Feed (void) -{ - LPC_WWDT->FEED = 0xAA; - - LPC_WWDT->FEED = 0x55; -} - -/********************************************************************//** - * @brief Update WDT timeout value and feed - * @param[in] WarnTime time to generate watchdog warning interrupt(us) - * should be in range: 2048 .. 8192 - * @return None - *********************************************************************/ -void WWDT_SetWarning(uint32_t WarnTime) -{ - uint32_t warnVal; - - warnVal = WDT_GET_FROM_USEC(WarnTime); - - if(warnVal <= WWDT_WARNINT_MIN) - { - warnVal = WWDT_WARNINT_MIN; - } - else if (warnVal >= WWDT_WARNINT_MAX) - { - warnVal = WWDT_WARNINT_MAX; - } - - LPC_WWDT->WARNINT = warnVal; -} - -/********************************************************************//** - * @brief Update WDT timeout value and feed - * @param[in] WindowedTime expected time to set watchdog window event(us) - * @return none - *********************************************************************/ -void WWDT_SetWindow(uint32_t WindowedTime) -{ - uint32_t wndVal; - - wndVal = WDT_GET_FROM_USEC(WindowedTime); - - if(wndVal <= WWDT_WINDOW_MIN) - { - wndVal = WWDT_WINDOW_MIN; - } - else if (wndVal >= WWDT_WINDOW_MAX) - { - wndVal = WWDT_WINDOW_MAX; - } - - LPC_WWDT->WINDOW = wndVal; -} -/*********************************************************************//** -* @brief Enable/Disable WWDT activity -* @param[in] None -* @return None - **********************************************************************/ -void WWDT_Configure(st_Wdt_Config wdtCfg) -{ - WWDT_SetTimeOut(wdtCfg.wdtTmrConst); - - if(wdtCfg.wdtReset) - { - LPC_WWDT->MOD |= WWDT_WDMOD_WDRESET; - } - else - { - LPC_WWDT->MOD &= ~WWDT_WDMOD_WDRESET; - } - - if(wdtCfg.wdtProtect) - { - LPC_WWDT->MOD |= WWDT_WDMOD_WDPROTECT; - } - else - { - LPC_WWDT->MOD &= ~WWDT_WDMOD_WDPROTECT; - } -} - -/*********************************************************************//** -* @brief Enable WWDT activity -* @param[in] None -* @return None - **********************************************************************/ -void WWDT_Start(void) -{ - LPC_WWDT->MOD |= WWDT_WDMOD_WDEN; - WWDT_Feed(); -} - -/********************************************************************//** - * @brief Read WWDT status flag - * @param[in] Status kind of status flag that you want to get, should be: - * - WWDT_WARNINT_FLAG: watchdog interrupt flag - * - WWDT_TIMEOUT_FLAG: watchdog time-out flag - * @return Time out flag status of WDT - *********************************************************************/ -FlagStatus WWDT_GetStatus (uint8_t Status) -{ - if(Status == WWDT_WARNINT_FLAG) - { - return ((FlagStatus)(LPC_WWDT->MOD & (1<<3))); - } - else if (Status == WWDT_TIMEOUT_FLAG) - { - return ((FlagStatus)(LPC_WWDT->MOD & (1<<2))); - } - return (FlagStatus)RESET; -} - -/********************************************************************//** - * @brief Read WWDT status flag - * @param[in] Status kind of status flag that you want to get, should be: - * - WWDT_WARNINT_FLAG: watchdog interrupt flag - * - WWDT_TIMEOUT_FLAG: watchdog time-out flag - * @return Time out flag status of WDT - *********************************************************************/ -void WWDT_ClearStatusFlag (uint8_t flag) -{ - if(flag == WWDT_WARNINT_FLAG) - { - // Write 1 to this bit to clear itself - LPC_WWDT->MOD |= WWDT_WDMOD_WDINT; - } - else if(flag == WWDT_TIMEOUT_FLAG) - { - // Write 0 to this bit to clear itself - LPC_WWDT->MOD &= ~ WWDT_WDMOD_WDTOF; - } -} - -/********************************************************************//** - * @brief Get the current value of WDT - * @param[in] None - * @return current value of WDT - *********************************************************************/ -uint32_t WWDT_GetCurrentCount(void) -{ - return LPC_WWDT->TV; -} - -/** - * @} - */ - -#endif /* _WWDT */ -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/system_LPC18xx.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/system_LPC18xx.c deleted file mode 100644 index 65d8574aa..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/system_LPC18xx.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Modifications for use with Code Red's toolchain - 2011/11/24 - */ -/********************************************************************** -* $Id$ system_LPC18xx.c 2011-06-02 -*//** -* @file system_LPC18xx.c -* @brief Cortex-M3 Device System Source File for NXP LPC18xx Series. -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#include "LPC18xx.h" -#include "lpc18xx_cgu.h" -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __IRC (12000000UL) /* IRC Oscillator frequency */ - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __IRC * 10UL; /*!< System Clock Frequency (Core Clock)*/ - -#ifndef __CODE_RED -extern uint32_t getPC(void); -#endif - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ -#ifdef __CODE_RED - // CodeRed startup code will modify VTOR register to match - // when code has been linked to run from. - - // Check whether we are running from external flash - if (SCB->VTOR == 0x1C000000) - /*Enable Buffer for External Flash*/ - LPC_EMC->STATICCONFIG0 |= 1<<19; - - // Call clock initialisation code - CGU_Init(); - -#else - // Enable VTOR register to point to vector table - SCB->VTOR = getPC() & 0xFFF00000; - /*Enable Buffer for External Flash*/ - LPC_EMC->STATICCONFIG0 |= 1<<19; - -#endif - -} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/cdcuser.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/cdcuser.c deleted file mode 100644 index b30c36225..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/cdcuser.c +++ /dev/null @@ -1,264 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: cdcuser.c - * Purpose: USB Communication Device Class User module - * Version: V1.10 - *---------------------------------------------------------------------------- -* This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include "lpc_types.h" - -#include "usb.h" -#include "usbhw.h" -#include "usbcfg.h" -#include "usbcore.h" -#include "cdc.h" -#include "cdcuser.h" - -#ifdef __ICCARM__ -#pragma data_alignment=4 -#define __align(x) -#elif defined ( __GNUC__ ) -#define __align(x) __attribute__((aligned(x))) -#endif - -unsigned char __align(4) BulkBufOut [USB_CDC_BUFSIZE]; // Buffer to store USB OUT packet - -#ifdef __ICCARM__ -#undef __align(x) -#endif - -/*---------------------------------------------------------------------------- - We need a buffer for incomming data on USB port because USB receives - much faster than UART transmits - *---------------------------------------------------------------------------*/ -/* Buffer masks */ -#define CDC_BUF_SIZE (64) // Output buffer in bytes (power 2) - // large enough for file transfer -#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul) - -/* Buffer read / write macros */ -#define CDC_BUF_RESET(cdcBuf) (cdcBuf.rdIdx = cdcBuf.wrIdx = 0) -#define CDC_BUF_WR(cdcBuf, dataIn) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.wrIdx++] = (dataIn)) -#define CDC_BUF_RD(cdcBuf) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.rdIdx++]) -#define CDC_BUF_EMPTY(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx) -#define CDC_BUF_FULL(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx+1) -#define CDC_BUF_COUNT(cdcBuf) (CDC_BUF_MASK & (cdcBuf.wrIdx - cdcBuf.rdIdx)) - - -// CDC output buffer -typedef struct __CDC_BUF_T { - unsigned char data[CDC_BUF_SIZE]; - unsigned int wrIdx; - unsigned int rdIdx; -} CDC_BUF_T; - -CDC_BUF_T CDC_OutBuf; // buffer for all CDC Out data - -/*---------------------------------------------------------------------------- - read data from CDC_OutBuf - *---------------------------------------------------------------------------*/ -int CDC_RdOutBuf (char *buffer, const int *length) { - int bytesToRead, bytesRead; - - /* Read *length bytes, block if *bytes are not avaialable */ - bytesToRead = *length; - bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length); - bytesRead = bytesToRead; - - // ... add code to check for underrun - - while (bytesToRead--) { - *buffer++ = CDC_BUF_RD(CDC_OutBuf); - } - return (bytesRead); -} - -/*---------------------------------------------------------------------------- - write data to CDC_OutBuf - *---------------------------------------------------------------------------*/ -int CDC_WrOutBuf (const char *buffer, int length) { - int bytesWritten; - - // ... add code to check for overwrite - - for( bytesWritten = 0; bytesWritten < length; bytesWritten++ ) { - CDC_BUF_WR(CDC_OutBuf, *buffer++); // Copy Data to buffer - } - - return (bytesWritten); -} - -/*---------------------------------------------------------------------------- - check if character(s) are available at CDC_OutBuf - *---------------------------------------------------------------------------*/ -int CDC_OutBufAvailChar (int *availChar) { - - *availChar = CDC_BUF_COUNT(CDC_OutBuf); - - return (0); -} -/* end Buffer handling */ - - - -/*---------------------------------------------------------------------------- - CDC SendEncapsulatedCommand Request Callback - Called automatically on CDC SEND_ENCAPSULATED_COMMAND Request - Parameters: None (global SetupPacket and EP0Buf) - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SendEncapsulatedCommand (void) { - - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC GetEncapsulatedResponse Request Callback - Called automatically on CDC Get_ENCAPSULATED_RESPONSE Request - Parameters: None (global SetupPacket and EP0Buf) - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_GetEncapsulatedResponse (void) { - - /* ... add code to handle request */ - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC SetCommFeature Request Callback - Called automatically on CDC Set_COMM_FATURE Request - Parameters: FeatureSelector - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector) { - - /* ... add code to handle request */ - ( void ) wFeatureSelector; - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC GetCommFeature Request Callback - Called automatically on CDC Get_COMM_FATURE Request - Parameters: FeatureSelector - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector) { - - /* ... add code to handle request */ - ( void ) wFeatureSelector; - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC ClearCommFeature Request Callback - Called automatically on CDC CLEAR_COMM_FATURE Request - Parameters: FeatureSelector - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector) { - - /* ... add code to handle request */ - ( void ) wFeatureSelector; - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC SetLineCoding Request Callback - Called automatically on CDC SET_LINE_CODING Request - Parameters: none (global SetupPacket and EP0Buf) - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SetLineCoding (void) { - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC GetLineCoding Request Callback - Called automatically on CDC GET_LINE_CODING Request - Parameters: None (global SetupPacket and EP0Buf) - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_GetLineCoding (void) { - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC SetControlLineState Request Callback - Called automatically on CDC SET_CONTROL_LINE_STATE Request - Parameters: ControlSignalBitmap - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap) { - - /* ... add code to handle request */ - ( void ) wControlSignalBitmap; - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC SendBreak Request Callback - Called automatically on CDC Set_COMM_FATURE Request - Parameters: 0xFFFF start of Break - 0x0000 stop of Break - 0x#### Duration of Break - Return Value: TRUE - Success, FALSE - Error - *---------------------------------------------------------------------------*/ -uint32_t CDC_SendBreak (unsigned short wDurationOfBreak) { - - /* ... add code to handle request */ - ( void ) wDurationOfBreak; - return (TRUE); -} - - -/*---------------------------------------------------------------------------- - CDC_BulkIn call on DataIn Request - Parameters: none - Return Value: none - *---------------------------------------------------------------------------*/ -void CDC_BulkIn(void) { -} - - -/*---------------------------------------------------------------------------- - CDC_BulkOut call on DataOut Request - Parameters: none - Return Value: none - *---------------------------------------------------------------------------*/ -void CDC_BulkOut(void) { - int numBytesRead; - - // get data from USB into intermediate buffer - numBytesRead = USB_ReadEP(CDC_DEP_OUT, &BulkBufOut[0]); - - // ... add code to check for overwrite - - // store data in a buffer to transmit it over serial interface - CDC_WrOutBuf ((char *)&BulkBufOut[0], numBytesRead); - vCDCNewDataNotify(); -} - -void CDC_BulkOutNak(void){ - - USB_ReadReqEP(CDC_DEP_OUT, &BulkBufOut[0], 64); -} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdc.h deleted file mode 100644 index 7bb2abf35..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdc.h +++ /dev/null @@ -1,283 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: CDC.h - * Purpose: USB Communication Device Class Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC family microcontroller devices only. Nothing - * else gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __CDC_H -#define __CDC_H -#include "lpc_types.h" - -#if defined ( __GNUC__ ) -#define __packed __attribute__((__packed__)) -#endif -/*---------------------------------------------------------------------------- - * Definitions based on usbcdc11.pdf (www.usb.org) - *---------------------------------------------------------------------------*/ -// Communication device class specification version 1.10 -#define CDC_V1_10 0x0110 - -// Communication interface class code -// (usbcdc11.pdf, 4.2, Table 15) -#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02 - -// Communication interface class subclass codes -// (usbcdc11.pdf, 4.3, Table 16) -#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01 -#define CDC_ABSTRACT_CONTROL_MODEL 0x02 -#define CDC_TELEPHONE_CONTROL_MODEL 0x03 -#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04 -#define CDC_CAPI_CONTROL_MODEL 0x05 -#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06 -#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07 - -// Communication interface class control protocol codes -// (usbcdc11.pdf, 4.4, Table 17) -#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01 - -// Data interface class code -// (usbcdc11.pdf, 4.5, Table 18) -#define CDC_DATA_INTERFACE_CLASS 0x0A - -// Data interface class protocol codes -// (usbcdc11.pdf, 4.7, Table 19) -#define CDC_PROTOCOL_ISDN_BRI 0x30 -#define CDC_PROTOCOL_HDLC 0x31 -#define CDC_PROTOCOL_TRANSPARENT 0x32 -#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50 -#define CDC_PROTOCOL_Q921_DATA_LINK 0x51 -#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52 -#define CDC_PROTOCOL_V42 0x90 -#define CDC_PROTOCOL_EURO_ISDN 0x91 -#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92 -#define CDC_PROTOCOL_CAPI 0x93 -#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD -#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE - -// Type values for bDescriptorType field of functional descriptors -// (usbcdc11.pdf, 5.2.3, Table 24) -#define CDC_CS_INTERFACE 0x24 -#define CDC_CS_ENDPOINT 0x25 - -// Type values for bDescriptorSubtype field of functional descriptors -// (usbcdc11.pdf, 5.2.3, Table 25) -#define CDC_HEADER 0x00 -#define CDC_CALL_MANAGEMENT 0x01 -#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02 -#define CDC_DIRECT_LINE_MANAGEMENT 0x03 -#define CDC_TELEPHONE_RINGER 0x04 -#define CDC_REPORTING_CAPABILITIES 0x05 -#define CDC_UNION 0x06 -#define CDC_COUNTRY_SELECTION 0x07 -#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08 -#define CDC_USB_TERMINAL 0x09 -#define CDC_NETWORK_CHANNEL 0x0A -#define CDC_PROTOCOL_UNIT 0x0B -#define CDC_EXTENSION_UNIT 0x0C -#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D -#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E -#define CDC_ETHERNET_NETWORKING 0x0F -#define CDC_ATM_NETWORKING 0x10 - -// CDC class-specific request codes -// (usbcdc11.pdf, 6.2, Table 46) -// see Table 45 for info about the specific requests. -#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define CDC_SET_COMM_FEATURE 0x02 -#define CDC_GET_COMM_FEATURE 0x03 -#define CDC_CLEAR_COMM_FEATURE 0x04 -#define CDC_SET_AUX_LINE_STATE 0x10 -#define CDC_SET_HOOK_STATE 0x11 -#define CDC_PULSE_SETUP 0x12 -#define CDC_SEND_PULSE 0x13 -#define CDC_SET_PULSE_TIME 0x14 -#define CDC_RING_AUX_JACK 0x15 -#define CDC_SET_LINE_CODING 0x20 -#define CDC_GET_LINE_CODING 0x21 -#define CDC_SET_CONTROL_LINE_STATE 0x22 -#define CDC_SEND_BREAK 0x23 -#define CDC_SET_RINGER_PARMS 0x30 -#define CDC_GET_RINGER_PARMS 0x31 -#define CDC_SET_OPERATION_PARMS 0x32 -#define CDC_GET_OPERATION_PARMS 0x33 -#define CDC_SET_LINE_PARMS 0x34 -#define CDC_GET_LINE_PARMS 0x35 -#define CDC_DIAL_DIGITS 0x36 -#define CDC_SET_UNIT_PARAMETER 0x37 -#define CDC_GET_UNIT_PARAMETER 0x38 -#define CDC_CLEAR_UNIT_PARAMETER 0x39 -#define CDC_GET_PROFILE 0x3A -#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 -#define CDC_SET_ETHERNET_PMP_FILTER 0x41 -#define CDC_GET_ETHERNET_PMP_FILTER 0x42 -#define CDC_SET_ETHERNET_PACKET_FILTER 0x43 -#define CDC_GET_ETHERNET_STATISTIC 0x44 -#define CDC_SET_ATM_DATA_FORMAT 0x50 -#define CDC_GET_ATM_DEVICE_STATISTICS 0x51 -#define CDC_SET_ATM_DEFAULT_VC 0x52 -#define CDC_GET_ATM_VC_STATISTICS 0x53 - -// Communication feature selector codes -// (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) -#define CDC_ABSTRACT_STATE 0x01 -#define CDC_COUNTRY_SETTING 0x02 - -// Feature Status returned for ABSTRACT_STATE Selector -// (usbcdc11.pdf, 6.2.3, Table 48) -#define CDC_IDLE_SETTING (1 << 0) -#define CDC_DATA_MULTPLEXED_STATE (1 << 1) - - -// Control signal bitmap values for the SetControlLineState request -// (usbcdc11.pdf, 6.2.14, Table 51) -#define CDC_DTE_PRESENT (1 << 0) -#define CDC_ACTIVATE_CARRIER (1 << 1) - -// CDC class-specific notification codes -// (usbcdc11.pdf, 6.3, Table 68) -// see Table 67 for Info about class-specific notifications -#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 -#define CDC_RESPONSE_AVAILABLE 0x01 -#define CDC_AUX_JACK_HOOK_STATE 0x08 -#define CDC_RING_DETECT 0x09 -#define CDC_NOTIFICATION_SERIAL_STATE 0x20 -#define CDC_CALL_STATE_CHANGE 0x28 -#define CDC_LINE_STATE_CHANGE 0x29 -#define CDC_CONNECTION_SPEED_CHANGE 0x2A - -// UART state bitmap values (Serial state notification). -// (usbcdc11.pdf, 6.3.5, Table 69) -#define CDC_SERIAL_STATE_OVERRUN (1 << 6) // receive data overrun error has occurred -#define CDC_SERIAL_STATE_PARITY (1 << 5) // parity error has occurred -#define CDC_SERIAL_STATE_FRAMING (1 << 4) // framing error has occurred -#define CDC_SERIAL_STATE_RING (1 << 3) // state of ring signal detection -#define CDC_SERIAL_STATE_BREAK (1 << 2) // state of break detection -#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) // state of transmission carrier -#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) // state of receiver carrier - - -/*---------------------------------------------------------------------------- - * Structures based on usbcdc11.pdf (www.usb.org) - *---------------------------------------------------------------------------*/ - -// Header functional descriptor -// (usbcdc11.pdf, 5.2.3.1) -// This header must precede any list of class-specific descriptors. - -#if defined ( __CC_ARM ) -typedef __packed struct _CDC_HEADER_DESCRIPTOR{ -#elif defined ( __GNUC__ ) -typedef struct __packed _CDC_HEADER_DESCRIPTOR{ -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _CDC_HEADER_DESCRIPTOR { -#endif - uint8_t bFunctionLength; // size of this descriptor in bytes - uint8_t bDescriptorType; // CS_INTERFACE descriptor type - uint8_t bDescriptorSubtype; // Header functional descriptor subtype - uint16_t bcdCDC; // USB CDC specification release version -} CDC_HEADER_DESCRIPTOR; - -//Call management functional descriptor -// (usbcdc11.pdf, 5.2.3.2) -// Describes the processing of calls for the communication class interface. -#if defined ( __CC_ARM ) -typedef __packed struct _CDC_CALL_MANAGEMENT_DESCRIPTOR{ -#elif defined ( __GNUC__ ) -typedef struct __packed _CDC_CALL_MANAGEMENT_DESCRIPTOR{ -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR { -#endif - uint8_t bFunctionLength; // size of this descriptor in bytes - uint8_t bDescriptorType; // CS_INTERFACE descriptor type - uint8_t bDescriptorSubtype; // call management functional descriptor subtype - uint8_t bmCapabilities; // capabilities that this configuration supports - uint8_t bDataInterface; // interface number of the data class interface used for call management (optional) -} CDC_CALL_MANAGEMENT_DESCRIPTOR; - -// Abstract control management functional descriptor -// (usbcdc11.pdf, 5.2.3.3) -// Describes the command supported by the communication interface class with the Abstract Control Model subclass code. -#if defined ( __CC_ARM ) -typedef __packed struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{ -#elif defined ( __GNUC__ ) -typedef struct __packed _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{ -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR { -#endif - uint8_t bFunctionLength; // size of this descriptor in bytes - uint8_t bDescriptorType; // CS_INTERFACE descriptor type - uint8_t bDescriptorSubtype; // abstract control management functional descriptor subtype - uint8_t bmCapabilities; // capabilities supported by this configuration -} CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR; - -// Union functional descriptors -// (usbcdc11.pdf, 5.2.3.8) -// Describes the relationship between a group of interfaces that can be considered to form a functional unit. -#if defined ( __CC_ARM ) -typedef __packed struct _CDC_UNION_DESCRIPTOR{ -#elif defined ( __GNUC__ ) -typedef struct __packed _CDC_UNION_DESCRIPTOR{ -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _CDC_UNION_DESCRIPTOR { -#endif - uint8_t bFunctionLength; // size of this descriptor in bytes - uint8_t bDescriptorType; // CS_INTERFACE descriptor type - uint8_t bDescriptorSubtype; // union functional descriptor subtype - uint8_t bMasterInterface; // interface number designated as master -} CDC_UNION_DESCRIPTOR; - -// Union functional descriptors with one slave interface -// (usbcdc11.pdf, 5.2.3.8) -#if defined ( __CC_ARM ) -typedef __packed struct _CDC_UNION_1SLAVE_DESCRIPTOR{ -#elif defined ( __GNUC__ ) -typedef struct __packed _CDC_UNION_1SLAVE_DESCRIPTOR{ -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR { -#endif - CDC_UNION_DESCRIPTOR sUnion; // Union functional descriptor - uint8_t bSlaveInterfaces[1]; // Slave interface 0 -} CDC_UNION_1SLAVE_DESCRIPTOR; - -// Line coding structure -// Format of the data returned when a GetLineCoding request is received -// (usbcdc11.pdf, 6.2.13) -#if defined ( __CC_ARM ) -typedef __packed struct _CDC_LINE_CODING{ -#elif defined ( __GNUC__ ) -typedef struct __packed _CDC_LINE_CODING{ -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _CDC_LINE_CODING { -#endif - uint32_t dwDTERate; // Data terminal rate in bits per second - uint8_t bCharFormat; // Number of stop bits - uint8_t bParityType; // Parity bit type - uint8_t bDataBits; // Number of data bits -} CDC_LINE_CODING; - -// Notification header -// Data sent on the notification endpoint must follow this header. -// see USB_SETUP_PACKET in file usb.h -typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER; - -#endif /* __CDC_H */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdcuser.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdcuser.h deleted file mode 100644 index f624e7b4a..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdcuser.h +++ /dev/null @@ -1,68 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: cdcuser.h - * Purpose: USB Communication Device Class User module Definitions - * Version: V1.10 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __CDCUSER_H__ -#define __CDCUSER_H__ - -/* CDC buffer handling */ -extern int CDC_RdOutBuf (char *buffer, const int *length); -extern int CDC_WrOutBuf (const char *buffer, int length); -extern int CDC_OutBufAvailChar (int *availChar); -extern void CDC_WaitNewData ( void ); - - -/* CDC Data In/Out Endpoint Address */ -#define CDC_DEP_IN 0x82 -#define CDC_DEP_OUT 0x02 - -/* CDC Communication In Endpoint Address */ -#define CDC_CEP_IN 0x81 - -/* CDC Requests Callback Functions */ -extern uint32_t CDC_SendEncapsulatedCommand (void); -extern uint32_t CDC_GetEncapsulatedResponse (void); -extern uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector); -extern uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector); -extern uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector); -extern uint32_t CDC_GetLineCoding (void); -extern uint32_t CDC_SetLineCoding (void); -extern uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap); -extern uint32_t CDC_SendBreak (unsigned short wDurationOfBreak); - -/* CDC Bulk Callback Functions */ -extern void CDC_BulkIn (void); -extern void CDC_BulkOut (void); -extern void CDC_BulkOutNak (void); - -/* CDC Notification Callback Function */ -extern void CDC_NotificationIn (void); - -/* CDC Initializtion Function */ -extern void CDC_Init (char portNum); - -/* CDC prepare the SERAIAL_STATE */ -extern unsigned short CDC_GetSerialState (void); - -/* CDC New data Notification Function */ -extern void vCDCNewDataNotify(); - -/* flow control */ -extern unsigned short CDC_DepInEmpty; // DataEndPoint IN empty - -#endif /* __CDCUSER_H__ */ - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/lpc43xx_libcfg.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/lpc43xx_libcfg.h deleted file mode 100644 index cbfc0a2dc..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/lpc43xx_libcfg.h +++ /dev/null @@ -1,146 +0,0 @@ -/********************************************************************** -* $Id$ lpc43xx_libcfg.h 2011-06-02 -*//** -* @file lpc43xx_libcfg.h -* @brief Library configuration file -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#ifndef lpc43xx_LIBCFG_H_ -#define lpc43xx_LIBCFG_H_ - -#include "lpc_types.h" - - -/************************** DEBUG MODE DEFINITIONS *********************************/ -/* Un-comment the line below to compile the library in DEBUG mode, this will expanse - the "CHECK_PARAM" macro in the FW library code */ - -#define DEBUG - - -/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/ - -/* Comment the line below to disable the specific peripheral inclusion */ - -/* GPIO ------------------------------- */ -#define _GPIO - -/* EXTI ------------------------------- */ -//#define _EXTI - -/* UART ------------------------------- */ -#define _UART -#define _UART0 -#define _UART1 -#define _UART2 -#define _UART3 - -/* SPI ------------------------------- */ -//#define _SPI - -/* SSP ------------------------------- */ -//#define _SSP -//#define _SSP0 -//#define _SSP1 - -/* SYSTICK --------------------------- */ -//#define _SYSTICK - -/* I2C ------------------------------- */ -//#define _I2C -//#define _I2C0 -//#define _I2C1 -//#define _I2C2 - -/* TIMER ------------------------------- */ -//#define _TIM - -/* WDT ------------------------------- */ -//#define _WDT - - -/* GPDMA ------------------------------- */ -//#define _GPDMA - - -/* DAC ------------------------------- */ -//#define _DAC - -/* DAC ------------------------------- */ -//#define _ADC - - -/* PWM ------------------------------- */ -//#define _PWM -//#define _PWM1 - -/* RTC ------------------------------- */ -//#define _RTC - -/* I2S ------------------------------- */ -//#define _I2S - -/* USB device ------------------------------- */ -#define _USBDEV -//#define _USB_DMA - -/* QEI ------------------------------- */ -//#define _QEI - -/* MCPWM ------------------------------- */ -//#define _MCPWM - -/* CAN--------------------------------*/ -//#define _CAN - -/* RIT ------------------------------- */ -//#define _RIT - -/* EMAC ------------------------------ */ -//#define _EMAC - -/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/ - -#ifdef DEBUG -/******************************************************************************* -* @brief The CHECK_PARAM macro is used for function's parameters check. -* It is used only if the library is compiled in DEBUG mode. -* @param[in] expr - If expr is false, it calls check_failed() function -* which reports the name of the source file and the source -* line number of the call that failed. -* - If expr is true, it returns no value. -* @return None -*******************************************************************************/ -#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) -#else -#define CHECK_PARAM(expr) -#endif /* DEBUG */ - - - -/************************** GLOBAL/PUBLIC FUNCTION DECLARATION *********************************/ - -#ifdef DEBUG -void check_failed(uint8_t *file, uint32_t line); -#endif - - -#endif /* lpc43xx_LIBCFG_H_ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usb.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usb.h deleted file mode 100644 index 629a7a036..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usb.h +++ /dev/null @@ -1,422 +0,0 @@ -/********************************************************************** -* $Id$ usb.h 2011-06-02 -*//** -* @file usb.h -* @brief USB Definitions -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -#ifndef __USB_H__ -#define __USB_H__ - -#include "usbcfg.h" - -#ifdef USE_USB0 -#define LPC_USB LPC_USB0 // Use USB0 -#else -#define LPC_USB LPC_USB1 // Use USB1 -#endif -#if defined ( __GNUC__ ) -#define __packed __attribute__((__packed__)) -#endif - -#if defined ( __CC_ARM ) -typedef __packed union { -#elif defined ( __GNUC__ ) -typedef union __packed { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef union { -#endif - uint16_t W; -#if defined ( __CC_ARM ) - __packed struct { -#elif defined ( __GNUC__ ) - struct __packed { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) - struct { -#endif - uint8_t L; - uint8_t H; - } WB; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif -} WORD_BYTE; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - - -/* bmRequestType.Dir */ -#define REQUEST_HOST_TO_DEVICE 0 -#define REQUEST_DEVICE_TO_HOST 1 - -/* bmRequestType.Type */ -#define REQUEST_STANDARD 0 -#define REQUEST_CLASS 1 -#define REQUEST_VENDOR 2 -#define REQUEST_RESERVED 3 - -/* bmRequestType.Recipient */ -#define REQUEST_TO_DEVICE 0 -#define REQUEST_TO_INTERFACE 1 -#define REQUEST_TO_ENDPOINT 2 -#define REQUEST_TO_OTHER 3 - -/* bmRequestType Definition */ -#if defined ( __CC_ARM ) -typedef __packed union _REQUEST_TYPE { -#elif defined ( __GNUC__ ) -typedef union __packed _REQUEST_TYPE { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef union _REQUEST_TYPE { -#endif -#if defined ( __CC_ARM ) - __packed struct _BM { -#elif defined ( __GNUC__ ) - struct __packed _BM { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) - struct _BM { -#endif - uint8_t Recipient : 5; - uint8_t Type : 2; - uint8_t Dir : 1; - } BM; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - uint8_t B; -} REQUEST_TYPE; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - -/* USB Standard Request Codes */ -#define USB_REQUEST_GET_STATUS 0 -#define USB_REQUEST_CLEAR_FEATURE 1 -#define USB_REQUEST_SET_FEATURE 3 -#define USB_REQUEST_SET_ADDRESS 5 -#define USB_REQUEST_GET_DESCRIPTOR 6 -#define USB_REQUEST_SET_DESCRIPTOR 7 -#define USB_REQUEST_GET_CONFIGURATION 8 -#define USB_REQUEST_SET_CONFIGURATION 9 -#define USB_REQUEST_GET_INTERFACE 10 -#define USB_REQUEST_SET_INTERFACE 11 -#define USB_REQUEST_SYNC_FRAME 12 - -/* USB GET_STATUS Bit Values */ -#define USB_GETSTATUS_SELF_POWERED 0x01 -#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 -#define USB_GETSTATUS_ENDPOINT_STALL 0x01 - -/* USB Standard Feature selectors */ -#define USB_FEATURE_ENDPOINT_STALL 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -/* USB Default Control Pipe Setup Packet */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_SETUP_PACKET { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_SETUP_PACKET { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_SETUP_PACKET { -#endif - REQUEST_TYPE bmRequestType; - uint8_t bRequest; - WORD_BYTE wValue; - WORD_BYTE wIndex; - uint16_t wLength; -} USB_SETUP_PACKET; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - - -/* USB Descriptor Types */ -#define USB_DEVICE_DESCRIPTOR_TYPE 1 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2 -#define USB_STRING_DESCRIPTOR_TYPE 3 -#define USB_INTERFACE_DESCRIPTOR_TYPE 4 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 5 -#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6 -#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7 -#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8 -#define USB_OTG_DESCRIPTOR_TYPE 9 -#define USB_DEBUG_DESCRIPTOR_TYPE 10 -#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11 - -/* USB Device Classes */ -#define USB_DEVICE_CLASS_RESERVED 0x00 -#define USB_DEVICE_CLASS_AUDIO 0x01 -#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02 -#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03 -#define USB_DEVICE_CLASS_MONITOR 0x04 -#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05 -#define USB_DEVICE_CLASS_POWER 0x06 -#define USB_DEVICE_CLASS_PRINTER 0x07 -#define USB_DEVICE_CLASS_STORAGE 0x08 -#define USB_DEVICE_CLASS_HUB 0x09 -#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF -#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF - -/* bmAttributes in Configuration Descriptor */ -#define USB_CONFIG_POWERED_MASK 0x40 -#define USB_CONFIG_BUS_POWERED 0x80 -#define USB_CONFIG_SELF_POWERED 0xC0 -#define USB_CONFIG_REMOTE_WAKEUP 0x20 - -/* bMaxPower in Configuration Descriptor */ -#define USB_CONFIG_POWER_MA(mA) ((mA)/2) - -/* bEndpointAddress in Endpoint Descriptor */ -#define USB_ENDPOINT_DIRECTION_MASK 0x80 -#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) -#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) - -/* bmAttributes in Endpoint Descriptor */ -#define USB_ENDPOINT_TYPE_MASK 0x03 -#define USB_ENDPOINT_TYPE_CONTROL 0x00 -#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 -#define USB_ENDPOINT_TYPE_BULK 0x02 -#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 -#define USB_ENDPOINT_SYNC_MASK 0x0C -#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00 -#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04 -#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08 -#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C -#define USB_ENDPOINT_USAGE_MASK 0x30 -#define USB_ENDPOINT_USAGE_DATA 0x00 -#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 -#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20 -#define USB_ENDPOINT_USAGE_RESERVED 0x30 - -/* USB Standard Device Descriptor */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_DEVICE_DESCRIPTOR { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_DEVICE_DESCRIPTOR { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_DEVICE_DESCRIPTOR { -#endif - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint16_t idVendor; - uint16_t idProduct; - uint16_t bcdDevice; - uint8_t iManufacturer; - uint8_t iProduct; - uint8_t iSerialNumber; - uint8_t bNumConfigurations; -} USB_DEVICE_DESCRIPTOR; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - -/* USB 2.0 Device Qualifier Descriptor */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_DEVICE_QUALIFIER_DESCRIPTOR { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_DEVICE_QUALIFIER_DESCRIPTOR { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR { -#endif - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint8_t bNumConfigurations; - uint8_t bReserved; -} USB_DEVICE_QUALIFIER_DESCRIPTOR; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - -/* USB Standard Configuration Descriptor */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_CONFIGURATION_DESCRIPTOR { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_CONFIGURATION_DESCRIPTOR { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_CONFIGURATION_DESCRIPTOR { -#endif - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; -} USB_CONFIGURATION_DESCRIPTOR; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - -/* USB Standard Interface Descriptor */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_INTERFACE_DESCRIPTOR { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_INTERFACE_DESCRIPTOR { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_INTERFACE_DESCRIPTOR { -#endif - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; -} USB_INTERFACE_DESCRIPTOR; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - -/* USB Standard Endpoint Descriptor */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_ENDPOINT_DESCRIPTOR { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_ENDPOINT_DESCRIPTOR { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_ENDPOINT_DESCRIPTOR { -#endif - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; -} USB_ENDPOINT_DESCRIPTOR; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - -/* USB String Descriptor */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_STRING_DESCRIPTOR { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_STRING_DESCRIPTOR { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_STRING_DESCRIPTOR { -#endif - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bString/*[]*/; -} USB_STRING_DESCRIPTOR; -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - -/* USB Common Descriptor */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_COMMON_DESCRIPTOR { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_COMMON_DESCRIPTOR { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_COMMON_DESCRIPTOR { -#endif - uint8_t bLength; - uint8_t bDescriptorType; -} USB_COMMON_DESCRIPTOR; - -/* USB Other Speed Configuration */ -#if defined ( __CC_ARM ) -typedef __packed struct _USB_OTHER_SPEED_CONFIGURATION { -#elif defined ( __GNUC__ ) -typedef struct __packed _USB_OTHER_SPEED_CONFIGURATION { -#elif defined ( __IAR_SYSTEMS_ICC__ ) -#pragma pack(1) -typedef struct _USB_OTHER_SPEED_CONFIGURATION { -#endif - - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t IConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; -} USB_OTHER_SPEED_CONFIGURATION; - - -/* USB Endpoint Callback Events */ -#define USB_EVT_SETUP 1 /* Setup Packet */ -#define USB_EVT_OUT 2 /* OUT Packet */ -#define USB_EVT_IN 3 /* IN Packet */ -#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */ -#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */ -#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */ -#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */ -#define USB_EVT_OUT_DMA_EOT 8 /* DMA OUT EP - End of Transfer */ -#define USB_EVT_IN_DMA_EOT 9 /* DMA IN EP - End of Transfer */ -#define USB_EVT_OUT_DMA_NDR 10 /* DMA OUT EP - New Descriptor Request */ -#define USB_EVT_IN_DMA_NDR 11 /* DMA IN EP - New Descriptor Request */ -#define USB_EVT_OUT_DMA_ERR 12 /* DMA OUT EP - Error */ -#define USB_EVT_IN_DMA_ERR 13 /* DMA IN EP - Error */ - -/* call back structure */ -typedef struct _USB_INIT_ -{ - uint32_t ep0_maxp; - /* USB Device Events Callback Functions */ - void (* USB_Power_Event)(uint32_t power); - void (* USB_Reset_Event)(void); - void (* USB_Suspend_Event)(void); - void (* USB_Resume_Event)(void); - void (* USB_WakeUp_Event)(void); - void (* USB_SOF_Event)(void); - void (* USB_Error_Event)(uint32_t error); - /* USB Core Events Callback Functions */ - void (* USB_Configure_Event)(void); - void (* USB_Interface_Event)(void); - void (* USB_Feature_Event)(void); - /* USB Endpoint Events Callback Pointers */ - void (* USB_P_EP[4])(uint32_t event); -} LPC_USBDRV_INIT_T; - -#ifdef __IAR_SYSTEMS_ICC__ -#pragma pack() -#endif - -#endif /* __USB_H__ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcfg.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcfg.h deleted file mode 100644 index a47472e64..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcfg.h +++ /dev/null @@ -1,135 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbcfg.h - * Purpose: USB Custom Configuration - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC family microcontroller devices only. Nothing - * else gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Added vendor specific support - * V1.00 Initial Version - *----------------------------------------------------------------------------*/ - -#ifndef __USBCFG_H__ -#define __USBCFG_H__ - - -//*** <<< Use Configuration Wizard in Context Menu >>> *** - - -/* -// USB Configuration -// USB Power -// Default Power Setting -// <0=> Bus-powered -// <1=> Self-powered -// Max Number of Interfaces <1-256> -// Max Number of Endpoints <1-32> -// Max Endpoint 0 Packet Size -// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes -// -*/ - -#define USB_POWER 1 -#define USB_IF_NUM 1 -#define USB_EP_NUM 4 -#define USB_MAX_PACKET0 64 - - -/* -// USB Event Handlers -// Device Events -// Power Event -// Reset Event -// Suspend Event -// Resume Event -// Remote Wakeup Event -// Start of Frame Event -// Error Event -// -// Endpoint Events -// Endpoint 0 Event -// Endpoint 1 Event -// Endpoint 2 Event -// Endpoint 3 Event -// Endpoint 4 Event -// -// USB Core Events -// Set Configuration Event -// Set Interface Event -// Set/Clear Feature Event -// -// -*/ - -#define USB_POWER_EVENT 0 -#define USB_RESET_EVENT 1 -#define USB_SUSPEND_EVENT 1 -#define USB_RESUME_EVENT 1 -#define USB_WAKEUP_EVENT 0 -#define USB_SOF_EVENT 0 -#define USB_ERROR_EVENT 0 -#define USB_EP_EVENT 0x0007 -#define USB_CONFIGURE_EVENT 1 -#define USB_INTERFACE_EVENT 0 -#define USB_FEATURE_EVENT 0 - - -/* -// USB Class Support -// enables USB Class specific Requests -// Human Interface Device (HID) -// Interface Number <0-255> -// -// Mass Storage -// Interface Number <0-255> -// -// Audio Device -// Control Interface Number <0-255> -// Streaming Interface 1 Number <0-255> -// Streaming Interface 2 Number <0-255> -// -// Communication Device -// Control Interface Number <0-255> -// Bulk Interface Number <0-255> -// Max Communication Device Buffer Size -// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes -// -// -*/ - -#define USB_CLASS 1 -#define USB_HID 0 -#define USB_HID_IF_NUM 0 -#define USB_MSC 0 -#define USB_MSC_IF_NUM 0 -#define USB_AUDIO 0 -#define USB_ADC_CIF_NUM 0 -#define USB_ADC_SIF1_NUM 1 -#define USB_ADC_SIF2_NUM 2 -#define USB_CDC 1 -#define USB_CDC_CIF_NUM 0 -#define USB_CDC_DIF_NUM 1 -#define USB_CDC_BUFSIZE 64 - -/* -// USB Vendor Support -// enables USB Vendor specific Requests -// -*/ -#define USB_VENDOR 0 - -#define USE_USB0 - - -#endif /* __USBCFG_H__ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcore.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcore.h deleted file mode 100644 index b9d0a9198..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcore.h +++ /dev/null @@ -1,51 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbcore.h - * Purpose: USB Core Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __USBCORE_H__ -#define __USBCORE_H__ - - -/* USB Endpoint Data Structure */ -typedef struct _USB_EP_DATA { - uint8_t *pData; - uint16_t Count; -} USB_EP_DATA; - -/* USB Core Global Variables */ -extern uint16_t USB_DeviceStatus; -extern uint8_t USB_DeviceAddress; -extern uint8_t USB_Configuration; -extern uint32_t USB_EndPointMask; -extern uint32_t USB_EndPointHalt; -extern uint32_t USB_EndPointStall; -extern uint8_t USB_AltSetting[USB_IF_NUM]; - -/* USB Endpoint 0 Buffer */ -extern uint8_t EP0Buf[USB_MAX_PACKET0]; - -/* USB Endpoint 0 Data Info */ -extern USB_EP_DATA EP0Data; - -/* USB Setup Packet */ -extern USB_SETUP_PACKET SetupPacket; - -/* USB Core Functions */ -extern void USB_ResetCore (void); - - -#endif /* __USBCORE_H__ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbdesc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbdesc.h deleted file mode 100644 index 6f00e0fb2..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbdesc.h +++ /dev/null @@ -1,41 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbdesc.h - * Purpose: USB Descriptors Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __USBDESC_H__ -#define __USBDESC_H__ - - -#define WBVAL(x) (x & 0xFF),((x >> 8) & 0xFF) - -#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR)) -#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR)) -#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR)) -#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR)) -#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR)) -#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION)) - -extern const uint8_t USB_DeviceDescriptor[]; -extern const uint8_t USB_FSConfigDescriptor[]; -extern const uint8_t USB_HSConfigDescriptor[]; -extern const uint8_t USB_StringDescriptor[]; -extern const uint8_t USB_DeviceQualifier[]; -extern const uint8_t USB_FSOtherSpeedConfiguration[]; -extern const uint8_t USB_HSOtherSpeedConfiguration[]; - - -#endif /* __USBDESC_H__ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbhw.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbhw.h deleted file mode 100644 index e946a4a78..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbhw.h +++ /dev/null @@ -1,156 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbhw.h - * Purpose: USB Hardware Layer Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC family microcontroller devices only. Nothing - * else gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Added USB_ClearEPBuf - * V1.00 Initial Version - *----------------------------------------------------------------------------*/ - -#ifndef __USBHW_H__ -#define __USBHW_H__ -#include "usb.h" -/* dTD Transfer Description */ -typedef volatile struct -{ - volatile uint32_t next_dTD; - volatile uint32_t total_bytes ; - volatile uint32_t buffer0; - volatile uint32_t buffer1; - volatile uint32_t buffer2; - volatile uint32_t buffer3; - volatile uint32_t buffer4; - volatile uint32_t reserved; -} DTD_T; - -/* dQH Queue Head */ -typedef volatile struct -{ - volatile uint32_t cap; - volatile uint32_t curr_dTD; - volatile uint32_t next_dTD; - volatile uint32_t total_bytes; - volatile uint32_t buffer0; - volatile uint32_t buffer1; - volatile uint32_t buffer2; - volatile uint32_t buffer3; - volatile uint32_t buffer4; - volatile uint32_t reserved; - volatile uint32_t setup[2]; - volatile uint32_t gap[4]; -} DQH_T; - -/* bit defines for USBCMD register */ -#define USBCMD_RS (1<<0) -#define USBCMD_RST (1<<1) -#define USBCMD_ATDTW (1<<12) -#define USBCMD_SUTW (1<<13) - -/* bit defines for USBSTS register */ -#define USBSTS_UI (1<<0) -#define USBSTS_UEI (1<<1) -#define USBSTS_PCI (1<<2) -#define USBSTS_URI (1<<6) -#define USBSTS_SRI (1<<7) -#define USBSTS_SLI (1<<8) -#define USBSTS_NAKI (1<<16) - -/* bit defines for DEVICEADDR register */ -#define USBDEV_ADDR_AD (1<<24) -#define USBDEV_ADDR(n) (((n) & 0x7F)<<25) - -/* bit defines for PRTSC1 register */ -#define USBPRTS_CCS (1<<0) -#define USBPRTS_PE (1<<2) -#define USBPRTS_FPR (1<<6) -#define USBPRTS_SUSP (1<<7) -#define USBPRTS_PR (1<<8) -#define USBPRTS_HSP (1<<9) -#define USBPRTS_PLPSCD (1<<23) -#define USBPRTS_PFSC (1<<24) - -/* bit defines for USBMODE register */ -#define USBMODE_CM_IDLE (0x0<<0) -#define USBMODE_CM_DEV (0x2<<0) -#define USBMODE_CM_HOST (0x3<<0) -#define USBMODE_SLOM (1<<3) -#define USBMODE_SDIS (1<<4) - -/* bit defines for EP registers*/ -#define USB_EP_BITPOS(n) (((n) & 0x80)? (0x10 | ((n) & 0x7)) : ((n) & 0x7)) - -/* bit defines EPcontrol registers*/ -#define EPCTRL_RXS (1<<0) -#define EPCTRL_RX_TYPE(n) (((n) & 0x3)<<2) -#define EPCTRL_RX_CTL (0<<2) -#define EPCTRL_RX_ISO (1<<2) -#define EPCTRL_RX_BLK (2<<2) -#define EPCTRL_RXI (1<<5) -#define EPCTRL_RXR (1<<6) -#define EPCTRL_RXE (1<<7) -#define EPCTRL_TXS (1<<16) -#define EPCTRL_TX_TYPE(n) (((n) & 0x3)<<18) -#define EPCTRL_TX_CTL (0<<18) -#define EPCTRL_TX_ISO (1<<18) -#define EPCTRL_TX_BLK (2<<18) -#define EPCTRL_TX_INT (3<<18) -#define EPCTRL_TXI (1<<21) -#define EPCTRL_TXR (1<<22) -#define EPCTRL_TXE (1<<23) - -/* dQH field and bit defines */ -/* Temp fixed on max, should be taken out of table */ -#define QH_MAX_CTRL_PAYLOAD 0x03ff -#define QH_MAX_PKT_LEN_POS 16 -#define QH_MAXP(n) (((n) & 0x3FF)<<16) -#define QH_IOS (1<<15) -#define QH_ZLT (1<<29) - -/* dTD field and bit defines */ -#define TD_NEXT_TERMINATE (1<<0) -#define TD_IOC (1<<15) - -/* Total physical enpoints*/ -#define EP_NUM_MAX 8 - - -/* USB Hardware Functions */ -extern void USB_Init (LPC_USBDRV_INIT_T* cbs); -extern void USB_Connect (uint32_t con); -extern void USB_Reset (void); -extern void USB_Suspend (void); -extern void USB_Resume (void); -extern void USB_WakeUp (void); -extern void USB_WakeUpCfg (uint32_t cfg); -extern void USB_SetAddress (uint32_t adr); -extern void USB_Configure (uint32_t cfg); -extern void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD); -extern void USB_DirCtrlEP (uint32_t dir); -extern void USB_EnableEP (uint32_t EPNum); -extern void USB_DisableEP (uint32_t EPNum); -extern void USB_ResetEP (uint32_t EPNum); -extern void USB_SetStallEP (uint32_t EPNum); -extern void USB_ClrStallEP (uint32_t EPNum); -extern void USB_ClearEPBuf (uint32_t EPNum); -extern uint32_t USB_SetTestMode(uint8_t mode); -extern uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData); -extern uint32_t USB_ReadReqEP(uint32_t EPNum, uint8_t *pData, uint32_t len); -extern uint32_t USB_ReadSetupPkt(uint32_t, uint32_t *); -extern uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt); -extern uint32_t USB_GetFrame (void); -//extern void USB_ISR(void) __irq; - -#endif /* __USBHW_H__ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbuser.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbuser.h deleted file mode 100644 index 5f1479989..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbuser.h +++ /dev/null @@ -1,49 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbuser.h - * Purpose: USB Custom User Definitions - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC family microcontroller devices only. Nothing - * else gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#ifndef __USBUSER_H__ -#define __USBUSER_H__ - - -/* USB Device Events Callback Functions */ -extern void USB_Power_Event (uint32_t power); -extern void USB_Reset_Event (void); -extern void USB_Suspend_Event (void); -extern void USB_Resume_Event (void); -extern void USB_WakeUp_Event (void); -extern void USB_SOF_Event (void); -extern void USB_Error_Event (uint32_t error); - -/* USB Endpoint Events Callback Pointers */ -extern void (* const USB_P_EP[USB_EP_NUM])(uint32_t event); - -/* USB Endpoint Events Callback Functions */ -extern void USB_EndPoint0 (uint32_t event); -extern void USB_EndPoint1 (uint32_t event); -extern void USB_EndPoint2 (uint32_t event); -extern void USB_EndPoint3 (uint32_t event); -extern void USB_EndPoint4 (uint32_t event); -extern void USB_EndPoint5 (uint32_t event); - -/* USB Core Events Callback Functions */ -extern void USB_Configure_Event (void); -extern void USB_Interface_Event (void); -extern void USB_Feature_Event (void); - - -#endif /* __USBUSER_H__ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom-win7.inf b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom-win7.inf deleted file mode 100644 index 5778adbf7..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom-win7.inf +++ /dev/null @@ -1,60 +0,0 @@ -; -; Keil - An ARM Company Comunication Device Class driver installation file -; (C)2007 Copyright -; - -[Version] -Signature="$Windows NT$" -Class=Ports -ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} -Provider=%Keil% -LayoutFile=layout.inf -DriverVer=01/06/07 - -[Manufacturer] -%Keil%=DeviceList,NT,NTamd64 - -[DestinationDirs] -DefaultDestDir=12 - -[SourceDisksFiles] - -[SourceDisksNames] - -[DeviceList.NT] -%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002 -[DeviceList.NTamd64] -%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002 - -;------------------------------------------------------------------------------ -; Windows Sections -;------------------------------------------------------------------------------ - -[LPC18xxUSB.NT] -Include=mdmcpq.inf -CopyFiles=FakeModemCopyFileSection -AddReg=LPC18xxUSB.NT.AddReg - -[LPC18xxUSB.NT.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[LPC18xxUSB.NT.Services] -AddService=usbser, 0x00000002, DriverService.NT - -[DriverService.NT] -DisplayName=%DESCRIPTION% -ServiceType=1 -StartType=3 -ErrorControl=1 -ServiceBinary=%12%\usbser.sys -LoadOrderGroup = Base - -;------------------------------------------------------------------------------ -; String Definitions -;------------------------------------------------------------------------------ - -[Strings] -NXP="NXP - Founded by Philips" -DESCRIPTION="LPC18xx USB VCom Port" diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom.inf b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom.inf deleted file mode 100644 index 715179f16..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom.inf +++ /dev/null @@ -1,65 +0,0 @@ -; -; Keil - An ARM Company Comunication Device Class driver installation file -; (C)2007 Copyright -; - -[Version] -Signature="$Windows NT$" -Class=Ports -ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} -Provider=%Keil% -;LayoutFile=layout.inf -DriverVer=01/06/07 - -[Manufacturer] -%Keil%=DeviceList - -[DestinationDirs] -DefaultDestDir=12 - -[SourceDisksFiles] - -[SourceDisksNames] - -[DeviceList] -%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002 - -;------------------------------------------------------------------------------ -; Windows 2000/XP Sections -;------------------------------------------------------------------------------ - -[LPC18xxUSB.nt] -include=mdmcpq.inf -CopyFiles=DriverCopyFiles -AddReg=LPC18xxUSB.nt.AddReg - -[DriverCopyFiles] -usbser.sys,,,0x20 - -[LPC18xxUSB.nt.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[LPC18xxUSB.nt.Services] -include=mdmcpq.inf -AddService=usbser, 0x00000002, DriverService - - -[LPC18xxUSB.nt.HW] -include=mdmcpq.inf - -[DriverService] -DisplayName=%DESCRIPTION% -ServiceType=1 -StartType=3 -ErrorControl=1 -ServiceBinary=%12%\usbser.sys - -;------------------------------------------------------------------------------ -; String Definitions -;------------------------------------------------------------------------------ - -[Strings] -NXP="NXP - Founded by Philips" -DESCRIPTION="LPC18xx USB VCom Port" diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbcore.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbcore.c deleted file mode 100644 index 554390aa7..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbcore.c +++ /dev/null @@ -1,1130 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbcore.c - * Purpose: USB Core Module - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC family microcontroller devices only. Nothing - * else gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Added vendor specific requests - * Changed string descriptor handling - * Reworked Endpoint0 - * V1.00 Initial Version - *----------------------------------------------------------------------------*/ -#include "lpc18xx.H" -#include "lpc_types.h" - -#include "usb.h" -#include "usbcfg.h" -#include "usbhw.h" -#include "usbcore.h" -#include "usbdesc.h" -#include "usbuser.h" - -#if (USB_CLASS) - -#if (USB_AUDIO) -#include "audio.h" -#include "adcuser.h" -#endif - -#if (USB_HID) -#include "hid.h" -#include "hiduser.h" -#endif - -#if (USB_MSC) -#include "msc.h" -#include "mscuser.h" -extern MSC_CSW CSW; -#endif - -#if (USB_CDC) -#include "cdc.h" -#include "cdcuser.h" -#endif - -#endif - -#if (USB_VENDOR) -#include "vendor.h" -#endif - -#ifdef __CC_ARM -#pragma diag_suppress 111,177,1441 -#endif - -#if defined ( __GNUC__ ) -#define __packed __attribute__((__packed__)) -#endif - -uint16_t USB_DeviceStatus; -uint8_t USB_DeviceAddress; -uint8_t USB_Configuration; -uint32_t USB_EndPointMask; -uint32_t USB_EndPointHalt; -uint32_t USB_EndPointStall; /* EP must stay stalled */ -uint8_t USB_NumInterfaces; -uint8_t USB_AltSetting[USB_IF_NUM]; - -USB_EP_DATA EP0Data; - -#pragma pack(4) -uint8_t EP0Buf[USB_MAX_PACKET0]; -USB_SETUP_PACKET SetupPacket; - -extern volatile uint32_t DevStatusFS2HS; - -/* - * Reset USB Core - * Parameters: None - * Return Value: None - */ - -void USB_ResetCore (void) { - - USB_DeviceStatus = USB_POWER; - USB_DeviceAddress = 0; - USB_Configuration = 0; - USB_EndPointMask = 0x00010001; - USB_EndPointHalt = 0x00000000; - USB_EndPointStall = 0x00000000; -} - - -/* - * USB Request - Setup Stage - * Parameters: None (global SetupPacket) - * Return Value: None - */ - -void USB_SetupStage (void) { - USB_ReadSetupPkt(0x00, (uint32_t *)&SetupPacket); -} - - -/* - * USB Request - Data In Stage - * Parameters: None (global EP0Data) - * Return Value: None - */ - -void USB_DataInStage (void) { - uint32_t cnt; - - if (EP0Data.Count > USB_MAX_PACKET0) { - cnt = USB_MAX_PACKET0; - } else { - cnt = EP0Data.Count; - } - cnt = USB_WriteEP(0x80, EP0Data.pData, cnt); - EP0Data.pData += cnt; - EP0Data.Count -= cnt; -} - - -/* - * USB Request - Data Out Stage - * Parameters: None (global EP0Data) - * Return Value: None - */ - -void USB_DataOutStage (void) { - uint32_t cnt; - - cnt = USB_ReadEP(0x00, EP0Data.pData); - EP0Data.pData += cnt; - EP0Data.Count -= cnt; -} - - -/* - * USB Request - Status In Stage - * Parameters: None - * Return Value: None - */ - -void USB_StatusInStage (void) { - USB_WriteEP(0x80, NULL, 0); -} - - -/* - * USB Request - Status Out Stage - * Parameters: None - * Return Value: None - */ - -void USB_StatusOutStage (void) { - USB_ReadEP(0x00, EP0Buf); -} - - -/* - * Get Status USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -INLINE uint32_t USB_ReqGetStatus (void) { - uint32_t n, m; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - EP0Data.pData = (uint8_t *)&USB_DeviceStatus; - break; - case REQUEST_TO_INTERFACE: - if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) { - *((__packed uint16_t *)EP0Buf) = 0; - EP0Data.pData = EP0Buf; - } else { - return (FALSE); - } - break; - case REQUEST_TO_ENDPOINT: - n = SetupPacket.wIndex.WB.L & 0x8F; - m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); - if (((USB_Configuration != 0) || ((n & 0x0F) == 0)) && (USB_EndPointMask & m)) { - *((__packed uint16_t *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0; - EP0Data.pData = EP0Buf; - } else { - return (FALSE); - } - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Set/Clear Feature USB Request - * Parameters: sc: 0 - Clear, 1 - Set - * (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -INLINE uint32_t USB_ReqSetClrFeature (uint32_t sc) { - uint32_t n, m; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - if (SetupPacket.wValue.W == USB_FEATURE_REMOTE_WAKEUP) { - if (sc) { - USB_WakeUpCfg(TRUE); - USB_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP; - } else { - USB_WakeUpCfg(FALSE); - USB_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP; - } - } else if (SetupPacket.wValue.W == USB_FEATURE_TEST_MODE) { - return USB_SetTestMode(SetupPacket.wIndex.WB.H); - } else { - return (FALSE); - } - break; - case REQUEST_TO_INTERFACE: - return (FALSE); - case REQUEST_TO_ENDPOINT: - n = SetupPacket.wIndex.WB.L & 0x8F; - m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); - if ((USB_Configuration != 0) && ((n & 0x0F) != 0) && (USB_EndPointMask & m)) { - if (SetupPacket.wValue.W == USB_FEATURE_ENDPOINT_STALL) { - if (sc) { - USB_SetStallEP(n); - USB_EndPointHalt |= m; - } else { - if ((USB_EndPointStall & m) != 0) { - return (TRUE); - } - USB_ClrStallEP(n); -#if (USB_MSC) - if ((n == MSC_EP_IN) && ((USB_EndPointHalt & m) != 0)) { - /* Compliance Test: rewrite CSW after unstall */ - if (CSW.dSignature == MSC_CSW_Signature) { - USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW)); - } - } -#endif - USB_EndPointHalt &= ~m; - } - } else { - return (FALSE); - } - } else { - return (FALSE); - } - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Set Address USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -INLINE uint32_t USB_ReqSetAddress (void) { - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - USB_DeviceAddress = 0x80 | SetupPacket.wValue.WB.L; - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Get Descriptor USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -INLINE uint32_t USB_ReqGetDescriptor (void) { - uint8_t *pD; - uint32_t len, n; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - switch (SetupPacket.wValue.WB.H) { - case USB_DEVICE_DESCRIPTOR_TYPE: - EP0Data.pData = (uint8_t *)USB_DeviceDescriptor; - len = USB_DEVICE_DESC_SIZE; - break; - case USB_CONFIGURATION_DESCRIPTOR_TYPE: - if ( DevStatusFS2HS == FALSE ) { - pD = (uint8_t *)USB_FSConfigDescriptor; - } else { - pD = (uint8_t *)USB_HSConfigDescriptor; - } - for (n = 0; n != SetupPacket.wValue.WB.L; n++) { - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) { - pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; - } - } - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) { - return (FALSE); - } - EP0Data.pData = pD; - len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; - break; - case USB_STRING_DESCRIPTOR_TYPE: - pD = (uint8_t *)USB_StringDescriptor; - for (n = 0; n != SetupPacket.wValue.WB.L; n++) { - if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) { - pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength; - } - } - if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) { - return (FALSE); - } - EP0Data.pData = pD; - len = ((USB_STRING_DESCRIPTOR *)pD)->bLength; - break; - case USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE: - /* USB Chapter 9. page 9.6.2 */ - if ( DevStatusFS2HS == FALSE ) { - return (FALSE); - } - else - { - EP0Data.pData = (uint8_t *)USB_DeviceQualifier; - len = USB_DEVICE_QUALI_SIZE; - } - break; - case USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE: - if ( DevStatusFS2HS == TRUE ) { - pD = (uint8_t *)USB_FSOtherSpeedConfiguration; - } else { - pD = (uint8_t *)USB_HSOtherSpeedConfiguration; - } - - for (n = 0; n != SetupPacket.wValue.WB.L; n++) { - if (((USB_OTHER_SPEED_CONFIGURATION *)pD)->bLength != 0) { - pD += ((USB_OTHER_SPEED_CONFIGURATION *)pD)->wTotalLength; - } - } - if (((USB_OTHER_SPEED_CONFIGURATION *)pD)->bLength == 0) { - return (FALSE); - } - EP0Data.pData = pD; - len = ((USB_OTHER_SPEED_CONFIGURATION *)pD)->wTotalLength; - break; - default: - return (FALSE); - } - break; - case REQUEST_TO_INTERFACE: - switch (SetupPacket.wValue.WB.H) { -#if USB_HID - case HID_HID_DESCRIPTOR_TYPE: - if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) { - return (FALSE); /* Only Single HID Interface is supported */ - } - if ( DevStatusFS2HS == FALSE ) { - EP0Data.pData = (uint8_t *)USB_FSConfigDescriptor + HID_DESC_OFFSET; - } else { - EP0Data.pData = (uint8_t *)USB_HSConfigDescriptor + HID_DESC_OFFSET; - } - len = HID_DESC_SIZE; - break; - case HID_REPORT_DESCRIPTOR_TYPE: - if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) { - return (FALSE); /* Only Single HID Interface is supported */ - } - EP0Data.pData = (uint8_t *)HID_ReportDescriptor; - len = HID_ReportDescSize; - break; - case HID_PHYSICAL_DESCRIPTOR_TYPE: - return (FALSE); /* HID Physical Descriptor is not supported */ -#endif - default: - return (FALSE); - } - break; - default: - return (FALSE); - } - - if (EP0Data.Count > len) { - EP0Data.Count = len; - } - - return (TRUE); -} - - -/* - * Get Configuration USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -INLINE uint32_t USB_ReqGetConfiguration (void) { - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - EP0Data.pData = &USB_Configuration; - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Set Configuration USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -INLINE uint32_t USB_ReqSetConfiguration (void) { - USB_COMMON_DESCRIPTOR *pD; - uint32_t alt = 0; - uint32_t n, m; - uint32_t new_addr; - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - - if (SetupPacket.wValue.WB.L) { - if ( DevStatusFS2HS == FALSE ) { - pD = (USB_COMMON_DESCRIPTOR *)USB_FSConfigDescriptor; - } else { - pD = (USB_COMMON_DESCRIPTOR *)USB_HSConfigDescriptor; - } - while (pD->bLength) { - switch (pD->bDescriptorType) { - case USB_CONFIGURATION_DESCRIPTOR_TYPE: - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == SetupPacket.wValue.WB.L) { - USB_Configuration = SetupPacket.wValue.WB.L; - USB_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces; - for (n = 0; n < USB_IF_NUM; n++) { - USB_AltSetting[n] = 0; - } - for (n = 1; n < USB_EP_NUM; n++) { - if (USB_EndPointMask & (1 << n)) { - USB_DisableEP(n); - } - if (USB_EndPointMask & ((1 << 16) << n)) { - USB_DisableEP(n | 0x80); - } - } - USB_EndPointMask = 0x00010001; - USB_EndPointHalt = 0x00000000; - USB_EndPointStall= 0x00000000; - USB_Configure(TRUE); - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) { - USB_DeviceStatus |= USB_GETSTATUS_SELF_POWERED; - } else { - USB_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED; - } - } else { - new_addr = (uint32_t)pD + ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; - pD = (USB_COMMON_DESCRIPTOR*)new_addr; - continue; - } - break; - case USB_INTERFACE_DESCRIPTOR_TYPE: - alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting; - break; - case USB_ENDPOINT_DESCRIPTOR_TYPE: - if (alt == 0) { - n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F; - m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); - USB_EndPointMask |= m; - USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD); - USB_EnableEP(n); - USB_ResetEP(n); - } - break; - } - new_addr = (uint32_t)pD + pD->bLength; - pD = (USB_COMMON_DESCRIPTOR*)new_addr; - } - } - else { - USB_Configuration = 0; - for (n = 1; n < USB_EP_NUM; n++) { - if (USB_EndPointMask & (1 << n)) { - USB_DisableEP(n); - } - if (USB_EndPointMask & ((1 << 16) << n)) { - USB_DisableEP(n | 0x80); - } - } - USB_EndPointMask = 0x00010001; - USB_EndPointHalt = 0x00000000; - USB_EndPointStall = 0x00000000; - USB_Configure(FALSE); - } - - if (USB_Configuration != SetupPacket.wValue.WB.L) { - return (FALSE); - } - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Get Interface USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -INLINE uint32_t USB_ReqGetInterface (void) { - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_INTERFACE: - if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) { - EP0Data.pData = USB_AltSetting + SetupPacket.wIndex.WB.L; - } else { - return (FALSE); - } - break; - default: - return (FALSE); - } - return (TRUE); -} - - -/* - * Set Interface USB Request - * Parameters: None (global SetupPacket) - * Return Value: TRUE - Success, FALSE - Error - */ - -INLINE uint32_t USB_ReqSetInterface (void) { - USB_COMMON_DESCRIPTOR *pD; - uint32_t ifn = 0, alt = 0, old = 0, msk = 0; - uint32_t n, m; - uint32_t set, new_addr; - - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_INTERFACE: - if (USB_Configuration == 0) return (FALSE); - set = FALSE; - if ( DevStatusFS2HS == FALSE ) { - pD = (USB_COMMON_DESCRIPTOR *)USB_FSConfigDescriptor; - } else { - pD = (USB_COMMON_DESCRIPTOR *)USB_HSConfigDescriptor; - } - while (pD->bLength) { - switch (pD->bDescriptorType) { - case USB_CONFIGURATION_DESCRIPTOR_TYPE: - if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != USB_Configuration) { - new_addr = (uint32_t)pD + ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength; - pD = (USB_COMMON_DESCRIPTOR*)new_addr; - continue; - } - break; - case USB_INTERFACE_DESCRIPTOR_TYPE: - ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber; - alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting; - msk = 0; - if ((ifn == SetupPacket.wIndex.WB.L) && (alt == SetupPacket.wValue.WB.L)) { - set = TRUE; - old = USB_AltSetting[ifn]; - USB_AltSetting[ifn] = (uint8_t)alt; - } - break; - case USB_ENDPOINT_DESCRIPTOR_TYPE: - if (ifn == SetupPacket.wIndex.WB.L) { - n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F; - m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); - if (alt == SetupPacket.wValue.WB.L) { - USB_EndPointMask |= m; - USB_EndPointHalt &= ~m; - USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD); - USB_EnableEP(n); - USB_ResetEP(n); - msk |= m; - } - else if ((alt == old) && ((msk & m) == 0)) { - USB_EndPointMask &= ~m; - USB_EndPointHalt &= ~m; - USB_DisableEP(n); - } - } - break; - } - new_addr = (uint32_t)pD + pD->bLength; - pD = (USB_COMMON_DESCRIPTOR*)new_addr; - } - break; - default: - return (FALSE); - } - - return (set); -} - - -/* - * USB Endpoint 0 Event Callback - * Parameters: event - * Return Value: none - */ - -void USB_EndPoint0 (uint32_t event) { - - switch (event) { - case USB_EVT_SETUP: - USB_SetupStage(); - USB_DirCtrlEP(SetupPacket.bmRequestType.BM.Dir); - EP0Data.Count = SetupPacket.wLength; /* Number of bytes to transfer */ - switch (SetupPacket.bmRequestType.BM.Type) { - - case REQUEST_STANDARD: - switch (SetupPacket.bRequest) { - case USB_REQUEST_GET_STATUS: - if (!USB_ReqGetStatus()) { - goto stall_i; - } - USB_DataInStage(); - break; - - case USB_REQUEST_CLEAR_FEATURE: - if (!USB_ReqSetClrFeature(0)) { - goto stall_i; - } - USB_StatusInStage(); -#if USB_FEATURE_EVENT - USB_Feature_Event(); -#endif - break; - - case USB_REQUEST_SET_FEATURE: - if (!USB_ReqSetClrFeature(1)) { - goto stall_i; - } - USB_StatusInStage(); -#if USB_FEATURE_EVENT - USB_Feature_Event(); -#endif - break; - - case USB_REQUEST_SET_ADDRESS: - if (!USB_ReqSetAddress()) { - goto stall_i; - } - USB_StatusInStage(); - break; - - case USB_REQUEST_GET_DESCRIPTOR: - if (!USB_ReqGetDescriptor()) { - goto stall_i; - } - USB_DataInStage(); - break; - - case USB_REQUEST_SET_DESCRIPTOR: -/*stall_o:*/ USB_SetStallEP(0x00); /* not supported */ - EP0Data.Count = 0; - break; - - case USB_REQUEST_GET_CONFIGURATION: - if (!USB_ReqGetConfiguration()) { - goto stall_i; - } - USB_DataInStage(); - break; - - case USB_REQUEST_SET_CONFIGURATION: - if (!USB_ReqSetConfiguration()) { - goto stall_i; - } - USB_StatusInStage(); -#if USB_CONFIGURE_EVENT - USB_Configure_Event(); -#endif - break; - - case USB_REQUEST_GET_INTERFACE: - if (!USB_ReqGetInterface()) { - goto stall_i; - } - USB_DataInStage(); - break; - - case USB_REQUEST_SET_INTERFACE: - if (!USB_ReqSetInterface()) { - goto stall_i; - } - USB_StatusInStage(); -#if USB_INTERFACE_EVENT - USB_Interface_Event(); -#endif - break; - - default: - goto stall_i; - } - break; /* end case REQUEST_STANDARD */ - -#if USB_CLASS - case REQUEST_CLASS: - switch (SetupPacket.bmRequestType.BM.Recipient) { - - case REQUEST_TO_DEVICE: - goto stall_i; /* not supported */ - - case REQUEST_TO_INTERFACE: -#if USB_HID - if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */ - switch (SetupPacket.bRequest) { - case HID_REQUEST_GET_REPORT: - if (HID_GetReport()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case HID_REQUEST_SET_REPORT: - EP0Data.pData = EP0Buf; /* data to be received */ - goto setup_class_ok; - case HID_REQUEST_GET_IDLE: - if (HID_GetIdle()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case HID_REQUEST_SET_IDLE: - if (HID_SetIdle()) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - case HID_REQUEST_GET_PROTOCOL: - if (HID_GetProtocol()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case HID_REQUEST_SET_PROTOCOL: - if (HID_SetProtocol()) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - } - } -#endif /* USB_HID */ -#if USB_MSC - if (SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) { /* IF number correct? */ - switch (SetupPacket.bRequest) { - case MSC_REQUEST_RESET: - if ((SetupPacket.wValue.W == 0) && /* RESET with invalid parameters -> STALL */ - (SetupPacket.wLength == 0)) { - if (MSC_Reset()) { - USB_StatusInStage(); - goto setup_class_ok; - } - } - break; - case MSC_REQUEST_GET_MAX_LUN: - if ((SetupPacket.wValue.W == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */ - (SetupPacket.wLength == 1)) { - if (MSC_GetMaxLUN()) { - EP0Data.pData = EP0Buf; - USB_DataInStage(); - goto setup_class_ok; - } - } - break; - } - } -#endif /* USB_MSC */ -#if USB_AUDIO - if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */ - (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) || - (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) { - switch (SetupPacket.bRequest) { - case AUDIO_REQUEST_GET_CUR: - case AUDIO_REQUEST_GET_MIN: - case AUDIO_REQUEST_GET_MAX: - case AUDIO_REQUEST_GET_RES: - if (ADC_IF_GetRequest()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case AUDIO_REQUEST_SET_CUR: -// case AUDIO_REQUEST_SET_MIN: -// case AUDIO_REQUEST_SET_MAX: -// case AUDIO_REQUEST_SET_RES: - EP0Data.pData = EP0Buf; /* data to be received */ - goto setup_class_ok; - } - } -#endif /* USB_AUDIO */ -#if USB_CDC - if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */ - (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) { - switch (SetupPacket.bRequest) { - case CDC_SEND_ENCAPSULATED_COMMAND: - EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ - goto setup_class_ok; - case CDC_GET_ENCAPSULATED_RESPONSE: - if (CDC_GetEncapsulatedResponse()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case CDC_SET_COMM_FEATURE: - EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ - goto setup_class_ok; - case CDC_GET_COMM_FEATURE: - if (CDC_GetCommFeature(SetupPacket.wValue.W)) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case CDC_CLEAR_COMM_FEATURE: - if (CDC_ClearCommFeature(SetupPacket.wValue.W)) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - case CDC_SET_LINE_CODING: - EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */ - goto setup_class_ok; - case CDC_GET_LINE_CODING: - if (CDC_GetLineCoding()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case CDC_SET_CONTROL_LINE_STATE: - if (CDC_SetControlLineState(SetupPacket.wValue.W)) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - case CDC_SEND_BREAK: - if (CDC_SendBreak(SetupPacket.wValue.W)) { - USB_StatusInStage(); /* send Acknowledge */ - goto setup_class_ok; - } - break; - } - } -#endif /* USB_CDC */ - goto stall_i; /* not supported */ - /* end case REQUEST_TO_INTERFACE */ - - case REQUEST_TO_ENDPOINT: -#if USB_AUDIO - switch (SetupPacket.bRequest) { - case AUDIO_REQUEST_GET_CUR: - case AUDIO_REQUEST_GET_MIN: - case AUDIO_REQUEST_GET_MAX: - case AUDIO_REQUEST_GET_RES: - if (ADC_EP_GetRequest()) { - EP0Data.pData = EP0Buf; /* point to data to be sent */ - USB_DataInStage(); /* send requested data */ - goto setup_class_ok; - } - break; - case AUDIO_REQUEST_SET_CUR: -// case AUDIO_REQUEST_SET_MIN: -// case AUDIO_REQUEST_SET_MAX: -// case AUDIO_REQUEST_SET_RES: - EP0Data.pData = EP0Buf; /* data to be received */ - goto setup_class_ok; - } -#endif /* USB_AUDIO */ - goto stall_i; - /* end case REQUEST_TO_ENDPOINT */ - - default: - goto stall_i; - } -setup_class_ok: /* request finished successfully */ - break; /* end case REQUEST_CLASS */ -#endif /* USB_CLASS */ - -#if USB_VENDOR - case REQUEST_VENDOR: - switch (SetupPacket.bmRequestType.BM.Recipient) { - - case REQUEST_TO_DEVICE: - if (!USB_ReqVendorDev(TRUE)) { - goto stall_i; /* not supported */ - } - break; - - case REQUEST_TO_INTERFACE: - if (!USB_ReqVendorIF(TRUE)) { - goto stall_i; /* not supported */ - } - break; - - case REQUEST_TO_ENDPOINT: - if (!USB_ReqVendorEP(TRUE)) { - goto stall_i; /* not supported */ - } - break; - - default: - goto stall_i; - } - - if (SetupPacket.wLength) { - if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) { - USB_DataInStage(); - } - } else { - USB_StatusInStage(); - } - - break; /* end case REQUEST_VENDOR */ -#endif /* USB_VENDOR */ - - default: -stall_i: USB_SetStallEP(0x80); - EP0Data.Count = 0; - break; - } - break; /* end case USB_EVT_SETUP */ - - case USB_EVT_OUT_NAK: - if (SetupPacket.bmRequestType.BM.Dir == 0) - { - USB_ReadReqEP(0x00, EP0Data.pData, EP0Data.Count); - } - else - { - /* might be zero length pkt */ - USB_ReadReqEP(0x00, EP0Data.pData, 0); - } - break; - case USB_EVT_OUT: - if (SetupPacket.bmRequestType.BM.Dir == REQUEST_HOST_TO_DEVICE) { - if (EP0Data.Count) { /* still data to receive ? */ - USB_DataOutStage(); /* receive data */ - if (EP0Data.Count == 0) { /* data complete ? */ - switch (SetupPacket.bmRequestType.BM.Type) { - - case REQUEST_STANDARD: - goto stall_i; /* not supported */ - -#if (USB_CLASS) - case REQUEST_CLASS: - switch (SetupPacket.bmRequestType.BM.Recipient) { - case REQUEST_TO_DEVICE: - goto stall_i; /* not supported */ - - case REQUEST_TO_INTERFACE: -#if USB_HID - if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */ - switch (SetupPacket.bRequest) { - case HID_REQUEST_SET_REPORT: - if (HID_SetReport()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - } - } -#endif /* USB_HID */ -#if USB_AUDIO - if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */ - (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) || - (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) { - switch (SetupPacket.bRequest) { - case AUDIO_REQUEST_SET_CUR: -// case AUDIO_REQUEST_SET_MIN: -// case AUDIO_REQUEST_SET_MAX: -// case AUDIO_REQUEST_SET_RES: - if (ADC_IF_SetRequest()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - } - } -#endif /* USB_AUDIO */ -#if USB_CDC - if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */ - (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) { - switch (SetupPacket.bRequest) { - case CDC_SEND_ENCAPSULATED_COMMAND: - if (CDC_SendEncapsulatedCommand()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - case CDC_SET_COMM_FEATURE: - if (CDC_SetCommFeature(SetupPacket.wValue.W)) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - case CDC_SET_LINE_CODING: - if (CDC_SetLineCoding()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - } - } -#endif /* USB_CDC */ - goto stall_i; - /* end case REQUEST_TO_INTERFACE */ - - case REQUEST_TO_ENDPOINT: -#if USB_AUDIO - switch (SetupPacket.bRequest) { - case AUDIO_REQUEST_SET_CUR: -// case AUDIO_REQUEST_SET_MIN: -// case AUDIO_REQUEST_SET_MAX: -// case AUDIO_REQUEST_SET_RES: - if (ADC_EP_SetRequest()) { - USB_StatusInStage(); /* send Acknowledge */ - goto out_class_ok; - } - break; - } -#endif /* USB_AUDIO */ - goto stall_i; - /* end case REQUEST_TO_ENDPOINT */ - - default: - goto stall_i; - } -out_class_ok: /* request finished successfully */ - break; /* end case REQUEST_CLASS */ -#endif /* USB_CLASS */ - -#if USB_VENDOR - case REQUEST_VENDOR: - switch (SetupPacket.bmRequestType.BM.Recipient) { - - case REQUEST_TO_DEVICE: - if (!USB_ReqVendorDev(FALSE)) { - goto stall_i; /* not supported */ - } - break; - - case REQUEST_TO_INTERFACE: - if (!USB_ReqVendorIF(FALSE)) { - goto stall_i; /* not supported */ - } - break; - - case REQUEST_TO_ENDPOINT: - if (!USB_ReqVendorEP(FALSE)) { - goto stall_i; /* not supported */ - } - break; - - default: - goto stall_i; - } - - USB_StatusInStage(); - - break; /* end case REQUEST_VENDOR */ -#endif /* USB_VENDOR */ - - default: - goto stall_i; - } - } - } - } else { - USB_StatusOutStage(); /* receive Acknowledge */ - } - break; /* end case USB_EVT_OUT */ - - case USB_EVT_IN : - if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) { - USB_DataInStage(); /* send data */ - } else { - if (USB_DeviceAddress & 0x80) { - USB_DeviceAddress &= 0x7F; - USB_SetAddress(USB_DeviceAddress); - } - } - break; /* end case USB_EVT_IN */ - - case USB_EVT_OUT_STALL: - USB_ClrStallEP(0x00); - break; - - case USB_EVT_IN_STALL: - USB_ClrStallEP(0x80); - break; - - } -} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbdesc.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbdesc.c deleted file mode 100644 index 270b838ca..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbdesc.c +++ /dev/null @@ -1,479 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbdesc.c - * Purpose: USB Descriptors - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC microcontroller devices only. Nothing else - * gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------- - * History: - * V1.20 Changed string descriptor handling - * V1.00 Initial Version - *----------------------------------------------------------------------------*/ -#include "lpc18xx.H" -#include "lpc_types.h" - -#include "usb.h" -#include "cdc.h" -#include "usbcfg.h" -#include "usbdesc.h" - - -/* USB Standard Device Descriptor */ -const uint8_t USB_DeviceDescriptor[] = { - USB_DEVICE_DESC_SIZE, /* bLength */ - USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(0x0200), /* 2.0 */ /* bcdUSB */ - USB_DEVICE_CLASS_COMMUNICATIONS, /* bDeviceClass CDC*/ - 0x00, /* bDeviceSubClass */ - 0x00, /* bDeviceProtocol */ - USB_MAX_PACKET0, /* bMaxPacketSize0 */ - WBVAL(0x1FC9), /* idVendor */ - WBVAL(0x2002), /* idProduct */ - WBVAL(0x0100), /* 1.00 */ /* bcdDevice */ - 0x01, /* iManufacturer */ - 0x02, /* iProduct */ - 0x03, /* iSerialNumber */ - 0x01 /* bNumConfigurations: one possible configuration*/ -}; - -/* USB FSConfiguration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -const uint8_t USB_FSConfigDescriptor[] = { -/* Configuration 1 */ - USB_CONFIGUARTION_DESC_SIZE, /* bLength */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(( /* wTotalLength */ - 1*USB_CONFIGUARTION_DESC_SIZE + - 1*USB_INTERFACE_DESC_SIZE + /* communication interface */ - 0x0013 + /* CDC functions */ - 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */ - 1*USB_INTERFACE_DESC_SIZE + /* data interface */ - 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */ - )), - 0x02, /* bNumInterfaces */ - 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */ - 0x00, /* iConfiguration: no string to describe this configuration */ - USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */ -/*USB_CONFIG_REMOTE_WAKEUP*/, - USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */ -/* Interface 0, Alternate Setting 0, Communication class interface descriptor */ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoint used */ - CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */ - CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x5E, /* iInterface: */ -/*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */ - WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */ -/*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */ - 0x01, /* bmCapabilities: device handles call management */ - 0x01, /* bDataInterface: CDC data IF ID */ -/*Abstract Control Management Functional Descriptor*/ - 0x04, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */ -/*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_UNION, /* bDescriptorSubtype: Union func desc */ - USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */ - USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */ -/*Endpoint 1 Descriptor*/ /* event notification (optional) */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(1), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ - WBVAL(0x0010), /* wMaxPacketSize */ - 0x02, /* 2ms */ /* bInterval */ -/* Interface 1, Alternate Setting 0, Data class interface descriptor*/ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: no alternate setting */ - 0x02, /* bNumEndpoints: two endpoints used */ - CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */ - 0x00, /* bInterfaceSubClass: no subclass available */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x5E, /* iInterface: */ -/* Endpoint, EP2 Bulk Out */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_OUT(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ -/* Endpoint, EP2 Bulk In */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ -/* Terminator */ - 0 /* bLength */ - /* bLength */ -}; - -/* USB HSConfiguration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -const uint8_t USB_HSConfigDescriptor[] = { -/* Configuration 1 */ - USB_CONFIGUARTION_DESC_SIZE, /* bLength */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(( /* wTotalLength */ - 1*USB_CONFIGUARTION_DESC_SIZE + - 1*USB_INTERFACE_DESC_SIZE + /* communication interface */ - 0x0013 + /* CDC functions */ - 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */ - 1*USB_INTERFACE_DESC_SIZE + /* data interface */ - 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */ - )), - 0x02, /* bNumInterfaces */ - 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */ - 0x00, /* iConfiguration: no string to describe this configuration */ - USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */ -/*USB_CONFIG_REMOTE_WAKEUP*/, - USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */ -/* Interface 0, Alternate Setting 0, Communication class interface descriptor */ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoint used */ - CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */ - CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x5E, /* iInterface: */ -/*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */ - WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */ -/*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */ - 0x01, /* bmCapabilities: device handles call management */ - 0x01, /* bDataInterface: CDC data IF ID */ -/*Abstract Control Management Functional Descriptor*/ - 0x04, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */ -/*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_UNION, /* bDescriptorSubtype: Union func desc */ - USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */ - USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */ -/*Endpoint 1 Descriptor*/ /* event notification (optional) */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(1), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ - WBVAL(0x0010), /* wMaxPacketSize */ - 0x02, /* 2ms */ /* bInterval */ -/* Interface 1, Alternate Setting 0, Data class interface descriptor*/ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: no alternate setting */ - 0x02, /* bNumEndpoints: two endpoints used */ - CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */ - 0x00, /* bInterfaceSubClass: no subclass available */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x5E, /* iInterface: */ -/* Endpoint, EP2 Bulk Out */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_OUT(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ -/* Endpoint, EP2 Bulk In */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ -/* Terminator */ - 0 /* bLength */ - /* bLength */ -}; - -/* USB String Descriptor (optional) */ -const uint8_t USB_StringDescriptor[] = { -/* Index 0x00: LANGID Codes */ - 0x04, /* bLength */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(0x0409), /* US English */ /* wLANGID */ -/* Index 0x01: Manufacturer */ - (16*2 + 2), /* bLength (13 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'N',0, - 'G',0, - 'X',0, - ' ',0, - 'T',0, - 'E',0, - 'C',0, - 'H',0, - 'N',0, - 'O',0, - 'L',0, - 'O',0, - 'G',0, - 'I',0, - 'E',0, - 'S',0, -/* Index 0x02: Product */ - (17*2 + 2), /* bLength ( 17 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'N',0, - 'G',0, - 'X',0, - ' ',0, - 'L',0, - 'P',0, - 'C',0, - '1',0, - '8',0, - 'x',0, - 'x',0, - ' ',0, - 'V',0, - 'C',0, - 'O',0, - 'M',0, - ' ',0, -/* Index 0x03: Serial Number */ - (12*2 + 2), /* bLength (12 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'D',0, - 'E',0, - 'M',0, - 'O',0, - '0',0, - '0',0, - '0',0, - '0',0, - '0',0, - '0',0, - '0',0, - '0',0, -/* Index 0x04: Interface 0, Alternate Setting 0 */ - ( 4*2 + 2), /* bLength (4 Char + Type + lenght) */ - USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */ - 'V',0, - 'C',0, - 'O',0, - 'M',0, -}; - -/* USB Device Qualifier */ -const uint8_t USB_DeviceQualifier[] = { - USB_DEVICE_QUALI_SIZE, /* bLength */ - USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(0x0200), /* 2.00 */ /* bcdUSB */ - 0x00, /* bDeviceClass */ - 0x00, /* bDeviceSubClass */ - 0x00, /* bDeviceProtocol */ - USB_MAX_PACKET0, /* bMaxPacketSize0 */ - 0x01, /* bNumOtherSpeedConfigurations */ - 0x00 /* bReserved */ -}; - -/* USB Configuration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -const uint8_t USB_FSOtherSpeedConfiguration[] = { -/* Configuration 1 */ - USB_CONFIGUARTION_DESC_SIZE, /* bLength */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(( /* wTotalLength */ - 1*USB_CONFIGUARTION_DESC_SIZE + - 1*USB_INTERFACE_DESC_SIZE + /* communication interface */ - 0x0013 + /* CDC functions */ - 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */ - 1*USB_INTERFACE_DESC_SIZE + /* data interface */ - 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */ - )), - 0x02, /* bNumInterfaces */ - 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */ - 0x00, /* iConfiguration: no string to describe this configuration */ - USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */ -/*USB_CONFIG_REMOTE_WAKEUP*/, - USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */ -/* Interface 0, Alternate Setting 0, Communication class interface descriptor */ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoint used */ - CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */ - CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x5E, /* iInterface: */ -/*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */ - WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */ -/*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */ - 0x01, /* bmCapabilities: device handles call management */ - 0x01, /* bDataInterface: CDC data IF ID */ -/*Abstract Control Management Functional Descriptor*/ - 0x04, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */ -/*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_UNION, /* bDescriptorSubtype: Union func desc */ - USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */ - USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */ -/*Endpoint 1 Descriptor*/ /* event notification (optional) */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(1), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ - WBVAL(0x0010), /* wMaxPacketSize */ - 0x02, /* 2ms */ /* bInterval */ -/* Interface 1, Alternate Setting 0, Data class interface descriptor*/ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: no alternate setting */ - 0x02, /* bNumEndpoints: two endpoints used */ - CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */ - 0x00, /* bInterfaceSubClass: no subclass available */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x5E, /* iInterface: */ -/* Endpoint, EP2 Bulk Out */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_OUT(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ -/* Endpoint, EP2 Bulk In */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ -/* Terminator */ - 0 /* bLength */ -}; - -/* USB Configuration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -const uint8_t USB_HSOtherSpeedConfiguration[] = { -/* Configuration 1 */ - USB_CONFIGUARTION_DESC_SIZE, /* bLength */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ - WBVAL(( /* wTotalLength */ - 1*USB_CONFIGUARTION_DESC_SIZE + - 1*USB_INTERFACE_DESC_SIZE + /* communication interface */ - 0x0013 + /* CDC functions */ - 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */ - 1*USB_INTERFACE_DESC_SIZE + /* data interface */ - 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */ - )), - 0x02, /* bNumInterfaces */ - 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */ - 0x00, /* iConfiguration: no string to describe this configuration */ - USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */ -/*USB_CONFIG_REMOTE_WAKEUP*/, - USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */ -/* Interface 0, Alternate Setting 0, Communication class interface descriptor */ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoint used */ - CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */ - CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x5E, /* iInterface: */ -/*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */ - WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */ -/*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */ - 0x01, /* bmCapabilities: device handles call management */ - 0x01, /* bDataInterface: CDC data IF ID */ -/*Abstract Control Management Functional Descriptor*/ - 0x04, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */ -/*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ - CDC_UNION, /* bDescriptorSubtype: Union func desc */ - USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */ - USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */ -/*Endpoint 1 Descriptor*/ /* event notification (optional) */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(1), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ - WBVAL(0x0010), /* wMaxPacketSize */ - 0x02, /* 2ms */ /* bInterval */ -/* Interface 1, Alternate Setting 0, Data class interface descriptor*/ - USB_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: no alternate setting */ - 0x02, /* bNumEndpoints: two endpoints used */ - CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */ - 0x00, /* bInterfaceSubClass: no subclass available */ - 0x00, /* bInterfaceProtocol: no protocol used */ - 0x5E, /* iInterface: */ -/* Endpoint, EP2 Bulk Out */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_OUT(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ -/* Endpoint, EP2 Bulk In */ - USB_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - USB_ENDPOINT_IN(2), /* bEndpointAddress */ - USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ - WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */ - 0x00, /* bInterval: ignore for Bulk transfer */ -/* Terminator */ - 0 /* bLength */ -}; diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbhw.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbhw.c deleted file mode 100644 index 01c222d67..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbhw.c +++ /dev/null @@ -1,803 +0,0 @@ -/********************************************************************** -* $Id$ usbhw.c 2011-06-02 -*//** -* @file usbhw.c -* @brief USB Hardware Layer Module for NXP's lpc43xx MCU -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ -#include -#include "lpc18xx.H" /* lpc43xx definitions */ -#include "lpc_types.h" -#include "usb.h" -#include "usbhw.h" -#include "usbcfg.h" -#include "usbcore.h" -#include "lpc18xx_scu.h" -#include "lpc18xx_cgu.h" -#include "FreeRTOS.h" -#ifdef __CC_ARM -#pragma diag_suppress 1441 -#endif - -#ifdef __ICCARM__ -#pragma data_alignment=2048 -DQH_T ep_QH[EP_NUM_MAX]; -#pragma data_alignment=32 -DTD_T ep_TD[EP_NUM_MAX]; -#pragma data_alignment=4 -#elif defined ( __GNUC__ ) -#define __align(x) __attribute__((aligned(x))) -DQH_T ep_QH[EP_NUM_MAX] __attribute__((aligned(2048))); -DTD_T ep_TD[EP_NUM_MAX] __attribute__((aligned(32))); -#else -DQH_T __align(2048) ep_QH[EP_NUM_MAX]; -DTD_T __align(32) ep_TD[EP_NUM_MAX]; -#endif - - -static uint32_t ep_read_len[4]; -volatile uint32_t DevStatusFS2HS = FALSE; -LPC_USBDRV_INIT_T g_drv; - -/* - * Get Endpoint Physical Address - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: Endpoint Physical Address - */ - -uint32_t EPAdr (uint32_t EPNum) { - uint32_t val; - - val = (EPNum & 0x0F) << 1; - if (EPNum & 0x80) { - val += 1; - } - return (val); -} - -/* - * USB Initialize Function - * Called by the User to initialize USB - * Return Value: None - */ - -void USB_Init (LPC_USBDRV_INIT_T* cbs) -{ - memcpy(&g_drv, cbs, sizeof(LPC_USBDRV_INIT_T)); - /*maxp for EP0 should be atleast 8 */ - if( g_drv.ep0_maxp == 0) - g_drv.ep0_maxp = 64; - -#ifdef USE_USB0 - scu_pinmux(0x8,1,MD_PLN_FAST,FUNC1); // 0: motocon pcap0_1 1: usb0 usb0_ind1 2: nc 3: gpio4 gpio4_1 - scu_pinmux(0x8,2,MD_PLN_FAST,FUNC1); // 0: motocon pcap0_0 1: usb0 usb0_ind0 2: nc 3: gpio4 gpio4_2 -#endif -#ifdef USE_USB0 - CGU_SetPLL0(); - CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE); - CGU_EntityConnect(CGU_CLKSRC_PLL0, CGU_BASE_USB0); -#else - CGU_SetPLL1(5); - CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE); - CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1); - /* enable USB phy */ - LPC_CREG->CREG0 &= ~(1 << 5); - /* enable USB1_DP and USB1_DN on chip FS phy */ - LPC_SCU->SFSUSB = 0x12; - /* enable USB1_VBUS */ - scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); - -#endif - /* Turn on the phy */ -#ifdef USE_USB0 - LPC_CREG->CREG0 &= ~(1<<5); -#endif - /* reset the controller */ - LPC_USB->USBCMD_D = USBCMD_RST; - /* wait for reset to complete */ - while (LPC_USB->USBCMD_D & USBCMD_RST); - - /* Program the controller to be the USB device controller */ - LPC_USB->USBMODE_D = USBMODE_CM_DEV - | USBMODE_SDIS - | USBMODE_SLOM ; - - /* set OTG transcever in proper state, device is present - on the port(CCS=1), port enable/disable status change(PES=1). */ -#ifdef USE_USB0 - LPC_USB->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/; -#else - /* force full speed */ - LPC_USB->PORTSC1_D |= (1<<24); -#endif - -#ifdef USE_USB0 - NVIC_EnableIRQ(USB0_IRQn); // enable USB0 interrrupts - NVIC_SetPriority(USB0_IRQn, configMIN_LIBRARY_INTERRUPT_PRIORITY ); -#else - NVIC_EnableIRQ(USB1_IRQn); // enable USB1 interrrupts - NVIC_SetPriority(USB0_IRQn, configMIN_LIBRARY_INTERRUPT_PRIORITY ); -#endif - - USB_Reset(); - USB_SetAddress(0); - return; -} - -/* - * USB Connect Function - * Called by the User to Connect/Disconnect USB - * Parameters: con: Connect/Disconnect - * Return Value: None - */ -void USB_Connect (uint32_t con) { - if (con) - LPC_USB->USBCMD_D |= USBCMD_RS; - else - LPC_USB->USBCMD_D &= ~USBCMD_RS; -} - - -/* - * USB Reset Function - * Called automatically on USB Reset - * Return Value: None - */ - -void USB_Reset (void) -{ - uint32_t i; - - DevStatusFS2HS = FALSE; - /* disable all EPs */ - LPC_USB->ENDPTCTRL0 &= ~(EPCTRL_RXE | EPCTRL_TXE); - LPC_USB->ENDPTCTRL2 &= ~(EPCTRL_RXE | EPCTRL_TXE); - LPC_USB->ENDPTCTRL3 &= ~(EPCTRL_RXE | EPCTRL_TXE); - - /* Clear all pending interrupts */ - LPC_USB->ENDPTNAK = 0xFFFFFFFF; - LPC_USB->ENDPTNAKEN = 0; - LPC_USB->USBSTS_D = 0xFFFFFFFF; - LPC_USB->ENDPTSETUPSTAT = LPC_USB->ENDPTSETUPSTAT; - LPC_USB->ENDPTCOMPLETE = LPC_USB->ENDPTCOMPLETE; - while (LPC_USB->ENDPTPRIME) /* Wait until all bits are 0 */ - { - } - LPC_USB->ENDPTFLUSH = 0xFFFFFFFF; - while (LPC_USB->ENDPTFLUSH); /* Wait until all bits are 0 */ - - - /* Set the interrupt Threshold control interval to 0 */ - LPC_USB->USBCMD_D &= ~0x00FF0000; - - /* Zero out the Endpoint queue heads */ - memset((void*)ep_QH, 0, EP_NUM_MAX * sizeof(DQH_T)); - /* Zero out the device transfer descriptors */ - memset((void*)ep_TD, 0, EP_NUM_MAX * sizeof(DTD_T)); - memset((void*)ep_read_len, 0, sizeof(ep_read_len)); - /* Configure the Endpoint List Address */ - /* make sure it in on 64 byte boundary !!! */ - /* init list address */ - LPC_USB->ENDPOINTLISTADDR = (uint32_t)ep_QH; - /* Initialize device queue heads for non ISO endpoint only */ - for (i = 0; i < EP_NUM_MAX; i++) - { - ep_QH[i].next_dTD = (uint32_t)&ep_TD[i]; - } - /* Enable interrupts */ - LPC_USB->USBINTR_D = USBSTS_UI - | USBSTS_UEI - | USBSTS_PCI - | USBSTS_URI - | USBSTS_SLI - | USBSTS_NAKI; -// LPC_USB->usbintr |= (0x1<<7); /* Test SOF */ - /* enable ep0 IN and ep0 OUT */ - ep_QH[0].cap = QH_MAXP(g_drv.ep0_maxp) - | QH_IOS - | QH_ZLT; - ep_QH[1].cap = QH_MAXP(g_drv.ep0_maxp) - | QH_IOS - | QH_ZLT; - /* enable EP0 */ - LPC_USB->ENDPTCTRL0 = EPCTRL_RXE | EPCTRL_RXR | EPCTRL_TXE | EPCTRL_TXR; - return; - -} - - -/* - * USB Suspend Function - * Called automatically on USB Suspend - * Return Value: None - */ - -void USB_Suspend (void) { - /* Performed by Hardware */ -} - - -/* - * USB Resume Function - * Called automatically on USB Resume - * Return Value: None - */ - -void USB_Resume (void) { - /* Performed by Hardware */ -} - - -/* - * USB Remote Wakeup Function - * Called automatically on USB Remote Wakeup - * Return Value: None - */ - -void USB_WakeUp (void) { - - //if (USB_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP) - { - /* Set FPR bit in PORTSCX reg p63 */ - LPC_USB->PORTSC1_D |= USBPRTS_FPR ; - } -} - - -/* - * USB Remote Wakeup Configuration Function - * Parameters: cfg: Enable/Disable - * Return Value: None - */ - -void USB_WakeUpCfg (uint32_t cfg) { - ( void ) cfg; - /* Not needed */ -} - - -/* - * USB Set Address Function - * Parameters: adr: USB Address - * Return Value: None - */ - -void USB_SetAddress (uint32_t adr) { - LPC_USB->DEVICEADDR = USBDEV_ADDR(adr); - LPC_USB->DEVICEADDR |= USBDEV_ADDR_AD; -} - -/* -* USB set test mode Function -* Parameters: mode: test mode -* Return Value: TRUE if supported else FALSE -*/ - -uint32_t USB_SetTestMode(uint8_t mode) -{ - uint32_t portsc; - - if ((mode > 0) && (mode < 8)) - { - portsc = LPC_USB->PORTSC1_D & ~(0xF << 16); - - LPC_USB->PORTSC1_D = portsc | (mode << 16); - return TRUE; - } - return (FALSE); -} - -/* - * USB Configure Function - * Parameters: cfg: Configure/Deconfigure - * Return Value: None - */ - -void USB_Configure (uint32_t cfg) { - ( void ) cfg; -} - - -/* - * Configure USB Endpoint according to Descriptor - * Parameters: pEPD: Pointer to Endpoint Descriptor - * Return Value: None - */ - -void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) { - uint32_t num, lep; - uint32_t ep_cfg; - uint8_t bmAttributes; - - lep = pEPD->bEndpointAddress & 0x7F; - num = EPAdr(pEPD->bEndpointAddress); - - ep_cfg = ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep]; - /* mask the attributes we are not-intersetd in */ - bmAttributes = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK; - /* set EP type */ - if (bmAttributes != USB_ENDPOINT_TYPE_ISOCHRONOUS) - { - /* init EP capabilities */ - ep_QH[num].cap = QH_MAXP(pEPD->wMaxPacketSize) - | QH_IOS | QH_ZLT ; - /* The next DTD pointer is INVALID */ - ep_TD[num].next_dTD = 0x01 ; - } - else - { - /* init EP capabilities */ - ep_QH[num].cap = QH_MAXP(0x400) | QH_ZLT; - } - /* setup EP control register */ - if (pEPD->bEndpointAddress & 0x80) - { - ep_cfg &= ~0xFFFF0000; - ep_cfg |= EPCTRL_TX_TYPE(bmAttributes) - | EPCTRL_TXR; - } - else - { - ep_cfg &= ~0xFFFF; - ep_cfg |= EPCTRL_RX_TYPE(bmAttributes) - | EPCTRL_RXR; - } - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] = ep_cfg; - return; -} - -/* - * Set Direction for USB Control Endpoint - * Parameters: dir: Out (dir == 0), In (dir <> 0) - * Return Value: None - */ - -void USB_DirCtrlEP (uint32_t dir) { - /* Not needed */ - ( void ) dir; -} - - -/* - * Enable USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_EnableEP (uint32_t EPNum) { - uint32_t lep, bitpos; - - lep = EPNum & 0x0F; - - if (EPNum & 0x80) - { - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXE; - } - else - { - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXE; - /* enable NAK interrupt */ - bitpos = USB_EP_BITPOS(EPNum); - LPC_USB->ENDPTNAKEN |= (1<ENDPTCTRL0))[lep] &= ~EPCTRL_TXE; - } - else - { - /* disable NAK interrupt */ - bitpos = USB_EP_BITPOS(EPNum); - LPC_USB->ENDPTNAKEN &= ~(1<ENDPTCTRL0))[lep] &= ~EPCTRL_RXE; - } -} - -/* - * Reset USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_ResetEP (uint32_t EPNum) { - uint32_t bit_pos = USB_EP_BITPOS(EPNum); - uint32_t lep = EPNum & 0x0F; - - /* flush EP buffers */ - LPC_USB->ENDPTFLUSH = (1<ENDPTFLUSH & (1<ENDPTCTRL0))[lep] |= EPCTRL_TXR; - } - else - { - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXR; - } -} - -/* - * Set Stall for USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_SetStallEP (uint32_t EPNum) { - uint32_t lep; - - lep = EPNum & 0x0F; - if (EPNum & 0x80) - { - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXS; - } - else - { - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXS; - } -} - -/* - * Clear Stall for USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USB_ClrStallEP (uint32_t EPNum) { - uint32_t lep; - - lep = EPNum & 0x0F; - if (EPNum & 0x80) - { - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] &= ~EPCTRL_TXS; - /* reset data toggle */ - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXR; - } - else - { - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] &= ~EPCTRL_RXS; - /* reset data toggle */ - ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXR; - } -} - -/* - * Process DTD - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Buffer pointer - * Transfer buffer size - * Return Value: None - */ -void USB_ProgDTD(uint32_t Edpt, uint32_t ptrBuff, uint32_t TsfSize) -{ - DTD_T* pDTD; - - pDTD = (DTD_T*)&ep_TD[ Edpt ]; - - /* Zero out the device transfer descriptors */ - memset((void*)pDTD, 0, sizeof(DTD_T)); - /* The next DTD pointer is INVALID */ - pDTD->next_dTD = 0x01 ; - - /* Length */ - pDTD->total_bytes = ((TsfSize & 0x7fff) << 16); - pDTD->total_bytes |= TD_IOC ; - pDTD->total_bytes |= 0x80 ; - - pDTD->buffer0 = ptrBuff; - pDTD->buffer1 = (ptrBuff + 0x1000) & 0xfffff000; - pDTD->buffer2 = (ptrBuff + 0x2000) & 0xfffff000; - pDTD->buffer3 = (ptrBuff + 0x3000) & 0xfffff000; - pDTD->buffer4 = (ptrBuff + 0x4000) & 0xfffff000; - - ep_QH[Edpt].next_dTD = (uint32_t)(&ep_TD[ Edpt ]); - ep_QH[Edpt].total_bytes &= (~0xC0) ; -} - -/* -* Read USB Endpoint Data -* Parameters: EPNum: Endpoint Number -* EPNum.0..3: Address -* EPNum.7: Dir -* pData: Pointer to Data Buffer -* Return Value: Number of bytes read -*/ -uint32_t USB_ReadSetupPkt(uint32_t EPNum, uint32_t *pData) -{ - uint32_t setup_int, cnt = 0; - uint32_t num = EPAdr(EPNum); - - setup_int = LPC_USB->ENDPTSETUPSTAT ; - /* Clear the setup interrupt */ - LPC_USB->ENDPTSETUPSTAT = setup_int; - - /* ********************************** */ - /* Check if we have received a setup */ - /* ********************************** */ - if (setup_int & (1<<0)) /* Check only for bit 0 */ - /* No setup are admitted on other endpoints than 0 */ - { - do - { - /* Setup in a setup - must considere only the second setup */ - /*- Set the tripwire */ - LPC_USB->USBCMD_D |= USBCMD_SUTW ; - - /* Transfer Set-up data to the gtmudsCore_Request buffer */ - pData[0] = ep_QH[num].setup[0]; - pData[1] = ep_QH[num].setup[1]; - cnt = 8; - - } - while (!(LPC_USB->USBCMD_D & USBCMD_SUTW)) ; - - /* setup in a setup - Clear the tripwire */ - LPC_USB->USBCMD_D &= (~USBCMD_SUTW); - } - while ((setup_int = LPC_USB->ENDPTSETUPSTAT) != 0) - { - /* Clear the setup interrupt */ - LPC_USB->ENDPTSETUPSTAT = setup_int; - } - return cnt; -} - -/* -* Enque read request -* Parameters: EPNum: Endpoint Number -* EPNum.0..3: Address -* EPNum.7: Dir -* pData: Pointer to Data Buffer -* Return Value: Number of bytes read -*/ - -uint32_t USB_ReadReqEP(uint32_t EPNum, uint8_t *pData, uint32_t len) -{ - uint32_t num = EPAdr(EPNum); - uint32_t n = USB_EP_BITPOS(EPNum); - - USB_ProgDTD(num, (uint32_t)pData, len); - ep_read_len[EPNum & 0x0F] = len; - /* prime the endpoint for read */ - LPC_USB->ENDPTPRIME |= (1<total_bytes >> 16) & 0x7FFF; - cnt = ep_read_len[EPNum & 0x0F] - cnt; - return (cnt); -} - -/* -* Write USB Endpoint Data -* Parameters: EPNum: Endpoint Number -* EPNum.0..3: Address -* EPNum.7: Dir -* pData: Pointer to Data Buffer -* cnt: Number of bytes to write -* Return Value: Number of bytes written -*/ -uint32_t USB_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt) -{ - uint32_t x = 0, n = USB_EP_BITPOS(EPNum); - - USB_ProgDTD(EPAdr(EPNum), (uint32_t)pData, cnt); - /* prime the endpoint for transmit */ - LPC_USB->ENDPTPRIME |= (1<ENDPTPRIME & (1<USBSTS_D; /* Device Interrupt Status */ - LPC_USB->USBSTS_D = disr; - -// printf("USB interrupt: 0x%08x\n",disr); - -// LPC_UART1->THR = 'U'; -// LPC_UART1->THR = 'S'; -// LPC_UART1->THR = 'B'; -// LPC_UART1->THR = '\n'; - - - /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */ - if (disr & USBSTS_URI) /* Reset */ - { -// LPC_UART1->THR = 'R'; -// LPC_UART1->THR = '\n'; - USB_Reset(); - if (g_drv.USB_Reset_Event) - g_drv.USB_Reset_Event(); - return; - //goto isr_end; - } - - if (disr & USBSTS_SLI) /* Suspend */ - { -// LPC_UART1->THR = 'U'; -// LPC_UART1->THR = '\n'; - if (g_drv.USB_Suspend_Event) - g_drv.USB_Suspend_Event(); - } - - if (disr & USBSTS_PCI) /* Resume */ - { -// LPC_UART1->THR = 'P'; -// LPC_UART1->THR = '\n'; - /* check if device isoperating in HS mode or full speed */ - if (LPC_USB->PORTSC1_D & (1<<9)) - DevStatusFS2HS = TRUE; - - if (g_drv.USB_Resume_Event) - g_drv.USB_Resume_Event(); - } - - /* handle setup status interrupts */ - val = LPC_USB->ENDPTSETUPSTAT; - /* Only EP0 will have setup packets so call EP0 handler */ - if (val) - { -// LPC_UART1->THR = 'S'; -// LPC_UART1->THR = '\n'; - /* Clear the endpoint complete CTRL OUT & IN when */ - /* a Setup is received */ - LPC_USB->ENDPTCOMPLETE = 0x00010001; - /* enable NAK inetrrupts */ - LPC_USB->ENDPTNAKEN |= 0x00010001; - if (g_drv.USB_P_EP[0]){ -// LPC_UART1->THR = 's'; -// LPC_UART1->THR = '\n'; - g_drv.USB_P_EP[0](USB_EVT_SETUP); - } - } - - /* handle completion interrupts */ - val = LPC_USB->ENDPTCOMPLETE; - if (val) - { -// LPC_UART1->THR = 'C'; -// LPC_UART1->THR = '\n'; - - LPC_USB->ENDPTNAK = val; - for (n = 0; n < EP_NUM_MAX / 2; n++) - { - if (val & (1<ENDPTCOMPLETE = (1<ENDPTCOMPLETE = (1<<(n + 16)); - } - } - } - - if (disr & USBSTS_NAKI) - { -// LPC_UART1->THR = 'N'; -// LPC_UART1->THR = '\n'; - val = LPC_USB->ENDPTNAK; - val &= LPC_USB->ENDPTNAKEN; - /* handle NAK interrupts */ - if (val) - { - for (n = 0; n < EP_NUM_MAX / 2; n++) - { - if (val & (1<ENDPTNAK = val; - } - } - - /* Start of Frame Interrupt */ - if (disr & USBSTS_SRI) - { -// LPC_UART1->THR = 'F'; -// LPC_UART1->THR = '\n'; - if (g_drv.USB_SOF_Event) - g_drv.USB_SOF_Event(); - } - - /* Error Interrupt */ - if (disr & USBSTS_UEI) - { -// LPC_UART1->THR = 'E'; -// LPC_UART1->THR = '\n'; - if (g_drv.USB_Error_Event) - g_drv.USB_Error_Event(disr); - } - -// LPC_UART1->THR = 'r'; -// LPC_UART1->THR = '\n'; -//isr_end: -// LPC_VIC->VectAddr = 0; /* Acknowledge Interrupt */ - return; -} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbuser.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbuser.c deleted file mode 100644 index b0226ac2a..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbuser.c +++ /dev/null @@ -1,221 +0,0 @@ -/*---------------------------------------------------------------------------- - * U S B - K e r n e l - *---------------------------------------------------------------------------- - * Name: usbuser.c - * Purpose: USB Custom User Module - * Version: V1.20 - *---------------------------------------------------------------------------- - * This software is supplied "AS IS" without any warranties, express, - * implied or statutory, including but not limited to the implied - * warranties of fitness for purpose, satisfactory quality and - * noninfringement. Keil extends you a royalty-free right to reproduce - * and distribute executable files created using this software for use - * on NXP Semiconductors LPC family microcontroller devices only. Nothing - * else gives you the right to use this software. - * - * Copyright (c) 2009 Keil - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include "lpc18xx.H" -#include "lpc_types.h" - -#include "usb.h" -#include "usbcfg.h" -#include "usbhw.h" -#include "usbcore.h" -#include "usbuser.h" -#include "cdcuser.h" - - - -/* - * USB Power Event Callback - * Called automatically on USB Power Event - * Parameter: power: On(TRUE)/Off(FALSE) - */ - -#if USB_POWER_EVENT -void USB_Power_Event (uint32_t power) { -} -#endif - - -/* - * USB Reset Event Callback - * Called automatically on USB Reset Event - */ - -#if USB_RESET_EVENT -void USB_Reset_Event (void) { - USB_ResetCore(); -} -#endif - - -/* - * USB Suspend Event Callback - * Called automatically on USB Suspend Event - */ - -#if USB_SUSPEND_EVENT -void USB_Suspend_Event (void) { -} -#endif - - -/* - * USB Resume Event Callback - * Called automatically on USB Resume Event - */ - -#if USB_RESUME_EVENT -void USB_Resume_Event (void) { -} -#endif - - -/* - * USB Remote Wakeup Event Callback - * Called automatically on USB Remote Wakeup Event - */ - -#if USB_WAKEUP_EVENT -void USB_WakeUp_Event (void) { -} -#endif - - -/* - * USB Start of Frame Event Callback - * Called automatically on USB Start of Frame Event - */ - -#if USB_SOF_EVENT -void USB_SOF_Event (void) { -} -#endif - - -/* - * USB Error Event Callback - * Called automatically on USB Error Event - * Parameter: error: Error Code - */ - -#if USB_ERROR_EVENT -void USB_Error_Event (uint32_t error) { -} -#endif - - -/* - * USB Set Configuration Event Callback - * Called automatically on USB Set Configuration Request - */ - -#if USB_CONFIGURE_EVENT -void USB_Configure_Event (void) { - - if (USB_Configuration) { /* Check if USB is configured */ - /* add your code here */ - } -} -#endif - - -/* - * USB Set Interface Event Callback - * Called automatically on USB Set Interface Request - */ - -#if USB_INTERFACE_EVENT -void USB_Interface_Event (void) { -} -#endif - - -/* - * USB Set/Clear Feature Event Callback - * Called automatically on USB Set/Clear Feature Request - */ - -#if USB_FEATURE_EVENT -void USB_Feature_Event (void) { -} -#endif - - -#define P_EP(n) ((USB_EP_EVENT & (1 << (n))) ? USB_EndPoint##n : NULL) - -/* USB Endpoint Events Callback Pointers */ -void (* const USB_P_EP[USB_EP_NUM]) (uint32_t event) = { - P_EP(0), - P_EP(1), - P_EP(2), - P_EP(3), -}; - - -/* - * USB Endpoint 1 Event Callback - * Called automatically on USB Endpoint 1 Event - * Parameter: event - */ - -void USB_EndPoint1 (uint32_t event) { - ( void ) event; -} - - -/* - * USB Endpoint 2 Event Callback - * Called automatically on USB Endpoint 2 Event - * Parameter: event - */ - -void USB_EndPoint2 (uint32_t event) { - switch (event) { - case USB_EVT_OUT_NAK: - CDC_BulkOutNak(); - break; - case USB_EVT_OUT: - CDC_BulkOut (); /* data received from Host */ - break; - case USB_EVT_IN: - CDC_BulkIn (); /* data expected from Host */ - break; - } -} - - -/* - * USB Endpoint 3 Event Callback - * Called automatically on USB Endpoint 3 Event - * Parameter: event - */ - -void USB_EndPoint3 (uint32_t event) { - ( void ) event; -} - - -/* - * USB Endpoint 4 Event Callback - * Called automatically on USB Endpoint 4 Event - * Parameter: event - */ - -void USB_EndPoint4 (uint32_t event) { - ( void ) event; -} - - -/* - * USB Endpoint 5 Event Callback - * Called automatically on USB Endpoint 5 Event - * Parameter: event - */ - -void USB_EndPoint5 (uint32_t event) { - ( void ) event; -} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/board.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/board.h deleted file mode 100644 index 38067a949..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/board.h +++ /dev/null @@ -1,3 +0,0 @@ -/* The name of this header file is set by the trace recorder code, but the name -of the actual header file is used below. */ -#include "lpc18xx.h" diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/cr_startup_lpc18xx.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/cr_startup_lpc18xx.c deleted file mode 100644 index 13853fc1d..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/cr_startup_lpc18xx.c +++ /dev/null @@ -1,531 +0,0 @@ -// ***************************************************************************** -// +--+ -// | ++----+ -// +-++ | -// | | -// +-+--+ | -// | +--+--+ -// +----+ Copyright (c) 2011-12 Code Red Technologies Ltd. -// -// LPC43xx Microcontroller Startup code for use with Red Suite -// -// Version : 120430 -// -// Software License Agreement -// -// The software is owned by Code Red Technologies and/or its suppliers, and is -// protected under applicable copyright laws. All rights are reserved. Any -// use in violation of the foregoing restrictions may subject the user to criminal -// sanctions under applicable laws, as well as to civil liability for the breach -// of the terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT -// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH -// CODE RED TECHNOLOGIES LTD. -// -// ***************************************************************************** - -#include "stdint.h" - -#if defined(__cplusplus) -#ifdef __REDLIB__ -#error Redlib does not support C++ -#else -// ***************************************************************************** -// -// The entry point for the C++ library startup -// -// ***************************************************************************** -extern "C" { -extern void __libc_init_array(void); - -} -#endif -#endif - -#define WEAK __attribute__ ((weak)) -#define ALIAS(f) __attribute__ ((weak, alias(# f))) - -// Code Red - if CMSIS is being used, then SystemInit() routine -// will be called by startup code rather than in application's main() -extern void SystemInit(void); - -// ***************************************************************************** -#if defined(__cplusplus) -extern "C" { -#endif - -// ***************************************************************************** -// -// Forward declaration of the default handlers. These are aliased. -// When the application defines a handler (with the same name), this will -// automatically take precedence over these weak definitions -// -// ***************************************************************************** -void ResetISR(void); -WEAK void NMI_Handler(void); -WEAK void HardFault_Handler(void); -WEAK void MemManage_Handler(void); -WEAK void BusFault_Handler(void); -WEAK void UsageFault_Handler(void); -WEAK void SVC_Handler(void); -WEAK void DebugMon_Handler(void); -WEAK void PendSV_Handler(void); -WEAK void SysTick_Handler(void); -WEAK void IntDefaultHandler(void); - -//***************************************************************************** -// -// Forward declaration of the specific IRQ handlers. These are aliased -// to the IntDefaultHandler, which is a 'forever' loop. When the application -// defines a handler (with the same name), this will automatically take -// precedence over these weak definitions -// -//***************************************************************************** -void DAC_IRQHandler(void) ALIAS(IntDefaultHandler); -void MX_CORE_IRQHandler(void) ALIAS(IntDefaultHandler); -void DMA_IRQHandler(void) ALIAS(IntDefaultHandler); -void FLASHEEPROM_IRQHandler(void) ALIAS(IntDefaultHandler); -void ETH_IRQHandler(void) ALIAS(IntDefaultHandler); -void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler); -void LCD_IRQHandler(void) ALIAS(IntDefaultHandler); -void USB0_IRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_IRQHandler(void) ALIAS(IntDefaultHandler); -void SCT_IRQHandler(void) ALIAS(IntDefaultHandler); -void RIT_IRQHandler(void) ALIAS(IntDefaultHandler); -void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler); -void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler); -void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler); -void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler); -void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler); -void SPI_IRQHandler (void) ALIAS(IntDefaultHandler); -void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler); -void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler); -void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART0_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART1_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART2_IRQHandler(void) ALIAS(IntDefaultHandler); -void UART3_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler); -void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler); -void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler); -void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler); -void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler); -void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler); -void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler); -void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler); -void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler); -void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler); -void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler); -void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler); -void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler); -void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler); -void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler); -void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler); -void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler); -void RTC_IRQHandler(void) ALIAS(IntDefaultHandler); -void WDT_IRQHandler(void) ALIAS(IntDefaultHandler); -void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler); -void QEI_IRQHandler(void) ALIAS(IntDefaultHandler); - -//***************************************************************************** -// -// The entry point for the application. -// __main() is the entry point for Redlib based applications -// main() is the entry point for Newlib based applications -// -//***************************************************************************** -#if defined (__REDLIB__) -extern void __main(void); -#endif -extern int main(void); -//***************************************************************************** -// -// External declaration for the pointer to the stack top from the Linker Script -// -//***************************************************************************** -extern void _vStackTop(void); - -//***************************************************************************** -#if defined (__cplusplus) -} // extern "C" -#endif -//***************************************************************************** -// -// The vector table. -// This relies on the linker script to place at correct location in memory. -// -// ***************************************************************************** -extern void(*const g_pfnVectors[]) (void); -__attribute__ ((section(".isr_vector"))) -void(*const g_pfnVectors[]) (void) = { - // Core Level - CM4/CM3 - &_vStackTop, // The initial stack pointer - ResetISR, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - MemManage_Handler, // The MPU fault handler - BusFault_Handler, // The bus fault handler - UsageFault_Handler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall handler - DebugMon_Handler, // Debug monitor handler - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - // Chip Level - LPC18xx/43xx - DAC_IRQHandler, // 16 D/A Converter - MX_CORE_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY) - DMA_IRQHandler, // 18 General Purpose DMA - 0, // 19 Reserved - FLASHEEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts - ETH_IRQHandler, // 21 Ethernet - SDIO_IRQHandler, // 22 SD/MMC - LCD_IRQHandler, // 23 LCD - USB0_IRQHandler, // 24 USB0 - USB1_IRQHandler, // 25 USB1 - SCT_IRQHandler, // 26 State Configurable Timer - RIT_IRQHandler, // 27 Repetitive Interrupt Timer - TIMER0_IRQHandler, // 28 Timer0 - TIMER1_IRQHandler, // 29 Timer 1 - TIMER2_IRQHandler, // 30 Timer 2 - TIMER3_IRQHandler, // 31 Timer 3 - MCPWM_IRQHandler, // 32 Motor Control PWM - ADC0_IRQHandler, // 33 A/D Converter 0 - I2C0_IRQHandler, // 34 I2C0 - I2C1_IRQHandler, // 35 I2C1 - SPI_IRQHandler, // 36 SPI (LPC43XX ONLY) - ADC1_IRQHandler, // 37 A/D Converter 1 - SSP0_IRQHandler, // 38 SSP0 - SSP1_IRQHandler, // 39 SSP1 - UART0_IRQHandler, // 40 UART0 - UART1_IRQHandler, // 41 UART1 - UART2_IRQHandler, // 42 UART2 - UART3_IRQHandler, // 43 USRT3 - I2S0_IRQHandler, // 44 I2S0 - I2S1_IRQHandler, // 45 I2S1 - SPIFI_IRQHandler, // 46 SPI Flash Interface - SGPIO_IRQHandler, // 47 SGPIO (LPC43XX ONLY) - GPIO0_IRQHandler, // 48 GPIO0 - GPIO1_IRQHandler, // 49 GPIO1 - GPIO2_IRQHandler, // 50 GPIO2 - GPIO3_IRQHandler, // 51 GPIO3 - GPIO4_IRQHandler, // 52 GPIO4 - GPIO5_IRQHandler, // 53 GPIO5 - GPIO6_IRQHandler, // 54 GPIO6 - GPIO7_IRQHandler, // 55 GPIO7 - GINT0_IRQHandler, // 56 GINT0 - GINT1_IRQHandler, // 57 GINT1 - EVRT_IRQHandler, // 58 Event Router - CAN1_IRQHandler, // 59 C_CAN1 - 0, // 60 Reserved - 0, // 61 Reserved - ATIMER_IRQHandler, // 62 ATIMER - RTC_IRQHandler, // 63 RTC - 0, // 64 Reserved - WDT_IRQHandler, // 65 WDT - 0, // 66 Reserved - CAN0_IRQHandler, // 67 C_CAN0 - QEI_IRQHandler, // 68 QEI -}; - -//***************************************************************************** -// Functions to carry out the initialization of RW and BSS data sections. These -// are written as separate functions rather than being inlined within the -// ResetISR() function in order to cope with MCUs with multiple banks of -// memory. -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void data_init(unsigned int romstart, unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int *pulSrc = (unsigned int*) romstart; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = *pulSrc++; -} - -__attribute__ ((section(".after_vectors"))) -void bss_init(unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = 0; -} - -//***************************************************************************** -// The following symbols are constructs generated by the linker, indicating -// the location of various points in the "Global Section Table". This table is -// created by the linker via the Code Red managed linker script mechanism. It -// contains the load address, execution address and length of each RW data -// section and the execution and length of each BSS (zero initialized) section. -//***************************************************************************** -extern unsigned int __data_section_table; -extern unsigned int __data_section_table_end; -extern unsigned int __bss_section_table; -extern unsigned int __bss_section_table_end; - -//***************************************************************************** -// Reset entry point for your code. -// Sets up a simple runtime environment and initializes the C/C++ -// library. -// -//***************************************************************************** -void -ResetISR(void) { - -// ************************************************************* -// The following conditional block of code manually resets as -// much of the peripheral set of the LPC18 as possible. This is -// done because the LPC18 does not provide a means of triggering -// a full system reset under debugger control, which can cause -// problems in certain circumstances when debugging. -// -// You can prevent this code block being included if you require -// (for example when creating a final executable which you will -// not debug) by setting the define 'DONT_RESET_ON_RESTART'. -// -#ifndef DONT_RESET_ON_RESTART - - // Disable interrupts - __asm volatile ("cpsid i"); - // equivalent to CMSIS '__disable_irq()' function - - unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100; - // LPC_RGU->RESET_CTRL0 @ 0x40053100 - // LPC_RGU->RESET_CTRL1 @ 0x40053104 - // Note that we do not use the CMSIS register access mechanism, - // as there is no guarantee that the project has been configured - // to use CMSIS. - - // Write to LPC_RGU->RESET_CTRL0 - *(RESET_CONTROL+0) = 0x10DF0000; - // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST| - // USB1_RST|USB0_RST|LCD_RST - - // Write to LPC_RGU->RESET_CTRL1 - *(RESET_CONTROL+1) = 0x00DFF7FF; - // CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST| - // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST| - // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST| - // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST - - // Clear all pending interrupts in the NVIC - volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280; - unsigned int irqpendloop; - for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) { - *(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF; - } - - // Reenable interrupts - __asm volatile ("cpsie i"); - // equivalent to CMSIS '__enable_irq()' function - -#endif // ifndef DONT_RESET_ON_RESTART -// ************************************************************* - - - // - // Copy the data sections from flash to SRAM. - // - unsigned int LoadAddr, ExeAddr, SectionLen; - unsigned int *SectionTableAddr; - - // Load base address of Global Section Table - SectionTableAddr = &__data_section_table; - - // Copy the data sections from flash to SRAM. - while (SectionTableAddr < &__data_section_table_end) { - LoadAddr = *SectionTableAddr++; - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - data_init(LoadAddr, ExeAddr, SectionLen); - } - // At this point, SectionTableAddr = &__bss_section_table; - // Zero fill the bss segment - while (SectionTableAddr < &__bss_section_table_end) { - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - bss_init(ExeAddr, SectionLen); - } - - // ****************************** - // Check to see if we are running the code from a non-zero - // address (eg RAM, external flash), in which case we need - // to modify the VTOR register to tell the CPU that the - // vector table is located at a non-0x0 address. - - // Note that we do not use the CMSIS register access mechanism, - // as there is no guarantee that the project has been configured - // to use CMSIS. - unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; - if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { - // CMSIS : SCB->VTOR =
- *pSCB_VTOR = (unsigned int)g_pfnVectors; - } - -#ifdef __USE_CMSIS - SystemInit(); -#endif - -#if defined (__cplusplus) - // - // Call C++ library initialisation - // - __libc_init_array(); -#endif - -#if defined (__REDLIB__) - // Call the Redlib library, which in turn calls main() - __main() ; -#else - main(); -#endif - - // - // main() shouldn't return, but if it does, we'll just enter an infinite loop - // - while (1) { - ; - } -} - -//***************************************************************************** -// Default exception handlers. Override the ones here by defining your own -// handler routines in your application code. -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void NMI_Handler(void) -{ - while(1) - { - } -} -__attribute__ ((section(".after_vectors"))) -void HardFault_Handler(void) -{ - __asm volatile - ( - " tst lr, #4 \n" - " ite eq \n" - " mrseq r0, msp \n" - " mrsne r0, psp \n" - " ldr r1, [r0, #24] \n" - " ldr r2, handler2_address_const \n" - " bx r2 \n" - " handler2_address_const: .word prvGetRegistersFromStack \n" - ); -} - -__attribute__ ((section(".after_vectors"))) -void MemManage_Handler(void) -{ - while(1) - { - } -} -__attribute__ ((section(".after_vectors"))) -void BusFault_Handler(void) -{ - while(1) - { - } -} -__attribute__ ((section(".after_vectors"))) -void UsageFault_Handler(void) -{ - while(1) - { - } -} -__attribute__ ((section(".after_vectors"))) -void SVCall_Handler(void) -{ - while(1) - { - } -} -__attribute__ ((section(".after_vectors"))) -void DebugMon_Handler(void) -{ - while(1) - { - } -} -__attribute__ ((section(".after_vectors"))) -void PendSV_Handler(void) -{ - while(1) - { - } -} -__attribute__ ((section(".after_vectors"))) -void SysTick_Handler(void) -{ - while(1) - { - } -} - -//***************************************************************************** -// -// Processor ends up here if an unexpected interrupt occurs or a specific -// handler is not present in the application code. -// -//***************************************************************************** -__attribute__ ((section(".after_vectors"))) -void IntDefaultHandler(void) -{ - while(1) - { - } -} - -/* Debug functions. */ -void prvGetRegistersFromStack( uint32_t *pulFaultStackAddress ) -{ -/* These are volatile to try and prevent the compiler/linker optimising them -away as the variables never actually get used. If the debugger won't show the -values of the variables, make them global my moving their declaration outside -of this function. */ -volatile uint32_t r0; -volatile uint32_t r1; -volatile uint32_t r2; -volatile uint32_t r3; -volatile uint32_t r12; -volatile uint32_t lr; /* Link register. */ -volatile uint32_t pc; /* Program counter. */ -volatile uint32_t psr;/* Program status register. */ - - r0 = pulFaultStackAddress[ 0 ]; - r1 = pulFaultStackAddress[ 1 ]; - r2 = pulFaultStackAddress[ 2 ]; - r3 = pulFaultStackAddress[ 3 ]; - - r12 = pulFaultStackAddress[ 4 ]; - lr = pulFaultStackAddress[ 5 ]; - pc = pulFaultStackAddress[ 6 ]; - psr = pulFaultStackAddress[ 7 ]; - - /* When the following line is hit, the variables contain the register values. */ - for( ;; ) - { - ( void ) r0; - ( void ) r1; - ( void ) r2; - ( void ) r3; - ( void ) r12; - ( void ) lr; - ( void ) pc; - ( void ) psr; - }; -} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/main.c deleted file mode 100644 index 027c2e166..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/main.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ -/* Standard includes. */ -#include -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "queue.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_Sockets.h" - -/* Example includes. */ -#include "TwoEchoClients.h" -#include "CDCCommandConsole.h" - -/* Library includes. */ -#include "LPC18xx.h" - -/* The size of the stack and the priority used by the two echo client tasks. */ -#define mainECHO_CLIENT_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) -#define mainECHO_CLIENT_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The size of the stack and the priority used by the USB CDC command console -task. */ -#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) -#define mainCDC_COMMAND_CONSOLE_TASK_PRIORITY ( 4U ) - -/* -* Register commands that can be used with FreeRTOS+CLI. The commands are -* defined in CLI-commands.c. -*/ -extern void vRegisterCLICommands( void ); - -/* - * Initialise the LED ports, and create a timer that periodically toggles an LED - * just to provide a visual indication that the program is running. - */ -extern void vLEDsInitialise( void ); - -/*-----------------------------------------------------------*/ - -/* The default IP and MAC address used by the demo. The address configuration -defined here will be used if ipconfigUSE_DHCP is 0, or if ipconfigUSE_DHCP is -1 but a DHCP server could not be contacted. See the online documentation for -more information. */ -static const uint8_t ucIPAddress[ 4 ] = { configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 }; -static const uint8_t ucNetMask[ 4 ] = { configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 }; -static const uint8_t ucGatewayAddress[ 4 ] = { configGATEWAY_ADDR0, configGATEWAY_ADDR1, configGATEWAY_ADDR2, configGATEWAY_ADDR3 }; -static const uint8_t ucDNSServerAddress[ 4 ] = { configDNS_SERVER_ADDR0, configDNS_SERVER_ADDR1, configDNS_SERVER_ADDR2, configDNS_SERVER_ADDR3 }; - -/* The MAC address used by the demo. In production units the MAC address would -probably be read from flash memory or an EEPROM. Here it is just hard coded. */ -const uint8_t ucMACAddress[ 6 ] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 }; - -/*-----------------------------------------------------------*/ - - -/****************************************************************************** - * - * See the following web page for information on using this demo. - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_and_CLI_LPC1830_NGX.shtml - * - ******************************************************************************/ - - -int main( void ) -{ - /* Prepare the trace recorder library. */ - #if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 - vTraceInitTraceData(); - #endif - - /* The examples assume that all priority bits are assigned as preemption - priority bits. */ - NVIC_SetPriorityGrouping( 0UL ); - - /* Start the timer that just toggles an LED to show the demo is running. */ - vLEDsInitialise(); - - /* Start the tasks that implements the command console on the UART, as - described above. */ - vCDCCommandConsoleStart( mainCDC_COMMAND_CONSOLE_STACK_SIZE, mainCDC_COMMAND_CONSOLE_TASK_PRIORITY ); - - /* Register CLI commands. */ - vRegisterCLICommands(); - - /* Initialise the network interface. Tasks that use the network are - created in the network event hook when the network is connected and ready - for use. The address values passed in here are used if ipconfigUSE_DHCP is - set to 0, or if ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be - contacted. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); - - /* If the trace recorder code is included... */ - #if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 - { - extern xQueueHandle xNetworkEventQueue; - - /* Name the queue for viewing in FreeRTOS+Trace. */ - vTraceSetQueueName( xNetworkEventQueue, "IPStackEvent" ); - } - #endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 */ - - /* Start the FreeRTOS scheduler. */ - vTaskStartScheduler(); - - /* The following line should never execute. If it does, it means there was - insufficient FreeRTOS heap memory available to create the Idle and/or timer - tasks. See the memory management section on the http://www.FreeRTOS.org web - site for more information. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( xTaskHandle pxTask, char *pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the - size of the heap available to pvPortMalloc() is defined by - configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() - API function can be used to query the size of free heap space that remains - (although it does not provide information on how the remaining heap might - be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} -/*-----------------------------------------------------------*/ - -/* Called by FreeRTOS+UDP when the network connects. */ -void vApplicationIPNetworkEventHook( eIPCallbackEvent_t eNetworkEvent ) -{ -static BaseType_t xTaskAlreadyCreated = pdFALSE; - - if( eNetworkEvent == eNetworkUp ) - { - /* Create the tasks that transmit to and receive from a standard - echo server (see the web documentation for this port) in both - standard and zero copy mode. */ - if( xTaskAlreadyCreated == pdFALSE ) - { - vStartEchoClientTasks( mainECHO_CLIENT_TASK_STACK_SIZE, mainECHO_CLIENT_TASK_PRIORITY ); - xTaskAlreadyCreated = pdTRUE; - } - } -} -/*-----------------------------------------------------------*/ - -/* Called by FreeRTOS+UDP when a reply is received to an outgoing ping request. */ -void vApplicationPingReplyHook( ePingReplyStatus_t eStatus, uint16_t usIdentifier ) -{ -static const char *pcSuccess = "\r\n\r\nPing reply received - "; -static const char *pcInvalidChecksum = "\r\n\r\nPing reply received with invalid checksum - "; -static const char *pcInvalidData = "\r\n\r\nPing reply received with invalid data - "; -static char cMessage[ 50 ]; -void vOutputString( const char * const pcMessage ); - - switch( eStatus ) - { - case eSuccess : - vOutputString( pcSuccess ); - break; - - case eInvalidChecksum : - vOutputString( pcInvalidChecksum ); - break; - - case eInvalidData : - vOutputString( pcInvalidData ); - break; - - default : - /* It is not possible to get here as all enums have their own - case. */ - break; - } - - sprintf( cMessage, "identifier %d\r\n\r\n", ( int ) usIdentifier ); - vOutputString( cMessage ); -} - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/printf-stdarg.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/printf-stdarg.c deleted file mode 100644 index 9bfc45a5c..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/printf-stdarg.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - Copyright 2001, 2002 Georges Menie (www.menie.org) - stdarg version contributed by Christian Ettinger - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU Lesser General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -/* - putchar is the only external dependency for this file, - if you have a working putchar, leave it commented out. - If not, uncomment the define below and - replace outbyte(c) by your own function call. - -*/ - -#define putchar(c) c - -#include - -static void printchar(char **str, int c) -{ - //extern int putchar(int c); - - if (str) { - **str = (char)c; - ++(*str); - } - else - { - (void)putchar(c); - } -} - -#define PAD_RIGHT 1 -#define PAD_ZERO 2 - -static int prints(char **out, const char *string, int width, int pad) -{ - register int pc = 0, padchar = ' '; - - if (width > 0) { - register int len = 0; - register const char *ptr; - for (ptr = string; *ptr; ++ptr) ++len; - if (len >= width) width = 0; - else width -= len; - if (pad & PAD_ZERO) padchar = '0'; - } - if (!(pad & PAD_RIGHT)) { - for ( ; width > 0; --width) { - printchar (out, padchar); - ++pc; - } - } - for ( ; *string ; ++string) { - printchar (out, *string); - ++pc; - } - for ( ; width > 0; --width) { - printchar (out, padchar); - ++pc; - } - - return pc; -} - -/* the following should be enough for 32 bit int */ -#define PRINT_BUF_LEN 12 - -static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase) -{ - char print_buf[PRINT_BUF_LEN]; - register char *s; - register int t, neg = 0, pc = 0; - register unsigned int u = (unsigned int)i; - - if (i == 0) { - print_buf[0] = '0'; - print_buf[1] = '\0'; - return prints (out, print_buf, width, pad); - } - - if (sg && b == 10 && i < 0) { - neg = 1; - u = (unsigned int)-i; - } - - s = print_buf + PRINT_BUF_LEN-1; - *s = '\0'; - - while (u) { - t = (unsigned int)u % b; - if( t >= 10 ) - t += letbase - '0' - 10; - *--s = (char)(t + '0'); - u /= b; - } - - if (neg) { - if( width && (pad & PAD_ZERO) ) { - printchar (out, '-'); - ++pc; - --width; - } - else { - *--s = '-'; - } - } - - return pc + prints (out, s, width, pad); -} - -static int print( char **out, const char *format, va_list args ) -{ - register int width, pad; - register int pc = 0; - char scr[2]; - - for (; *format != 0; ++format) { - if (*format == '%') { - ++format; - width = pad = 0; - if (*format == '\0') break; - if (*format == '%') goto out; - if (*format == '-') { - ++format; - pad = PAD_RIGHT; - } - while (*format == '0') { - ++format; - pad |= PAD_ZERO; - } - for ( ; *format >= '0' && *format <= '9'; ++format) { - width *= 10; - width += *format - '0'; - } - if( *format == 's' ) { - register char *s = (char *)va_arg( args, int ); - pc += prints (out, s?s:"(null)", width, pad); - continue; - } - if( *format == 'd' || *format == 'i' ) { - pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a'); - continue; - } - if( *format == 'x' ) { - pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a'); - continue; - } - if( *format == 'X' ) { - pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A'); - continue; - } - if( *format == 'u' ) { - pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a'); - continue; - } - if( *format == 'c' ) { - /* char are converted to int then pushed on the stack */ - scr[0] = (char)va_arg( args, int ); - scr[1] = '\0'; - pc += prints (out, scr, width, pad); - continue; - } - } - else { - out: - printchar (out, *format); - ++pc; - } - } - if (out) **out = '\0'; - va_end( args ); - return pc; -} - -int printf(const char *format, ...) -{ - va_list args; - - va_start( args, format ); - return print( 0, format, args ); -} - -int sprintf(char *out, const char *format, ...) -{ - va_list args; - - va_start( args, format ); - return print( &out, format, args ); -} - - -int snprintf( char *buf, unsigned int count, const char *format, ... ) -{ - va_list args; - - ( void ) count; - - va_start( args, format ); - return print( &buf, format, args ); -} - -#ifdef TEST_PRINTF -int main(void) -{ - char *ptr = "Hello world!"; - char *np = 0; - int i = 5; - unsigned int bs = sizeof(int)*8; - int mi; - char buf[80]; - - mi = (1 << (bs-1)) + 1; - printf("%s\n", ptr); - printf("printf test\n"); - printf("%s is null pointer\n", np); - printf("%d = 5\n", i); - printf("%d = - max int\n", mi); - printf("char %c = 'a'\n", 'a'); - printf("hex %x = ff\n", 0xff); - printf("hex %02x = 00\n", 0); - printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3); - printf("%d %s(s)%", 0, "message"); - printf("\n"); - printf("%d %s(s) with %%\n", 0, "message"); - sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf); - sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf); - sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf); - sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf); - sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf); - sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf); - sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf); - sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf); - - return 0; -} - -/* - * if you compile this file with - * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c - * you will get a normal warning: - * printf.c:214: warning: spurious trailing `%' in format - * this line is testing an invalid % at the end of the format string. - * - * this should display (on 32bit int machine) : - * - * Hello world! - * printf test - * (null) is null pointer - * 5 = 5 - * -2147483647 = - max int - * char a = 'a' - * hex ff = ff - * hex 00 = 00 - * signed -3 = unsigned 4294967293 = hex fffffffd - * 0 message(s) - * 0 message(s) with % - * justif: "left " - * justif: " right" - * 3: 0003 zero padded - * 3: 3 left justif. - * 3: 3 right justif. - * -3: -003 zero padded - * -3: -3 left justif. - * -3: -3 right justif. - */ - -#endif - - -/* To keep linker happy. */ -int write( int i, char* c, int n) -{ - (void)i; - (void)n; - (void)c; - return 0; -} - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/trcConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/trcConfig.h deleted file mode 100644 index f09345f97..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/trcConfig.h +++ /dev/null @@ -1,160 +0,0 @@ -/******************************************************************************* - * Trace Recorder Library for Tracealyzer v3.1.2 - * Percepio AB, www.percepio.com - * - * trcConfig.h - * - * Main configuration parameters for the trace recorder library. - * More settings can be found in trcStreamingConfig.h and trcSnapshotConfig.h. - * - * Read more at http://percepio.com/2016/10/05/rtos-tracing/ - * - * Terms of Use - * This file is part of the trace recorder library (RECORDER), which is the - * intellectual property of Percepio AB (PERCEPIO) and provided under a - * license as follows. - * The RECORDER may be used free of charge for the purpose of recording data - * intended for analysis in PERCEPIO products. It may not be used or modified - * for other purposes without explicit permission from PERCEPIO. - * You may distribute the RECORDER in its original source code form, assuming - * this text (terms of use, disclaimer, copyright notice) is unchanged. You are - * allowed to distribute the RECORDER with minor modifications intended for - * configuration or porting of the RECORDER, e.g., to allow using it on a - * specific processor, processor family or with a specific communication - * interface. Any such modifications should be documented directly below - * this comment block. - * - * Disclaimer - * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty - * as to its use or performance. PERCEPIO does not and cannot warrant the - * performance or results you may obtain by using the RECORDER or documentation. - * PERCEPIO make no warranties, express or implied, as to noninfringement of - * third party rights, merchantability, or fitness for any particular purpose. - * In no event will PERCEPIO, its technology partners, or distributors be liable - * to you for any consequential, incidental or special damages, including any - * lost profits or lost savings, even if a representative of PERCEPIO has been - * advised of the possibility of such damages, or for any claim by any third - * party. Some jurisdictions do not allow the exclusion or limitation of - * incidental, consequential or special damages, or the exclusion of implied - * warranties or limitations on how long an implied warranty may last, so the - * above limitations may not apply to you. - * - * Tabs are used for indent in this file (1 tab = 4 spaces) - * - * Copyright Percepio AB, 2016. - * www.percepio.com - ******************************************************************************/ - -#ifndef TRC_CONFIG_H -#define TRC_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "trcPortDefines.h" - -/****************************************************************************** - * Include of processor header file - * - * Here you may need to include the header file for your processor. This is - * required at least for the ARM Cortex-M port, that uses the ARM CMSIS API. - * Try that in case of build problems. Otherwise, remove the #error line below. - *****************************************************************************/ -//#error "Trace Recorder: Please include your processor's header file here and remove this line." -#include "lpc18xx.h" - -/******************************************************************************* - * Configuration Macro: TRC_CFG_HARDWARE_PORT - * - * Specify what hardware port to use (i.e., the "timestamping driver"). - * - * All ARM Cortex-M MCUs are supported by "TRC_HARDWARE_PORT_ARM_Cortex_M". - * This port uses the DWT cycle counter for Cortex-M3/M4/M7 devices, which is - * available on most such devices. In case your device don't have DWT support, - * you will get an error message opening the trace. In that case, you may - * force the recorder to use SysTick timestamping instead, using this define: - * - * #define TRC_CFG_ARM_CM_USE_SYSTICK - * - * For ARM Cortex-M0/M0+ devices, SysTick mode is used automatically. - * - * See trcHardwarePort.h for available ports and information on how to - * define your own port, if not already present. - ******************************************************************************/ -#define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_ARM_Cortex_M - -/******************************************************************************* - * Configuration Macro: TRC_CFG_RECORDER_MODE - * - * Specify what recording mode to use. Snapshot means that the data is saved in - * an internal RAM buffer, for later upload. Streaming means that the data is - * transferred continuously to the host PC. - * - * For more information, see http://percepio.com/2016/10/05/rtos-tracing/ - * and the Tracealyzer User Manual. - * - * Values: - * TRC_RECORDER_MODE_SNAPSHOT - * TRC_RECORDER_MODE_STREAMING - ******************************************************************************/ -#define TRC_CFG_RECORDER_MODE TRC_RECORDER_MODE_SNAPSHOT - -/******************************************************************************* - * Configuration Macro: TRC_CFG_RECORDER_BUFFER_ALLOCATION - * - * Specifies how the recorder buffer is allocated (also in case of streaming, in - * port using the recorder's internal temporary buffer) - * - * Values: - * TRC_RECORDER_BUFFER_ALLOCATION_STATIC - Static allocation (internal) - * TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC - Malloc in vTraceEnable - * TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM - Use vTraceSetRecorderDataBuffer - * - * Static and dynamic mode does the allocation for you, either in compile time - * (static) or in runtime (malloc). - * The custom mode allows you to control how and where the allocation is made, - * for details see TRC_ALLOC_CUSTOM_BUFFER and vTraceSetRecorderDataBuffer(). - ******************************************************************************/ -#define TRC_CFG_RECORDER_BUFFER_ALLOCATION TRC_RECORDER_BUFFER_ALLOCATION_STATIC - -/****************************************************************************** - * TRC_CFG_FREERTOS_VERSION - * - * Specify what version of FreeRTOS that is used (don't change unless using the - * trace recorder library with an older version of FreeRTOS). - * - * TRC_FREERTOS_VERSION_7_3_OR_7_4 If using FreeRTOS v7.3.0 - v7.4.2 - * TRC_FREERTOS_VERSION_7_5_OR_7_6 If using FreeRTOS v7.5.0 - v7.6.0 - * TRC_FREERTOS_VERSION_8_X If using FreeRTOS v8.X.X - * TRC_FREERTOS_VERSION_9_X If using FreeRTOS v9.X.X - *****************************************************************************/ -#define TRC_CFG_FREERTOS_VERSION TRC_FREERTOS_VERSION_9_X - -/****************************************************************************** - * TRC_CFG_MAX_ISR_NESTING - * - * Defines how many levels of interrupt nesting the recorder can handle, in - * case multiple ISRs are traced and ISR nesting is possible. If this - * is exceeded, the particular ISR will not be traced and the recorder then - * logs an error message. This setting is used to allocate an internal stack - * for keeping track of the previous execution context (4 byte per entry). - * - * This value must be a non-zero positive constant, at least 1. - * - * Default value: 8 - *****************************************************************************/ -#define TRC_CFG_MAX_ISR_NESTING 8 - -/* Specific configuration, depending on Streaming/Snapshot mode */ -#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) -#include "trcSnapshotConfig.h" -#elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) -#include "trcStreamingConfig.h" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _TRC_CONFIG_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/trcSnapshotConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/trcSnapshotConfig.h deleted file mode 100644 index e84a40b0c..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/trcSnapshotConfig.h +++ /dev/null @@ -1,472 +0,0 @@ -/******************************************************************************* - * Trace Recorder Library for Tracealyzer v3.1.2 - * Percepio AB, www.percepio.com - * - * trcSnapshotConfig.h - * - * Configuration parameters for trace recorder library in snapshot mode. - * Read more at http://percepio.com/2016/10/05/rtos-tracing/ - * - * Terms of Use - * This file is part of the trace recorder library (RECORDER), which is the - * intellectual property of Percepio AB (PERCEPIO) and provided under a - * license as follows. - * The RECORDER may be used free of charge for the purpose of recording data - * intended for analysis in PERCEPIO products. It may not be used or modified - * for other purposes without explicit permission from PERCEPIO. - * You may distribute the RECORDER in its original source code form, assuming - * this text (terms of use, disclaimer, copyright notice) is unchanged. You are - * allowed to distribute the RECORDER with minor modifications intended for - * configuration or porting of the RECORDER, e.g., to allow using it on a - * specific processor, processor family or with a specific communication - * interface. Any such modifications should be documented directly below - * this comment block. - * - * Disclaimer - * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty - * as to its use or performance. PERCEPIO does not and cannot warrant the - * performance or results you may obtain by using the RECORDER or documentation. - * PERCEPIO make no warranties, express or implied, as to noninfringement of - * third party rights, merchantability, or fitness for any particular purpose. - * In no event will PERCEPIO, its technology partners, or distributors be liable - * to you for any consequential, incidental or special damages, including any - * lost profits or lost savings, even if a representative of PERCEPIO has been - * advised of the possibility of such damages, or for any claim by any third - * party. Some jurisdictions do not allow the exclusion or limitation of - * incidental, consequential or special damages, or the exclusion of implied - * warranties or limitations on how long an implied warranty may last, so the - * above limitations may not apply to you. - * - * Tabs are used for indent in this file (1 tab = 4 spaces) - * - * Copyright Percepio AB, 2017. - * www.percepio.com - ******************************************************************************/ - -#ifndef TRC_SNAPSHOT_CONFIG_H -#define TRC_SNAPSHOT_CONFIG_H - -#define TRC_SNAPSHOT_MODE_RING_BUFFER (0x01) -#define TRC_SNAPSHOT_MODE_STOP_WHEN_FULL (0x02) - -/****************************************************************************** - * TRC_CFG_SNAPSHOT_MODE - * - * Macro which should be defined as one of: - * - TRC_SNAPSHOT_MODE_RING_BUFFER - * - TRC_SNAPSHOT_MODE_STOP_WHEN_FULL - * Default is TRC_SNAPSHOT_MODE_RING_BUFFER. - * - * With TRC_CFG_SNAPSHOT_MODE set to TRC_SNAPSHOT_MODE_RING_BUFFER, the - * events are stored in a ring buffer, i.e., where the oldest events are - * overwritten when the buffer becomes full. This allows you to get the last - * events leading up to an interesting state, e.g., an error, without having - * to store the whole run since startup. - * - * When TRC_CFG_SNAPSHOT_MODE is TRC_SNAPSHOT_MODE_STOP_WHEN_FULL, the - * recording is stopped when the buffer becomes full. This is useful for - * recording events following a specific state, e.g., the startup sequence. - *****************************************************************************/ -#define TRC_CFG_SNAPSHOT_MODE TRC_SNAPSHOT_MODE_RING_BUFFER - -/******************************************************************************* - * TRC_CFG_SCHEDULING_ONLY - * - * Macro which should be defined as an integer value. - * - * If this setting is enabled (= 1), only scheduling events are recorded. - * If disabled (= 0), all events are recorded. - * - * For users of Tracealyzer Free Edition, that only displays scheduling events, this - * option can be used to avoid storing other events. - * - * Default value is 0 (store all enabled events). - * - ******************************************************************************/ -#define TRC_CFG_SCHEDULING_ONLY 0 - -/******************************************************************************* - * TRC_CFG_EVENT_BUFFER_SIZE - * - * Macro which should be defined as an integer value. - * - * This defines the capacity of the event buffer, i.e., the number of records - * it may store. Most events use one record (4 byte), although some events - * require multiple 4-byte records. You should adjust this to the amount of RAM - * available in the target system. - * - * Default value is 1000, which means that 4000 bytes is allocated for the - * event buffer. - ******************************************************************************/ -#define TRC_CFG_EVENT_BUFFER_SIZE 1000 - -/******************************************************************************* - * TRC_CFG_NTASK, TRC_CFG_NISR, TRC_CFG_NQUEUE, TRC_CFG_NSEMAPHORE... - * - * A group of macros which should be defined as integer values, zero or larger. - * - * These define the capacity of the Object Property Table, i.e., the maximum - * number of objects active at any given point, within each object class (e.g., - * task, queue, semaphore, ...). - * - * If tasks or other objects are deleted in your system, this - * setting does not limit the total amount of objects created, only the number - * of objects that have been successfully created but not yet deleted. - * - * Using too small values will cause vTraceError to be called, which stores an - * error message in the trace that is shown when opening the trace file. The - * error message can also be retrieved using xTraceGetLastError. - * - * It can be wise to start with large values for these constants, - * unless you are very confident on these numbers. Then do a recording and - * check the actual usage by selecting View menu -> Trace Details -> - * Resource Usage -> Object Table. - ******************************************************************************/ -#define TRC_CFG_NTASK 15 -#define TRC_CFG_NISR 4 -#define TRC_CFG_NQUEUE 10 -#define TRC_CFG_NSEMAPHORE 10 -#define TRC_CFG_NMUTEX 5 -#define TRC_CFG_NTIMER 10 -#define TRC_CFG_NEVENTGROUP 1 - -/****************************************************************************** - * TRC_CFG_INCLUDE_MEMMANG_EVENTS - * - * Macro which should be defined as either zero (0) or one (1). - * - * This controls if malloc and free calls should be traced. Set this to zero (0) - * to exclude malloc/free calls, or one (1) to include such events in the trace. - * - * Default value is 1. - *****************************************************************************/ -#define TRC_CFG_INCLUDE_MEMMANG_EVENTS 1 - -/****************************************************************************** - * TRC_CFG_INCLUDE_USER_EVENTS - * - * Macro which should be defined as either zero (0) or one (1). - * - * If this is zero (0) the code for creating User Events is excluded to - * reduce code size. User Events are application-generated events, like - * "printf" but for the trace log and the formatting is done offline, by the - * Tracealyzer visualization tool. User Events are much faster than a printf - * and can therefore be used in timing critical code. - * - * Default value is 1. - *****************************************************************************/ -#define TRC_CFG_INCLUDE_USER_EVENTS 0 - -/***************************************************************************** - * TRC_CFG_INCLUDE_ISR_TRACING - * - * Macro which should be defined as either zero (0) or one (1). - * - * If this is zero (0), the code for recording Interrupt Service Routines is - * excluded, in order to reduce code size. - * - * Default value is 1. - * - * Note: tracing ISRs requires that you insert calls to vTraceStoreISRBegin - * and vTraceStoreISREnd in your interrupt handlers. - *****************************************************************************/ -#define TRC_CFG_INCLUDE_ISR_TRACING 1 - -/***************************************************************************** - * TRC_CFG_INCLUDE_READY_EVENTS - * - * Macro which should be defined as either zero (0) or one (1). - * - * If one (1), events are recorded when tasks enter scheduling state "ready". - * This allows Tracealyzer to show the initial pending time before tasks enter - * the execution state, and present accurate response times. - * If zero (0), "ready events" are not created, which allows for recording - * longer traces in the same amount of RAM. - * - * Default value is 1. - *****************************************************************************/ -#define TRC_CFG_INCLUDE_READY_EVENTS 1 - -/***************************************************************************** - * TRC_CFG_INCLUDE_OSTICK_EVENTS - * - * Macro which should be defined as either zero (0) or one (1). - * - * If this is one (1), events will be generated whenever the OS clock is - * increased. If zero (0), OS tick events are not generated, which allows for - * recording longer traces in the same amount of RAM. - * - * Default value is 0. - *****************************************************************************/ -#define TRC_CFG_INCLUDE_OSTICK_EVENTS 1 - -/****************************************************************************** - * TRC_CFG_INCLUDE_FLOAT_SUPPORT - * - * Macro which should be defined as either zero (0) or one (1). - * - * If this is zero (0), the support for logging floating point values in - * vTracePrintF is stripped out, in case floating point values are not used or - * supported by the platform used. - * - * Floating point values are only used in vTracePrintF and its subroutines, to - * allow for storing float (%f) or double (%lf) arguments. - * - * vTracePrintF can be used with integer and string arguments in either case. - * - * Default value is 0. - *****************************************************************************/ -#define TRC_CFG_INCLUDE_FLOAT_SUPPORT 0 - -/****************************************************************************** - * TRC_CFG_INCLUDE_OBJECT_DELETE - * - * Macro which should be defined as either zero (0) or one (1). - * - * This must be enabled (1) if tasks, queues or other - * traced kernel objects are deleted at runtime. If no deletes are made, this - * can be set to 0 in order to exclude the delete-handling code. - * - * Default value is 1. - *****************************************************************************/ -#define TRC_CFG_INCLUDE_OBJECT_DELETE 1 - -/******************************************************************************* - * TRC_CFG_SYMBOL_TABLE_SIZE - * - * Macro which should be defined as an integer value. - * - * This defines the capacity of the symbol table, in bytes. This symbol table - * stores User Events labels and names of deleted tasks, queues, or other kernel - * objects. If you don't use User Events or delete any kernel - * objects you set this to a very low value. The minimum recommended value is 4. - * A size of zero (0) is not allowed since a zero-sized array may result in a - * 32-bit pointer, i.e., using 4 bytes rather than 0. - * - * Default value is 800. - ******************************************************************************/ -#define TRC_CFG_SYMBOL_TABLE_SIZE 5000 - -#if (TRC_CFG_SYMBOL_TABLE_SIZE == 0) -#error "TRC_CFG_SYMBOL_TABLE_SIZE may not be zero!" -#endif - -/****************************************************************************** - * TRC_CFG_NAME_LEN_TASK, TRC_CFG_NAME_LEN_QUEUE, ... - * - * Macros that specify the maximum lengths (number of characters) for names of - * kernel objects, such as tasks and queues. If longer names are used, they will - * be truncated when stored in the recorder. - *****************************************************************************/ -#define TRC_CFG_NAME_LEN_TASK 15 -#define TRC_CFG_NAME_LEN_ISR 15 -#define TRC_CFG_NAME_LEN_QUEUE 15 -#define TRC_CFG_NAME_LEN_SEMAPHORE 15 -#define TRC_CFG_NAME_LEN_MUTEX 15 -#define TRC_CFG_NAME_LEN_TIMER 15 -#define TRC_CFG_NAME_LEN_EVENTGROUP 15 - -/****************************************************************************** - *** ADVANCED SETTINGS ******************************************************** - ****************************************************************************** - * The remaining settings are not necessary to modify but allows for optimizing - * the recorder setup for your specific needs, e.g., to exclude events that you - * are not interested in, in order to get longer traces. - *****************************************************************************/ - -/****************************************************************************** -* TRC_CFG_HEAP_SIZE_BELOW_16M -* -* An integer constant that can be used to reduce the buffer usage of memory -* allocation events (malloc/free). This value should be 1 if the heap size is -* below 16 MB (2^24 byte), and you can live with reported addresses showing the -* lower 24 bits only. If 0, you get the full 32-bit addresses. -* -* Default value is 0. -******************************************************************************/ -#define TRC_CFG_HEAP_SIZE_BELOW_16M 0 - -/****************************************************************************** - * TRC_CFG_USE_IMPLICIT_IFE_RULES - * - * Macro which should be defined as either zero (0) or one (1). - * Default is 1. - * - * Tracealyzer groups the events into "instances" based on Instance Finish - * Events (IFEs), produced either by default rules or calls to the recorder - * functions vTraceInstanceFinishedNow and vTraceInstanceFinishedNext. - * - * If TRC_CFG_USE_IMPLICIT_IFE_RULES is one (1), the default IFE rules is - * used, resulting in a "typical" grouping of events into instances. - * If these rules don't give appropriate instances in your case, you can - * override the default rules using vTraceInstanceFinishedNow/Next for one - * or several tasks. The default IFE rules are then disabled for those tasks. - * - * If TRC_CFG_USE_IMPLICIT_IFE_RULES is zero (0), the implicit IFE rules are - * disabled globally. You must then call vTraceInstanceFinishedNow or - * vTraceInstanceFinishedNext to manually group the events into instances, - * otherwise the tasks will appear a single long instance. - * - * The default IFE rules count the following events as "instance finished": - * - Task delay, delay until - * - Task suspend - * - Blocking on "input" operations, i.e., when the task is waiting for the - * next a message/signal/event. But only if this event is blocking. - * - * For details, see trcSnapshotKernelPort.h and look for references to the - * macro trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED. - *****************************************************************************/ -#define TRC_CFG_USE_IMPLICIT_IFE_RULES 1 - -/****************************************************************************** - * TRC_CFG_USE_16BIT_OBJECT_HANDLES - * - * Macro which should be defined as either zero (0) or one (1). - * - * If set to 0 (zero), the recorder uses 8-bit handles to identify kernel - * objects such as tasks and queues. This limits the supported number of - * concurrently active objects to 255 of each type (tasks, queues, mutexes, - * etc.) Note: 255, not 256, since handle 0 is reserved. - * - * If set to 1 (one), the recorder uses 16-bit handles to identify kernel - * objects such as tasks and queues. This limits the supported number of - * concurrent objects to 65535 of each type (object class). However, since the - * object property table is limited to 64 KB, the practical limit is about - * 3000 objects in total. - * - * Default is 0 (8-bit handles) - * - * NOTE: An object with handle above 255 will use an extra 4-byte record in - * the event buffer whenever the object is referenced. Moreover, some internal - * tables in the recorder gets slightly larger when using 16-bit handles. - *****************************************************************************/ -#define TRC_CFG_USE_16BIT_OBJECT_HANDLES 0 - -/****************************************************************************** - * TRC_CFG_USE_TRACE_ASSERT - * - * Macro which should be defined as either zero (0) or one (1). - * Default is 1. - * - * If this is one (1), the TRACE_ASSERT macro (used at various locations in the - * trace recorder) will verify that a relevant condition is true. - * If the condition is false, prvTraceError() will be called, which stops the - * recording and stores an error message that is displayed when opening the - * trace in Tracealyzer. - * - * This is used on several places in the recorder code for sanity checks on - * parameters. Can be switched off to reduce the footprint of the tracing, but - * we recommend to have it enabled initially. - *****************************************************************************/ -#define TRC_CFG_USE_TRACE_ASSERT 1 - -/******************************************************************************* - * TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER - * - * Macro which should be defined as an integer value. - * - * Set TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER to 1 to enable the - * separate user event buffer (UB). - * In this mode, user events are stored separately from other events, - * e.g., RTOS events. Thereby you can get a much longer history of - * user events as they don't need to share the buffer space with more - * frequent events. - * - * The UB is typically used with the snapshot ring-buffer mode, so the - * recording can continue when the main buffer gets full. And since the - * main buffer then overwrites the earliest events, Tracealyzer displays - * "Unknown Actor" instead of task scheduling for periods with UB data only. - * - * In UB mode, user events are structured as UB channels, which contains - * a channel name and a default format string. Register a UB channel using - * xTraceRegisterUBChannel. - * - * Events and data arguments are written using vTraceUBEvent and - * vTraceUBData. They are designed to provide efficient logging of - * repeating events, using the same format string within each channel. - * - * Examples: - * - * traceString chn1 = xTraceRegisterString("Channel 1"); - * traceString fmt1 = xTraceRegisterString("Event!"); - * traceUBChannel UBCh1 = xTraceRegisterUBChannel(chn1, fmt1); - * - * traceString chn2 = xTraceRegisterString("Channel 2"); - * traceString fmt2 = xTraceRegisterString("X: %d, Y: %d"); - * traceUBChannel UBCh2 = xTraceRegisterUBChannel(chn2, fmt2); - * - * // Result in "[Channel 1] Event!" - * vTraceUBEvent(UBCh1); - * - * // Result in "[Channel 2] X: 23, Y: 19" - * vTraceUBData(UBCh2, 23, 19); - * - * You can also use the other user event functions, like vTracePrintF. - * as they are then rerouted to the UB instead of the main event buffer. - * vTracePrintF then looks up the correct UB channel based on the - * provided channel name and format string, or creates a new UB channel - * if no match is found. The format string should therefore not contain - * "random" messages but mainly format specifiers. Random strings should - * be stored using %s and with the string as an argument. - * - * // Creates a new UB channel ("Channel 2", "%Z: %d") - * vTracePrintF(chn2, "%Z: %d", value1); - * - * // Finds the existing UB channel - * vTracePrintF(chn2, "%Z: %d", value2); - - ******************************************************************************/ -#define TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER 0 - -/******************************************************************************* - * TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE - * - * Macro which should be defined as an integer value. - * - * This defines the capacity of the user event buffer (UB), in number of slots. - * A single user event can use multiple slots, depending on the arguments. - * - * Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1. - ******************************************************************************/ -#define TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE 10 - -/******************************************************************************* - * TRC_CFG_UB_CHANNELS - * - * Macro which should be defined as an integer value. - * - * This defines the number of User Event Buffer Channels (UB channels). - * These are used to structure the events when using the separate user - * event buffer, and contains both a User Event Channel (the name) and - * a default format string for the channel. - * - * Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1. - ******************************************************************************/ -#define TRC_CFG_UB_CHANNELS 32 - -/******************************************************************************* - * TRC_CFG_ISR_TAILCHAINING_THRESHOLD - * - * Macro which should be defined as an integer value. - * - * If tracing multiple ISRs, this setting allows for accurate display of the - * context-switching also in cases when the ISRs execute in direct sequence. - * - * vTraceStoreISREnd normally assumes that the ISR returns to the previous - * context, i.e., a task or a preempted ISR. But if another traced ISR - * executes in direct sequence, Tracealyzer may incorrectly display a minimal - * fragment of the previous context in between the ISRs. - * - * By using TRC_CFG_ISR_TAILCHAINING_THRESHOLD you can avoid this. This is - * however a threshold value that must be measured for your specific setup. - * See http://percepio.com/2014/03/21/isr_tailchaining_threshold/ - * - * The default setting is 0, meaning "disabled" and that you may get an - * extra fragments of the previous context in between tail-chained ISRs. - * - * Note: This setting has separate definitions in trcSnapshotConfig.h and - * trcStreamingConfig.h, since it is affected by the recorder mode. - ******************************************************************************/ -#define TRC_CFG_ISR_TAILCHAINING_THRESHOLD 0 - -#endif /*TRC_SNAPSHOT_CONFIG_H*/ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/SelectServer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/SelectServer.c deleted file mode 100644 index 0a3ec1ead..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/SelectServer.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * A number of sockets are created and added to a set. One task then blocks on - * the set while the other task sends data to a (pseudo) random member of the - * set. - */ - -/* Standard includes. */ -#include -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_Sockets.h" - -#define selTINY_DELAY ( ( TickType_t ) 2 ) -#define selNUMBER_OF_SOCKETS ( 3 ) -#define selSELECT_QUEUE_SIZE ( selNUMBER_OF_SOCKETS * 2 ) - -/* - * Sends data to multiple different sockets. - */ -static void prvMultipleSocketTxTask( void *pvParameters ); - -/* - * Uses the FreeRTOS_select() API function to receive from multiple sockets. - */ -static void prvMultipleSocketRxTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -static xSocket_t xRxSockets[ selNUMBER_OF_SOCKETS ] = { 0 }; - -/*-----------------------------------------------------------*/ - -void vStartSelectUDPServerTasks( uint16_t usStackSize, uint32_t ulFirstPortNumber, UBaseType_t uxPriority ) -{ - /* Create task that sends to multiple sockets, and the task that uses the - FreeRTOS_select() function to receive from multiple sockets. The first - port number to use is passed into both tasks using the task's parameter. - Other port numbers are consecutive from the first. */ - xTaskCreate( prvMultipleSocketTxTask, "MultiTx", usStackSize, ( void * ) ulFirstPortNumber, uxPriority, NULL ); - xTaskCreate( prvMultipleSocketRxTask, "MultiRx", usStackSize, ( void * ) ulFirstPortNumber, uxPriority, NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvMultipleSocketRxTask( void *pvParameters ) -{ -xSocketSet_t xFD_Set; -xSocket_t xSocket; -struct freertos_sockaddr xAddress; -uint32_t xClientLength = sizeof( struct freertos_sockaddr ), ulFirstRxPortNumber, x; -uint32_t ulReceivedValue = 0, ulExpectedValue = 0UL, ulReceivedCount[ selNUMBER_OF_SOCKETS ] = { 0 }; -int32_t lBytes; -const TickType_t xRxBlockTime = 0; - - /* The number of the port the first Rx socket will be bound to is passed in - as the task parameter. Other port numbers used are consecutive from this. */ - ulFirstRxPortNumber = ( uint32_t ) pvParameters; - - /* Create the set of sockets that will be passed into FreeRTOS_select(). */ - xFD_Set = FreeRTOS_CreateSocketSet( selSELECT_QUEUE_SIZE ); - - for( x = 0; x < selNUMBER_OF_SOCKETS; x++ ) - { - /* Create the next Rx socket. */ - xRxSockets[ x ] = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - configASSERT( xRxSockets[ x ] ); - - /* Bind to the next port number. */ - xAddress.sin_port = FreeRTOS_htons( ( uint16_t ) ( ulFirstRxPortNumber + x ) ); - FreeRTOS_bind( xRxSockets[ x ], &xAddress, sizeof( struct freertos_sockaddr ) ); - - /* There should always be data available on the socket returned from - FreeRTOS_select() so blocking on a read should not be necessary. */ - FreeRTOS_setsockopt( xRxSockets[ x ], 0, FREERTOS_SO_RCVTIMEO, &xRxBlockTime, sizeof( xRxBlockTime ) ); - - /* Add the created socket to the set. */ - FreeRTOS_FD_SET( xRxSockets[ x ], xFD_Set ); - } - - for( ;; ) - { - /* Wait for a socket from the set to become available for reading. */ - xSocket = FreeRTOS_select( xFD_Set, portMAX_DELAY ); - - /* xSocket should never be NULL because FreeRTOS_select() was called - with an indefinite delay (assuming INCLUDE_vTaskSuspend is set to 1). */ - configASSERT( xSocket ); - - lBytes = FreeRTOS_recvfrom( xSocket, &( ulReceivedValue ), sizeof( uint32_t ), 0, &xAddress, &xClientLength ); - - /* It is possible that the first value received will not be zero - because the first few transmitted packets may have been dropped to - send an ARP and then wait the ARP reply. */ - if( ulExpectedValue == 0 ) - { - if( ulExpectedValue != ulReceivedValue ) - { - /* Correct for packets lost to ARP traffic. */ - ulExpectedValue = ulReceivedValue; - } - } - - /* Data should always be available even though the block time was set - to zero because the socket was returned from FreeRTOS_select(). */ - configASSERT( lBytes == 4 ); - configASSERT( ulReceivedValue == ulExpectedValue ); - - ulExpectedValue++; - - /* Keep a record of the number of times each socket has been used so it - can be verified (using the debugger) that they all get used. */ - for( x= 0; x < selNUMBER_OF_SOCKETS; x++ ) - { - if( xSocket == xRxSockets[ x ] ) - { - ( ulReceivedCount[ x ] )++; - break; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvMultipleSocketTxTask( void *pvParameters ) -{ -uint32_t ulTxValue = 0; -struct freertos_sockaddr xDestinationAddress; -uint32_t ulIPAddress, ulFirstDestinationPortNumber, xPortNumber; -xSocket_t xTxSocket; -const TickType_t xShortDelay = 100 / portTICK_RATE_MS, xSendBlockTime = 500 / portTICK_RATE_MS; - - srand( ( unsigned int ) &xPortNumber ); - - /* The first destination port number is passed in as the task parameter. - Other destination port numbers used are consecutive from this. */ - ulFirstDestinationPortNumber = ( uint32_t ) pvParameters; - - /* Create the socket used to send to the sockets created by the Rx task. - Let the IP stack select a port to bind to. */ - xTxSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - FreeRTOS_bind( xTxSocket, NULL, sizeof( struct freertos_sockaddr ) ); - - /* The Rx and Tx tasks execute at the same priority so it is possible that - the Tx task will fill up the send queue - set a Tx block time to ensure - flow control is managed if this happens. */ - FreeRTOS_setsockopt( xTxSocket, 0, FREERTOS_SO_SNDTIMEO, &xSendBlockTime, sizeof( xSendBlockTime ) ); - - /* It is assumed that this task is not created until the network is up, - so the IP address can be obtained immediately. Store the IP address being - used in ulIPAddress. This is done so the socket can send to a different - port on the same IP address. */ - FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL ); - - /* This test sends to itself, so data sent from here is received by a server - socket on the same IP address. Setup the freertos_sockaddr structure with - this nodes IP address. */ - xDestinationAddress.sin_addr = ulIPAddress; - - /* Block for a short time to ensure the task implemented by the - prvMultipleSocketRxTask() function has finished creating the Rx sockets. */ - vTaskDelay( xShortDelay ); - - for( ;; ) - { - /* Pseudo randomly select the destination port number from the range of - valid destination port numbers. */ - xPortNumber = rand() % selNUMBER_OF_SOCKETS; - xDestinationAddress.sin_port = ( uint16_t ) ( ulFirstDestinationPortNumber + xPortNumber ); - xDestinationAddress.sin_port = FreeRTOS_htons( xDestinationAddress.sin_port ); - - /* Send an incrementing value. */ - FreeRTOS_sendto( xTxSocket, &ulTxValue, sizeof( ulTxValue ), 0, &xDestinationAddress, sizeof( xDestinationAddress ) ); - ulTxValue++; - - /* Delay here because in the Windows simulator the MAC interrupt - simulator delays, so network trafic cannot be received any faster - than this. */ - vTaskDelay( configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ); - } -} - - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/SimpleClientAndServer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/SimpleClientAndServer.c deleted file mode 100644 index 4222240d1..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/SimpleClientAndServer.c +++ /dev/null @@ -1,359 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * Creates two transmitting tasks and two receiving tasks. The transmitting - * tasks send values that are received by the receiving tasks. One set of tasks - * uses the standard API. The other set of tasks uses the zero copy API. - */ - -/* Standard includes. */ -#include -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_Sockets.h" - -#define simpTINY_DELAY ( ( TickType_t ) 2 ) - -/* - * Uses a socket to send data without using the zero copy option. - * prvSimpleServerTask() will receive the data. - */ -static void prvSimpleClientTask( void *pvParameters ); - -/* - * Uses a socket to receive the data sent by the prvSimpleClientTask() task. - * Does not use the zero copy option. - */ -static void prvSimpleServerTask( void *pvParameters ); - -/* - * Uses a socket to send data using the zero copy option. - * prvSimpleZeroCopyServerTask() will receive the data. - */ -static void prvSimpleZeroCopyUDPClientTask( void *pvParameters ); - -/* - * Uses a socket to receive the data sent by the prvSimpleZeroCopyUDPClientTask() - * task. Uses the zero copy option. - */ -static void prvSimpleZeroCopyServerTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -void vStartSimpleUDPClientServerTasks( uint16_t usStackSize, uint32_t ulPort, UBaseType_t uxPriority ) -{ - /* Create the client and server tasks that do not use the zero copy - interface. */ - xTaskCreate( prvSimpleClientTask, "SimpCpyClnt", usStackSize, ( void * ) ulPort, uxPriority, NULL ); - xTaskCreate( prvSimpleServerTask, "SimpCpySrv", usStackSize, ( void * ) ulPort, uxPriority + 1, NULL ); - - /* Create the client and server tasks that do use the zero copy interface. */ - xTaskCreate( prvSimpleZeroCopyUDPClientTask, "SimpZCpyClnt", usStackSize, ( void * ) ( ulPort + 1 ), uxPriority, NULL ); - xTaskCreate( prvSimpleZeroCopyServerTask, "SimpZCpySrv", usStackSize, ( void * ) ( ulPort + 1 ), uxPriority + 1, NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvSimpleClientTask( void *pvParameters ) -{ -xSocket_t xClientSocket; -struct freertos_sockaddr xDestinationAddress; -char cString[ 50 ]; -BaseType_t lReturned; -uint32_t ulCount = 0UL, ulIPAddress; -const uint32_t ulLoopsPerSocket = 10UL; -const TickType_t x150ms = 150UL / portTICK_RATE_MS; - - /* Remove compiler warning about unused parameters. */ - ( void ) pvParameters; - - /* It is assumed that this task is not created until the network is up, - so the IP address can be obtained immediately. store the IP address being - used in ulIPAddress. This is done so the socket can send to a different - port on the same IP address. */ - FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL ); - - /* This test sends to itself, so data sent from here is received by a server - socket on the same IP address. Setup the freertos_sockaddr structure with - this nodes IP address, and the port number being sent to. The strange - casting is to try and remove compiler warnings on 32 bit machines. */ - xDestinationAddress.sin_addr = ulIPAddress; - xDestinationAddress.sin_port = ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL; - xDestinationAddress.sin_port = FreeRTOS_htons( xDestinationAddress.sin_port ); - - for( ;; ) - { - /* Create the socket. */ - xClientSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - configASSERT( xClientSocket != FREERTOS_INVALID_SOCKET ); - - /* The count is used to differentiate between different messages sent to - the server, and to break out of the do while loop below. */ - ulCount = 0UL; - - do - { - /* Create the string that is sent to the server. */ - sprintf( cString, "Server received (not zero copy): Message number %lu\r\n", ulCount ); - - /* Send the string to the socket. ulFlags is set to 0, so the zero - copy option is not selected. That means the data from cString[] is - copied into a network buffer inside FreeRTOS_sendto(), and cString[] - can be reused as soon as FreeRTOS_sendto() has returned. */ - lReturned = FreeRTOS_sendto( xClientSocket, ( void * ) cString, strlen( cString ), 0, &xDestinationAddress, sizeof( xDestinationAddress ) ); - - ulCount++; - - } while( ( lReturned != FREERTOS_SOCKET_ERROR ) && ( ulCount < ulLoopsPerSocket ) ); - - FreeRTOS_closesocket( xClientSocket ); - - /* A short delay to prevent the messages printed by the server task - scrolling off the screen too quickly, and to prevent reduce the network - loading. */ - vTaskDelay( x150ms ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSimpleServerTask( void *pvParameters ) -{ -long lBytes; -char cReceivedString[ 60 ]; -struct freertos_sockaddr xClient, xBindAddress; -uint32_t xClientLength = sizeof( xClient ); -xSocket_t xListeningSocket; - - /* Just to prevent compiler warnings. */ - ( void ) pvParameters; - - /* Attempt to open the socket. */ - xListeningSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - configASSERT( xListeningSocket != FREERTOS_INVALID_SOCKET ); - - /* This test receives data sent from a different port on the same IP - address. Configure the freertos_sockaddr structure with the address being - bound to. The strange casting is to try and remove compiler warnings on 32 - bit machines. Note that this task is only created after the network is up, - so the IP address is valid here. */ - xBindAddress.sin_port = ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL; - xBindAddress.sin_port = FreeRTOS_htons( xBindAddress.sin_port ); - - /* Bind the socket to the port that the client task will send to. */ - FreeRTOS_bind( xListeningSocket, &xBindAddress, sizeof( xBindAddress ) ); - - for( ;; ) - { - /* Zero out the receive array so there is NULL at the end of the string - when it is printed out. */ - memset( cReceivedString, 0x00, sizeof( cReceivedString ) ); - - /* Receive data on the socket. ulFlags is zero, so the zero copy option - is not set and the received data is copied into the buffer pointed to by - cReceivedString. By default the block time is portMAX_DELAY. - xClientLength is not actually used by FreeRTOS_recvfrom(), but is set - appropriately in case future versions do use it. */ - lBytes = FreeRTOS_recvfrom( xListeningSocket, cReceivedString, sizeof( cReceivedString ), 0, &xClient, &xClientLength ); - - /* Print the received characters. */ - if( lBytes > 0 ) - { - vOutputString( cReceivedString ); - } - - /* Error check. */ - configASSERT( lBytes == ( BaseType_t ) strlen( cReceivedString ) ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSimpleZeroCopyUDPClientTask( void *pvParameters ) -{ -xSocket_t xClientSocket; -uint8_t *pucUDPPayloadBuffer; -struct freertos_sockaddr xDestinationAddress; -BaseType_t lReturned; -uint32_t ulCount = 0UL, ulIPAddress; -const uint32_t ulLoopsPerSocket = 10UL; -const char *pcStringToSend = "Server received (using zero copy): Message number "; -const TickType_t x150ms = 150UL / portTICK_RATE_MS; -/* 15 is added to ensure the number, \r\n and terminating zero fit. */ -const size_t xStringLength = strlen( pcStringToSend ) + 15; - - /* Remove compiler warning about unused parameters. */ - ( void ) pvParameters; - - /* It is assumed that this task is not created until the network is up, - so the IP address can be obtained immediately. store the IP address being - used in ulIPAddress. This is done so the socket can send to a different - port on the same IP address. */ - FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL ); - - /* This test sends to itself, so data sent from here is received by a server - socket on the same IP address. Setup the freertos_sockaddr structure with - this nodes IP address, and the port number being sent to. The strange - casting is to try and remove compiler warnings on 32 bit machines. */ - xDestinationAddress.sin_addr = ulIPAddress; - xDestinationAddress.sin_port = ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL; - xDestinationAddress.sin_port = FreeRTOS_htons( xDestinationAddress.sin_port ); - - for( ;; ) - { - /* Create the socket. */ - xClientSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - configASSERT( xClientSocket != FREERTOS_INVALID_SOCKET ); - - /* The count is used to differentiate between different messages sent to - the server, and to break out of the do while loop below. */ - ulCount = 0UL; - - do - { - /* This task is going to send using the zero copy interface. The - data being sent is therefore written directly into a buffer that is - passed into, rather than copied into, the FreeRTOS_sendto() - function. - - First obtain a buffer of adequate length from the IP stack into which - the string will be written. Although a max delay is used, the actual - delay will be capped to ipconfigMAX_SEND_BLOCK_TIME_TICKS, hence - the do while loop is used to ensure a buffer is obtained. */ - do - { - } while( ( pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xStringLength, portMAX_DELAY ) ) == NULL ); - - /* A buffer was successfully obtained. Create the string that is - sent to the server. First the string is filled with zeros as this will - effectively be the null terminator when the string is received at the other - end. Note that the string is being written directly into the buffer - obtained from the IP stack above. */ - memset( ( void * ) pucUDPPayloadBuffer, 0x00, xStringLength ); - sprintf( ( char * ) pucUDPPayloadBuffer, "%s%lu\r\n", pcStringToSend, ulCount ); - - /* Pass the buffer into the send function. ulFlags has the - FREERTOS_ZERO_COPY bit set so the IP stack will take control of the - buffer rather than copy data out of the buffer. */ - lReturned = FreeRTOS_sendto( xClientSocket, /* The socket being sent to. */ - ( void * ) pucUDPPayloadBuffer, /* A pointer to the the data being sent. */ - strlen( ( const char * ) pucUDPPayloadBuffer ) + 1, /* The length of the data being sent - including the string's null terminator. */ - FREERTOS_ZERO_COPY, /* ulFlags with the FREERTOS_ZERO_COPY bit set. */ - &xDestinationAddress, /* Where the data is being sent. */ - sizeof( xDestinationAddress ) ); - - if( lReturned == 0 ) - { - /* The send operation failed, so this task is still responsible - for the buffer obtained from the IP stack. To ensure the buffer - is not lost it must either be used again, or, as in this case, - returned to the IP stack using FreeRTOS_ReleaseUDPPayloadBuffer(). - pucUDPPayloadBuffer can be safely re-used after this call. */ - FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer ); - } - else - { - /* The send was successful so the IP stack is now managing the - buffer pointed to by pucUDPPayloadBuffer, and the IP stack will - return the buffer once it has been sent. pucUDPPayloadBuffer can - be safely re-used. */ - } - - ulCount++; - - } while( ( lReturned != FREERTOS_SOCKET_ERROR ) && ( ulCount < ulLoopsPerSocket ) ); - - FreeRTOS_closesocket( xClientSocket ); - - /* A short delay to prevent the messages scrolling off the screen too - quickly. */ - vTaskDelay( x150ms ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSimpleZeroCopyServerTask( void *pvParameters ) -{ -int32_t lBytes; -uint8_t *pucUDPPayloadBuffer; -struct freertos_sockaddr xClient, xBindAddress; -uint32_t xClientLength = sizeof( xClient ), ulIPAddress; -xSocket_t xListeningSocket; - - /* Just to prevent compiler warnings. */ - ( void ) pvParameters; - - /* Attempt to open the socket. */ - xListeningSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - configASSERT( xListeningSocket != FREERTOS_INVALID_SOCKET ); - - /* This test receives data sent from a different port on the same IP address. - Obtain the nodes IP address. Configure the freertos_sockaddr structure with - the address being bound to. The strange casting is to try and remove - compiler warnings on 32 bit machines. Note that this task is only created - after the network is up, so the IP address is valid here. */ - FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL ); - xBindAddress.sin_addr = ulIPAddress; - xBindAddress.sin_port = ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL; - xBindAddress.sin_port = FreeRTOS_htons( xBindAddress.sin_port ); - - /* Bind the socket to the port that the client task will send to. */ - FreeRTOS_bind( xListeningSocket, &xBindAddress, sizeof( xBindAddress ) ); - - for( ;; ) - { - /* Receive data on the socket. ulFlags has the zero copy bit set - (FREERTOS_ZERO_COPY) indicating to the stack that a reference to the - received data should be passed out to this task using the second - parameter to the FreeRTOS_recvfrom() call. When this is done the - IP stack is no longer responsible for releasing the buffer, and - the task *must* return the buffer to the stack when it is no longer - needed. By default the block time is portMAX_DELAY. */ - lBytes = FreeRTOS_recvfrom( xListeningSocket, ( void * ) &pucUDPPayloadBuffer, 0, FREERTOS_ZERO_COPY, &xClient, &xClientLength ); - - /* It is expected to receive one more byte than the string length as - the NULL terminator is also transmitted. */ - configASSERT( lBytes == ( ( BaseType_t ) strlen( ( const char * ) pucUDPPayloadBuffer ) + 1 ) ); - - /* Print the received characters. */ - if( lBytes > 0 ) - { - vOutputString( ( char * ) pucUDPPayloadBuffer ); - } - - if( lBytes >= 0 ) - { - /* The buffer *must* be freed once it is no longer needed. */ - FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer ); - } - } -} - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/UDPCommandServer.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/UDPCommandServer.c deleted file mode 100644 index 53ab0aa2f..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/UDPCommandServer.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* FreeRTOS+CLI includes. */ -#include "FreeRTOS_CLI.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_Sockets.h" - -/* Demo app includes. */ -#include "UDPCommandInterpreter.h" - -/* Dimensions the buffer into which input characters are placed. */ -#define cmdMAX_INPUT_SIZE 60 - -/* Dimensions the buffer into which string outputs can be placed. */ -#define cmdMAX_OUTPUT_SIZE 1024 - -/* Dimensions the buffer passed to the recvfrom() call. */ -#define cmdSOCKET_INPUT_BUFFER_SIZE 60 - -/* - * The task that runs FreeRTOS+CLI. - */ -void vUDPCommandInterpreterTask( void *pvParameters ); - -/* - * Open and configure the UDP socket. - */ -static xSocket_t prvOpenUDPServerSocket( uint16_t usPort ); - -/*-----------------------------------------------------------*/ - -void vStartUDPCommandInterpreterTask( uint16_t usStackSize, uint32_t ulPort, UBaseType_t uxPriority ) -{ - xTaskCreate( vUDPCommandInterpreterTask, "CLI", usStackSize, ( void * ) ulPort, uxPriority, NULL ); -} -/*-----------------------------------------------------------*/ - -/* - * Task that provides the input and output for the FreeRTOS+CLI command - * interpreter. In this case a UDP port is used. See the URL in the comments - * within main.c for the location of the online documentation. - */ -void vUDPCommandInterpreterTask( void *pvParameters ) -{ -long lBytes, lByte; -signed char cInChar, cInputIndex = 0; -static signed char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ], cLocalBuffer[ cmdSOCKET_INPUT_BUFFER_SIZE ]; -BaseType_t xMoreDataToFollow; -struct freertos_sockaddr xClient; -socklen_t xClientAddressLength = 0; /* This is required as a parameter to maintain the sendto() Berkeley sockets API - but it is not actually used so can take any value. */ -xSocket_t xSocket; -extern const uint8_t ucIPAddress[ 4 ]; -extern const uint8_t ucMACAddress[ 6 ]; - - /* Just to prevent compiler warnings. */ - ( void ) pvParameters; - - /* Attempt to open the socket. The port number is passed in the task - parameter. The strange casting is to remove compiler warnings on 32-bit - machines. */ - xSocket = prvOpenUDPServerSocket( ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL ); - - if( xSocket != FREERTOS_INVALID_SOCKET ) - { - for( ;; ) - { - /* Wait for incoming data on the opened socket. */ - lBytes = FreeRTOS_recvfrom( xSocket, ( void * ) cLocalBuffer, sizeof( cLocalBuffer ), 0, &xClient, &xClientAddressLength ); - - if( lBytes != FREERTOS_SOCKET_ERROR ) - { - /* Process each received byte in turn. */ - lByte = 0; - while( lByte < lBytes ) - { - /* The next character in the input buffer. */ - cInChar = cLocalBuffer[ lByte ]; - lByte++; - - /* Newline characters are taken as the end of the command - string. */ - if( cInChar == '\n' ) - { - /* Process the input string received prior to the - newline. */ - do - { - /* Pass the string to FreeRTOS+CLI. */ - xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE ); - - /* Send the output generated by the command's - implementation. */ - FreeRTOS_sendto( xSocket, cOutputString, strlen( cOutputString ), 0, &xClient, xClientAddressLength ); - - } while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */ - - /* All the strings generated by the command processing - have been sent. Clear the input string ready to receive - the next command. */ - cInputIndex = 0; - memset( cInputString, 0x00, cmdMAX_INPUT_SIZE ); - - /* Transmit a spacer, just to make the command console - easier to read. */ - FreeRTOS_sendto( xSocket, "\r\n", strlen( "\r\n" ), 0, &xClient, xClientAddressLength ); - } - else - { - if( cInChar == '\r' ) - { - /* Ignore the character. Newlines are used to - detect the end of the input string. */ - } - else if( cInChar == '\b' ) - { - /* Backspace was pressed. Erase the last character - in the string - if any. */ - if( cInputIndex > 0 ) - { - cInputIndex--; - cInputString[ cInputIndex ] = '\0'; - } - } - else - { - /* A character was entered. Add it to the string - entered so far. When a \n is entered the complete - string will be passed to the command interpreter. */ - if( cInputIndex < cmdMAX_INPUT_SIZE ) - { - cInputString[ cInputIndex ] = cInChar; - cInputIndex++; - } - } - } - } - } - } - } - else - { - /* The socket could not be opened. */ - vTaskDelete( NULL ); - } -} -/*-----------------------------------------------------------*/ - -static xSocket_t prvOpenUDPServerSocket( uint16_t usPort ) -{ -struct freertos_sockaddr xServer; -xSocket_t xSocket = FREERTOS_INVALID_SOCKET; - - xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - if( xSocket != FREERTOS_INVALID_SOCKET) - { - /* Zero out the server structure. */ - memset( ( void * ) &xServer, 0x00, sizeof( xServer ) ); - - /* Set family and port. */ - xServer.sin_port = FreeRTOS_htons( usPort ); - - /* Bind the address to the socket. */ - if( FreeRTOS_bind( xSocket, &xServer, sizeof( xServer ) ) == -1 ) - { - FreeRTOS_closesocket( xSocket ); - xSocket = FREERTOS_INVALID_SOCKET; - } - } - - return xSocket; -} - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/SelectServer.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/SelectServer.h deleted file mode 100644 index bb3b64f86..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/SelectServer.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef SELECT_SERVER_H -#define SELECT_SERVER_H - -void vStartSelectUDPServerTasks( uint16_t usStackSize, uint32_t ulFirstPortNumber, UBaseType_t uxPriority ); - -#endif /* SELECT_SERVER_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/SimpleClientAndServer.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/SimpleClientAndServer.h deleted file mode 100644 index 44e8ca13a..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/SimpleClientAndServer.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef SIMPLE_CLIENT_AND_SERVER_H -#define SIMPLE_CLIENT_AND_SERVER_H - -void vStartSimpleUDPClientServerTasks( uint16_t usStackSize, uint32_t ulsPort, UBaseType_t uxPriority ); - -#endif /* SIMPLE_CLIENT_AND_SERVER_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/UDPCommandInterpreter.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/UDPCommandInterpreter.h deleted file mode 100644 index 2cd88c5a5..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/DemoTasks/include/UDPCommandInterpreter.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef UDP_COMMAND_INTERPRETER_H -#define UDP_COMMAND_INTERPRETER_H - -void vStartUDPCommandInterpreterTask( uint16_t usStackSize, uint32_t ulPort, UBaseType_t uxPriority ); - -#endif /* UDP_COMMAND_INTERPRETER_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOSConfig.h deleted file mode 100644 index f49bf87e4..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOSConfig.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * http://www.freertos.org/a00110.html - * - * The bottom of this file contains some constants specific to running the UDP - * stack in this demo. Constants specific to FreeRTOS+UDP itself (rather than - * the demo) are contained in FreeRTOSIPConfig.h. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configMAX_PRIORITIES ( 7 ) -#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */ -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32U * 1024U ) ) -#define configMAX_TASK_NAME_LEN ( 7 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_CO_ROUTINES 0 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 0 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_ALTERNATIVE_API 0 - -/* Hook function related definitions. */ -#define configUSE_TICK_HOOK 0 -#define configUSE_IDLE_HOOK 1 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */ - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) - -/* Run time stats gathering definitions. */ -unsigned long ulGetRunTimeCounterValue( void ); -void vConfigureTimerForRunTimeStats( void ); -#define configGENERATE_RUN_TIME_STATS 1 -#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() -#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#define INCLUDE_xTimerGetTimerTaskHandle 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xQueueGetMutexHolder 1 - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 - -/* Assert call defined for debug builds. */ -#ifdef _DEBUG - extern void vAssertCalled( void ); - #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled() -#endif /* _DEBUG */ - - - -/* Application specific definitions follow. **********************************/ - -/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace -macros are defined to gather some UDP stack statistics that can then be viewed -through the CLI interface. */ -#define configINCLUDE_DEMO_DEBUG_STATS 1 - -/* The size of the global output buffer that is available for use when there -are multiple command interpreters running at once (for example, one on a UART -and one on TCP/IP). This is done to prevent an output buffer being defined by -each implementation - which would waste RAM. In this case, there is only one -command interpreter running, and it has its own local output buffer, so the -global buffer is just set to be one byte long as it is not used and should not -take up unnecessary RAM. */ -#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1 - -/* Only used when running in the FreeRTOS Windows simulator. Defines the -priority of the task used to simulate Ethernet interrupts. */ -#define configMAC_ISR_SIMULATOR_PRIORITY ( configMAX_PRIORITIES - 1 ) - -/* This demo creates a virtual network connection by accessing the raw Ethernet -or WiFi data to and from a real network connection. Many computers have more -than one real network port, and configNETWORK_INTERFACE_TO_USE is used to tell -the demo which real port should be used to create the virtual port. The ports -available are displayed on the console when the application is executed. For -example, on my development laptop setting configNETWORK_INTERFACE_TO_USE to 1 -results in the wired network being used, while setting -configNETWORK_INTERFACE_TO_USE to 2 results in the wireless network being -used. */ -#define configNETWORK_INTERFACE_TO_USE 4L - -/* Only when using BufferAllocation_1.c. */ -#define configUSE_STATIC_BUFFERS 1 - -/* The address of an echo server that will be used by the two demo echo client -tasks. -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */ -#define configECHO_SERVER_ADDR0 172 -#define configECHO_SERVER_ADDR1 25 -#define configECHO_SERVER_ADDR2 218 -#define configECHO_SERVER_ADDR3 100 - -/* Default MAC address configuration. The demo creates a virtual network -connection that uses this MAC address by accessing the raw Ethernet/WiFi data -to and from a real network connection on the host PC. See the -configNETWORK_INTERFACE_TO_USE definition above for information on how to -configure the real network connection to use. */ -#define configMAC_ADDR0 0x00 -#define configMAC_ADDR1 0x11 -#define configMAC_ADDR2 0x22 -#define configMAC_ADDR3 0x33 -#define configMAC_ADDR4 0x44 -#define configMAC_ADDR5 0x55 - -/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or -ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configIP_ADDR0 172 -#define configIP_ADDR1 25 -#define configIP_ADDR2 218 -#define configIP_ADDR3 200 - -/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to -0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configGATEWAY_ADDR0 192 -#define configGATEWAY_ADDR1 168 -#define configGATEWAY_ADDR2 1 -#define configGATEWAY_ADDR3 1 - -/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and -208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set -to 1 but a DNS server cannot be contacted.*/ -#define configDNS_SERVER_ADDR0 208 -#define configDNS_SERVER_ADDR1 67 -#define configDNS_SERVER_ADDR2 222 -#define configDNS_SERVER_ADDR3 222 - -/* Defalt netmask configuration. Used in ipconfigUSE_DNS is set to 0, or -ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configNET_MASK0 255 -#define configNET_MASK1 255 -#define configNET_MASK2 255 -#define configNET_MASK3 0 - -/* Provided to guard prints to the console with a semaphore. */ -void vOutputString( char *pcMessage ); - -#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOSIPConfig.h deleted file mode 100644 index 11d1c88ac..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOSIPConfig.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for configuration information. - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Configuration.shtml - * - *****************************************************************************/ - -#ifndef FREERTOS_IP_CONFIG_H -#define FREERTOS_IP_CONFIG_H - -/* The IP stack executes it its own task (although any application task can make -use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY -sets the priority of the task that executes the IP stack. The priority is a -standard FreeRTOS task priority so can take any value from 0 (the lowest -priority) to (configMAX_PRIORITIES - 1) (the highest priority). -configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in -FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to -the priority assigned to the task executing the IP stack relative to the -priority assigned to tasks that use the IP stack. */ -#define ipconfigUDP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) - -/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+UDP -task. This setting is less important when the FreeRTOS Win32 simulator is used -as the Win32 simulator only stores a fixed amount of information on the task -stack. FreeRTOS includes optional stack overflow detection, see: -http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigUDP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) - -/* ipconfigRAND32() is called by the IP stack to generate a random number that -is then used as a DHCP transaction number. Random number generation is performed -via this macro to allow applications to use their own random number generation -method. For example, it might be possible to generate a random number by -sampling noise on an analogue input. */ -#define ipconfigRAND32() 1 - -/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+UDP will call the -network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK -is not set to 1 then the network event hook will never be called. See -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml -*/ -#define ipconfigUSE_NETWORK_EVENT_HOOK 1 - -/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but -a network buffer cannot be obtained then the calling task is held in the Blocked -state (so other tasks can continue to executed) until either a network buffer -becomes available or the send block time expires. If the send block time expires -then the send operation is aborted. The maximum allowable send block time is -capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the -maximum allowable send block time prevents prevents a deadlock occurring when -all the network buffers are in use and the tasks that process (and subsequently -free) the network buffers are themselves blocked waiting for a network buffer. -ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in -milliseconds can be converted to a time in ticks by dividing the time in -milliseconds by portTICK_RATE_MS. */ -#define ipconfigMAX_SEND_BLOCK_TIME_TICKS ( 20 / portTICK_RATE_MS ) - -/* If ipconfigUSE_DHCP is 1 then FreeRTOS+UDP will attempt to retrieve an IP -address, netmask, DNS server address and gateway address from a DHCP server. If -ipconfigUSE_DHCP is 0 then FreeRTOS+UDP will use a static IP address. The -stack will revert to using the static IP address even when ipconfigUSE_DHCP is -set to 1 if a valid configuration cannot be obtained from a DHCP server for any -reason. The static configuration used is that passed into the stack by the -FreeRTOS_IPInit() function call. */ -#define ipconfigUSE_DHCP 1 - -/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at -increasing time intervals until either a reply is received from a DHCP server -and accepted, or the interval between transmissions reaches -ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the -static IP address passed as a parameter to FreeRTOS_IPInit() if the -re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without -a DHCP reply being received. */ -#ifdef _WINDOWS_ - /* The windows simulated time is not real time so the max delay is much - shorter. */ - #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 999 / portTICK_RATE_MS ) -#else - #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 120000 / portTICK_RATE_MS ) -#endif /* _WINDOWS_ */ - -/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP -stack can only send a UDP message to a remove IP address if it knowns the MAC -address associated with the IP address, or the MAC address of the router used to -contact the remote IP address. When a UDP message is received from a remote IP -address the MAC address and IP address are added to the ARP cache. When a UDP -message is sent to a remote IP address that does not already appear in the ARP -cache then the UDP message is replaced by a ARP message that solicits the -required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum -number of entries that can exist in the ARP table at any one time. */ -#define ipconfigARP_CACHE_ENTRIES 6 - -/* ARP requests that do not result in an ARP response will be re-transmitted a -maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is -aborted. */ -#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 ) - -/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP -table being created or refreshed and the entry being removed because it is stale. -New ARP requests are sent for ARP cache entries that are nearing their maximum -age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is -equal to 1500 seconds (or 25 minutes). */ -#define ipconfigMAX_ARP_AGE 150 - -/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling -routines, which are relatively large. To save code space the full -FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster -alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr() -takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter. -FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets -(for example, 192, 168, 0, 1) as its parameters. If -ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and -FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is -not set to 1 then only FreeRTOS_indet_addr_quick() is available. */ -#define ipconfigINCLUDE_FULL_INET_ADDR 1 - -/* ipconfigNUM_NETWORK_BUFFERS defines the total number of network buffer that -are available to the IP stack. The total number of network buffers is limited -to ensure the total amount of RAM that can be consumed by the IP stack is capped -to a pre-determinable value. */ -#define ipconfigNUM_NETWORK_BUFFERS 45 - -/* A FreeRTOS queue is used to send events from application tasks to the IP -stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can -be queued for processing at any one time. The event queue must be a minimum of -5 greater than the total number of network buffers. */ -#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFERS + 5 ) - -/* The address of a socket is the combination of its IP address and its port -number. FreeRTOS_bind() is used to manually allocate a port number to a socket -(to 'bind' the socket to a port), but manual binding is not normally necessary -for client sockets (those sockets that initiate outgoing connections rather than -wait for incoming connections on a known port number). If -ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling -FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP -stack automatically binding the socket to a port number from the range -socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If -ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto() -on a socket that has not yet been bound will result in the send operation being -aborted. */ -#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1 - -/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */ -#define updconfigIP_TIME_TO_LIVE 128 - -/* If ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 1 then UDP packets that -contain more data than will fit in a single network frame will be fragmented -across multiple IP packets. Also see the ipconfigNETWORK_MTU setting. If -ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must -be divisible by 8. Setting ipconfigCAN_FRAGMENT_OUTGOING_PACKETS to 1 will -increase both the code size and execution time. */ -#define ipconfigCAN_FRAGMENT_OUTGOING_PACKETS 0 - -/* The MTU is the maximum number of bytes the payload of a network frame can -contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a -lower value can save RAM, depending on the buffer management scheme used. If -ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must -be divisible by 8. */ -#define ipconfigNETWORK_MTU 1500 - -/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used -through the FreeRTOS_gethostbyname() API function. */ -#define ipconfigUSE_DNS 1 - -/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will -generate replies to incoming ICMP echo (ping) requests. */ -#define ipconfigREPLY_TO_INCOMING_PINGS 1 - -/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the -FreeRTOS_SendPingRequest() API function is available. */ -#define ipconfigSUPPORT_OUTGOING_PINGS 1 - -/* If ipconfigSUPPORT_SELECT_FUNCTION is set to 1 then the FreeRTOS_select() -(and associated) API function is available. */ -#define ipconfigSUPPORT_SELECT_FUNCTION 1 - -/* Used for stack testing only, and must be implemented in the network -interface. */ -#define updconfigLOOPBACK_ETHERNET_PACKETS 0 - -/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames -that are not in Ethernet II format will be dropped. This option is included for -potential future IP stack developments. */ -#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1 - -/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the -responsibility of the Ethernet interface to filter out packets that are of no -interest. If the Ethernet interface does not implement this functionality, then -set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack -perform the filtering instead (it is much less efficient for the stack to do it -because the packet will already have been passed into the stack). If the -Ethernet driver does all the necessary filtering in hardware then software -filtering can be removed by using a value other than 1 or 0. */ -#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 1 - -/* The windows simulator cannot really simulate MAC interrupts, and needs to -block occasionally to allow other tasks to run. */ -#ifdef _WINDOWS_ - #define configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ( 3 / portTICK_RATE_MS ) -#endif - -/* The example IP trace macros are included here so the definitions are -available in all the FreeRTOS+UDP source files. */ -#include "DemoIPTrace.h" - -#endif /* FREERTOS_IP_CONFIG_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.sln deleted file mode 100644 index 3f819af17..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.sln +++ /dev/null @@ -1,20 +0,0 @@ - -Microsoft Visual Studio Solution File, Format Version 11.00 -# Visual C++ Express 2010 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WIN32", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" -EndProject -Global - GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|Win32 = Debug|Win32 - Release|Win32 = Release|Win32 - EndGlobalSection - GlobalSection(ProjectConfigurationPlatforms) = postSolution - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32 - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection -EndGlobal diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/READ_ME.url b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/READ_ME.url deleted file mode 100644 index 0d3763ac5..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/READ_ME.url +++ /dev/null @@ -1,5 +0,0 @@ -[InternetShortcut] -URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_CLI_Windows_Simulator.shtml -IDList= -[{000214A0-0000-0000-C000-000000000046}] -Prop3=19,2 diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/ReadMe.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/ReadMe.txt new file mode 100644 index 000000000..24bb5461e --- /dev/null +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/ReadMe.txt @@ -0,0 +1,4 @@ +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/Run-time-stats-utils.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/Run-time-stats-utils.c deleted file mode 100644 index 538fb29bf..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/Run-time-stats-utils.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * Utility functions required to gather run time statistics. See: - * http://www.freertos.org/rtos-run-time-stats.html - * - * Note that this is a simulated port, where simulated time is a lot slower than - * real time, therefore the run time counter values have no real meaningful - * units. - * - * Also note that it is assumed this demo is going to be used for short periods - * of time only, and therefore timer overflows are not handled. -*/ - -/* FreeRTOS includes. */ -#include - -/* Variables used in the creation of the run time stats time base. Run time -stats record how much time each task spends in the Running state. */ -static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL; - -/*-----------------------------------------------------------*/ - -void vConfigureTimerForRunTimeStats( void ) -{ -LARGE_INTEGER liPerformanceCounterFrequency, liInitialRunTimeValue; - - /* Initialise the variables used to create the run time stats time base. - Run time stats record how much time each task spends in the Running - state. */ - - if( QueryPerformanceFrequency( &liPerformanceCounterFrequency ) == 0 ) - { - llTicksPerHundedthMillisecond = 1; - } - else - { - /* How many times does the performance counter increment in 1/100th - millisecond. */ - llTicksPerHundedthMillisecond = liPerformanceCounterFrequency.QuadPart / 100000LL; - - /* What is the performance counter value now, this will be subtracted - from readings taken at run time. */ - QueryPerformanceCounter( &liInitialRunTimeValue ); - llInitialRunTimeCounterValue = liInitialRunTimeValue.QuadPart; - } -} -/*-----------------------------------------------------------*/ - -unsigned long ulGetRunTimeCounterValue( void ) -{ -LARGE_INTEGER liCurrentCount; -unsigned long ulReturn; - - /* What is the performance counter value now? */ - QueryPerformanceCounter( &liCurrentCount ); - - /* Subtract the performance counter value reading taken when the - application started to get a count from that reference point, then - scale to (simulated) 1/100ths of a millisecond. */ - if( llTicksPerHundedthMillisecond == 0 ) - { - /* The trace macros can call this function before the kernel has been - started, in which case llTicksPerHundedthMillisecond will not have been - initialised. */ - ulReturn = 0; - } - else - { - ulReturn = ( unsigned long ) ( ( liCurrentCount.QuadPart - llInitialRunTimeCounterValue ) / llTicksPerHundedthMillisecond ); - } - - return ulReturn; -} -/*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj deleted file mode 100644 index 78206e497..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj +++ /dev/null @@ -1,172 +0,0 @@ - - - - - Debug - Win32 - - - Release - Win32 - - - - {C686325E-3261-42F7-AEB1-DDE5280E1CEB} - RTOSDemo - - - - Application - false - MultiByte - - - Application - false - MultiByte - - - - - - - - - - - - - - - <_ProjectFileVersion>10.0.30319.1 - .\Debug\ - .\Debug\ - true - .\Release\ - .\Release\ - false - - - - .\Debug/WIN32.tlb - - - - - Disabled - .\Trace_Recorder_Configuration;..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients;..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1;..\..\Source\FreeRTOS-Plus-UDP\portable\BufferManagement;.\DemoTasks\include;..\..\Source\FreeRTOS-Plus-UDP\portable\Compiler\MSVC;.\WinPCap;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\Source\FreeRTOS-Plus-CLI;..\..\Source\FreeRTOS-Plus-Trace\Include;..\..\Source\FreeRTOS-Plus-UDP\include;.;%(AdditionalIncludeDirectories) - WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - EnableFastChecks - MultiThreadedDebug - .\Debug/WIN32.pch - .\Debug/ - .\Debug/ - .\Debug/ - Level4 - true - false - EditAndContinue - /wd4210 %(AdditionalOptions) - - - _DEBUG;%(PreprocessorDefinitions) - 0x0c09 - - - .\Debug/RTOSDemo.exe - true - true - .\Debug/WIN32.pdb - Console - MachineX86 - wpcap.lib;%(AdditionalDependencies) - .\WinPCap - - - true - .\Debug/WIN32.bsc - - - - - .\Release/WIN32.tlb - - - - - MaxSpeed - OnlyExplicitInline - _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - MultiThreaded - true - .\Release/WIN32.pch - .\Release/ - .\Release/ - .\Release/ - Level3 - true - ..\Common\Utils;..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap;..\Common\ethernet\lwip-1.4.0\src\include\ipv4;..\Common\ethernet\lwip-1.4.0\src\include;..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\ethernet\lwip-1.4.0\ports\win32\include;..\Common\Include;.\lwIP_Apps;.;%(AdditionalIncludeDirectories) - - - NDEBUG;%(PreprocessorDefinitions) - 0x0c09 - - - .\Release/RTOSDemo.exe - true - .\Release/WIN32.pdb - Console - MachineX86 - ..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap - wpcap.lib;%(AdditionalDependencies) - - - true - .\Release/WIN32.bsc - - - - - - - - - - - - - - - - true - - - - - - - - - - - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj.filters b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj.filters deleted file mode 100644 index dd25ff982..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj.filters +++ /dev/null @@ -1,139 +0,0 @@ - - - - - {38712199-cebf-4124-bf15-398f7c3419ea} - ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe - - - {34567deb-d5ab-4a56-8640-0aaec609521a} - cpp;c;cxx;rc;def;r;odl;idl;hpj;bat - - - {af3445a1-4908-4170-89ed-39345d90d30c} - - - {f32be356-4763-4cae-9020-974a2638cb08} - *.c - - - {88f409e6-d396-4ac5-94bd-7a99c914be46} - - - {e5ad4ec7-23dc-4295-8add-2acaee488f5a} - - - {fd43c0ed-fdbc-437f-a5a3-c50399690bd7} - - - {8672fa26-b119-481f-8b8d-086419c01a3e} - - - {4570be11-ec96-4b55-ac58-24b50ada980a} - - - {5d93ed51-023a-41ad-9243-8d230165d34b} - - - {b71e974a-9f28-4815-972b-d930ba8a34d0} - - - {19ff1a34-36de-4c48-9d10-3fb1fa0d1fa4} - h;hpp;hxx;hm;inl - - - {c5889fe2-af0f-4cea-927f-6a6935ec5e14} - - - - - Demo App Source - - - FreeRTOS\Source\Portable - - - FreeRTOS\Source - - - FreeRTOS\Source - - - FreeRTOS\Source - - - FreeRTOS\Source - - - Demo App Source - - - Demo App Source\DemoTasks - - - Demo App Source\DemoTasks - - - FreeRTOS\Source\Portable - - - FreeRTOS+\FreeRTOS+UDP - - - FreeRTOS+\FreeRTOS+UDP - - - FreeRTOS+\FreeRTOS+UDP - - - FreeRTOS+\FreeRTOS+UDP - - - FreeRTOS+\FreeRTOS+UDP\portable - - - FreeRTOS+\FreeRTOS+UDP\portable - - - FreeRTOS+\FreeRTOS+CLI - - - Demo App Source - - - Demo App Source\DemoTasks - - - Demo App Source\DemoTasks - - - Demo App Source\DemoTasks - - - FreeRTOS+\FreeRTOS+UDP\portable - - - - - Demo App Source\Configuration Files - - - Demo App Source\Configuration Files - - - FreeRTOS+\FreeRTOS+UDP\include - - - FreeRTOS+\FreeRTOS+UDP\include - - - FreeRTOS+\FreeRTOS+UDP\include - - - FreeRTOS+\FreeRTOS+UDP\include - - - FreeRTOS+\FreeRTOS+CLI\include - - - \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj.user b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj.user deleted file mode 100644 index 695b5c78b..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WIN32.vcxproj.user +++ /dev/null @@ -1,3 +0,0 @@ - - - \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/Packet32.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/Packet32.h deleted file mode 100644 index 1e0eacd77..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/Packet32.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * Copyright (c) 1999 - 2005 NetGroup, Politecnico di Torino (Italy) - * Copyright (c) 2005 - 2007 CACE Technologies, Davis (California) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Politecnico di Torino, CACE Technologies - * nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** @ingroup packetapi - * @{ - */ - -/** @defgroup packet32h Packet.dll definitions and data structures - * Packet32.h contains the data structures and the definitions used by packet.dll. - * The file is used both by the Win9x and the WinNTx versions of packet.dll, and can be included - * by the applications that use the functions of this library - * @{ - */ - -#ifndef __PACKET32 -#define __PACKET32 - -#include - -#ifdef HAVE_AIRPCAP_API -#include -#else -#if !defined(AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_) -#define AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ -typedef struct _AirpcapHandle *PAirpcapHandle; -#endif /* AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ */ -#endif /* HAVE_AIRPCAP_API */ - -#ifdef HAVE_DAG_API -#include -#endif /* HAVE_DAG_API */ - -// Working modes -#define PACKET_MODE_CAPT 0x0 ///< Capture mode -#define PACKET_MODE_STAT 0x1 ///< Statistical mode -#define PACKET_MODE_MON 0x2 ///< Monitoring mode -#define PACKET_MODE_DUMP 0x10 ///< Dump mode -#define PACKET_MODE_STAT_DUMP MODE_DUMP | MODE_STAT ///< Statistical dump Mode - - -/// Alignment macro. Defines the alignment size. -#define Packet_ALIGNMENT sizeof(int) -/// Alignment macro. Rounds up to the next even multiple of Packet_ALIGNMENT. -#define Packet_WORDALIGN(x) (((x)+(Packet_ALIGNMENT-1))&~(Packet_ALIGNMENT-1)) - -#define NdisMediumNull -1 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumCHDLC -2 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumPPPSerial -3 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumBare80211 -4 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumRadio80211 -5 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumPpi -6 ///< Custom linktype: NDIS doesn't provide an equivalent - -// Loopback behaviour definitions -#define NPF_DISABLE_LOOPBACK 1 ///< Drop the packets sent by the NPF driver -#define NPF_ENABLE_LOOPBACK 2 ///< Capture the packets sent by the NPF driver - -/*! - \brief Network type structure. - - This structure is used by the PacketGetNetType() function to return information on the current adapter's type and speed. -*/ -typedef struct NetType -{ - UINT LinkType; ///< The MAC of the current network adapter (see function PacketGetNetType() for more information) - ULONGLONG LinkSpeed; ///< The speed of the network in bits per second -}NetType; - - -//some definitions stolen from libpcap - -#ifndef BPF_MAJOR_VERSION - -/*! - \brief A BPF pseudo-assembly program. - - The program will be injected in the kernel by the PacketSetBPF() function and applied to every incoming packet. -*/ -struct bpf_program -{ - UINT bf_len; ///< Indicates the number of instructions of the program, i.e. the number of struct bpf_insn that will follow. - struct bpf_insn *bf_insns; ///< A pointer to the first instruction of the program. -}; - -/*! - \brief A single BPF pseudo-instruction. - - bpf_insn contains a single instruction for the BPF register-machine. It is used to send a filter program to the driver. -*/ -struct bpf_insn -{ - USHORT code; ///< Instruction type and addressing mode. - UCHAR jt; ///< Jump if true - UCHAR jf; ///< Jump if false - int k; ///< Generic field used for various purposes. -}; - -/*! - \brief Structure that contains a couple of statistics values on the current capture. - - It is used by packet.dll to return statistics about a capture session. -*/ -struct bpf_stat -{ - UINT bs_recv; ///< Number of packets that the driver received from the network adapter - ///< from the beginning of the current capture. This value includes the packets - ///< lost by the driver. - UINT bs_drop; ///< number of packets that the driver lost from the beginning of a capture. - ///< Basically, a packet is lost when the the buffer of the driver is full. - ///< In this situation the packet cannot be stored and the driver rejects it. - UINT ps_ifdrop; ///< drops by interface. XXX not yet supported - UINT bs_capt; ///< number of packets that pass the filter, find place in the kernel buffer and - ///< thus reach the application. -}; - -/*! - \brief Packet header. - - This structure defines the header associated with every packet delivered to the application. -*/ -struct bpf_hdr -{ - struct timeval bh_tstamp; ///< The timestamp associated with the captured packet. - ///< It is stored in a TimeVal structure. - UINT bh_caplen; ///< Length of captured portion. The captured portion can be different - ///< from the original packet, because it is possible (with a proper filter) - ///< to instruct the driver to capture only a portion of the packets. - UINT bh_datalen; ///< Original length of packet - USHORT bh_hdrlen; ///< Length of bpf header (this struct plus alignment padding). In some cases, - ///< a padding could be added between the end of this structure and the packet - ///< data for performance reasons. This filed can be used to retrieve the actual data - ///< of the packet. -}; - -/*! - \brief Dump packet header. - - This structure defines the header associated with the packets in a buffer to be used with PacketSendPackets(). - It is simpler than the bpf_hdr, because it corresponds to the header associated by WinPcap and libpcap to a - packet in a dump file. This makes straightforward sending WinPcap dump files to the network. -*/ -struct dump_bpf_hdr{ - struct timeval ts; ///< Time stamp of the packet - UINT caplen; ///< Length of captured portion. The captured portion can smaller than the - ///< the original packet, because it is possible (with a proper filter) to - ///< instruct the driver to capture only a portion of the packets. - UINT len; ///< Length of the original packet (off wire). -}; - - -#endif - -struct bpf_stat; - -#define DOSNAMEPREFIX TEXT("Packet_") ///< Prefix added to the adapters device names to create the WinPcap devices -#define MAX_LINK_NAME_LENGTH 64 //< Maximum length of the devices symbolic links -#define NMAX_PACKET 65535 - -/*! - \brief Addresses of a network adapter. - - This structure is used by the PacketGetNetInfoEx() function to return the IP addresses associated with - an adapter. -*/ -typedef struct npf_if_addr { - struct sockaddr_storage IPAddress; ///< IP address. - struct sockaddr_storage SubnetMask; ///< Netmask for that address. - struct sockaddr_storage Broadcast; ///< Broadcast address. -}npf_if_addr; - - -#define ADAPTER_NAME_LENGTH 256 + 12 ///< Maximum length for the name of an adapter. The value is the same used by the IP Helper API. -#define ADAPTER_DESC_LENGTH 128 ///< Maximum length for the description of an adapter. The value is the same used by the IP Helper API. -#define MAX_MAC_ADDR_LENGTH 8 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. -#define MAX_NETWORK_ADDRESSES 16 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. - - -typedef struct WAN_ADAPTER_INT WAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API -typedef WAN_ADAPTER *PWAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API - -#define INFO_FLAG_NDIS_ADAPTER 0 ///< Flag for ADAPTER_INFO: this is a traditional ndis adapter -#define INFO_FLAG_NDISWAN_ADAPTER 1 ///< Flag for ADAPTER_INFO: this is a NdisWan adapter, and it's managed by WANPACKET -#define INFO_FLAG_DAG_CARD 2 ///< Flag for ADAPTER_INFO: this is a DAG card -#define INFO_FLAG_DAG_FILE 6 ///< Flag for ADAPTER_INFO: this is a DAG file -#define INFO_FLAG_DONT_EXPORT 8 ///< Flag for ADAPTER_INFO: when this flag is set, the adapter will not be listed or openend by winpcap. This allows to prevent exporting broken network adapters, like for example FireWire ones. -#define INFO_FLAG_AIRPCAP_CARD 16 ///< Flag for ADAPTER_INFO: this is an airpcap card -#define INFO_FLAG_NPFIM_DEVICE 32 - -/*! - \brief Describes an opened network adapter. - - This structure is the most important for the functioning of packet.dll, but the great part of its fields - should be ignored by the user, since the library offers functions that avoid to cope with low-level parameters -*/ -typedef struct _ADAPTER { - HANDLE hFile; ///< \internal Handle to an open instance of the NPF driver. - CHAR SymbolicLink[MAX_LINK_NAME_LENGTH]; ///< \internal A string containing the name of the network adapter currently opened. - int NumWrites; ///< \internal Number of times a packets written on this adapter will be repeated - ///< on the wire. - HANDLE ReadEvent; ///< A notification event associated with the read calls on the adapter. - ///< It can be passed to standard Win32 functions (like WaitForSingleObject - ///< or WaitForMultipleObjects) to wait until the driver's buffer contains some - ///< data. It is particularly useful in GUI applications that need to wait - ///< concurrently on several events. In Windows NT/2000 the PacketSetMinToCopy() - ///< function can be used to define the minimum amount of data in the kernel buffer - ///< that will cause the event to be signalled. - - UINT ReadTimeOut; ///< \internal The amount of time after which a read on the driver will be released and - ///< ReadEvent will be signaled, also if no packets were captured - CHAR Name[ADAPTER_NAME_LENGTH]; - PWAN_ADAPTER pWanAdapter; - UINT Flags; ///< Adapter's flags. Tell if this adapter must be treated in a different way, using the Netmon API or the dagc API. - -#ifdef HAVE_AIRPCAP_API - PAirpcapHandle AirpcapAd; -#endif // HAVE_AIRPCAP_API - -#ifdef HAVE_NPFIM_API - void* NpfImHandle; -#endif // HAVE_NPFIM_API - -#ifdef HAVE_DAG_API - dagc_t *pDagCard; ///< Pointer to the dagc API adapter descriptor for this adapter - PCHAR DagBuffer; ///< Pointer to the buffer with the packets that is received from the DAG card - struct timeval DagReadTimeout; ///< Read timeout. The dagc API requires a timeval structure - unsigned DagFcsLen; ///< Length of the frame check sequence attached to any packet by the card. Obtained from the registry - DWORD DagFastProcess; ///< True if the user requests fast capture processing on this card. Higher level applications can use this value to provide a faster but possibly unprecise capture (for example, libpcap doesn't convert the timestamps). -#endif // HAVE_DAG_API -} ADAPTER, *LPADAPTER; - -/*! - \brief Structure that contains a group of packets coming from the driver. - - This structure defines the header associated with every packet delivered to the application. -*/ -typedef struct _PACKET { - HANDLE hEvent; ///< \deprecated Still present for compatibility with old applications. - OVERLAPPED OverLapped; ///< \deprecated Still present for compatibility with old applications. - PVOID Buffer; ///< Buffer with containing the packets. See the PacketReceivePacket() for - ///< details about the organization of the data in this buffer - UINT Length; ///< Length of the buffer - DWORD ulBytesReceived; ///< Number of valid bytes present in the buffer, i.e. amount of data - ///< received by the last call to PacketReceivePacket() - BOOLEAN bIoComplete; ///< \deprecated Still present for compatibility with old applications. -} PACKET, *LPPACKET; - -/*! - \brief Structure containing an OID request. - - It is used by the PacketRequest() function to send an OID to the interface card driver. - It can be used, for example, to retrieve the status of the error counters on the adapter, its MAC address, - the list of the multicast groups defined on it, and so on. -*/ -struct _PACKET_OID_DATA { - ULONG Oid; ///< OID code. See the Microsoft DDK documentation or the file ntddndis.h - ///< for a complete list of valid codes. - ULONG Length; ///< Length of the data field - UCHAR Data[1]; ///< variable-lenght field that contains the information passed to or received - ///< from the adapter. -}; -typedef struct _PACKET_OID_DATA PACKET_OID_DATA, *PPACKET_OID_DATA; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @} - */ - -/* -BOOLEAN QueryWinPcapRegistryStringA(CHAR *SubKeyName, - CHAR *Value, - UINT *pValueLen, - CHAR *DefaultVal); - -BOOLEAN QueryWinPcapRegistryStringW(WCHAR *SubKeyName, - WCHAR *Value, - UINT *pValueLen, - WCHAR *DefaultVal); -*/ - -//--------------------------------------------------------------------------- -// EXPORTED FUNCTIONS -//--------------------------------------------------------------------------- - -PCHAR PacketGetVersion(); -PCHAR PacketGetDriverVersion(); -BOOLEAN PacketSetMinToCopy(LPADAPTER AdapterObject,int nbytes); -BOOLEAN PacketSetNumWrites(LPADAPTER AdapterObject,int nwrites); -BOOLEAN PacketSetMode(LPADAPTER AdapterObject,int mode); -BOOLEAN PacketSetReadTimeout(LPADAPTER AdapterObject,int timeout); -BOOLEAN PacketSetBpf(LPADAPTER AdapterObject,struct bpf_program *fp); -BOOLEAN PacketSetLoopbackBehavior(LPADAPTER AdapterObject, UINT LoopbackBehavior); -INT PacketSetSnapLen(LPADAPTER AdapterObject,int snaplen); -BOOLEAN PacketGetStats(LPADAPTER AdapterObject,struct bpf_stat *s); -BOOLEAN PacketGetStatsEx(LPADAPTER AdapterObject,struct bpf_stat *s); -BOOLEAN PacketSetBuff(LPADAPTER AdapterObject,int dim); -BOOLEAN PacketGetNetType (LPADAPTER AdapterObject,NetType *type); -LPADAPTER PacketOpenAdapter(PCHAR AdapterName); -BOOLEAN PacketSendPacket(LPADAPTER AdapterObject,LPPACKET pPacket,BOOLEAN Sync); -INT PacketSendPackets(LPADAPTER AdapterObject,PVOID PacketBuff,ULONG Size, BOOLEAN Sync); -LPPACKET PacketAllocatePacket(void); -VOID PacketInitPacket(LPPACKET lpPacket,PVOID Buffer,UINT Length); -VOID PacketFreePacket(LPPACKET lpPacket); -BOOLEAN PacketReceivePacket(LPADAPTER AdapterObject,LPPACKET lpPacket,BOOLEAN Sync); -BOOLEAN PacketSetHwFilter(LPADAPTER AdapterObject,ULONG Filter); -BOOLEAN PacketGetAdapterNames(PTSTR pStr,PULONG BufferSize); -BOOLEAN PacketGetNetInfoEx(PCHAR AdapterName, npf_if_addr* buffer, PLONG NEntries); -BOOLEAN PacketRequest(LPADAPTER AdapterObject,BOOLEAN Set,PPACKET_OID_DATA OidData); -HANDLE PacketGetReadEvent(LPADAPTER AdapterObject); -BOOLEAN PacketSetDumpName(LPADAPTER AdapterObject, void *name, int len); -BOOLEAN PacketSetDumpLimits(LPADAPTER AdapterObject, UINT maxfilesize, UINT maxnpacks); -BOOLEAN PacketIsDumpEnded(LPADAPTER AdapterObject, BOOLEAN sync); -BOOL PacketStopDriver(); -VOID PacketCloseAdapter(LPADAPTER lpAdapter); -BOOLEAN PacketStartOem(PCHAR errorString, UINT errorStringLength); -BOOLEAN PacketStartOemEx(PCHAR errorString, UINT errorStringLength, ULONG flags); -PAirpcapHandle PacketGetAirPcapHandle(LPADAPTER AdapterObject); - -// -// Used by PacketStartOemEx -// -#define PACKET_START_OEM_NO_NETMON 0x00000001 - -#ifdef __cplusplus -} -#endif - -#endif //__PACKET32 diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/PacketData.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/PacketData.h deleted file mode 100644 index 8124db66d..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/PacketData.h +++ /dev/null @@ -1,267 +0,0 @@ -char pkt1[] = { -0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, -0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, -0x00, 0x30, 0x09, 0x9c, 0x40, 0x00, 0x80, 0x06, -0x6f, 0x07, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, -0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, -0xc7, 0x35, 0x00, 0x00, 0x00, 0x00, 0x70, 0x02, -0x40, 0x00, 0xdf, 0xab, 0x00, 0x00, 0x02, 0x04, -0x05, 0xb4, 0x01, 0x01, 0x04, 0x02 }; - -char pkt2[] = { -0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, -0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, -0x00, 0x2c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, -0xf8, 0xa6, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, -0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, -0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, -0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, -0x05, 0x92 }; - -char pkt3[] = { -0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, -0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, -0x00, 0x28, 0x09, 0x9e, 0x40, 0x00, 0x80, 0x06, -0x6f, 0x0d, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, -0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, -0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, -0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; - -char pkt4[] = { -0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, -0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, -0x02, 0x27, 0x09, 0x9f, 0x40, 0x00, 0x80, 0x06, -0x6d, 0x0d, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, -0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, -0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x18, -0x42, 0xd8, 0x84, 0x3e, 0x00, 0x00, 0x47, 0x45, -0x54, 0x20, 0x2f, 0x20, 0x48, 0x54, 0x54, 0x50, -0x2f, 0x31, 0x2e, 0x31, 0x0d, 0x0a, 0x41, 0x63, -0x63, 0x65, 0x70, 0x74, 0x3a, 0x20, 0x69, 0x6d, -0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0x2c, -0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x78, -0x2d, 0x78, 0x62, 0x69, 0x74, 0x6d, 0x61, 0x70, -0x2c, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, -0x6a, 0x70, 0x65, 0x67, 0x2c, 0x20, 0x69, 0x6d, -0x61, 0x67, 0x65, 0x2f, 0x70, 0x6a, 0x70, 0x65, -0x67, 0x2c, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, -0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, -0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, 0x65, 0x78, -0x63, 0x65, 0x6c, 0x2c, 0x20, 0x61, 0x70, 0x70, -0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, -0x2f, 0x6d, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x2c, -0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, -0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, 0x6e, 0x64, -0x2e, 0x6d, 0x73, 0x2d, 0x70, 0x6f, 0x77, 0x65, -0x72, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x2c, 0x20, -0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, -0x69, 0x6f, 0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, -0x2d, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, -0x74, 0x69, 0x6f, 0x6e, 0x2c, 0x20, 0x61, 0x70, -0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, -0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, 0x2d, 0x78, -0x62, 0x61, 0x70, 0x2c, 0x20, 0x61, 0x70, 0x70, -0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, -0x2f, 0x76, 0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, -0x78, 0x70, 0x73, 0x64, 0x6f, 0x63, 0x75, 0x6d, -0x65, 0x6e, 0x74, 0x2c, 0x20, 0x61, 0x70, 0x70, -0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, -0x2f, 0x78, 0x61, 0x6d, 0x6c, 0x2b, 0x78, 0x6d, -0x6c, 0x2c, 0x20, 0x2a, 0x2f, 0x2a, 0x0d, 0x0a, -0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x4c, -0x61, 0x6e, 0x67, 0x75, 0x61, 0x67, 0x65, 0x3a, -0x20, 0x65, 0x6e, 0x2d, 0x67, 0x62, 0x0d, 0x0a, -0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x45, -0x6e, 0x63, 0x6f, 0x64, 0x69, 0x6e, 0x67, 0x3a, -0x20, 0x67, 0x7a, 0x69, 0x70, 0x2c, 0x20, 0x64, -0x65, 0x66, 0x6c, 0x61, 0x74, 0x65, 0x0d, 0x0a, -0x55, 0x73, 0x65, 0x72, 0x2d, 0x41, 0x67, 0x65, -0x6e, 0x74, 0x3a, 0x20, 0x4d, 0x6f, 0x7a, 0x69, -0x6c, 0x6c, 0x61, 0x2f, 0x34, 0x2e, 0x30, 0x20, -0x28, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, -0x62, 0x6c, 0x65, 0x3b, 0x20, 0x4d, 0x53, 0x49, -0x45, 0x20, 0x36, 0x2e, 0x30, 0x3b, 0x20, 0x57, -0x69, 0x6e, 0x64, 0x6f, 0x77, 0x73, 0x20, 0x4e, -0x54, 0x20, 0x35, 0x2e, 0x31, 0x3b, 0x20, 0x53, -0x56, 0x31, 0x3b, 0x20, 0x47, 0x6f, 0x6f, 0x67, -0x6c, 0x65, 0x54, 0x35, 0x3b, 0x20, 0x2e, 0x4e, -0x45, 0x54, 0x20, 0x43, 0x4c, 0x52, 0x20, 0x32, -0x2e, 0x30, 0x2e, 0x35, 0x30, 0x37, 0x32, 0x37, -0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, -0x4c, 0x52, 0x20, 0x33, 0x2e, 0x30, 0x2e, 0x30, -0x34, 0x35, 0x30, 0x36, 0x2e, 0x36, 0x34, 0x38, -0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, -0x4c, 0x52, 0x20, 0x33, 0x2e, 0x35, 0x2e, 0x32, -0x31, 0x30, 0x32, 0x32, 0x29, 0x0d, 0x0a, 0x48, -0x6f, 0x73, 0x74, 0x3a, 0x20, 0x31, 0x39, 0x32, -0x2e, 0x31, 0x36, 0x38, 0x2e, 0x30, 0x2e, 0x31, -0x32, 0x0d, 0x0a, 0x43, 0x6f, 0x6e, 0x6e, 0x65, -0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x4b, -0x65, 0x65, 0x70, 0x2d, 0x41, 0x6c, 0x69, 0x76, -0x65, 0x0d, 0x0a, 0x0d, 0x0a }; - -char pkt5[] = { -0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, -0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, -0x00, 0x2c, 0x00, 0x02, 0x00, 0x00, 0x40, 0x06, -0xf8, 0xa5, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, -0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, -0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, -0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, -0x05, 0x92 }; - -char pkt6[] = { -0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, -0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, -0x00, 0x28, 0x09, 0xa1, 0x40, 0x00, 0x80, 0x06, -0x6f, 0x0a, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, -0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, -0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, -0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; - -char pkt7[] = { -0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, -0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, -0x02, 0x27, 0x09, 0xa2, 0x40, 0x00, 0x80, 0x06, -0x6d, 0x0a, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, -0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, -0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x18, -0x42, 0xd8, 0x84, 0x3e, 0x00, 0x00, 0x47, 0x45, -0x54, 0x20, 0x2f, 0x20, 0x48, 0x54, 0x54, 0x50, -0x2f, 0x31, 0x2e, 0x31, 0x0d, 0x0a, 0x41, 0x63, -0x63, 0x65, 0x70, 0x74, 0x3a, 0x20, 0x69, 0x6d, -0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0x2c, -0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x78, -0x2d, 0x78, 0x62, 0x69, 0x74, 0x6d, 0x61, 0x70, -0x2c, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, -0x6a, 0x70, 0x65, 0x67, 0x2c, 0x20, 0x69, 0x6d, -0x61, 0x67, 0x65, 0x2f, 0x70, 0x6a, 0x70, 0x65, -0x67, 0x2c, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, -0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, -0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, 0x65, 0x78, -0x63, 0x65, 0x6c, 0x2c, 0x20, 0x61, 0x70, 0x70, -0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, -0x2f, 0x6d, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x2c, -0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, -0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, 0x6e, 0x64, -0x2e, 0x6d, 0x73, 0x2d, 0x70, 0x6f, 0x77, 0x65, -0x72, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x2c, 0x20, -0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, -0x69, 0x6f, 0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, -0x2d, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, -0x74, 0x69, 0x6f, 0x6e, 0x2c, 0x20, 0x61, 0x70, -0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, -0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, 0x2d, 0x78, -0x62, 0x61, 0x70, 0x2c, 0x20, 0x61, 0x70, 0x70, -0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, -0x2f, 0x76, 0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, -0x78, 0x70, 0x73, 0x64, 0x6f, 0x63, 0x75, 0x6d, -0x65, 0x6e, 0x74, 0x2c, 0x20, 0x61, 0x70, 0x70, -0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, -0x2f, 0x78, 0x61, 0x6d, 0x6c, 0x2b, 0x78, 0x6d, -0x6c, 0x2c, 0x20, 0x2a, 0x2f, 0x2a, 0x0d, 0x0a, -0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x4c, -0x61, 0x6e, 0x67, 0x75, 0x61, 0x67, 0x65, 0x3a, -0x20, 0x65, 0x6e, 0x2d, 0x67, 0x62, 0x0d, 0x0a, -0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x45, -0x6e, 0x63, 0x6f, 0x64, 0x69, 0x6e, 0x67, 0x3a, -0x20, 0x67, 0x7a, 0x69, 0x70, 0x2c, 0x20, 0x64, -0x65, 0x66, 0x6c, 0x61, 0x74, 0x65, 0x0d, 0x0a, -0x55, 0x73, 0x65, 0x72, 0x2d, 0x41, 0x67, 0x65, -0x6e, 0x74, 0x3a, 0x20, 0x4d, 0x6f, 0x7a, 0x69, -0x6c, 0x6c, 0x61, 0x2f, 0x34, 0x2e, 0x30, 0x20, -0x28, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, -0x62, 0x6c, 0x65, 0x3b, 0x20, 0x4d, 0x53, 0x49, -0x45, 0x20, 0x36, 0x2e, 0x30, 0x3b, 0x20, 0x57, -0x69, 0x6e, 0x64, 0x6f, 0x77, 0x73, 0x20, 0x4e, -0x54, 0x20, 0x35, 0x2e, 0x31, 0x3b, 0x20, 0x53, -0x56, 0x31, 0x3b, 0x20, 0x47, 0x6f, 0x6f, 0x67, -0x6c, 0x65, 0x54, 0x35, 0x3b, 0x20, 0x2e, 0x4e, -0x45, 0x54, 0x20, 0x43, 0x4c, 0x52, 0x20, 0x32, -0x2e, 0x30, 0x2e, 0x35, 0x30, 0x37, 0x32, 0x37, -0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, -0x4c, 0x52, 0x20, 0x33, 0x2e, 0x30, 0x2e, 0x30, -0x34, 0x35, 0x30, 0x36, 0x2e, 0x36, 0x34, 0x38, -0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, -0x4c, 0x52, 0x20, 0x33, 0x2e, 0x35, 0x2e, 0x32, -0x31, 0x30, 0x32, 0x32, 0x29, 0x0d, 0x0a, 0x48, -0x6f, 0x73, 0x74, 0x3a, 0x20, 0x31, 0x39, 0x32, -0x2e, 0x31, 0x36, 0x38, 0x2e, 0x30, 0x2e, 0x31, -0x32, 0x0d, 0x0a, 0x43, 0x6f, 0x6e, 0x6e, 0x65, -0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x4b, -0x65, 0x65, 0x70, 0x2d, 0x41, 0x6c, 0x69, 0x76, -0x65, 0x0d, 0x0a, 0x0d, 0x0a }; - -char pkt8[] = { -0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, -0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, -0x00, 0x2c, 0x00, 0x03, 0x00, 0x00, 0x40, 0x06, -0xf8, 0xa4, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, -0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, -0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, -0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, -0x05, 0x92 }; - -char pkt9[] = { -0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, -0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, -0x00, 0x28, 0x09, 0xa3, 0x40, 0x00, 0x80, 0x06, -0x6f, 0x08, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, -0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, -0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, -0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; - -char pkt10[] = { -0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, -0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, -0x00, 0x2c, 0x00, 0x04, 0x00, 0x00, 0x40, 0x06, -0xf8, 0xa3, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, -0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, -0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, -0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, -0x05, 0x92 }; - -char pkt11[] = { -0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, -0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, -0x00, 0x28, 0x09, 0xa6, 0x40, 0x00, 0x80, 0x06, -0x6f, 0x05, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, -0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, -0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, -0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; - -char pkt12[] = { -0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, -0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, -0x00, 0x28, 0x09, 0xa7, 0x40, 0x00, 0x80, 0x06, -0x6f, 0x04, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, -0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, -0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x14, -0x00, 0x00, 0x43, 0xf4, 0x00, 0x00 }; - - -typedef struct -{ - char *pcData; - int iDataLen; -} xPacketData; - -xPacketData xAllPackets[] = -{ - { pkt1, sizeof( pkt1 ) }, -// { pkt2, sizeof( pkt2 ) }, - { pkt3, sizeof( pkt3 ) }, - { pkt4, sizeof( pkt4 ) }, -// { pkt5, sizeof( pkt5 ) }, - { pkt6, sizeof( pkt6 ) }, - { pkt7, sizeof( pkt7 ) }, - { pkt8, sizeof( pkt8 ) }, - { pkt9, sizeof( pkt9 ) }, - { pkt10, sizeof( pkt10 ) }, -// { pkt11, sizeof( pkt11 ) }, -// { pkt12, sizeof( pkt12 ) }, -// { pkt13, sizeof( pkt13 ) }, -// { pkt14, sizeof( pkt14 ) }, -// { pkt15, sizeof( pkt15 ) }, -// { pkt16, sizeof( pkt16 ) }, -}; diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/Win32-Extensions.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/Win32-Extensions.h deleted file mode 100644 index d3b063b0f..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/Win32-Extensions.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 1999 - 2005 NetGroup, Politecnico di Torino (Italy) - * Copyright (c) 2005 - 2006 CACE Technologies, Davis (California) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Politecnico di Torino, CACE Technologies - * nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __WIN32_EXTENSIONS_H__ -#define __WIN32_EXTENSIONS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Definitions */ - -/*! - \brief A queue of raw packets that will be sent to the network with pcap_sendqueue_transmit(). -*/ -struct pcap_send_queue -{ - u_int maxlen; ///< Maximum size of the the queue, in bytes. This variable contains the size of the buffer field. - u_int len; ///< Current size of the queue, in bytes. - char *buffer; ///< Buffer containing the packets to be sent. -}; - -typedef struct pcap_send_queue pcap_send_queue; - -/*! - \brief This typedef is a support for the pcap_get_airpcap_handle() function -*/ -#if !defined(AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_) -#define AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ -typedef struct _AirpcapHandle *PAirpcapHandle; -#endif - -#define BPF_MEM_EX_IMM 0xc0 -#define BPF_MEM_EX_IND 0xe0 - -/*used for ST*/ -#define BPF_MEM_EX 0xc0 -#define BPF_TME 0x08 - -#define BPF_LOOKUP 0x90 -#define BPF_EXECUTE 0xa0 -#define BPF_INIT 0xb0 -#define BPF_VALIDATE 0xc0 -#define BPF_SET_ACTIVE 0xd0 -#define BPF_RESET 0xe0 -#define BPF_SET_MEMORY 0x80 -#define BPF_GET_REGISTER_VALUE 0x70 -#define BPF_SET_REGISTER_VALUE 0x60 -#define BPF_SET_WORKING 0x50 -#define BPF_SET_ACTIVE_READ 0x40 -#define BPF_SET_AUTODELETION 0x30 -#define BPF_SEPARATION 0xff - -/* Prototypes */ -pcap_send_queue* pcap_sendqueue_alloc(u_int memsize); - -void pcap_sendqueue_destroy(pcap_send_queue* queue); - -int pcap_sendqueue_queue(pcap_send_queue* queue, const struct pcap_pkthdr *pkt_header, const u_char *pkt_data); - -u_int pcap_sendqueue_transmit(pcap_t *p, pcap_send_queue* queue, int sync); - -HANDLE pcap_getevent(pcap_t *p); - -struct pcap_stat *pcap_stats_ex(pcap_t *p, int *pcap_stat_size); - -int pcap_setuserbuffer(pcap_t *p, int size); - -int pcap_live_dump(pcap_t *p, char *filename, int maxsize, int maxpacks); - -int pcap_live_dump_ended(pcap_t *p, int sync); - -int pcap_offline_filter(struct bpf_program *prog, const struct pcap_pkthdr *header, const u_char *pkt_data); - -int pcap_start_oem(char* err_str, int flags); - -PAirpcapHandle pcap_get_airpcap_handle(pcap_t *p); - -#ifdef __cplusplus -} -#endif - -#endif //__WIN32_EXTENSIONS_H__ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/arch.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/arch.c deleted file mode 100644 index f038826a6..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/arch.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* WinPCap includes. */ -#include "pcap.h" -#include "remote-ext.h" - -/* uIP includes. */ -#include "net/uip.h" -#include "net/uip_arp.h" -#include "net/clock-arch.h" - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* - * Query the computer the simulation is being executed on to find the network - * interfaces it has installed. - */ -static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ); - -/* - * Open the network interface. The number of the interface to be opened is set - * by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. - */ -static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ); - -/* - * Configure the capture filter to allow blocking reads, and to filter out - * packets that are not of interest to this demo. - */ -static void prvConfigureCaptureBehaviour( void ); - -pcap_t *pxOpenedInterfaceHandle = NULL; -LARGE_INTEGER freq, sys_start_time; - -#define archNUM_BUFFERS 5 -#define archNUM_BUFFER_POINTERS ( archNUM_BUFFERS - 1 ) - -static void prvInterruptSimulator( void *pvParameters ); - -static unsigned char ucEthernetBuffer[ archNUM_BUFFERS ][ UIP_CONF_BUFFER_SIZE ]; -static unsigned char *pucEthernetBufferPointers[ archNUM_BUFFER_POINTERS ]; - -static long lLengthOfDataInBuffer[ archNUM_BUFFER_POINTERS ] = { 0 }; -static unsigned char ucNextBufferToFill = 0U, ucNextBufferToProcess = 0U; - -unsigned char *uip_buf = NULL; -char cErrorBuffer[PCAP_ERRBUF_SIZE]; - -void vNetifTx( void ) -{ - pcap_sendpacket( pxOpenedInterfaceHandle, uip_buf, uip_len ); - pcap_sendpacket( pxOpenedInterfaceHandle, uip_buf, uip_len ); -} -/*-----------------------------------------------------------*/ - -UBaseType_t uxNetifRx( void ) -{ -UBaseType_t xDataLen; -unsigned char *pucTemp; - - /* Check there is really data available. */ - xDataLen = lLengthOfDataInBuffer[ ucNextBufferToProcess ]; - if( xDataLen != 0L ) - { - - /* The buffer pointed to by uip_buf is going to change. Remember which - buffer uip_buf is currently pointing to. */ - pucTemp = uip_buf; - - /* Point uip_buf at the next buffer that contains data. */ - uip_buf = pucEthernetBufferPointers[ ucNextBufferToProcess ]; - - /* The buffer pointed to by - pucEthernetBufferPointeres[ ucNextBufferToProcess ] is now in use by - uip_buf, but the buffer uip_buf was pointing to on entry to this - function is free. Set - pucEthernetBufferPointeres[ ucNextBufferToProcess ] to the free - buffer. */ - pucEthernetBufferPointers[ ucNextBufferToProcess ] = pucTemp; - lLengthOfDataInBuffer[ ucNextBufferToProcess ] = 0L; - - ucNextBufferToProcess++; - if( ucNextBufferToProcess >= archNUM_BUFFER_POINTERS ) - { - ucNextBufferToProcess = 0L; - } - } - - return xDataLen; -} -/*-----------------------------------------------------------*/ - -BaseType_t xNetifInit( void ) -{ -BaseType_t x; -pcap_if_t *pxAllNetworkInterfaces; - - /* Allocate a free buffer to each buffer pointer. */ - for( x = 0; x < sizeof( pucEthernetBufferPointers ) / sizeof( unsigned char * ); x++ ) - { - pucEthernetBufferPointers[ x ] = &( ucEthernetBuffer[ x ][ 0 ] ); - } - - /* Start with uip_buf pointing to a buffer that is not referenced from the - pucEthernetBufferPointers[] array. */ - uip_buf = &( ucEthernetBuffer[ archNUM_BUFFERS - 1 ][ 0 ] ); - - /* Query the computer the simulation is being executed on to find the - network interfaces it has installed. */ - pxAllNetworkInterfaces = prvPrintAvailableNetworkInterfaces(); - - /* Open the network interface. The number of the interface to be opened is - set by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. - Calling this function will set the pxOpenedInterfaceHandle variable. If, - after calling this function, pxOpenedInterfaceHandle is equal to NULL, then - the interface could not be opened. */ - if( pxAllNetworkInterfaces != NULL ) - { - prvOpenSelectedNetworkInterface( pxAllNetworkInterfaces ); - } - - - return x; -} -/*-----------------------------------------------------------*/ - -static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ) -{ -pcap_if_t * pxAllNetworkInterfaces = NULL, *xInterface; -long lInterfaceNumber = 1; - - if( pcap_findalldevs_ex( PCAP_SRC_IF_STRING, NULL, &pxAllNetworkInterfaces, cErrorBuffer ) == -1 ) - { - printf( "\r\nCould not obtain a list of network interfaces\r\n%s\r\n", cErrorBuffer ); - pxAllNetworkInterfaces = NULL; - } - - if( pxAllNetworkInterfaces != NULL ) - { - /* Print out the list of network interfaces. The first in the list - is interface '1', not interface '0'. */ - for( xInterface = pxAllNetworkInterfaces; xInterface != NULL; xInterface = xInterface->next ) - { - printf( "%d. %s", lInterfaceNumber, xInterface->name ); - - if( xInterface->description != NULL ) - { - printf( " (%s)\r\n", xInterface->description ); - } - else - { - printf( " (No description available)\r\n") ; - } - - lInterfaceNumber++; - } - } - - if( lInterfaceNumber == 1 ) - { - /* The interface number was never incremented, so the above for() loop - did not execute meaning no interfaces were found. */ - printf( " \r\nNo network interfaces were found.\r\n" ); - pxAllNetworkInterfaces = NULL; - } - - printf( "\r\nThe interface that will be opened is set by configNETWORK_INTERFACE_TO_USE which should be defined in FreeRTOSConfig.h\r\n" ); - printf( "Attempting to open interface number %d.\r\n", configNETWORK_INTERFACE_TO_USE ); - - if( ( configNETWORK_INTERFACE_TO_USE < 1L ) || ( configNETWORK_INTERFACE_TO_USE > lInterfaceNumber ) ) - { - printf("\r\nconfigNETWORK_INTERFACE_TO_USE is not in the valid range.\r\n" ); - - if( pxAllNetworkInterfaces != NULL ) - { - /* Free the device list, as no devices are going to be opened. */ - pcap_freealldevs( pxAllNetworkInterfaces ); - pxAllNetworkInterfaces = NULL; - } - } - - return pxAllNetworkInterfaces; -} -/*-----------------------------------------------------------*/ - -static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ) -{ -pcap_if_t *xInterface; -long x; - - /* Walk the list of devices until the selected device is located. */ - xInterface = pxAllNetworkInterfaces; - for( x = 0L; x < ( configNETWORK_INTERFACE_TO_USE - 1L ); x++ ) - { - xInterface = xInterface->next; - } - - /* Open the selected interface. */ - pxOpenedInterfaceHandle = pcap_open( xInterface->name, /* The name of the selected interface. */ - UIP_CONF_BUFFER_SIZE, /* The size of the packet to capture. */ - PCAP_OPENFLAG_PROMISCUOUS, /* Open in promiscious mode as the MAC and - IP address is going to be "simulated", and - not be the real MAC and IP address. This allows - trafic to the simulated IP address to be routed - to uIP, and trafic to the real IP address to be - routed to the Windows TCP/IP stack. */ - 0xfffffffL, /* The read time out. This is going to block - until data is available. */ - NULL, /* No authentication is required as this is - not a remote capture session. */ - cErrorBuffer - ); - - if ( pxOpenedInterfaceHandle == NULL ) - { - printf( "\r\n%s is not supported by WinPcap and cannot be opened\r\n", xInterface->name ); - } - else - { - /* Configure the capture filter to allow blocking reads, and to filter - out packets that are not of interest to this demo. */ - prvConfigureCaptureBehaviour(); - } - - /* The device list is no longer required. */ - pcap_freealldevs( pxAllNetworkInterfaces ); -} -/*-----------------------------------------------------------*/ - -static void prvConfigureCaptureBehaviour( void ) -{ -struct bpf_program xFilterCode; -const long lMinBytesToCopy = 10L, lBlocking = 0L; -unsigned long ulNetMask; - - /* Unblock a read as soon as anything is received. */ - pcap_setmintocopy( pxOpenedInterfaceHandle, lMinBytesToCopy ); - - /* Allow blocking. */ - pcap_setnonblock( pxOpenedInterfaceHandle, lBlocking, cErrorBuffer ); - - /* Set up a filter so only the packets of interest are passed to the uIP - stack. cErrorBuffer is used for convenience to create the string. Don't - confuse this with an error message. */ - sprintf( cErrorBuffer, "broadcast or multicast or host %d.%d.%d.%d", configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 ); - - ulNetMask = ( configNET_MASK3 << 24UL ) | ( configNET_MASK2 << 16UL ) | ( configNET_MASK1 << 8L ) | configNET_MASK0; - - if( pcap_compile(pxOpenedInterfaceHandle, &xFilterCode, cErrorBuffer, 1, ulNetMask ) < 0 ) - { - printf("\r\nThe packet filter string is invalid\r\n" ); - } - else - { - if( pcap_setfilter( pxOpenedInterfaceHandle, &xFilterCode ) < 0 ) - { - printf( "\r\nAn error occurred setting the packet filter.\r\n" ); - } - } - - /* Create a task that simulates an interrupt in a real system. This will - block waiting for packets, then send a message to the uIP task when data - is available. */ - xTaskCreate( prvInterruptSimulator, "MAC_ISR", configMINIMAL_STACK_SIZE, NULL, ( configuIP_TASK_PRIORITY - 1 ), NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvInterruptSimulator( void *pvParameters ) -{ -static struct pcap_pkthdr *pxHeader; -const unsigned char *pucPacketData; -extern xQueueHandle xEMACEventQueue; -const unsigned long ulRxEvent = uipETHERNET_RX_EVENT; -long lResult; - - /* Just to kill the compiler warning. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Get the next packet. */ - lResult = pcap_next_ex( pxOpenedInterfaceHandle, &pxHeader, &pucPacketData ); - if( lResult ) - { - /* Is the next buffer into which data should be placed free? */ - if( lLengthOfDataInBuffer[ ucNextBufferToFill ] == 0L ) - { - /* Copy the data from the captured packet into the buffer. */ - memcpy( pucEthernetBufferPointers[ ucNextBufferToFill ], pucPacketData, pxHeader->len ); - - /* Note the amount of data that was copied. */ - lLengthOfDataInBuffer[ ucNextBufferToFill ] = pxHeader->len; - - /* Move onto the next buffer, wrapping around if necessary. */ - ucNextBufferToFill++; - if( ucNextBufferToFill >= archNUM_BUFFER_POINTERS ) - { - ucNextBufferToFill = 0U; - } - - /* Data was received and stored. Send a message to the uIP task - to let it know. */ - xQueueSendToBack( xEMACEventQueue, &ulRxEvent, portMAX_DELAY ); - } - } - } -} - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/bittypes.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/bittypes.h deleted file mode 100644 index f55fcecfd..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/bittypes.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) 1999 WIDE Project. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the project nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#ifndef _BITTYPES_H -#define _BITTYPES_H - -#ifndef HAVE_U_INT8_T - -#if SIZEOF_CHAR == 1 -typedef unsigned char u_int8_t; -typedef signed char _int8_t; -#elif SIZEOF_INT == 1 -typedef unsigned int u_int8_t; -typedef signed int int8_t; -#else /* XXX */ -#error "there's no appropriate type for u_int8_t" -#endif -#define HAVE_U_INT8_T 1 -#define HAVE_INT8_T 1 - -#endif /* HAVE_U_INT8_T */ - -#ifndef HAVE_U_INT16_T - -#if SIZEOF_SHORT == 2 -typedef unsigned short u_int16_t; -typedef signed short _int16_t; -#elif SIZEOF_INT == 2 -typedef unsigned int u_int16_t; -typedef signed int int16_t; -#elif SIZEOF_CHAR == 2 -typedef unsigned char u_int16_t; -typedef signed char int16_t; -#else /* XXX */ -#error "there's no appropriate type for u_int16_t" -#endif -#define HAVE_U_INT16_T 1 -#define HAVE_INT16_T 1 - -#endif /* HAVE_U_INT16_T */ - -#ifndef HAVE_U_INT32_T - -#if SIZEOF_INT == 4 -typedef unsigned int u_int32_t; -typedef signed int _int32_t; -#elif SIZEOF_LONG == 4 -typedef unsigned long u_int32_t; -typedef signed long int32_t; -#elif SIZEOF_SHORT == 4 -typedef unsigned short u_int32_t; -typedef signed short int32_t; -#else /* XXX */ -#error "there's no appropriate type for u_int32_t" -#endif -#define HAVE_U_INT32_T 1 -#define HAVE_INT32_T 1 - -#endif /* HAVE_U_INT32_T */ - -#ifndef HAVE_U_INT64_T -#if SIZEOF_LONG_LONG == 8 -typedef unsigned long long u_int64_t; -typedef long long int64_t; -#elif defined(_MSC_EXTENSIONS) -typedef unsigned _int64 u_int64_t; -typedef _int64 int64_t; -#elif SIZEOF_INT == 8 -typedef unsigned int u_int64_t; -#elif SIZEOF_LONG == 8 -typedef unsigned long u_int64_t; -#elif SIZEOF_SHORT == 8 -typedef unsigned short u_int64_t; -#else /* XXX */ -#error "there's no appropriate type for u_int64_t" -#endif - -#endif /* HAVE_U_INT64_T */ - -#ifndef PRId64 -#ifdef _MSC_EXTENSIONS -#define PRId64 "I64d" -#else /* _MSC_EXTENSIONS */ -#define PRId64 "lld" -#endif /* _MSC_EXTENSIONS */ -#endif /* PRId64 */ - -#ifndef PRIo64 -#ifdef _MSC_EXTENSIONS -#define PRIo64 "I64o" -#else /* _MSC_EXTENSIONS */ -#define PRIo64 "llo" -#endif /* _MSC_EXTENSIONS */ -#endif /* PRIo64 */ - -#ifndef PRIx64 -#ifdef _MSC_EXTENSIONS -#define PRIx64 "I64x" -#else /* _MSC_EXTENSIONS */ -#define PRIx64 "llx" -#endif /* _MSC_EXTENSIONS */ -#endif /* PRIx64 */ - -#ifndef PRIu64 -#ifdef _MSC_EXTENSIONS -#define PRIu64 "I64u" -#else /* _MSC_EXTENSIONS */ -#define PRIu64 "llu" -#endif /* _MSC_EXTENSIONS */ -#endif /* PRIu64 */ - -#endif /* _BITTYPES_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/ip6_misc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/ip6_misc.h deleted file mode 100644 index 562fa6184..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/ip6_misc.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 1993, 1994, 1997 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that: (1) source code distributions - * retain the above copyright notice and this paragraph in its entirety, (2) - * distributions including binary code include the above copyright notice and - * this paragraph in its entirety in the documentation or other materials - * provided with the distribution, and (3) all advertising materials mentioning - * features or use of this software display the following acknowledgement: - * ``This product includes software developed by the University of California, - * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of - * the University nor the names of its contributors may be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * @(#) $Header: /tcpdump/master/libpcap/Win32/Include/ip6_misc.h,v 1.5 2006-01-22 18:02:18 gianluca Exp $ (LBL) - */ - -/* - * This file contains a collage of declarations for IPv6 from FreeBSD not present in Windows - */ - -#include - -#include - -#ifndef __MINGW32__ -#define IN_MULTICAST(a) IN_CLASSD(a) -#endif - -#define IN_EXPERIMENTAL(a) ((((u_int32_t) (a)) & 0xf0000000) == 0xf0000000) - -#define IN_LOOPBACKNET 127 - -#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) -/* IPv6 address */ -struct in6_addr - { - union - { - u_int8_t u6_addr8[16]; - u_int16_t u6_addr16[8]; - u_int32_t u6_addr32[4]; - } in6_u; -#define s6_addr in6_u.u6_addr8 -#define s6_addr16 in6_u.u6_addr16 -#define s6_addr32 in6_u.u6_addr32 -#define s6_addr64 in6_u.u6_addr64 - }; - -#define IN6ADDR_ANY_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } -#define IN6ADDR_LOOPBACK_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1 } -#endif /* __MINGW32__ */ - - -#if (defined _MSC_VER) || (defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)) -typedef unsigned short sa_family_t; -#endif - - -#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) - -#define __SOCKADDR_COMMON(sa_prefix) \ - sa_family_t sa_prefix##family - -/* Ditto, for IPv6. */ -struct sockaddr_in6 - { - __SOCKADDR_COMMON (sin6_); - u_int16_t sin6_port; /* Transport layer port # */ - u_int32_t sin6_flowinfo; /* IPv6 flow information */ - struct in6_addr sin6_addr; /* IPv6 address */ - }; - -#define IN6_IS_ADDR_V4MAPPED(a) \ - ((((u_int32_t *) (a))[0] == 0) && (((u_int32_t *) (a))[1] == 0) && \ - (((u_int32_t *) (a))[2] == htonl (0xffff))) - -#define IN6_IS_ADDR_MULTICAST(a) (((u_int8_t *) (a))[0] == 0xff) - -#define IN6_IS_ADDR_LINKLOCAL(a) \ - ((((u_int32_t *) (a))[0] & htonl (0xffc00000)) == htonl (0xfe800000)) - -#define IN6_IS_ADDR_LOOPBACK(a) \ - (((u_int32_t *) (a))[0] == 0 && ((u_int32_t *) (a))[1] == 0 && \ - ((u_int32_t *) (a))[2] == 0 && ((u_int32_t *) (a))[3] == htonl (1)) -#endif /* __MINGW32__ */ - -#define ip6_vfc ip6_ctlun.ip6_un2_vfc -#define ip6_flow ip6_ctlun.ip6_un1.ip6_un1_flow -#define ip6_plen ip6_ctlun.ip6_un1.ip6_un1_plen -#define ip6_nxt ip6_ctlun.ip6_un1.ip6_un1_nxt -#define ip6_hlim ip6_ctlun.ip6_un1.ip6_un1_hlim -#define ip6_hops ip6_ctlun.ip6_un1.ip6_un1_hlim - -#define nd_rd_type nd_rd_hdr.icmp6_type -#define nd_rd_code nd_rd_hdr.icmp6_code -#define nd_rd_cksum nd_rd_hdr.icmp6_cksum -#define nd_rd_reserved nd_rd_hdr.icmp6_data32[0] - -/* - * IPV6 extension headers - */ -#define IPPROTO_HOPOPTS 0 /* IPv6 hop-by-hop options */ -#define IPPROTO_IPV6 41 /* IPv6 header. */ -#define IPPROTO_ROUTING 43 /* IPv6 routing header */ -#define IPPROTO_FRAGMENT 44 /* IPv6 fragmentation header */ -#define IPPROTO_ESP 50 /* encapsulating security payload */ -#define IPPROTO_AH 51 /* authentication header */ -#define IPPROTO_ICMPV6 58 /* ICMPv6 */ -#define IPPROTO_NONE 59 /* IPv6 no next header */ -#define IPPROTO_DSTOPTS 60 /* IPv6 destination options */ -#define IPPROTO_PIM 103 /* Protocol Independent Multicast. */ - -#define IPV6_RTHDR_TYPE_0 0 - -/* Option types and related macros */ -#define IP6OPT_PAD1 0x00 /* 00 0 00000 */ -#define IP6OPT_PADN 0x01 /* 00 0 00001 */ -#define IP6OPT_JUMBO 0xC2 /* 11 0 00010 = 194 */ -#define IP6OPT_JUMBO_LEN 6 -#define IP6OPT_ROUTER_ALERT 0x05 /* 00 0 00101 */ - -#define IP6OPT_RTALERT_LEN 4 -#define IP6OPT_RTALERT_MLD 0 /* Datagram contains an MLD message */ -#define IP6OPT_RTALERT_RSVP 1 /* Datagram contains an RSVP message */ -#define IP6OPT_RTALERT_ACTNET 2 /* contains an Active Networks msg */ -#define IP6OPT_MINLEN 2 - -#define IP6OPT_BINDING_UPDATE 0xc6 /* 11 0 00110 */ -#define IP6OPT_BINDING_ACK 0x07 /* 00 0 00111 */ -#define IP6OPT_BINDING_REQ 0x08 /* 00 0 01000 */ -#define IP6OPT_HOME_ADDRESS 0xc9 /* 11 0 01001 */ -#define IP6OPT_EID 0x8a /* 10 0 01010 */ - -#define IP6OPT_TYPE(o) ((o) & 0xC0) -#define IP6OPT_TYPE_SKIP 0x00 -#define IP6OPT_TYPE_DISCARD 0x40 -#define IP6OPT_TYPE_FORCEICMP 0x80 -#define IP6OPT_TYPE_ICMP 0xC0 - -#define IP6OPT_MUTABLE 0x20 - - -#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) -#ifndef EAI_ADDRFAMILY -struct addrinfo { - int ai_flags; /* AI_PASSIVE, AI_CANONNAME */ - int ai_family; /* PF_xxx */ - int ai_socktype; /* SOCK_xxx */ - int ai_protocol; /* 0 or IPPROTO_xxx for IPv4 and IPv6 */ - size_t ai_addrlen; /* length of ai_addr */ - char *ai_canonname; /* canonical name for hostname */ - struct sockaddr *ai_addr; /* binary address */ - struct addrinfo *ai_next; /* next structure in linked list */ -}; -#endif -#endif /* __MINGW32__ */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/netif.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/netif.h deleted file mode 100644 index 95ebacd33..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/netif.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef NET_IF_H -#define NET_IF_H - -/* - * Send uip_len bytes from uip_buf to the network interface selected by the - * configNETWORK_INTERFACE_TO_USE constant (defined in FreeRTOSConfig.h). - */ -void vNetifTx( void ); - -/* - * Receive bytes from the network interface selected by the - * configNETWORK_INTERFACE_TO_USE constant (defined in FreeRTOSConfig.h). The - * bytes are placed in uip_buf. The number of bytes copied into uip_buf is - * returned. - */ -UBaseType_t uxNetifRx( void ); - -/* - * Prepare a packet capture session. This will print out all the network - * interfaces available, and the one actually used is set by the - * configNETWORK_INTERFACE_TO_USE constant that is defined in - * FreeRTOSConfig.h. */ -BaseType_t xNetifInit( void ); - -#endif /* NET_IF_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-bpf.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-bpf.h deleted file mode 100644 index 5fe129dbb..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-bpf.h +++ /dev/null @@ -1,47 +0,0 @@ -/*- - * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from the Stanford/CMU enet packet filter, - * (net/enet.c) distributed as part of 4.3BSD, and code contributed - * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence - * Berkeley Laboratory. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#) $Header: /tcpdump/master/libpcap/pcap-bpf.h,v 1.50 2007/04/01 21:43:55 guy Exp $ (LBL) - */ - -/* - * For backwards compatibility. - * - * Note to OS vendors: do NOT get rid of this file! Some applications - * might expect to be able to include . - */ -#include diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-namedb.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-namedb.h deleted file mode 100644 index 80a2f0040..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-namedb.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 1994, 1996 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the Computer Systems - * Engineering Group at Lawrence Berkeley Laboratory. - * 4. Neither the name of the University nor of the Laboratory may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#) $Header: /tcpdump/master/libpcap/pcap-namedb.h,v 1.13 2006/10/04 18:13:32 guy Exp $ (LBL) - */ - -/* - * For backwards compatibility. - * - * Note to OS vendors: do NOT get rid of this file! Some applications - * might expect to be able to include . - */ -#include diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-stdinc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-stdinc.h deleted file mode 100644 index ded432579..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap-stdinc.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2002 - 2005 NetGroup, Politecnico di Torino (Italy) - * Copyright (c) 2005 - 2009 CACE Technologies, Inc. Davis (California) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Politecnico di Torino nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * @(#) $Header: /tcpdump/master/libpcap/pcap-stdinc.h,v 1.10.2.1 2008-10-06 15:38:39 gianluca Exp $ (LBL) - */ - -#define SIZEOF_CHAR 1 -#define SIZEOF_SHORT 2 -#define SIZEOF_INT 4 -#ifndef _MSC_EXTENSIONS -#define SIZEOF_LONG_LONG 8 -#endif - -/* - * Avoids a compiler warning in case this was already defined - * (someone defined _WINSOCKAPI_ when including 'windows.h', in order - * to prevent it from including 'winsock.h') - */ -#ifdef _WINSOCKAPI_ -#undef _WINSOCKAPI_ -#endif - -#include - -#include "bittypes.h" -#include -#include - -#ifndef __MINGW32__ -#include "IP6_misc.h" -#endif - -#define caddr_t char* - -#if _MSC_VER < 1500 -#define snprintf _snprintf -#define vsnprintf _vsnprintf -#define strdup _strdup -#endif - -#define inline __inline - -#ifdef __MINGW32__ -#include -#else /*__MINGW32__*/ -/* MSVC compiler */ -#ifndef _UINTPTR_T_DEFINED -#ifdef _WIN64 -typedef unsigned __int64 uintptr_t; -#else -typedef _W64 unsigned int uintptr_t; -#endif -#define _UINTPTR_T_DEFINED -#endif - -#ifndef _INTPTR_T_DEFINED -#ifdef _WIN64 -typedef __int64 intptr_t; -#else -typedef _W64 int intptr_t; -#endif -#define _INTPTR_T_DEFINED -#endif - -#endif /*__MINGW32__*/ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap.h deleted file mode 100644 index ad8fc40ac..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap.h +++ /dev/null @@ -1,407 +0,0 @@ -/* -*- Mode: c; tab-width: 8; indent-tabs-mode: 1; c-basic-offset: 8; -*- */ -/* - * Copyright (c) 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the Computer Systems - * Engineering Group at Lawrence Berkeley Laboratory. - * 4. Neither the name of the University nor of the Laboratory may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#) $Header: /tcpdump/master/libpcap/pcap/pcap.h,v 1.4.2.11 2008-10-06 15:38:39 gianluca Exp $ (LBL) - */ - -#ifndef lib_pcap_pcap_h -#define lib_pcap_pcap_h - -#if defined(WIN32) - #include -#elif defined(MSDOS) - #include - #include /* u_int, u_char etc. */ -#else /* UN*X */ - #include - #include -#endif /* WIN32/MSDOS/UN*X */ - -#ifndef PCAP_DONT_INCLUDE_PCAP_BPF_H -#include -#endif - -#include - -#ifdef HAVE_REMOTE - // We have to define the SOCKET here, although it has been defined in sockutils.h - // This is to avoid the distribution of the 'sockutils.h' file around - // (for example in the WinPcap developer's pack) - #ifndef SOCKET - #ifdef WIN32 - #define SOCKET unsigned int - #else - #define SOCKET int - #endif - #endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#define PCAP_VERSION_MAJOR 2 -#define PCAP_VERSION_MINOR 4 - -#define PCAP_ERRBUF_SIZE 256 - -/* - * Compatibility for systems that have a bpf.h that - * predates the bpf typedefs for 64-bit support. - */ -#if BPF_RELEASE - 0 < 199406 -typedef int bpf_int32; -typedef u_int bpf_u_int32; -#endif - -typedef struct pcap pcap_t; -typedef struct pcap_dumper pcap_dumper_t; -typedef struct pcap_if pcap_if_t; -typedef struct pcap_addr pcap_addr_t; - -/* - * The first record in the file contains saved values for some - * of the flags used in the printout phases of tcpdump. - * Many fields here are 32 bit ints so compilers won't insert unwanted - * padding; these files need to be interchangeable across architectures. - * - * Do not change the layout of this structure, in any way (this includes - * changes that only affect the length of fields in this structure). - * - * Also, do not change the interpretation of any of the members of this - * structure, in any way (this includes using values other than - * LINKTYPE_ values, as defined in "savefile.c", in the "linktype" - * field). - * - * Instead: - * - * introduce a new structure for the new format, if the layout - * of the structure changed; - * - * send mail to "tcpdump-workers@lists.tcpdump.org", requesting - * a new magic number for your new capture file format, and, when - * you get the new magic number, put it in "savefile.c"; - * - * use that magic number for save files with the changed file - * header; - * - * make the code in "savefile.c" capable of reading files with - * the old file header as well as files with the new file header - * (using the magic number to determine the header format). - * - * Then supply the changes as a patch at - * - * http://sourceforge.net/projects/libpcap/ - * - * so that future versions of libpcap and programs that use it (such as - * tcpdump) will be able to read your new capture file format. - */ -struct pcap_file_header { - bpf_u_int32 magic; - u_short version_major; - u_short version_minor; - bpf_int32 thiszone; /* gmt to local correction */ - bpf_u_int32 sigfigs; /* accuracy of timestamps */ - bpf_u_int32 snaplen; /* max length saved portion of each pkt */ - bpf_u_int32 linktype; /* data link type (LINKTYPE_*) */ -}; - -/* - * Macros for the value returned by pcap_datalink_ext(). - * - * If LT_FCS_LENGTH_PRESENT(x) is true, the LT_FCS_LENGTH(x) macro - * gives the FCS length of packets in the capture. - */ -#define LT_FCS_LENGTH_PRESENT(x) ((x) & 0x04000000) -#define LT_FCS_LENGTH(x) (((x) & 0xF0000000) >> 28) -#define LT_FCS_DATALINK_EXT(x) ((((x) & 0xF) << 28) | 0x04000000) - -typedef enum { - PCAP_D_INOUT = 0, - PCAP_D_IN, - PCAP_D_OUT -} pcap_direction_t; - -/* - * Generic per-packet information, as supplied by libpcap. - * - * The time stamp can and should be a "struct timeval", regardless of - * whether your system supports 32-bit tv_sec in "struct timeval", - * 64-bit tv_sec in "struct timeval", or both if it supports both 32-bit - * and 64-bit applications. The on-disk format of savefiles uses 32-bit - * tv_sec (and tv_usec); this structure is irrelevant to that. 32-bit - * and 64-bit versions of libpcap, even if they're on the same platform, - * should supply the appropriate version of "struct timeval", even if - * that's not what the underlying packet capture mechanism supplies. - */ -struct pcap_pkthdr { - struct timeval ts; /* time stamp */ - bpf_u_int32 caplen; /* length of portion present */ - bpf_u_int32 len; /* length this packet (off wire) */ -}; - -/* - * As returned by the pcap_stats() - */ -struct pcap_stat { - u_int ps_recv; /* number of packets received */ - u_int ps_drop; /* number of packets dropped */ - u_int ps_ifdrop; /* drops by interface XXX not yet supported */ -#ifdef HAVE_REMOTE - u_int ps_capt; /* number of packets that are received by the application; please get rid off the Win32 ifdef */ - u_int ps_sent; /* number of packets sent by the server on the network */ - u_int ps_netdrop; /* number of packets lost on the network */ -#endif /* HAVE_REMOTE */ -}; - -#ifdef MSDOS -/* - * As returned by the pcap_stats_ex() - */ -struct pcap_stat_ex { - u_long rx_packets; /* total packets received */ - u_long tx_packets; /* total packets transmitted */ - u_long rx_bytes; /* total bytes received */ - u_long tx_bytes; /* total bytes transmitted */ - u_long rx_errors; /* bad packets received */ - u_long tx_errors; /* packet transmit problems */ - u_long rx_dropped; /* no space in Rx buffers */ - u_long tx_dropped; /* no space available for Tx */ - u_long multicast; /* multicast packets received */ - u_long collisions; - - /* detailed rx_errors: */ - u_long rx_length_errors; - u_long rx_over_errors; /* receiver ring buff overflow */ - u_long rx_crc_errors; /* recv'd pkt with crc error */ - u_long rx_frame_errors; /* recv'd frame alignment error */ - u_long rx_fifo_errors; /* recv'r fifo overrun */ - u_long rx_missed_errors; /* recv'r missed packet */ - - /* detailed tx_errors */ - u_long tx_aborted_errors; - u_long tx_carrier_errors; - u_long tx_fifo_errors; - u_long tx_heartbeat_errors; - u_long tx_window_errors; - }; -#endif - -/* - * Item in a list of interfaces. - */ -struct pcap_if { - struct pcap_if *next; - char *name; /* name to hand to "pcap_open_live()" */ - char *description; /* textual description of interface, or NULL */ - struct pcap_addr *addresses; - bpf_u_int32 flags; /* PCAP_IF_ interface flags */ -}; - -#define PCAP_IF_LOOPBACK 0x00000001 /* interface is loopback */ - -/* - * Representation of an interface address. - */ -struct pcap_addr { - struct pcap_addr *next; - struct sockaddr *addr; /* address */ - struct sockaddr *netmask; /* netmask for that address */ - struct sockaddr *broadaddr; /* broadcast address for that address */ - struct sockaddr *dstaddr; /* P2P destination address for that address */ -}; - -typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *, - const u_char *); - -/* - * Error codes for the pcap API. - * These will all be negative, so you can check for the success or - * failure of a call that returns these codes by checking for a - * negative value. - */ -#define PCAP_ERROR -1 /* generic error code */ -#define PCAP_ERROR_BREAK -2 /* loop terminated by pcap_breakloop */ -#define PCAP_ERROR_NOT_ACTIVATED -3 /* the capture needs to be activated */ -#define PCAP_ERROR_ACTIVATED -4 /* the operation can't be performed on already activated captures */ -#define PCAP_ERROR_NO_SUCH_DEVICE -5 /* no such device exists */ -#define PCAP_ERROR_RFMON_NOTSUP -6 /* this device doesn't support rfmon (monitor) mode */ -#define PCAP_ERROR_NOT_RFMON -7 /* operation supported only in monitor mode */ -#define PCAP_ERROR_PERM_DENIED -8 /* no permission to open the device */ -#define PCAP_ERROR_IFACE_NOT_UP -9 /* interface isn't up */ - -/* - * Warning codes for the pcap API. - * These will all be positive and non-zero, so they won't look like - * errors. - */ -#define PCAP_WARNING 1 /* generic warning code */ -#define PCAP_WARNING_PROMISC_NOTSUP 2 /* this device doesn't support promiscuous mode */ - -char *pcap_lookupdev(char *); -int pcap_lookupnet(const char *, bpf_u_int32 *, bpf_u_int32 *, char *); - -pcap_t *pcap_create(const char *, char *); -int pcap_set_snaplen(pcap_t *, int); -int pcap_set_promisc(pcap_t *, int); -int pcap_can_set_rfmon(pcap_t *); -int pcap_set_rfmon(pcap_t *, int); -int pcap_set_timeout(pcap_t *, int); -int pcap_set_buffer_size(pcap_t *, int); -int pcap_activate(pcap_t *); - -pcap_t *pcap_open_live(const char *, int, int, int, char *); -pcap_t *pcap_open_dead(int, int); -pcap_t *pcap_open_offline(const char *, char *); -#if defined(WIN32) -pcap_t *pcap_hopen_offline(intptr_t, char *); -#if !defined(LIBPCAP_EXPORTS) -#define pcap_fopen_offline(f,b) \ - pcap_hopen_offline(_get_osfhandle(_fileno(f)), b) -#else /*LIBPCAP_EXPORTS*/ -static pcap_t *pcap_fopen_offline(FILE *, char *); -#endif -#else /*WIN32*/ -pcap_t *pcap_fopen_offline(FILE *, char *); -#endif /*WIN32*/ - -void pcap_close(pcap_t *); -int pcap_loop(pcap_t *, int, pcap_handler, u_char *); -int pcap_dispatch(pcap_t *, int, pcap_handler, u_char *); -const u_char* - pcap_next(pcap_t *, struct pcap_pkthdr *); -int pcap_next_ex(pcap_t *, struct pcap_pkthdr **, const u_char **); -void pcap_breakloop(pcap_t *); -int pcap_stats(pcap_t *, struct pcap_stat *); -int pcap_setfilter(pcap_t *, struct bpf_program *); -int pcap_setdirection(pcap_t *, pcap_direction_t); -int pcap_getnonblock(pcap_t *, char *); -int pcap_setnonblock(pcap_t *, int, char *); -int pcap_inject(pcap_t *, const void *, size_t); -int pcap_sendpacket(pcap_t *, const u_char *, int); -const char *pcap_statustostr(int); -const char *pcap_strerror(int); -char *pcap_geterr(pcap_t *); -void pcap_perror(pcap_t *, char *); -int pcap_compile(pcap_t *, struct bpf_program *, const char *, int, - bpf_u_int32); -int pcap_compile_nopcap(int, int, struct bpf_program *, - const char *, int, bpf_u_int32); -void pcap_freecode(struct bpf_program *); -int pcap_offline_filter(struct bpf_program *, const struct pcap_pkthdr *, - const u_char *); -int pcap_datalink(pcap_t *); -int pcap_datalink_ext(pcap_t *); -int pcap_list_datalinks(pcap_t *, int **); -int pcap_set_datalink(pcap_t *, int); -void pcap_free_datalinks(int *); -int pcap_datalink_name_to_val(const char *); -const char *pcap_datalink_val_to_name(int); -const char *pcap_datalink_val_to_description(int); -int pcap_snapshot(pcap_t *); -int pcap_is_swapped(pcap_t *); -int pcap_major_version(pcap_t *); -int pcap_minor_version(pcap_t *); - -/* XXX */ -FILE *pcap_file(pcap_t *); -int pcap_fileno(pcap_t *); - -pcap_dumper_t *pcap_dump_open(pcap_t *, const char *); -pcap_dumper_t *pcap_dump_fopen(pcap_t *, FILE *fp); -FILE *pcap_dump_file(pcap_dumper_t *); -long pcap_dump_ftell(pcap_dumper_t *); -int pcap_dump_flush(pcap_dumper_t *); -void pcap_dump_close(pcap_dumper_t *); -void pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *); - -int pcap_findalldevs(pcap_if_t **, char *); -void pcap_freealldevs(pcap_if_t *); - -const char *pcap_lib_version(void); - -/* XXX this guy lives in the bpf tree */ -u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int); -int bpf_validate(const struct bpf_insn *f, int len); -char *bpf_image(const struct bpf_insn *, int); -void bpf_dump(const struct bpf_program *, int); - -#if defined(WIN32) - -/* - * Win32 definitions - */ - -int pcap_setbuff(pcap_t *p, int dim); -int pcap_setmode(pcap_t *p, int mode); -int pcap_setmintocopy(pcap_t *p, int size); - -#ifdef WPCAP -/* Include file with the wpcap-specific extensions */ -#include -#endif /* WPCAP */ - -#define MODE_CAPT 0 -#define MODE_STAT 1 -#define MODE_MON 2 - -#elif defined(MSDOS) - -/* - * MS-DOS definitions - */ - -int pcap_stats_ex (pcap_t *, struct pcap_stat_ex *); -void pcap_set_wait (pcap_t *p, void (*yield)(void), int wait); -u_long pcap_mac_packets (void); - -#else /* UN*X */ - -/* - * UN*X definitions - */ - -int pcap_get_selectable_fd(pcap_t *); - -#endif /* WIN32/MSDOS/UN*X */ - -#ifdef HAVE_REMOTE -/* Includes most of the public stuff that is needed for the remote capture */ -#include -#endif /* HAVE_REMOTE */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/bluetooth.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/bluetooth.h deleted file mode 100644 index 7bf65df03..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/bluetooth.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2006 Paolo Abeni (Italy) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * bluetooth data struct - * By Paolo Abeni - * - * @(#) $Header: /tcpdump/master/libpcap/pcap/bluetooth.h,v 1.1 2007/09/22 02:10:17 guy Exp $ - */ - -#ifndef _PCAP_BLUETOOTH_STRUCTS_H__ -#define _PCAP_BLUETOOTH_STRUCTS_H__ - -/* - * Header prepended libpcap to each bluetooth h:4 frame. - * fields are in network byte order - */ -typedef struct _pcap_bluetooth_h4_header { - u_int32_t direction; /* if first bit is set direction is incoming */ -} pcap_bluetooth_h4_header; - - -#endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/bpf.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/bpf.h deleted file mode 100644 index 9f4ca33e3..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/bpf.h +++ /dev/null @@ -1,934 +0,0 @@ -/*- - * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from the Stanford/CMU enet packet filter, - * (net/enet.c) distributed as part of 4.3BSD, and code contributed - * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence - * Berkeley Laboratory. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)bpf.h 7.1 (Berkeley) 5/7/91 - * - * @(#) $Header: /tcpdump/master/libpcap/pcap/bpf.h,v 1.19.2.8 2008-09-22 20:16:01 guy Exp $ (LBL) - */ - -/* - * This is libpcap's cut-down version of bpf.h; it includes only - * the stuff needed for the code generator and the userland BPF - * interpreter, and the libpcap APIs for setting filters, etc.. - * - * "pcap-bpf.c" will include the native OS version, as it deals with - * the OS's BPF implementation. - * - * XXX - should this all just be moved to "pcap.h"? - */ - -#ifndef BPF_MAJOR_VERSION - -#ifdef __cplusplus -extern "C" { -#endif - -/* BSD style release date */ -#define BPF_RELEASE 199606 - -#ifdef MSDOS /* must be 32-bit */ -typedef long bpf_int32; -typedef unsigned long bpf_u_int32; -#else -typedef int bpf_int32; -typedef u_int bpf_u_int32; -#endif - -/* - * Alignment macros. BPF_WORDALIGN rounds up to the next - * even multiple of BPF_ALIGNMENT. - */ -#ifndef __NetBSD__ -#define BPF_ALIGNMENT sizeof(bpf_int32) -#else -#define BPF_ALIGNMENT sizeof(long) -#endif -#define BPF_WORDALIGN(x) (((x)+(BPF_ALIGNMENT-1))&~(BPF_ALIGNMENT-1)) - -#define BPF_MAXBUFSIZE 0x8000 -#define BPF_MINBUFSIZE 32 - -/* - * Structure for "pcap_compile()", "pcap_setfilter()", etc.. - */ -struct bpf_program { - u_int bf_len; - struct bpf_insn *bf_insns; -}; - -/* - * Struct return by BIOCVERSION. This represents the version number of - * the filter language described by the instruction encodings below. - * bpf understands a program iff kernel_major == filter_major && - * kernel_minor >= filter_minor, that is, if the value returned by the - * running kernel has the same major number and a minor number equal - * equal to or less than the filter being downloaded. Otherwise, the - * results are undefined, meaning an error may be returned or packets - * may be accepted haphazardly. - * It has nothing to do with the source code version. - */ -struct bpf_version { - u_short bv_major; - u_short bv_minor; -}; -/* Current version number of filter architecture. */ -#define BPF_MAJOR_VERSION 1 -#define BPF_MINOR_VERSION 1 - -/* - * Data-link level type codes. - * - * Do *NOT* add new values to this list without asking - * "tcpdump-workers@lists.tcpdump.org" for a value. Otherwise, you run - * the risk of using a value that's already being used for some other - * purpose, and of having tools that read libpcap-format captures not - * being able to handle captures with your new DLT_ value, with no hope - * that they will ever be changed to do so (as that would destroy their - * ability to read captures using that value for that other purpose). - */ - -/* - * These are the types that are the same on all platforms, and that - * have been defined by for ages. - */ -#define DLT_NULL 0 /* BSD loopback encapsulation */ -#define DLT_EN10MB 1 /* Ethernet (10Mb) */ -#define DLT_EN3MB 2 /* Experimental Ethernet (3Mb) */ -#define DLT_AX25 3 /* Amateur Radio AX.25 */ -#define DLT_PRONET 4 /* Proteon ProNET Token Ring */ -#define DLT_CHAOS 5 /* Chaos */ -#define DLT_IEEE802 6 /* 802.5 Token Ring */ -#define DLT_ARCNET 7 /* ARCNET, with BSD-style header */ -#define DLT_SLIP 8 /* Serial Line IP */ -#define DLT_PPP 9 /* Point-to-point Protocol */ -#define DLT_FDDI 10 /* FDDI */ - -/* - * These are types that are different on some platforms, and that - * have been defined by for ages. We use #ifdefs to - * detect the BSDs that define them differently from the traditional - * libpcap - * - * XXX - DLT_ATM_RFC1483 is 13 in BSD/OS, and DLT_RAW is 14 in BSD/OS, - * but I don't know what the right #define is for BSD/OS. - */ -#define DLT_ATM_RFC1483 11 /* LLC-encapsulated ATM */ - -#ifdef __OpenBSD__ -#define DLT_RAW 14 /* raw IP */ -#else -#define DLT_RAW 12 /* raw IP */ -#endif - -/* - * Given that the only OS that currently generates BSD/OS SLIP or PPP - * is, well, BSD/OS, arguably everybody should have chosen its values - * for DLT_SLIP_BSDOS and DLT_PPP_BSDOS, which are 15 and 16, but they - * didn't. So it goes. - */ -#if defined(__NetBSD__) || defined(__FreeBSD__) -#ifndef DLT_SLIP_BSDOS -#define DLT_SLIP_BSDOS 13 /* BSD/OS Serial Line IP */ -#define DLT_PPP_BSDOS 14 /* BSD/OS Point-to-point Protocol */ -#endif -#else -#define DLT_SLIP_BSDOS 15 /* BSD/OS Serial Line IP */ -#define DLT_PPP_BSDOS 16 /* BSD/OS Point-to-point Protocol */ -#endif - -/* - * 17 is used for DLT_OLD_PFLOG in OpenBSD; - * OBSOLETE: DLT_PFLOG is 117 in OpenBSD now as well. See below. - * 18 is used for DLT_PFSYNC in OpenBSD; don't use it for anything else. - */ - -#define DLT_ATM_CLIP 19 /* Linux Classical-IP over ATM */ - -/* - * Apparently Redback uses this for its SmartEdge 400/800. I hope - * nobody else decided to use it, too. - */ -#define DLT_REDBACK_SMARTEDGE 32 - -/* - * These values are defined by NetBSD; other platforms should refrain from - * using them for other purposes, so that NetBSD savefiles with link - * types of 50 or 51 can be read as this type on all platforms. - */ -#define DLT_PPP_SERIAL 50 /* PPP over serial with HDLC encapsulation */ -#define DLT_PPP_ETHER 51 /* PPP over Ethernet */ - -/* - * The Axent Raptor firewall - now the Symantec Enterprise Firewall - uses - * a link-layer type of 99 for the tcpdump it supplies. The link-layer - * header has 6 bytes of unknown data, something that appears to be an - * Ethernet type, and 36 bytes that appear to be 0 in at least one capture - * I've seen. - */ -#define DLT_SYMANTEC_FIREWALL 99 - -/* - * Values between 100 and 103 are used in capture file headers as - * link-layer types corresponding to DLT_ types that differ - * between platforms; don't use those values for new DLT_ new types. - */ - -/* - * This value was defined by libpcap 0.5; platforms that have defined - * it with a different value should define it here with that value - - * a link type of 104 in a save file will be mapped to DLT_C_HDLC, - * whatever value that happens to be, so programs will correctly - * handle files with that link type regardless of the value of - * DLT_C_HDLC. - * - * The name DLT_C_HDLC was used by BSD/OS; we use that name for source - * compatibility with programs written for BSD/OS. - * - * libpcap 0.5 defined it as DLT_CHDLC; we define DLT_CHDLC as well, - * for source compatibility with programs written for libpcap 0.5. - */ -#define DLT_C_HDLC 104 /* Cisco HDLC */ -#define DLT_CHDLC DLT_C_HDLC - -#define DLT_IEEE802_11 105 /* IEEE 802.11 wireless */ - -/* - * 106 is reserved for Linux Classical IP over ATM; it's like DLT_RAW, - * except when it isn't. (I.e., sometimes it's just raw IP, and - * sometimes it isn't.) We currently handle it as DLT_LINUX_SLL, - * so that we don't have to worry about the link-layer header.) - */ - -/* - * Frame Relay; BSD/OS has a DLT_FR with a value of 11, but that collides - * with other values. - * DLT_FR and DLT_FRELAY packets start with the Q.922 Frame Relay header - * (DLCI, etc.). - */ -#define DLT_FRELAY 107 - -/* - * OpenBSD DLT_LOOP, for loopback devices; it's like DLT_NULL, except - * that the AF_ type in the link-layer header is in network byte order. - * - * DLT_LOOP is 12 in OpenBSD, but that's DLT_RAW in other OSes, so - * we don't use 12 for it in OSes other than OpenBSD. - */ -#ifdef __OpenBSD__ -#define DLT_LOOP 12 -#else -#define DLT_LOOP 108 -#endif - -/* - * Encapsulated packets for IPsec; DLT_ENC is 13 in OpenBSD, but that's - * DLT_SLIP_BSDOS in NetBSD, so we don't use 13 for it in OSes other - * than OpenBSD. - */ -#ifdef __OpenBSD__ -#define DLT_ENC 13 -#else -#define DLT_ENC 109 -#endif - -/* - * Values between 110 and 112 are reserved for use in capture file headers - * as link-layer types corresponding to DLT_ types that might differ - * between platforms; don't use those values for new DLT_ types - * other than the corresponding DLT_ types. - */ - -/* - * This is for Linux cooked sockets. - */ -#define DLT_LINUX_SLL 113 - -/* - * Apple LocalTalk hardware. - */ -#define DLT_LTALK 114 - -/* - * Acorn Econet. - */ -#define DLT_ECONET 115 - -/* - * Reserved for use with OpenBSD ipfilter. - */ -#define DLT_IPFILTER 116 - -/* - * OpenBSD DLT_PFLOG; DLT_PFLOG is 17 in OpenBSD, but that's DLT_LANE8023 - * in SuSE 6.3, so we can't use 17 for it in capture-file headers. - * - * XXX: is there a conflict with DLT_PFSYNC 18 as well? - */ -#ifdef __OpenBSD__ -#define DLT_OLD_PFLOG 17 -#define DLT_PFSYNC 18 -#endif -#define DLT_PFLOG 117 - -/* - * Registered for Cisco-internal use. - */ -#define DLT_CISCO_IOS 118 - -/* - * For 802.11 cards using the Prism II chips, with a link-layer - * header including Prism monitor mode information plus an 802.11 - * header. - */ -#define DLT_PRISM_HEADER 119 - -/* - * Reserved for Aironet 802.11 cards, with an Aironet link-layer header - * (see Doug Ambrisko's FreeBSD patches). - */ -#define DLT_AIRONET_HEADER 120 - -/* - * Reserved for Siemens HiPath HDLC. - */ -#define DLT_HHDLC 121 - -/* - * This is for RFC 2625 IP-over-Fibre Channel. - * - * This is not for use with raw Fibre Channel, where the link-layer - * header starts with a Fibre Channel frame header; it's for IP-over-FC, - * where the link-layer header starts with an RFC 2625 Network_Header - * field. - */ -#define DLT_IP_OVER_FC 122 - -/* - * This is for Full Frontal ATM on Solaris with SunATM, with a - * pseudo-header followed by an AALn PDU. - * - * There may be other forms of Full Frontal ATM on other OSes, - * with different pseudo-headers. - * - * If ATM software returns a pseudo-header with VPI/VCI information - * (and, ideally, packet type information, e.g. signalling, ILMI, - * LANE, LLC-multiplexed traffic, etc.), it should not use - * DLT_ATM_RFC1483, but should get a new DLT_ value, so tcpdump - * and the like don't have to infer the presence or absence of a - * pseudo-header and the form of the pseudo-header. - */ -#define DLT_SUNATM 123 /* Solaris+SunATM */ - -/* - * Reserved as per request from Kent Dahlgren - * for private use. - */ -#define DLT_RIO 124 /* RapidIO */ -#define DLT_PCI_EXP 125 /* PCI Express */ -#define DLT_AURORA 126 /* Xilinx Aurora link layer */ - -/* - * Header for 802.11 plus a number of bits of link-layer information - * including radio information, used by some recent BSD drivers as - * well as the madwifi Atheros driver for Linux. - */ -#define DLT_IEEE802_11_RADIO 127 /* 802.11 plus radiotap radio header */ - -/* - * Reserved for the TZSP encapsulation, as per request from - * Chris Waters - * TZSP is a generic encapsulation for any other link type, - * which includes a means to include meta-information - * with the packet, e.g. signal strength and channel - * for 802.11 packets. - */ -#define DLT_TZSP 128 /* Tazmen Sniffer Protocol */ - -/* - * BSD's ARCNET headers have the source host, destination host, - * and type at the beginning of the packet; that's what's handed - * up to userland via BPF. - * - * Linux's ARCNET headers, however, have a 2-byte offset field - * between the host IDs and the type; that's what's handed up - * to userland via PF_PACKET sockets. - * - * We therefore have to have separate DLT_ values for them. - */ -#define DLT_ARCNET_LINUX 129 /* ARCNET */ - -/* - * Juniper-private data link types, as per request from - * Hannes Gredler . The DLT_s are used - * for passing on chassis-internal metainformation such as - * QOS profiles, etc.. - */ -#define DLT_JUNIPER_MLPPP 130 -#define DLT_JUNIPER_MLFR 131 -#define DLT_JUNIPER_ES 132 -#define DLT_JUNIPER_GGSN 133 -#define DLT_JUNIPER_MFR 134 -#define DLT_JUNIPER_ATM2 135 -#define DLT_JUNIPER_SERVICES 136 -#define DLT_JUNIPER_ATM1 137 - -/* - * Apple IP-over-IEEE 1394, as per a request from Dieter Siegmund - * . The header that's presented is an Ethernet-like - * header: - * - * #define FIREWIRE_EUI64_LEN 8 - * struct firewire_header { - * u_char firewire_dhost[FIREWIRE_EUI64_LEN]; - * u_char firewire_shost[FIREWIRE_EUI64_LEN]; - * u_short firewire_type; - * }; - * - * with "firewire_type" being an Ethernet type value, rather than, - * for example, raw GASP frames being handed up. - */ -#define DLT_APPLE_IP_OVER_IEEE1394 138 - -/* - * Various SS7 encapsulations, as per a request from Jeff Morriss - * and subsequent discussions. - */ -#define DLT_MTP2_WITH_PHDR 139 /* pseudo-header with various info, followed by MTP2 */ -#define DLT_MTP2 140 /* MTP2, without pseudo-header */ -#define DLT_MTP3 141 /* MTP3, without pseudo-header or MTP2 */ -#define DLT_SCCP 142 /* SCCP, without pseudo-header or MTP2 or MTP3 */ - -/* - * DOCSIS MAC frames. - */ -#define DLT_DOCSIS 143 - -/* - * Linux-IrDA packets. Protocol defined at http://www.irda.org. - * Those packets include IrLAP headers and above (IrLMP...), but - * don't include Phy framing (SOF/EOF/CRC & byte stuffing), because Phy - * framing can be handled by the hardware and depend on the bitrate. - * This is exactly the format you would get capturing on a Linux-IrDA - * interface (irdaX), but not on a raw serial port. - * Note the capture is done in "Linux-cooked" mode, so each packet include - * a fake packet header (struct sll_header). This is because IrDA packet - * decoding is dependant on the direction of the packet (incomming or - * outgoing). - * When/if other platform implement IrDA capture, we may revisit the - * issue and define a real DLT_IRDA... - * Jean II - */ -#define DLT_LINUX_IRDA 144 - -/* - * Reserved for IBM SP switch and IBM Next Federation switch. - */ -#define DLT_IBM_SP 145 -#define DLT_IBM_SN 146 - -/* - * Reserved for private use. If you have some link-layer header type - * that you want to use within your organization, with the capture files - * using that link-layer header type not ever be sent outside your - * organization, you can use these values. - * - * No libpcap release will use these for any purpose, nor will any - * tcpdump release use them, either. - * - * Do *NOT* use these in capture files that you expect anybody not using - * your private versions of capture-file-reading tools to read; in - * particular, do *NOT* use them in products, otherwise you may find that - * people won't be able to use tcpdump, or snort, or Ethereal, or... to - * read capture files from your firewall/intrusion detection/traffic - * monitoring/etc. appliance, or whatever product uses that DLT_ value, - * and you may also find that the developers of those applications will - * not accept patches to let them read those files. - * - * Also, do not use them if somebody might send you a capture using them - * for *their* private type and tools using them for *your* private type - * would have to read them. - * - * Instead, ask "tcpdump-workers@lists.tcpdump.org" for a new DLT_ value, - * as per the comment above, and use the type you're given. - */ -#define DLT_USER0 147 -#define DLT_USER1 148 -#define DLT_USER2 149 -#define DLT_USER3 150 -#define DLT_USER4 151 -#define DLT_USER5 152 -#define DLT_USER6 153 -#define DLT_USER7 154 -#define DLT_USER8 155 -#define DLT_USER9 156 -#define DLT_USER10 157 -#define DLT_USER11 158 -#define DLT_USER12 159 -#define DLT_USER13 160 -#define DLT_USER14 161 -#define DLT_USER15 162 - -/* - * For future use with 802.11 captures - defined by AbsoluteValue - * Systems to store a number of bits of link-layer information - * including radio information: - * - * http://www.shaftnet.org/~pizza/software/capturefrm.txt - * - * but it might be used by some non-AVS drivers now or in the - * future. - */ -#define DLT_IEEE802_11_RADIO_AVS 163 /* 802.11 plus AVS radio header */ - -/* - * Juniper-private data link type, as per request from - * Hannes Gredler . The DLT_s are used - * for passing on chassis-internal metainformation such as - * QOS profiles, etc.. - */ -#define DLT_JUNIPER_MONITOR 164 - -/* - * Reserved for BACnet MS/TP. - */ -#define DLT_BACNET_MS_TP 165 - -/* - * Another PPP variant as per request from Karsten Keil . - * - * This is used in some OSes to allow a kernel socket filter to distinguish - * between incoming and outgoing packets, on a socket intended to - * supply pppd with outgoing packets so it can do dial-on-demand and - * hangup-on-lack-of-demand; incoming packets are filtered out so they - * don't cause pppd to hold the connection up (you don't want random - * input packets such as port scans, packets from old lost connections, - * etc. to force the connection to stay up). - * - * The first byte of the PPP header (0xff03) is modified to accomodate - * the direction - 0x00 = IN, 0x01 = OUT. - */ -#define DLT_PPP_PPPD 166 - -/* - * Names for backwards compatibility with older versions of some PPP - * software; new software should use DLT_PPP_PPPD. - */ -#define DLT_PPP_WITH_DIRECTION DLT_PPP_PPPD -#define DLT_LINUX_PPP_WITHDIRECTION DLT_PPP_PPPD - -/* - * Juniper-private data link type, as per request from - * Hannes Gredler . The DLT_s are used - * for passing on chassis-internal metainformation such as - * QOS profiles, cookies, etc.. - */ -#define DLT_JUNIPER_PPPOE 167 -#define DLT_JUNIPER_PPPOE_ATM 168 - -#define DLT_GPRS_LLC 169 /* GPRS LLC */ -#define DLT_GPF_T 170 /* GPF-T (ITU-T G.7041/Y.1303) */ -#define DLT_GPF_F 171 /* GPF-F (ITU-T G.7041/Y.1303) */ - -/* - * Requested by Oolan Zimmer for use in Gcom's T1/E1 line - * monitoring equipment. - */ -#define DLT_GCOM_T1E1 172 -#define DLT_GCOM_SERIAL 173 - -/* - * Juniper-private data link type, as per request from - * Hannes Gredler . The DLT_ is used - * for internal communication to Physical Interface Cards (PIC) - */ -#define DLT_JUNIPER_PIC_PEER 174 - -/* - * Link types requested by Gregor Maier of Endace - * Measurement Systems. They add an ERF header (see - * http://www.endace.com/support/EndaceRecordFormat.pdf) in front of - * the link-layer header. - */ -#define DLT_ERF_ETH 175 /* Ethernet */ -#define DLT_ERF_POS 176 /* Packet-over-SONET */ - -/* - * Requested by Daniele Orlandi for raw LAPD - * for vISDN (http://www.orlandi.com/visdn/). Its link-layer header - * includes additional information before the LAPD header, so it's - * not necessarily a generic LAPD header. - */ -#define DLT_LINUX_LAPD 177 - -/* - * Juniper-private data link type, as per request from - * Hannes Gredler . - * The DLT_ are used for prepending meta-information - * like interface index, interface name - * before standard Ethernet, PPP, Frelay & C-HDLC Frames - */ -#define DLT_JUNIPER_ETHER 178 -#define DLT_JUNIPER_PPP 179 -#define DLT_JUNIPER_FRELAY 180 -#define DLT_JUNIPER_CHDLC 181 - -/* - * Multi Link Frame Relay (FRF.16) - */ -#define DLT_MFR 182 - -/* - * Juniper-private data link type, as per request from - * Hannes Gredler . - * The DLT_ is used for internal communication with a - * voice Adapter Card (PIC) - */ -#define DLT_JUNIPER_VP 183 - -/* - * Arinc 429 frames. - * DLT_ requested by Gianluca Varenni . - * Every frame contains a 32bit A429 label. - * More documentation on Arinc 429 can be found at - * http://www.condoreng.com/support/downloads/tutorials/ARINCTutorial.pdf - */ -#define DLT_A429 184 - -/* - * Arinc 653 Interpartition Communication messages. - * DLT_ requested by Gianluca Varenni . - * Please refer to the A653-1 standard for more information. - */ -#define DLT_A653_ICM 185 - -/* - * USB packets, beginning with a USB setup header; requested by - * Paolo Abeni . - */ -#define DLT_USB 186 - -/* - * Bluetooth HCI UART transport layer (part H:4); requested by - * Paolo Abeni. - */ -#define DLT_BLUETOOTH_HCI_H4 187 - -/* - * IEEE 802.16 MAC Common Part Sublayer; requested by Maria Cruz - * . - */ -#define DLT_IEEE802_16_MAC_CPS 188 - -/* - * USB packets, beginning with a Linux USB header; requested by - * Paolo Abeni . - */ -#define DLT_USB_LINUX 189 - -/* - * Controller Area Network (CAN) v. 2.0B packets. - * DLT_ requested by Gianluca Varenni . - * Used to dump CAN packets coming from a CAN Vector board. - * More documentation on the CAN v2.0B frames can be found at - * http://www.can-cia.org/downloads/?269 - */ -#define DLT_CAN20B 190 - -/* - * IEEE 802.15.4, with address fields padded, as is done by Linux - * drivers; requested by Juergen Schimmer. - */ -#define DLT_IEEE802_15_4_LINUX 191 - -/* - * Per Packet Information encapsulated packets. - * DLT_ requested by Gianluca Varenni . - */ -#define DLT_PPI 192 - -/* - * Header for 802.16 MAC Common Part Sublayer plus a radiotap radio header; - * requested by Charles Clancy. - */ -#define DLT_IEEE802_16_MAC_CPS_RADIO 193 - -/* - * Juniper-private data link type, as per request from - * Hannes Gredler . - * The DLT_ is used for internal communication with a - * integrated service module (ISM). - */ -#define DLT_JUNIPER_ISM 194 - -/* - * IEEE 802.15.4, exactly as it appears in the spec (no padding, no - * nothing); requested by Mikko Saarnivala . - */ -#define DLT_IEEE802_15_4 195 - -/* - * Various link-layer types, with a pseudo-header, for SITA - * (http://www.sita.aero/); requested by Fulko Hew (fulko.hew@gmail.com). - */ -#define DLT_SITA 196 - -/* - * Various link-layer types, with a pseudo-header, for Endace DAG cards; - * encapsulates Endace ERF records. Requested by Stephen Donnelly - * . - */ -#define DLT_ERF 197 - -/* - * Special header prepended to Ethernet packets when capturing from a - * u10 Networks board. Requested by Phil Mulholland - * . - */ -#define DLT_RAIF1 198 - -/* - * IPMB packet for IPMI, beginning with the I2C slave address, followed - * by the netFn and LUN, etc.. Requested by Chanthy Toeung - * . - */ -#define DLT_IPMB 199 - -/* - * Juniper-private data link type, as per request from - * Hannes Gredler . - * The DLT_ is used for capturing data on a secure tunnel interface. - */ -#define DLT_JUNIPER_ST 200 - -/* - * Bluetooth HCI UART transport layer (part H:4), with pseudo-header - * that includes direction information; requested by Paolo Abeni. - */ -#define DLT_BLUETOOTH_HCI_H4_WITH_PHDR 201 - -/* - * AX.25 packet with a 1-byte KISS header; see - * - * http://www.ax25.net/kiss.htm - * - * as per Richard Stearn . - */ -#define DLT_AX25_KISS 202 - -/* - * LAPD packets from an ISDN channel, starting with the address field, - * with no pseudo-header. - * Requested by Varuna De Silva . - */ -#define DLT_LAPD 203 - -/* - * Variants of various link-layer headers, with a one-byte direction - * pseudo-header prepended - zero means "received by this host", - * non-zero (any non-zero value) means "sent by this host" - as per - * Will Barker . - */ -#define DLT_PPP_WITH_DIR 204 /* PPP - don't confuse with DLT_PPP_WITH_DIRECTION */ -#define DLT_C_HDLC_WITH_DIR 205 /* Cisco HDLC */ -#define DLT_FRELAY_WITH_DIR 206 /* Frame Relay */ -#define DLT_LAPB_WITH_DIR 207 /* LAPB */ - -/* - * 208 is reserved for an as-yet-unspecified proprietary link-layer - * type, as requested by Will Barker. - */ - -/* - * IPMB with a Linux-specific pseudo-header; as requested by Alexey Neyman - * . - */ -#define DLT_IPMB_LINUX 209 - -/* - * FlexRay automotive bus - http://www.flexray.com/ - as requested - * by Hannes Kaelber . - */ -#define DLT_FLEXRAY 210 - -/* - * Media Oriented Systems Transport (MOST) bus for multimedia - * transport - http://www.mostcooperation.com/ - as requested - * by Hannes Kaelber . - */ -#define DLT_MOST 211 - -/* - * Local Interconnect Network (LIN) bus for vehicle networks - - * http://www.lin-subbus.org/ - as requested by Hannes Kaelber - * . - */ -#define DLT_LIN 212 - -/* - * X2E-private data link type used for serial line capture, - * as requested by Hannes Kaelber . - */ -#define DLT_X2E_SERIAL 213 - -/* - * X2E-private data link type used for the Xoraya data logger - * family, as requested by Hannes Kaelber . - */ -#define DLT_X2E_XORAYA 214 - -/* - * IEEE 802.15.4, exactly as it appears in the spec (no padding, no - * nothing), but with the PHY-level data for non-ASK PHYs (4 octets - * of 0 as preamble, one octet of SFD, one octet of frame length+ - * reserved bit, and then the MAC-layer data, starting with the - * frame control field). - * - * Requested by Max Filippov . - */ -#define DLT_IEEE802_15_4_NONASK_PHY 215 - - -/* - * DLT and savefile link type values are split into a class and - * a member of that class. A class value of 0 indicates a regular - * DLT_/LINKTYPE_ value. - */ -#define DLT_CLASS(x) ((x) & 0x03ff0000) - -/* - * NetBSD-specific generic "raw" link type. The class value indicates - * that this is the generic raw type, and the lower 16 bits are the - * address family we're dealing with. Those values are NetBSD-specific; - * do not assume that they correspond to AF_ values for your operating - * system. - */ -#define DLT_CLASS_NETBSD_RAWAF 0x02240000 -#define DLT_NETBSD_RAWAF(af) (DLT_CLASS_NETBSD_RAWAF | (af)) -#define DLT_NETBSD_RAWAF_AF(x) ((x) & 0x0000ffff) -#define DLT_IS_NETBSD_RAWAF(x) (DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF) - - -/* - * The instruction encodings. - */ -/* instruction classes */ -#define BPF_CLASS(code) ((code) & 0x07) -#define BPF_LD 0x00 -#define BPF_LDX 0x01 -#define BPF_ST 0x02 -#define BPF_STX 0x03 -#define BPF_ALU 0x04 -#define BPF_JMP 0x05 -#define BPF_RET 0x06 -#define BPF_MISC 0x07 - -/* ld/ldx fields */ -#define BPF_SIZE(code) ((code) & 0x18) -#define BPF_W 0x00 -#define BPF_H 0x08 -#define BPF_B 0x10 -#define BPF_MODE(code) ((code) & 0xe0) -#define BPF_IMM 0x00 -#define BPF_ABS 0x20 -#define BPF_IND 0x40 -#define BPF_MEM 0x60 -#define BPF_LEN 0x80 -#define BPF_MSH 0xa0 - -/* alu/jmp fields */ -#define BPF_OP(code) ((code) & 0xf0) -#define BPF_ADD 0x00 -#define BPF_SUB 0x10 -#define BPF_MUL 0x20 -#define BPF_DIV 0x30 -#define BPF_OR 0x40 -#define BPF_AND 0x50 -#define BPF_LSH 0x60 -#define BPF_RSH 0x70 -#define BPF_NEG 0x80 -#define BPF_JA 0x00 -#define BPF_JEQ 0x10 -#define BPF_JGT 0x20 -#define BPF_JGE 0x30 -#define BPF_JSET 0x40 -#define BPF_SRC(code) ((code) & 0x08) -#define BPF_K 0x00 -#define BPF_X 0x08 - -/* ret - BPF_K and BPF_X also apply */ -#define BPF_RVAL(code) ((code) & 0x18) -#define BPF_A 0x10 - -/* misc */ -#define BPF_MISCOP(code) ((code) & 0xf8) -#define BPF_TAX 0x00 -#define BPF_TXA 0x80 - -/* - * The instruction data structure. - */ -struct bpf_insn { - u_short code; - u_char jt; - u_char jf; - bpf_u_int32 k; -}; - -/* - * Macros for insn array initializers. - */ -#define BPF_STMT(code, k) { (u_short)(code), 0, 0, k } -#define BPF_JUMP(code, k, jt, jf) { (u_short)(code), jt, jf, k } - -#if __STDC__ || defined(__cplusplus) -extern int bpf_validate(const struct bpf_insn *, int); -extern u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int); -#else -extern int bpf_validate(); -extern u_int bpf_filter(); -#endif - -/* - * Number of scratch memory words (for BPF_LD|BPF_MEM and BPF_ST). - */ -#define BPF_MEMWORDS 16 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/namedb.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/namedb.h deleted file mode 100644 index 9002c7509..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/namedb.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 1994, 1996 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the Computer Systems - * Engineering Group at Lawrence Berkeley Laboratory. - * 4. Neither the name of the University nor of the Laboratory may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#) $Header: /tcpdump/master/libpcap/pcap/namedb.h,v 1.1 2006/10/04 18:09:22 guy Exp $ (LBL) - */ - -#ifndef lib_pcap_namedb_h -#define lib_pcap_namedb_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * As returned by the pcap_next_etherent() - * XXX this stuff doesn't belong in this interface, but this - * library already must do name to address translation, so - * on systems that don't have support for /etc/ethers, we - * export these hooks since they'll - */ -struct pcap_etherent { - u_char addr[6]; - char name[122]; -}; -#ifndef PCAP_ETHERS_FILE -#define PCAP_ETHERS_FILE "/etc/ethers" -#endif -struct pcap_etherent *pcap_next_etherent(FILE *); -u_char *pcap_ether_hostton(const char*); -u_char *pcap_ether_aton(const char *); - -bpf_u_int32 **pcap_nametoaddr(const char *); -#ifdef INET6 -struct addrinfo *pcap_nametoaddrinfo(const char *); -#endif -bpf_u_int32 pcap_nametonetaddr(const char *); - -int pcap_nametoport(const char *, int *, int *); -int pcap_nametoportrange(const char *, int *, int *, int *); -int pcap_nametoproto(const char *); -int pcap_nametoeproto(const char *); -int pcap_nametollc(const char *); -/* - * If a protocol is unknown, PROTO_UNDEF is returned. - * Also, pcap_nametoport() returns the protocol along with the port number. - * If there are ambiguous entried in /etc/services (i.e. domain - * can be either tcp or udp) PROTO_UNDEF is returned. - */ -#define PROTO_UNDEF -1 - -/* XXX move these to pcap-int.h? */ -int __pcap_atodn(const char *, bpf_u_int32 *); -int __pcap_atoin(const char *, bpf_u_int32 *); -u_short __pcap_nametodnaddr(const char *); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/sll.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/sll.h deleted file mode 100644 index e9d5452af..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/sll.h +++ /dev/null @@ -1,129 +0,0 @@ -/*- - * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from the Stanford/CMU enet packet filter, - * (net/enet.c) distributed as part of 4.3BSD, and code contributed - * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence - * Berkeley Laboratory. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#) $Header: /tcpdump/master/libpcap/pcap/sll.h,v 1.2.2.1 2008-05-30 01:36:06 guy Exp $ (LBL) - */ - -/* - * For captures on Linux cooked sockets, we construct a fake header - * that includes: - * - * a 2-byte "packet type" which is one of: - * - * LINUX_SLL_HOST packet was sent to us - * LINUX_SLL_BROADCAST packet was broadcast - * LINUX_SLL_MULTICAST packet was multicast - * LINUX_SLL_OTHERHOST packet was sent to somebody else - * LINUX_SLL_OUTGOING packet was sent *by* us; - * - * a 2-byte Ethernet protocol field; - * - * a 2-byte link-layer type; - * - * a 2-byte link-layer address length; - * - * an 8-byte source link-layer address, whose actual length is - * specified by the previous value. - * - * All fields except for the link-layer address are in network byte order. - * - * DO NOT change the layout of this structure, or change any of the - * LINUX_SLL_ values below. If you must change the link-layer header - * for a "cooked" Linux capture, introduce a new DLT_ type (ask - * "tcpdump-workers@lists.tcpdump.org" for one, so that you don't give it - * a value that collides with a value already being used), and use the - * new header in captures of that type, so that programs that can - * handle DLT_LINUX_SLL captures will continue to handle them correctly - * without any change, and so that capture files with different headers - * can be told apart and programs that read them can dissect the - * packets in them. - */ - -#ifndef lib_pcap_sll_h -#define lib_pcap_sll_h - -/* - * A DLT_LINUX_SLL fake link-layer header. - */ -#define SLL_HDR_LEN 16 /* total header length */ -#define SLL_ADDRLEN 8 /* length of address field */ - -struct sll_header { - u_int16_t sll_pkttype; /* packet type */ - u_int16_t sll_hatype; /* link-layer address type */ - u_int16_t sll_halen; /* link-layer address length */ - u_int8_t sll_addr[SLL_ADDRLEN]; /* link-layer address */ - u_int16_t sll_protocol; /* protocol */ -}; - -/* - * The LINUX_SLL_ values for "sll_pkttype"; these correspond to the - * PACKET_ values on Linux, but are defined here so that they're - * available even on systems other than Linux, and so that they - * don't change even if the PACKET_ values change. - */ -#define LINUX_SLL_HOST 0 -#define LINUX_SLL_BROADCAST 1 -#define LINUX_SLL_MULTICAST 2 -#define LINUX_SLL_OTHERHOST 3 -#define LINUX_SLL_OUTGOING 4 - -/* - * The LINUX_SLL_ values for "sll_protocol"; these correspond to the - * ETH_P_ values on Linux, but are defined here so that they're - * available even on systems other than Linux. We assume, for now, - * that the ETH_P_ values won't change in Linux; if they do, then: - * - * if we don't translate them in "pcap-linux.c", capture files - * won't necessarily be readable if captured on a system that - * defines ETH_P_ values that don't match these values; - * - * if we do translate them in "pcap-linux.c", that makes life - * unpleasant for the BPF code generator, as the values you test - * for in the kernel aren't the values that you test for when - * reading a capture file, so the fixup code run on BPF programs - * handed to the kernel ends up having to do more work. - * - * Add other values here as necessary, for handling packet types that - * might show up on non-Ethernet, non-802.x networks. (Not all the ones - * in the Linux "if_ether.h" will, I suspect, actually show up in - * captures.) - */ -#define LINUX_SLL_P_802_3 0x0001 /* Novell 802.3 frames without 802.2 LLC header */ -#define LINUX_SLL_P_802_2 0x0004 /* 802.2 frames (not D/I/X Ethernet) */ - -#endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/usb.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/usb.h deleted file mode 100644 index adcd19c05..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/usb.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2006 Paolo Abeni (Italy) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Basic USB data struct - * By Paolo Abeni - * - * @(#) $Header: /tcpdump/master/libpcap/pcap/usb.h,v 1.6 2007/09/22 02:06:08 guy Exp $ - */ - -#ifndef _PCAP_USB_STRUCTS_H__ -#define _PCAP_USB_STRUCTS_H__ - -/* - * possible transfer mode - */ -#define URB_TRANSFER_IN 0x80 -#define URB_ISOCHRONOUS 0x0 -#define URB_INTERRUPT 0x1 -#define URB_CONTROL 0x2 -#define URB_BULK 0x3 - -/* - * possible event type - */ -#define URB_SUBMIT 'S' -#define URB_COMPLETE 'C' -#define URB_ERROR 'E' - -/* - * USB setup header as defined in USB specification. - * Appears at the front of each packet in DLT_USB captures. - */ -typedef struct _usb_setup { - u_int8_t bmRequestType; - u_int8_t bRequest; - u_int16_t wValue; - u_int16_t wIndex; - u_int16_t wLength; -} pcap_usb_setup; - - -/* - * Header prepended by linux kernel to each event. - * Appears at the front of each packet in DLT_USB_LINUX captures. - */ -typedef struct _usb_header { - u_int64_t id; - u_int8_t event_type; - u_int8_t transfer_type; - u_int8_t endpoint_number; - u_int8_t device_address; - u_int16_t bus_id; - char setup_flag;/*if !=0 the urb setup header is not present*/ - char data_flag; /*if !=0 no urb data is present*/ - int64_t ts_sec; - int32_t ts_usec; - int32_t status; - u_int32_t urb_len; - u_int32_t data_len; /* amount of urb data really present in this event*/ - pcap_usb_setup setup; -} pcap_usb_header; - - -#endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/vlan.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/vlan.h deleted file mode 100644 index b0cb7949b..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/pcap/vlan.h +++ /dev/null @@ -1,46 +0,0 @@ -/*- - * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#) $Header: /tcpdump/master/libpcap/pcap/vlan.h,v 1.1.2.2 2008-08-06 07:45:59 guy Exp $ - */ - -#ifndef lib_pcap_vlan_h -#define lib_pcap_vlan_h - -struct vlan_tag { - u_int16_t vlan_tpid; /* ETH_P_8021Q */ - u_int16_t vlan_tci; /* VLAN TCI */ -}; - -#define VLAN_TAG_LEN 4 - -#endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/remote-ext.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/remote-ext.h deleted file mode 100644 index 9f54d6974..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/remote-ext.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright (c) 2002 - 2003 - * NetGroup, Politecnico di Torino (Italy) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Politecnico di Torino nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef __REMOTE_EXT_H__ -#define __REMOTE_EXT_H__ - - -#ifndef HAVE_REMOTE -#error Please do not include this file directly. Just define HAVE_REMOTE and then include pcap.h -#endif - -// Definition for Microsoft Visual Studio -#if _MSC_VER > 1000 -#pragma once -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \file remote-ext.h - - The goal of this file it to include most of the new definitions that should be - placed into the pcap.h file. - - It includes all new definitions (structures and functions like pcap_open(). - Some of the functions are not really a remote feature, but, right now, - they are placed here. -*/ - - - -// All this stuff is public -/*! \addtogroup remote_struct - \{ -*/ - - - - -/*! - \brief Defines the maximum buffer size in which address, port, interface names are kept. - - In case the adapter name or such is larger than this value, it is truncated. - This is not used by the user; however it must be aware that an hostname / interface - name longer than this value will be truncated. -*/ -#define PCAP_BUF_SIZE 1024 - - -/*! \addtogroup remote_source_ID - \{ -*/ - - -/*! - \brief Internal representation of the type of source in use (file, - remote/local interface). - - This indicates a file, i.e. the user want to open a capture from a local file. -*/ -#define PCAP_SRC_FILE 2 -/*! - \brief Internal representation of the type of source in use (file, - remote/local interface). - - This indicates a local interface, i.e. the user want to open a capture from - a local interface. This does not involve the RPCAP protocol. -*/ -#define PCAP_SRC_IFLOCAL 3 -/*! - \brief Internal representation of the type of source in use (file, - remote/local interface). - - This indicates a remote interface, i.e. the user want to open a capture from - an interface on a remote host. This does involve the RPCAP protocol. -*/ -#define PCAP_SRC_IFREMOTE 4 - -/*! - \} -*/ - - - -/*! \addtogroup remote_source_string - - The formats allowed by the pcap_open() are the following: - - file://path_and_filename [opens a local file] - - rpcap://devicename [opens the selected device devices available on the local host, without using the RPCAP protocol] - - rpcap://host/devicename [opens the selected device available on a remote host] - - rpcap://host:port/devicename [opens the selected device available on a remote host, using a non-standard port for RPCAP] - - adaptername [to open a local adapter; kept for compability, but it is strongly discouraged] - - (NULL) [to open the first local adapter; kept for compability, but it is strongly discouraged] - - The formats allowed by the pcap_findalldevs_ex() are the following: - - file://folder/ [lists all the files in the given folder] - - rpcap:// [lists all local adapters] - - rpcap://host:port/ [lists the devices available on a remote host] - - Referring to the 'host' and 'port' paramters, they can be either numeric or literal. Since - IPv6 is fully supported, these are the allowed formats: - - - host (literal): e.g. host.foo.bar - - host (numeric IPv4): e.g. 10.11.12.13 - - host (numeric IPv4, IPv6 style): e.g. [10.11.12.13] - - host (numeric IPv6): e.g. [1:2:3::4] - - port: can be either numeric (e.g. '80') or literal (e.g. 'http') - - Here you find some allowed examples: - - rpcap://host.foo.bar/devicename [everything literal, no port number] - - rpcap://host.foo.bar:1234/devicename [everything literal, with port number] - - rpcap://10.11.12.13/devicename [IPv4 numeric, no port number] - - rpcap://10.11.12.13:1234/devicename [IPv4 numeric, with port number] - - rpcap://[10.11.12.13]:1234/devicename [IPv4 numeric with IPv6 format, with port number] - - rpcap://[1:2:3::4]/devicename [IPv6 numeric, no port number] - - rpcap://[1:2:3::4]:1234/devicename [IPv6 numeric, with port number] - - rpcap://[1:2:3::4]:http/devicename [IPv6 numeric, with literal port number] - - \{ -*/ - - -/*! - \brief String that will be used to determine the type of source in use (file, - remote/local interface). - - This string will be prepended to the interface name in order to create a string - that contains all the information required to open the source. - - This string indicates that the user wants to open a capture from a local file. -*/ -#define PCAP_SRC_FILE_STRING "file://" -/*! - \brief String that will be used to determine the type of source in use (file, - remote/local interface). - - This string will be prepended to the interface name in order to create a string - that contains all the information required to open the source. - - This string indicates that the user wants to open a capture from a network interface. - This string does not necessarily involve the use of the RPCAP protocol. If the - interface required resides on the local host, the RPCAP protocol is not involved - and the local functions are used. -*/ -#define PCAP_SRC_IF_STRING "rpcap://" - -/*! - \} -*/ - - - - - -/*! - \addtogroup remote_open_flags - \{ -*/ - -/*! - \brief Defines if the adapter has to go in promiscuous mode. - - It is '1' if you have to open the adapter in promiscuous mode, '0' otherwise. - Note that even if this parameter is false, the interface could well be in promiscuous - mode for some other reason (for example because another capture process with - promiscuous mode enabled is currently using that interface). - On on Linux systems with 2.2 or later kernels (that have the "any" device), this - flag does not work on the "any" device; if an argument of "any" is supplied, - the 'promisc' flag is ignored. -*/ -#define PCAP_OPENFLAG_PROMISCUOUS 1 - -/*! - \brief Defines if the data trasfer (in case of a remote - capture) has to be done with UDP protocol. - - If it is '1' if you want a UDP data connection, '0' if you want - a TCP data connection; control connection is always TCP-based. - A UDP connection is much lighter, but it does not guarantee that all - the captured packets arrive to the client workstation. Moreover, - it could be harmful in case of network congestion. - This flag is meaningless if the source is not a remote interface. - In that case, it is simply ignored. -*/ -#define PCAP_OPENFLAG_DATATX_UDP 2 - - -/*! - \brief Defines if the remote probe will capture its own generated traffic. - - In case the remote probe uses the same interface to capture traffic and to send - data back to the caller, the captured traffic includes the RPCAP traffic as well. - If this flag is turned on, the RPCAP traffic is excluded from the capture, so that - the trace returned back to the collector is does not include this traffic. -*/ -#define PCAP_OPENFLAG_NOCAPTURE_RPCAP 4 - -/*! - \brief Defines if the local adapter will capture its own generated traffic. - - This flag tells the underlying capture driver to drop the packets that were sent by itself. - This is usefult when building applications like bridges, that should ignore the traffic - they just sent. -*/ -#define PCAP_OPENFLAG_NOCAPTURE_LOCAL 8 - -/*! - \brief This flag configures the adapter for maximum responsiveness. - - In presence of a large value for nbytes, WinPcap waits for the arrival of several packets before - copying the data to the user. This guarantees a low number of system calls, i.e. lower processor usage, - i.e. better performance, which is good for applications like sniffers. If the user sets the - PCAP_OPENFLAG_MAX_RESPONSIVENESS flag, the capture driver will copy the packets as soon as the application - is ready to receive them. This is suggested for real time applications (like, for example, a bridge) - that need the best responsiveness.*/ -#define PCAP_OPENFLAG_MAX_RESPONSIVENESS 16 - -/*! - \} -*/ - - -/*! - \addtogroup remote_samp_methods - \{ -*/ - -/*! - \brief No sampling has to be done on the current capture. - - In this case, no sampling algorithms are applied to the current capture. -*/ -#define PCAP_SAMP_NOSAMP 0 - -/*! - \brief It defines that only 1 out of N packets must be returned to the user. - - In this case, the 'value' field of the 'pcap_samp' structure indicates the - number of packets (minus 1) that must be discarded before one packet got accepted. - In other words, if 'value = 10', the first packet is returned to the caller, while - the following 9 are discarded. -*/ -#define PCAP_SAMP_1_EVERY_N 1 - -/*! - \brief It defines that we have to return 1 packet every N milliseconds. - - In this case, the 'value' field of the 'pcap_samp' structure indicates the 'waiting - time' in milliseconds before one packet got accepted. - In other words, if 'value = 10', the first packet is returned to the caller; the next - returned one will be the first packet that arrives when 10ms have elapsed. -*/ -#define PCAP_SAMP_FIRST_AFTER_N_MS 2 - -/*! - \} -*/ - - -/*! - \addtogroup remote_auth_methods - \{ -*/ - -/*! - \brief It defines the NULL authentication. - - This value has to be used within the 'type' member of the pcap_rmtauth structure. - The 'NULL' authentication has to be equal to 'zero', so that old applications - can just put every field of struct pcap_rmtauth to zero, and it does work. -*/ -#define RPCAP_RMTAUTH_NULL 0 -/*! - \brief It defines the username/password authentication. - - With this type of authentication, the RPCAP protocol will use the username/ - password provided to authenticate the user on the remote machine. If the - authentication is successful (and the user has the right to open network devices) - the RPCAP connection will continue; otherwise it will be dropped. - - This value has to be used within the 'type' member of the pcap_rmtauth structure. -*/ -#define RPCAP_RMTAUTH_PWD 1 - -/*! - \} -*/ - - - - -/*! - - \brief This structure keeps the information needed to autheticate - the user on a remote machine. - - The remote machine can either grant or refuse the access according - to the information provided. - In case the NULL authentication is required, both 'username' and - 'password' can be NULL pointers. - - This structure is meaningless if the source is not a remote interface; - in that case, the functions which requires such a structure can accept - a NULL pointer as well. -*/ -struct pcap_rmtauth -{ - /*! - \brief Type of the authentication required. - - In order to provide maximum flexibility, we can support different types - of authentication based on the value of this 'type' variable. The currently - supported authentication methods are defined into the - \link remote_auth_methods Remote Authentication Methods Section\endlink. - - */ - int type; - /*! - \brief Zero-terminated string containing the username that has to be - used on the remote machine for authentication. - - This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication - and it can be NULL. - */ - char *username; - /*! - \brief Zero-terminated string containing the password that has to be - used on the remote machine for authentication. - - This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication - and it can be NULL. - */ - char *password; -}; - - -/*! - \brief This structure defines the information related to sampling. - - In case the sampling is requested, the capturing device should read - only a subset of the packets coming from the source. The returned packets depend - on the sampling parameters. - - \warning The sampling process is applied after the filtering process. - In other words, packets are filtered first, then the sampling process selects a - subset of the 'filtered' packets and it returns them to the caller. -*/ -struct pcap_samp -{ - /*! - Method used for sampling. Currently, the supported methods are listed in the - \link remote_samp_methods Sampling Methods Section\endlink. - */ - int method; - - /*! - This value depends on the sampling method defined. For its meaning, please check - at the \link remote_samp_methods Sampling Methods Section\endlink. - */ - int value; -}; - - - - -//! Maximum lenght of an host name (needed for the RPCAP active mode) -#define RPCAP_HOSTLIST_SIZE 1024 - - -/*! - \} -*/ // end of public documentation - - -// Exported functions - - - -/** \name New WinPcap functions - - This section lists the new functions that are able to help considerably in writing - WinPcap programs because of their easiness of use. - */ -//\{ -pcap_t *pcap_open(const char *source, int snaplen, int flags, int read_timeout, struct pcap_rmtauth *auth, char *errbuf); -int pcap_createsrcstr(char *source, int type, const char *host, const char *port, const char *name, char *errbuf); -int pcap_parsesrcstr(const char *source, int *type, char *host, char *port, char *name, char *errbuf); -int pcap_findalldevs_ex(char *source, struct pcap_rmtauth *auth, pcap_if_t **alldevs, char *errbuf); -struct pcap_samp *pcap_setsampling(pcap_t *p); - -//\} -// End of new winpcap functions - - - -/** \name Remote Capture functions - */ -//\{ -SOCKET pcap_remoteact_accept(const char *address, const char *port, const char *hostlist, char *connectinghost, struct pcap_rmtauth *auth, char *errbuf); -int pcap_remoteact_list(char *hostlist, char sep, int size, char *errbuf); -int pcap_remoteact_close(const char *host, char *errbuf); -void pcap_remoteact_cleanup(); -//\} -// End of remote capture functions - -#ifdef __cplusplus -} -#endif - - -#endif - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/wpcap.lib b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/wpcap.lib deleted file mode 100644 index f832e0445..000000000 Binary files a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/WinPCap/wpcap.lib and /dev/null differ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/main.c deleted file mode 100644 index ec948d2ae..000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/main.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include -#include - -/* FreeRTOS includes. */ -#include -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo application includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_Sockets.h" -#include "SimpleClientAndServer.h" -#include "TwoEchoClients.h" -#include "UDPCommandInterpreter.h" -#include "SelectServer.h" - -/* UDP command server task parameters. */ -#define mainUDP_CLI_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainUDP_CLI_PORT_NUMBER ( 5001UL ) -#define mainUDP_CLI_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE ) - -/* Simple UDP client and server task parameters. */ -#define mainSIMPLE_CLIENT_SERVER_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainSIMPLE_CLIENT_SERVER_PORT ( 5005UL ) -#define mainSIMPLE_CLIENT_SERVER_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE ) - -/* Select UDP server task parameters. */ -#define mainSELECT_SERVER_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainSELECT_SERVER_PORT ( 10001UL ) -#define mainSELECT_SERVER_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE ) - -/* Echo client task parameters. */ -#define mainECHO_CLIENT_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) -#define mainECHO_CLIENT_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* Set the following constants to 1 or 0 to define which tasks to include and -exclude. */ -#define mainCREATE_UDP_CLI_TASKS 1 -#define mainCREATE_SIMPLE_UDP_CLIENT_SERVER_TASKS 0 -#define mainCREATE_SELECT_UDP_SERVER_TASKS 0 -#define mainCREATE_UDP_ECHO_TASKS 1 - -/*-----------------------------------------------------------*/ - -/* - * Register commands that can be used with FreeRTOS+CLI through the UDP socket. - * The commands are defined in CLI-commands.c. - */ -extern void vRegisterCLICommands( void ); - -/* The default IP and MAC address used by the demo. The address configuration -defined here will be used if ipconfigUSE_DHCP is 0, or if ipconfigUSE_DHCP is -1 but a DHCP server could not be contacted. See the online documentation for -more information. */ -static const uint8_t ucIPAddress[ 4 ] = { configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 }; -static const uint8_t ucNetMask[ 4 ] = { configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 }; -static const uint8_t ucGatewayAddress[ 4 ] = { configGATEWAY_ADDR0, configGATEWAY_ADDR1, configGATEWAY_ADDR2, configGATEWAY_ADDR3 }; -static const uint8_t ucDNSServerAddress[ 4 ] = { configDNS_SERVER_ADDR0, configDNS_SERVER_ADDR1, configDNS_SERVER_ADDR2, configDNS_SERVER_ADDR3 }; - -/* Default MAC address configuration. The demo creates a virtual network -connection that uses this MAC address by accessing the raw Ethernet data -to and from a real network connection on the host PC. See the -configNETWORK_INTERFACE_TO_USE definition for information on how to configure -the real network connection to use. */ -const uint8_t ucMACAddress[ 6 ] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 }; - -/* Used to guard prints to the console. */ -static xSemaphoreHandle xConsoleMutex = NULL; - -/*-----------------------------------------------------------*/ - - - -/****************************************************************************** - * - * See the following web page for information on using this demo. - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_CLI_Windows_Simulator.shtml - * - ******************************************************************************/ - - -int main( void ) -{ -const uint32_t ulLongTime_ms = 250UL; - - /* Create a mutex that is used to guard against the console being accessed - by more than one task simultaniously. */ - xConsoleMutex = xSemaphoreCreateMutex(); - - /* Initialise the network interface. Tasks that use the network are - created in the network event hook when the network is connected and ready - for use. The address values passed in here are used if ipconfigUSE_DHCP is - set to 0, or if ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be - contacted. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); - - /* Register commands with the FreeRTOS+CLI command interpreter. */ - vRegisterCLICommands(); - - /* Start the RTOS scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details (this is standard text that is not - really applicable to the Win32 simulator port). */ - for( ;; ) - { - Sleep( ulLongTime_ms ); - } -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ -const unsigned long ulMSToSleep = 5; - - /* This function is called on each cycle of the idle task if - configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h. Sleep to reduce CPU - load. */ - Sleep( ulMSToSleep ); -} -/*-----------------------------------------------------------*/ - -void vAssertCalled( void ) -{ -const unsigned long ulLongSleep = 1000UL; -volatile uint32_t ulBlockVariable = 0UL; - - /* Setting ulBlockVariable to a non-zero value in the debugger will allow - this function to be exited. */ - taskDISABLE_INTERRUPTS(); - { - while( ulBlockVariable == 0UL ) - { - Sleep( ulLongSleep ); - } - } - taskENABLE_INTERRUPTS(); -} -/*-----------------------------------------------------------*/ - -void vOutputString( char *pcMessage ) -{ - /* Wrap the standard windows console output (as opposed to the FreeRTOS+CLI - console) with a mutex to ensure it can only be accessed by one task at a - time. */ - xSemaphoreTake( xConsoleMutex, portMAX_DELAY ); - printf( pcMessage ); - xSemaphoreGive( xConsoleMutex ); -} -/*-----------------------------------------------------------*/ - -/* Called by FreeRTOS+UDP when the network connects. */ -void vApplicationIPNetworkEventHook( eIPCallbackEvent_t eNetworkEvent ) -{ -uint32_t ulIPAddress, ulNetMask, ulGatewayAddress, ulDNSServerAddress; -int8_t cBuffer[ 16 ]; -static BaseType_t xTasksAlreadyCreated = pdFALSE; - - if( eNetworkEvent == eNetworkUp ) - { - /* Create the tasks that use the IP stack if they have not already been - created. */ - if( xTasksAlreadyCreated == pdFALSE ) - { - #if( mainCREATE_SIMPLE_UDP_CLIENT_SERVER_TASKS == 1 ) - { - /* Create tasks that demonstrate sending and receiving in both - standard and zero copy mode. */ - vStartSimpleUDPClientServerTasks( mainSIMPLE_CLIENT_SERVER_TASK_STACK_SIZE, mainSIMPLE_CLIENT_SERVER_PORT, mainSIMPLE_CLIENT_SERVER_TASK_PRIORITY ); - } - #endif /* mainCREATE_SIMPLE_UDP_CLIENT_SERVER_TASKS */ - - #if( mainCREATE_SELECT_UDP_SERVER_TASKS == 1 ) - { - /* Create tasks that demonstrate sending and receiving in both - standard and zero copy mode. */ - vStartSelectUDPServerTasks( mainSELECT_SERVER_TASK_STACK_SIZE, mainSELECT_SERVER_PORT, mainSELECT_SERVER_TASK_PRIORITY ); - } - #endif /* mainCREATE_SIMPLE_UDP_CLIENT_SERVER_TASKS */ - - - #if( mainCREATE_UDP_ECHO_TASKS == 1 ) - { - /* Create the tasks that transmit to and receive from a standard - echo server (see the web documentation for this port) in both - standard and zero copy mode. */ - vStartEchoClientTasks( mainECHO_CLIENT_TASK_STACK_SIZE, mainECHO_CLIENT_TASK_PRIORITY ); - } - #endif /* mainCREATE_UDP_ECHO_TASKS */ - - #if( mainCREATE_UDP_CLI_TASKS == 1 ) - { - /* Create the task that handles the CLI on a UDP port. The port number - is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */ - vStartUDPCommandInterpreterTask( mainUDP_CLI_TASK_STACK_SIZE, mainUDP_CLI_PORT_NUMBER, mainUDP_CLI_TASK_PRIORITY ); - } - #endif /* mainCREATE_UDP_CLI_TASKS */ - - xTasksAlreadyCreated = pdTRUE; - } - - /* Print out the network configuration, which may have come from a DHCP - server. */ - FreeRTOS_GetAddressConfiguration( &ulIPAddress, &ulNetMask, &ulGatewayAddress, &ulDNSServerAddress ); - vOutputString( "IP Address: " ); - FreeRTOS_inet_ntoa( ulIPAddress, cBuffer ); - vOutputString( ( char * ) cBuffer ); - vOutputString( "\r\nSubnet Mask: " ); - FreeRTOS_inet_ntoa( ulNetMask, cBuffer ); - vOutputString( ( char * ) cBuffer ); - vOutputString( "\r\nGateway Address: " ); - FreeRTOS_inet_ntoa( ulGatewayAddress, cBuffer ); - vOutputString( ( char * ) cBuffer ); - vOutputString( "\r\nDNS Server Address: " ); - FreeRTOS_inet_ntoa( ulDNSServerAddress, cBuffer ); - vOutputString( ( char * ) cBuffer ); - vOutputString( "\r\n\r\n" ); - } -} -/*-----------------------------------------------------------*/ - -/* Called automatically when a reply to an outgoing ping is received. */ -void vApplicationPingReplyHook( ePingReplyStatus_t eStatus, uint16_t usIdentifier ) -{ -static const uint8_t *pcSuccess = ( uint8_t * ) "Ping reply received - "; -static const uint8_t *pcInvalidChecksum = ( uint8_t * ) "Ping reply received with invalid checksum - "; -static const uint8_t *pcInvalidData = ( uint8_t * ) "Ping reply received with invalid data - "; -static uint8_t cMessage[ 50 ]; - - - switch( eStatus ) - { - case eSuccess : - vOutputString( ( char * ) pcSuccess ); - break; - - case eInvalidChecksum : - vOutputString( ( char * ) pcInvalidChecksum ); - break; - - case eInvalidData : - vOutputString( ( char * ) pcInvalidData ); - break; - - default : - /* It is not possible to get here as all enums have their own - case. */ - break; - } - - sprintf( ( char * ) cMessage, "identifier %d\r\n", ( int ) usIdentifier ); - vOutputString( ( char * ) cMessage ); -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the - size of the heap available to pvPortMalloc() is defined by - configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() - API function can be used to query the size of free heap space that remains - (although it does not provide information on how the remaining heap might - be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DHCP.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DHCP.c deleted file mode 100644 index 752e5dcdf..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DHCP.c +++ /dev/null @@ -1,728 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "timers.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_DHCP.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkInterface.h" -#include "IPTraceMacroDefaults.h" - -/* Exclude the entire file if DHCP is not enabled. */ -#if ipconfigUSE_DHCP != 0 - -#if ( ipconfigUSE_DHCP != 0 ) && ( ipconfigNETWORK_MTU < 586 ) - /* DHCP must be able to receive an options field of 312 bytes, the fixed - part of the DHCP packet is 240 bytes, and the IP/UDP headers take 28 bytes. */ - #error ipconfigNETWORK_MTU needs to be at least 586 to use DHCP (588 if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 1) -#endif - -/* Parameter widths in the DHCP packet. */ -#define dhcpCLIENT_HARDWARE_ADDRESS_LENGTH 16 -#define dhcpSERVER_HOST_NAME_LENGTH 64 -#define dhcpBOOT_FILE_NAME_LENGTH 128 - -/* Timer parameters. Windows simulator times are much shorter because simulated -time is not real time. */ -#ifdef _WINDOWS_ - #define dhcpINITIAL_DHCP_TX_PERIOD ( 100 / portTICK_RATE_MS ) - #define dhcpINITIAL_TIMER_PERIOD ( 10 / portTICK_RATE_MS ) - #define dhcpMAX_TIME_TO_WAIT_FOR_ACK ( 200 / portTICK_RATE_MS ) -#else - #define dhcpINITIAL_DHCP_TX_PERIOD ( 5000 / portTICK_RATE_MS ) - #define dhcpINITIAL_TIMER_PERIOD ( 250 / portTICK_RATE_MS ) - #define dhcpMAX_TIME_TO_WAIT_FOR_ACK ( 5000 / portTICK_RATE_MS ) -#endif /* _WINDOWS_ */ - -/* Codes of interest found in the DHCP options field. */ -#define dhcpSUBNET_MASK_OPTION_CODE ( 1 ) -#define dhcpGATEWAY_OPTION_CODE ( 3 ) -#define hdcpDNS_SERVER_OPTIONS_CODE ( 6 ) -#define dhcpMESSAGE_TYPE_OPTION_CODE ( 53 ) -#define dhcpLEASE_TIME_OPTION_CODE ( 51 ) -#define dhcpCLIENT_IDENTIFIER_OPTION_CODE ( 61 ) -#define dhcpPARAMETER_REQUEST_OPTION_CODE ( 55 ) -#define dhcpREQUEST_IP_ADDRESS_OPTION_CODE ( 50 ) -#define dhcpSERVER_IP_ADDRESS_OPTION_CODE ( 54 ) - -/* The four DHCP message types of interest. */ -#define dhcpMESSAGE_TYPE_DISCOVER ( 1 ) -#define dhcpMESSAGE_TYPE_OFFER ( 2 ) -#define dhcpMESSAGE_TYPE_REQUEST ( 3 ) -#define dhcpMESSAGE_TYPE_ACK ( 5 ) -#define dhcpMESSAGE_TYPE_NACK ( 6 ) - -/* Offsets into the transmitted DHCP options fields at which various parameters -are located. */ -#define dhcpCLIENT_IDENTIFIER_OFFSET ( 5 ) -#define dhcpREQUESTED_IP_ADDRESS_OFFSET ( 13 ) -#define dhcpDHCP_SERVER_IP_ADDRESS_OFFSET ( 19 ) - -/* Values used in the DHCP packets. */ -#define dhcpREQUEST_OPCODE ( 1 ) -#define dhcpREPLY_OPCODE ( 2 ) -#define dhcpADDRESS_TYPE_ETHERNET ( 1 ) -#define dhcpETHERNET_ADDRESS_LENGTH ( 6 ) - -/* If a lease time is not received, use the default of two days. */ -#define dhcpDEFAULT_LEASE_TIME ( ( 48UL * 60UL * 60UL * 1000UL ) / portTICK_RATE_MS ) /* 48 hours in ticks. */ - -/* Don't allow the lease time to be too short. */ -#define dhcpMINIMUM_LEASE_TIME ( 60000UL / portTICK_RATE_MS ) /* 60 seconds in ticks. */ - -/* Marks the end of the variable length options field in the DHCP packet. */ -#define dhcpOPTION_END_BYTE 0xff - -/* Offset into a DHCP message at which the first byte of the options is -located. */ -#define dhcpFIRST_OPTION_BYTE_OFFSET ( 0xf0 ) - -/* When walking the variable length options field, the following value is used -to ensure the walk has not gone past the end of the valid options. 2 bytes is -made up of the length byte, and minimum one byte value. */ -#define dhcpMAX_OPTION_LENGTH_OF_INTEREST ( 2L ) - -/* Standard DHCP port numbers and magic cookie value. */ -#if( ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN ) - #define dhcpCLIENT_PORT 0x4400 - #define dhcpSERVER_PORT 0x4300 - #define dhcpCOOKIE 0x63538263 - #define dhcpBROADCAST 0x0080 -#else - #define dhcpCLIENT_PORT 0x0044 - #define dhcpSERVER_PORT 0x0043 - #define dhcpCOOKIE 0x63825363 - #define dhcpBROADCAST 0x8000 -#endif /* ipconfigBYTE_ORDER */ - -#include "pack_struct_start.h" -struct xDHCPMessage -{ - uint8_t ucOpcode; - uint8_t ucAddressType; - uint8_t ucAddressLength; - uint8_t ucHops; - uint32_t ulTransactionID; - uint16_t usElapsedTime; - uint16_t usFlags; - uint32_t ulClientIPAddress_ciaddr; - uint32_t ulYourIPAddress_yiaddr; - uint32_t ulServerIPAddress_siaddr; - uint32_t ulRelayAgentIPAddress_giaddr; - uint8_t ucClientHardwareAddress[ dhcpCLIENT_HARDWARE_ADDRESS_LENGTH ]; - uint8_t ucServerHostName[ dhcpSERVER_HOST_NAME_LENGTH ]; - uint8_t ucBootFileName[ dhcpBOOT_FILE_NAME_LENGTH ]; - uint32_t ulDHCPCookie; - uint8_t ucFirstOptionByte; -} -#include "pack_struct_end.h" -typedef struct xDHCPMessage xDHCPMessage_t; - -/* DHCP state machine states. */ -typedef enum -{ - eWaitingSendFirstDiscover = 0, /* Initial state. Send a discover the first time it is called, and reset all timers. */ - eWaitingOffer, /* Either resend the discover, or, if the offer is forthcoming, send a request. */ - eWaitingAcknowledge, /* Either resend the request. */ - eLeasedAddress, /* Resend the request at the appropriate time to renew the lease. */ - eNotUsingLeasedAddress /* DHCP failed, and a default IP address is being used. */ -} eDHCPState_t; - -/* - * Generate a DHCP discover message and send it on the DHCP socket. - */ -static void prvSendDHCPDiscover( xMACAddress_t *pxMACAddress ); - -/* - * Interpret message received on the DHCP socket. - */ -static BaseType_t prvProcessDHCPReplies( uint8_t ucExpectedMessageType, xMACAddress_t *pxMACAddress, xNetworkAddressingParameters_t *pxNetworkAddressing ); - -/* - * Generate a DHCP request packet, and send it on the DHCP socket. - */ -static void prvSendDHCPRequest( xMACAddress_t *pxMACAddress ); - -/* - * Prepare to start a DHCP transaction. This initialises some state variables - * and creates the DHCP socket if necessary. - */ -static void prvInitialiseDHCP( void ); - -/* - * Creates the part of outgoing DHCP messages that are common to all outgoing - * DHCP messages. - */ -static uint8_t *prvCreatePartDHCPMessage( struct freertos_sockaddr *pxAddress, xMACAddress_t *pxMACAddress, uint8_t ucOpcode, const uint8_t * const pucOptionsArray, size_t xOptionsArraySize ); - -/* - * Create the DHCP socket, if it has not been created already. - */ -static void prvCreateDHCPSocket( void ); - -/*-----------------------------------------------------------*/ - -/* The timer used to drive the DHCP state machine. */ -static xTimerHandle xDHCPTimer = NULL; - -/* The UDP socket used for all incoming and outgoing DHCP traffic. */ -static xSocket_t xDHCPSocket = NULL; - -/* Hold information in between steps in the DHCP state machine. */ -static uint32_t ulTransactionId = 0UL, ulOfferedIPAddress = 0UL, ulDHCPServerAddress = 0UL, ulLeaseTime = 0; - -/* Hold information on the current timer state. */ -static TickType_t xDHCPTxTime = 0x00, xDHCPTxPeriod = 0x00; - -/* Maintains the DHCP state machine state. */ -static eDHCPState_t eDHCPState = eWaitingSendFirstDiscover; - -/*-----------------------------------------------------------*/ - -void vDHCPProcess( BaseType_t xReset, xMACAddress_t *pxMACAddress, uint32_t *pulIPAddress, xNetworkAddressingParameters_t *pxNetworkAddressing ) -{ - if( xReset != pdFALSE ) - { - eDHCPState = eWaitingSendFirstDiscover; - } - - switch( eDHCPState ) - { - case eWaitingSendFirstDiscover : - - /* Initial state. Create the DHCP socket, timer, etc. if they - have not already been created. */ - prvInitialiseDHCP(); - *pulIPAddress = 0UL; - - /* Send the first discover request. */ - if( xDHCPSocket != NULL ) - { - xDHCPTxTime = xTaskGetTickCount(); - prvSendDHCPDiscover( pxMACAddress ); - eDHCPState = eWaitingOffer; - } - break; - - case eWaitingOffer : - - /* Look for offers coming in. */ - if( prvProcessDHCPReplies( dhcpMESSAGE_TYPE_OFFER, pxMACAddress, pxNetworkAddressing ) == pdPASS ) - { - /* An offer has been made, generate the request. */ - xDHCPTxTime = xTaskGetTickCount(); - xDHCPTxPeriod = dhcpINITIAL_DHCP_TX_PERIOD; - prvSendDHCPRequest( pxMACAddress ); - eDHCPState = eWaitingAcknowledge; - } - else - { - /* Is it time to send another Discover? */ - if( ( xTaskGetTickCount() - xDHCPTxTime ) > xDHCPTxPeriod ) - { - /* Increase the time period, and if it has not got to the - point of giving up - send another discovery. */ - xDHCPTxPeriod <<= 1; - if( xDHCPTxPeriod <= ipconfigMAXIMUM_DISCOVER_TX_PERIOD ) - { - ulTransactionId++; - xDHCPTxTime = xTaskGetTickCount(); - prvSendDHCPDiscover( pxMACAddress ); - } - else - { - /* Revert to static IP address. */ - taskENTER_CRITICAL(); - { - *pulIPAddress = pxNetworkAddressing->ulDefaultIPAddress; - iptraceDHCP_REQUESTS_FAILED_USING_DEFAULT_IP_ADDRESS( pxNetworkAddressing->ulDefaultIPAddress ); - } - taskEXIT_CRITICAL(); - eDHCPState = eNotUsingLeasedAddress; - xTimerStop( xDHCPTimer, ( TickType_t ) 0 ); - - #if ipconfigUSE_NETWORK_EVENT_HOOK == 1 - { - vApplicationIPNetworkEventHook( eNetworkUp ); - } - #endif - - /* Static configuration is being used, so the network is now up. */ - #if ipconfigFREERTOS_PLUS_NABTO == 1 - { - /* Return value is used in configASSERT() inside the - function. */ - ( void ) xStartNabtoTask(); - } - #endif /* ipconfigFREERTOS_PLUS_NABTO */ - - /* Close socket to ensure packets don't queue on it. */ - FreeRTOS_closesocket( xDHCPSocket ); - xDHCPSocket = NULL; - } - } - } - break; - - case eWaitingAcknowledge : - - /* Look for acks coming in. */ - if( prvProcessDHCPReplies( dhcpMESSAGE_TYPE_ACK, pxMACAddress, pxNetworkAddressing ) == pdPASS ) - { - /* DHCP completed. The IP address can now be used, and the - timer set to the lease timeout time. */ - *pulIPAddress = ulOfferedIPAddress; - eDHCPState = eLeasedAddress; - - #if ipconfigUSE_NETWORK_EVENT_HOOK == 1 - { - vApplicationIPNetworkEventHook( eNetworkUp ); - } - #endif - - /* Static configuration is being used, so the network is now - up. */ - #if ipconfigFREERTOS_PLUS_NABTO == 1 - { - /* Return value is used in configASSERT() inside the - function. */ - ( void ) xStartNabtoTask(); - } - #endif /* ipconfigFREERTOS_PLUS_NABTO */ - - /* Close socket to ensure packets don't queue on it. */ - FreeRTOS_closesocket( xDHCPSocket ); - xDHCPSocket = NULL; - - if( ulLeaseTime == 0UL ) - { - ulLeaseTime = dhcpDEFAULT_LEASE_TIME; - } - else if( ulLeaseTime < dhcpMINIMUM_LEASE_TIME ) - { - ulLeaseTime = dhcpMINIMUM_LEASE_TIME; - } - else - { - /* The lease time is already valid. */ - } - - xTimerChangePeriod( xDHCPTimer, ulLeaseTime, portMAX_DELAY ); - } - else - { - /* Is it time to send another Discover? */ - if( ( xTaskGetTickCount() - xDHCPTxTime ) > xDHCPTxPeriod ) - { - /* Increase the time period, and if it has not got to the - point of giving up - send another request. */ - xDHCPTxPeriod <<= 1; - if( xDHCPTxPeriod <= ipconfigMAXIMUM_DISCOVER_TX_PERIOD ) - { - xDHCPTxTime = xTaskGetTickCount(); - prvSendDHCPRequest( pxMACAddress ); - } - else - { - /* Give up, start again. */ - eDHCPState = eWaitingSendFirstDiscover; - } - } - } - break; - - case eLeasedAddress : - - /* Resend the request at the appropriate time to renew the lease. */ - prvCreateDHCPSocket(); - if( xDHCPSocket != NULL ) - { - xDHCPTxTime = xTaskGetTickCount(); - xDHCPTxPeriod = dhcpINITIAL_DHCP_TX_PERIOD; - prvSendDHCPRequest( pxMACAddress ); - eDHCPState = eWaitingAcknowledge; - } - xTimerChangePeriod( xDHCPTimer, dhcpINITIAL_TIMER_PERIOD, portMAX_DELAY ); - break; - - case eNotUsingLeasedAddress: - xTimerStop( xDHCPTimer, ( TickType_t ) 0 ); - break; - } -} -/*-----------------------------------------------------------*/ - -static void prvCreateDHCPSocket( void ) -{ -struct freertos_sockaddr xAddress; -BaseType_t xReturn; -TickType_t xTimeoutTime = 0; - - /* Create the socket, if it has not already been created. */ - if( xDHCPSocket == NULL ) - { - xDHCPSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - configASSERT( ( xDHCPSocket != FREERTOS_INVALID_SOCKET ) ); - - /* Ensure the Rx and Tx timeouts are zero as the DHCP executes in the - context of the IP task. */ - FreeRTOS_setsockopt( xDHCPSocket, 0, FREERTOS_SO_RCVTIMEO, ( void * ) &xTimeoutTime, sizeof( TickType_t ) ); - FreeRTOS_setsockopt( xDHCPSocket, 0, FREERTOS_SO_SNDTIMEO, ( void * ) &xTimeoutTime, sizeof( TickType_t ) ); - - /* Bind to the standard DHCP client port. */ - xAddress.sin_port = dhcpCLIENT_PORT; - xReturn = FreeRTOS_bind( xDHCPSocket, &xAddress, sizeof( xAddress ) ); - configASSERT( xReturn == 0 ); - - /* Remove compiler warnings if configASSERT() is not defined. */ - ( void ) xReturn; - } -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseDHCP( void ) -{ -extern void vIPFunctionsTimerCallback( xTimerHandle xTimer ); - - /* Initialise the parameters that will be set by the DHCP process. */ - if( ulTransactionId == 0 ) - { - ulTransactionId = ipconfigRAND32(); - } - else - { - ulTransactionId++; - } - ulOfferedIPAddress = 0UL; - ulDHCPServerAddress = 0UL; - xDHCPTxPeriod = dhcpINITIAL_DHCP_TX_PERIOD; - - /* Create the DHCP socket if it has not already been created. */ - prvCreateDHCPSocket(); - - if( xDHCPTimer == NULL ) - { - xDHCPTimer = xTimerCreate( "DHCP", dhcpINITIAL_TIMER_PERIOD, pdTRUE, ( void * ) eDHCPEvent, vIPFunctionsTimerCallback ); - configASSERT( xDHCPTimer ); - xTimerStart( xDHCPTimer, portMAX_DELAY ); - } - else - { - xTimerChangePeriod( xDHCPTimer, dhcpINITIAL_TIMER_PERIOD, portMAX_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static BaseType_t prvProcessDHCPReplies( uint8_t ucExpectedMessageType, xMACAddress_t *pxMACAddress, xNetworkAddressingParameters_t *pxNetworkAddressing ) -{ -uint8_t *pucUDPPayload, *pucLastByte; -struct freertos_sockaddr xClient; -uint32_t xClientLength = sizeof( xClient ); -int32_t lBytes; -xDHCPMessage_t *pxDHCPMessage; -uint8_t *pucByte, ucOptionCode, ucLength; -uint32_t ulProcessed; -BaseType_t xReturn = pdFALSE; -const uint32_t ulMandatoryOptions = 2; /* DHCP server address, and the correct DHCP message type must be present in the options. */ - - lBytes = FreeRTOS_recvfrom( xDHCPSocket, ( void * ) &pucUDPPayload, 0, FREERTOS_ZERO_COPY, &xClient, &xClientLength ); - - if( lBytes > 0 ) - { - /* Map a DHCP structure onto the received data. */ - pxDHCPMessage = ( xDHCPMessage_t * ) ( pucUDPPayload ); - - /* Sanity check. */ - if( ( pxDHCPMessage->ulDHCPCookie == dhcpCOOKIE ) && ( pxDHCPMessage->ucOpcode == dhcpREPLY_OPCODE ) && ( pxDHCPMessage->ulTransactionID == ulTransactionId ) ) - { - if( memcmp( ( void * ) &( pxDHCPMessage->ucClientHardwareAddress ), ( void * ) pxMACAddress, sizeof( xMACAddress_t ) ) == 0 ) - { - /* None of the essential options have been processed yet. */ - ulProcessed = 0; - - /* Walk through the options until the dhcpOPTION_END_BYTE byte - is found, taking care not to walk off the end of the options. */ - pucByte = &( pxDHCPMessage->ucFirstOptionByte ); - pucLastByte = &( pucUDPPayload[ lBytes - dhcpMAX_OPTION_LENGTH_OF_INTEREST ] ); - while( ( *pucByte != dhcpOPTION_END_BYTE ) && ( pucByte < pucLastByte ) ) - { - ucOptionCode = *pucByte; - pucByte++; - ucLength = *pucByte; - pucByte++; - - switch( ucOptionCode ) - { - case dhcpMESSAGE_TYPE_OPTION_CODE : - - if( *pucByte == ucExpectedMessageType ) - { - /* The message type is the message type the - state machine is expecting. */ - ulProcessed++; - } - else if( *pucByte == dhcpMESSAGE_TYPE_NACK ) - { - if( ucExpectedMessageType == dhcpMESSAGE_TYPE_ACK ) - { - /* Start again. */ - eDHCPState = eWaitingSendFirstDiscover; - } - } - else - { - /* Don't process other message types. */ - } - break; - - case dhcpSUBNET_MASK_OPTION_CODE : - - if( ucLength == sizeof( uint32_t ) ) - { - memcpy( ( void * ) &( pxNetworkAddressing->ulNetMask ), ( void * ) pucByte, ( size_t ) ucLength ); - } - break; - - case dhcpGATEWAY_OPTION_CODE : - - if( ucLength == sizeof( uint32_t ) ) - { - /* ulProcessed is not incremented in this case - because the gateway is not essential. */ - memcpy( ( void * ) &( pxNetworkAddressing->ulGatewayAddress ), ( void * ) pucByte, ( size_t ) ucLength ); - } - break; - - case hdcpDNS_SERVER_OPTIONS_CODE : - - /* ulProcessed is not incremented in this case - because the DNS server is not essential. Only the - first DNS server address is taken. */ - memcpy( ( void * ) &( pxNetworkAddressing->ulDNSServerAddress ), ( void * ) pucByte, sizeof( uint32_t ) ); - break; - - case dhcpSERVER_IP_ADDRESS_OPTION_CODE : - - if( ucLength == sizeof( uint32_t ) ) - { - if( ucExpectedMessageType == dhcpMESSAGE_TYPE_OFFER ) - { - /* Offers state the replying server. */ - ulProcessed++; - memcpy( ( void * ) &ulDHCPServerAddress, ( void * ) pucByte, ( size_t ) ucLength ); - } - else - { - /* The ack must come from the expected server. */ - if( memcmp( ( void * ) &ulDHCPServerAddress, ( void * ) pucByte, ( size_t ) ucLength ) == 0 ) - { - ulProcessed++; - } - } - } - break; - - case dhcpLEASE_TIME_OPTION_CODE : - - if( ucLength == sizeof( &ulLeaseTime ) ) - { - /* ulProcessed is not incremented in this case - because the lease time is not essential. */ - memcpy( ( void * ) &ulLeaseTime, ( void * ) pucByte, ( size_t ) ucLength ); - ulLeaseTime = FreeRTOS_ntohl( ulLeaseTime ); - - /* Convert the lease time to milliseconds - (*1000) then ticks (/portTICK_RATE_MS). */ - ulLeaseTime *= ( 1000UL / portTICK_RATE_MS ); - - /* Divide the lease time to ensure a renew - request is sent before the lease actually - expires. */ - ulLeaseTime >>= 1UL; - } - break; - - default : - - /* Not interested in this field. */ - - break; - } - - /* Jump over the data to find the next option code. */ - if( ucLength == 0 ) - { - break; - } - else - { - pucByte += ucLength; - } - } - - /* Were all the mandatory options received? */ - if( ulProcessed == ulMandatoryOptions ) - { - ulOfferedIPAddress = pxDHCPMessage->ulYourIPAddress_yiaddr; - xReturn = pdPASS; - } - } - } - - FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayload ); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static uint8_t *prvCreatePartDHCPMessage( struct freertos_sockaddr *pxAddress, xMACAddress_t *pxMACAddress, uint8_t ucOpcode, const uint8_t * const pucOptionsArray, size_t xOptionsArraySize ) -{ -xDHCPMessage_t *pxDHCPMessage; -const size_t xRequiredBufferSize = sizeof( xDHCPMessage_t ) + xOptionsArraySize; -uint8_t *pucUDPPayloadBuffer; -static uint8_t ucUseBroadcastFlag = pdFALSE; - - /* Get a buffer. This uses a maximum delay, but the delay will be capped - to ipconfigMAX_SEND_BLOCK_TIME_TICKS so the return value still needs to be - test. */ - do - { - }while( ( pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xRequiredBufferSize, portMAX_DELAY ) ) == NULL ); - - pxDHCPMessage = ( xDHCPMessage_t * ) pucUDPPayloadBuffer; - - /* Most fields need to be zero. */ - memset( ( void * ) pxDHCPMessage, 0x00, sizeof( xDHCPMessage_t ) ); - - /* Create the message. */ - pxDHCPMessage->ucOpcode = ucOpcode; - pxDHCPMessage->ucAddressType = dhcpADDRESS_TYPE_ETHERNET; - pxDHCPMessage->ucAddressLength = dhcpETHERNET_ADDRESS_LENGTH; - pxDHCPMessage->ulTransactionID = ulTransactionId; - pxDHCPMessage->ulDHCPCookie = dhcpCOOKIE; - - /* For maximum possibility of success, alternate between broadcast and non - broadcast. */ - ucUseBroadcastFlag = !ucUseBroadcastFlag; - if( ucUseBroadcastFlag == pdTRUE ) - { - pxDHCPMessage->usFlags = dhcpBROADCAST; - } - else - { - pxDHCPMessage->usFlags = 0; - } - - memcpy( ( void * ) &( pxDHCPMessage->ucClientHardwareAddress[ 0 ] ), ( void * ) pxMACAddress, sizeof( xMACAddress_t ) ); - - /* Copy in the const part of the options options. */ - memcpy( ( void * ) &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET ] ), ( void * ) pucOptionsArray, xOptionsArraySize ); - - /* Map in the client identifier. */ - memcpy( ( void * ) &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET + dhcpCLIENT_IDENTIFIER_OFFSET ] ), ( void * ) pxMACAddress, sizeof( xMACAddress_t ) ); - - /* Set the addressing. */ - pxAddress->sin_addr = ipBROADCAST_IP_ADDRESS; - pxAddress->sin_port = ( uint16_t ) dhcpSERVER_PORT; - - return pucUDPPayloadBuffer; -} -/*-----------------------------------------------------------*/ - -static void prvSendDHCPRequest( xMACAddress_t *pxMACAddress ) -{ -uint8_t *pucUDPPayloadBuffer; -struct freertos_sockaddr xAddress; -static const uint8_t ucDHCPRequestOptions[] = -{ - /* Do not change the ordering without also changing - dhcpCLIENT_IDENTIFIER_OFFSET, dhcpREQUESTED_IP_ADDRESS_OFFSET and - dhcpDHCP_SERVER_IP_ADDRESS_OFFSET. */ - dhcpMESSAGE_TYPE_OPTION_CODE, 1, dhcpMESSAGE_TYPE_REQUEST, /* Message type option. */ - dhcpCLIENT_IDENTIFIER_OPTION_CODE, 6, 0, 0, 0, 0, 0, 0, /* Client identifier. */ - dhcpREQUEST_IP_ADDRESS_OPTION_CODE, 4, 0, 0, 0, 0, /* The IP address being requested. */ - dhcpSERVER_IP_ADDRESS_OPTION_CODE, 4, 0, 0, 0, 0, /* The IP address of the DHCP server. */ - dhcpOPTION_END_BYTE -}; - - pucUDPPayloadBuffer = prvCreatePartDHCPMessage( &xAddress, pxMACAddress, dhcpREQUEST_OPCODE, ucDHCPRequestOptions, sizeof( ucDHCPRequestOptions ) ); - - /* Copy in the IP address being requested. */ - memcpy( ( void * ) &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET + dhcpREQUESTED_IP_ADDRESS_OFFSET ] ), ( void * ) &ulOfferedIPAddress, sizeof( ulOfferedIPAddress ) ); - - /* Copy in the address of the DHCP server being used. */ - memcpy( ( void * ) &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET + dhcpDHCP_SERVER_IP_ADDRESS_OFFSET ] ), ( void * ) &ulDHCPServerAddress, sizeof( ulDHCPServerAddress ) ); - - iptraceSENDING_DHCP_REQUEST(); - if( FreeRTOS_sendto( xDHCPSocket, pucUDPPayloadBuffer, ( sizeof( xDHCPMessage_t ) + sizeof( ucDHCPRequestOptions ) ), FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) == 0 ) - { - /* The packet was not successfully queued for sending and must be - returned to the stack. */ - FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSendDHCPDiscover( xMACAddress_t *pxMACAddress ) -{ -uint8_t *pucUDPPayloadBuffer; -struct freertos_sockaddr xAddress; -static const uint8_t ucDHCPDiscoverOptions[] = -{ - /* Do not change the ordering without also changing dhcpCLIENT_IDENTIFIER_OFFSET. */ - dhcpMESSAGE_TYPE_OPTION_CODE, 1, dhcpMESSAGE_TYPE_DISCOVER, /* Message type option. */ - dhcpCLIENT_IDENTIFIER_OPTION_CODE, 6, 0, 0, 0, 0, 0, 0, /* Client identifier. */ - dhcpPARAMETER_REQUEST_OPTION_CODE, 3, dhcpSUBNET_MASK_OPTION_CODE, dhcpGATEWAY_OPTION_CODE, hdcpDNS_SERVER_OPTIONS_CODE, /* Parameter request option. */ - dhcpOPTION_END_BYTE -}; - - pucUDPPayloadBuffer = prvCreatePartDHCPMessage( &xAddress, pxMACAddress, dhcpREQUEST_OPCODE, ucDHCPDiscoverOptions, sizeof( ucDHCPDiscoverOptions ) ); - - iptraceSENDING_DHCP_DISCOVER(); - if( FreeRTOS_sendto( xDHCPSocket, pucUDPPayloadBuffer, ( sizeof( xDHCPMessage_t ) + sizeof( ucDHCPDiscoverOptions ) ), FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) == 0 ) - { - /* The packet was not successfully queued for sending and must be - returned to the stack. */ - FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer ); - } -} -/*-----------------------------------------------------------*/ - -#endif /* ipconfigUSE_DHCP != 0 */ - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DNS.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DNS.c deleted file mode 100644 index 20d06cfae..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DNS.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "timers.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_DNS.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkInterface.h" -#include "IPTraceMacroDefaults.h" - -/* Exclude the entire file if DNS is not enabled. */ -#if ipconfigUSE_DNS != 0 - -#if( ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN ) - #define dnsOUTGOING_FLAGS 0x0001 /* Standard query. */ - #define dnsTYPE 0x0100 /* A record (host address. */ - #define dnsCLASS 0x0100 /* IN */ - #define dnsDNS_PORT 0x3500 - #define dnsONE_QUESTION 0x0100 - #define dnsRX_FLAGS_MASK 0x0f80 /* The bits of interest in the flags field of incoming DNS messages. */ - #define dnsEXPECTED_RX_FLAGS 0x0080 /* Should be a response, without any errors. */ -#else - #define dnsDNS_PORT 0x35 - #define dnsONE_QUESTION 0x01 - #define dnsFLAG_QUERY_RESPONSE_BIT 0x8000 - #define dnsFLAG_OPERATION_CODE_BITS 0x7800 - #define dnsFLAG_TRUNCATION_BIT 0x0200 - #define dnsFLAG_RESPONSE_CODE_BITS 0x000f - #define dnsOUTGOING_FLAGS 0x0100 /* Standard query. */ - #define dnsTYPE 0x0001 /* A record (host address. */ - #define dnsCLASS 0x0001 /* IN */ - #define dnsRX_FLAGS_MASK 0x800f /* The bits of interest in the flags field of incoming DNS messages. */ - #define dnsEXPECTED_RX_FLAGS 0x8000 /* Should be a response, without any errors. */ -#endif /* ipconfigBYTE_ORDER */ - -/* The maximum number of times a DNS request should be sent out if a response -is not received, before giving up. */ -#define dnsMAX_REQUEST_ATTEMPTS 5 - -/* If the top two bits in the first character of a name field are set then the -name field is an offset to the string, rather than the string itself. */ -#define dnsNAME_IS_OFFSET ( ( uint8_t ) 0xc0 ) - -/* - * Create a socket and bind it to the standard DNS port number. Return the - * the created socket - or NULL if the socket could not be created or bound. - */ -static xSocket_t prvCreateDNSSocket( void ); - -/* - * Create the DNS message in the zero copy buffer passed in the first parameter. - */ -static size_t prvCreateDNSMessage( uint8_t *pucUDPPayloadBuffer, const char *pcHostName, uint16_t usIdentifier ); - -/* - * Simple routine that jumps over the NAME field of a resource record. - */ -static uint8_t *prvSkipNameField( uint8_t *pucByte ); - -/* - * Process a response packet from a DNS server. - */ -static uint32_t prvParseDNSReply( uint8_t *pucUDPPayloadBuffer, uint16_t usIdentifier ); - -/*-----------------------------------------------------------*/ - -#include "pack_struct_start.h" -struct xDNSMessage -{ - uint16_t usIdentifier; - uint16_t usFlags; - uint16_t usQuestions; - uint16_t usAnswers; - uint16_t usAuthorityRRs; - uint16_t usAdditionalRRs; -} -#include "pack_struct_end.h" -typedef struct xDNSMessage xDNSMessage_t; - -/*-----------------------------------------------------------*/ - -uint32_t FreeRTOS_gethostbyname( const char *pcHostName ) -{ -static uint16_t usIdentifier = 0; -struct freertos_sockaddr xAddress; -static xSocket_t xDNSSocket = NULL; -uint32_t ulIPAddress = 0UL; -uint8_t *pucUDPPayloadBuffer; -static uint32_t ulAddressLength; -BaseType_t xAttempt; -int32_t lBytes; -size_t xPayloadLength; -const size_t xExpectedPayloadLength = sizeof( xDNSMessage_t ) + strlen( pcHostName ) + sizeof( uint16_t ) + sizeof( uint16_t ) + 2; /* Two for the count of characters in the first subdomain part, and the string end byte */ - - if( xDNSSocket == NULL ) - { - xDNSSocket = prvCreateDNSSocket(); - } - - if( xDNSSocket != NULL ) - { - /* Generate a unique identifier for this query. */ - usIdentifier++; - - for( xAttempt = 0; xAttempt < dnsMAX_REQUEST_ATTEMPTS; xAttempt++ ) - { - /* Get a buffer. This uses a maximum delay, but the delay will be - capped to ipconfigMAX_SEND_BLOCK_TIME_TICKS so the return value - still needs to be tested. */ - pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xExpectedPayloadLength, portMAX_DELAY ); - if( pucUDPPayloadBuffer != NULL ) - { - /* Create the message in the obtained buffer. */ - xPayloadLength = prvCreateDNSMessage( pucUDPPayloadBuffer, pcHostName, usIdentifier ); - iptraceSENDING_DNS_REQUEST(); - - /* Obtain the DNS server address. */ - FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulIPAddress ); - - /* Send the DNS message. */ - xAddress.sin_addr = ulIPAddress; - xAddress.sin_port = dnsDNS_PORT; - ulIPAddress = 0; - - if( FreeRTOS_sendto( xDNSSocket, pucUDPPayloadBuffer, xPayloadLength, FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) != 0 ) - { - /* Wait for the reply. */ - lBytes = FreeRTOS_recvfrom( xDNSSocket, &pucUDPPayloadBuffer, 0, FREERTOS_ZERO_COPY, &xAddress, &ulAddressLength ); - - if( lBytes > 0 ) - { - /* The reply was received. Process it. */ - ulIPAddress = prvParseDNSReply( pucUDPPayloadBuffer, usIdentifier ); - - /* Finished with the buffer. The zero copy interface - is being used, so the buffer must be freed by the - task. */ - FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer ); - - if( ulIPAddress != 0 ) - { - /* All done. */ - break; - } - } - } - else - { - /* The message was not sent so the stack will not be - releasing the zero copy - it must be released here. */ - FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer ); - } - } - } - } - - return ulIPAddress; -} -/*-----------------------------------------------------------*/ - -static size_t prvCreateDNSMessage( uint8_t *pucUDPPayloadBuffer, const char *pcHostName, uint16_t usIdentifier ) -{ -xDNSMessage_t *pxDNSMessageHeader; -uint8_t *pucStart, *pucByte; -const uint16_t usARecordType = dnsTYPE, usClass = dnsCLASS; -static const xDNSMessage_t xDefaultPartDNSHeader = -{ - 0, /* The identifier will be overwritten. */ - dnsOUTGOING_FLAGS, /* Flags set for standard query. */ - dnsONE_QUESTION, /* One question is being asked. */ - 0, /* No replies are included. */ - 0, /* No authorities. */ - 0 /* No additional authorities. */ -}; - - /* Copy in the const part of the header. */ - memcpy( ( void * ) pucUDPPayloadBuffer, ( void * ) &xDefaultPartDNSHeader, sizeof( xDefaultPartDNSHeader ) ); - - /* Write in a unique identifier. */ - pxDNSMessageHeader = ( xDNSMessage_t * ) pucUDPPayloadBuffer; - pxDNSMessageHeader->usIdentifier = usIdentifier; - - /* Create the resource record at the end of the header. First - find the end of the header. */ - pucStart = pucUDPPayloadBuffer + sizeof( xDefaultPartDNSHeader ); - - /* Leave a gap for the first length bytes. */ - pucByte = pucStart + 1; - - /* Copy in the host name. */ - strcpy( ( char * ) pucByte, pcHostName ); - - /* Mark the end of the string. */ - pucByte += strlen( pcHostName ); - *pucByte = 0x00; - - /* Walk the string to replace the '.' characters with byte counts. - pucStart holds the address of the byte count. Walking the string - starts after the byte count position. */ - pucByte = pucStart; - - do - { - pucByte++; - - while( ( *pucByte != 0x00 ) && ( *pucByte != '.' ) ) - { - pucByte++; - } - - /* Fill in the byte count, then move the pucStart pointer up to - the found byte position. */ - *pucStart = ( uint8_t ) ( ( uint32_t ) pucByte - ( uint32_t ) pucStart ); - ( *pucStart )--; - - pucStart = pucByte; - - } while( *pucByte != 0x00 ); - - /* Finish off the record. */ - pucByte++; - memcpy( ( void * ) pucByte, &usARecordType, sizeof( uint16_t ) ); - pucByte += sizeof( uint16_t ); - memcpy( ( void * ) pucByte, &usClass, sizeof( uint16_t ) ); - pucByte += sizeof( uint16_t ); - - /* Return the total size of the generated message, which is the space from - the last written byte to the beginning of the buffer. */ - return ( ( uint32_t ) pucByte - ( uint32_t ) pucUDPPayloadBuffer ); -} -/*-----------------------------------------------------------*/ - -static uint8_t *prvSkipNameField( uint8_t *pucByte ) -{ - /* Determine if the name is the fully coded name, or an offset to the name - elsewhere in the message. */ - if( ( *pucByte & dnsNAME_IS_OFFSET ) == dnsNAME_IS_OFFSET ) - { - /* Jump over the two byte offset. */ - pucByte += sizeof( uint16_t ); - - } - else - { - /* pucByte points to the full name. Walk over the string. */ - while( *pucByte != 0x00 ) - { - /* The number of bytes to jump for each name section is stored in the byte - before the name section. */ - pucByte += ( *pucByte + 1 ); - } - - pucByte++; - } - - return pucByte; -} -/*-----------------------------------------------------------*/ - -static uint32_t prvParseDNSReply( uint8_t *pucUDPPayloadBuffer, uint16_t usIdentifier ) -{ -xDNSMessage_t *pxDNSMessageHeader; -uint32_t ulIPAddress = 0UL; -uint8_t *pucByte; -uint16_t x, usDataLength; -const uint16_t usARecordType = dnsTYPE; - - pxDNSMessageHeader = ( xDNSMessage_t * ) pucUDPPayloadBuffer; - - if( pxDNSMessageHeader->usIdentifier == usIdentifier ) - { - if( ( pxDNSMessageHeader->usFlags & dnsRX_FLAGS_MASK ) == dnsEXPECTED_RX_FLAGS ) - { - /* Start at the first byte after the header. */ - pucByte = pucUDPPayloadBuffer + sizeof( xDNSMessage_t ); - - /* Skip any question records. */ - pxDNSMessageHeader->usQuestions = FreeRTOS_ntohs( pxDNSMessageHeader->usQuestions ); - for( x = 0; x < pxDNSMessageHeader->usQuestions; x++ ) - { - /* Skip the variable length name field. */ - pucByte = prvSkipNameField( pucByte ); - - /* Skip the type and class fields. */ - pucByte += sizeof( uint32_t ); - } - - /* Search through the answers records. */ - pxDNSMessageHeader->usAnswers = FreeRTOS_ntohs( pxDNSMessageHeader->usAnswers ); - for( x = 0; x < pxDNSMessageHeader->usAnswers; x++ ) - { - pucByte = prvSkipNameField( pucByte ); - - /* Is the type field that of an A record? */ - if( memcmp( ( void * ) pucByte, ( void * ) &usARecordType, sizeof( uint16_t ) ) == 0 ) - { - /* This is the required record. Skip the type, class, and - time to live fields, plus the first byte of the data - length. */ - pucByte += ( sizeof( uint32_t ) + sizeof( uint32_t ) + sizeof( uint8_t ) ); - - /* Sanity check the data length. */ - if( *pucByte == sizeof( uint32_t ) ) - { - /* Skip the second byte of the length. */ - pucByte++; - - /* Copy the IP address out of the record. */ - memcpy( ( void * ) &ulIPAddress, ( void * ) pucByte, sizeof( uint32_t ) ); - } - - break; - } - else - { - /* Skip the type, class and time to live fields. */ - pucByte += ( sizeof( uint32_t ) + sizeof( uint32_t ) ); - - /* Determine the length of the data in the field. */ - memcpy( ( void * ) &usDataLength, ( void * ) pucByte, sizeof( uint16_t ) ); - usDataLength = FreeRTOS_ntohs( usDataLength ); - - /* Jump over the data lenth bytes, and the data itself. */ - pucByte += usDataLength + sizeof( uint16_t ); - } - } - } - } - - return ulIPAddress; -} -/*-----------------------------------------------------------*/ - -static xSocket_t prvCreateDNSSocket( void ) -{ -static xSocket_t xSocket = NULL; -struct freertos_sockaddr xAddress; -BaseType_t xReturn; -TickType_t xTimeoutTime = 200 / portTICK_RATE_MS; - - /* This must be the first time this function has been called. Create - the socket. */ - xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); - - /* Auto bind the port. */ - xAddress.sin_port = 0; - xReturn = FreeRTOS_bind( xSocket, &xAddress, sizeof( xAddress ) ); - - /* Check the bind was successful, and clean up if not. */ - if( xReturn != 0 ) - { - FreeRTOS_closesocket( xSocket ); - xSocket = NULL; - } - else - { - /* Set the send and receive timeouts. */ - FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, ( void * ) &xTimeoutTime, sizeof( TickType_t ) ); - FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDTIMEO, ( void * ) &xTimeoutTime, sizeof( TickType_t ) ); - } - - return xSocket; -} - -#endif /* ipconfigUSE_DNS != 0 */ - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_Sockets.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_Sockets.c deleted file mode 100644 index 2006deac1..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_Sockets.c +++ /dev/null @@ -1,1045 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkBufferManagement.h" - -/* Sanity check the UDP payload length setting is compatible with the -fragmentation setting. */ -#if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 - #if ( ( ipMAX_UDP_PAYLOAD_LENGTH % 8 ) != 0 ) - #error ( ipconfigNETWORK_MTU - 28 ) must be divisible by 8 when fragmentation is used - #endif /* ipMAX_UDP_PAYLOAD_LENGTH */ -#endif /* ipconfigFRAGMENT_OUTGOING_PACKETS */ - -/* The ItemValue of the sockets xBoundSocketListItem member holds the socket's -port number. */ -#define socketSET_SOCKET_ADDRESS( pxSocket, usPort ) listSET_LIST_ITEM_VALUE( ( &( ( pxSocket )->xBoundSocketListItem ) ), ( usPort ) ) -#define socketGET_SOCKET_ADDRESS( pxSocket ) listGET_LIST_ITEM_VALUE( ( &( ( pxSocket )->xBoundSocketListItem ) ) ) - -/* xWaitingPacketSemaphore is not created until the socket is bound, so can be -tested to see if bind() has been called. */ -#define socketSOCKET_IS_BOUND( pxSocket ) ( ( BaseType_t ) pxSocket->xWaitingPacketSemaphore ) - -/* If FreeRTOS_sendto() is called on a socket that is not bound to a port -number then, depending on the FreeRTOSIPConfig.h settings, it might be that a -port number is automatically generated for the socket. Automatically generated -port numbers will be between socketAUTO_PORT_ALLOCATION_START_NUMBER and -0xffff. */ -#define socketAUTO_PORT_ALLOCATION_START_NUMBER ( ( uint16_t ) 0xc000 ) - -/* When the automatically generated port numbers overflow, the next value used -is not set back to socketAUTO_PORT_ALLOCATION_START_NUMBER because it is likely -that the first few automatically generated ports will still be in use. Instead -it is reset back to the value defined by this constant. */ -#define socketAUTO_PORT_ALLOCATION_RESET_NUMBER ( ( uint16_t ) 0xc100 ) - -/* The number of octets that make up an IP address. */ -#define socketMAX_IP_ADDRESS_OCTETS 4 -/*-----------------------------------------------------------*/ - -/* - * Allocate the next port number from the private allocation range. - */ -static uint16_t prvGetPrivatePortNumber( void ); - -/* - * Return the list itme from within pxList that has an item value of - * xWantedItemValue. If there is no such list item return NULL. - */ -xListItem * pxListFindListItemWithValue( xList *pxList, TickType_t xWantedItemValue ); - -/*-----------------------------------------------------------*/ - -typedef struct XSOCKET -{ - xSemaphoreHandle xWaitingPacketSemaphore; - xList xWaitingPacketsList; - xListItem xBoundSocketListItem; /* Used to reference the socket from a bound sockets list. */ - TickType_t xReceiveBlockTime; - TickType_t xSendBlockTime; - uint8_t ucSocketOptions; - #if ipconfigSUPPORT_SELECT_FUNCTION == 1 - xQueueHandle xSelectQueue; - #endif -} xFreeRTOS_Socket_t; - - -/* The list that contains mappings between sockets and port numbers. Accesses -to this list must be protected by critical sections of one kind or another. */ -static xList xBoundSocketsList; - -/*-----------------------------------------------------------*/ - -xSocket_t FreeRTOS_socket( BaseType_t xDomain, BaseType_t xType, BaseType_t xProtocol ) -{ -xFreeRTOS_Socket_t *pxSocket; - - /* Only UDP on Ethernet is currently supported. */ - configASSERT( xDomain == FREERTOS_AF_INET ); - configASSERT( xType == FREERTOS_SOCK_DGRAM ); - configASSERT( xProtocol == FREERTOS_IPPROTO_UDP ); - configASSERT( listLIST_IS_INITIALISED( &xBoundSocketsList ) ); - - /* Allocate the structure that will hold the socket information. */ - pxSocket = ( xFreeRTOS_Socket_t * ) pvPortMalloc( sizeof( xFreeRTOS_Socket_t ) ); - - if( pxSocket == NULL ) - { - pxSocket = ( xFreeRTOS_Socket_t * ) FREERTOS_INVALID_SOCKET; - iptraceFAILED_TO_CREATE_SOCKET(); - } - else - { - /* Initialise the socket's members. The semaphore will be created if - the socket is bound to an address, for now the pointer to the semaphore - is just set to NULL to show it has not been created. */ - pxSocket->xWaitingPacketSemaphore = NULL; - vListInitialise( &( pxSocket->xWaitingPacketsList ) ); - vListInitialiseItem( &( pxSocket->xBoundSocketListItem ) ); - listSET_LIST_ITEM_OWNER( &( pxSocket->xBoundSocketListItem ), ( void * ) pxSocket ); - pxSocket->xSendBlockTime = ( TickType_t ) 0; - pxSocket->xReceiveBlockTime = portMAX_DELAY; - pxSocket->ucSocketOptions = FREERTOS_SO_UDPCKSUM_OUT; - #if ipconfigSUPPORT_SELECT_FUNCTION == 1 - pxSocket->xSelectQueue = NULL; - #endif - } - - /* Remove compiler warnings in the case the configASSERT() is not defined. */ - ( void ) xDomain; - ( void ) xType; - ( void ) xProtocol; - - return ( xSocket_t ) pxSocket; -} -/*-----------------------------------------------------------*/ - -#if ipconfigSUPPORT_SELECT_FUNCTION == 1 - - xSocketSet_t FreeRTOS_CreateSocketSet( UBaseType_t uxEventQueueLength ) - { - xQueueHandle xSelectQueue; - - /* Create the queue into which the address of sockets that are - available to read are posted. */ - xSelectQueue = xQueueCreate( uxEventQueueLength, sizeof( xSocket_t ) ); - - return ( xSocketSet_t ) xSelectQueue; - } - -#endif /* ipconfigSUPPORT_SELECT_FUNCTION */ -/*-----------------------------------------------------------*/ - -#if ipconfigSUPPORT_SELECT_FUNCTION == 1 - - BaseType_t FreeRTOS_FD_SET( xSocket_t xSocket, xSocketSet_t xSocketSet ) - { - xFreeRTOS_Socket_t *pxSocket = ( xFreeRTOS_Socket_t * ) xSocket; - BaseType_t xReturn = pdFALSE; - UBaseType_t uxMessagesWaiting; - - configASSERT( xSocket ); - - /* Is the socket already a member of a select group? */ - if( pxSocket->xSelectQueue == NULL ) - { - taskENTER_CRITICAL(); - { - /* Are there packets queued on the socket already? */ - uxMessagesWaiting = uxQueueMessagesWaiting( pxSocket->xWaitingPacketSemaphore ); - - /* Are there enough notification spaces in the select queue for the - number of packets already queued on the socket? */ - if( uxQueueSpacesAvailable( ( xQueueHandle ) xSocketSet ) >= uxMessagesWaiting ) - { - /* Store a pointer to the select group in the socket for - future reference. */ - pxSocket->xSelectQueue = ( xQueueHandle ) xSocketSet; - - while( uxMessagesWaiting > 0 ) - { - /* Add notifications of the number of packets that are - already queued on the socket to the select queue. */ - xQueueSendFromISR( pxSocket->xSelectQueue, &pxSocket, NULL ); - uxMessagesWaiting--; - } - - xReturn = pdPASS; - } - } - taskEXIT_CRITICAL(); - } - - return xReturn; - } - -#endif /* ipconfigSUPPORT_SELECT_FUNCTION */ -/*-----------------------------------------------------------*/ - -#if ipconfigSUPPORT_SELECT_FUNCTION == 1 - - BaseType_t FreeRTOS_FD_CLR( xSocket_t xSocket, xSocketSet_t xSocketSet ) - { - xFreeRTOS_Socket_t *pxSocket = ( xFreeRTOS_Socket_t * ) xSocket; - BaseType_t xReturn; - - /* Is the socket a member of the select group? */ - if( pxSocket->xSelectQueue == ( xQueueHandle ) xSocketSet ) - { - /* The socket is no longer a member of the select group. */ - pxSocket->xSelectQueue = NULL; - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; - } - -#endif /* ipconfigSUPPORT_SELECT_FUNCTION */ -/*-----------------------------------------------------------*/ - -#if ipconfigSUPPORT_SELECT_FUNCTION == 1 - - xSocket_t FreeRTOS_select( xSocketSet_t xSocketSet, TickType_t xBlockTimeTicks ) - { - xFreeRTOS_Socket_t *pxSocket; - - /* Wait for a socket to be ready to read. */ - if( xQueueReceive( ( xQueueHandle ) xSocketSet, &pxSocket, xBlockTimeTicks ) != pdPASS ) - { - pxSocket = NULL; - } - - return ( xSocket_t ) pxSocket; - } - -#endif /* ipconfigSUPPORT_SELECT_FUNCTION */ -/*-----------------------------------------------------------*/ - -int32_t FreeRTOS_recvfrom( xSocket_t xSocket, void *pvBuffer, size_t xBufferLength, uint32_t ulFlags, struct freertos_sockaddr *pxSourceAddress, socklen_t *pxSourceAddressLength ) -{ -xNetworkBufferDescriptor_t *pxNetworkBuffer; -int32_t lReturn; -xFreeRTOS_Socket_t *pxSocket; - - pxSocket = ( xFreeRTOS_Socket_t * ) xSocket; - - /* The function prototype is designed to maintain the expected Berkeley - sockets standard, but this implementation does not use all the parameters. */ - ( void ) pxSourceAddressLength; - - if( socketSOCKET_IS_BOUND( pxSocket ) != pdFALSE ) - { - /* The semaphore is given when received data is queued on the socket. */ - if( xSemaphoreTake( pxSocket->xWaitingPacketSemaphore, pxSocket->xReceiveBlockTime ) == pdPASS ) - { - taskENTER_CRITICAL(); - { - configASSERT( ( listCURRENT_LIST_LENGTH( &( pxSocket->xWaitingPacketsList ) ) > 0U ) ); - - /* The owner of the list item is the network buffer. */ - pxNetworkBuffer = ( xNetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &( pxSocket->xWaitingPacketsList ) ); - - /* Remove the network buffer from the list of buffers waiting to - be processed by the socket. */ - uxListRemove( &( pxNetworkBuffer->xBufferListItem ) ); - } - taskEXIT_CRITICAL(); - - if( ( ulFlags & FREERTOS_ZERO_COPY ) == 0 ) - { - /* The zero copy flag is not set. Truncate the length if it - won't fit in the provided buffer. */ - if( pxNetworkBuffer->xDataLength > xBufferLength ) - { - iptraceRECVFROM_DISCARDING_BYTES( ( xBufferLength - pxNetworkBuffer->xDataLength ) ); - pxNetworkBuffer->xDataLength = xBufferLength; - } - - /* Copy the received data into the provided buffer, then - release the network buffer. */ - memcpy( pvBuffer, ( void * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET ] ), pxNetworkBuffer->xDataLength ); - vNetworkBufferRelease( pxNetworkBuffer ); - } - else - { - /* The zero copy flag was set. pvBuffer is not a buffer into - which the received data can be copied, but a pointer that must - be set to point to the buffer in which the received data has - already been placed. */ - *( ( void** ) pvBuffer ) = ( void * ) ( &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET ] ) ); - } - - /* The returned value is the data length, which may have been - capped to the receive buffer size. */ - lReturn = ( int32_t ) pxNetworkBuffer->xDataLength; - - if( pxSourceAddress != NULL ) - { - pxSourceAddress->sin_port = pxNetworkBuffer->usPort; - pxSourceAddress->sin_addr = pxNetworkBuffer->ulIPAddress; - } - } - else - { - lReturn = FREERTOS_EWOULDBLOCK; - iptraceRECVFROM_TIMEOUT(); - } - } - else - { - lReturn = FREERTOS_EINVAL; - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - -#if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 - - int32_t FreeRTOS_sendto( xSocket_t xSocket, const void *pvBuffer, size_t xTotalDataLength, uint32_t ulFlags, const struct freertos_sockaddr *pxDestinationAddress, socklen_t xDestinationAddressLength ) - { - xNetworkBufferDescriptor_t *pxNetworkBuffer; - xIPFragmentParameters_t *pxFragmentParameters; - size_t xBytesToSend, xBytesRemaining; - xIPStackEvent_t xStackTxEvent = { eStackTxEvent, NULL }; - extern xQueueHandle xNetworkEventQueue; - uint8_t *pucBuffer; - xTimeOutType xTimeOut; - TickType_t xTicksToWait; - uint16_t usFragmentOffset; - xFreeRTOS_Socket_t *pxSocket; - - pxSocket = ( xFreeRTOS_Socket_t * ) xSocket; - - /* The function prototype is designed to maintain the expected Berkeley - sockets standard, but this implementation does not use all the - parameters. */ - ( void ) xDestinationAddressLength; - configASSERT( xNetworkEventQueue ); - configASSERT( pvBuffer ); - - xBytesRemaining = xTotalDataLength; - - if( socketSOCKET_IS_BOUND( pxSocket ) == pdFALSE ) - { - /* If the socket is not already bound to an address, bind it now. - Passing NULL as the address parameter tells FreeRTOS_bind() to select - the address to bind to. */ - FreeRTOS_bind( xSocket, NULL, 0 ); - } - - if( socketSOCKET_IS_BOUND( pxSocket ) != pdFALSE ) - { - /* pucBuffer will be reset if this send turns out to be a zero copy - send because in that case pvBuffer is actually a pointer to an - xUserData_t structure, not the UDP payload. */ - pucBuffer = ( uint8_t * ) pvBuffer; - vTaskSetTimeOutState( &xTimeOut ); - xTicksToWait = pxSocket->xSendBlockTime; - - /* The data being transmitted will be sent in - ipMAX_UDP_PAYLOAD_LENGTH chunks if xDataLength is greater than the - network buffer payload size. Loop until all the data is sent. */ - while( xBytesRemaining > 0 ) - { - if( xBytesRemaining > ipMAX_UDP_PAYLOAD_LENGTH ) - { - /* Cap the amount being sent in this packet to the maximum - UDP payload size. This will be a multiple of 8 already, - removing the need to check in the code. */ - xBytesToSend = ipMAX_UDP_PAYLOAD_LENGTH; - } - else - { - /* Send all remaining bytes - which may well be the total - number of bytes if the packet was not chopped up. */ - xBytesToSend = xBytesRemaining; - } - - /* If the zero copy flag is set, then the data is already in a - network buffer. Otherwise, get a new network buffer. */ - if( ( ulFlags & FREERTOS_ZERO_COPY ) == 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdTRUE ) - { - xTicksToWait = 0; - } - - pxNetworkBuffer = pxNetworkBufferGet( xBytesToSend + sizeof( xUDPPacket_t ), xTicksToWait ); - } - else - { - if( xTotalDataLength > ipMAX_UDP_PAYLOAD_LENGTH ) - { - /* The packet needs fragmenting, but zero copy buffers - cannot be fragmented. */ - pxNetworkBuffer = NULL; - } - else - { - /* When zero copy is used, pvBuffer is a pointer to the - payload of a buffer that has already been obtained from the - stack. Obtain the network buffer pointer from the buffer. */ - pucBuffer = ( uint8_t * ) pvBuffer; - pucBuffer -= ( ipBUFFER_PADDING + sizeof( xUDPPacket_t ) ); - pxNetworkBuffer = * ( ( xNetworkBufferDescriptor_t ** ) pucBuffer ); - } - } - - if( pxNetworkBuffer != NULL ) - { - /* Use the part of the network buffer that will be completed - by the IP layer as temporary storage to pass extra - information required by the IP layer. */ - pxFragmentParameters = ( xIPFragmentParameters_t * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipFRAGMENTATION_PARAMETERS_OFFSET ] ); - pxFragmentParameters->ucSocketOptions = pxSocket->ucSocketOptions; - - if( xBytesRemaining > ipMAX_UDP_PAYLOAD_LENGTH ) - { - /* The packet is being chopped up, and more data will - follow. */ - pxFragmentParameters->ucSocketOptions = ( pxSocket->ucSocketOptions | FREERTOS_NOT_LAST_IN_FRAGMENTED_PACKET ); - } - - if( xTotalDataLength > ipMAX_UDP_PAYLOAD_LENGTH ) - { - /* Let the IP layer know this packet has been chopped up, - and supply the IP layer with any addition information it - needs to make sense of it. */ - pxFragmentParameters->ucSocketOptions |= FREERTOS_FRAGMENTED_PACKET; - usFragmentOffset = ( uint16_t ) ( xTotalDataLength - xBytesRemaining ); - pxFragmentParameters->usFragmentedPacketOffset = usFragmentOffset; - pxFragmentParameters->usFragmentLength = ( uint16_t ) xBytesToSend; - } - else - { - usFragmentOffset = 0; - } - - /* Write the payload into the packet. The IP layer is - queried to find where in the IP payload the data should be - written. This is because the necessary offset is different - for the first packet, because the first packet leaves space - for a UDP header. Note that this changes usFragmentOffset - from the offset in the entire UDP packet, to the offset - in the IP packet. */ - if( ( ulFlags & FREERTOS_ZERO_COPY ) == 0 ) - { - /* Only copy the data if it is not already in the - expected location. */ - usFragmentOffset = ipGET_UDP_PAYLOAD_OFFSET_FOR_FRAGMENT( usFragmentOffset ); - memcpy( ( void * ) &( pxNetworkBuffer->pucEthernetBuffer[ usFragmentOffset ] ), ( void * ) pucBuffer, xBytesToSend ); - } - pxNetworkBuffer->xDataLength = xTotalDataLength; - pxNetworkBuffer->usPort = pxDestinationAddress->sin_port; - pxNetworkBuffer->usBoundPort = ( uint16_t ) socketGET_SOCKET_ADDRESS( pxSocket ); - pxNetworkBuffer->ulIPAddress = pxDestinationAddress->sin_addr; - - /* Tell the networking task that the packet needs sending. */ - xStackTxEvent.pvData = pxNetworkBuffer; - - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdTRUE ) - { - xTicksToWait = 0; - } - - if( xQueueSendToBack( xNetworkEventQueue, &xStackTxEvent, xTicksToWait ) != pdPASS ) - { - /* If the buffer was allocated in this function, release it. */ - if( ( ulFlags & FREERTOS_ZERO_COPY ) == 0 ) - { - vNetworkBufferRelease( pxNetworkBuffer ); - } - iptraceSTACK_TX_EVENT_LOST( ipSTACK_TX_EVENT ); - break; - } - - /* Adjust counters ready to either exit the loop, or send - another chunk of data. */ - xBytesRemaining -= xBytesToSend; - pucBuffer += xBytesToSend; - } - else - { - /* If errno was available, errno would be set to - FREERTOS_ENOPKTS. As it is, the function must return the - number of transmitted bytes, so the calling function knows how - much data was actually sent. */ - break; - } - } - } - - return ( xTotalDataLength - xBytesRemaining ); - } /* Tested */ - -#else /* ipconfigCAN_FRAGMENT_OUTGOING_PACKETS */ - - int32_t FreeRTOS_sendto( xSocket_t xSocket, const void *pvBuffer, size_t xTotalDataLength, uint32_t ulFlags, const struct freertos_sockaddr *pxDestinationAddress, socklen_t xDestinationAddressLength ) - { - xNetworkBufferDescriptor_t *pxNetworkBuffer; - xIPStackEvent_t xStackTxEvent = { eStackTxEvent, NULL }; - extern xQueueHandle xNetworkEventQueue; - xTimeOutType xTimeOut; - TickType_t xTicksToWait; - int32_t lReturn = 0; - xFreeRTOS_Socket_t *pxSocket; - uint8_t *pucBuffer; - - pxSocket = ( xFreeRTOS_Socket_t * ) xSocket; - - /* The function prototype is designed to maintain the expected Berkeley - sockets standard, but this implementation does not use all the - parameters. */ - ( void ) xDestinationAddressLength; - configASSERT( xNetworkEventQueue ); - configASSERT( pvBuffer ); - - if( xTotalDataLength <= ipMAX_UDP_PAYLOAD_LENGTH ) - { - if( socketSOCKET_IS_BOUND( pxSocket ) == pdFALSE ) - { - /* If the socket is not already bound to an address, bind it now. - Passing NULL as the address parameter tells FreeRTOS_bind() to - select the address to bind to. */ - FreeRTOS_bind( pxSocket, NULL, 0 ); - } - - if( socketSOCKET_IS_BOUND( pxSocket ) != pdFALSE ) - { - xTicksToWait = pxSocket->xSendBlockTime; - - if( ( ulFlags & FREERTOS_ZERO_COPY ) == 0 ) - { - /* Zero copy is not set, so obtain a network buffer into - which the payload will be copied. */ - vTaskSetTimeOutState( &xTimeOut ); - pxNetworkBuffer = pxNetworkBufferGet( xTotalDataLength + sizeof( xUDPPacket_t ), xTicksToWait ); - - if( pxNetworkBuffer != NULL ) - { - memcpy( ( void * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET ] ), ( void * ) pvBuffer, xTotalDataLength ); - - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdTRUE ) - { - /* The entire block time has been used up. */ - xTicksToWait = 0; - } - } - } - else - { - /* When zero copy is used, pvBuffer is a pointer to the - payload of a buffer that has already been obtained from the - stack. Obtain the network buffer pointer from the buffer. */ - pucBuffer = ( uint8_t * ) pvBuffer; - pucBuffer -= ( ipBUFFER_PADDING + sizeof( xUDPPacket_t ) ); - pxNetworkBuffer = * ( ( xNetworkBufferDescriptor_t ** ) pucBuffer ); - } - - if( pxNetworkBuffer != NULL ) - { - pxNetworkBuffer->xDataLength = xTotalDataLength; - pxNetworkBuffer->usPort = pxDestinationAddress->sin_port; - pxNetworkBuffer->usBoundPort = ( uint16_t ) socketGET_SOCKET_ADDRESS( pxSocket ); - pxNetworkBuffer->ulIPAddress = pxDestinationAddress->sin_addr; - - /* The socket options are passed to the IP layer in the - space that will eventually get used by the Ethernet header. */ - pxNetworkBuffer->pucEthernetBuffer[ ipSOCKET_OPTIONS_OFFSET ] = pxSocket->ucSocketOptions; - - /* Tell the networking task that the packet needs sending. */ - xStackTxEvent.pvData = pxNetworkBuffer; - - if( xQueueSendToBack( xNetworkEventQueue, &xStackTxEvent, xTicksToWait ) != pdPASS ) - { - /* If the buffer was allocated in this function, release it. */ - if( ( ulFlags & FREERTOS_ZERO_COPY ) == 0 ) - { - vNetworkBufferRelease( pxNetworkBuffer ); - } - iptraceSTACK_TX_EVENT_LOST( ipSTACK_TX_EVENT ); - } - else - { - lReturn = ( int32_t ) xTotalDataLength; - } - } - else - { - /* If errno was available, errno would be set to - FREERTOS_ENOPKTS. As it is, the function must return the - number of transmitted bytes, so the calling function knows how - much data was actually sent. */ - iptraceNO_BUFFER_FOR_SENDTO(); - } - } - else - { - iptraceSENDTO_SOCKET_NOT_BOUND(); - } - } - else - { - /* The data is longer than the available buffer space. Setting - ipconfigCAN_FRAGMENT_OUTGOING_PACKETS to 1 may allow this packet - to be sent. */ - iptraceSENDTO_DATA_TOO_LONG(); - } - - return lReturn; - } /* Tested */ - -#endif /* ipconfigCAN_FRAGMENT_OUTGOING_PACKETS */ -/*-----------------------------------------------------------*/ - -BaseType_t FreeRTOS_bind( xSocket_t xSocket, struct freertos_sockaddr * pxAddress, socklen_t xAddressLength ) -{ -BaseType_t xReturn = 0; /* In Berkeley sockets, 0 means pass for bind(). */ -xFreeRTOS_Socket_t *pxSocket; -#if ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND == 1 - struct freertos_sockaddr xAddress; -#endif /* ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND */ - - pxSocket = ( xFreeRTOS_Socket_t * ) xSocket; - - /* The function prototype is designed to maintain the expected Berkeley - sockets standard, but this implementation does not use all the parameters. */ - ( void ) xAddressLength; - - configASSERT( xSocket ); - configASSERT( xSocket != FREERTOS_INVALID_SOCKET ); - - #if ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND == 1 - { - /* pxAddress will be NULL if sendto() was called on a socket without the - socket being bound to an address. In this case, automatically allocate - an address to the socket. There is a very tiny chance that the allocated - port will already be in use - if that is the case, then the check below - [pxListFindListItemWithValue()] will result in an error being returned. */ - if( pxAddress == NULL ) - { - pxAddress = &xAddress; - pxAddress->sin_port = prvGetPrivatePortNumber(); - } - } - #endif /* ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND == 1 */ - - /* Sockets must be bound before calling FreeRTOS_sendto() if - ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is not set to 1. */ - configASSERT( pxAddress ); - - if( pxAddress != NULL ) - { - if( pxAddress->sin_port == 0 ) - { - pxAddress->sin_port = prvGetPrivatePortNumber(); - } - - vTaskSuspendAll(); - { - /* Check to ensure the port is not already in use. */ - if( pxListFindListItemWithValue( &xBoundSocketsList, ( TickType_t ) pxAddress->sin_port ) != NULL ) - { - xReturn = FREERTOS_EADDRINUSE; - } - } - xTaskResumeAll(); - - /* Check that xReturn has not been set before continuing. */ - if( xReturn == 0 ) - { - if( pxSocket->xWaitingPacketSemaphore == NULL ) - { - /* Create the semaphore used to count the number of packets that - are queued on this socket. */ - pxSocket->xWaitingPacketSemaphore = xSemaphoreCreateCounting( ipconfigNUM_NETWORK_BUFFERS, 0 ); - - if( pxSocket->xWaitingPacketSemaphore != NULL ) - { - /* Allocate the port number to the socket. */ - socketSET_SOCKET_ADDRESS( pxSocket, pxAddress->sin_port ); - taskENTER_CRITICAL(); - { - /* Add the socket to the list of bound ports. */ - vListInsertEnd( &xBoundSocketsList, &( pxSocket->xBoundSocketListItem ) ); - } - taskEXIT_CRITICAL(); - } - else - { - /* Out of memory. */ - xReturn = FREERTOS_ENOBUFS; - } - } - else - { - /* The socket is already bound. */ - xReturn = FREERTOS_EINVAL; - } - } - } - else - { - xReturn = FREERTOS_EADDRNOTAVAIL; - } - - if( xReturn != 0 ) - { - iptraceBIND_FAILED( xSocket, ( FreeRTOS_ntohs( pxAddress->sin_port ) ) ); - } - - return xReturn; -} /* Tested */ -/*-----------------------------------------------------------*/ - -BaseType_t FreeRTOS_closesocket( xSocket_t xSocket ) -{ -xNetworkBufferDescriptor_t *pxNetworkBuffer; -xFreeRTOS_Socket_t *pxSocket; - - pxSocket = ( xFreeRTOS_Socket_t * ) xSocket; - - configASSERT( pxSocket ); - configASSERT( pxSocket != FREERTOS_INVALID_SOCKET ); - - /* Socket must be unbound first, to ensure no more packets are queued on - it. */ - if( socketSOCKET_IS_BOUND( pxSocket ) != pdFALSE ) - { - taskENTER_CRITICAL(); - { - uxListRemove( &( pxSocket->xBoundSocketListItem ) ); - } - taskEXIT_CRITICAL(); - } - - /* Now the socket is not bound the list of waiting packets can be - drained. */ - if( pxSocket->xWaitingPacketSemaphore != NULL ) - { - while( listCURRENT_LIST_LENGTH( &( pxSocket->xWaitingPacketsList ) ) > 0U ) - { - pxNetworkBuffer = ( xNetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &( pxSocket->xWaitingPacketsList ) ); - uxListRemove( &( pxNetworkBuffer->xBufferListItem ) ); - vNetworkBufferRelease( pxNetworkBuffer ); - } - vSemaphoreDelete( pxSocket->xWaitingPacketSemaphore ); - } - - vPortFree( pxSocket ); - - return 0; -} /* Tested */ -/*-----------------------------------------------------------*/ - -void FreeRTOS_SocketsInit( void ) -{ - vListInitialise( &xBoundSocketsList ); -} -/*-----------------------------------------------------------*/ - -BaseType_t FreeRTOS_setsockopt( xSocket_t xSocket, int32_t lLevel, int32_t lOptionName, const void *pvOptionValue, size_t xOptionLength ) -{ -/* The standard Berkeley function returns 0 for success. */ -BaseType_t xReturn = 0; -BaseType_t lOptionValue; -xFreeRTOS_Socket_t *pxSocket; - - pxSocket = ( xFreeRTOS_Socket_t * ) xSocket; - - /* The function prototype is designed to maintain the expected Berkeley - sockets standard, but this implementation does not use all the parameters. */ - ( void ) lLevel; - ( void ) xOptionLength; - - configASSERT( xSocket ); - - switch( lOptionName ) - { - case FREERTOS_SO_RCVTIMEO : - /* Receive time out. */ - pxSocket->xReceiveBlockTime = *( ( TickType_t * ) pvOptionValue ); - break; - - case FREERTOS_SO_SNDTIMEO : - /* The send time out is capped for the reason stated in the comments - where ipconfigMAX_SEND_BLOCK_TIME_TICKS is defined in - FreeRTOSIPConfig.h (assuming an official configuration file is being - used. */ - pxSocket->xSendBlockTime = *( ( TickType_t * ) pvOptionValue ); - if( pxSocket->xSendBlockTime > ipconfigMAX_SEND_BLOCK_TIME_TICKS ) - { - pxSocket->xSendBlockTime = ipconfigMAX_SEND_BLOCK_TIME_TICKS; - } - break; - - case FREERTOS_SO_UDPCKSUM_OUT : - /* Turn calculating of the UDP checksum on/off for this socket. */ - lOptionValue = ( BaseType_t ) pvOptionValue; - - if( lOptionValue == 0 ) - { - pxSocket->ucSocketOptions &= ~FREERTOS_SO_UDPCKSUM_OUT; - } - else - { - pxSocket->ucSocketOptions |= FREERTOS_SO_UDPCKSUM_OUT; - } - break; - - default : - /* No other options are handled. */ - xReturn = FREERTOS_ENOPROTOOPT; - break; - } - - return xReturn; -} /* Tested */ -/*-----------------------------------------------------------*/ - -BaseType_t xProcessReceivedUDPPacket( xNetworkBufferDescriptor_t *pxNetworkBuffer, uint16_t usPort ) -{ -xListItem *pxListItem; -BaseType_t xReturn = pdPASS; -xFreeRTOS_Socket_t *pxSocket; -BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - vTaskSuspendAll(); - { - /* See if there is a list item associated with the port number on the - list of bound sockets. */ - pxListItem = pxListFindListItemWithValue( &xBoundSocketsList, ( TickType_t ) usPort ); - } - xTaskResumeAll(); - - if( pxListItem != NULL ) - { - /* The owner of the list item is the socket itself. */ - pxSocket = ( xFreeRTOS_Socket_t * ) listGET_LIST_ITEM_OWNER( pxListItem ); - - vTaskSuspendAll(); - { - #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) - { - /* Is the socket a member of a select() group? */ - if( pxSocket->xSelectQueue != NULL ) - { - /* Can the select group be notified that the socket is - ready to be read? */ - if( xQueueSendFromISR( pxSocket->xSelectQueue, &pxSocket, &xHigherPriorityTaskWoken ) != pdPASS ) - { - /* Could not notify the select group. */ - xReturn = pdFAIL; - iptraceFAILED_TO_NOTIFY_SELECT_GROUP( pxSocket ); - } - } - } - #endif - - if( xReturn == pdPASS ) - { - taskENTER_CRITICAL(); - { - /* Add the network packet to the list of packets to be - processed by the socket. */ - vListInsertEnd( &( pxSocket->xWaitingPacketsList ), &( pxNetworkBuffer->xBufferListItem ) ); - } - taskEXIT_CRITICAL(); - - /* The socket's counting semaphore records how many packets are - waiting to be processed by the socket. */ - xSemaphoreGiveFromISR( pxSocket->xWaitingPacketSemaphore, &xHigherPriorityTaskWoken ); - } - } - if( xTaskResumeAll() == pdFALSE ) - { - if( xHigherPriorityTaskWoken != pdFALSE ) - { - taskYIELD(); - } - } - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static uint16_t prvGetPrivatePortNumber( void ) -{ -static uint16_t usNextPortToUse = socketAUTO_PORT_ALLOCATION_START_NUMBER - 1; -uint16_t usReturn; - - /* Assign the next port in the range. */ - taskENTER_CRITICAL(); - { - usNextPortToUse++; - - /* Has it overflowed? */ - if( usNextPortToUse == 0U ) - { - /* Don't go right back to the start of the dynamic/private port - range numbers as any persistent sockets are likely to have been - create first so the early port numbers may still be in use. */ - usNextPortToUse = socketAUTO_PORT_ALLOCATION_RESET_NUMBER; - } - - usReturn = FreeRTOS_htons( usNextPortToUse ); - } - taskEXIT_CRITICAL(); - - return usReturn; -} /* Tested */ -/*-----------------------------------------------------------*/ - -xListItem * pxListFindListItemWithValue( xList *pxList, TickType_t xWantedItemValue ) -{ -xListItem *pxIterator, *pxReturn; - - pxReturn = NULL; - for( pxIterator = ( xListItem * ) pxList->xListEnd.pxNext; pxIterator != ( xListItem* ) &( pxList->xListEnd ); pxIterator = ( xListItem * ) pxIterator->pxNext ) - { - if( pxIterator->xItemValue == xWantedItemValue ) - { - pxReturn = pxIterator; - break; - } - } - - return pxReturn; -} /* Tested */ -/*-----------------------------------------------------------*/ - -#if ipconfigINCLUDE_FULL_INET_ADDR == 1 - - uint32_t FreeRTOS_inet_addr( const char *pcIPAddress ) - { - const uint8_t ucDecimalBase = 10; - uint8_t ucOctet[ socketMAX_IP_ADDRESS_OCTETS ]; - const char *pcPointerOnEntering; - uint32_t ulReturn = 0UL, ulOctetNumber, ulValue; - BaseType_t xResult = pdPASS; - - for( ulOctetNumber = 0; ulOctetNumber < socketMAX_IP_ADDRESS_OCTETS; ulOctetNumber++ ) - { - ulValue = 0; - pcPointerOnEntering = pcIPAddress; - - while( ( *pcIPAddress >= ( uint8_t ) '0' ) && ( *pcIPAddress <= ( uint8_t ) '9' ) ) - { - /* Move previous read characters into the next decimal - position. */ - ulValue *= ucDecimalBase; - - /* Add the binary value of the ascii character. */ - ulValue += ( *pcIPAddress - ( uint8_t ) '0' ); - - /* Move to next character in the string. */ - pcIPAddress++; - } - - /* Check characters were read. */ - if( pcIPAddress == pcPointerOnEntering ) - { - xResult = pdFAIL; - } - - /* Check the value fits in an 8-bit number. */ - if( ulValue > 0xffUL ) - { - xResult = pdFAIL; - } - else - { - ucOctet[ ulOctetNumber ] = ( uint8_t ) ulValue; - - /* Check the next character is as expected. */ - if( ulOctetNumber < ( socketMAX_IP_ADDRESS_OCTETS - 1 ) ) - { - if( *pcIPAddress != ( uint8_t ) '.' ) - { - xResult = pdFAIL; - } - else - { - /* Move past the dot. */ - pcIPAddress++; - } - } - } - - if( xResult == pdFAIL ) - { - /* No point going on. */ - break; - } - } - - if( *pcIPAddress != ( uint8_t ) 0x00 ) - { - /* Expected the end of the string. */ - xResult = pdFAIL; - } - - if( ulOctetNumber != socketMAX_IP_ADDRESS_OCTETS ) - { - /* Didn't read enough octets. */ - xResult = pdFAIL; - } - - if( xResult == pdPASS ) - { - ulReturn = FreeRTOS_inet_addr_quick( ucOctet[ 0 ], ucOctet[ 1 ], ucOctet[ 2 ], ucOctet[ 3 ] ); - } - - return ulReturn; - } - -#endif /* ipconfigINCLUDE_FULL_INET_ADDR */ -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_UDP_IP.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_UDP_IP.c deleted file mode 100644 index c1743b173..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_UDP_IP.c +++ /dev/null @@ -1,1853 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" -#include "timers.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_Sockets.h" -#include "FreeRTOS_DHCP.h" -#include "NetworkInterface.h" -#include "NetworkBufferManagement.h" - -/* Sanity check the configuration. */ -#if configUSE_TIMERS != 1 - #error configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h to use this file -#endif - -#if configTICK_RATE_HZ > 1000 - #error configTICK_RATE_HZ must be less than 1000 to use FreeRTOS+UDP -#endif - -#if ( ipconfigEVENT_QUEUE_LENGTH < ( ipconfigNUM_NETWORK_BUFFERS + 5 ) ) - #error The ipconfigEVENT_QUEUE_LENGTH parameter must be at least ipconfigNUM_NETWORK_BUFFERS + 5 -#endif - -#if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 && ipconfigSUPPORT_OUTGOING_PINGS == 1 - #error ipconfigSUPPORT_OUTGOING_PINGS can only be set to 1 if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 0 as IP fragmentation is not supported for ICMP (ping) packets -#endif - -#if ( ipconfigNETWORK_MTU < 46 ) - #error ipconfigNETWORK_MTU must be at least 46. -#endif -/*-----------------------------------------------------------*/ - -/* The IP header length in bytes. */ -#define ipIP_HEADER_LENGTH ( 20 ) - -/* IP protocol definitions. */ -#define ipPROTOCOL_ICMP ( 1 ) -#define ipPROTOCOL_UDP ( 17 ) - -/* ICMP protocol definitions. */ -#define ipICMP_ECHO_REQUEST ( ( uint16_t ) 8 ) -#define ipICMP_ECHO_REPLY ( ( uint16_t ) 0 ) - -/* The expected IP version and header length coded into the IP header itself. */ -#define ipIP_VERSION_AND_HEADER_LENGTH_BYTE ( ( uint8_t ) 0x45 ) - -/* Time delay between repeated attempts to initialise the network hardware. */ -#define ipINITIALISATION_RETRY_DELAY ( ( ( TickType_t ) 3000 ) / portTICK_RATE_MS ) - -/* The local MAC address is accessed from within xDefaultPartUDPPacketHeader, -rather than duplicated in its own variable. */ -#define ipLOCAL_MAC_ADDRESS ( xDefaultPartUDPPacketHeader ) - -/* The local IP address is accessed from within xDefaultPartUDPPacketHeader, -rather than duplicated in its own variable. */ -#define ipLOCAL_IP_ADDRESS_POINTER ( ( uint32_t * ) &( xDefaultPartUDPPacketHeader[ 20 ] ) ) - -/* Defines how often the ARP timer callback function is executed. The time is -shorted in the Windows simulator as simulated time is not real time. */ -#ifdef _WINDOWS_ - #define ipARP_TIMER_PERIOD_MS ( 500 ) /* For windows simulator builds. */ -#else - #define ipARP_TIMER_PERIOD_MS ( 10000 ) -#endif - -/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1, then the Ethernet -driver will filter incoming packets and only pass the stack those packets it -considers need processing. In this case ipCONSIDER_FRAME_FOR_PROCESSING() can -be #defined away. If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 0 -then the Ethernet driver will pass all received packets to the stack, and the -stack must do the filtering itself. In this case ipCONSIDER_FRAME_FOR_PROCESSING -needs to call eConsiderFrameForProcessing. */ -#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 0 - #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) -#else - #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer -#endif - -/* When the age of an entry in the ARP table reaches this value (it counts down -to zero, so this is an old entry) an ARP request will be sent to see if the -entry is still valid and can therefore be refreshed. */ -#define ipMAX_ARP_AGE_BEFORE_NEW_ARP_REQUEST ( 3 ) - -/* Number of bits to shift to divide by 8. Used to remove the need for a -divide. */ -#define ipSHIFT_TO_DIVIDE_BY_8 ( 3U ) - -/* The bit set in the IP header flags to indicate that the IP packet contains -a fragment of the eventual total payload, and that more fragments will follow. */ -#define ipMORE_FRAGMENTS_FLAG_BIT ( 0x2000U ) - -/* ICMP packets are sent using the same function as UDP packets. The port -number is used to distinguish between the two, as 0 is an invalid UDP port. */ -#define ipPACKET_CONTAINS_ICMP_DATA ( 0 ) - -/* The character used to fill ICMP echo requests, and therefore also the -character expected to fill ICMP echo replies. */ -#define ipECHO_DATA_FILL_BYTE 'x' - -#if( ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN ) - #define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0xff0f ) /* The bits in the two byte IP header field that make up the fragment offset value. */ -#else - #define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */ - #if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 - #warning Fragment offsets have not been tested on big endian machines. - #endif /* ipconfigCAN_FRAGMENT_OUTGOING_PACKETS */ -#endif /* ipconfigBYTE_ORDER */ - -/*-----------------------------------------------------------*/ -/* Miscellaneous structure and definitions. */ -/*-----------------------------------------------------------*/ - -typedef struct xARP_CACHE_TABLE_ROW -{ - uint32_t ulIPAddress; /* The IP address of an ARP cache entry. */ - xMACAddress_t xMACAddress; /* The MAC address of an ARP cache entry. */ - uint8_t ucAge; /* A value that is periodically decremented but can also be refreshed by active communication. The ARP cache entry is removed if the value reaches zero. */ -} xARPCacheRow_t; - -typedef enum -{ - eARPCacheMiss = 0, /* An ARP table lookup did not find a valid entry. */ - eARPCacheHit, /* An ARP table lookup found a valid entry. */ - eCantSendPacket /* There is no IP address, or an ARP is still in progress, so the packet cannot be sent. */ -} eARPLookupResult_t; - -typedef enum -{ - eNotFragment = 0, /* The IP packet being sent is not part of a fragment. */ - eFirstFragment, /* The IP packet being sent is the first in a set of fragmented packets. */ - eFollowingFragment /* The IP packet being sent is part of a set of fragmented packets. */ -} eIPFragmentStatus_t; - - -/*-----------------------------------------------------------*/ - -/* - * Called when new data is available from the network interface. - */ -static void prvProcessEthernetPacket( xNetworkBufferDescriptor_t * const pxNetworkBuffer ); - -/* - * Called when the application has generated a UDP packet to send. - */ -static void prvProcessGeneratedPacket( xNetworkBufferDescriptor_t * const pxNetworkBuffer ); - -/* - * Processes incoming ARP packets. - */ -static eFrameProcessingResult_t prvProcessARPPacket( xARPPacket_t * const pxARPFrame ); - -/* - * Process incoming IP packets. - */ -static eFrameProcessingResult_t prvProcessIPPacket( const xIPPacket_t * const pxIPPacket, xNetworkBufferDescriptor_t * const pxNetworkBuffer ); - -/* - * Process incoming ICMP packets. - */ -#if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - static eFrameProcessingResult_t prvProcessICMPPacket( xICMPPacket_t * const pxICMPPacket ); -#endif /* ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) */ - -/* - * Swap the source and destination addresses in an already constructed Ethernet - * frame, and send the frame to the network. - */ -static void prvReturnEthernetFrame( xNetworkBufferDescriptor_t * const pxNetworkBuffer ); - -/* - * Return the checksum generated over usDataLengthBytes from pucNextData. - */ -static uint16_t prvGenerateChecksum( const uint8_t * const pucNextData, const uint16_t usDataLengthBytes, BaseType_t xChecksumIsOffloaded ); - -/* - * The callback function that is assigned to all periodic processing timers - - * namely the DHCP timer and the ARP timer. - */ -void vIPFunctionsTimerCallback( xTimerHandle xTimer ); - -/* - * Reduce the age count in each entry within the ARP cache. An entry is no - * longer considered valid and is deleted if its age reaches zero. - */ -static void prvAgeARPCache( void ); - -/* - * If ulIPAddress is already in the ARP cache table then reset the age of the - * entry back to its maximum value. If ulIPAddress is not already in the ARP - * cache table then add it - replacing the oldest current entry if there is not - * a free space available. - */ -static void prvRefreshARPCacheEntry( const xMACAddress_t * const pxMACAddress, const uint32_t ulIPAddress ); - -/* - * Creates the pseudo header necessary then generate the checksum over the UDP - * packet. Returns the calculated checksum. - */ -static uint16_t prvGenerateUDPChecksum( const xUDPPacket_t * const pxUDPPacket, BaseType_t xChecksumIsOffloaded ); - -/* - * Look for ulIPAddress in the ARP cache. If the IP address exists, copy the - * associated MAC address into pxMACAddress, refresh the ARP cache entry's - * age, and return eARPCacheHit. If the IP address does not exist in the ARP - * cache return eARPCacheMiss. If the packet cannot be sent for any reason - * (maybe DHCP is still in process, or the addressing needs a gateway but there - * isn't a gateway defined) then return eCantSendPacket. - */ -static eARPLookupResult_t prvGetARPCacheEntry( uint32_t *pulIPAddress, xMACAddress_t * const pxMACAddress ); - -/* - * The main UDP/IP stack processing task. This task receives commands/events - * from the network hardware drivers, tasks that are using sockets, and software - * timers (such as the ARP timer). - */ -static void prvIPTask( void *pvParameters ); - -/* - * Send out an ARP request for the IP address contained in pxNetworkBuffer, and - * add an entry into the ARP table that indicates that an ARP reply is - * outstanding so re-transmissions can be generated. - */ -static void prvGenerateARPRequestPacket( xNetworkBufferDescriptor_t * const pxNetworkBuffer ); - -/* - * Called when outgoing packets are fragmented and require a fragment offset in - * their IP headers. Set the fragment offset (which includes the IP flags) and - * length from the data passed in the pxFragmentParameters structure. - */ - #if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 - static void prvCalculateFragmentOffsetAndLength( xIPFragmentParameters_t *pxFragmentParameters, uint16_t *pusFragmentOffset, uint16_t *pusFragmentLength ); -#endif /* ipconfigCAN_FRAGMENT_OUTGOING_PACKETS */ - -/* - * Complete the pxUDPPacket header with the information passed in - * pxNetworkBuffer. ucSocketOptions are passed in case the options include - * disabling the checksum. - */ -static void prvCompleteUDPHeader( xNetworkBufferDescriptor_t *pxNetworkBuffer, xUDPPacket_t *pxUDPPacket, uint8_t ucSocketOptions ); - -/* - * Send the event eEvent to the IP task event queue, using a block time of - * zero. Return pdPASS if the message was sent successfully, otherwise return - * pdFALSE. -*/ -static BaseType_t prvSendEventToIPTask( eIPEvent_t eEvent ); - -/* - * Generate and send an ARP request for the IP address passed in ulIPAddress. - */ -static void prvOutputARPRequest( uint32_t ulIPAddress ); - -/* - * Turns around an incoming ping request to convert it into a ping reply. - */ -#if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) - static eFrameProcessingResult_t prvProcessICMPEchoRequest( xICMPPacket_t * const pxICMPPacket ); -#endif /* ipconfigREPLY_TO_INCOMING_PINGS */ - -/* - * Processes incoming ping replies. The application callback function - * vApplicationPingReplyHook() is called with the results. - */ -#if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - static void prvProcessICMPEchoReply( xICMPPacket_t * const pxICMPPacket ); -#endif /* ipconfigSUPPORT_OUTGOING_PINGS */ - -/* - * Called to create a network connection when the stack is first started, or - * when the network connection is lost. - */ -static void prvProcessNetworkDownEvent( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used to pass events into the UDP task for processing. */ -xQueueHandle xNetworkEventQueue = NULL; - -/* The ARP cache. */ -static xARPCacheRow_t xARPCache[ ipconfigARP_CACHE_ENTRIES ]; - -/* The timer that triggers ARP events. */ -static xTimerHandle xARPTimer = NULL; - -/* Used to ensure network down events cannot be missed when they cannot be -posted to the network event queue because the network event queue is already -full. */ -static BaseType_t xNetworkDownEventPending = pdFALSE; - -/* For convenience, a MAC address of all zeros and another of all 0xffs are -defined const for quick reference. */ -static const xMACAddress_t xNullMACAddress = { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }; -static const xMACAddress_t xBroadcastMACAddress = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } }; - -/* Part of the Ethernet and IP headers are always constant when sending an IPv4 -UDP packet. This array defines the constant parts, allowing this part of the -packet to be filled in using a simple memcpy() instead of individual writes. */ -uint8_t xDefaultPartUDPPacketHeader[] = -{ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Ethernet source MAC address. */ - 0x08, 0x00, /* Ethernet frame type. */ - ipIP_VERSION_AND_HEADER_LENGTH_BYTE, /* ucVersionHeaderLength. */ - 0x00, /* ucDifferentiatedServicesCode. */ - 0x00, 0x00, /* usLength. */ - 0x00, 0x00, /* usIdentification. */ - 0x00, 0x00, /* usFragmentOffset. */ - updconfigIP_TIME_TO_LIVE, /* ucTimeToLive */ - ipPROTOCOL_UDP, /* ucProtocol. */ - 0x00, 0x00, /* usHeaderChecksum. */ - 0x00, 0x00, 0x00, 0x00 /* Source IP address. */ -}; - -/* Part of the Ethernet and ARP headers are always constant when sending an IPv4 -ARP packet. This array defines the constant parts, allowing this part of the -packet to be filled in using a simple memcpy() instead of individual writes. */ -static const uint8_t xDefaultPartARPPacketHeader[] = -{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* Ethernet destination address. */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Ethernet source address. */ - 0x08, 0x06, /* Ethernet frame type (ipARP_TYPE). */ - 0x00, 0x01, /* usHardwareType (ipARP_HARDWARE_TYPE_ETHERNET). */ - 0x08, 0x00, /* usProtocolType. */ - ipMAC_ADDRESS_LENGTH_BYTES, /* ucHardwareAddressLength. */ - ipIP_ADDRESS_LENGTH_BYTES, /* ucProtocolAddressLength. */ - 0x00, 0x01, /* usOperation (ipARP_REQUEST). */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* xSenderHardwareAddress. */ - 0x00, 0x00, 0x00, 0x00, /* ulSenderProtocolAddress. */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* xTargetHardwareAddress. */ -}; - -/* Structure that stores the netmask, gateway address and DNS server addresses. */ -static xNetworkAddressingParameters_t xNetworkAddressing = { 0, 0, 0, 0 }; - -/*-----------------------------------------------------------*/ - -static void prvIPTask( void *pvParameters ) -{ -xIPStackEvent_t xReceivedEvent; - - /* Just to prevent compiler warnings about unused parameters. */ - ( void ) pvParameters; - - /* Create the ARP timer, but don't start it until the network has - connected. */ - xARPTimer = xTimerCreate( "ARPTimer", ( ipARP_TIMER_PERIOD_MS / portTICK_RATE_MS ), pdTRUE, ( void * ) eARPTimerEvent, vIPFunctionsTimerCallback ); - configASSERT( xARPTimer ); - - /* Generate a dummy message to say that the network connection has gone - down. This will cause this task to initialise the network interface. After - this it is the responsibility of the network interface hardware driver to - send this message if a previously connected network is disconnected. */ - FreeRTOS_NetworkDown(); - - /* Loop, processing IP events. */ - for( ;; ) - { - /* Wait until there is something to do. */ - if( xQueueReceive( xNetworkEventQueue, ( void * ) &xReceivedEvent, portMAX_DELAY ) == pdPASS ) - { - iptraceNETWORK_EVENT_RECEIVED( xReceivedEvent.eEventType ); - - switch( xReceivedEvent.eEventType ) - { - case eNetworkDownEvent : - /* Attempt to establish a connection. */ - prvProcessNetworkDownEvent(); - break; - - case eEthernetRxEvent : - /* The network hardware driver has received a new packet. - A pointer to the received buffer is located in the pvData - member of the received event structure. */ - prvProcessEthernetPacket( ( xNetworkBufferDescriptor_t * ) ( xReceivedEvent.pvData ) ); - break; - - case eARPTimerEvent : - /* The ARP timer has expired, process the ARP cache. */ - prvAgeARPCache(); - break; - - case eStackTxEvent : - /* The network stack has generated a packet to send. A - pointer to the generated buffer is located in the pvData - member of the received event structure. */ - prvProcessGeneratedPacket( ( xNetworkBufferDescriptor_t * ) ( xReceivedEvent.pvData ) ); - break; - - case eDHCPEvent: - /* The DHCP state machine needs processing. */ - #if ipconfigUSE_DHCP == 1 - { - vDHCPProcess( pdFALSE, ( xMACAddress_t * ) ipLOCAL_MAC_ADDRESS, ipLOCAL_IP_ADDRESS_POINTER, &xNetworkAddressing ); - } - #endif - break; - - default : - /* Should not get here. */ - break; - } - - if( xNetworkDownEventPending != pdFALSE ) - { - /* A network down event could not be posted to the network - event queue because the queue was full. Try posting again. */ - FreeRTOS_NetworkDown(); - } - } - } -} -/*-----------------------------------------------------------*/ - -void FreeRTOS_NetworkDown( void ) -{ -static const xIPStackEvent_t xNetworkDownEvent = { eNetworkDownEvent, NULL }; -const TickType_t xDontBlock = 0; - - /* Simply send the network task the appropriate event. */ - if( xQueueSendToBack( xNetworkEventQueue, &xNetworkDownEvent, xDontBlock ) != pdPASS ) - { - xNetworkDownEventPending = pdTRUE; - } - else - { - xNetworkDownEventPending = pdFALSE; - } - - iptraceNETWORK_DOWN(); -} -/*-----------------------------------------------------------*/ - -BaseType_t FreeRTOS_NetworkDownFromISR( void ) -{ -static const xIPStackEvent_t xNetworkDownEvent = { eNetworkDownEvent, NULL }; -BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - /* Simply send the network task the appropriate event. */ - if( xQueueSendToBackFromISR( xNetworkEventQueue, &xNetworkDownEvent, &xHigherPriorityTaskWoken ) != pdPASS ) - { - xNetworkDownEventPending = pdTRUE; - } - else - { - xNetworkDownEventPending = pdFALSE; - } - iptraceNETWORK_DOWN(); - - return xHigherPriorityTaskWoken; -} -/*-----------------------------------------------------------*/ - -void *FreeRTOS_GetUDPPayloadBuffer( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ) -{ -xNetworkBufferDescriptor_t *pxNetworkBuffer; -void *pvReturn; - - /* Cap the block time. The reason for this is explained where - ipconfigMAX_SEND_BLOCK_TIME_TICKS is defined (assuming an official - FreeRTOSIPConfig.h header file is being used). */ - if( xBlockTimeTicks > ipconfigMAX_SEND_BLOCK_TIME_TICKS ) - { - xBlockTimeTicks = ipconfigMAX_SEND_BLOCK_TIME_TICKS; - } - - /* Obtain a network buffer with the required amount of storage. */ - pxNetworkBuffer = pxNetworkBufferGet( sizeof( xUDPPacket_t ) + xRequestedSizeBytes, xBlockTimeTicks ); - - if( pxNetworkBuffer != NULL ) - { - /* Leave space for the UPD header. */ - pvReturn = ( void * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET ] ); - } - else - { - pvReturn = NULL; - } - - return ( void * ) pvReturn; -} -/*-----------------------------------------------------------*/ - -void FreeRTOS_ReleaseUDPPayloadBuffer( void *pvBuffer ) -{ -uint8_t *pucBuffer; - - /* Obtain the network buffer from the zero copy pointer. */ - pucBuffer = ( uint8_t * ) pvBuffer; - pucBuffer -= ( ipBUFFER_PADDING + sizeof( xUDPPacket_t ) ); - - vNetworkBufferRelease( * ( ( xNetworkBufferDescriptor_t ** ) pucBuffer ) ); -} -/*-----------------------------------------------------------*/ - -uint8_t * FreeRTOS_GetMACAddress( void ) -{ - return ipLOCAL_MAC_ADDRESS; -} -/*-----------------------------------------------------------*/ - -BaseType_t FreeRTOS_IPInit( const uint8_t ucIPAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucNetMask[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucGatewayAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucDNSServerAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucMACAddress[ ipMAC_ADDRESS_LENGTH_BYTES ] ) -{ -static BaseType_t xReturn = pdFALSE; - - /* Only create the IP event queue if it has not already been created, in - case this function is called more than once. */ - if( xNetworkEventQueue == NULL ) - { - xNetworkEventQueue = xQueueCreate( ipconfigEVENT_QUEUE_LENGTH, sizeof( xIPStackEvent_t ) ); - configASSERT( xNetworkEventQueue ); - vQueueAddToRegistry( xNetworkEventQueue, "NetEvnt" ); - } - - if( xNetworkBuffersInitialise() == pdPASS ) - { - if( xNetworkEventQueue != NULL ) - { - /* xReturn is static to ensure the network interface is not - initialised twice. */ - if( xReturn == pdFALSE ) - { - /* Store the local IP and MAC address. */ - xNetworkAddressing.ulDefaultIPAddress = FreeRTOS_inet_addr_quick( ucIPAddress[ 0 ], ucIPAddress[ 1 ], ucIPAddress[ 2 ], ucIPAddress[ 3 ] ); - xNetworkAddressing.ulNetMask = FreeRTOS_inet_addr_quick( ucNetMask[ 0 ], ucNetMask[ 1 ], ucNetMask[ 2 ], ucNetMask[ 3 ] ); - xNetworkAddressing.ulGatewayAddress = FreeRTOS_inet_addr_quick( ucGatewayAddress[ 0 ], ucGatewayAddress[ 1 ], ucGatewayAddress[ 2 ], ucGatewayAddress[ 3 ] ); - xNetworkAddressing.ulDNSServerAddress = FreeRTOS_inet_addr_quick( ucDNSServerAddress[ 0 ], ucDNSServerAddress[ 1 ], ucDNSServerAddress[ 2 ], ucDNSServerAddress[ 3 ] ); - - #if ipconfigUSE_DHCP == 1 - { - /* The IP address is not set until DHCP completes. */ - *ipLOCAL_IP_ADDRESS_POINTER = 0x00UL; - } - #else - { - *ipLOCAL_IP_ADDRESS_POINTER = xNetworkAddressing.ulDefaultIPAddress; - - /* Ensure the gateway is on the same subnet as the IP - address. */ - configASSERT( ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) == ( xNetworkAddressing.ulGatewayAddress & xNetworkAddressing.ulNetMask ) ); - } - #endif /* ipconfigUSE_DHCP == 1 */ - - /* The MAC address is stored in the start of the default packet - header fragment, which is used when sending UDP packets. */ - memcpy( ( void * ) ipLOCAL_MAC_ADDRESS, ( void * ) ucMACAddress, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); - - /* Prepare the sockets interface. */ - FreeRTOS_SocketsInit(); - - /* Create the task that processes Ethernet and stack events. */ - xReturn = xTaskCreate( prvIPTask, "UDP/IP", ipconfigUDP_TASK_STACK_SIZE_WORDS, NULL, ipconfigUDP_TASK_PRIORITY, NULL ); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void FreeRTOS_GetAddressConfiguration( uint32_t *pulIPAddress, uint32_t *pulNetMask, uint32_t *pulGatewayAddress, uint32_t *pulDNSServerAddress ) -{ - if( pulIPAddress != NULL ) - { - *pulIPAddress = *ipLOCAL_IP_ADDRESS_POINTER; - } - - if( pulNetMask != NULL ) - { - *pulNetMask = xNetworkAddressing.ulNetMask; - } - - if( pulGatewayAddress != NULL ) - { - *pulGatewayAddress = xNetworkAddressing.ulGatewayAddress; - } - - if( pulDNSServerAddress != NULL ) - { - *pulDNSServerAddress = xNetworkAddressing.ulDNSServerAddress; - } -} -/*-----------------------------------------------------------*/ - -#if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - - BaseType_t FreeRTOS_SendPingRequest( uint32_t ulIPAddress, size_t xNumberOfBytesToSend, TickType_t xBlockTimeTicks ) - { - xNetworkBufferDescriptor_t *pxNetworkBuffer; - xICMPHeader_t *pxICMPHeader; - BaseType_t xReturn = pdFAIL; - static uint16_t usSequenceNumber = 0; - uint8_t *pucChar; - xIPStackEvent_t xStackTxEvent = { eStackTxEvent, NULL }; - - if( xNumberOfBytesToSend < ( ( ipconfigNETWORK_MTU - sizeof( xIPHeader_t ) ) - sizeof( xICMPHeader_t ) ) ) - { - pxNetworkBuffer = pxNetworkBufferGet( xNumberOfBytesToSend + sizeof( xICMPPacket_t ), xBlockTimeTicks ); - - if( pxNetworkBuffer != NULL ) - { - pxICMPHeader = ( xICMPHeader_t * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipIP_PAYLOAD_OFFSET ] ); - usSequenceNumber++; - - /* Fill in the basic header information. */ - pxICMPHeader->ucTypeOfMessage = ipICMP_ECHO_REQUEST; - pxICMPHeader->ucTypeOfService = 0; - pxICMPHeader->usIdentifier = usSequenceNumber; - pxICMPHeader->usSequenceNumber = usSequenceNumber; - pxICMPHeader->usChecksum = 0; - - /* Find the start of the data. */ - pucChar = ( uint8_t * ) pxICMPHeader; - pucChar += sizeof( xICMPHeader_t ); - - /* Just memset the data to a fixed value. */ - memset( ( void * ) pucChar, ( int ) ipECHO_DATA_FILL_BYTE, xNumberOfBytesToSend ); - - /* The message is complete, calculate the checksum. */ - pxICMPHeader->usChecksum = prvGenerateChecksum( ( uint8_t * ) pxICMPHeader, ( uint16_t ) ( xNumberOfBytesToSend + sizeof( xICMPHeader_t ) ), pdFALSE ); - - /* Complete the network buffer information. */ - pxNetworkBuffer->ulIPAddress = ulIPAddress; - pxNetworkBuffer->usPort = ipPACKET_CONTAINS_ICMP_DATA; - pxNetworkBuffer->xDataLength = xNumberOfBytesToSend + sizeof( xICMPHeader_t ); - - /* Send to the stack. */ - xStackTxEvent.pvData = pxNetworkBuffer; - if( xQueueSendToBack( xNetworkEventQueue, &xStackTxEvent, xBlockTimeTicks ) != pdPASS ) - { - vNetworkBufferRelease( pxNetworkBuffer ); - iptraceSTACK_TX_EVENT_LOST( ipSTACK_TX_EVENT ); - } - else - { - xReturn = usSequenceNumber; - } - } - } - else - { - /* The requested number of bytes will not fit in the available space - in the network buffer. Outgoing fragmentation is only supported for - UDP packets. */ - } - - return xReturn; - } - -#endif /* ipconfigSUPPORT_OUTGOING_PINGS == 1 */ - -/*-----------------------------------------------------------*/ - -static BaseType_t prvSendEventToIPTask( eIPEvent_t eEvent ) -{ -xIPStackEvent_t xEventMessage; -const TickType_t xDontBlock = 0; -BaseType_t xReturn; - - xEventMessage.eEventType = eEvent; - xReturn = xQueueSendToBack( xNetworkEventQueue, &xEventMessage, xDontBlock ); - - if( xReturn != pdPASS ) - { - iptraceSTACK_TX_EVENT_LOST( ipARP_TIMER_EVENT ); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vIPFunctionsTimerCallback( xTimerHandle xTimer ) -{ -eIPEvent_t eMessage; - - /* This time can be used to send more than one type of message to the IP - task. The message ID is stored in the ID of the timer. The strange - casting is to avoid compiler warnings. */ - eMessage = ( eIPEvent_t ) ( ( BaseType_t ) pvTimerGetTimerID( xTimer ) ); - - prvSendEventToIPTask( eMessage ); -} -/*-----------------------------------------------------------*/ - -static void prvOutputARPRequest( uint32_t ulIPAddress ) -{ -xNetworkBufferDescriptor_t *pxNetworkBuffer; - - /* This is called from the context of the IP event task, so a block time - must not be used. */ - pxNetworkBuffer = pxNetworkBufferGet( sizeof( xARPPacket_t ), 0 ); - if( pxNetworkBuffer != NULL ) - { - pxNetworkBuffer->ulIPAddress = ulIPAddress; - prvGenerateARPRequestPacket( pxNetworkBuffer ); - xNetworkInterfaceOutput( pxNetworkBuffer ); - } -} -/*-----------------------------------------------------------*/ - -static void prvAgeARPCache( void ) -{ -BaseType_t x; - - /* Loop through each entry in the ARP cache. */ - for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) - { - /* If the entry is valid (its age is greater than zero). */ - if( xARPCache[ x ].ucAge > 0U ) - { - /* Decrement the age value of the entry in this ARP cache table row. - When the age reaches zero it is no longer considered valid. */ - ( xARPCache[ x ].ucAge )--; - - /* If the entry has a MAC address of 0, then it is waiting an ARP - reply, and the ARP request should be retransmitted. */ - if( memcmp( ( void * ) &xNullMACAddress, ( void * ) &( xARPCache[ x ].xMACAddress ), sizeof( xMACAddress_t ) ) == 0 ) - { - prvOutputARPRequest( xARPCache[ x ].ulIPAddress ); - } - else if( xARPCache[ x ].ucAge <= ipMAX_ARP_AGE_BEFORE_NEW_ARP_REQUEST ) - { - /* This entry will get removed soon. See if the MAC address is - still valid to prevent this happening. */ - iptraceARP_TABLE_ENTRY_WILL_EXPIRE( xARPCache[ x ].ulIPAddress ); - prvOutputARPRequest( xARPCache[ x ].ulIPAddress ); - } - else - { - /* The age has just ticked down, with nothing to do. */ - } - - if( xARPCache[ x ].ucAge == 0 ) - { - /* The entry is no longer valid. Wipe it out. */ - iptraceARP_TABLE_ENTRY_EXPIRED( xARPCache[ x ].ulIPAddress ); - xARPCache[ x ].ulIPAddress = 0UL; - } - } - } -} -/*-----------------------------------------------------------*/ - -static eARPLookupResult_t prvGetARPCacheEntry( uint32_t *pulIPAddress, xMACAddress_t * const pxMACAddress ) -{ -BaseType_t x; -eARPLookupResult_t eReturn; -uint32_t ulAddressToLookup; - - if( *pulIPAddress == ipBROADCAST_IP_ADDRESS ) - { - /* This is a broadcast so uses the broadcast MAC address. */ - memcpy( ( void * ) pxMACAddress, &xBroadcastMACAddress, sizeof( xMACAddress_t ) ); - eReturn = eARPCacheHit; - } - else if( *ipLOCAL_IP_ADDRESS_POINTER == 0UL ) - { - /* The IP address has not yet been assigned, so there is nothing that - can be done. */ - eReturn = eCantSendPacket; - } - else - { - if( ( *pulIPAddress & xNetworkAddressing.ulNetMask ) != ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) ) - { - /* The IP address is off the local network, so look up the hardware - address of the router, if any. */ - ulAddressToLookup = xNetworkAddressing.ulGatewayAddress; - } - else - { - /* The IP address is on the local network, so lookup the requested - IP address directly. */ - ulAddressToLookup = *pulIPAddress; - } - - if( ulAddressToLookup == 0UL ) - { - /* The address is not on the local network, and there is not a - router. */ - eReturn = eCantSendPacket; - } - else - { - eReturn = eARPCacheMiss; - - /* Loop through each entry in the ARP cache. */ - for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) - { - /* Does this row in the ARP cache table hold an entry for the IP - address being queried? */ - if( xARPCache[ x ].ulIPAddress == ulAddressToLookup ) - { - /* The IP address matched. Is there a valid MAC address? */ - if( memcmp( ( void * ) &xNullMACAddress, ( void * ) &( xARPCache[ x ].xMACAddress ), sizeof( xMACAddress_t ) ) == 0 ) - { - /* This entry is waiting an ARP reply, so is not valid. */ - eReturn = eCantSendPacket; - } - else - { - /* A valid entry was found. */ - memcpy( pxMACAddress, &( xARPCache[ x ].xMACAddress ), sizeof( xMACAddress_t ) ); - eReturn = eARPCacheHit; - } - } - - if( eReturn != eARPCacheMiss ) - { - break; - } - } - - if( eReturn == eARPCacheMiss ) - { - /* It might be that the ARP has to go to the gateway. */ - *pulIPAddress = ulAddressToLookup; - } - } - } - - return eReturn; -} -/*-----------------------------------------------------------*/ - -static void prvRefreshARPCacheEntry( const xMACAddress_t * const pxMACAddress, const uint32_t ulIPAddress ) -{ -BaseType_t x, xEntryFound = pdFALSE, xOldestEntry = 0; -uint8_t ucMinAgeFound = 0U; - - /* Only process the IP address if it is on the local network. */ - if( ( ulIPAddress & xNetworkAddressing.ulNetMask ) == ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) ) - { - /* Start with the maximum possible number. */ - ucMinAgeFound--; - - /* For each entry in the ARP cache table. */ - for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) - { - /* Does this line in the cache table hold an entry for the IP - address being queried? */ - if( xARPCache[ x ].ulIPAddress == ulIPAddress ) - { - /* If the MAC address is all zeros then the refresh is due to - an ARP reply, so in effect this is a new entry in the ARP - cache. */ - if( memcmp( &( xARPCache[ x ].xMACAddress ), &xNullMACAddress, sizeof( xMACAddress_t ) ) == 0 ) - { - iptraceARP_TABLE_ENTRY_CREATED( xARPCache[ x ].ulIPAddress, *pxMACAddress ); - } - - /* Refresh the cache entry so the entry's age is back to its - maximum value. */ - xARPCache[ x ].ucAge = ipconfigMAX_ARP_AGE; - memcpy( &( xARPCache[ x ].xMACAddress ), pxMACAddress, sizeof( xMACAddress_t ) ); - xEntryFound = pdTRUE; - break; - } - else - { - /* As the table is traversed, remember the table row that - contains the oldest entry (the lowest age count, as ages are - decremented to zero) so the row can be re-used if this function - needs to add an entry that does not already exist. */ - if( xARPCache[ x ].ucAge < ucMinAgeFound ) - { - ucMinAgeFound = xARPCache[ x ].ucAge; - xOldestEntry = x; - } - } - } - - if( xEntryFound == pdFALSE ) - { - /* The wanted entry does not already exist. Add the entry into the - cache, replacing the oldest entry (which might be an empty entry). */ - xARPCache[ xOldestEntry ].ulIPAddress = ulIPAddress; - memcpy( &( xARPCache[ xOldestEntry ].xMACAddress ), pxMACAddress, sizeof( xMACAddress_t ) ); - - /* If the MAC address is all zeros, then this entry is not yet - complete but still waiting the reply from an ARP request. When this - is the case the age is set to a much lower value as an ARP - retransmission will be generated each time the ARP timer is called - while the reply is still outstanding. */ - if( pxMACAddress == &xNullMACAddress ) - { - xARPCache[ xOldestEntry ].ucAge = ipconfigMAX_ARP_RETRANSMISSIONS; - } - else - { - iptraceARP_TABLE_ENTRY_CREATED( xARPCache[ xOldestEntry ].ulIPAddress, xARPCache[ xOldestEntry ].xMACAddress ); - xARPCache[ xOldestEntry ].ucAge = ipconfigMAX_ARP_AGE; - } - } - } -} -/*-----------------------------------------------------------*/ - -#if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 - - static void prvCalculateFragmentOffsetAndLength( xIPFragmentParameters_t *pxFragmentParameters, uint16_t *pusFragmentOffset, uint16_t *pusFragmentLength ) - { - *pusFragmentOffset = pxFragmentParameters->usFragmentedPacketOffset; - - if( *pusFragmentOffset != 0 ) - { - /* Take into account that the payload has had a UDP header added in the - first fragment of the set. */ - *pusFragmentOffset += sizeof( xUDPHeader_t ); - } - - /* The offset is defined in multiples of 8 bytes. */ - *pusFragmentOffset >>= ipSHIFT_TO_DIVIDE_BY_8; - *pusFragmentLength = pxFragmentParameters->usFragmentLength; - - if( ( pxFragmentParameters->ucSocketOptions & FREERTOS_NOT_LAST_IN_FRAGMENTED_PACKET ) != 0 ) - { - /* Set the more fragments flag. */ - *pusFragmentOffset |= ipMORE_FRAGMENTS_FLAG_BIT; - } - } - -#endif -/*-----------------------------------------------------------*/ - -static void prvCompleteUDPHeader( xNetworkBufferDescriptor_t *pxNetworkBuffer, xUDPPacket_t *pxUDPPacket, uint8_t ucSocketOptions ) -{ -xUDPHeader_t *pxUDPHeader; - - pxUDPHeader = &( pxUDPPacket->xUDPHeader ); - - pxUDPHeader->usDestinationPort = pxNetworkBuffer->usPort; - pxUDPHeader->usSourcePort = pxNetworkBuffer->usBoundPort; - pxUDPHeader->usLength = ( uint16_t ) ( pxNetworkBuffer->xDataLength + sizeof( xUDPHeader_t ) ); - pxUDPHeader->usLength = FreeRTOS_htons( pxUDPPacket->xUDPHeader.usLength ); - pxUDPHeader->usChecksum = 0; - - if( ( ucSocketOptions & FREERTOS_SO_UDPCKSUM_OUT ) != 0U ) - { - pxUDPHeader->usChecksum = prvGenerateUDPChecksum( pxUDPPacket, ipconfigETHERNET_DRIVER_ADDS_UDP_CHECKSUM ); - if( pxUDPHeader->usChecksum == 0x00 ) - { - /* A calculated checksum of 0 must be inverted as 0 means the - checksum is disabled. */ - pxUDPHeader->usChecksum = 0xffffU; - } - } -} -/*-----------------------------------------------------------*/ - -#if ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 - - static void prvProcessGeneratedPacket( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) - { - xUDPPacket_t *pxUDPPacket; - xUDPHeader_t *pxUDPHeader; - xIPHeader_t *pxIPHeader; - eARPLookupResult_t eReturned; - eIPFragmentStatus_t eFragmentStatus; - uint16_t usFragmentOffset = 0, usFragmentLength; - xIPFragmentParameters_t *pxFragmentParameters; - static uint16_t usPacketIdentifier = 0U; - - /* Map the UDP packet onto the start of the frame. */ - pxUDPPacket = ( xUDPPacket_t * ) pxNetworkBuffer->pucEthernetBuffer; - - /* Determine the ARP cache status for the requested IP address. */ - eReturned = prvGetARPCacheEntry( &( pxNetworkBuffer->ulIPAddress ), &( pxUDPPacket->xEthernetHeader.xDestinationAddress ) ); - - if( eReturned != eCantSendPacket ) - { - if( eReturned == eARPCacheHit ) - { - iptraceSENDING_UDP_PACKET( pxNetworkBuffer->ulIPAddress ); - - /* Create short cuts to the data within the packet. */ - pxUDPHeader = &( pxUDPPacket->xUDPHeader ); - pxIPHeader = &( pxUDPPacket->xIPHeader ); - pxFragmentParameters = ( xIPFragmentParameters_t * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipFRAGMENTATION_PARAMETERS_OFFSET ] ); - - /* IP header source and destination addresses must be set - before the UDP checksum is calculated. */ - pxIPHeader->ulDestinationIPAddress = pxNetworkBuffer->ulIPAddress; - pxIPHeader->ulSourceIPAddress = *ipLOCAL_IP_ADDRESS_POINTER; - - /* If the packet is not fragmented, or if the packet is the - first in a fragmented packet, then a UDP header is required. */ - if( ( pxFragmentParameters->ucSocketOptions & FREERTOS_FRAGMENTED_PACKET ) == 0 ) - { - eFragmentStatus = eNotFragment; - - #if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - { - /* Is it possible that the packet is not actually a UDP - packet after all, but an ICMP packet. */ - if( pxNetworkBuffer->usPort != ipPACKET_CONTAINS_ICMP_DATA ) - { - prvCompleteUDPHeader( pxNetworkBuffer, pxUDPPacket, pxFragmentParameters->ucSocketOptions ); - } - } - #else /* ipconfigSUPPORT_OUTGOING_PINGS */ - { - prvCompleteUDPHeader( pxNetworkBuffer, pxUDPPacket, pxFragmentParameters->ucSocketOptions ); - } - #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ - - - usFragmentLength = 0U; - - /* The identifier is incremented as this is a new and - unfragmented IP packet. */ - usPacketIdentifier++; - } - else if( pxFragmentParameters->usFragmentedPacketOffset == 0 ) - { - eFragmentStatus = eFirstFragment; - prvCalculateFragmentOffsetAndLength( pxFragmentParameters, &usFragmentOffset, &usFragmentLength ); - /* Note FREERTOS_SO_UDPCKSUM_OUT is used because checksums - cannot currently be used on fragmented packets. */ - pxFragmentParameters->ucSocketOptions &= ~FREERTOS_SO_UDPCKSUM_OUT; - prvCompleteUDPHeader( pxNetworkBuffer, pxUDPPacket, pxFragmentParameters->ucSocketOptions ); - - /* The identifier is incremented because, although this is a - fragmented packet, it is the first in the fragmentation - set. */ - usPacketIdentifier++; - } - else - { - eFragmentStatus = eFollowingFragment; - prvCalculateFragmentOffsetAndLength( pxFragmentParameters, &usFragmentOffset, &usFragmentLength ); - } - - /* memcpy() the constant parts of the header information into the - correct location within the packet. This fills in: - xEthernetHeader.xSourceAddress - xEthernetHeader.usFrameType - xIPHeader.ucVersionHeaderLength - xIPHeader.ucDifferentiatedServicesCode - xIPHeader.usLength - xIPHeader.usIdentification - xIPHeader.usFragmentOffset - xIPHeader.ucTimeToLive - xIPHeader.ucProtocol - and - xIPHeader.usHeaderChecksum - */ - memcpy( ( void *) &( pxUDPPacket->xEthernetHeader.xSourceAddress ), ( void * ) xDefaultPartUDPPacketHeader, sizeof( xDefaultPartUDPPacketHeader ) ); - - /* The fragment status is used to complete the length and - fragment offset fields. */ - if( eFragmentStatus == eNotFragment ) - { - pxIPHeader->usLength = ( uint16_t ) ( pxNetworkBuffer->xDataLength + sizeof( xIPHeader_t ) + sizeof( xUDPHeader_t ) ); - } - else if( eFragmentStatus == eFirstFragment ) - { - pxIPHeader->usFragmentOffset = FreeRTOS_htons( usFragmentOffset ); - pxIPHeader->usLength = ( uint16_t ) ( usFragmentLength + sizeof( xIPHeader_t ) + sizeof( xUDPHeader_t ) ); - } - else - { - pxIPHeader->usFragmentOffset = FreeRTOS_htons( usFragmentOffset ); - pxIPHeader->usLength = ( uint16_t ) ( usFragmentLength + sizeof( xIPHeader_t ) ); - } - - /* The total transmit size adds on the Ethernet header. */ - pxNetworkBuffer->xDataLength = pxIPHeader->usLength + sizeof( xEthernetHeader_t ); - pxIPHeader->usLength = FreeRTOS_htons( pxIPHeader->usLength ); - pxIPHeader->ulDestinationIPAddress = pxNetworkBuffer->ulIPAddress; - pxIPHeader->usIdentification = usPacketIdentifier; - pxIPHeader->usHeaderChecksum = prvGenerateChecksum( ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipIP_HEADER_LENGTH, ipconfigETHERNET_DRIVER_ADDS_IP_CHECKSUM ); - } - else if ( eReturned == eARPCacheMiss ) - { - /* Send an ARP for the required IP address. */ - iptracePACKET_DROPPED_TO_GENERATE_ARP( pxNetworkBuffer->ulIPAddress ); - prvGenerateARPRequestPacket( pxNetworkBuffer ); - - /* Add an entry to the ARP table with a null hardware address. - This allows the ARP timer to know that an ARP reply is - outstanding, and perform retransmissions if necessary. */ - prvRefreshARPCacheEntry( &xNullMACAddress, pxNetworkBuffer->ulIPAddress ); - } - else - { - /* The lookup indicated that an ARP request has already been - sent out for the queried IP address. */ - eReturned = eCantSendPacket; - } - } - - if( eReturned != eCantSendPacket ) - { - /* The network driver is responsible for freeing the network buffer - after the packet has been sent. */ - xNetworkInterfaceOutput( pxNetworkBuffer ); - } - else - { - /* The packet can't be sent (DHCP not completed?). Just drop the - packet. */ - vNetworkBufferRelease( pxNetworkBuffer ); - } - } - -#else /* ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 */ - - static void prvProcessGeneratedPacket( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) - { - xUDPPacket_t *pxUDPPacket; - xIPHeader_t *pxIPHeader; - eARPLookupResult_t eReturned; - - /* Map the UDP packet onto the start of the frame. */ - pxUDPPacket = ( xUDPPacket_t * ) pxNetworkBuffer->pucEthernetBuffer; - - /* Determine the ARP cache status for the requested IP address. */ - eReturned = prvGetARPCacheEntry( &( pxNetworkBuffer->ulIPAddress ), &( pxUDPPacket->xEthernetHeader.xDestinationAddress ) ); - if( eReturned != eCantSendPacket ) - { - if( eReturned == eARPCacheHit ) - { - iptraceSENDING_UDP_PACKET( pxNetworkBuffer->ulIPAddress ); - - /* Create short cuts to the data within the packet. */ - pxIPHeader = &( pxUDPPacket->xIPHeader ); - - /* IP header source and destination addresses must be set before - the UDP checksum is calculated. The socket options, which - specify whether a checksum should be calculated or not, are - passed in the as yet unused part of the packet data. */ - pxIPHeader->ulDestinationIPAddress = pxNetworkBuffer->ulIPAddress; - pxIPHeader->ulSourceIPAddress = *ipLOCAL_IP_ADDRESS_POINTER; - - #if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - { - /* Is it possible that the packet is not actually a UDP packet - after all, but an ICMP packet. */ - if( pxNetworkBuffer->usPort != ipPACKET_CONTAINS_ICMP_DATA ) - { - prvCompleteUDPHeader( pxNetworkBuffer, pxUDPPacket, pxNetworkBuffer->pucEthernetBuffer[ ipSOCKET_OPTIONS_OFFSET ] ); - } - } - #else /* ipconfigSUPPORT_OUTGOING_PINGS */ - { - prvCompleteUDPHeader( pxNetworkBuffer, pxUDPPacket, pxNetworkBuffer->pucEthernetBuffer[ ipSOCKET_OPTIONS_OFFSET ] ); - } - #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ - - /* memcpy() the constant parts of the header information into - the correct location within the packet. This fills in: - xEthernetHeader.xSourceAddress - xEthernetHeader.usFrameType - xIPHeader.ucVersionHeaderLength - xIPHeader.ucDifferentiatedServicesCode - xIPHeader.usLength - xIPHeader.usIdentification - xIPHeader.usFragmentOffset - xIPHeader.ucTimeToLive - xIPHeader.ucProtocol - and - xIPHeader.usHeaderChecksum - */ - memcpy( ( void *) &( pxUDPPacket->xEthernetHeader.xSourceAddress ), ( void * ) xDefaultPartUDPPacketHeader, sizeof( xDefaultPartUDPPacketHeader ) ); - - #if ipconfigSUPPORT_OUTGOING_PINGS == 1 - { - if( pxNetworkBuffer->usPort == ipPACKET_CONTAINS_ICMP_DATA ) - { - pxIPHeader->ucProtocol = ipPROTOCOL_ICMP; - pxIPHeader->usLength = ( uint16_t ) ( pxNetworkBuffer->xDataLength + sizeof( xIPHeader_t ) ); - } - else - { - pxIPHeader->usLength = ( uint16_t ) ( pxNetworkBuffer->xDataLength + sizeof( xIPHeader_t ) + sizeof( xUDPHeader_t ) ); - } - } - #else /* ipconfigSUPPORT_OUTGOING_PINGS */ - { - pxIPHeader->usLength = ( uint16_t ) ( pxNetworkBuffer->xDataLength + sizeof( xIPHeader_t ) + sizeof( xUDPHeader_t ) ); - } - #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ - - /* The total transmit size adds on the Ethernet header. */ - pxNetworkBuffer->xDataLength = pxIPHeader->usLength + sizeof( xEthernetHeader_t ); - pxIPHeader->usLength = FreeRTOS_htons( pxIPHeader->usLength ); - pxIPHeader->ulDestinationIPAddress = pxNetworkBuffer->ulIPAddress; - pxIPHeader->usHeaderChecksum = prvGenerateChecksum( ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipIP_HEADER_LENGTH, ipconfigETHERNET_DRIVER_ADDS_IP_CHECKSUM ); - } - else if ( eReturned == eARPCacheMiss ) - { - /* Generate an ARP for the required IP address. */ - iptracePACKET_DROPPED_TO_GENERATE_ARP( pxNetworkBuffer->ulIPAddress ); - prvGenerateARPRequestPacket( pxNetworkBuffer ); - - /* Add an entry to the ARP table with a null hardware address. - This allows the ARP timer to know that an ARP reply is - outstanding, and perform retransmissions if necessary. */ - prvRefreshARPCacheEntry( &xNullMACAddress, pxNetworkBuffer->ulIPAddress ); - } - else - { - /* The lookup indicated that an ARP request has already been - sent out for the queried IP address. */ - eReturned = eCantSendPacket; - } - } - - if( eReturned != eCantSendPacket ) - { - /* The network driver is responsible for freeing the network buffer - after the packet has been sent. */ - xNetworkInterfaceOutput( pxNetworkBuffer ); - } - else - { - /* The packet can't be sent (DHCP not completed?). Just drop the - packet. */ - vNetworkBufferRelease( pxNetworkBuffer ); - } - } - - -#endif /* ipconfigCAN_FRAGMENT_OUTGOING_PACKETS == 1 */ -/*-----------------------------------------------------------*/ - -static void prvGenerateARPRequestPacket( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -xARPPacket_t *pxARPPacket; - - pxARPPacket = ( xARPPacket_t * ) pxNetworkBuffer->pucEthernetBuffer; - - /* memcpy the const part of the header information into the correct - location in the packet. This copies: - xEthernetHeader.ulDestinationAddress - xEthernetHeader.usFrameType; - xARPHeader.usHardwareType; - xARPHeader.usProtocolType; - xARPHeader.ucHardwareAddressLength; - xARPHeader.ucProtocolAddressLength; - xARPHeader.usOperation; - xARPHeader.xTargetHardwareAddress; - */ - memcpy( ( void * ) &( pxARPPacket->xEthernetHeader ), ( void * ) xDefaultPartARPPacketHeader, sizeof( xDefaultPartARPPacketHeader ) ); - memcpy( ( void * ) &( pxARPPacket->xEthernetHeader.xSourceAddress ) , ( void * ) ipLOCAL_MAC_ADDRESS, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); - memcpy( ( void * ) &( pxARPPacket->xARPHeader.xSenderHardwareAddress ), ( void * ) ipLOCAL_MAC_ADDRESS, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); - pxARPPacket->xARPHeader.ulSenderProtocolAddress = *ipLOCAL_IP_ADDRESS_POINTER; - pxARPPacket->xARPHeader.ulTargetProtocolAddress = pxNetworkBuffer->ulIPAddress; - - pxNetworkBuffer->xDataLength = sizeof( xARPPacket_t ); - - iptraceCREATING_ARP_REQUEST( pxNetworkBuffer->ulIPAddress ); -} -/*-----------------------------------------------------------*/ - -eFrameProcessingResult_t eConsiderFrameForProcessing( const uint8_t * const pucEthernetBuffer ) -{ -eFrameProcessingResult_t eReturn; -const xEthernetHeader_t *pxEthernetHeader; - - pxEthernetHeader = ( const xEthernetHeader_t * ) pucEthernetBuffer; - - if( memcmp( ( void * ) &xBroadcastMACAddress, ( void * ) &( pxEthernetHeader->xDestinationAddress ), sizeof( xMACAddress_t ) ) == 0 ) - { - /* The packet was a broadcast - process it. */ - eReturn = eProcessBuffer; - } - else if( memcmp( ( void * ) ipLOCAL_MAC_ADDRESS, ( void * ) &( pxEthernetHeader->xDestinationAddress ), sizeof( xMACAddress_t ) ) == 0 ) - { - /* The packet was to this node directly - process it. */ - eReturn = eProcessBuffer; - } - else - { - /* The packet was not a broadcast, or for this node, just release - the buffer without taking any other action. */ - eReturn = eReleaseBuffer; - } - - #if ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES == 1 - { - uint16_t usFrameType; - - if( eReturn == eProcessBuffer ) - { - usFrameType = pxEthernetHeader->usFrameType; - usFrameType = FreeRTOS_ntohs( usFrameType ); - - if( usFrameType <= 0x600U ) - { - /* Not an Ethernet II frame. */ - eReturn = eReleaseBuffer; - } - } - } - #endif /* ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES == 1 */ - - return eReturn; -} -/*-----------------------------------------------------------*/ - -static void prvProcessNetworkDownEvent( void ) -{ - /* Stop the ARP timer while there is no network. */ - xTimerStop( xARPTimer, portMAX_DELAY ); - - #if ipconfigUSE_NETWORK_EVENT_HOOK == 1 - { - static BaseType_t xCallEventHook = pdFALSE; - - /* The first network down event is generated by the IP stack - itself to initialise the network hardware, so do not call the - network down event the first time through. */ - if( xCallEventHook == pdTRUE ) - { - vApplicationIPNetworkEventHook( eNetworkDown ); - } - xCallEventHook = pdTRUE; - } - #endif - - /* The network has been disconnected (or is being - initialised for the first time). Perform whatever hardware - processing is necessary to bring it up again, or wait for it - to be available again. This is hardware dependent. */ - if( xNetworkInterfaceInitialise() != pdPASS ) - { - /* Ideally the network interface initialisation function - will only return when the network is available. In case - this is not the case, wait a while before retrying the - initialisation. */ - vTaskDelay( ipINITIALISATION_RETRY_DELAY ); - FreeRTOS_NetworkDown(); - } - else - { - /* Start the ARP timer. */ - xTimerStart( xARPTimer, portMAX_DELAY ); - - #if ipconfigUSE_DHCP == 1 - { - /* The network is not up until DHCP has completed. */ - vDHCPProcess( pdTRUE, ( xMACAddress_t * ) ipLOCAL_MAC_ADDRESS, ipLOCAL_IP_ADDRESS_POINTER, &xNetworkAddressing ); - prvSendEventToIPTask( eDHCPEvent ); - } - #else - { - #if ipconfigUSE_NETWORK_EVENT_HOOK == 1 - { - vApplicationIPNetworkEventHook( eNetworkUp ); - } - #endif /* ipconfigUSE_NETWORK_EVENT_HOOK */ - - /* Static configuration is being used, so the network is now up. */ - #if ipconfigFREERTOS_PLUS_NABTO == 1 - { - /* Return value is used in configASSERT() inside the - function. */ - ( void ) xStartNabtoTask(); - } - #endif /* ipconfigFREERTOS_PLUS_NABTO */ - } - #endif - } -} -/*-----------------------------------------------------------*/ - -static void prvProcessEthernetPacket( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -xEthernetHeader_t *pxEthernetHeader; -volatile eFrameProcessingResult_t eReturned; /* Volatile to prevent complier warnings when ipCONSIDER_FRAME_FOR_PROCESSING just sets it to eProcessBuffer. */ - - configASSERT( pxNetworkBuffer ); - - /* Interpret the Ethernet frame. */ - eReturned = ipCONSIDER_FRAME_FOR_PROCESSING( pxNetworkBuffer->pucEthernetBuffer ); - pxEthernetHeader = ( xEthernetHeader_t * ) pxNetworkBuffer->pucEthernetBuffer; - - if( eReturned == eProcessBuffer ) - { - /* Interpret the received Ethernet packet. */ - switch ( pxEthernetHeader->usFrameType ) - { - case ipARP_TYPE : - /* The Ethernet frame contains an ARP packet. */ - eReturned = prvProcessARPPacket( ( xARPPacket_t * ) pxEthernetHeader ); - break; - - case ipIP_TYPE : - /* The Ethernet frame contains an IP packet. */ - eReturned = prvProcessIPPacket( ( xIPPacket_t * ) pxEthernetHeader, pxNetworkBuffer ); - break; - - default : - /* No other packet types are handled. Nothing to do. */ - eReturned = eReleaseBuffer; - break; - } - } - - /* Perform any actions that resulted from processing the Ethernet - frame. */ - switch( eReturned ) - { - case eReturnEthernetFrame : - /* The Ethernet frame will have been updated (maybe it was - an ARP request or a PING request?) and should be sent back to - its source. */ - prvReturnEthernetFrame( pxNetworkBuffer ); - /* The buffer must be released once - the frame has been transmitted. */ - break; - - case eFrameConsumed : - /* The frame is in use somewhere, don't release the buffer - yet. */ - break; - - default : - /* The frame is not being used anywhere, and the - xNetworkBufferDescriptor_t structure containing the frame should just be - released back to the list of free buffers. */ - vNetworkBufferRelease( pxNetworkBuffer ); - break; - } -} -/*-----------------------------------------------------------*/ - -static eFrameProcessingResult_t prvProcessIPPacket( const xIPPacket_t * const pxIPPacket, xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -eFrameProcessingResult_t eReturn = eReleaseBuffer; -const xIPHeader_t * pxIPHeader; -xUDPPacket_t *pxUDPPacket; -BaseType_t xChecksumIsCorrect; - - pxIPHeader = &( pxIPPacket->xIPHeader ); - - /* Is the packet for this node? */ - if( ( pxIPHeader->ulDestinationIPAddress == *ipLOCAL_IP_ADDRESS_POINTER ) || ( pxIPHeader->ulDestinationIPAddress == ipBROADCAST_IP_ADDRESS ) || ( *ipLOCAL_IP_ADDRESS_POINTER == 0 ) ) - { - /* Ensure the frame is IPv4 with no options bytes, and that the incoming - packet is not fragmented (only outgoing packets can be fragmented) as - these are the only handled IP frames currently. */ - if( ( pxIPHeader->ucVersionHeaderLength == ipIP_VERSION_AND_HEADER_LENGTH_BYTE ) && ( ( pxIPHeader->usFragmentOffset & ipFRAGMENT_OFFSET_BIT_MASK ) == 0U ) ) - { - /* Is the IP header checksum correct? */ - if( prvGenerateChecksum( ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipIP_HEADER_LENGTH, ipconfigETHERNET_DRIVER_CHECKS_IP_CHECKSUM ) == 0 ) - { - /* Add the IP and MAC addresses to the ARP table if they are not - already there - otherwise refresh the age of the existing - entry. */ - prvRefreshARPCacheEntry( &( pxIPPacket->xEthernetHeader.xSourceAddress ), pxIPHeader->ulSourceIPAddress ); - switch( pxIPHeader->ucProtocol ) - { - case ipPROTOCOL_ICMP : - - /* The IP packet contained an ICMP frame. Don't bother - checking the ICMP checksum, as if it is wrong then the - wrong data will also be returned, and the source of the - ping will know something went wrong because it will not - be able to validate what it receives. */ - #if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - { - if( pxIPHeader->ulDestinationIPAddress == *ipLOCAL_IP_ADDRESS_POINTER ) - { - eReturn = prvProcessICMPPacket( ( xICMPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ) ); - } - } - #endif /* ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) */ - break; - - case ipPROTOCOL_UDP : - - /* The IP packet contained a UDP frame. */ - pxUDPPacket = ( xUDPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); - - /* Note the header values required prior to the - checksum generation as the checksum pseudo header - may clobber some of these values. */ - pxNetworkBuffer->xDataLength = FreeRTOS_ntohs( pxUDPPacket->xUDPHeader.usLength ) - sizeof( xUDPHeader_t ); - pxNetworkBuffer->usPort = pxUDPPacket->xUDPHeader.usSourcePort; - pxNetworkBuffer->ulIPAddress = pxUDPPacket->xIPHeader.ulSourceIPAddress; - - /* Is the checksum required? */ - if( pxUDPPacket->xUDPHeader.usChecksum == 0 ) - { - xChecksumIsCorrect = pdTRUE; - } - else if( prvGenerateUDPChecksum( pxUDPPacket, ipconfigETHERNET_DRIVER_CHECKS_UDP_CHECKSUM ) == 0 ) - { - xChecksumIsCorrect = pdTRUE; - } - else - { - xChecksumIsCorrect = pdFALSE; - } - - /* Is the checksum correct? */ - if( xChecksumIsCorrect == pdTRUE ) - { - /* Pass the packet payload to the UDP sockets - implementation. */ - if( xProcessReceivedUDPPacket( pxNetworkBuffer, pxUDPPacket->xUDPHeader.usDestinationPort ) == pdPASS ) - { - eReturn = eFrameConsumed; - } - } - break; - - default : - - /* Not a supported frame type. */ - break; - } - } - } - } - - return eReturn; -} -/*-----------------------------------------------------------*/ - -static uint16_t prvGenerateUDPChecksum( const xUDPPacket_t * const pxUDPPacket, BaseType_t xChecksumIsOffloaded ) -{ -xPseudoHeader_t *pxPseudoHeader; -uint16_t usLength, usReturn; - - if( xChecksumIsOffloaded == pdFALSE ) - { - /* Map the pseudo header into the correct place within the real IP - header. */ - pxPseudoHeader = ( xPseudoHeader_t * ) &( pxUDPPacket->xIPHeader.ucTimeToLive ); - - /* Ordering here is important so as not to overwrite data that is required - but has not yet been used as the pseudo header overlaps the information - that is being copied into it. */ - pxPseudoHeader->ulSourceAddress = pxUDPPacket->xIPHeader.ulSourceIPAddress; - pxPseudoHeader->ulDestinationAddress = pxUDPPacket->xIPHeader.ulDestinationIPAddress; - pxPseudoHeader->ucZeros = 0x00; - pxPseudoHeader->ucProtocol = ipPROTOCOL_UDP; - pxPseudoHeader->usUDPLength = pxUDPPacket->xUDPHeader.usLength; - - usLength = FreeRTOS_ntohs( pxPseudoHeader->usUDPLength ); - usReturn = prvGenerateChecksum( ( uint8_t * ) pxPseudoHeader, usLength + sizeof( xPseudoHeader_t ), pdFALSE ); - } - else - { - /* The hardware will check the checksum. Returning 0 allows this - function to be used to both check an incoming checksum and set an - outgoing checksum in this case. */ - usReturn = 0; - } - - return usReturn; -} -/*-----------------------------------------------------------*/ - -#if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - - static void prvProcessICMPEchoReply( xICMPPacket_t * const pxICMPPacket ) - { - ePingReplyStatus_t eStatus = eSuccess; - uint16_t usDataLength, usCount; - uint8_t *pucByte; - - /* Find the total length of the IP packet. */ - usDataLength = pxICMPPacket->xIPHeader.usLength; - usDataLength = FreeRTOS_ntohs( usDataLength ); - - /* Remove the length of the IP headers to obtain the length of the ICMP - message itself. */ - usDataLength -= sizeof( xIPHeader_t ); - - if( prvGenerateChecksum( ( uint8_t * ) &( pxICMPPacket->xICMPHeader ), usDataLength, pdFALSE ) != 0 ) - { - eStatus = eInvalidChecksum; - } - else - { - /* Remove the length of the ICMP header, to obtain the length of - data contained in the ping. */ - usDataLength -= sizeof( xICMPHeader_t ); - - /* Find the first byte of the data within the ICMP packet. */ - pucByte = ( uint8_t * ) pxICMPPacket; - pucByte += sizeof( xICMPPacket_t ); - - /* Check each byte. */ - for( usCount = 0; usCount < usDataLength; usCount++ ) - { - if( *pucByte != ipECHO_DATA_FILL_BYTE ) - { - eStatus = eInvalidData; - break; - } - - pucByte++; - } - } - - vApplicationPingReplyHook( eStatus, pxICMPPacket->xICMPHeader.usIdentifier ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) - - static eFrameProcessingResult_t prvProcessICMPEchoRequest( xICMPPacket_t * const pxICMPPacket ) - { - xICMPHeader_t *pxICMPHeader; - xIPHeader_t *pxIPHeader; - - pxICMPHeader = &( pxICMPPacket->xICMPHeader ); - pxIPHeader = &( pxICMPPacket->xIPHeader ); - - iptraceSENDING_PING_REPLY( pxIPHeader->ulSourceIPAddress ); - - /* The checksum can be checked here - but a ping reply should be - returned even if the checksum is incorrect so the other end can - tell that the ping was received - even if the ping reply contains - invalid data. */ - pxICMPHeader->ucTypeOfMessage = ipICMP_ECHO_REPLY; - pxIPHeader->ulDestinationIPAddress = pxIPHeader->ulSourceIPAddress; - pxIPHeader->ulSourceIPAddress = *ipLOCAL_IP_ADDRESS_POINTER; - - /* Update the checksum because the ucTypeOfMessage member in the - header has been changed to ipICMP_ECHO_REPLY. */ - if( pxICMPHeader->usChecksum >= FreeRTOS_htons( ( ( uint16_t ) 0xffffU ) - ( ipICMP_ECHO_REQUEST << ( ( uint16_t ) 8U ) ) ) ) - { - pxICMPHeader->usChecksum += FreeRTOS_htons( ipICMP_ECHO_REQUEST << ( ( uint16_t ) 8U ) ) + ( uint16_t ) 1U; - } - else - { - pxICMPHeader->usChecksum += FreeRTOS_htons( ipICMP_ECHO_REQUEST << ( ( uint16_t ) 8U ) ); - } - - return eReturnEthernetFrame; - } - -#endif /* ipconfigREPLY_TO_INCOMING_PINGS == 1 */ - -/*-----------------------------------------------------------*/ - -#if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - - static eFrameProcessingResult_t prvProcessICMPPacket( xICMPPacket_t * const pxICMPPacket ) - { - eFrameProcessingResult_t eReturn = eReleaseBuffer; - - iptraceICMP_PACKET_RECEIVED(); - - switch( pxICMPPacket->xICMPHeader.ucTypeOfMessage ) - { - case ipICMP_ECHO_REQUEST : - #if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) - { - eReturn = prvProcessICMPEchoRequest( pxICMPPacket ); - } - #endif /* ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) */ - break; - - case ipICMP_ECHO_REPLY : - #if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) - { - prvProcessICMPEchoReply( pxICMPPacket ); - } - #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ - break; - - default : - break; - } - - return eReturn; - } - -#endif /* ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) */ -/*-----------------------------------------------------------*/ - -static uint16_t prvGenerateChecksum( const uint8_t * const pucNextData, const uint16_t usDataLengthBytes, BaseType_t xChecksumIsOffloaded ) -{ -uint32_t ulChecksum = 0; -uint16_t us, usDataLength16BitWords, *pusNextData, usReturn; - - if( xChecksumIsOffloaded == pdFALSE ) - { - /* There are half as many 16 bit words than bytes. */ - usDataLength16BitWords = ( usDataLengthBytes >> 1U ); - - pusNextData = ( uint16_t * ) pucNextData; - - for( us = 0U; us < usDataLength16BitWords; us++ ) - { - ulChecksum += ( uint32_t ) pusNextData[ us ]; - } - - if( ( usDataLengthBytes & 0x01U ) != 0x00 ) - { - /* There is one byte left over. */ - #if ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN - { - ulChecksum += ( uint32_t ) pucNextData[ usDataLengthBytes - 1 ]; - } - #else - { - us = ( uint16_t ) pucNextData[ usDataLengthBytes - 1 ]; - ulChecksum += ( uint32_t ) ( us << 8 ); - } - #endif - } - - while( ( ulChecksum >> 16UL ) != 0x00UL ) - { - ulChecksum = ( ulChecksum & 0xffffUL ) + ( ulChecksum >> 16UL ); - } - - usReturn = ~( ( uint16_t ) ulChecksum ); - } - else - { - /* The checksum is calculated by the hardware. Return 0 here to ensure - this works for both incoming and outgoing checksums. */ - usReturn = 0; - } - - return usReturn; -} -/*-----------------------------------------------------------*/ - -static void prvReturnEthernetFrame( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -xEthernetHeader_t *pxEthernetHeader; - - pxEthernetHeader = ( xEthernetHeader_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); - - /* Swap source and destination MAC addresses. */ - memcpy( ( void * ) &( pxEthernetHeader->xDestinationAddress ), ( void * ) &( pxEthernetHeader->xSourceAddress ), sizeof( pxEthernetHeader->xDestinationAddress ) ); - memcpy( ( void * ) &( pxEthernetHeader->xSourceAddress) , ( void * ) ipLOCAL_MAC_ADDRESS, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); - - /* Send! */ - xNetworkInterfaceOutput( pxNetworkBuffer ); -} -/*-----------------------------------------------------------*/ - -static eFrameProcessingResult_t prvProcessARPPacket( xARPPacket_t * const pxARPFrame ) -{ -eFrameProcessingResult_t eReturn = eReleaseBuffer; -xARPHeader_t *pxARPHeader; - - pxARPHeader = &( pxARPFrame->xARPHeader ); - - traceARP_PACKET_RECEIVED(); - - /* Sanity check the protocol type. Don't do anything if the local IP - address is zero because that means a DHCP request has not completed. */ - if( ( pxARPHeader->usProtocolType == ipARP_PROTOCOL_TYPE ) && ( *ipLOCAL_IP_ADDRESS_POINTER != 0UL ) ) - { - switch( pxARPHeader->usOperation ) - { - case ipARP_REQUEST : - /* The packet contained an ARP request. Was it for the IP - address of the node running this code? */ - if( pxARPHeader->ulTargetProtocolAddress == *ipLOCAL_IP_ADDRESS_POINTER ) - { - iptraceSENDING_ARP_REPLY( pxARPHeader->ulSenderProtocolAddress ); - - /* The request is for the address of this node. Add the - entry into the ARP cache, or refresh the entry if it - already exists. */ - prvRefreshARPCacheEntry( &( pxARPHeader->xSenderHardwareAddress ), pxARPHeader->ulSenderProtocolAddress ); - - /* Generate a reply payload in the same buffer. */ - pxARPHeader->usOperation = ipARP_REPLY; - memcpy( ( void * ) &( pxARPHeader->xTargetHardwareAddress ), ( void * ) &( pxARPHeader->xSenderHardwareAddress ), sizeof( xMACAddress_t ) ); - pxARPHeader->ulTargetProtocolAddress = pxARPHeader->ulSenderProtocolAddress; - memcpy( ( void * ) &( pxARPHeader->xSenderHardwareAddress ), ( void * ) ipLOCAL_MAC_ADDRESS, sizeof( xMACAddress_t ) ); - pxARPHeader->ulSenderProtocolAddress = *ipLOCAL_IP_ADDRESS_POINTER; - - eReturn = eReturnEthernetFrame; - } - break; - - case ipARP_REPLY : - iptracePROCESSING_RECEIVED_ARP_REPLY( pxARPHeader->ulTargetProtocolAddress ); - prvRefreshARPCacheEntry( &( pxARPHeader->xSenderHardwareAddress ), pxARPHeader->ulSenderProtocolAddress ); - break; - - default : - /* Invalid. */ - break; - } - } - - return eReturn; -} -/*-----------------------------------------------------------*/ - -#if( ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN ) - uint16_t FreeRTOS_htons( uint16_t usIn ) - { - return ( ( usIn & ( uint16_t ) 0x00ff ) << ( uint16_t ) 8U ) | - ( ( usIn & ( uint16_t ) 0xff00 ) >> ( uint16_t ) 8U ); - } -#endif /* ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN */ -/*-----------------------------------------------------------*/ - -#if( ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN ) - uint32_t FreeRTOS_htonl( uint32_t ulIn ) - { - return ( ( ulIn & 0x000000ffUL ) << 24UL ) | - ( ( ulIn & 0x0000ff00UL ) << 8UL ) | - ( ( ulIn & 0x00ff0000UL ) >> 8UL ) | - ( ( ulIn & 0xff000000UL ) >> 24UL ); - } -#endif /* ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN */ - -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/History.txt b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/History.txt deleted file mode 100644 index 99f13203b..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/History.txt +++ /dev/null @@ -1,64 +0,0 @@ -Changes between V1.0.3 and V1.0.4 released - - + Update to use stdint and the FreeRTOS specific typedefs that were - introduced in FreeRTOS V8.0.0. - -Changes between V1.0.2 and V1.0.3 - - + Previously, and in line with good software engineering practice, the - FreeRTOS coding standard did not permit the use of char types that were - not explicitly qualified as either signed or unsigned. As a result char - pointers used to reference strings required casts, as did the use of any - standard string handling functions. The casts ensured compiler warnings - were not generated by compilers that defaulted unqualified char types to - be signed or compilers that defaulted unqualified char types to be - unsigned. As it has in later MISRA standards, this rule has now been - relaxed, and unqualified char types are now permitted, but only when: - 1) The char is used to point to a human readable text string. - 2) The char is used to hold a single ASCII character. - -Changes between V1.0.1 and V1.0.2 - - + Increase the size of the critical section in the function that obtains a - private port number. - + Add defaults for more trace macros. - + Update network interfaces so all compile with latest code revision. - + Added the following definitions for improved performance on hardware that - has the ability to offload checksum generation and/or checking: - ipconfigETHERNET_DRIVER_ADDS_UDP_CHECKSUM - ipconfigETHERNET_DRIVER_ADDS_IP_CHECKSUM - ipconfigETHERNET_DRIVER_CHECKS_IP_CHECKSUM - ipconfigETHERNET_DRIVER_CHECKS_UDP_CHECKSUM - -Changes between V1.0.0 and V1.0.1 - - + Set the broadcast flag in DHCP messages. - + Improve the DHCP standards compliance. - + Correct the check used to ensure the network event hook is not called for - the first network down event (which is generated by the stack itself). - + Allow sockets to be added to a set when they already have packets queued - waiting to be processed. - -Changes between V1.0.0 and V1.0.0 - - + Add select() function. - -Changes between V1.0.0rc1 and V1.0.0: - - + Correct name of prvCompleteUDPHeader(). - + Ensure network down events cannot be missed when the network event queue - to which they are posted is full. - + Only start the ARP timer when the network has connected. - + Remove initialisation call to the DHCP state machine - the call is made - directly when the network connects. - + Add the network event queue and the BufferAllocation_2.c counting - semaphore to the queue registry. - + Only initialise the DMA buffers in the lpc18xx_emac.c driver if the - autonegotiation was successful. - - Known issues in this version: - - + DHCP server attempts to copy the IP addresses of all the offered DNS - servers into a buffer than can only hold one address. - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/LICENSE_INFORMATION.txt b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/LICENSE_INFORMATION.txt deleted file mode 100644 index f67f5b812..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/LICENSE_INFORMATION.txt +++ /dev/null @@ -1,19 +0,0 @@ -FreeRTOS+UDP is released under the following MIT license. - -Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. -Permission is hereby granted, free of charge, to any person obtaining a copy of -this software and associated documentation files (the "Software"), to deal in -the Software without restriction, including without limitation the rights to -use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -the Software, and to permit persons to whom the Software is furnished to do so, -subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/ReadMe.url b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/ReadMe.url deleted file mode 100644 index 434898e55..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/ReadMe.url +++ /dev/null @@ -1,5 +0,0 @@ -[InternetShortcut] -URL=http://www.freertos.org/udp -IDList= -[{000214A0-0000-0000-C000-000000000046}] -Prop3=19,2 diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOSIPConfigDefaults.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOSIPConfigDefaults.h deleted file mode 100644 index 5edcd572e..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOSIPConfigDefaults.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef FREERTOS_DEFAULT_IP_CONFIG_H -#define FREERTOS_DEFAULT_IP_CONFIG_H - -/* This file provides default values for configuration options that are missing -from the FreeRTOSIPConfig.h configuration header file. */ - -#ifndef ipconfigUSE_NETWORK_EVENT_HOOK - #define ipconfigUSE_NETWORK_EVENT_HOOK 0 -#endif - -#ifndef ipconfigMAX_SEND_BLOCK_TIME_TICKS - #define ipconfigMAX_SEND_BLOCK_TIME_TICKS ( 20 / portTICK_RATE_MS ) -#endif - -#ifndef ipconfigARP_CACHE_ENTRIES - #define ipconfigARP_CACHE_ENTRIES 10 -#endif - -#ifndef ipconfigMAX_ARP_RETRANSMISSIONS - #define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 ) -#endif - -#ifndef ipconfigMAX_ARP_AGE - #define ipconfigMAX_ARP_AGE 150 -#endif - -#ifndef ipconfigINCLUDE_FULL_INET_ADDR - #define ipconfigINCLUDE_FULL_INET_ADDR 1 -#endif - -#ifndef ipconfigNUM_NETWORK_BUFFERS - #define ipconfigNUM_NETWORK_BUFFERS 45 -#endif - -#ifndef ipconfigEVENT_QUEUE_LENGTH - #define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFERS + 5 ) -#endif - -#ifndef ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND - #define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1 -#endif - -#ifndef updconfigIP_TIME_TO_LIVE - #define updconfigIP_TIME_TO_LIVE 128 -#endif - -#ifndef ipconfigCAN_FRAGMENT_OUTGOING_PACKETS - #define ipconfigCAN_FRAGMENT_OUTGOING_PACKETS 0 -#endif - -#ifndef ipconfigNETWORK_MTU - #define ipconfigNETWORK_MTU 1500 -#endif - -#ifndef ipconfigUSE_DHCP - #define ipconfigUSE_DHCP 1 -#endif - -#ifndef ipconfigMAXIMUM_DISCOVER_TX_PERIOD - #ifdef _WINDOWS_ - #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 999 / portTICK_RATE_MS ) - #else - #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 30000 / portTICK_RATE_MS ) - #endif /* _WINDOWS_ */ -#endif /* ipconfigMAXIMUM_DISCOVER_TX_PERIOD */ - -#ifndef ipconfigUSE_DNS - #define ipconfigUSE_DNS 1 -#endif - -#ifndef ipconfigREPLY_TO_INCOMING_PINGS - #define ipconfigREPLY_TO_INCOMING_PINGS 1 -#endif - -#ifndef ipconfigSUPPORT_OUTGOING_PINGS - #define ipconfigSUPPORT_OUTGOING_PINGS 0 -#endif - -#ifndef updconfigLOOPBACK_ETHERNET_PACKETS - #define updconfigLOOPBACK_ETHERNET_PACKETS 0 -#endif - -#ifndef ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES - #define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1 -#endif - -#ifndef ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES - #define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 1 -#endif - -#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS - #define ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS 0 -#else - #define ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS configINCLUDE_TRACE_RELATED_CLI_COMMANDS -#endif - -#ifndef ipconfigFREERTOS_PLUS_NABTO - #define ipconfigFREERTOS_PLUS_NABTO 0 -#endif - -#ifndef ipconfigNABTO_TASK_STACK_SIZE - #define ipconfigNABTO_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) -#endif - -#ifndef ipconfigNABTO_TASK_PRIORITY - #define ipconfigNABTO_TASK_PRIORITY ( ipconfigUDP_TASK_PRIORITY + 1 ) -#endif - -#ifndef ipconfigSUPPORT_SELECT_FUNCTION - #define ipconfigSUPPORT_SELECT_FUNCTION 0 -#endif - -#ifndef ipconfigETHERNET_DRIVER_ADDS_UDP_CHECKSUM - #define ipconfigETHERNET_DRIVER_ADDS_UDP_CHECKSUM 0 -#endif - -#ifndef ipconfigETHERNET_DRIVER_ADDS_IP_CHECKSUM - #define ipconfigETHERNET_DRIVER_ADDS_IP_CHECKSUM 0 -#endif - -#ifndef ipconfigETHERNET_DRIVER_CHECKS_IP_CHECKSUM - #define ipconfigETHERNET_DRIVER_CHECKS_IP_CHECKSUM 0 -#endif - -#ifndef ipconfigETHERNET_DRIVER_CHECKS_UDP_CHECKSUM - #define ipconfigETHERNET_DRIVER_CHECKS_UDP_CHECKSUM 0 -#endif - -#endif /* FREERTOS_DEFAULT_IP_CONFIG_H */ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_DHCP.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_DHCP.h deleted file mode 100644 index d311441e7..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_DHCP.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef FREERTOS_DHCP_H -#define FREERTOS_DHCP_H - -/* Application level configuration options. */ -#include "FreeRTOSIPConfig.h" -#include "IPTraceMacroDefaults.h" - -/* - * NOT A PUBLIC API FUNCTION. - */ -void vDHCPProcess( BaseType_t xReset, xMACAddress_t *pxMACAddress, uint32_t *pulIPAddress, xNetworkAddressingParameters_t *pxNetworkAddressing ); - -#endif /* FREERTOS_DHCP_H */ - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_DNS.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_DNS.h deleted file mode 100644 index b3f522154..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_DNS.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef FREERTOS_DNS_H -#define FREERTOS_DNS_H - -/* Application level configuration options. */ -#include "FreeRTOSIPConfig.h" -#include "IPTraceMacroDefaults.h" - -/** - * FULL, UP-TO-DATE AND MAINTAINED REFERENCE DOCUMENTATION FOR ALL THESE - * FUNCTIONS IS AVAILABLE ON THE FOLLOWING URL: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.shtml - */ -uint32_t FreeRTOS_gethostbyname( const char *pcHostName ); - -#endif /* FREERTOS_DNS_H */ - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_IP_Private.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_IP_Private.h deleted file mode 100644 index 3c8dda9a3..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_IP_Private.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef FREERTOS_IP_PRIVATE_H -#define FREERTOS_IP_PRIVATE_H - -/* Application level configuration options. */ -#include "FreeRTOSIPConfig.h" -#include "IPTraceMacroDefaults.h" - -typedef struct xNetworkAddressingParameters -{ - uint32_t ulDefaultIPAddress; - uint32_t ulNetMask; - uint32_t ulGatewayAddress; - uint32_t ulDNSServerAddress; -} xNetworkAddressingParameters_t; - - -/*-----------------------------------------------------------*/ -/* Protocol headers. */ -/*-----------------------------------------------------------*/ - -#include "pack_struct_start.h" -struct xETH_HEADER -{ - xMACAddress_t xDestinationAddress; - xMACAddress_t xSourceAddress; - uint16_t usFrameType; -} -#include "pack_struct_end.h" -typedef struct xETH_HEADER xEthernetHeader_t; - -#include "pack_struct_start.h" -struct xARP_HEADER -{ - uint16_t usHardwareType; - uint16_t usProtocolType; - uint8_t ucHardwareAddressLength; - uint8_t ucProtocolAddressLength; - uint16_t usOperation; - xMACAddress_t xSenderHardwareAddress; - uint32_t ulSenderProtocolAddress; - xMACAddress_t xTargetHardwareAddress; - uint32_t ulTargetProtocolAddress; -} -#include "pack_struct_end.h" -typedef struct xARP_HEADER xARPHeader_t; - -#include "pack_struct_start.h" -struct xIP_HEADER -{ - uint8_t ucVersionHeaderLength; - uint8_t ucDifferentiatedServicesCode; - uint16_t usLength; - uint16_t usIdentification; - uint16_t usFragmentOffset; - uint8_t ucTimeToLive; - uint8_t ucProtocol; - uint16_t usHeaderChecksum; - uint32_t ulSourceIPAddress; - uint32_t ulDestinationIPAddress; -} -#include "pack_struct_end.h" -typedef struct xIP_HEADER xIPHeader_t; -#define ipSIZE_OF_IP_HEADER 20 - -#include "pack_struct_start.h" -struct xICMP_HEADER -{ - uint8_t ucTypeOfMessage; - uint8_t ucTypeOfService; - uint16_t usChecksum; - uint16_t usIdentifier; - uint16_t usSequenceNumber; -} -#include "pack_struct_end.h" -typedef struct xICMP_HEADER xICMPHeader_t; - -#include "pack_struct_start.h" -struct xUDP_HEADER -{ - uint16_t usSourcePort; - uint16_t usDestinationPort; - uint16_t usLength; - uint16_t usChecksum; -} -#include "pack_struct_end.h" -typedef struct xUDP_HEADER xUDPHeader_t; -#define ipSIZE_OF_UDP_HEADER 8 - -#include "pack_struct_start.h" -struct xPSEUDO_HEADER -{ - uint32_t ulSourceAddress; - uint32_t ulDestinationAddress; - uint8_t ucZeros; - uint8_t ucProtocol; - uint16_t usUDPLength; -} -#include "pack_struct_end.h" -typedef struct xPSEUDO_HEADER xPseudoHeader_t; - -/*-----------------------------------------------------------*/ -/* Nested protocol packets. */ -/*-----------------------------------------------------------*/ - -#include "pack_struct_start.h" -struct xARP_PACKET -{ - xEthernetHeader_t xEthernetHeader; - xARPHeader_t xARPHeader; -} -#include "pack_struct_end.h" -typedef struct xARP_PACKET xARPPacket_t; - -#include "pack_struct_start.h" -struct xIP_PACKET -{ - xEthernetHeader_t xEthernetHeader; - xIPHeader_t xIPHeader; -} -#include "pack_struct_end.h" -typedef struct xIP_PACKET xIPPacket_t; - -#include "pack_struct_start.h" -struct xICMP_PACKET -{ - xEthernetHeader_t xEthernetHeader; - xIPHeader_t xIPHeader; - xICMPHeader_t xICMPHeader; -} -#include "pack_struct_end.h" -typedef struct xICMP_PACKET xICMPPacket_t; - -#include "pack_struct_start.h" -struct xUDP_PACKET -{ - xEthernetHeader_t xEthernetHeader; - xIPHeader_t xIPHeader; - xUDPHeader_t xUDPHeader; -} -#include "pack_struct_end.h" -typedef struct xUDP_PACKET xUDPPacket_t; - -/* Dimensions the buffers that are filled by received Ethernet frames. */ -#define ipETHERNET_CRC_BYTES ( 4UL ) -#define ipETHERNET_OPTIONAL_802_1Q_TAG_BYTES ( 4UL ) -#define ipTOTAL_ETHERNET_FRAME_SIZE ( ipconfigNETWORK_MTU + sizeof( xEthernetHeader_t ) + ipETHERNET_CRC_BYTES + ipETHERNET_OPTIONAL_802_1Q_TAG_BYTES ) - -/* The maximum UDP payload length. */ -#define ipMAX_UDP_PAYLOAD_LENGTH ( ( ipconfigNETWORK_MTU - ipSIZE_OF_IP_HEADER ) - ipSIZE_OF_UDP_HEADER ) - -typedef enum -{ - eReleaseBuffer = 0, /* Processing the frame did not find anything to do - just release the buffer. */ - eProcessBuffer, /* An Ethernet frame has a valid address - continue process its contents. */ - eReturnEthernetFrame, /* The Ethernet frame contains an ARP or ICMP packet that can be returned to its source. */ - eFrameConsumed /* Processing the Ethernet packet contents resulted in the payload being sent to the stack. */ -} eFrameProcessingResult_t; - -typedef enum -{ - eNetworkDownEvent = 0, /* The network interface has been lost and/or needs [re]connecting. */ - eEthernetRxEvent, /* The network interface has queued a received Ethernet frame. */ - eARPTimerEvent, /* The ARP timer expired. */ - eStackTxEvent, /* The software stack has queued a packet to transmit. */ - eDHCPEvent /* Process the DHCP state machine. */ -} eIPEvent_t; - -typedef struct IP_TASK_COMMANDS -{ - eIPEvent_t eEventType; - void *pvData; -} xIPStackEvent_t; - -#define ipBROADCAST_IP_ADDRESS 0xffffffffUL - -/* Offset into the Ethernet frame that is used to temporarily store information -on the fragmentation status of the packet being sent. The value is important, -as it is past the location into which the destination address will get placed. */ -#define ipFRAGMENTATION_PARAMETERS_OFFSET ( 6 ) -#define ipSOCKET_OPTIONS_OFFSET ( 6 ) - -/* Only used when outgoing fragmentation is being used (FreeRTOSIPConfig.h -setting. */ -#define ipGET_UDP_PAYLOAD_OFFSET_FOR_FRAGMENT( usFragmentOffset ) ( ( ( usFragmentOffset ) == 0 ) ? ipUDP_PAYLOAD_OFFSET : ipIP_PAYLOAD_OFFSET ) - -/* The offset into a UDP packet at which the UDP data (payload) starts. */ -#define ipUDP_PAYLOAD_OFFSET ( sizeof( xUDPPacket_t ) ) - -/* The offset into an IP packet into which the IP data (payload) starts. */ -#define ipIP_PAYLOAD_OFFSET ( sizeof( xIPPacket_t ) ) - -/* Space left at the beginning of a network buffer storage area to store a -pointer back to the network buffer. Should be a multiple of 8 to ensure -8 byte alignment is maintained on architectures that require it. */ -#define ipBUFFER_PADDING ( 8 ) - -#include "pack_struct_start.h" -struct xUDP_IP_FRACMENT_PARAMETERS -{ - uint8_t ucSocketOptions; - uint8_t ucPadFor16BitAlignment; - uint16_t usFragmentedPacketOffset; - uint16_t usFragmentLength; - uint16_t usPayloadChecksum; -} -#include "pack_struct_end.h" -typedef struct xUDP_IP_FRACMENT_PARAMETERS xIPFragmentParameters_t; - -#if( ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN ) - - /* Ethernet frame types. */ - #define ipARP_TYPE ( 0x0608U ) - #define ipIP_TYPE ( 0x0008U ) - - /* ARP related definitions. */ - #define ipARP_PROTOCOL_TYPE ( 0x0008U ) - #define ipARP_HARDWARE_TYPE_ETHERNET ( 0x0100U ) - #define ipARP_REQUEST ( 0x0100 ) - #define ipARP_REPLY ( 0x0200 ) - -#else - - /* Ethernet frame types. */ - #define ipARP_TYPE ( 0x0806U ) - #define ipIP_TYPE ( 0x0800U ) - - /* ARP related definitions. */ - #define ipARP_PROTOCOL_TYPE ( 0x0800U ) - #define ipARP_HARDWARE_TYPE_ETHERNET ( 0x0001U ) - #define ipARP_REQUEST ( 0x0001 ) - #define ipARP_REPLY ( 0x0002 ) - -#endif /* ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN */ - -/* The structure used to store buffers and pass them around the network stack. -Buffers can be in use by the stack, in use by the network interface hardware -driver, or free (not in use). */ -typedef struct xNETWORK_BUFFER -{ - xListItem xBufferListItem; /* Used to reference the buffer form the free buffer list or a socket. */ - uint32_t ulIPAddress; /* Source or destination IP address, depending on usage scenario. */ - uint8_t *pucEthernetBuffer; /* Pointer to the start of the Ethernet frame. */ - size_t xDataLength; /* Starts by holding the total Ethernet frame length, then the UDP payload length. */ - uint16_t usPort; /* Source or destination port, depending on usage scenario. */ - uint16_t usBoundPort; /* The port to which a transmitting socket is bound. */ -} xNetworkBufferDescriptor_t; - -void vNetworkBufferRelease( xNetworkBufferDescriptor_t * const pxNetworkBuffer ); - -/* - * A version of FreeRTOS_GetReleaseNetworkBuffer() that can be called from an - * interrupt. If a non zero value is returned, then the calling ISR should - * perform a context switch before exiting the ISR. - */ -BaseType_t FreeRTOS_ReleaseFreeNetworkBufferFromISR( void ); - -/* - * Create a message that contains a command to initialise the network interface. - * This is used during initialisation, and at any time the network interface - * goes down thereafter. The network interface hardware driver is responsible - * for sending the message that contains the network interface down command/ - * event. - * - * Only use the FreeRTOS_NetworkDownFromISR() version if the function is to be - * called from an interrupt service routine. If FreeRTOS_NetworkDownFromISR() - * returns a non-zero value then a context switch should be performed ebfore - * the interrupt is exited. - */ -void FreeRTOS_NetworkDown( void ); -BaseType_t FreeRTOS_NetworkDownFromISR( void ); - -/* - * Inspect an Ethernet frame to see if it contains data that the stack needs to - * process. eProcessBuffer is returned if the frame should be processed by the - * stack. eReleaseBuffer is returned if the frame should be discarded. - */ -eFrameProcessingResult_t eConsiderFrameForProcessing( const uint8_t * const pucEthernetBuffer ); - -#if( ipconfigINCLUDE_TEST_CODE == 1 ) - UBaseType_t uxGetNumberOfFreeNetworkBuffers( void ); -#endif /* ipconfigINCLUDE_TEST_CODE */ - -/* Socket related private functions. */ -BaseType_t xProcessReceivedUDPPacket( xNetworkBufferDescriptor_t *pxNetworkBuffer, uint16_t usPort ); -void FreeRTOS_SocketsInit( void ); - -/* If FreeRTOS+NABTO is included then include the prototype of the function that -creates the Nabto task. */ -#if( ipconfigFREERTOS_PLUS_NABTO == 1 ) - void vStartNabtoTask( void ); -#endif - - -#endif /* FREERTOS_IP_PRIVATE_H */ - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_Sockets.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_Sockets.h deleted file mode 100644 index 5fb5417c0..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_Sockets.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef FREERTOS_UDP_H -#define FREERTOS_UDP_H - -/* Standard includes. */ -#include - -/* Application level configuration options. */ -#include "FreeRTOSIPConfig.h" - -#ifndef INC_FREERTOS_H - #error FreeRTOS.h must be included before FreeRTOS_Sockets.h. -#endif - -#ifndef INC_TASK_H - #ifndef TASK_H /* For compatibility with older FreeRTOS versions. */ - #error The FreeRTOS header file task.h must be included before FreeRTOS_Sockets.h. - #endif -#endif - -/* Assigned to an xSocket_t variable when the socket is not valid, probably -because it could not be created. */ -#define FREERTOS_INVALID_SOCKET ( ( void * ) ~0U ) - -/* API function error values. As errno is supported, the FreeRTOS sockets -functions return error codes rather than just a pass or fail indication. */ -#define FREERTOS_SOCKET_ERROR ( -1 ) -#define FREERTOS_EWOULDBLOCK ( -2 ) -#define FREERTOS_EINVAL ( -4 ) -#define FREERTOS_EADDRNOTAVAIL ( -5 ) -#define FREERTOS_EADDRINUSE ( -6 ) -#define FREERTOS_ENOBUFS ( -7 ) -#define FREERTOS_ENOPROTOOPT ( -8 ) - -/* Values for the parameters to FreeRTOS_socket(), inline with the Berkeley -standard. See the documentation of FreeRTOS_socket() for more information. */ -#define FREERTOS_AF_INET ( 2 ) -#define FREERTOS_SOCK_DGRAM ( 2 ) -#define FREERTOS_IPPROTO_UDP ( 17 ) - -/* A bit value that can be passed into the FreeRTOS_sendto() function as part of -the flags parameter. Setting the FREERTOS_ZERO_COPY in the flags parameter -indicates that the zero copy interface is being used. See the documentation for -FreeRTOS_sockets() for more information. */ -#define FREERTOS_ZERO_COPY ( 0x01UL ) - -/* Values that can be passed in the option name parameter of calls to -FreeRTOS_setsockopt(). */ -#define FREERTOS_SO_RCVTIMEO ( 0 ) /* Used to set the receive time out. */ -#define FREERTOS_SO_SNDTIMEO ( 1 ) /* Used to set the send time out. */ -#define FREERTOS_SO_UDPCKSUM_OUT ( 0x02 ) /* Used to turn the use of the UDP checksum by a socket on or off. This also doubles as part of an 8-bit bitwise socket option. */ -#define FREERTOS_NOT_LAST_IN_FRAGMENTED_PACKET ( 0x80 ) /* For internal use only, but also part of an 8-bit bitwise value. */ -#define FREERTOS_FRAGMENTED_PACKET ( 0x40 ) /* For internal use only, but also part of an 8-bit bitwise value. */ - -/* For compatibility with the expected Berkeley sockets naming. */ -#define socklen_t uint32_t - -/* For this limited implementation, only two members are required in the -Berkeley style sockaddr structure. */ -struct freertos_sockaddr -{ - uint16_t sin_port; - uint32_t sin_addr; -}; - -#if ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN - - #define FreeRTOS_inet_addr_quick( ucOctet0, ucOctet1, ucOctet2, ucOctet3 ) \ - ( ( ( ( uint32_t ) ( ucOctet3 ) ) << 24UL ) | \ - ( ( ( uint32_t ) ( ucOctet2 ) ) << 16UL ) | \ - ( ( ( uint32_t ) ( ucOctet1 ) ) << 8UL ) | \ - ( ( uint32_t ) ( ucOctet0 ) ) ) - - #define FreeRTOS_inet_ntoa( ulIPAddress, pucBuffer ) \ - sprintf( ( char * ) ( pucBuffer ), "%d.%d.%d.%d", \ - ( int ) ( ( ulIPAddress ) & 0xffUL ), \ - ( int ) ( ( ( ulIPAddress ) >> 8UL ) & 0xffUL ),\ - ( int ) ( ( ( ulIPAddress ) >> 16UL ) & 0xffUL ),\ - ( int ) ( ( ( ulIPAddress ) >> 24UL ) & 0xffUL ) ) - -#else /* ipconfigBYTE_ORDER */ - - #define FreeRTOS_inet_addr_quick( ucOctet0, ucOctet1, ucOctet2, ucOctet3 ) \ - ( ( ( ( uint32_t ) ( ucOctet0 ) ) << 24UL ) | \ - ( ( ( uint32_t ) ( ucOctet1 ) ) << 16UL ) | \ - ( ( ( uint32_t ) ( ucOctet2 ) ) << 8UL ) | \ - ( ( uint32_t ) ( ucOctet3 ) ) ) - - #define FreeRTOS_inet_ntoa( ulIPAddress, pucBuffer ) \ - sprintf( ( char * ) ( pucBuffer ), "%d.%d.%d.%d", \ - ( ( ( ulIPAddress ) >> 24UL ) & 0xffUL ), \ - ( ( ( ulIPAddress ) >> 16UL ) & 0xffUL ), \ - ( ( ( ulIPAddress ) >> 8UL ) & 0xffUL ), \ - ( ( ulIPAddress ) & 0xffUL ) ) - -#endif /* ipconfigBYTE_ORDER */ - -/* The socket type itself. */ -typedef void *xSocket_t; - -/* The xSocketSet_t type is the equivalent to the fd_set type used by the -Berkeley API. */ -typedef void *xSocketSet_t; - -/** - * FULL, UP-TO-DATE AND MAINTAINED REFERENCE DOCUMENTATION FOR ALL THESE - * FUNCTIONS IS AVAILABLE ON THE FOLLOWING URL: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.shtml - */ -xSocket_t FreeRTOS_socket( BaseType_t xDomain, BaseType_t xType, BaseType_t xProtocol ); -int32_t FreeRTOS_recvfrom( xSocket_t xSocket, void *pvBuffer, size_t xBufferLength, uint32_t ulFlags, struct freertos_sockaddr *pxSourceAddress, socklen_t *pxSourceAddressLength ); -int32_t FreeRTOS_sendto( xSocket_t xSocket, const void *pvBuffer, size_t xTotalDataLength, uint32_t ulFlags, const struct freertos_sockaddr *pxDestinationAddress, socklen_t xDestinationAddressLength ); -BaseType_t FreeRTOS_bind( xSocket_t xSocket, struct freertos_sockaddr *pxAddress, socklen_t xAddressLength ); -BaseType_t FreeRTOS_setsockopt( xSocket_t xSocket, int32_t lLevel, int32_t lOptionName, const void *pvOptionValue, size_t xOptionLength ); -BaseType_t FreeRTOS_closesocket( xSocket_t xSocket ); -uint32_t FreeRTOS_gethostbyname( const char *pcHostName ); -uint32_t FreeRTOS_inet_addr( const char *pcIPAddress ); - -#if ipconfigSUPPORT_SELECT_FUNCTION == 1 - xSocketSet_t FreeRTOS_CreateSocketSet( UBaseType_t uxEventQueueLength ); - BaseType_t FreeRTOS_FD_SET( xSocket_t xSocket, xSocketSet_t xSocketSet ); - BaseType_t FreeRTOS_FD_CLR( xSocket_t xSocket, xSocketSet_t xSocketSet ); - xSocket_t FreeRTOS_select( xSocketSet_t xSocketSet, TickType_t xBlockTimeTicks ); -#endif /* ipconfigSUPPORT_SELECT_FUNCTION */ - -#endif /* FREERTOS_UDP_H */ - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_UDP_IP.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_UDP_IP.h deleted file mode 100644 index a3cc13ebe..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/FreeRTOS_UDP_IP.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef FREERTOS_IP_H -#define FREERTOS_IP_H - -/* Use in FreeRTOSIPConfig.h. */ -#define FREERTOS_LITTLE_ENDIAN 0 -#define FREERTOS_BIG_ENDIAN 1 - -/* Application level configuration options. */ -#include "FreeRTOSIPConfig.h" -#include "FreeRTOSIPConfigDefaults.h" -#include "IPTraceMacroDefaults.h" - -/* The number of octets in the MAC and IP addresses respectively. */ -#define ipMAC_ADDRESS_LENGTH_BYTES ( 6 ) -#define ipIP_ADDRESS_LENGTH_BYTES ( 4 ) - -#include "pack_struct_start.h" -struct xMAC_ADDRESS -{ - uint8_t ucBytes[ ipMAC_ADDRESS_LENGTH_BYTES ]; -} -#include "pack_struct_end.h" -typedef struct xMAC_ADDRESS xMACAddress_t; - -typedef enum eNETWORK_EVENTS -{ - eNetworkUp, /* The network is configured. */ - eNetworkDown /* The network connection has been lost. */ -} eIPCallbackEvent_t; - -typedef enum ePING_REPLY_STATUS -{ - eSuccess = 0, /* A correct reply has been received for an outgoing ping. */ - eInvalidChecksum, /* A reply was received for an outgoing ping but the checksum of the reply was incorrect. */ - eInvalidData /* A reply was received to an outgoing ping but the payload of the reply was not correct. */ -} ePingReplyStatus_t; - -/* Endian related definitions. */ -#if( ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN ) - - uint16_t FreeRTOS_htons( uint16_t usIn ); - uint32_t FreeRTOS_htonl( uint32_t ulIn ); - -#else - - #define FreeRTOS_htons( x ) ( x ) - #define FreeRTOS_htonl( x ) ( x ) - -#endif /* ipconfigBYTE_ORDER == FREERTOS_LITTLE_ENDIAN */ - -#define FreeRTOS_ntohs( x ) FreeRTOS_htons( x ) -#define FreeRTOS_ntohl( x ) FreeRTOS_htonl( x ) - -/** - * FULL, UP-TO-DATE AND MAINTAINED REFERENCE DOCUMENTATION FOR ALL THESE - * FUNCTIONS IS AVAILABLE ON THE FOLLOWING URL: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.shtml - */ -BaseType_t FreeRTOS_IPInit( const uint8_t ucIPAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucNetMask[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucGatewayAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucDNSServerAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucMACAddress[ ipMAC_ADDRESS_LENGTH_BYTES ] ); -void * FreeRTOS_GetUDPPayloadBuffer( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ); -void FreeRTOS_GetAddressConfiguration( uint32_t *pulIPAddress, uint32_t *pulNetMask, uint32_t *pulGatewayAddress, uint32_t *pulDNSServerAddress ); -BaseType_t FreeRTOS_SendPingRequest( uint32_t ulIPAddress, size_t xNumberOfBytesToSend, TickType_t xBlockTimeTicks ); -void vApplicationIPNetworkEventHook( eIPCallbackEvent_t eNetworkEvent ); -void vApplicationPingReplyHook( ePingReplyStatus_t eStatus, uint16_t usIdentifier ); -void FreeRTOS_ReleaseUDPPayloadBuffer( void *pvBuffer ); -uint8_t * FreeRTOS_GetMACAddress( void ); - -#if ( ipconfigFREERTOS_PLUS_NABTO == 1 ) - BaseType_t xStartNabtoTask( void ); -#endif - -#endif /* FREERTOS_IP_H */ - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/IPTraceMacroDefaults.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/IPTraceMacroDefaults.h deleted file mode 100644 index 394cac5d7..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/IPTraceMacroDefaults.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* This file provides default (empty) implementations for any IP trace macros -that are not defined by the user. See -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml */ - -#ifndef UDP_TRACE_MACRO_DEFAULTS_H -#define UDP_TRACE_MACRO_DEFAULTS_H - -#ifndef iptraceNETWORK_DOWN - #define iptraceNETWORK_DOWN() -#endif - -#ifndef iptraceNETWORK_BUFFER_RELEASED - #define iptraceNETWORK_BUFFER_RELEASED( pxBufferAddress ) -#endif - -#ifndef iptraceNETWORK_BUFFER_OBTAINED - #define iptraceNETWORK_BUFFER_OBTAINED( pxBufferAddress ) -#endif - -#ifndef iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR - #define iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxBufferAddress ) -#endif - -#ifndef iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER - #define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER() -#endif - -#ifndef iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER_FROM_ISR - #define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER_FROM_ISR() -#endif - -#ifndef iptraceCREATING_ARP_REQUEST - #define iptraceCREATING_ARP_REQUEST( ulIPAddress ) -#endif - -#ifndef iptraceARP_TABLE_ENTRY_WILL_EXPIRE - #define iptraceARP_TABLE_ENTRY_WILL_EXPIRE( ulIPAddress ) -#endif - -#ifndef iptraceARP_TABLE_ENTRY_EXPIRED - #define iptraceARP_TABLE_ENTRY_EXPIRED( ulIPAddress ) -#endif - -#ifndef iptraceARP_TABLE_ENTRY_CREATED - #define iptraceARP_TABLE_ENTRY_CREATED( ulIPAddress, ucMACAddress ) -#endif - -#ifndef iptraceSENDING_UDP_PACKET - #define iptraceSENDING_UDP_PACKET( ulIPAddress ) -#endif - -#ifndef iptracePACKET_DROPPED_TO_GENERATE_ARP - #define iptracePACKET_DROPPED_TO_GENERATE_ARP( ulIPAddress ) -#endif - -#ifndef iptraceICMP_PACKET_RECEIVED - #define iptraceICMP_PACKET_RECEIVED() -#endif - -#ifndef iptraceSENDING_PING_REPLY - #define iptraceSENDING_PING_REPLY( ulIPAddress ) -#endif - -#ifndef traceARP_PACKET_RECEIVED - #define traceARP_PACKET_RECEIVED() -#endif - -#ifndef iptracePROCESSING_RECEIVED_ARP_REPLY - #define iptracePROCESSING_RECEIVED_ARP_REPLY( ulIPAddress ) -#endif - -#ifndef iptraceSENDING_ARP_REPLY - #define iptraceSENDING_ARP_REPLY( ulIPAddress ) -#endif - -#ifndef iptraceFAILED_TO_CREATE_SOCKET - #define iptraceFAILED_TO_CREATE_SOCKET() -#endif - -#ifndef iptraceRECVFROM_DISCARDING_BYTES - #define iptraceRECVFROM_DISCARDING_BYTES( xNumberOfBytesDiscarded ) -#endif - -#ifndef iptraceETHERNET_RX_EVENT_LOST - #define iptraceETHERNET_RX_EVENT_LOST() -#endif - -#ifndef iptraceSTACK_TX_EVENT_LOST - #define iptraceSTACK_TX_EVENT_LOST( xEvent ) -#endif - -#ifndef iptraceNETWORK_EVENT_RECEIVED - #define iptraceNETWORK_EVENT_RECEIVED( eEvent ) -#endif - -#ifndef iptraceBIND_FAILED - #define iptraceBIND_FAILED( xSocket, usPort ) -#endif - -#ifndef iptraceDHCP_REQUESTS_FAILED_USING_DEFAULT_IP_ADDRESS - #define iptraceDHCP_REQUESTS_FAILED_USING_DEFAULT_IP_ADDRESS( ulIPAddress ) -#endif - -#ifndef iptraceSENDING_DHCP_DISCOVER - #define iptraceSENDING_DHCP_DISCOVER() -#endif - -#ifndef iptraceSENDING_DHCP_REQUEST - #define iptraceSENDING_DHCP_REQUEST() -#endif - -#ifndef iptraceNETWORK_INTERFACE_TRANSMIT - #define iptraceNETWORK_INTERFACE_TRANSMIT() -#endif - -#ifndef iptraceNETWORK_INTERFACE_RECEIVE - #define iptraceNETWORK_INTERFACE_RECEIVE() -#endif - -#ifndef iptraceSENDING_DNS_REQUEST - #define iptraceSENDING_DNS_REQUEST() -#endif - -#ifndef iptraceWAITING_FOR_TX_DMA_DESCRIPTOR - #define iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() -#endif - -#ifndef ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS - #define ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS 0 -#endif - -#ifndef iptraceFAILED_TO_NOTIFY_SELECT_GROUP - #define iptraceFAILED_TO_NOTIFY_SELECT_GROUP( xSocket ) -#endif - -#ifndef iptraceRECVFROM_TIMEOUT - #define iptraceRECVFROM_TIMEOUT() -#endif - -#ifndef iptraceNO_BUFFER_FOR_SENDTO - #define iptraceNO_BUFFER_FOR_SENDTO() -#endif - -#ifndef iptraceSENDTO_SOCKET_NOT_BOUND - #define iptraceSENDTO_SOCKET_NOT_BOUND() -#endif - -#ifndef iptraceSENDTO_DATA_TOO_LONG - #define iptraceSENDTO_DATA_TOO_LONG() -#endif - -#endif /* UDP_TRACE_MACRO_DEFAULTS_H */ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/NetworkBufferManagement.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/NetworkBufferManagement.h deleted file mode 100644 index 5be505603..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/NetworkBufferManagement.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef NETWORK_BUFFER_MANAGEMENT_H -#define NETWORK_BUFFER_MANAGEMENT_H - -/* NOTE PUBLIC API FUNCTIONS. */ -BaseType_t xNetworkBuffersInitialise( void ); -xNetworkBufferDescriptor_t *pxNetworkBufferGet( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ); -xNetworkBufferDescriptor_t *pxNetworkBufferGetFromISR( size_t xRequestedSizeBytes ); -void vNetworkBufferRelease( xNetworkBufferDescriptor_t * const pxNetworkBuffer ); -BaseType_t vNetworkBufferReleaseFromISR( xNetworkBufferDescriptor_t * const pxNetworkBuffer ); -uint8_t *pucEthernetBufferGet( size_t *pxRequestedSizeBytes ); -void vEthernetBufferRelease( uint8_t *pucEthernetBuffer ); - -#endif /* NETWORK_BUFFER_MANAGEMENT_H */ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/NetworkInterface.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/NetworkInterface.h deleted file mode 100644 index 7dae4c80a..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include/NetworkInterface.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef NETWORK_INTERFACE_H -#define NETWORK_INTERFACE_H - -/* NOTE PUBLIC API FUNCTIONS. */ -BaseType_t xNetworkInterfaceInitialise( void ); -BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer ); -void vNetworkInterfaceAllocateRAMToBuffers( xNetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFERS ] ); - -#endif /* NETWORK_INTERFACE_H */ - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_1.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_1.c deleted file mode 100644 index fbd7eb66a..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_1.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -/****************************************************************************** - * - * See the following web page for essential buffer allocation scheme usage and - * configuration details: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Buffer_Management.shtml - * - ******************************************************************************/ - - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "NetworkInterface.h" - -/* For an Ethernet interrupt to be able to obtain a network buffer there must -be at least this number of buffers available. */ -#define ipINTERRUPT_BUFFER_GET_THRESHOLD ( 3 ) - -/* A list of free (available) xNetworkBufferDescriptor_t structures. */ -static xList xFreeBuffersList; - -/* Declares the pool of xNetworkBufferDescriptor_t structures that are available to the -system. All the network buffers referenced from xFreeBuffersList exist in this -array. The array is not accessed directly except during initialisation, when -the xFreeBuffersList is filled (as all the buffers are free when the system is -booted). */ -static xNetworkBufferDescriptor_t xNetworkBuffers[ ipconfigNUM_NETWORK_BUFFERS ]; - -/* The semaphore used to obtain network buffers. */ -static xSemaphoreHandle xNetworkBufferSemaphore = NULL; - -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkBuffersInitialise( void ) -{ -BaseType_t xReturn, x; - - /* Only initialise the buffers and their associated kernel objects if they - have not been initialised before. */ - if( xNetworkBufferSemaphore == NULL ) - { - xNetworkBufferSemaphore = xSemaphoreCreateCounting( ipconfigNUM_NETWORK_BUFFERS, ipconfigNUM_NETWORK_BUFFERS ); - configASSERT( xNetworkBufferSemaphore ); - - if( xNetworkBufferSemaphore != NULL ) - { - vListInitialise( &xFreeBuffersList ); - - /* Initialise all the network buffers. The buffer storage comes - from the network interface, and different hardware has different - requirements. */ - vNetworkInterfaceAllocateRAMToBuffers( xNetworkBuffers ); - for( x = 0; x < ipconfigNUM_NETWORK_BUFFERS; x++ ) - { - /* Initialise and set the owner of the buffer list items. */ - vListInitialiseItem( &( xNetworkBuffers[ x ].xBufferListItem ) ); - listSET_LIST_ITEM_OWNER( &( xNetworkBuffers[ x ].xBufferListItem ), &xNetworkBuffers[ x ] ); - - /* Currently, all buffers are available for use. */ - vListInsert( &xFreeBuffersList, &( xNetworkBuffers[ x ].xBufferListItem ) ); - } - } - } - - if( xNetworkBufferSemaphore == NULL ) - { - xReturn = pdFAIL; - } - else - { - xReturn = pdPASS; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -xNetworkBufferDescriptor_t *pxNetworkBufferGet( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ) -{ -xNetworkBufferDescriptor_t *pxReturn = NULL; - - /*_RB_ The current implementation only has a single size memory block, so - the requested size parameter is not used (yet). */ - ( void ) xRequestedSizeBytes; - - /* If there is a semaphore available, there is a network buffer available. */ - if( xSemaphoreTake( xNetworkBufferSemaphore, xBlockTimeTicks ) == pdPASS ) - { - /* Protect the structure as it is accessed from tasks and interrupts. */ - taskENTER_CRITICAL(); - { - pxReturn = ( xNetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList ); - uxListRemove( &( pxReturn->xBufferListItem ) ); - } - taskEXIT_CRITICAL(); - iptraceNETWORK_BUFFER_OBTAINED( pxReturn ); - } - else - { - iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER(); - } - - return pxReturn; -} -/*-----------------------------------------------------------*/ - -xNetworkBufferDescriptor_t *pxNetworkBufferGetFromISR( size_t xRequestedSizeBytes ) -{ -xNetworkBufferDescriptor_t *pxReturn = NULL; -UBaseType_t uxSavedInterruptStatus; - - /*_RB_ The current implementation only has a single size memory block, so - the requested size parameter is not used (yet). */ - ( void ) xRequestedSizeBytes; - - /* If there is a semaphore available then there is a buffer available, but, - as this is called from an interrupt, only take a buffer if there are at - least ipINTERRUPT_BUFFER_GET_THRESHOLD buffers remaining. This prevents, - to a certain degree at least, a rapidly executing interrupt exhausting - buffer and in so doing preventing tasks from continuing. */ - if( uxQueueMessagesWaitingFromISR( ( xQueueHandle ) xNetworkBufferSemaphore ) > ipINTERRUPT_BUFFER_GET_THRESHOLD ) - { - if( xSemaphoreTakeFromISR( xNetworkBufferSemaphore, NULL ) == pdPASS ) - { - /* Protect the structure as it is accessed from tasks and interrupts. */ - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - { - pxReturn = ( xNetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList ); - uxListRemove( &( pxReturn->xBufferListItem ) ); - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); - - iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxReturn ); - } - } - - if( pxReturn == NULL ) - { - iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER_FROM_ISR(); - } - - return pxReturn; -} -/*-----------------------------------------------------------*/ - -BaseType_t vNetworkBufferReleaseFromISR( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -UBaseType_t uxSavedInterruptStatus; -BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - /* Ensure the buffer is returned to the list of free buffers before the - counting semaphore is 'given' to say a buffer is available. */ - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - { - vListInsertEnd( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); - - xSemaphoreGiveFromISR( xNetworkBufferSemaphore, &xHigherPriorityTaskWoken ); - iptraceNETWORK_BUFFER_RELEASED( pxNetworkBuffer ); - - return xHigherPriorityTaskWoken; -} -/*-----------------------------------------------------------*/ - -void vNetworkBufferRelease( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -BaseType_t xListItemAlreadyInFreeList; - - /* Ensure the buffer is returned to the list of free buffers before the - counting semaphore is 'given' to say a buffer is available. */ - taskENTER_CRITICAL(); - { - xListItemAlreadyInFreeList = listIS_CONTAINED_WITHIN( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); - - if( xListItemAlreadyInFreeList == pdFALSE ) - { - vListInsertEnd( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); - } - - configASSERT( xListItemAlreadyInFreeList == pdFALSE ); - } - taskEXIT_CRITICAL(); - - xSemaphoreGive( xNetworkBufferSemaphore ); - iptraceNETWORK_BUFFER_RELEASED( pxNetworkBuffer ); -} -/*-----------------------------------------------------------*/ - -#if( ipconfigINCLUDE_TEST_CODE == 1 ) - -UBaseType_t uxGetNumberOfFreeNetworkBuffers( void ) -{ - return listCURRENT_LIST_LENGTH( &xFreeBuffersList ); -} - -#endif /* ipconfigINCLUDE_TEST_CODE */ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_2.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_2.c deleted file mode 100644 index 7fa5779fb..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_2.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/****************************************************************************** - * - * See the following web page for essential buffer allocation scheme usage and - * configuration details: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Buffer_Management.shtml - * - ******************************************************************************/ - -/* THIS FILE SHOULD NOT BE USED IF THE PROJECT INCLUDES A MEMORY ALLOCATOR -THAT WILL FRAGMENT THE HEAP MEMORY. For example, heap_2 must not be used, -heap_4 can be used. */ - - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "NetworkInterface.h" - -/* For an Ethernet interrupt to be able to obtain a network buffer there must -be at least this number of buffers available. */ -#define ipINTERRUPT_BUFFER_GET_THRESHOLD ( 3 ) - -/* A list of free (available) xNetworkBufferDescriptor_t structures. */ -static xList xFreeBuffersList; - -/* Declares the pool of xNetworkBufferDescriptor_t structures that are available to the -system. All the network buffers referenced from xFreeBuffersList exist in this -array. The array is not accessed directly except during initialisation, when -the xFreeBuffersList is filled (as all the buffers are free when the system is -booted). */ -static xNetworkBufferDescriptor_t xNetworkBuffers[ ipconfigNUM_NETWORK_BUFFERS ]; - -/* The semaphore used to obtain network buffers. */ -static xSemaphoreHandle xNetworkBufferSemaphore = NULL; - -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkBuffersInitialise( void ) -{ -BaseType_t xReturn, x; - - /* Only initialise the buffers and their associated kernel objects if they - have not been initialised before. */ - if( xNetworkBufferSemaphore == NULL ) - { - xNetworkBufferSemaphore = xSemaphoreCreateCounting( ipconfigNUM_NETWORK_BUFFERS, ipconfigNUM_NETWORK_BUFFERS ); - configASSERT( xNetworkBufferSemaphore ); - vQueueAddToRegistry( xNetworkBufferSemaphore, "NetBufSem" ); - - /* If the trace recorder code is included name the semaphore for viewing - in FreeRTOS+Trace. */ - #if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 - { - extern xQueueHandle xNetworkEventQueue; - vTraceSetQueueName( xNetworkEventQueue, "IPStackEvent" ); - vTraceSetQueueName( xNetworkBufferSemaphore, "NetworkBufferCount" ); - } - #endif /* ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 */ - - if( xNetworkBufferSemaphore != NULL ) - { - vListInitialise( &xFreeBuffersList ); - - /* Initialise all the network buffers. No storage is allocated to - the buffers yet. */ - for( x = 0; x < ipconfigNUM_NETWORK_BUFFERS; x++ ) - { - /* Initialise and set the owner of the buffer list items. */ - xNetworkBuffers[ x ].pucEthernetBuffer = NULL; - vListInitialiseItem( &( xNetworkBuffers[ x ].xBufferListItem ) ); - listSET_LIST_ITEM_OWNER( &( xNetworkBuffers[ x ].xBufferListItem ), &xNetworkBuffers[ x ] ); - - /* Currently, all buffers are available for use. */ - vListInsert( &xFreeBuffersList, &( xNetworkBuffers[ x ].xBufferListItem ) ); - } - } - } - - if( xNetworkBufferSemaphore == NULL ) - { - xReturn = pdFAIL; - } - else - { - xReturn = pdPASS; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -uint8_t *pucEthernetBufferGet( size_t *pxRequestedSizeBytes ) -{ -uint8_t *pucEthernetBuffer; - - if( *pxRequestedSizeBytes < sizeof( xARPPacket_t ) ) - { - /* Buffers must be at least large enough to hold ARP packets, otherwise - nothing can be done. */ - *pxRequestedSizeBytes = sizeof( xARPPacket_t ); - } - - /* Allocate a buffer large enough to store the requested Ethernet frame size - and a pointer to a network buffer structure (hence the addition of - ipBUFFER_PADDING bytes). */ - pucEthernetBuffer = ( uint8_t * ) pvPortMalloc( *pxRequestedSizeBytes + ipBUFFER_PADDING ); - - /* Enough space is left at the start of the buffer to place a pointer to - the network buffer structure that references this Ethernet buffer. Return - a pointer to the start of the Ethernet buffer itself. */ - pucEthernetBuffer += ipBUFFER_PADDING; - - return pucEthernetBuffer; -} -/*-----------------------------------------------------------*/ - -void vEthernetBufferRelease( uint8_t *pucEthernetBuffer ) -{ - /* There is space before the Ethernet buffer in which a pointer to the - network buffer that references this Ethernet buffer is stored. Remove the - space before freeing the buffer. */ - if( pucEthernetBuffer != NULL ) - { - pucEthernetBuffer -= ipBUFFER_PADDING; - vPortFree( ( void * ) pucEthernetBuffer ); - } -} -/*-----------------------------------------------------------*/ - -xNetworkBufferDescriptor_t *pxNetworkBufferGet( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ) -{ -xNetworkBufferDescriptor_t *pxReturn = NULL; - - if( ( xRequestedSizeBytes != 0 ) && ( xRequestedSizeBytes < sizeof( xARPPacket_t ) ) ) - { - /* ARP packets can replace application packets, so the storage must be - at least large enough to hold an ARP. */ - xRequestedSizeBytes = sizeof( xARPPacket_t ); - } - - /* If there is a semaphore available, there is a network buffer available. */ - if( xSemaphoreTake( xNetworkBufferSemaphore, xBlockTimeTicks ) == pdPASS ) - { - /* Protect the structure as it is accessed from tasks and interrupts. */ - taskENTER_CRITICAL(); - { - pxReturn = ( xNetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList ); - uxListRemove( &( pxReturn->xBufferListItem ) ); - } - taskEXIT_CRITICAL(); - - /* Allocate storage of exactly the requested size to the buffer. */ - configASSERT( pxReturn->pucEthernetBuffer == NULL ); - if( xRequestedSizeBytes > 0 ) - { - /* Extra space is obtained so a pointer to the network buffer can - be stored at the beginning of the buffer. */ - pxReturn->pucEthernetBuffer = ( uint8_t * ) pvPortMalloc( xRequestedSizeBytes + ipBUFFER_PADDING ); - - if( pxReturn->pucEthernetBuffer == NULL ) - { - /* The attempt to allocate storage for the buffer payload failed, - so the network buffer structure cannot be used and must be - released. */ - vNetworkBufferRelease( pxReturn ); - pxReturn = NULL; - } - else - { - /* Store a pointer to the network buffer structure in the - buffer storage area, then move the buffer pointer on past the - stored pointer so the pointer value is not overwritten by the - application when the buffer is used. */ - *( ( xNetworkBufferDescriptor_t ** ) ( pxReturn->pucEthernetBuffer ) ) = pxReturn; - pxReturn->pucEthernetBuffer += ipBUFFER_PADDING; - iptraceNETWORK_BUFFER_OBTAINED( pxReturn ); - - /* Store the actual size of the allocated buffer, which may be - greater than the requested size. */ - pxReturn->xDataLength = xRequestedSizeBytes; - } - } - else - { - iptraceNETWORK_BUFFER_OBTAINED( pxReturn ); - } - } - - if( pxReturn == NULL ) - { - iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER(); - } - - return pxReturn; -} -/*-----------------------------------------------------------*/ - -void vNetworkBufferRelease( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -BaseType_t xListItemAlreadyInFreeList; - - /* Ensure the buffer is returned to the list of free buffers before the - counting semaphore is 'given' to say a buffer is available. Release the - storage allocated to the buffer payload. THIS FILE SHOULD NOT BE USED - IF THE PROJECT INCLUDES A MEMORY ALLOCATOR THAT WILL FRAGMENT THE HEAP - MEMORY. For example, heap_2 must not be used, heap_4 can be used. */ - vEthernetBufferRelease( pxNetworkBuffer->pucEthernetBuffer ); - pxNetworkBuffer->pucEthernetBuffer = NULL; - - taskENTER_CRITICAL(); - { - xListItemAlreadyInFreeList = listIS_CONTAINED_WITHIN( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); - - if( xListItemAlreadyInFreeList == pdFALSE ) - { - vListInsertEnd( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); - } - - configASSERT( xListItemAlreadyInFreeList == pdFALSE ); - } - taskEXIT_CRITICAL(); - - xSemaphoreGive( xNetworkBufferSemaphore ); - iptraceNETWORK_BUFFER_RELEASED( pxNetworkBuffer ); -} -/*-----------------------------------------------------------*/ - -#if( ipconfigINCLUDE_TEST_CODE == 1 ) - -UBaseType_t uxGetNumberOfFreeNetworkBuffers( void ) -{ - return listCURRENT_LIST_LENGTH( &xFreeBuffersList ); -} - -#endif /* ipconfigINCLUDE_TEST_CODE */ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC/pack_struct_end.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC/pack_struct_end.h deleted file mode 100644 index 73558077d..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC/pack_struct_end.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for an explanation of this file: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Compiler_Porting.shtml - * - *****************************************************************************/ -__attribute__( (packed) ); - - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC/pack_struct_start.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC/pack_struct_start.h deleted file mode 100644 index 9cc9a3556..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC/pack_struct_start.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for an explanation of this file: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Compiler_Porting.shtml - * - *****************************************************************************/ - -/* Nothing to do here. */ - - - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/MSVC/pack_struct_end.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/MSVC/pack_struct_end.h deleted file mode 100644 index 6257eb07a..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/MSVC/pack_struct_end.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for an explanation of this file: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Compiler_Porting.shtml - * - *****************************************************************************/ - -; -#pragma pack( pop ) - - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/MSVC/pack_struct_start.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/MSVC/pack_struct_start.h deleted file mode 100644 index 64ba0a629..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/MSVC/pack_struct_start.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for an explanation of this file: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Compiler_Porting.shtml - * - *****************************************************************************/ - -#pragma pack( push, 1 ) - - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/Renesas/pack_struct_end.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/Renesas/pack_struct_end.h deleted file mode 100644 index c85c8c848..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/Renesas/pack_struct_end.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for an explanation of this file: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Compiler_Porting.shtml - * - *****************************************************************************/ - - -#ifdef _SH - #ifdef __RENESAS__ - ; - #pragma unpack - #endif -#endif - - - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/Renesas/pack_struct_start.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/Renesas/pack_struct_start.h deleted file mode 100644 index 2552d528f..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/Renesas/pack_struct_start.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for an explanation of this file: - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Compiler_Porting.shtml - * - *****************************************************************************/ - - -#ifdef _SH - #ifdef __RENESAS__ - #pragma pack 1 - #endif -#endif - - - - - - - - - - - - - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC17xx/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC17xx/NetworkInterface.c deleted file mode 100644 index 57efdb542..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC17xx/NetworkInterface.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* Hardware abstraction. */ -#include "FreeRTOS_IO.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkBufferManagement.h" - -/* Driver includes. */ -#include "lpc17xx_emac.h" -#include "lpc17xx_pinsel.h" - -/* Demo includes. */ -#include "NetworkInterface.h" - -#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES != 1 - #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer -#else - #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) -#endif - -/* When a packet is ready to be sent, if it cannot be sent immediately then the -task performing the transmit will block for niTX_BUFFER_FREE_WAIT -milliseconds. It will do this a maximum of niMAX_TX_ATTEMPTS before giving -up. */ -#define niTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_RATE_MS ) -#define niMAX_TX_ATTEMPTS ( 5 ) - -/* The length of the queue used to send interrupt status words from the -interrupt handler to the deferred handler task. */ -#define niINTERRUPT_QUEUE_LENGTH ( 10 ) - -/*-----------------------------------------------------------*/ - -/* - * A deferred interrupt handler task that processes - */ -static void prvEMACHandlerTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used to communicate Ethernet events with the IP task. */ -extern xQueueHandle xNetworkEventQueue; - -/* The semaphore used to wake the deferred interrupt handler task when an Rx -interrupt is received. */ -static xSemaphoreHandle xEMACRxEventSemaphore = NULL; -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceInitialise( void ) -{ -EMAC_CFG_Type Emac_Config; -PINSEL_CFG_Type xPinConfig; -BaseType_t xStatus, xReturn; -extern uint8_t ucMACAddress[ 6 ]; - - /* Enable Ethernet Pins */ - boardCONFIGURE_ENET_PINS( xPinConfig ); - - Emac_Config.Mode = EMAC_MODE_AUTO; - Emac_Config.pbEMAC_Addr = ucMACAddress; - xStatus = EMAC_Init( &Emac_Config ); - - LPC_EMAC->IntEnable &= ~( EMAC_INT_TX_DONE ); - - if( xStatus != ERROR ) - { - vSemaphoreCreateBinary( xEMACRxEventSemaphore ); - configASSERT( xEMACRxEventSemaphore ); - - /* The handler task is created at the highest possible priority to - ensure the interrupt handler can return directly to it. */ - xTaskCreate( prvEMACHandlerTask, "EMAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); - - /* Enable the interrupt and set its priority to the minimum - interrupt priority. */ - NVIC_SetPriority( ENET_IRQn, configMAC_INTERRUPT_PRIORITY ); - NVIC_EnableIRQ( ENET_IRQn ); - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - configASSERT( xStatus != ERROR ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -BaseType_t xReturn = pdFAIL; -int32_t x; -extern void EMAC_StartTransmitNextBuffer( uint32_t ulLength ); -extern void EMAC_SetNextPacketToSend( uint8_t * pucBuffer ); - - - /* Attempt to obtain access to a Tx buffer. */ - for( x = 0; x < niMAX_TX_ATTEMPTS; x++ ) - { - if( EMAC_CheckTransmitIndex() == TRUE ) - { - /* Will the data fit in the Tx buffer? */ - if( pxNetworkBuffer->xDataLength < EMAC_ETH_MAX_FLEN ) /*_RB_ The size needs to come from FreeRTOSIPConfig.h. */ - { - /* Assign the buffer to the Tx descriptor that is now known to - be free. */ - EMAC_SetNextPacketToSend( pxNetworkBuffer->pucEthernetBuffer ); - - /* The EMAC now owns the buffer. */ - pxNetworkBuffer->pucEthernetBuffer = NULL; - - /* Initiate the Tx. */ - EMAC_StartTransmitNextBuffer( pxNetworkBuffer->xDataLength ); - iptraceNETWORK_INTERFACE_TRANSMIT(); - - /* The Tx has been initiated. */ - xReturn = pdPASS; - } - break; - } - else - { - vTaskDelay( niTX_BUFFER_FREE_WAIT ); - } - } - - /* Finished with the network buffer. */ - vNetworkBufferRelease( pxNetworkBuffer ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void ENET_IRQHandler( void ) -{ -uint32_t ulInterruptCause; - - while( ( ulInterruptCause = LPC_EMAC->IntStatus ) != 0 ) - { - /* Clear the interrupt. */ - LPC_EMAC->IntClear = ulInterruptCause; - - /* Clear fatal error conditions. NOTE: The driver does not clear all - errors, only those actually experienced. For future reference, range - errors are not actually errors so can be ignored. */ - if( ( ulInterruptCause & EMAC_INT_TX_UNDERRUN ) != 0U ) - { - LPC_EMAC->Command |= EMAC_CR_TX_RES; - } - - /* Unblock the deferred interrupt handler task if the event was an - Rx. */ - if( ( ulInterruptCause & EMAC_INT_RX_DONE ) != 0UL ) - { - xSemaphoreGiveFromISR( xEMACRxEventSemaphore, NULL ); - } - } - - /* ulInterruptCause is used for convenience here. A context switch is - wanted, but coding portEND_SWITCHING_ISR( 1 ) would likely result in a - compiler warning. */ - portEND_SWITCHING_ISR( ulInterruptCause ); -} -/*-----------------------------------------------------------*/ - -static void prvEMACHandlerTask( void *pvParameters ) -{ -size_t xDataLength; -const uint16_t usCRCLength = 4; -xNetworkBufferDescriptor_t *pxNetworkBuffer; -xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL }; - -/* This is not included in the header file for some reason. */ -extern uint8_t *EMAC_NextPacketToRead( void ); - - ( void ) pvParameters; - configASSERT( xEMACRxEventSemaphore ); - - for( ;; ) - { - /* Wait for the EMAC interrupt to indicate that another packet has been - received. The while() loop is only needed if INCLUDE_vTaskSuspend is - set to 0 in FreeRTOSConfig.h. */ - while( xSemaphoreTake( xEMACRxEventSemaphore, portMAX_DELAY ) == pdFALSE ); - - /* At least one packet has been received. */ - while( EMAC_CheckReceiveIndex() != FALSE ) - { - /* Obtain the length, minus the CRC. The CRC is four bytes - but the length is already minus 1. */ - xDataLength = ( size_t ) EMAC_GetReceiveDataSize() - ( usCRCLength - 1U ); - - if( xDataLength > 0U ) - { - /* Obtain a network buffer to pass this data into the - stack. No storage is required as the network buffer - will point directly to the buffer that already holds - the received data. */ - pxNetworkBuffer = pxNetworkBufferGet( 0, ( TickType_t ) 0 ); - - if( pxNetworkBuffer != NULL ) - { - pxNetworkBuffer->pucEthernetBuffer = EMAC_NextPacketToRead(); - pxNetworkBuffer->xDataLength = xDataLength; - xRxEvent.pvData = ( void * ) pxNetworkBuffer; - - /* Data was received and stored. Send a message to the IP - task to let it know. */ - if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( TickType_t ) 0 ) == pdFALSE ) - { - vNetworkBufferRelease( pxNetworkBuffer ); - iptraceETHERNET_RX_EVENT_LOST(); - } - } - else - { - iptraceETHERNET_RX_EVENT_LOST(); - } - - iptraceNETWORK_INTERFACE_RECEIVE(); - } - - /* Release the frame. */ - EMAC_UpdateRxConsumeIndex(); - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/NetworkInterface.c deleted file mode 100644 index 2cd7fed51..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/NetworkInterface.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 (C) 2014 Real Time Engineers ltd. - * All rights reserved - * - * This file is part of the FreeRTOS+UDP distribution. The FreeRTOS+UDP license - * terms are different to the FreeRTOS license terms. - * - * FreeRTOS+UDP uses a dual license model that allows the software to be used - * under a pure GPL open source license (as opposed to the modified GPL license - * under which FreeRTOS is distributed) or a commercial license. Details of - * both license options follow: - * - * - Open source licensing - - * FreeRTOS+UDP is a free download and may be used, modified, evaluated and - * distributed without charge provided the user adheres to version two of the - * GNU General Public License (GPL) and does not remove the copyright notice or - * this text. The GPL V2 text is available on the gnu.org web site, and on the - * following URL: http://www.FreeRTOS.org/gpl-2.0.txt. - * - * - Commercial licensing - - * Businesses and individuals that for commercial or other reasons cannot comply - * with the terms of the GPL V2 license must obtain a commercial license before - * incorporating FreeRTOS+UDP into proprietary software for distribution in any - * form. Commercial licenses can be purchased from http://shop.freertos.org/udp - * and do not require any source files to be changed. - * - * FreeRTOS+UDP is distributed in the hope that it will be useful. You cannot - * use FreeRTOS+UDP unless you agree that you use the software 'as is'. - * FreeRTOS+UDP is provided WITHOUT ANY WARRANTY; without even the implied - * warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A PARTICULAR - * PURPOSE. Real Time Engineers Ltd. disclaims all conditions and terms, be they - * implied, expressed, or statutory. - * - * 1 tab == 4 spaces! - * - * http://www.FreeRTOS.org - * http://www.FreeRTOS.org/udp - * - */ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkBufferManagement.h" - -/* Driver includes. */ -#include "lpc18xx_emac.h" - -/* Demo includes. */ -#include "NetworkInterface.h" - -#ifndef configNUM_RX_ETHERNET_DMA_DESCRIPTORS - #error configNUM_RX_ETHERNET_DMA_DESCRIPTORS must be defined in FreeRTOSConfig.h to set the number of RX DMA descriptors -#endif - -#ifndef configNUM_TX_ETHERNET_DMA_DESCRIPTORS - #error configNUM_TX_ETHERNET_DMA_DESCRIPTORS must be defined in FreeRTOSConfig.h to set the number of TX DMA descriptors -#endif - -/* If a packet cannot be sent immediately then the task performing the send -operation will be held in the Blocked state (so other tasks can execute) for -niTX_BUFFER_FREE_WAIT ticks. It will do this a maximum of niMAX_TX_ATTEMPTS -before giving up. */ -#define niTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_RATE_MS ) -#define niMAX_TX_ATTEMPTS ( 5 ) - -/*-----------------------------------------------------------*/ - -/* - * A deferred interrupt handler task that processes received frames. - */ -static void prvEMACDeferredInterruptHandlerTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used to communicate Ethernet events to the IP task. */ -extern xQueueHandle xNetworkEventQueue; - -/* The semaphore used to wake the deferred interrupt handler task when an Rx -interrupt is received. */ -static xSemaphoreHandle xEMACRxEventSemaphore = NULL; - -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceInitialise( void ) -{ -EMAC_CFG_Type Emac_Config; -BaseType_t xReturn; -extern uint8_t ucMACAddress[ 6 ]; - - Emac_Config.pbEMAC_Addr = ucMACAddress; - xReturn = EMAC_Init( &Emac_Config ); - - if( xReturn == pdPASS ) - { - LPC_ETHERNET->DMA_INT_EN = DMA_INT_NOR_SUM | DMA_INT_RECEIVE; - - /* Create the event semaphore if it has not already been created. */ - if( xEMACRxEventSemaphore == NULL ) - { - vSemaphoreCreateBinary( xEMACRxEventSemaphore ); - #if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 - { - /* If the trace recorder code is included name the semaphore for - viewing in FreeRTOS+Trace. */ - vTraceSetQueueName( xEMACRxEventSemaphore, "MAC_RX" ); - } - #endif /* ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 */ - } - - configASSERT( xEMACRxEventSemaphore ); - - /* The Rx deferred interrupt handler task is created at the highest - possible priority to ensure the interrupt handler can return directly to - it no matter which task was running when the interrupt occurred. */ - xTaskCreate( prvEMACDeferredInterruptHandlerTask, /* The function that implements the task. */ - "MACTsk", - configMINIMAL_STACK_SIZE, /* Stack allocated to the task (defined in words, not bytes). */ - NULL, /* The task parameter is not used. */ - configMAX_PRIORITIES - 1, /* The priority assigned to the task. */ - NULL ); /* The handle is not required, so NULL is passed. */ - - /* Enable the interrupt and set its priority as configured. THIS - DRIVER REQUIRES configMAC_INTERRUPT_PRIORITY TO BE DEFINED, PREFERABLY - IN FreeRTOSConfig.h. */ - NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY ); - NVIC_EnableIRQ( ETHERNET_IRQn ); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -BaseType_t xReturn = pdFAIL; -int32_t x; - - /* Attempt to obtain access to a Tx descriptor. */ - for( x = 0; x < niMAX_TX_ATTEMPTS; x++ ) - { - if( EMAC_CheckTransmitIndex() == TRUE ) - { - /* Assign the buffer being transmitted to the Tx descriptor. */ - EMAC_SetNextPacketToSend( pxNetworkBuffer->pucEthernetBuffer ); - - /* The EMAC now owns the buffer and will free it when it has been - transmitted. Set pucBuffer to NULL to ensure the buffer is not - freed when the network buffer structure is returned to the pool - of network buffers. */ - pxNetworkBuffer->pucEthernetBuffer = NULL; - - /* Initiate the Tx. */ - EMAC_StartTransmitNextBuffer( pxNetworkBuffer->xDataLength ); - iptraceNETWORK_INTERFACE_TRANSMIT(); - - /* The Tx has been initiated. */ - xReturn = pdPASS; - - break; - } - else - { - iptraceWAITING_FOR_TX_DMA_DESCRIPTOR(); - vTaskDelay( niTX_BUFFER_FREE_WAIT ); - } - } - - /* Finished with the network buffer. */ - vNetworkBufferRelease( pxNetworkBuffer ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void ETH_IRQHandler( void ) -{ -uint32_t ulInterruptCause; - - ulInterruptCause = LPC_ETHERNET->DMA_STAT ; - - /* Clear the interrupt. */ - LPC_ETHERNET->DMA_STAT |= ( DMA_INT_NOR_SUM | DMA_INT_RECEIVE ); - - /* Clear fatal error conditions. NOTE: The driver does not clear all - errors, only those actually experienced. For future reference, range - errors are not actually errors so can be ignored. */ - if( ( ulInterruptCause & ( 1 << 13 ) ) != 0U ) - { - LPC_ETHERNET->DMA_STAT |= ( 1 << 13 ); - } - - /* Unblock the deferred interrupt handler task if the event was an Rx. */ - if( ( ulInterruptCause & DMA_INT_RECEIVE ) != 0UL ) - { - xSemaphoreGiveFromISR( xEMACRxEventSemaphore, NULL ); - } - - /* ulInterruptCause is used for convenience here. A context switch is - wanted, but coding portEND_SWITCHING_ISR( 1 ) would likely result in a - compiler warning. */ - portEND_SWITCHING_ISR( ulInterruptCause ); -} -/*-----------------------------------------------------------*/ - -static void prvEMACDeferredInterruptHandlerTask( void *pvParameters ) -{ -xNetworkBufferDescriptor_t *pxNetworkBuffer; -xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL }; - - ( void ) pvParameters; - configASSERT( xEMACRxEventSemaphore ); - - for( ;; ) - { - /* Wait for the EMAC interrupt to indicate that another packet has been - received. The while() loop is only needed if INCLUDE_vTaskSuspend is - set to 0 in FreeRTOSConfig.h. If INCLUDE_vTaskSuspend is set to 1 - then portMAX_DELAY would be an indefinite block time and - xSemaphoreTake() would only return when the semaphore was actually - obtained. */ - while( xSemaphoreTake( xEMACRxEventSemaphore, portMAX_DELAY ) == pdFALSE ); - - /* At least one packet has been received. */ - while( EMAC_CheckReceiveIndex() != FALSE ) - { - /* The buffer filled by the DMA is going to be passed into the IP - stack. Allocate another buffer for the DMA descriptor. */ - pxNetworkBuffer = pxNetworkBufferGet( ipTOTAL_ETHERNET_FRAME_SIZE, ( TickType_t ) 0 ); - - if( pxNetworkBuffer != NULL ) - { - /* Swap the buffer just allocated and referenced from the - pxNetworkBuffer with the buffer that has already been filled by - the DMA. pxNetworkBuffer will then hold a reference to the - buffer that already contains the data without any data having - been copied between buffers. */ - EMAC_NextPacketToRead( pxNetworkBuffer ); - - #if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 1 - { - if( pxNetworkBuffer->xDataLength > 0 ) - { - /* If the frame would not be processed by the IP stack then - don't even bother sending it to the IP stack. */ - if( eConsiderFrameForProcessing( pxNetworkBuffer->pucEthernetBuffer ) != eProcessBuffer ) - { - pxNetworkBuffer->xDataLength = 0; - } - } - } - #endif - - if( pxNetworkBuffer->xDataLength > 0 ) - { - /* Store a pointer to the network buffer structure in the - padding space that was left in front of the Ethernet frame. - The pointer is needed to ensure the network buffer structure - can be located when it is time for it to be freed if the - Ethernet frame gets used as a zero copy buffer. */ - *( ( xNetworkBufferDescriptor_t ** ) ( ( pxNetworkBuffer->pucEthernetBuffer - ipBUFFER_PADDING ) ) ) = pxNetworkBuffer; - - /* Data was received and stored. Send it to the IP task - for processing. */ - xRxEvent.pvData = ( void * ) pxNetworkBuffer; - if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( TickType_t ) 0 ) == pdFALSE ) - { - /* The buffer could not be sent to the IP task so the - buffer must be released. */ - vNetworkBufferRelease( pxNetworkBuffer ); - iptraceETHERNET_RX_EVENT_LOST(); - } - else - { - iptraceNETWORK_INTERFACE_RECEIVE(); - } - } - else - { - /* The buffer does not contain any data so there is no - point sending it to the IP task. Just release it. */ - vNetworkBufferRelease( pxNetworkBuffer ); - iptraceETHERNET_RX_EVENT_LOST(); - } - } - else - { - iptraceETHERNET_RX_EVENT_LOST(); - } - - /* Release the descriptor. */ - EMAC_UpdateRxConsumeIndex(); - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/lpc18xx_emac.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/lpc18xx_emac.c deleted file mode 100644 index 98730ada5..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/lpc18xx_emac.c +++ /dev/null @@ -1,610 +0,0 @@ -/********************************************************************** -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* Heavily modified by Real Time Engineers ltd. -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -**********************************************************************/ - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "NetworkBufferManagement.h" - -/* Library includes. */ -#include "lpc18xx_emac.h" -#include "lpc18xx_rgu.h" -#include "lpc18xx_scu.h" -#include "lpc18xx_gpio.h" - - -#define emacTIMEOUT_DELAY ( 2 ) -#define emacNEGOTIATE_DELAY ( 10 / portTICK_RATE_MS ) - -#define emacEXPECTED_RX_STATUS_MASK ( RX_FIRST_SEGM | RX_LAST_SEGM ) - -/* Rx descriptors and data array. */ -static volatile RX_Desc Rx_Desc[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ]; -static unsigned int RxDescIndex = 0; - -/** Rx Status data array - Must be 8-Byte aligned */ -#if defined ( __CC_ARM ) - static __align(8) RX_Stat Rx_Stat[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ]; -#elif defined ( __ICCARM__ ) - #pragma data_alignment=8 - static RX_Stat Rx_Stat[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ]; -#elif defined ( __GNUC__ ) - static volatile __attribute__ ((aligned (8))) RX_Stat Rx_Stat[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ]; -#endif - -/* Tx descriptors and status array. */ -static volatile TX_Desc Tx_Desc[ configNUM_TX_ETHERNET_DMA_DESCRIPTORS ]; -static volatile TX_Stat Tx_Stat[ configNUM_TX_ETHERNET_DMA_DESCRIPTORS ]; -static unsigned int TxDescIndex = 0; - -/* Private Functions ---------------------------------------------------------- */ -static void rx_descr_init( void ); -static void tx_descr_init( void ); -static int32_t write_PHY( uint32_t PhyReg, uint16_t Value ); -static int32_t read_PHY( uint32_t PhyReg ); -static void setEmacAddr( uint8_t abStationAddr[] ); - -/*********************************************************************//** - * @brief Initializes the EMAC peripheral according to the specified - * parameters in the EMAC_ConfigStruct. - * @param[in] EMAC_ConfigStruct Pointer to a EMAC_CFG_Type structure - * that contains the configuration information for the - * specified EMAC peripheral. - * @return None - * - * Note: This function will initialize EMAC module according to procedure below: - * - Remove the soft reset condition from the MAC - * - Configure the PHY via the MIIM interface of the MAC - * - Select RMII mode - * - Configure the transmit and receive DMA engines, including the descriptor arrays - * - Configure the host registers (MAC1,MAC2 etc.) in the MAC - * - Enable the receive and transmit data paths - * In default state after initializing, only Rx Done and Tx Done interrupt are enabled, - * all remain interrupts are disabled - * (Ref. from LPC17xx UM) - **********************************************************************/ -BaseType_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct) -{ -int32_t id1, id2, regv, phy = 0; -int32_t phy_linkstatus_reg, phy_linkstatus_mask; -uint32_t x; -const uint32_t ulMaxAttempts = 250UL; -BaseType_t xReturn = pdPASS; - - /* Enable Ethernet Pins (NGX LPC1830 Xplorer. */ - scu_pinmux(0x2 ,0 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7); - scu_pinmux(0x1 ,17 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); - scu_pinmux(0x1 ,18 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); - scu_pinmux(0x1 ,20 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); - scu_pinmux(0x1 ,19 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0); - scu_pinmux(0x0 ,1 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC6); - scu_pinmux(0x1 ,15 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); - scu_pinmux(0x0 ,0 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2); - scu_pinmux(0x1 ,16 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); - scu_pinmux(0xC ,9 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); - scu_pinmux(0x1 ,16 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7); - - /* Ethernet RESET Pins */ - scu_pinmux(0x1 ,0 , MD_PUP, FUNC0); - GPIO_SetDir(0,(1<<4), 1); - GPIO_SetValue(0,(1<<4)); - - - #if MII /* Select MII interface */ // check MUXING for new Eagle... - scu_pinmux(0xC ,6 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD2: PC_6 -> FUNC3 - scu_pinmux(0xC ,7 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD3: PC_7 -> FUNC3 - scu_pinmux(0xC ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXLK: PC_0 -> FUNC3 - scu_pinmux(0xC ,2 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD2: PC_2 -> FUNC3 - scu_pinmux(0xC ,3 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD3: PC_3 -> FUNC3 - scu_pinmux(0xC ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_ER: PC_5 -> FUNC3 - scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_COL: P0_1 -> FUNC2 - #else /* Select RMII interface */ - LPC_CREG->CREG6 |= RMII_SELECT; - #endif - - - RGU_SoftReset( RGU_SIG_ETHERNET ); - - /* Wait for reset. */ - while( !( LPC_RGU->RESET_ACTIVE_STATUS0 & ( 1 << ETHERNET_RST ) ) ) - { - vTaskDelay( emacTIMEOUT_DELAY ); - } - - /* Reset all GMAC Subsystem internal registers and logic. */ - LPC_ETHERNET->DMA_BUS_MODE |= DMA_SOFT_RESET; - - /* Wait for software reset completion. */ - while( LPC_ETHERNET->DMA_BUS_MODE & DMA_SOFT_RESET ) - { - vTaskDelay( emacTIMEOUT_DELAY ); - } - - /* Put the PHY in reset mode */ - write_PHY( PHY_REG_BMCR, PHY_BMCR_RESET ); - - /* Wait for hardware reset to end. */ - for( x = 0; x < ulMaxAttempts; x++ ) - { - regv = read_PHY (PHY_REG_BMCR); - if( !( regv & PHY_BMCR_RESET ) ) - { - /* Reset complete */ - break; - } - else - { - vTaskDelay( emacTIMEOUT_DELAY ); - } - } - - if( x == ulMaxAttempts ) - { - xReturn = pdFAIL; - } - - /* Check if this is a DP83848C PHY. */ - id1 = read_PHY( PHY_REG_IDR1 ); - id2 = read_PHY( PHY_REG_IDR2 ); - if( ( ( id1 << 16 ) | ( id2 & 0xFFF0 ) ) == DP83848C_ID ) - { - phy = DP83848C_ID; - } - else if( ( ( id1 << 16 ) | id2 ) == LAN8720_ID ) - { - phy = LAN8720_ID; - } - - if( phy != 0 ) - { - /* Use autonegotiation about the link speed. */ - write_PHY( PHY_REG_BMCR, PHY_AUTO_NEG ); - - /* Wait to complete Auto_Negotiation. */ - for( x = 0; x < ulMaxAttempts; x++ ) - { - regv = read_PHY( PHY_REG_BMSR ); - - if( ( regv & PHY_AUTO_NEG_DONE ) != 0 ) - { - /* Auto negotiation Complete. */ - break; - } - else - { - vTaskDelay( emacNEGOTIATE_DELAY ); - } - } - - if( x == ulMaxAttempts ) - { - xReturn = pdFAIL; - } - } - else - { - xReturn = pdFAIL; - } - - - if( xReturn == pdPASS ) - { - /* Default to DP83848C. */ - phy_linkstatus_reg = PHY_REG_STS; - phy_linkstatus_mask = 0x0001; - - if( phy == LAN8720_ID ) - { - phy_linkstatus_reg = PHY_REG_BMSR; - phy_linkstatus_mask = 0x0004; - } - - /* Check the link status. */ - for( x = 0; x < ulMaxAttempts; x++ ) - { - regv = read_PHY( phy_linkstatus_reg ); - - if( ( regv & phy_linkstatus_mask ) != 0 ) - { - /* Link is on. */ - break; - } - else - { - vTaskDelay( emacNEGOTIATE_DELAY ); - } - } - - if( x == ulMaxAttempts ) - { - xReturn = pdFAIL; - } - - regv = read_PHY( PHY_REG_SPCON ); - regv &= PHY_REG_HCDSPEED_MASK; - - /* Configure 100MBit/10MBit mode and Full/Half Duplex mode. */ - switch( regv ) - { - case PHY_REG_HCDSPEED_10MB_FULLD: - LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE; - break; - - case PHY_REG_HCDSPEED_100MB_HALFD: - LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS; - break; - - case PHY_REG_HCDSPEED_100MB_FULLD: - LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE; - LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS; - break; - - default: - break; - } - - /* Set the Ethernet MAC Address registers */ - setEmacAddr( EMAC_ConfigStruct->pbEMAC_Addr ); - - /* Initialize Descriptor Lists */ - rx_descr_init(); - tx_descr_init(); - - /* Configure Filter - LPC_ETHERNET->MAC_FRAME_FILTER is left at its default value. - MAC_PROMISCUOUS and MAC_RECEIVEALL can be set if required. */ - - /* Enable Receiver and Transmitter */ - LPC_ETHERNET->MAC_CONFIG |= (MAC_TX_ENABLE | MAC_RX_ENABLE); - - /* Enable interrupts */ - LPC_ETHERNET->DMA_INT_EN = DMA_INT_NOR_SUM | DMA_INT_RECEIVE ; - - /* Start Transmission & Receive processes */ - LPC_ETHERNET->DMA_OP_MODE |= (DMA_SS_TRANSMIT | DMA_SS_RECEIVE ); - } - - return xReturn; -} - -/*********************************************************************//** - **********************************************************************/ -BaseType_t EMAC_CheckTransmitIndex( void ) -{ -BaseType_t xReturn; - - if( ( Tx_Desc[ TxDescIndex ].Status & OWN_BIT ) == 0 ) - { - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} - -/*********************************************************************//** - * @brief EMAC_SetNextPacketToSend - * @param[in] pucBuffer - * @return None - ***********************************************************************/ -void EMAC_SetNextPacketToSend( uint8_t * pucBuffer ) -{ - /* The old packet is now finished with and can be freed. */ - vEthernetBufferRelease( ( void * ) Tx_Desc[ TxDescIndex ].Packet ); - - /* Assign the new packet to the descriptor. */ - Tx_Desc[ TxDescIndex ].Packet = ( uint32_t ) pucBuffer; -} - -void EMAC_StartTransmitNextBuffer( uint32_t ulLength ) -{ - Tx_Desc[ TxDescIndex ].Ctrl = ulLength; - Tx_Desc[ TxDescIndex ].Status |= OWN_BIT; - - /* Wake Up the DMA if it's in Suspended Mode. */ - LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; - TxDescIndex++; - - if( TxDescIndex == configNUM_TX_ETHERNET_DMA_DESCRIPTORS ) - { - TxDescIndex = 0; - } -} - -/*********************************************************************//** - * @brief Get size of current Received data in received buffer (due to - * RxConsumeIndex) - * @param[in] None - * @return Size of received data - **********************************************************************/ -uint32_t EMAC_GetReceiveDataSize(void) -{ -unsigned short RxLen = 0; - - RxLen = ( Rx_Desc[ RxDescIndex ].Status >> 16 ) & 0x03FFF; - return RxLen; -} - -/*********************************************************************//** - * @brief Increase the RxConsumeIndex (after reading the Receive buffer - * to release the Receive buffer) and wrap-around the index if - * it reaches the maximum Receive Number - * @param[in] None - * @return None - **********************************************************************/ -void EMAC_UpdateRxConsumeIndex( void ) -{ - Rx_Desc[ RxDescIndex ].Status = OWN_BIT; - RxDescIndex++; - - if( RxDescIndex == configNUM_RX_ETHERNET_DMA_DESCRIPTORS ) - { - RxDescIndex = 0; - } -} - -/*********************************************************************//** - * @brief Check whether if the current RxConsumeIndex is not equal to the - * current RxProduceIndex. - * @param[in] None - * @return TRUE if they're not equal, otherwise return FALSE - * - * Note: In case the RxConsumeIndex is not equal to the RxProduceIndex, - * it means there're available data has been received. They should be read - * out and released the Receive Data Buffer by updating the RxConsumeIndex value. - **********************************************************************/ -BaseType_t EMAC_CheckReceiveIndex(void) -{ -BaseType_t xReturn; - - if( ( Rx_Desc[ RxDescIndex ].Status & OWN_BIT ) == 0 ) - { - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} - -void EMAC_NextPacketToRead( xNetworkBufferDescriptor_t *pxNetworkBuffer ) -{ -uint8_t *pucTemp; - - /* Swap the buffer in the network buffer with the buffer used by the DMA. - This allows the data to be passed out without having to perform any copies. */ - pucTemp = ( uint8_t * ) Rx_Desc[ RxDescIndex ].Packet; - Rx_Desc[ RxDescIndex ].Packet = ( uint32_t ) pxNetworkBuffer->pucEthernetBuffer; - pxNetworkBuffer->pucEthernetBuffer = pucTemp; - - /* Only supports frames coming in single buffers. If this frame is split - across multiple buffers then reject it (and if the frame is needed increase - the ipconfigNETWORK_MTU setting). */ - if( ( Rx_Desc[ RxDescIndex ].Status & emacEXPECTED_RX_STATUS_MASK ) != emacEXPECTED_RX_STATUS_MASK ) - { - pxNetworkBuffer->xDataLength = 0; - } - else - { - pxNetworkBuffer->xDataLength = ( size_t ) EMAC_GetReceiveDataSize() - ( ipETHERNET_CRC_BYTES - 1U );; - } -} - -/*********************************************************************//** - * @brief Initializes RX Descriptor - * @param[in] None - * @return None - ***********************************************************************/ -static void rx_descr_init( void ) -{ -uint32_t x; -size_t xBufferSize = ipTOTAL_ETHERNET_FRAME_SIZE; - - for( x = 0; x < configNUM_RX_ETHERNET_DMA_DESCRIPTORS; x++ ) - { - /* Obtain the buffer first, as the size of the buffer might be changed - within the pucEthernetBufferGet() call. */ - Rx_Desc[ x ].Packet = ( uint32_t ) pucEthernetBufferGet( &xBufferSize ); - Rx_Desc[ x ].Status = OWN_BIT; - Rx_Desc[ x ].Ctrl = xBufferSize; - Rx_Desc[ x ].NextDescripter = ( uint32_t ) &Rx_Desc[ x + 1 ]; - - configASSERT( ( ( ( uint32_t ) Rx_Desc[x].Packet ) & 0x07 ) == 0 ); - } - - /* Last Descriptor */ - Rx_Desc[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS - 1 ].Ctrl |= RX_END_RING; - - RxDescIndex = 0; - - /* Set Starting address of RX Descriptor list */ - LPC_ETHERNET->DMA_REC_DES_ADDR = ( uint32_t ) Rx_Desc; -} - -/*********************************************************************//** - * @brief Initializes TX Descriptor - * @param[in] None - * @return None - ***********************************************************************/ -static void tx_descr_init( void ) -{ -/* Initialize Transmit Descriptor and Status array. */ -uint32_t x; - - for( x = 0; x < configNUM_TX_ETHERNET_DMA_DESCRIPTORS; x++ ) - { - Tx_Desc[ x ].Status = TX_LAST_SEGM | TX_FIRST_SEGM; - Tx_Desc[ x ].Ctrl = 0; - Tx_Desc[ x ].NextDescripter = ( uint32_t ) &Tx_Desc[ x + 1 ]; - - /* Packet is assigned when a Tx is initiated. */ - Tx_Desc[ x ].Packet = ( uint32_t )NULL; - } - - /* Last Descriptor? */ - Tx_Desc[ configNUM_TX_ETHERNET_DMA_DESCRIPTORS-1 ].Status |= TX_END_RING; - - /* Set Starting address of TX Descriptor list */ - LPC_ETHERNET->DMA_TRANS_DES_ADDR = ( uint32_t ) Tx_Desc; -} - - -/*********************************************************************//** - * @brief Write value to PHY device - * @param[in] PhyReg: PHY Register address - * @param[in] Value: Value to write - * @return 0 - if success - * 1 - if fail - ***********************************************************************/ -static int32_t write_PHY (uint32_t PhyReg, uint16_t Value) -{ -uint32_t x; -const uint32_t ulMaxAttempts = 250UL; -int32_t lReturn = pdPASS; - - /* Write a data 'Value' to PHY register 'PhyReg'. */ - x = 0; - while( LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY ) - { - x++; - - if( x >= ulMaxAttempts ) - { - /* Time out. */ - lReturn = pdFAIL; - break; - } - else - { - /* GMII is busy. */ - vTaskDelay( emacTIMEOUT_DELAY ); - } - } - - if( lReturn == pdPASS ) - { - LPC_ETHERNET->MAC_MII_ADDR = ( DP83848C_DEF_ADR << 11 ) | ( PhyReg << 6 ) | GMII_WRITE; - LPC_ETHERNET->MAC_MII_DATA = Value; - - /* Start PHY Write Cycle. */ - LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY; - - /* Wait untl operation completed. */ - for( x = 0; x < ulMaxAttempts; x++ ) - { - if( ( LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY ) == 0 ) - { - break; - } - else - { - vTaskDelay( emacTIMEOUT_DELAY ); - } - } - - if( x == ulMaxAttempts ) - { - /* Timeout. */ - lReturn = pdFAIL; - } - } - - return lReturn; -} - -/*********************************************************************//** - * @brief Read value from PHY device - * @param[in] PhyReg: PHY Register address - * @return 0 - if success - * 1 - if fail - ***********************************************************************/ -static int32_t read_PHY( uint32_t PhyReg ) -{ -int32_t lValue = 0; -uint32_t x; -const uint32_t ulMaxAttempts = 250UL; - - /* Write a data 'Value' to PHY register 'PhyReg'. */ - x = 0; - while( LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY ) - { - x++; - - if( x >= ulMaxAttempts ) - { - /* Time out. */ - break; - } - else - { - /* GMII is busy. */ - vTaskDelay( emacTIMEOUT_DELAY ); - } - } - - if( x < ulMaxAttempts ) - { - /* Read a PHY register 'PhyReg'. */ - LPC_ETHERNET->MAC_MII_ADDR = ( DP83848C_DEF_ADR << 11 ) | ( PhyReg << 6 ) | GMII_READ; - - /* Start PHY Read Cycle. */ - LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY; - - /* Wait until operation completed */ - for( x = 0; x < ulMaxAttempts; x++ ) - { - if( ( LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY ) == 0 ) - { - break; - } - else - { - vTaskDelay( emacTIMEOUT_DELAY ); - } - } - - configASSERT( x != ulMaxAttempts ); - lValue = LPC_ETHERNET->MAC_MII_DATA; - } - - return lValue; -} - -/*********************************************************************//** - * @brief Set Station MAC address for EMAC module - * @param[in] abStationAddr Pointer to Station address that contains 6-bytes - * of MAC address (should be in order from MAC Address 1 to MAC Address 6) - * @return None - **********************************************************************/ -static void setEmacAddr( uint8_t abStationAddr[] ) -{ - /* Set the Ethernet MAC Address registers */ - LPC_ETHERNET->MAC_ADDR0_HIGH = (( uint32_t ) abStationAddr[ 5 ] << 8 ) | ( uint32_t )abStationAddr[ 4 ]; - LPC_ETHERNET->MAC_ADDR0_LOW = (( uint32_t )abStationAddr[ 3 ] << 24) | (( uint32_t )abStationAddr[ 2 ] << 16) | (( uint32_t )abStationAddr[ 1 ] << 8 ) | ( uint32_t )abStationAddr[ 0 ]; -} - - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/lpc18xx_emac.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/lpc18xx_emac.h deleted file mode 100644 index 1c318fcc8..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_CMSISv2p10_LPC18xx_DriverLib/lpc18xx_emac.h +++ /dev/null @@ -1,238 +0,0 @@ -/***********************************************************************//** - * @file lpc17xx_emac.h - * @brief Contains all macro definitions and function prototypes - * support for Ethernet MAC firmware library on LPC17xx - * @version 2.0 - * @date 21. May. 2010 - * @author NXP MCU SW Application Team - ************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - **************************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup EMAC EMAC - * @ingroup LPC1700CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC18XX_EMAC_H_ -#define LPC18XX_EMAC_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC18xx.h" - - - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "lpc_types.h" - -/* Configuration */ - -/* Interface Selection */ -#define MII 0 // =0 RMII - =1 MII - -/* End of Configuration */ - -/* Descriptors Fields bits */ -#define OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */ -#define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */ -#define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */ -#define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */ -#define RX_LAST_SEGM (1<<9) -#define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */ -#define RX_FIRST_SEGM (1<<8) /* First Segment bit in TDES0 */ -#define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */ -#define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */ - -/* EMAC Memory Buffer configuration for 16K Ethernet RAM */ -#define EMAC_ETH_MAX_FLEN ipETHERNET_FRAME_SIZE_TO_USE - -/* NOTE: EMAC_NUM_RX_FRAG is not used by the example FreeRTOS drivers - use -configNUM_RX_ETHERNET_DMA_DESCRIPTORS. */ -#define EMAC_NUM_RX_FRAG 6 /**< Num.of RX Fragments */ - -/* NOTE: EMAC_NUM_TX_FRAG is not used by the example FreeRTOS drivers - use -configNUM_TX_ETHERNET_DMA_DESCRIPTORS. */ -#define EMAC_NUM_TX_FRAG 2 /**< Num.of TX Fragments */ - -/* EMAC Control and Status bits */ -#define MAC_RX_ENABLE (1<<2) /* Receiver Enable in MAC_CONFIG reg */ -#define MAC_TX_ENABLE (1<<3) /* Transmitter Enable in MAC_CONFIG reg */ -#define MAC_PADCRC_STRIP (1<<7) /* Automatic Pad-CRC Stripping in MAC_CONFIG reg */ -#define MAC_DUPMODE (1<<11) /* Duplex Mode in MAC_CONFIG reg */ -#define MAC_100MPS (1<<14) /* Speed is 100Mbps in MAC_CONFIG reg */ -#define MAC_PROMISCUOUS (1U<<0) /* Promiscuous Mode bit in MAC_FRAME_FILTER reg */ -#define MAC_DIS_BROAD (1U<<5) /* Disable Broadcast Frames bit in MAC_FRAME_FILTER reg */ -#define MAC_RECEIVEALL (1U<<31) /* Receive All bit in MAC_FRAME_FILTER reg */ -#define DMA_SOFT_RESET 0x01 /* Software Reset bit in DMA_BUS_MODE reg */ -#define DMA_SS_RECEIVE (1<<1) /* Start/Stop Receive bit in DMA_OP_MODE reg */ -#define DMA_SS_TRANSMIT (1<<13) /* Start/Stop Transmission bit in DMA_OP_MODE reg */ -#define DMA_INT_TRANSMIT (1<<0) /* Transmit Interrupt Enable bit in DMA_INT_EN reg */ -#define DMA_INT_OVERFLOW (1<<4) /* Overflow Interrupt Enable bit in DMA_INT_EN reg */ -#define DMA_INT_UNDERFLW (1<<5) /* Underflow Interrupt Enable bit in DMA_INT_EN reg */ -#define DMA_INT_RECEIVE (1<<6) /* Receive Interrupt Enable bit in DMA_INT_EN reg */ -#define DMA_INT_ABN_SUM (1<<15) /* Abnormal Interrupt Summary Enable bit in DMA_INT_EN reg */ -#define DMA_INT_NOR_SUM (1<<16) /* Normal Interrupt Summary Enable bit in DMA_INT_EN reg */ - -/* MII Management Command Register */ -#define GMII_READ (0<<1) /* GMII Read PHY */ -#define GMII_WRITE (1<<1) /* GMII Write PHY */ -#define GMII_BUSY 0x00000001 /* GMII is Busy / Start Read/Write */ -#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ -#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ - -/* MII Management Address Register */ -#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ - -/* LAN8720 PHY Registers */ -#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ -#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ -#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ -#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ -#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ -#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ -#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ - -/* LAN8720 PHY Speed identify */ -#define PHY_REG_SPCON 0x1f /* Speed indication Register */ -#define PHY_REG_HCDSPEED_MASK 0x1c /* Speed indication Register mask*/ -#define PHY_REG_HCDSPEED_10MB_HALFD 0x04 /* Speed is 10Mbps HALF-duplex */ -#define PHY_REG_HCDSPEED_10MB_FULLD 0x14 /* Speed is 10Mbps FULL-duplex */ -#define PHY_REG_HCDSPEED_100MB_HALFD 0x08 /* Speed is 100Mbps HALF-duplex */ -#define PHY_REG_HCDSPEED_100MB_FULLD 0x18 /* Speed is 100Mbps FULL-duplex */ - - -/* PHY Extended Registers */ -#define PHY_REG_STS 0x10 /* Status Register */ -#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ -#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ -#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ -#define PHY_REG_RECR 0x15 /* Receive Error Counter */ -#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ -#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ -#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ -#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ -#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ -#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ -#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ - -/* PHY Control and Status bits */ -#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ -#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ -#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ -#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ -#define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */ -#define PHY_AUTO_NEG_DONE 0x0020 /* AutoNegotiation Complete in BMSR PHY reg */ -#define PHY_BMCR_RESET 0x8000 /* Reset bit at BMCR PHY reg */ -#define LINK_VALID_STS 0x0001 /* Link Valid Status at REG_STS PHY reg */ -#define FULL_DUP_STS 0x0004 /* Full Duplex Status at REG_STS PHY reg */ -#define SPEED_10M_STS 0x0002 /* 10Mbps Status at REG_STS PHY reg */ - -#define DP83848C_DEF_ADR 0x01 /* Default PHY device address */ -#define DP83848C_ID 0x20005C90 /* PHY Identifier (without Rev. info */ -#define LAN8720_ID 0x0007C0F1 /* PHY Identifier for SMSC PHY */ - -/* Misc */ -#define ETHERNET_RST 22 /* Reset Output for EMAC at RGU */ -#define RMII_SELECT 0x04 /* Select RMII in EMACCFG */ - - -/** - * @brief EMAC configuration structure definition - */ -typedef struct { - uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following: - - EMAC_MODE_AUTO - - EMAC_MODE_10M_FULL - - EMAC_MODE_10M_HALF - - EMAC_MODE_100M_FULL - - EMAC_MODE_100M_HALF - */ - uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes - of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5]) - */ -} EMAC_CFG_Type; - -/* Descriptor and status formats ---------------------------------------------- */ -/** - * @brief RX Descriptor structure type definition - */ -typedef struct { - uint32_t Status; /**< Receive Status Descriptor */ - uint32_t Ctrl; /**< Receive Control Descriptor */ - uint32_t Packet; /**< Receive Packet Descriptor */ - uint32_t NextDescripter;/**< Receive Next Descriptor Address */ -} RX_Desc; - -/** - * @brief RX Status structure type definition - */ -typedef struct { - uint32_t Info; /**< Receive Information Status */ - uint32_t HashCRC; /**< Receive Hash CRC Status */ -} RX_Stat; - -/** - * @brief TX Descriptor structure type definition - */ -typedef struct { - uint32_t Status; /**< Transmit Status Descriptor */ - uint32_t Ctrl; /**< Transmit Control Descriptor */ - uint32_t Packet; /**< Transmit Packet Descriptor */ - uint32_t NextDescripter; /**< Transmit Next Descriptor Address */ -} TX_Desc; - -/** - * @brief TX Status structure type definition - */ -typedef struct { - uint32_t Info; /**< Transmit Information Status */ -} TX_Stat; - - -/** - * @brief TX Data Buffer structure definition - */ -typedef struct { - uint32_t ulDataLen; /**< Data length */ - uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */ -} EMAC_PACKETBUF_Type; - - - -/* Prototypes */ -BaseType_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct); -int32_t EMAC_UpdatePHYStatus(void); -uint32_t EMAC_GetReceiveDataSize(void); -void EMAC_StartTransmitNextBuffer( uint32_t ulLength ); -void EMAC_SetNextPacketToSend( uint8_t * pucBuffer ); -void EMAC_NextPacketToRead( xNetworkBufferDescriptor_t *pxNetworkBuffer ); -void EMAC_UpdateRxConsumeIndex(void); -BaseType_t EMAC_CheckReceiveIndex(void); -BaseType_t EMAC_CheckTransmitIndex(void); - -#ifdef __cplusplus -} -#endif - -#endif /* LPC18XX_EMAC_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/NetworkInterface.c deleted file mode 100644 index 670e2d541..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/NetworkInterface.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkBufferManagement.h" -#include "lpc18xx_43xx_EMAC_LPCOpen.h" - -/* Demo includes. */ -#include "NetworkInterface.h" - -/* Library includes. */ -#include "board.h" - -#if configMAC_INTERRUPT_PRIORITY > configMAC_INTERRUPT_PRIORITY - #error configMAC_INTERRUPT_PRIORITY must be greater than or equal to configMAC_INTERRUPT_PRIORITY (higher numbers mean lower logical priority) -#endif - -#ifndef configNUM_RX_ETHERNET_DMA_DESCRIPTORS - #error configNUM_RX_ETHERNET_DMA_DESCRIPTORS must be defined in FreeRTOSConfig.h to set the number of RX DMA descriptors -#endif - -#ifndef configNUM_TX_ETHERNET_DMA_DESCRIPTORS - #error configNUM_TX_ETHERNET_DMA_DESCRIPTORS must be defined in FreeRTOSConfig.h to set the number of TX DMA descriptors -#endif - -/* If a packet cannot be sent immediately then the task performing the send -operation will be held in the Blocked state (so other tasks can execute) for -niTX_BUFFER_FREE_WAIT ticks. It will do this a maximum of niMAX_TX_ATTEMPTS -before giving up. */ -#define niTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_RATE_MS ) -#define niMAX_TX_ATTEMPTS ( 5 ) - -/*-----------------------------------------------------------*/ - -/* - * A deferred interrupt handler task that processes received frames. - */ -static void prvEMACDeferredInterruptHandlerTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used to communicate Ethernet events to the IP task. */ -extern xQueueHandle xNetworkEventQueue; - -/* The semaphore used to wake the deferred interrupt handler task when an Rx -interrupt is received. */ -xSemaphoreHandle xEMACRxEventSemaphore = NULL; - -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceInitialise( void ) -{ -BaseType_t xReturn; -extern uint8_t ucMACAddress[ 6 ]; - - xReturn = xEMACInit( ucMACAddress ); - - if( xReturn == pdPASS ) - { - /* Create the event semaphore if it has not already been created. */ - if( xEMACRxEventSemaphore == NULL ) - { - vSemaphoreCreateBinary( xEMACRxEventSemaphore ); - #if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 - { - /* If the trace recorder code is included name the semaphore for - viewing in FreeRTOS+Trace. */ - vTraceSetQueueName( xEMACRxEventSemaphore, "MAC_RX" ); - } - #endif /* ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 */ - - configASSERT( xEMACRxEventSemaphore ); - - /* The Rx deferred interrupt handler task is created at the highest - possible priority to ensure the interrupt handler can return directly to - it no matter which task was running when the interrupt occurred. */ - xTaskCreate( prvEMACDeferredInterruptHandlerTask,/* The function that implements the task. */ - "MACTsk", - configMINIMAL_STACK_SIZE, /* Stack allocated to the task (defined in words, not bytes). */ - NULL, /* The task parameter is not used. */ - configMAX_PRIORITIES - 1, /* The priority assigned to the task. */ - NULL ); /* The handle is not required, so NULL is passed. */ - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -BaseType_t xReturn = pdFAIL; -int32_t x; - - /* Attempt to obtain access to a Tx descriptor. */ - for( x = 0; x < niMAX_TX_ATTEMPTS; x++ ) - { - if( xEMACIsTxDescriptorAvailable() == TRUE ) - { - /* Assign the buffer being transmitted to the Tx descriptor. */ - vEMACAssignBufferToDescriptor( pxNetworkBuffer->pucEthernetBuffer ); - - /* The EMAC now owns the buffer and will free it when it has been - transmitted. Set pucBuffer to NULL to ensure the buffer is not - freed when the network buffer structure is returned to the pool - of network buffers. */ - pxNetworkBuffer->pucEthernetBuffer = NULL; - - /* Initiate the Tx. */ - vEMACStartNextTransmission( pxNetworkBuffer->xDataLength ); - iptraceNETWORK_INTERFACE_TRANSMIT(); - - /* The Tx has been initiated. */ - xReturn = pdPASS; - - break; - } - else - { - iptraceWAITING_FOR_TX_DMA_DESCRIPTOR(); - vTaskDelay( niTX_BUFFER_FREE_WAIT ); - } - } - - /* Finished with the network buffer. */ - vNetworkBufferRelease( pxNetworkBuffer ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static void prvEMACDeferredInterruptHandlerTask( void *pvParameters ) -{ -xNetworkBufferDescriptor_t *pxNetworkBuffer; -xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL }; - - ( void ) pvParameters; - configASSERT( xEMACRxEventSemaphore ); - - for( ;; ) - { - /* Wait for the EMAC interrupt to indicate that another packet has been - received. The while() loop is only needed if INCLUDE_vTaskSuspend is - set to 0 in FreeRTOSConfig.h. If INCLUDE_vTaskSuspend is set to 1 - then portMAX_DELAY would be an indefinite block time and - xSemaphoreTake() would only return when the semaphore was actually - obtained. */ - while( xSemaphoreTake( xEMACRxEventSemaphore, portMAX_DELAY ) == pdFALSE ); - - /* At least one packet has been received. */ - while( xEMACRxDataAvailable() != FALSE ) - { - /* The buffer filled by the DMA is going to be passed into the IP - stack. Allocate another buffer for the DMA descriptor. */ - pxNetworkBuffer = pxNetworkBufferGet( ipTOTAL_ETHERNET_FRAME_SIZE, ( TickType_t ) 0 ); - - if( pxNetworkBuffer != NULL ) - { - /* Swap the buffer just allocated and referenced from the - pxNetworkBuffer with the buffer that has already been filled by - the DMA. pxNetworkBuffer will then hold a reference to the - buffer that already contains the data without any data having - been copied between buffers. */ - vEMACSwapEmptyBufferForRxedData( pxNetworkBuffer ); - - #if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 1 - { - if( pxNetworkBuffer->xDataLength > 0 ) - { - /* If the frame would not be processed by the IP stack then - don't even bother sending it to the IP stack. */ - if( eConsiderFrameForProcessing( pxNetworkBuffer->pucEthernetBuffer ) != eProcessBuffer ) - { - pxNetworkBuffer->xDataLength = 0; - } - } - } - #endif - - if( pxNetworkBuffer->xDataLength > 0 ) - { - /* Store a pointer to the network buffer structure in the - padding space that was left in front of the Ethernet frame. - The pointer is needed to ensure the network buffer structure - can be located when it is time for it to be freed if the - Ethernet frame gets used as a zero copy buffer. */ - *( ( xNetworkBufferDescriptor_t ** ) ( ( pxNetworkBuffer->pucEthernetBuffer - ipBUFFER_PADDING ) ) ) = pxNetworkBuffer; - - /* Data was received and stored. Send it to the IP task - for processing. */ - xRxEvent.pvData = ( void * ) pxNetworkBuffer; - if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( TickType_t ) 0 ) == pdFALSE ) - { - /* The buffer could not be sent to the IP task so the - buffer must be released. */ - vNetworkBufferRelease( pxNetworkBuffer ); - iptraceETHERNET_RX_EVENT_LOST(); - } - else - { - iptraceNETWORK_INTERFACE_RECEIVE(); - } - } - else - { - /* The buffer does not contain any data so there is no - point sending it to the IP task. Just release it. */ - vNetworkBufferRelease( pxNetworkBuffer ); - iptraceETHERNET_RX_EVENT_LOST(); - } - } - else - { - iptraceETHERNET_RX_EVENT_LOST(); - } - - /* Release the descriptor. */ - vEMACReturnRxDescriptor(); - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/lpc18xx_43xx_EMAC_LPCOpen.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/lpc18xx_43xx_EMAC_LPCOpen.c deleted file mode 100644 index 1e64a4974..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/lpc18xx_43xx_EMAC_LPCOpen.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "NetworkBufferManagement.h" - -/* Library includes. */ -#include "board.h" - -/* Descriptors that reference received buffers are expected to have both the -first and last frame bits set because buffers are dimensioned to hold complete -Ethernet frames. */ -#define emacEXPECTED_RX_STATUS_MASK ( RDES_LS | RDES_FS ) - -/*-----------------------------------------------------------*/ - -/* - * Set the Rx and Tx descriptors into their expected initial state. - */ -static void prvResetRxDescriptors( void ); -static void prvResetTxDescriptors( void ); - -/* - * Returns the length of the data pointed to by the next Rx descriptor. - */ -static uint32_t prvReceivedDataLength( void ); - - -/*-----------------------------------------------------------*/ - -/* Rx and Tx descriptors and data array. */ -static volatile IP_ENET_001_ENHRXDESC_T xRXDescriptors[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ]; -static volatile IP_ENET_001_ENHTXDESC_T xTxDescriptors[ configNUM_TX_ETHERNET_DMA_DESCRIPTORS ]; - -/* Indexes into the Rx and Tx descriptor arrays. */ -static unsigned int xRxDescriptorIndex = 0; -static unsigned int xTxDescriptorIndex = 0; - -/*-----------------------------------------------------------*/ - -BaseType_t xEMACInit( uint8_t ucMACAddress[ 6 ] ) -{ -BaseType_t xReturn; -uint32_t ulPHYStatus; - - /* Configure the hardware. */ - Chip_ENET_Init( LPC_ETHERNET ); - - if( lpc_phy_init( pdTRUE, vTaskDelay ) == SUCCESS ) - { - /* The MAC address is passed in as the function parameter. */ - Chip_ENET_SetADDR( LPC_ETHERNET, ucMACAddress ); - - /* Wait for autonegotiation to complete. */ - do - { - vTaskDelay( 100 ); - ulPHYStatus = lpcPHYStsPoll(); - } while( ( ulPHYStatus & PHY_LINK_CONNECTED ) == 0x00 ); - - /* Configure the hardware as per the negotiated link. */ - if( ( ulPHYStatus & PHY_LINK_FULLDUPLX ) == PHY_LINK_FULLDUPLX ) - { - IP_ENET_SetDuplex( LPC_ETHERNET, pdTRUE ); - } - else - { - IP_ENET_SetDuplex( LPC_ETHERNET, pdFALSE ); - } - - if( ( ulPHYStatus & PHY_LINK_SPEED100 ) == PHY_LINK_SPEED100 ) - { - IP_ENET_SetSpeed( LPC_ETHERNET, pdTRUE ); - } - else - { - IP_ENET_SetSpeed( LPC_ETHERNET, pdFALSE ); - } - - /* Set descriptors to their initial state. */ - prvResetRxDescriptors(); - prvResetTxDescriptors(); - - /* Enable RX and TX. */ - Chip_ENET_TXEnable( LPC_ETHERNET ); - Chip_ENET_RXEnable( LPC_ETHERNET ); - - /* Enable the interrupt and set its priority as configured. THIS - DRIVER REQUIRES configMAC_INTERRUPT_PRIORITY TO BE DEFINED, PREFERABLY - IN FreeRTOSConfig.h. */ - NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY ); - NVIC_EnableIRQ( ETHERNET_IRQn ); - - /* Enable interrupts. */ - LPC_ETHERNET->DMA_INT_EN = DMA_IE_NIE | DMA_IE_RIE; - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -BaseType_t xEMACIsTxDescriptorAvailable( void ) -{ -BaseType_t xReturn; - - if( ( xTxDescriptors[ xTxDescriptorIndex ].CTRLSTAT & RDES_OWN ) == 0 ) - { - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vEMACAssignBufferToDescriptor( uint8_t * pucBuffer ) -{ - /* The old packet is now finished with and can be freed. */ - vEthernetBufferRelease( ( void * ) xTxDescriptors[ xTxDescriptorIndex ].B1ADD ); - - /* Assign the new packet to the descriptor. */ - xTxDescriptors[ xTxDescriptorIndex ].B1ADD = ( uint32_t ) pucBuffer; -} -/*-----------------------------------------------------------*/ - -void vEMACStartNextTransmission( uint32_t ulLength ) -{ - xTxDescriptors[ xTxDescriptorIndex ].BSIZE = ulLength; - xTxDescriptors[ xTxDescriptorIndex ].CTRLSTAT |= RDES_OWN; - - /* Wake Up the DMA if it's in Suspended Mode. */ - LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; - xTxDescriptorIndex++; - - if( xTxDescriptorIndex == configNUM_TX_ETHERNET_DMA_DESCRIPTORS ) - { - xTxDescriptorIndex = 0; - } -} -/*-----------------------------------------------------------*/ - -static uint32_t prvReceivedDataLength( void ) -{ -unsigned short RxLen = 0; - - RxLen = ( xRXDescriptors[ xRxDescriptorIndex ].STATUS >> 16 ) & 0x03FFF; - return RxLen; -} -/*-----------------------------------------------------------*/ - -void vEMACReturnRxDescriptor( void ) -{ - xRXDescriptors[ xRxDescriptorIndex ].STATUS = RDES_OWN; - xRxDescriptorIndex++; - - if( xRxDescriptorIndex == configNUM_RX_ETHERNET_DMA_DESCRIPTORS ) - { - xRxDescriptorIndex = 0; - } -} -/*-----------------------------------------------------------*/ - -BaseType_t xEMACRxDataAvailable( void ) -{ -BaseType_t xReturn; - - if( ( xRXDescriptors[ xRxDescriptorIndex ].STATUS & RDES_OWN ) == 0 ) - { - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vEMACSwapEmptyBufferForRxedData( xNetworkBufferDescriptor_t *pxNetworkBuffer ) -{ -uint8_t *pucTemp; - - /* Swap the buffer in the network buffer with the buffer used by the DMA. - This allows the data to be passed out without having to perform any copies. */ - pucTemp = ( uint8_t * ) xRXDescriptors[ xRxDescriptorIndex ].B1ADD; - xRXDescriptors[ xRxDescriptorIndex ].B1ADD = ( uint32_t ) pxNetworkBuffer->pucEthernetBuffer; - pxNetworkBuffer->pucEthernetBuffer = pucTemp; - - /* Only supports frames coming in single buffers. If this frame is split - across multiple buffers then reject it (and if the frame is needed increase - the ipconfigNETWORK_MTU setting). */ - if( ( xRXDescriptors[ xRxDescriptorIndex ].STATUS & emacEXPECTED_RX_STATUS_MASK ) != emacEXPECTED_RX_STATUS_MASK ) - { - pxNetworkBuffer->xDataLength = 0; - } - else - { - pxNetworkBuffer->xDataLength = ( size_t ) prvReceivedDataLength() - ( ipETHERNET_CRC_BYTES - 1U );; - } -} -/*-----------------------------------------------------------*/ - -static void prvResetRxDescriptors( void ) -{ -uint32_t x; -size_t xBufferSize = ipTOTAL_ETHERNET_FRAME_SIZE; - - for( x = 0; x < configNUM_RX_ETHERNET_DMA_DESCRIPTORS; x++ ) - { - /* Obtain the buffer first, as the size of the buffer might be changed - within the pucEthernetBufferGet() call. */ - xRXDescriptors[ x ].B1ADD = ( uint32_t ) pucEthernetBufferGet( &xBufferSize ); - xRXDescriptors[ x ].STATUS = RDES_OWN; - xRXDescriptors[ x ].CTRL = xBufferSize; - xRXDescriptors[ x ].B2ADD = ( uint32_t ) &xRXDescriptors[ x + 1 ]; - - configASSERT( ( ( ( uint32_t ) xRXDescriptors[x].B1ADD ) & 0x07 ) == 0 ); - } - - /* Last Descriptor */ - xRXDescriptors[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS - 1 ].CTRL |= RDES_ENH_RER; - - xRxDescriptorIndex = 0; - - /* Set Starting address of RX Descriptor list */ - LPC_ETHERNET->DMA_REC_DES_ADDR = ( uint32_t ) xRXDescriptors; -} -/*-----------------------------------------------------------*/ - -static void prvResetTxDescriptors( void ) -{ -/* Initialize Transmit Descriptor and Status array. */ -uint32_t x; - - for( x = 0; x < configNUM_TX_ETHERNET_DMA_DESCRIPTORS; x++ ) - { - xTxDescriptors[ x ].CTRLSTAT = TDES_ENH_FS | TDES_ENH_LS; - xTxDescriptors[ x ].BSIZE = 0; - xTxDescriptors[ x ].B2ADD = ( uint32_t ) &xTxDescriptors[ x + 1 ]; - - /* Packet is assigned when a Tx is initiated. */ - xTxDescriptors[ x ].B1ADD = ( uint32_t )NULL; - } - - /* Last Descriptor? */ - xTxDescriptors[ configNUM_TX_ETHERNET_DMA_DESCRIPTORS-1 ].CTRLSTAT |= TDES_ENH_TER; - - /* Set Starting address of TX Descriptor list */ - LPC_ETHERNET->DMA_TRANS_DES_ADDR = ( uint32_t ) xTxDescriptors; -} -/*-----------------------------------------------------------*/ - -void ETH_IRQHandler( void ) -{ -uint32_t ulInterruptCause; -extern xSemaphoreHandle xEMACRxEventSemaphore; - - configASSERT( xEMACRxEventSemaphore ); - - ulInterruptCause = LPC_ETHERNET->DMA_STAT ; - - /* Clear the interrupt. */ - LPC_ETHERNET->DMA_STAT |= ( DMA_ST_NIS | DMA_ST_RI ); - - /* Clear fatal error conditions. NOTE: The driver does not clear all - errors, only those actually experienced. For future reference, range - errors are not actually errors so can be ignored. */ - if( ( ulInterruptCause & DMA_ST_FBI ) != 0U ) - { - LPC_ETHERNET->DMA_STAT |= DMA_ST_FBI; - } - - /* Unblock the deferred interrupt handler task if the event was an Rx. */ - if( ( ulInterruptCause & DMA_IE_RIE ) != 0UL ) - { - xSemaphoreGiveFromISR( xEMACRxEventSemaphore, NULL ); - } - - /* ulInterruptCause is used for convenience here. A context switch is - wanted, but coding portEND_SWITCHING_ISR( 1 ) would likely result in a - compiler warning. */ - portEND_SWITCHING_ISR( ulInterruptCause ); -} - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/lpc18xx_43xx_EMAC_LPCOpen.h b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/lpc18xx_43xx_EMAC_LPCOpen.h deleted file mode 100644 index e7c03d83d..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx/Using_LPCOpen_Library/lpc18xx_43xx_EMAC_LPCOpen.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef LPC18xx_43xx_EMAC_H -#define LPC18xx_43xx_EMAC_H - -/* - * Initialise the MAC and PHY. - */ -BaseType_t xEMACInit( uint8_t ucMACAddress[ 6 ] ); - -/* - * Return pdTRUE if there is a FreeRTOS Tx descriptor. Return pdFALSE if all - * Tx descriptors are already in use. - */ -BaseType_t xEMACIsTxDescriptorAvailable( void ); - -/* - * Assign a buffer to a Tx descriptor so it is ready to be transmitted, but - * don't start the transmission yet. - */ -void vEMACAssignBufferToDescriptor( uint8_t * pucBuffer ); - -/* - * Start transmitting the buffer pointed to by the next Tx descriptor. The - * buffer must have first been allocated to the Tx descriptor using a call to - * vEMACAssignBufferToDescriptor(). - */ -void vEMACStartNextTransmission( uint32_t ulLength ); - -/* - * The data pointed to by the Rx descriptor has been consumed, and the Rx - * descriptor can be returned to the control of the DMS. - */ -void vEMACReturnRxDescriptor( void ); - -/* - * Returns pdTRUE if the next Rx descriptor contains received data. Returns - * pdFLASE fi the next Rx descriptor is still under the control of the DMA. - */ -BaseType_t xEMACRxDataAvailable( void ); -void vEMACSwapEmptyBufferForRxedData( xNetworkBufferDescriptor_t *pxNetworkBuffer ); - -#endif /* LPC18xx_43xx_EMAC_H */ - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/SAM4E/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/SAM4E/NetworkInterface.c deleted file mode 100644 index 58c33006f..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/SAM4E/NetworkInterface.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkBufferManagement.h" - -/* Demo includes. */ -#include "NetworkInterface.h" - -/* If a packet cannot be sent immediately then the task performing the send -operation will be held in the Blocked state (so other tasks can execute) for -niTX_BUFFER_FREE_WAIT ticks. It will do this a maximum of niMAX_TX_ATTEMPTS -before giving up. */ -#define niTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_RATE_MS ) -#define niMAX_TX_ATTEMPTS ( 5 ) - -/*-----------------------------------------------------------*/ - -/* - * A deferred interrupt handler task that processes received frames. - */ -static void prvGMACDeferredInterruptHandlerTask( void *pvParameters ); - -/* - * Called by the ASF GMAC driver when a packet is received. - */ -static void prvGMACRxCallback( uint32_t ulStatus ); - -/*-----------------------------------------------------------*/ - -/* The queue used to communicate Ethernet events to the IP task. */ -extern xQueueHandle xNetworkEventQueue; - -/* The GMAC driver instance. */ -static gmac_device_t xGMACStruct; - -/* Handle of the task used to process MAC events. */ -static TaskHandle_t xMACEventHandlingTask = NULL; - -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceInitialise( void ) -{ -gmac_options_t xGMACOptions; -extern uint8_t ucMACAddress[ 6 ]; -const TickType_t xPHYDelay_400ms = 400UL; -BaseType_t xReturn = pdFALSE; - - /* Ensure PHY is ready. */ - vTaskDelay( xPHYDelay_400ms / portTICK_RATE_MS ); - - /* Enable GMAC clock. */ - pmc_enable_periph_clk( ID_GMAC ); - - /* Fill in GMAC options */ - xGMACOptions.uc_copy_all_frame = 0; - xGMACOptions.uc_no_boardcast = 0; - memcpy( xGMACOptions.uc_mac_addr, ucMACAddress, sizeof( ucMACAddress ) ); - - xGMACStruct.p_hw = GMAC; - - /* Init GMAC driver structure. */ - gmac_dev_init( GMAC, &xGMACStruct, &xGMACOptions ); - - /* Init MAC PHY driver. */ - if( ethernet_phy_init( GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz() ) == GMAC_OK ) - { - /* Auto Negotiate, work in RMII mode. */ - if( ethernet_phy_auto_negotiate( GMAC, BOARD_GMAC_PHY_ADDR ) == GMAC_OK ) - { - /* Establish Ethernet link. */ - vTaskDelay( xPHYDelay_400ms * 2UL ); - if( ethernet_phy_set_link( GMAC, BOARD_GMAC_PHY_ADDR, 1 ) == GMAC_OK ) - { - /* Register the callbacks. */ - gmac_dev_set_rx_callback( &xGMACStruct, prvGMACRxCallback ); - - /* The Rx deferred interrupt handler task is created at the - highest possible priority to ensure the interrupt handler can - return directly to it no matter which task was running when the - interrupt occurred. */ - xTaskCreate( prvGMACDeferredInterruptHandlerTask,/* The function that implements the task. */ - "MACTsk", - configMINIMAL_STACK_SIZE, /* Stack allocated to the task (defined in words, not bytes). */ - NULL, /* The task parameter is not used. */ - configMAX_PRIORITIES - 1, /* The priority assigned to the task. */ - &xMACEventHandlingTask ); /* The handle is stored so the ISR knows which task to notify. */ - - /* Enable the interrupt and set its priority as configured. - THIS DRIVER REQUIRES configMAC_INTERRUPT_PRIORITY TO BE DEFINED, - PREFERABLY IN FreeRTOSConfig.h. */ - NVIC_SetPriority( GMAC_IRQn, configMAC_INTERRUPT_PRIORITY ); - NVIC_EnableIRQ( GMAC_IRQn ); - xReturn = pdPASS; - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static void prvGMACRxCallback( uint32_t ulStatus ) -{ -BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - configASSERT( xMACEventHandlingTask ); - - /* Unblock the deferred interrupt handler task if the event was an Rx. */ - if( ( ulStatus & GMAC_RSR_REC ) != 0 ) - { - vTaskNotifyGiveFromISR( xMACEventHandlingTask, &xHigherPriorityTaskWoken ); - } - - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); -} -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -BaseType_t xReturn = pdFAIL; -int32_t x; - - /* Attempt to obtain access to a Tx descriptor. */ - for( x = 0; x < niMAX_TX_ATTEMPTS; x++ ) - { - if( gmac_dev_write( &xGMACStruct, pxNetworkBuffer->pucEthernetBuffer, ( uint32_t ) pxNetworkBuffer->xDataLength, NULL ) == GMAC_OK ) - { - /* The Tx has been initiated. */ - xReturn = pdPASS; - break; - } - else - { - iptraceWAITING_FOR_TX_DMA_DESCRIPTOR(); - vTaskDelay( niTX_BUFFER_FREE_WAIT ); - } - } - - /* Finished with the network buffer. */ - vNetworkBufferRelease( pxNetworkBuffer ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void GMAC_Handler( void ) -{ - gmac_handler( &xGMACStruct ); -} -/*-----------------------------------------------------------*/ - -static void prvGMACDeferredInterruptHandlerTask( void *pvParameters ) -{ -xNetworkBufferDescriptor_t *pxNetworkBuffer = NULL; -xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL }; -static const TickType_t xBufferWaitDelay = 1500UL / portTICK_RATE_MS; -uint32_t ulReturned; - - /* This is a very simply but also inefficient implementation. */ - - ( void ) pvParameters; - - for( ;; ) - { - /* Wait for the GMAC interrupt to indicate that another packet has been - received. A while loop is used to process all received frames each time - this task is notified, so it is ok to clear the notification count on the - take (hence the first parameter is pdTRUE ). */ - ulTaskNotifyTake( pdTRUE, xBufferWaitDelay ); - - ulReturned = GMAC_OK; - while( ulReturned == GMAC_OK ) - { - /* Allocate a buffer to hold the data if one is not already held. */ - if( pxNetworkBuffer == NULL ) - { - pxNetworkBuffer = pxNetworkBufferGet( ipTOTAL_ETHERNET_FRAME_SIZE, xBufferWaitDelay ); - } - - if( pxNetworkBuffer != NULL ) - { - /* Attempt to read data. */ - ulReturned = gmac_dev_read( &xGMACStruct, pxNetworkBuffer->pucEthernetBuffer, ipTOTAL_ETHERNET_FRAME_SIZE, ( uint32_t * ) &( pxNetworkBuffer->xDataLength ) ); - - if( ulReturned == GMAC_OK ) - { - #if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 1 - { - if( pxNetworkBuffer->xDataLength > 0 ) - { - /* If the frame would not be processed by the IP - stack then don't even bother sending it to the IP - stack. */ - if( eConsiderFrameForProcessing( pxNetworkBuffer->pucEthernetBuffer ) != eProcessBuffer ) - { - pxNetworkBuffer->xDataLength = 0; - } - } - } - #endif - - if( pxNetworkBuffer->xDataLength > 0 ) - { - /* Store a pointer to the network buffer structure in - the padding space that was left in front of the Ethernet - frame. The pointer is needed to ensure the network - buffer structure can be located when it is time for it - to be freed if the Ethernet frame gets used as a zero - copy buffer. */ - *( ( xNetworkBufferDescriptor_t ** ) ( ( pxNetworkBuffer->pucEthernetBuffer - ipBUFFER_PADDING ) ) ) = pxNetworkBuffer; - - /* Data was received and stored. Send it to the IP task - for processing. */ - xRxEvent.pvData = ( void * ) pxNetworkBuffer; - if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( TickType_t ) 0 ) == pdFALSE ) - { - /* The buffer could not be sent to the IP task. The - frame will be dropped and the buffer reused. */ - iptraceETHERNET_RX_EVENT_LOST(); - } - else - { - iptraceNETWORK_INTERFACE_RECEIVE(); - - /* The buffer is not owned by the IP task - a new - buffer is needed the next time around. */ - pxNetworkBuffer = NULL; - } - } - else - { - /* The buffer does not contain any data so there is no - point sending it to the IP task. Re-use the buffer on - the next loop. */ - iptraceETHERNET_RX_EVENT_LOST(); - } - } - else - { - /* No data was received, keep the buffer for re-use. The - loop will exit as ulReturn is not GMAC_OK. */ - } - } - else - { - /* Left a frame in the driver as a buffer was not available. - Break out of loop. */ - ulReturned = GMAC_INVALID; - } - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/SH2A/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/SH2A/NetworkInterface.c deleted file mode 100644 index fbf4b7bb1..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/SH2A/NetworkInterface.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkBufferManagement.h" - -/* Hardware includes. */ -#include "hwEthernet.h" - -/* Demo includes. */ -#include "NetworkInterface.h" - -#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES != 1 - #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer -#else - #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) -#endif - -/* When a packet is ready to be sent, if it cannot be sent immediately then the -task performing the transmit will block for niTX_BUFFER_FREE_WAIT -milliseconds. It will do this a maximum of niMAX_TX_ATTEMPTS before giving -up. */ -#define niTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_RATE_MS ) -#define niMAX_TX_ATTEMPTS ( 5 ) - -/* The length of the queue used to send interrupt status words from the -interrupt handler to the deferred handler task. */ -#define niINTERRUPT_QUEUE_LENGTH ( 10 ) - -/*-----------------------------------------------------------*/ - -/* - * A deferred interrupt handler task that processes - */ -extern void vEMACHandlerTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used to communicate Ethernet events with the IP task. */ -extern xQueueHandle xNetworkEventQueue; - -/* The semaphore used to wake the deferred interrupt handler task when an Rx -interrupt is received. */ -xSemaphoreHandle xEMACRxEventSemaphore = NULL; -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceInitialise( void ) -{ -BaseType_t xStatus, xReturn; -extern uint8_t ucMACAddress[ 6 ]; - - /* Initialise the MAC. */ - vInitEmac(); - - while( lEMACWaitForLink() != pdPASS ) - { - vTaskDelay( 20 ); - } - - vSemaphoreCreateBinary( xEMACRxEventSemaphore ); - configASSERT( xEMACRxEventSemaphore ); - - /* The handler task is created at the highest possible priority to - ensure the interrupt handler can return directly to it. */ - xTaskCreate( vEMACHandlerTask, "EMAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); - xReturn = pdPASS; - - return xReturn; -} -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) -{ -extern void vEMACCopyWrite( uint8_t * pucBuffer, uint16_t usLength ); - - vEMACCopyWrite( pxNetworkBuffer->pucEthernetBuffer, pxNetworkBuffer->xDataLength ); - - /* Finished with the network buffer. */ - vNetworkBufferRelease( pxNetworkBuffer ); - - return pdTRUE; -} -/*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/WinPCap/NetworkInterface.c b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/WinPCap/NetworkInterface.c deleted file mode 100644 index ce9c4733e..000000000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/WinPCap/NetworkInterface.c +++ /dev/null @@ -1,475 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* WinPCap includes. */ -#define HAVE_REMOTE -#include "pcap.h" - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_Sockets.h" -#include "NetworkBufferManagement.h" - -/* Demo includes. */ -#include "NetworkInterface.h" - -/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1, then the Ethernet -driver will filter incoming packets and only pass the stack those packets it -considers need processing. In this case ipCONSIDER_FRAME_FOR_PROCESSING() can -be #defined away. If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 0 -then the Ethernet driver will pass all received packets to the stack, and the -stack must do the filtering itself. In this case ipCONSIDER_FRAME_FOR_PROCESSING -needs to call eConsiderFrameForProcessing. */ -#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES != 1 - #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer -#else - #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) -#endif - -/*-----------------------------------------------------------*/ - -/* - * Print out a numbered list of network interfaces that are available on the - * host computer. - */ -static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ); - -/* - * Open the network interface. The number of the interface to be opened is set - * by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. - */ -static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ); - -/* - * Configure the capture filter to allow blocking reads, and to filter out - * packets that are not of interest to this demo. - */ -static void prvConfigureCaptureBehaviour( void ); - -/* - * A function that simulates Ethernet interrupts by periodically polling the - * WinPCap interface for new data. - */ -static void prvInterruptSimulatorTask( void *pvParameters ); - -/* The interface being used by WinPCap. */ -static pcap_t *pxOpenedInterfaceHandle = NULL; - -/*-----------------------------------------------------------*/ - -/* Required by the WinPCap library. */ -static char cErrorBuffer[ PCAP_ERRBUF_SIZE ]; - -/* When statically allocated network buffers are used (as opposed to having -the buffer payloads allocated and freed as required) the actual buffer storage -areas must be defined in the portable layer. This is because different -microcontrollers have different location, size and alignment requirements. In -this case the network buffers are declared in NetworkInterface.c because, as -this file is only used on Windows machines, wasting a few bytes in buffers that -never get used does not matter (the buffers will not get used if the dynamic -payload allocation file is included in the project). */ -static uint8_t ucBuffers[ ipconfigNUM_NETWORK_BUFFERS ][ ipTOTAL_ETHERNET_FRAME_SIZE + ipBUFFER_PADDING ]; - -/* The queue used to communicate Ethernet events with the IP task. */ -extern xQueueHandle xNetworkEventQueue; - -/* Protect the PCAP interface as it is accessed from two tasks (an interrupt -simulator is used as real interrupts cannot be obtained from the Ethernet as -would normally be the case). */ -xSemaphoreHandle xPCAPMutex = NULL; - -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceInitialise( void ) -{ -BaseType_t xReturn = pdFALSE; -pcap_if_t *pxAllNetworkInterfaces; - - if( xPCAPMutex == NULL ) - { - xPCAPMutex = xSemaphoreCreateMutex(); - configASSERT( xPCAPMutex ); - } - - /* Query the computer the simulation is being executed on to find the - network interfaces it has installed. */ - pxAllNetworkInterfaces = prvPrintAvailableNetworkInterfaces(); - - /* Open the network interface. The number of the interface to be opened is - set by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. - Calling this function will set the pxOpenedInterfaceHandle variable. If, - after calling this function, pxOpenedInterfaceHandle is equal to NULL, then - the interface could not be opened. */ - if( pxAllNetworkInterfaces != NULL ) - { - prvOpenSelectedNetworkInterface( pxAllNetworkInterfaces ); - } - - if( pxOpenedInterfaceHandle != NULL ) - { - xReturn = pdPASS; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if updconfigLOOPBACK_ETHERNET_PACKETS == 1 - - BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) - { - xEthernetHeader_t *pxEthernetHeader; - xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL }; - extern uint8_t xDefaultPartUDPPacketHeader[]; - static const xMACAddress_t xBroadcastMACAddress = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; - BaseType_t xCanLoopback; - - pxEthernetHeader = ( xEthernetHeader_t * ) pxNetworkBuffer->pucEthernetBuffer; - - if( memcmp( ( void * ) &( pxEthernetHeader->xDestinationAddress ), ( void * ) &xBroadcastMACAddress, sizeof( xMACAddress_t ) ) == 0 ) - { - /* This is a broadcast. */ - xCanLoopback = pdTRUE; - } - else if( memcmp( ( void * ) &( pxEthernetHeader->xDestinationAddress ), ( void * ) xDefaultPartUDPPacketHeader, sizeof( xMACAddress_t ) ) == 0 ) - { - /* This is being sent to itself. */ - xCanLoopback = pdTRUE; - } - else - { - /* This is being sent externally. */ - xCanLoopback = pdFALSE; - } - - iptraceNETWORK_INTERFACE_TRANSMIT(); - - if( xCanLoopback == pdTRUE ) - { - /* Just loop the frame back to the input queue. Here the loopback - is sending a message to itself, so a block time cannot be used for - fear of deadlocking. */ - xRxEvent.pvData = ( void * ) pxNetworkBuffer; - if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( TickType_t ) 0 ) == pdFALSE ) - { - vNetworkBufferRelease( pxNetworkBuffer ); - iptraceETHERNET_RX_EVENT_LOST(); - } - else - { - iptraceNETWORK_INTERFACE_RECEIVE(); - } - } - else - { - /* Send the packet. */ - xSemaphoreTake( xPCAPMutex, portMAX_DELAY ); - { - pcap_sendpacket( pxOpenedInterfaceHandle, pxNetworkBuffer->pucEthernetBuffer, pxNetworkBuffer->xDataLength ); - } - xSemaphoreGive( xPCAPMutex ); - - /* The buffer has been transmitted so can be released. */ - vNetworkBufferRelease( pxNetworkBuffer ); - } - - return pdPASS; - } - -#else /* updconfigLOOPBACK_ETHERNET_PACKETS == 1 */ - - BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer ) - { - xSemaphoreTake( xPCAPMutex, portMAX_DELAY ); - { - iptraceNETWORK_INTERFACE_TRANSMIT(); - pcap_sendpacket( pxOpenedInterfaceHandle, pxNetworkBuffer->pucEthernetBuffer, pxNetworkBuffer->xDataLength ); - } - xSemaphoreGive( xPCAPMutex ); - - /* The buffer has been transmitted so can be released. */ - vNetworkBufferRelease( pxNetworkBuffer ); - - return pdPASS; - } - -#endif /* updconfigLOOPBACK_ETHERNET_PACKETS == 1 */ -/*-----------------------------------------------------------*/ - -static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ) -{ -pcap_if_t * pxAllNetworkInterfaces = NULL, *xInterface; -long lInterfaceNumber = 1; - - if( pcap_findalldevs_ex( PCAP_SRC_IF_STRING, NULL, &pxAllNetworkInterfaces, cErrorBuffer ) == -1 ) - { - printf( "\r\nCould not obtain a list of network interfaces\r\n%s\r\n", cErrorBuffer ); - pxAllNetworkInterfaces = NULL; - } - - if( pxAllNetworkInterfaces != NULL ) - { - /* Print out the list of network interfaces. The first in the list - is interface '1', not interface '0'. */ - for( xInterface = pxAllNetworkInterfaces; xInterface != NULL; xInterface = xInterface->next ) - { - printf( "%d. %s", lInterfaceNumber, xInterface->name ); - - if( xInterface->description != NULL ) - { - printf( " (%s)\r\n", xInterface->description ); - } - else - { - printf( " (No description available)\r\n") ; - } - - lInterfaceNumber++; - } - } - - if( lInterfaceNumber == 1 ) - { - /* The interface number was never incremented, so the above for() loop - did not execute meaning no interfaces were found. */ - printf( " \r\nNo network interfaces were found.\r\n" ); - pxAllNetworkInterfaces = NULL; - } - - printf( "\r\nThe interface that will be opened is set by configNETWORK_INTERFACE_TO_USE which should be defined in FreeRTOSConfig.h\r\n" ); - printf( "Attempting to open interface number %d.\r\n", configNETWORK_INTERFACE_TO_USE ); - - if( ( configNETWORK_INTERFACE_TO_USE < 1L ) || ( configNETWORK_INTERFACE_TO_USE > lInterfaceNumber ) ) - { - printf("\r\nconfigNETWORK_INTERFACE_TO_USE is not in the valid range.\r\n" ); - - if( pxAllNetworkInterfaces != NULL ) - { - /* Free the device list, as no devices are going to be opened. */ - pcap_freealldevs( pxAllNetworkInterfaces ); - pxAllNetworkInterfaces = NULL; - } - } - - return pxAllNetworkInterfaces; -} -/*-----------------------------------------------------------*/ - -static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ) -{ -pcap_if_t *xInterface; -long x; - - /* Walk the list of devices until the selected device is located. */ - xInterface = pxAllNetworkInterfaces; - for( x = 0L; x < ( configNETWORK_INTERFACE_TO_USE - 1L ); x++ ) - { - xInterface = xInterface->next; - } - - /* Open the selected interface. */ - pxOpenedInterfaceHandle = pcap_open( xInterface->name, /* The name of the selected interface. */ - ipTOTAL_ETHERNET_FRAME_SIZE, /* The size of the packet to capture. */ - PCAP_OPENFLAG_PROMISCUOUS, /* Open in promiscious mode as the MAC and - IP address is going to be "simulated", and - not be the real MAC and IP address. This allows - trafic to the simulated IP address to be routed - to uIP, and trafic to the real IP address to be - routed to the Windows TCP/IP stack. */ - 0x00L, /* The read time out. */ - NULL, /* No authentication is required as this is - not a remote capture session. */ - cErrorBuffer - ); - - if ( pxOpenedInterfaceHandle == NULL ) - { - printf( "\r\n%s is not supported by WinPcap and cannot be opened\r\n", xInterface->name ); - } - else - { - /* Configure the capture filter to allow blocking reads, and to filter - out packets that are not of interest to this demo. */ - prvConfigureCaptureBehaviour(); - } - - /* The device list is no longer required. */ - pcap_freealldevs( pxAllNetworkInterfaces ); -} -/*-----------------------------------------------------------*/ - -static void prvConfigureCaptureBehaviour( void ) -{ -struct bpf_program xFilterCode; -const long lMinBytesToCopy = 10L, lBlocking = 1L; -unsigned long ulNetMask; - - /* Unblock a read as soon as anything is received. */ - pcap_setmintocopy( pxOpenedInterfaceHandle, lMinBytesToCopy ); - - /* Allow blocking. */ - pcap_setnonblock( pxOpenedInterfaceHandle, lBlocking, cErrorBuffer ); - - /* Set up a filter so only the packets of interest are passed to the IP - stack. cErrorBuffer is used for convenience to create the string. Don't - confuse this with an error message. *//*_RB_ This should not use the #defined constants. *//*_RB_ Constants should not be used, but passed through a generic network API. */ - sprintf( cErrorBuffer, "broadcast or multicast or ether host %x:%x:%x:%x:%x:%x", configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 ); - - /*_RB_ Constants should not be used, but passed through a generic network API. */ - ulNetMask = ( configNET_MASK3 << 24UL ) | ( configNET_MASK2 << 16UL ) | ( configNET_MASK1 << 8L ) | configNET_MASK0; - - if( pcap_compile(pxOpenedInterfaceHandle, &xFilterCode, cErrorBuffer, 1, ulNetMask ) < 0 ) - { - printf("\r\nThe packet filter string is invalid\r\n" ); - } - else - { - if( pcap_setfilter( pxOpenedInterfaceHandle, &xFilterCode ) < 0 ) - { - printf( "\r\nAn error occurred setting the packet filter.\r\n" ); - } - } - - /* Create a task that simulates an interrupt in a real system. This will - block waiting for packets, then send a message to the uIP task when data - is available. */ - xTaskCreate( prvInterruptSimulatorTask, "MAC_ISR", configMINIMAL_STACK_SIZE, NULL, configMAC_ISR_SIMULATOR_PRIORITY, NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvInterruptSimulatorTask( void *pvParameters ) -{ -static struct pcap_pkthdr *pxHeader; -const uint8_t *pucPacketData; -long lResult; -xNetworkBufferDescriptor_t *pxNetworkBuffer; -xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL }; -eFrameProcessingResult_t eResult; - - /* Just to kill the compiler warning. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Get the next packet. */ - xSemaphoreTake( xPCAPMutex, portMAX_DELAY ); - { - lResult = pcap_next_ex( pxOpenedInterfaceHandle, &pxHeader, &pucPacketData ); - } - xSemaphoreGive( xPCAPMutex ); - - if( lResult == 1 ) - { - eResult = ipCONSIDER_FRAME_FOR_PROCESSING( pucPacketData ); - if( eResult == eProcessBuffer ) - { - /* Will the data fit into the frame buffer? */ - if( pxHeader->len <= ipTOTAL_ETHERNET_FRAME_SIZE ) - { - /* Obtain a buffer into which the data can be placed. This - is only an interrupt simulator, not a real interrupt, so it - is ok to call the task level function here. */ - xSemaphoreTake( xPCAPMutex, portMAX_DELAY ); - { - pxNetworkBuffer = pxNetworkBufferGet( pxHeader->len, 0 ); - } - xSemaphoreGive( xPCAPMutex ); - - if( pxNetworkBuffer != NULL ) - { - memcpy( pxNetworkBuffer->pucEthernetBuffer, pucPacketData, pxHeader->len ); - pxNetworkBuffer->xDataLength = ( size_t ) pxHeader->len; - xRxEvent.pvData = ( void * ) pxNetworkBuffer; - - /* Data was received and stored. Send a message to the IP - task to let it know. */ - if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( TickType_t ) 0 ) == pdFALSE ) - { - /* The buffer could not be sent to the stack so - must be released again. This is only an interrupt - simulator, not a real interrupt, so it is ok to use - the task level function here. */ - vNetworkBufferRelease( pxNetworkBuffer ); - iptraceETHERNET_RX_EVENT_LOST(); - } - else - { - iptraceNETWORK_INTERFACE_RECEIVE(); - } - } - else - { - iptraceETHERNET_RX_EVENT_LOST(); - } - } - else - { - /* Log that a packet was dropped because it would have - overflowed the buffer. */ - } - } - } - else - { - /* There is no real way of simulating an interrupt. Make sure - other tasks can run. */ - vTaskDelay( configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ); - } - } -} -/*-----------------------------------------------------------*/ - -#if configUSE_STATIC_BUFFERS == 1 - void vNetworkInterfaceAllocateRAMToBuffers( xNetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFERS ] ) - { - BaseType_t x; - xNetworkBufferDescriptor_t **ppxStartOfBuffer; - - for( x = 0; x < ipconfigNUM_NETWORK_BUFFERS; x++ ) - { - /* Place a pointer to the network buffer structure at the beginning - of the buffer that will be allocated to the structure. */ - ppxStartOfBuffer = ( xNetworkBufferDescriptor_t ** ) &( ucBuffers[ x ][ 0 ] ); - *ppxStartOfBuffer = &( pxNetworkBuffers[ x ] ); - - /* Allocate the buffer to the network buffer structure, jumping over - the bytes where the pointer to the network buffer is now stored. */ - pxNetworkBuffers[ x ].pucEthernetBuffer = &( ucBuffers[ x ][ ipBUFFER_PADDING ] ); - } - } -#endif -/*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/readme.txt b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/readme.txt index 193368659..24bb5461e 100644 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/readme.txt +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/readme.txt @@ -1,16 +1,4 @@ -Contains the files that implement FreeRTOS+UDP. - -User documentation, including an API reference is available on: -http://www.FreeRTOS.org/udp - -A description of the source code organisation is available on: -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_IP_Embedded_Ethernet_Tutorial.shtml - -The porting guide is available one: -http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_Porting.shtml - - -At this time it is recommended to use BufferAllocation_2.c in which case it is -essential to use the heap_4.c memory allocation scheme: -http://www.freertos.org/a00111.html - +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.atsln b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.atsln deleted file mode 100644 index 8de4446cc..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.atsln +++ /dev/null @@ -1,20 +0,0 @@ - -Microsoft Visual Studio Solution File, Format Version 11.00 -# Atmel Studio Solution File, Format Version 11.00 -Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "RTOSDemo", "RTOSDemo.cproj", "{257FE152-8D54-41CA-AFE7-777DE72FE329}" -EndProject -Global - GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|ARM = Debug|ARM - Release|ARM = Release|ARM - EndGlobalSection - GlobalSection(ProjectConfigurationPlatforms) = postSolution - {257FE152-8D54-41CA-AFE7-777DE72FE329}.Debug|ARM.ActiveCfg = Debug|ARM - {257FE152-8D54-41CA-AFE7-777DE72FE329}.Debug|ARM.Build.0 = Debug|ARM - {257FE152-8D54-41CA-AFE7-777DE72FE329}.Release|ARM.ActiveCfg = Release|ARM - {257FE152-8D54-41CA-AFE7-777DE72FE329}.Release|ARM.Build.0 = Release|ARM - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection -EndGlobal diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.atsuo b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.atsuo deleted file mode 100644 index c783a6382..000000000 Binary files a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.atsuo and /dev/null differ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj deleted file mode 100644 index 3a53b9e86..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj +++ /dev/null @@ -1,1184 +0,0 @@ - - - - 2.0 - 7.0 - {257fe152-8d54-41ca-afe7-777de72fe329} - $(MSBuildProjectName) - $(MSBuildProjectName) - $(MSBuildProjectName) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ATSAM4E16E - sam4e - C - com.Atmel.ARMGCC.C - - $(MSBuildProjectDirectory)\$(Configuration) - $(MSBuildProjectName) - .elf - Executable - Native - true - false - true - true - 0x20000000 - - exception_table - 2 - 1 - com.atmel.avrdbg.tool.samice - - - - false - 7020000 - - SWD - - com.atmel.avrdbg.tool.samice - 158000789 - J-Link - - SWD - true - - - - - True - True - True - True - True - - - ARM_MATH_CM4=true - BOARD=SAM4E_EK - __SAM4E16E__ - printf=iprintf - - - - - ../src - ../src/ASF/common/boards - ../src/ASF/common/services/clock - ../src/ASF/common/services/ioport - ../src/ASF/common/utils - ../src/ASF/sam/boards - ../src/ASF/sam/boards/sam4e_ek - ../src/ASF/sam/drivers/pmc - ../src/ASF/sam/utils - ../src/ASF/sam/utils/cmsis/sam4e/include - ../src/ASF/sam/utils/cmsis/sam4e/source/templates - ../src/ASF/sam/utils/fpu - ../src/ASF/sam/utils/header_files - ../src/ASF/sam/utils/preprocessor - ../src/ASF/thirdparty/CMSIS/Include - ../src/ASF/thirdparty/CMSIS/Lib/GCC - ../src/config - %24(ToolchainDir)\..\..\CMSIS_Atmel - %24(ToolchainDir)\..\..\CMSIS_Atmel\CMSIS\Include - %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL - %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include - ../src/ASF/sam/components/ethernet_phy/ksz8051mnl - ../src/ASF/sam/drivers/gmac - ../src/ASF/sam/components/display/aat31xx - ../src/ASF/sam/components/display/ili93xx - ../src/ASF/sam/drivers/ebi/smc - ../src/ASF/sam/drivers/tc - - - Optimize for size (-Os) - -fdata-sections - True - True - -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=vfpv4 - - - arm_cortexM4lf_math - m - - - - - ../src/ASF/thirdparty/CMSIS/Lib/GCC - - - True - -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/sam4e/sam4e16e/gcc/flash.ld - -DARM_MATH_CM4=true -DBOARD=SAM4E_EK -D__SAM4E16E__ -Dprintf=iprintf - - - ../src - ../src/ASF/common/boards - ../src/ASF/common/services/clock - ../src/ASF/common/services/ioport - ../src/ASF/common/utils - ../src/ASF/sam/boards - ../src/ASF/sam/boards/sam4e_ek - ../src/ASF/sam/drivers/pmc - ../src/ASF/sam/utils - ../src/ASF/sam/utils/cmsis/sam4e/include - ../src/ASF/sam/utils/cmsis/sam4e/source/templates - ../src/ASF/sam/utils/fpu - ../src/ASF/sam/utils/header_files - ../src/ASF/sam/utils/preprocessor - ../src/ASF/thirdparty/CMSIS/Include - ../src/ASF/thirdparty/CMSIS/Lib/GCC - ../src/config - %24(ToolchainDir)\..\..\CMSIS_Atmel - %24(ToolchainDir)\..\..\CMSIS_Atmel\CMSIS\Include - %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL - %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include - ../src/ASF/sam/components/ethernet_phy/ksz8051mnl - ../src/ASF/sam/drivers/gmac - ../src/ASF/sam/components/display/aat31xx - ../src/ASF/sam/components/display/ili93xx - ../src/ASF/sam/drivers/ebi/smc - ../src/ASF/sam/drivers/tc - - - - - True - True - True - True - - - - - True - True - True - True - True - - - ARM_MATH_CM4=true - BOARD=SAM4E_EK - __SAM4E16E__ - - - - - ../src - ../src/ASF/common/boards - ../src/ASF/common/services/clock - ../src/ASF/common/services/ioport - ../src/ASF/common/utils - ../src/ASF/sam/boards - ../src/ASF/sam/boards/sam4e_ek - ../src/ASF/sam/drivers/pmc - ../src/ASF/sam/utils - ../src/ASF/sam/utils/cmsis/sam4e/include - ../src/ASF/sam/utils/cmsis/sam4e/source/templates - ../src/ASF/sam/utils/fpu - ../src/ASF/sam/utils/header_files - ../src/ASF/sam/utils/preprocessor - ../src/ASF/thirdparty/CMSIS/Include - ../src/ASF/thirdparty/CMSIS/Lib/GCC - ../src/config - %24(ToolchainDir)\..\..\CMSIS_Atmel - %24(ToolchainDir)\..\..\CMSIS_Atmel\CMSIS\Include - %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL - %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include - ../../../../FreeRTOS/Source/portable/GCC/ARM_CM4F - ../../../../FreeRTOS/Source/include - ../../../../FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include - ../../../../FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC - ../../../../FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1 - ../src/ASF/sam/components/ethernet_phy/ksz8051mnl - ../src/ASF/sam/drivers/gmac - ../../../../FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI - ../../../../FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/api - ../../../../FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands - ../../Common/include - ../src/ASF/sam/components/display/aat31xx - ../src/ASF/sam/components/display/ili93xx - ../src/ASF/sam/drivers/ebi/smc - ../../../../FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients - ../src/ASF/sam/drivers/tc - - - Optimize (-O1) - -fdata-sections - True - Maximum (-g3) - True - True - -pipe -fno-strict-aliasing -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=vfpv4 -Wno-attributes -Wno-unused-function - - - m - - - - - ../src/ASF/thirdparty/CMSIS/Lib/GCC - - - True - - -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/sam4e/sam4e16e/gcc/flash.ld - Default (-g) - -DARM_MATH_CM4=true -DBOARD=SAM4E_EK -D__SAM4E16E__ -Dprintf=iprintf - - - ../src - ../src/ASF/common/boards - ../src/ASF/common/services/clock - ../src/ASF/common/services/ioport - ../src/ASF/common/utils - ../src/ASF/sam/boards - ../src/ASF/sam/boards/sam4e_ek - ../src/ASF/sam/drivers/pmc - ../src/ASF/sam/utils - ../src/ASF/sam/utils/cmsis/sam4e/include - ../src/ASF/sam/utils/cmsis/sam4e/source/templates - ../src/ASF/sam/utils/fpu - ../src/ASF/sam/utils/header_files - ../src/ASF/sam/utils/preprocessor - ../src/ASF/thirdparty/CMSIS/Include - ../src/ASF/thirdparty/CMSIS/Lib/GCC - ../src/config - %24(ToolchainDir)\..\..\CMSIS_Atmel - %24(ToolchainDir)\..\..\CMSIS_Atmel\CMSIS\Include - %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL - %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\sam4e\include - ../src/ASF/sam/components/ethernet_phy/ksz8051mnl - ../src/ASF/sam/drivers/gmac - ../src/ASF/sam/components/display/aat31xx - ../src/ASF/sam/components/display/ili93xx - ../src/ASF/sam/drivers/ebi/smc - ../src/ASF/sam/drivers/tc - - - Default (-Wa,-g) - - - True - True - True - True - - - - compile - src\File-Related-CLI-commands.c - - - compile - src\Sample-CLI-commands.c - - - compile - src\UDP-Related-CLI-commands.c - - - compile - src\File-system-demo.c - - - compile - src\UDPCommandServer.c - - - compile - src\TwoEchoClients.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\dir.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\drv.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\fat.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\file.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\f_lock.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\util.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\util_sfn.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\volume.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\Media Driver\ramdrv_f.c - - - compile - src\FreeRTOS+\FreeRTOS+FAT SL\PSP\Target\RTC\psp_rtc.c - - - compile - src\FreeRTOS\event_groups.c - - - compile - src\Common Demo Tasks\blocktim.c - - - compile - src\Common Demo Tasks\countsem.c - - - compile - src\Common Demo Tasks\dynamic.c - - - compile - src\Common Demo Tasks\EventGroupsDemo.c - - - compile - src\Common Demo Tasks\flash_timer.c - - - compile - src\Common Demo Tasks\GenQTest.c - - - compile - src\Common Demo Tasks\IntQueue.c - - - compile - src\Common Demo Tasks\IntSemTest.c - - - compile - src\Common Demo Tasks\QPeek.c - - - compile - src\Common Demo Tasks\QueueOverwrite.c - - - compile - src\Common Demo Tasks\QueueSet.c - - - compile - src\Common Demo Tasks\recmutex.c - - - compile - src\Common Demo Tasks\semtest.c - - - compile - src\Common Demo Tasks\TaskNotify.c - - - compile - src\Common Demo Tasks\TimerDemo.c - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - src\DemoIPTrace.c - - - compile - src\FreeRTOS+\FreeRTOS+CLI\FreeRTOS_CLI.c - - - compile - src\FreeRTOS+\FreeRTOS+UDP\FreeRTOS_DHCP.c - - - compile - src\FreeRTOS+\FreeRTOS+UDP\FreeRTOS_DNS.c - - - compile - src\FreeRTOS+\FreeRTOS+UDP\FreeRTOS_Sockets.c - - - compile - src\FreeRTOS+\FreeRTOS+UDP\FreeRTOS_UDP_IP.c - - - compile - src\FreeRTOS+\FreeRTOS+UDP\portable\NetworkBuffers\BufferAllocation_2.c - - - compile - src\FreeRTOS+\FreeRTOS+UDP\portable\NetWorkInterface\NetworkInterface.c - - - compile - src\FreeRTOS\list.c - - - compile - src\FreeRTOS\portable\port.c - - - compile - src\FreeRTOS\portable\heap_4.c - - - compile - src\FreeRTOS\queue.c - - - compile - src\FreeRTOS\tasks.c - - - compile - src\FreeRTOS\timers.c - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - compile - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/ReadMe.txt b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/ReadMe.txt new file mode 100644 index 000000000..24bb5461e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/ReadMe.txt @@ -0,0 +1,4 @@ +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/Read_Me_Instructions.url b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/Read_Me_Instructions.url deleted file mode 100644 index 86d28f180..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/Read_Me_Instructions.url +++ /dev/null @@ -1,5 +0,0 @@ -[InternetShortcut] -URL=http://www.freertos.org/Atmel_SAM4E_RTOS_Demo.html -IDList= -[{000214A0-0000-0000-C000-000000000046}] -Prop3=19,2 diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/See also FreeRTOS+TCP.url b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/See also FreeRTOS+TCP.url new file mode 100644 index 000000000..2da199cac --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/See also FreeRTOS+TCP.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/index.html +IDList= diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/jlink.config b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/jlink.config deleted file mode 100644 index de1b137f3..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/jlink.config +++ /dev/null @@ -1,34 +0,0 @@ -[BREAKPOINTS] -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="UNSPECIFIED" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/boards/board.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/boards/board.h deleted file mode 100644 index c355c03eb..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/boards/board.h +++ /dev/null @@ -1,347 +0,0 @@ -/** - * \file - * - * \brief Standard board header file. - * - * This file includes the appropriate board header file according to the - * defined board (parameter BOARD). - * - * Copyright (c) 2009-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/** - * \defgroup group_common_boards Generic board support - * - * The generic board support module includes board-specific definitions - * and function prototypes, such as the board initialization function. - * - * \{ - */ - -#include "compiler.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/*! \name Base Boards - */ -//! @{ -#define EVK1100 1 //!< AT32UC3A EVK1100 board. -#define EVK1101 2 //!< AT32UC3B EVK1101 board. -#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board. -#define EVK1104 4 //!< AT32UC3A3 EVK1104 board. -#define EVK1105 5 //!< AT32UC3A EVK1105 board. -#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board. -#define UC3L_EK 7 //!< AT32UC3L-EK board. -#define XPLAIN 8 //!< ATxmega128A1 Xplain board. -#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board. -#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board. -#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board. -#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board. -#define STK600_RCUC3D 16 //!< STK600 RCUC3D board. -#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board. -#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board. -#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board. -#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board -#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board -#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board -#define STK600_RC044X 24 //!< STK600 with RC044X routing card board. -#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board. -#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board. -#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board. -#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board. -#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board. -#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards -#define RZ600 31 //!< AT32UC3A RZ600 MCU board -#define SAM3S_EK 32 //!< SAM3S-EK board. -#define SAM3U_EK 33 //!< SAM3U-EK board. -#define SAM3X_EK 34 //!< SAM3X-EK board. -#define SAM3N_EK 35 //!< SAM3N-EK board. -#define SAM3S_EK2 36 //!< SAM3S-EK2 board. -#define SAM4S_EK 37 //!< SAM4S-EK board. -#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board. -#define STK600_MEGA 39 //!< STK600 MEGA board. -#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board. -#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board. -#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board. -#define ARDUINO_DUE_X 43 //!< Arduino Due/X board. -#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board -#define SAM4L_EK 45 //!< SAM4L-EK board. -#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board. -#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board. -#define STK600_RC032X 48 //!< STK600 with RC032X routing card board. -#define SAM4S_EK2 49 //!< SAM4S-EK2 board. -#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board. -#define SAM4E_EK 51 //!< SAM4E-EK board. -#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board. -#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board. -#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board. -#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit -#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 zigbit -#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B zigbit -#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board. -#define SAMD20_XPLAINED_PRO 59 //!< SAMD20 Xplained PRO board -#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board. -#define SAM4N_XPLAINED_PRO 61 //!< SAM4N-XPLAINED-PRO board. -#define XMEGA_A3_REB_CBB 62 //!< SAM4L8 Xplained Pro board. -#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB -#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices -#define AVR_SIMULATOR_UC3 98 //!< AVR SIMULATOR for AVR UC3 device family. -#define USER_BOARD 99 //!< User-reserved board (if any). -#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader) -//! @} - -/*! \name Extension Boards - */ -//! @{ -#define EXT1102 1 //!< AT32UC3B EXT1102 board -#define MC300 2 //!< AT32UC3 MC300 board -#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1 -#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2 -#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board -#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board -#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A" -#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600 -#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600 -#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600 -#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard -#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board -#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any). -//! @} - -#if BOARD == EVK1100 -# include "evk1100/evk1100.h" -#elif BOARD == EVK1101 -# include "evk1101/evk1101.h" -#elif BOARD == UC3C_EK -# include "uc3c_ek/uc3c_ek.h" -#elif BOARD == EVK1104 -# include "evk1104/evk1104.h" -#elif BOARD == EVK1105 -# include "evk1105/evk1105.h" -#elif BOARD == STK600_RCUC3L0 -# include "stk600/rcuc3l0/stk600_rcuc3l0.h" -#elif BOARD == UC3L_EK -# include "uc3l_ek/uc3l_ek.h" -#elif BOARD == STK600_RCUC3L4 -# include "stk600/rcuc3l4/stk600_rcuc3l4.h" -#elif BOARD == XPLAIN -# include "xplain/xplain.h" -#elif BOARD == STK600_MEGA - /*No header-file to include*/ -#elif BOARD == STK600_MEGA_RF -# include "stk600.h" -#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO -# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h" -#elif BOARD == ATMEGA256RFR2_ZIGBIT -# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h" -#elif BOARD == STK600_RC032X -# include "stk600/rc032x/stk600_rc032x.h" -#elif BOARD == STK600_RC044X -# include "stk600/rc044x/stk600_rc044x.h" -#elif BOARD == STK600_RC064X -# include "stk600/rc064x/stk600_rc064x.h" -#elif BOARD == STK600_RC100X -# include "stk600/rc100x/stk600_rc100x.h" -#elif BOARD == UC3_A3_XPLAINED -# include "uc3_a3_xplained/uc3_a3_xplained.h" -#elif BOARD == UC3_L0_XPLAINED -# include "uc3_l0_xplained/uc3_l0_xplained.h" -#elif BOARD == STK600_RCUC3B0 -# include "stk600/rcuc3b0/stk600_rcuc3b0.h" -#elif BOARD == STK600_RCUC3D -# include "stk600/rcuc3d/stk600_rcuc3d.h" -#elif BOARD == STK600_RCUC3C0 -# include "stk600/rcuc3c0/stk600_rcuc3c0.h" -#elif BOARD == XMEGA_B1_XPLAINED -# include "xmega_b1_xplained/xmega_b1_xplained.h" -#elif BOARD == STK600_RC064X_LCDX -# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h" -#elif BOARD == STK600_RC100X_LCDX -# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h" -#elif BOARD == XMEGA_A1_XPLAINED -# include "xmega_a1_xplained/xmega_a1_xplained.h" -#elif BOARD == UC3_L0_XPLAINED_BC -# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h" -#elif BOARD == SAM3S_EK -# include "sam3s_ek/sam3s_ek.h" -# include "system_sam3s.h" -#elif BOARD == SAM3S_EK2 -# include "sam3s_ek2/sam3s_ek2.h" -# include "system_sam3sd8.h" -#elif BOARD == SAM3U_EK -# include "sam3u_ek/sam3u_ek.h" -# include "system_sam3u.h" -#elif BOARD == SAM3X_EK -# include "sam3x_ek/sam3x_ek.h" -# include "system_sam3x.h" -#elif BOARD == SAM3N_EK -# include "sam3n_ek/sam3n_ek.h" -# include "system_sam3n.h" -#elif BOARD == SAM4S_EK -# include "sam4s_ek/sam4s_ek.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_WPIR_RD -# include "sam4s_wpir_rd/sam4s_wpir_rd.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_XPLAINED -# include "sam4s_xplained/sam4s_xplained.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_EK2 -# include "sam4s_ek2/sam4s_ek2.h" -# include "system_sam4s.h" -#elif BOARD == MEGA_1284P_XPLAINED - /*No header-file to include*/ -#elif BOARD == ARDUINO_DUE_X -# include "arduino_due_x/arduino_due_x.h" -# include "system_sam3x.h" -#elif BOARD == SAM4L_EK -# include "sam4l_ek/sam4l_ek.h" -#elif BOARD == SAM4E_EK -# include "sam4e_ek/sam4e_ek.h" -#elif BOARD == SAMD20_XPLAINED_PRO -# include "samd20_xplained_pro/samd20_xplained_pro.h" -#elif BOARD == SAM4N_XPLAINED_PRO -# include "sam4n_xplained_pro/sam4n_xplained_pro.h" -#elif BOARD == MEGA1284P_XPLAINED_BC -# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h" -#elif BOARD == UC3_L0_QT600 -# include "uc3_l0_qt600/uc3_l0_qt600.h" -#elif BOARD == XMEGA_A3BU_XPLAINED -# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h" -#elif BOARD == XMEGA_E5_XPLAINED -# include "xmega_e5_xplained/xmega_e5_xplained.h" -#elif BOARD == UC3B_BOARD_CONTROLLER -# include "uc3b_board_controller/uc3b_board_controller.h" -#elif BOARD == RZ600 -# include "rz600/rz600.h" -#elif BOARD == STK600_RCUC3A0 -# include "stk600/rcuc3a0/stk600_rcuc3a0.h" -#elif BOARD == ATXMEGA128A1_QT600 -# include "atxmega128a1_qt600/atxmega128a1_qt600.h" -#elif BOARD == STK600_RCUC3L3 -# include "stk600/rcuc3l3/stk600_rcuc3l3.h" -#elif BOARD == SAM4S_XPLAINED_PRO -# include "sam4s_xplained_pro/sam4s_xplained_pro.h" -#elif BOARD == SAM4L_XPLAINED_PRO -# include "sam4l_xplained_pro/sam4l_xplained_pro.h" -#elif BOARD == SAM4L8_XPLAINED_PRO -# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h" -#elif BOARD == SIMULATOR_XMEGA_A1 -# include "simulator/xmega_a1/simulator_xmega_a1.h" -#elif BOARD == XMEGA_C3_XPLAINED -# include "xmega_c3_xplained/xmega_c3_xplained.h" -#elif BOARD == XMEGA_RF233_ZIGBIT -# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h" -#elif BOARD == XMEGA_A3_REB_CBB -# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h" -#elif BOARD == ATMEGARFX_RCB -# include "atmegarfx_rcb/atmegarfx_rcb.h" -#elif BOARD == XMEGA_RF212B_ZIGBIT -# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h" -#elif BOARD == AVR_SIMULATOR_UC3 -# include "avr_simulator_uc3/avr_simulator_uc3.h" -#elif BOARD == USER_BOARD - // User-reserved area: #include the header file of your board here (if any). -# include "user_board.h" -#elif BOARD == DUMMY_BOARD -# include "dummy/dummy_board.h" -#else -# error No known Atmel board defined -#endif - -#if (defined EXT_BOARD) -# if EXT_BOARD == MC300 -# include "mc300/mc300.h" -# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \ - (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \ - (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD) -# include "sensors_xplained/sensors_xplained.h" -# elif EXT_BOARD == RZ600_AT86RF231 -# include "at86rf231/at86rf231.h" -# elif EXT_BOARD == RZ600_AT86RF230B -# include "at86rf230b/at86rf230b.h" -# elif EXT_BOARD == RZ600_AT86RF212 -# include "at86rf212/at86rf212.h" -# elif EXT_BOARD == SECURITY_XPLAINED -# include "security_xplained.h" -# elif EXT_BOARD == USER_EXT_BOARD - // User-reserved area: #include the header file of your extension board here - // (if any). -# endif -#endif - - -#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__)) -#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. - -/*! \brief This function initializes the board target resources - * - * This function should be called to ensure proper initialization of the target - * board hardware connected to the part. - */ -extern void board_init(void); - -#endif // #ifdef __AVR32_ABI_COMPILER__ -#else -/*! \brief This function initializes the board target resources - * - * This function should be called to ensure proper initialization of the target - * board hardware connected to the part. - */ -extern void board_init(void); -#endif - - -#ifdef __cplusplus -} -#endif - -/** - * \} - */ - -#endif // _BOARD_H_ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/genclk.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/genclk.h deleted file mode 100644 index 4de140d9e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/genclk.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - * \file - * - * \brief Generic clock management - * - * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef CLK_GENCLK_H_INCLUDED -#define CLK_GENCLK_H_INCLUDED - -#include "parts.h" - -#if SAM3S -# include "sam3s/genclk.h" -#elif SAM3U -# include "sam3u/genclk.h" -#elif SAM3N -# include "sam3n/genclk.h" -#elif SAM3XA -# include "sam3x/genclk.h" -#elif SAM4S -# include "sam4s/genclk.h" -#elif SAM4L -# include "sam4l/genclk.h" -#elif SAM4E -# include "sam4e/genclk.h" -#elif SAM4N -# include "sam4n/genclk.h" -#elif (UC3A0 || UC3A1) -# include "uc3a0_a1/genclk.h" -#elif UC3A3 -# include "uc3a3_a4/genclk.h" -#elif UC3B -# include "uc3b0_b1/genclk.h" -#elif UC3C -# include "uc3c/genclk.h" -#elif UC3D -# include "uc3d/genclk.h" -#elif UC3L -# include "uc3l/genclk.h" -#else -# error Unsupported chip type -#endif - -/** - * \ingroup clk_group - * \defgroup genclk_group Generic Clock Management - * - * Generic clocks are configurable clocks which run outside the system - * clock domain. They are often connected to peripherals which have an - * asynchronous component running independently of the bus clock, e.g. - * USB controllers, low-power timers and RTCs, etc. - * - * Note that not all platforms have support for generic clocks; on such - * platforms, this API will not be available. - * - * @{ - */ - -/** - * \def GENCLK_DIV_MAX - * \brief Maximum divider supported by the generic clock implementation - */ -/** - * \enum genclk_source - * \brief Generic clock source ID - * - * Each generic clock may be generated from a different clock source. - * These are the available alternatives provided by the chip. - */ - -//! \name Generic clock configuration -//@{ -/** - * \struct genclk_config - * \brief Hardware representation of a set of generic clock parameters - */ -/** - * \fn void genclk_config_defaults(struct genclk_config *cfg, - * unsigned int id) - * \brief Initialize \a cfg to the default configuration for the clock - * identified by \a id. - */ -/** - * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id) - * \brief Read the currently active configuration of the clock - * identified by \a id into \a cfg. - */ -/** - * \fn void genclk_config_write(const struct genclk_config *cfg, - * unsigned int id) - * \brief Activate the configuration \a cfg on the clock identified by - * \a id. - */ -/** - * \fn void genclk_config_set_source(struct genclk_config *cfg, - * enum genclk_source src) - * \brief Select a new source clock \a src in configuration \a cfg. - */ -/** - * \fn void genclk_config_set_divider(struct genclk_config *cfg, - * unsigned int divider) - * \brief Set a new \a divider in configuration \a cfg. - */ -/** - * \fn void genclk_enable_source(enum genclk_source src) - * \brief Enable the source clock \a src used by a generic clock. - */ - //@} - -//! \name Enabling and disabling Generic Clocks -//@{ -/** - * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id) - * \brief Activate the configuration \a cfg on the clock identified by - * \a id and enable it. - */ -/** - * \fn void genclk_disable(unsigned int id) - * \brief Disable the generic clock identified by \a id. - */ -//@} - -/** - * \brief Enable the configuration defined by \a src and \a divider - * for the generic clock identified by \a id. - * - * \param id The ID of the generic clock. - * \param src The source clock of the generic clock. - * \param divider The divider used to generate the generic clock. - */ -static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider) -{ - struct genclk_config gcfg; - - genclk_config_defaults(&gcfg, id); - genclk_enable_source(src); - genclk_config_set_source(&gcfg, src); - genclk_config_set_divider(&gcfg, divider); - genclk_enable(&gcfg, id); -} - -//! @} - -#endif /* CLK_GENCLK_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/osc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/osc.h deleted file mode 100644 index a21c7eb6e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/osc.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - * \file - * - * \brief Oscillator management - * - * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef OSC_H_INCLUDED -#define OSC_H_INCLUDED - -#include "parts.h" -#include "conf_clock.h" - -#if SAM3S -# include "sam3s/osc.h" -#elif SAM3XA -# include "sam3x/osc.h" -#elif SAM3U -# include "sam3u/osc.h" -#elif SAM3N -# include "sam3n/osc.h" -#elif SAM4S -# include "sam4s/osc.h" -#elif SAM4E -# include "sam4e/osc.h" -#elif SAM4L -# include "sam4l/osc.h" -#elif SAM4N -# include "sam4n/osc.h" -#elif (UC3A0 || UC3A1) -# include "uc3a0_a1/osc.h" -#elif UC3A3 -# include "uc3a3_a4/osc.h" -#elif UC3B -# include "uc3b0_b1/osc.h" -#elif UC3C -# include "uc3c/osc.h" -#elif UC3D -# include "uc3d/osc.h" -#elif UC3L -# include "uc3l/osc.h" -#elif XMEGA -# include "xmega/osc.h" -#else -# error Unsupported chip type -#endif - -/** - * \ingroup clk_group - * \defgroup osc_group Oscillator Management - * - * This group contains functions and definitions related to configuring - * and enabling/disabling on-chip oscillators. Internal RC-oscillators, - * external crystal oscillators and external clock generators are - * supported by this module. What all of these have in common is that - * they swing at a fixed, nominal frequency which is normally not - * adjustable. - * - * \par Example: Enabling an oscillator - * - * The following example demonstrates how to enable the external - * oscillator on XMEGA A and wait for it to be ready to use. The - * oscillator identifiers are platform-specific, so while the same - * procedure is used on all platforms, the parameter to osc_enable() - * will be different from device to device. - * \code - osc_enable(OSC_ID_XOSC); - osc_wait_ready(OSC_ID_XOSC); \endcode - * - * \section osc_group_board Board-specific Definitions - * If external oscillators are used, the board code must provide the - * following definitions for each of those: - * - \b BOARD__HZ: The nominal frequency of the oscillator. - * - \b BOARD__STARTUP_US: The startup time of the - * oscillator in microseconds. - * - \b BOARD__TYPE: The type of oscillator connected, i.e. - * whether it's a crystal or external clock, and sometimes what kind - * of crystal it is. The meaning of this value is platform-specific. - * - * @{ - */ - -//! \name Oscillator Management -//@{ -/** - * \fn void osc_enable(uint8_t id) - * \brief Enable oscillator \a id - * - * The startup time and mode value is automatically determined based on - * definitions in the board code. - */ -/** - * \fn void osc_disable(uint8_t id) - * \brief Disable oscillator \a id - */ -/** - * \fn osc_is_ready(uint8_t id) - * \brief Determine whether oscillator \a id is ready. - * \retval true Oscillator \a id is running and ready to use as a clock - * source. - * \retval false Oscillator \a id is not running. - */ -/** - * \fn uint32_t osc_get_rate(uint8_t id) - * \brief Return the frequency of oscillator \a id in Hz - */ - -#ifndef __ASSEMBLY__ - -/** - * \brief Wait until the oscillator identified by \a id is ready - * - * This function will busy-wait for the oscillator identified by \a id - * to become stable and ready to use as a clock source. - * - * \param id A number identifying the oscillator to wait for. - */ -static inline void osc_wait_ready(uint8_t id) -{ - while (!osc_is_ready(id)) { - /* Do nothing */ - } -} - -#endif /* __ASSEMBLY__ */ - -//@} - -//! @} - -#endif /* OSC_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/pll.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/pll.h deleted file mode 100644 index 82bcd2468..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/pll.h +++ /dev/null @@ -1,322 +0,0 @@ -/** - * \file - * - * \brief PLL management - * - * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef CLK_PLL_H_INCLUDED -#define CLK_PLL_H_INCLUDED - -#include "parts.h" -#include "conf_clock.h" - -#if SAM3S -# include "sam3s/pll.h" -#elif SAM3XA -# include "sam3x/pll.h" -#elif SAM3U -# include "sam3u/pll.h" -#elif SAM3N -# include "sam3n/pll.h" -#elif SAM4S -# include "sam4s/pll.h" -#elif SAM4E -# include "sam4e/pll.h" -#elif SAM4L -# include "sam4l/pll.h" -#elif SAM4N -# include "sam4n/pll.h" -#elif (UC3A0 || UC3A1) -# include "uc3a0_a1/pll.h" -#elif UC3A3 -# include "uc3a3_a4/pll.h" -#elif UC3B -# include "uc3b0_b1/pll.h" -#elif UC3C -# include "uc3c/pll.h" -#elif UC3D -# include "uc3d/pll.h" -#elif (UC3L0128 || UC3L0256 || UC3L3_L4) -# include "uc3l/pll.h" -#elif XMEGA -# include "xmega/pll.h" -#else -# error Unsupported chip type -#endif - -/** - * \ingroup clk_group - * \defgroup pll_group PLL Management - * - * This group contains functions and definitions related to configuring - * and enabling/disabling on-chip PLLs. A PLL will take an input signal - * (the \em source), optionally divide the frequency by a configurable - * \em divider, and then multiply the frequency by a configurable \em - * multiplier. - * - * Some devices don't support input dividers; specifying any other - * divisor than 1 on these devices will result in an assertion failure. - * Other devices may have various restrictions to the frequency range of - * the input and output signals. - * - * \par Example: Setting up PLL0 with default parameters - * - * The following example shows how to configure and enable PLL0 using - * the default parameters specified using the configuration symbols - * listed above. - * \code - pll_enable_config_defaults(0); \endcode - * - * To configure, enable PLL0 using the default parameters and to disable - * a specific feature like Wide Bandwidth Mode (a UC3A3-specific - * PLL option.), you can use this initialization process. - * \code - struct pll_config pllcfg; - if (pll_is_locked(pll_id)) { - return; // Pll already running - } - pll_enable_source(CONFIG_PLL0_SOURCE); - pll_config_defaults(&pllcfg, 0); - pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE); - pll_enable(&pllcfg, 0); - pll_wait_for_lock(0); \endcode - * - * When the last function call returns, PLL0 is ready to be used as the - * main system clock source. - * - * \section pll_group_config Configuration Symbols - * - * Each PLL has a set of default parameters determined by the following - * configuration symbols in the application's configuration file: - * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the - * input of PLL \a n. Must be one of the values defined by the - * #pll_source enum. - * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL - * \a n. - * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n. - * - * These configuration symbols determine the result of calling - * pll_config_defaults() and pll_get_default_rate(). - * - * @{ - */ - -//! \name Chip-specific PLL characteristics -//@{ -/** - * \def PLL_MAX_STARTUP_CYCLES - * \brief Maximum PLL startup time in number of slow clock cycles - */ -/** - * \def NR_PLLS - * \brief Number of on-chip PLLs - */ - -/** - * \def PLL_MIN_HZ - * \brief Minimum frequency that the PLL can generate - */ -/** - * \def PLL_MAX_HZ - * \brief Maximum frequency that the PLL can generate - */ -/** - * \def PLL_NR_OPTIONS - * \brief Number of PLL option bits - */ -//@} - -/** - * \enum pll_source - * \brief PLL clock source - */ - -//! \name PLL configuration -//@{ - -/** - * \struct pll_config - * \brief Hardware-specific representation of PLL configuration. - * - * This structure contains one or more device-specific values - * representing the current PLL configuration. The contents of this - * structure is typically different from platform to platform, and the - * user should not access any fields except through the PLL - * configuration API. - */ - -/** - * \fn void pll_config_init(struct pll_config *cfg, - * enum pll_source src, unsigned int div, unsigned int mul) - * \brief Initialize PLL configuration from standard parameters. - * - * \note This function may be defined inline because it is assumed to be - * called very few times, and usually with constant parameters. Inlining - * it will in such cases reduce the code size significantly. - * - * \param cfg The PLL configuration to be initialized. - * \param src The oscillator to be used as input to the PLL. - * \param div PLL input divider. - * \param mul PLL loop divider (i.e. multiplier). - * - * \return A configuration which will make the PLL run at - * (\a mul / \a div) times the frequency of \a src - */ -/** - * \def pll_config_defaults(cfg, pll_id) - * \brief Initialize PLL configuration using default parameters. - * - * After this function returns, \a cfg will contain a configuration - * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) - * times the frequency of CONFIG_PLLx_SOURCE. - * - * \param cfg The PLL configuration to be initialized. - * \param pll_id Use defaults for this PLL. - */ -/** - * \def pll_get_default_rate(pll_id) - * \brief Get the default rate in Hz of \a pll_id - */ -/** - * \fn void pll_config_set_option(struct pll_config *cfg, - * unsigned int option) - * \brief Set the PLL option bit \a option in the configuration \a cfg. - * - * \param cfg The PLL configuration to be changed. - * \param option The PLL option bit to be set. - */ -/** - * \fn void pll_config_clear_option(struct pll_config *cfg, - * unsigned int option) - * \brief Clear the PLL option bit \a option in the configuration \a cfg. - * - * \param cfg The PLL configuration to be changed. - * \param option The PLL option bit to be cleared. - */ -/** - * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id) - * \brief Read the currently active configuration of \a pll_id. - * - * \param cfg The configuration object into which to store the currently - * active configuration. - * \param pll_id The ID of the PLL to be accessed. - */ -/** - * \fn void pll_config_write(const struct pll_config *cfg, - * unsigned int pll_id) - * \brief Activate the configuration \a cfg on \a pll_id - * - * \param cfg The configuration object representing the PLL - * configuration to be activated. - * \param pll_id The ID of the PLL to be updated. - */ - -//@} - -//! \name Interaction with the PLL hardware -//@{ -/** - * \fn void pll_enable(const struct pll_config *cfg, - * unsigned int pll_id) - * \brief Activate the configuration \a cfg and enable PLL \a pll_id. - * - * \param cfg The PLL configuration to be activated. - * \param pll_id The ID of the PLL to be enabled. - */ -/** - * \fn void pll_disable(unsigned int pll_id) - * \brief Disable the PLL identified by \a pll_id. - * - * After this function is called, the PLL identified by \a pll_id will - * be disabled. The PLL configuration stored in hardware may be affected - * by this, so if the caller needs to restore the same configuration - * later, it should either do a pll_config_read() before disabling the - * PLL, or remember the last configuration written to the PLL. - * - * \param pll_id The ID of the PLL to be disabled. - */ -/** - * \fn bool pll_is_locked(unsigned int pll_id) - * \brief Determine whether the PLL is locked or not. - * - * \param pll_id The ID of the PLL to check. - * - * \retval true The PLL is locked and ready to use as a clock source - * \retval false The PLL is not yet locked, or has not been enabled. - */ -/** - * \fn void pll_enable_source(enum pll_source src) - * \brief Enable the source of the pll. - * The source is enabled, if the source is not already running. - * - * \param src The ID of the PLL source to enable. - */ -/** - * \fn void pll_enable_config_defaults(unsigned int pll_id) - * \brief Enable the pll with the default configuration. - * PLL is enabled, if the PLL is not already locked. - * - * \param pll_id The ID of the PLL to enable. - */ - -/** - * \brief Wait for PLL \a pll_id to become locked - * - * \todo Use a timeout to avoid waiting forever and hanging the system - * - * \param pll_id The ID of the PLL to wait for. - * - * \retval STATUS_OK The PLL is now locked. - * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. - */ -static inline int pll_wait_for_lock(unsigned int pll_id) -{ - Assert(pll_id < NR_PLLS); - - while (!pll_is_locked(pll_id)) { - /* Do nothing */ - } - - return 0; -} - -//@} -//! @} - -#endif /* CLK_PLL_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/genclk.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/genclk.h deleted file mode 100644 index f9dc6d061..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/genclk.h +++ /dev/null @@ -1,266 +0,0 @@ -/** - * \file - * - * \brief Chip-specific generic clock management. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CHIP_GENCLK_H_INCLUDED -#define CHIP_GENCLK_H_INCLUDED - -#include -#include - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \weakgroup genclk_group - * @{ - */ - -//! \name Programmable Clock Identifiers (PCK) -//@{ -#define GENCLK_PCK_0 0 //!< PCK0 ID -#define GENCLK_PCK_1 1 //!< PCK1 ID -#define GENCLK_PCK_2 2 //!< PCK2 ID -//@} - -//! \name Programmable Clock Sources (PCK) -//@{ - -enum genclk_source { - GENCLK_PCK_SRC_SLCK_RC = 0,//!< Internal 32kHz RC oscillator as PCK source clock - GENCLK_PCK_SRC_SLCK_XTAL = 1,//!< External 32kHz crystal oscillator as PCK source clock - GENCLK_PCK_SRC_SLCK_BYPASS = 2,//!< External 32kHz bypass oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_4M_RC = 3,//!< Internal 4MHz RC oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_8M_RC = 4,//!< Internal 8MHz RC oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_12M_RC = 5,//!< Internal 12MHz RC oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_XTAL = 6,//!< External crystal oscillator as PCK source clock - GENCLK_PCK_SRC_MAINCK_BYPASS = 7,//!< External bypass oscillator as PCK source clock - GENCLK_PCK_SRC_PLLACK = 8,//!< Use PLLACK as PCK source clock - GENCLK_PCK_SRC_MCK = 9,//!< Use Master Clk as PCK source clock -}; - -//@} - -//! \name Programmable Clock Prescalers (PCK) -//@{ - -enum genclk_divider { - GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1 - GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2 - GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4 - GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8 - GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16 - GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32 - GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64 -}; - -//@} - -struct genclk_config { - uint32_t ctrl; -}; - -static inline void genclk_config_defaults(struct genclk_config *p_cfg, - uint32_t ul_id) -{ - ul_id = ul_id; - p_cfg->ctrl = 0; -} - -static inline void genclk_config_read(struct genclk_config *p_cfg, - uint32_t ul_id) -{ - p_cfg->ctrl = PMC->PMC_PCK[ul_id]; -} - -static inline void genclk_config_write(const struct genclk_config *p_cfg, - uint32_t ul_id) -{ - PMC->PMC_PCK[ul_id] = p_cfg->ctrl; -} - -//! \name Programmable Clock Source and Prescaler configuration -//@{ - -static inline void genclk_config_set_source(struct genclk_config *p_cfg, - enum genclk_source e_src) -{ - p_cfg->ctrl &= (~PMC_PCK_CSS_Msk); - - switch (e_src) { - case GENCLK_PCK_SRC_SLCK_RC: - case GENCLK_PCK_SRC_SLCK_XTAL: - case GENCLK_PCK_SRC_SLCK_BYPASS: - p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK); - break; - - case GENCLK_PCK_SRC_MAINCK_4M_RC: - case GENCLK_PCK_SRC_MAINCK_8M_RC: - case GENCLK_PCK_SRC_MAINCK_12M_RC: - case GENCLK_PCK_SRC_MAINCK_XTAL: - case GENCLK_PCK_SRC_MAINCK_BYPASS: - p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK); - break; - - case GENCLK_PCK_SRC_PLLACK: - p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK); - break; - - case GENCLK_PCK_SRC_MCK: - p_cfg->ctrl |= (PMC_PCK_CSS_MCK); - break; - - default: - break; - } -} - -static inline void genclk_config_set_divider(struct genclk_config *p_cfg, - uint32_t e_divider) -{ - p_cfg->ctrl &= ~PMC_PCK_PRES_Msk; - p_cfg->ctrl |= e_divider; -} - -//@} - -static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id) -{ - PMC->PMC_PCK[ul_id] = p_cfg->ctrl; - pmc_enable_pck(ul_id); -} - -static inline void genclk_disable(uint32_t ul_id) -{ - pmc_disable_pck(ul_id); -} - -static inline void genclk_enable_source(enum genclk_source e_src) -{ - switch (e_src) { - case GENCLK_PCK_SRC_SLCK_RC: - if (!osc_is_ready(OSC_SLCK_32K_RC)) { - osc_enable(OSC_SLCK_32K_RC); - osc_wait_ready(OSC_SLCK_32K_RC); - } - break; - - case GENCLK_PCK_SRC_SLCK_XTAL: - if (!osc_is_ready(OSC_SLCK_32K_XTAL)) { - osc_enable(OSC_SLCK_32K_XTAL); - osc_wait_ready(OSC_SLCK_32K_XTAL); - } - break; - - case GENCLK_PCK_SRC_SLCK_BYPASS: - if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) { - osc_enable(OSC_SLCK_32K_BYPASS); - osc_wait_ready(OSC_SLCK_32K_BYPASS); - } - break; - - case GENCLK_PCK_SRC_MAINCK_4M_RC: - if (!osc_is_ready(OSC_MAINCK_4M_RC)) { - osc_enable(OSC_MAINCK_4M_RC); - osc_wait_ready(OSC_MAINCK_4M_RC); - } - break; - - case GENCLK_PCK_SRC_MAINCK_8M_RC: - if (!osc_is_ready(OSC_MAINCK_8M_RC)) { - osc_enable(OSC_MAINCK_8M_RC); - osc_wait_ready(OSC_MAINCK_8M_RC); - } - break; - - case GENCLK_PCK_SRC_MAINCK_12M_RC: - if (!osc_is_ready(OSC_MAINCK_12M_RC)) { - osc_enable(OSC_MAINCK_12M_RC); - osc_wait_ready(OSC_MAINCK_12M_RC); - } - break; - - case GENCLK_PCK_SRC_MAINCK_XTAL: - if (!osc_is_ready(OSC_MAINCK_XTAL)) { - osc_enable(OSC_MAINCK_XTAL); - osc_wait_ready(OSC_MAINCK_XTAL); - } - break; - - case GENCLK_PCK_SRC_MAINCK_BYPASS: - if (!osc_is_ready(OSC_MAINCK_BYPASS)) { - osc_enable(OSC_MAINCK_BYPASS); - osc_wait_ready(OSC_MAINCK_BYPASS); - } - break; - -#ifdef CONFIG_PLL0_SOURCE - case GENCLK_PCK_SRC_PLLACK: - pll_enable_config_defaults(0); - break; -#endif - - case GENCLK_PCK_SRC_MCK: - break; - - default: - Assert(false); - break; - } -} - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CHIP_GENCLK_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/osc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/osc.h deleted file mode 100644 index 69f1de181..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/osc.h +++ /dev/null @@ -1,223 +0,0 @@ -/** - * \file - * - * \brief Chip-specific oscillator management functions. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CHIP_OSC_H_INCLUDED -#define CHIP_OSC_H_INCLUDED - -#include "board.h" -#include "pmc.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \weakgroup osc_group - * @{ - */ - -//! \name Oscillator identifiers -//@{ -#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator. -#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator. -#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator. -#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator. -#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator. -#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator. -#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator. -#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator. -//@} - -//! \name Oscillator clock speed in hertz -//@{ -#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator. -#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator. -#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator. -#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator. -#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator. -#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator. -#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator. -#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator. -//@} - -static inline void osc_enable(uint32_t ul_id) -{ - switch (ul_id) { - case OSC_SLCK_32K_RC: - break; - - case OSC_SLCK_32K_XTAL: - pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); - break; - - case OSC_SLCK_32K_BYPASS: - pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS); - break; - - - case OSC_MAINCK_4M_RC: - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); - break; - - case OSC_MAINCK_8M_RC: - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); - break; - - case OSC_MAINCK_12M_RC: - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); - break; - - - case OSC_MAINCK_XTAL: - pmc_switch_mainck_to_xtal(PMC_OSC_XTAL, - pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, - OSC_SLCK_32K_RC_HZ)); - break; - - case OSC_MAINCK_BYPASS: - pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS, - pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, - OSC_SLCK_32K_RC_HZ)); - break; - } -} - -static inline void osc_disable(uint32_t ul_id) -{ - switch (ul_id) { - case OSC_SLCK_32K_RC: - case OSC_SLCK_32K_XTAL: - case OSC_SLCK_32K_BYPASS: - break; - - case OSC_MAINCK_4M_RC: - case OSC_MAINCK_8M_RC: - case OSC_MAINCK_12M_RC: - pmc_osc_disable_fastrc(); - break; - - case OSC_MAINCK_XTAL: - pmc_osc_disable_xtal(PMC_OSC_XTAL); - break; - - case OSC_MAINCK_BYPASS: - pmc_osc_disable_xtal(PMC_OSC_BYPASS); - break; - } -} - -static inline bool osc_is_ready(uint32_t ul_id) -{ - switch (ul_id) { - case OSC_SLCK_32K_RC: - return 1; - - case OSC_SLCK_32K_XTAL: - case OSC_SLCK_32K_BYPASS: - return pmc_osc_is_ready_32kxtal(); - - case OSC_MAINCK_4M_RC: - case OSC_MAINCK_8M_RC: - case OSC_MAINCK_12M_RC: - case OSC_MAINCK_XTAL: - case OSC_MAINCK_BYPASS: - return pmc_osc_is_ready_mainck(); - } - - return 0; -} - -static inline uint32_t osc_get_rate(uint32_t ul_id) -{ - switch (ul_id) { - case OSC_SLCK_32K_RC: - return OSC_SLCK_32K_RC_HZ; - -#ifdef BOARD_FREQ_SLCK_XTAL - case OSC_SLCK_32K_XTAL: - return BOARD_FREQ_SLCK_XTAL; -#endif - -#ifdef BOARD_FREQ_SLCK_BYPASS - case OSC_SLCK_32K_BYPASS: - return BOARD_FREQ_SLCK_BYPASS; -#endif - - case OSC_MAINCK_4M_RC: - return OSC_MAINCK_4M_RC_HZ; - - case OSC_MAINCK_8M_RC: - return OSC_MAINCK_8M_RC_HZ; - - case OSC_MAINCK_12M_RC: - return OSC_MAINCK_12M_RC_HZ; - -#ifdef BOARD_FREQ_MAINCK_XTAL - case OSC_MAINCK_XTAL: - return BOARD_FREQ_MAINCK_XTAL; -#endif - -#ifdef BOARD_FREQ_MAINCK_BYPASS - case OSC_MAINCK_BYPASS: - return BOARD_FREQ_MAINCK_BYPASS; -#endif - } - - return 0; -} - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CHIP_OSC_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/pll.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/pll.h deleted file mode 100644 index 5570e9dc3..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/pll.h +++ /dev/null @@ -1,225 +0,0 @@ -/** - * \file - * - * \brief Chip-specific PLL definitions. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CHIP_PLL_H_INCLUDED -#define CHIP_PLL_H_INCLUDED - -#include - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \weakgroup pll_group - * @{ - */ - -#define PLL_OUTPUT_MIN_HZ 80000000 -#define PLL_OUTPUT_MAX_HZ 240000000 - -#define PLL_INPUT_MIN_HZ 3000000 -#define PLL_INPUT_MAX_HZ 32000000 - -#define NR_PLLS 1 -#define PLLA_ID 0 - -#define PLL_COUNT 0x3fU - -enum pll_source { - PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator. - PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator. - PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator. - PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator. - PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator. - PLL_NR_SOURCES, //!< Number of PLL sources. -}; - -struct pll_config { - uint32_t ctrl; -}; - -#define pll_get_default_rate(pll_id) \ - ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \ - * CONFIG_PLL##pll_id##_MUL) \ - / CONFIG_PLL##pll_id##_DIV) - -/** - * \note The SAM4E PLL hardware interprets mul as mul+1. For readability the - * hardware mul+1 is hidden in this implementation. Use mul as mul effective - * value. - */ -static inline void pll_config_init(struct pll_config *p_cfg, - enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul) -{ - uint32_t vco_hz; - - Assert(e_src < PLL_NR_SOURCES); - - /* Calculate internal VCO frequency */ - vco_hz = osc_get_rate(e_src) / ul_div; - Assert(vco_hz >= PLL_INPUT_MIN_HZ); - Assert(vco_hz <= PLL_INPUT_MAX_HZ); - - vco_hz *= ul_mul; - Assert(vco_hz >= PLL_OUTPUT_MIN_HZ); - Assert(vco_hz <= PLL_OUTPUT_MAX_HZ); - - /* PMC hardware will automatically make it mul+1 */ - p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) | \ - CKGR_PLLAR_PLLACOUNT(PLL_COUNT); -} - -#define pll_config_defaults(cfg, pll_id) \ - pll_config_init(cfg, \ - CONFIG_PLL##pll_id##_SOURCE, \ - CONFIG_PLL##pll_id##_DIV, \ - CONFIG_PLL##pll_id##_MUL) - -static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - p_cfg->ctrl = PMC->CKGR_PLLAR; - } -} - -static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - pmc_disable_pllack(); // Always stop PLL first! - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; - } -} - -static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - pmc_disable_pllack(); // Always stop PLL first! - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; - } -} - -/** - * \note This will only disable the selected PLL, not the underlying oscillator (mainck). - */ -static inline void pll_disable(uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - if (ul_pll_id == PLLA_ID) { - pmc_disable_pllack(); - } -} - -static inline uint32_t pll_is_locked(uint32_t ul_pll_id) -{ - Assert(ul_pll_id < NR_PLLS); - - UNUSED(ul_pll_id); - return pmc_is_locked_pllack(); -} - -static inline void pll_enable_source(enum pll_source e_src) -{ - switch (e_src) { - case PLL_SRC_MAINCK_4M_RC: - case PLL_SRC_MAINCK_8M_RC: - case PLL_SRC_MAINCK_12M_RC: - case PLL_SRC_MAINCK_XTAL: - case PLL_SRC_MAINCK_BYPASS: - osc_enable(e_src); - osc_wait_ready(e_src); - break; - - default: - Assert(false); - break; - } -} - -static inline void pll_enable_config_defaults(unsigned int ul_pll_id) -{ - struct pll_config pllcfg; - - if (pll_is_locked(ul_pll_id)) { - return; // Pll already running - } - switch (ul_pll_id) { -#ifdef CONFIG_PLL0_SOURCE - case 0: - pll_enable_source(CONFIG_PLL0_SOURCE); - pll_config_init(&pllcfg, - CONFIG_PLL0_SOURCE, - CONFIG_PLL0_DIV, - CONFIG_PLL0_MUL); - break; -#endif - default: - Assert(false); - break; - } - pll_enable(&pllcfg, ul_pll_id); - while (!pll_is_locked(ul_pll_id)); -} - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CHIP_PLL_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/sysclk.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/sysclk.c deleted file mode 100644 index 66288d833..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/sysclk.c +++ /dev/null @@ -1,234 +0,0 @@ -/** - * \file - * - * \brief Chip-specific system clock management functions. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \weakgroup sysclk_group - * @{ - */ - -#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) -/** - * \brief boolean signalling that the sysclk_init is done. - */ -uint32_t sysclk_initialized = 0; -#endif - -/** - * \brief Set system clock prescaler configuration - * - * This function will change the system clock prescaler configuration to - * match the parameters. - * - * \note The parameters to this function are device-specific. - * - * \param ul_pres The CPU clock will be divided by \f$2^{mck\_pres}\f$ - */ -void sysclk_set_prescalers(uint32_t ul_pres) -{ - pmc_mck_set_prescaler(ul_pres); - SystemCoreClockUpdate(); -} - -/** - * \brief Change the source of the main system clock. - * - * \param ul_src The new system clock source. Must be one of the constants - * from the System Clock Sources section. - */ -void sysclk_set_source(uint32_t ul_src) -{ - switch (ul_src) { - case SYSCLK_SRC_SLCK_RC: - case SYSCLK_SRC_SLCK_XTAL: - case SYSCLK_SRC_SLCK_BYPASS: - pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK); - break; - - case SYSCLK_SRC_MAINCK_4M_RC: - case SYSCLK_SRC_MAINCK_8M_RC: - case SYSCLK_SRC_MAINCK_12M_RC: - case SYSCLK_SRC_MAINCK_XTAL: - case SYSCLK_SRC_MAINCK_BYPASS: - pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK); - break; - - case SYSCLK_SRC_PLLACK: - pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK); - break; - } - - SystemCoreClockUpdate(); -} - -#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__) -/** - * \brief Enable USB clock. - * - * \note The SAM3S UDP hardware interprets div as div+1. For readability the hardware div+1 - * is hidden in this implementation. Use div as div effective value. - * - * \param pll_id Source of the USB clock. - * \param div Actual clock divisor. Must be superior to 0. - */ -void sysclk_enable_usb(void) -{ - Assert(CONFIG_USBCLK_DIV > 0); - -#ifdef CONFIG_PLL0_SOURCE - if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) { - struct pll_config pllcfg; - - pll_enable_source(CONFIG_PLL0_SOURCE); - pll_config_defaults(&pllcfg, 0); - pll_enable(&pllcfg, 0); - pll_wait_for_lock(0); - pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1); - pmc_enable_udpck(); - return; - } -#endif -} - -/** - * \brief Disable the USB clock. - * - * \note This implementation does not switch off the PLL, it just turns off the USB clock. - */ -void sysclk_disable_usb(void) -{ - pmc_disable_udpck(); -} -#endif // CONFIG_USBCLK_SOURCE - -void sysclk_init(void) -{ - /* Set a flash wait state depending on the new cpu frequency */ - system_init_flash(sysclk_get_cpu_hz()); - - /* Config system clock setting */ - if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { - osc_enable(OSC_SLCK_32K_RC); - osc_wait_ready(OSC_SLCK_32K_RC); - pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { - osc_enable(OSC_SLCK_32K_XTAL); - osc_wait_ready(OSC_SLCK_32K_XTAL); - pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { - osc_enable(OSC_SLCK_32K_BYPASS); - osc_wait_ready(OSC_SLCK_32K_BYPASS); - pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { - /* Already running from SYSCLK_SRC_MAINCK_4M_RC */ - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { - osc_enable(OSC_MAINCK_8M_RC); - osc_wait_ready(OSC_MAINCK_8M_RC); - pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { - osc_enable(OSC_MAINCK_12M_RC); - osc_wait_ready(OSC_MAINCK_12M_RC); - pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { - osc_enable(OSC_MAINCK_XTAL); - osc_wait_ready(OSC_MAINCK_XTAL); - pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); - } - - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { - osc_enable(OSC_MAINCK_BYPASS); - osc_wait_ready(OSC_MAINCK_BYPASS); - pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); - } - -#ifdef CONFIG_PLL0_SOURCE - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { - struct pll_config pllcfg; - - pll_enable_source(CONFIG_PLL0_SOURCE); - pll_config_defaults(&pllcfg, 0); - pll_enable(&pllcfg, 0); - pll_wait_for_lock(0); - pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); - } -#endif - - /* Update the SystemFrequency variable */ - SystemCoreClockUpdate(); - -#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) - /* Signal that the internal frequencies are setup */ - sysclk_initialized = 1; -#endif -} - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/sysclk.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/sysclk.h deleted file mode 100644 index 4460fd561..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sam4e/sysclk.h +++ /dev/null @@ -1,456 +0,0 @@ -/** - * \file - * - * \brief Chip-specific system clock management functions. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CHIP_SYSCLK_H_INCLUDED -#define CHIP_SYSCLK_H_INCLUDED - -#include -#include - -/** - * \page sysclk_quickstart Quick Start Guide for the System Clock Management - * service (SAM4E) - * - * This is the quick start guide for the \ref sysclk_group "System Clock - * Management" service, with step-by-step instructions on how to configure and - * use the service for specific use cases. - * - * \section sysclk_quickstart_usecases System Clock Management use cases - * - \ref sysclk_quickstart_basic - * - \ref sysclk_quickstart_use_case_2 - * - * \section sysclk_quickstart_basic Basic usage of the System Clock Management - * service - * This section will present a basic use case for the System Clock Management - * service. This use case will configure the main system clock to 120MHz, - * using an internal PLL module to multiply the frequency of a crystal attached - * to the microcontroller. - * - * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites - * - None - * - * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code - * Add to the application initialization code: - * \code - * sysclk_init(); - * \endcode - * - * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow - * -# Configure the system clocks according to the settings in conf_clock.h: - * \code sysclk_init(); \endcode - * - * \subsection sysclk_quickstart_use_case_1_example_code Example code - * Add or uncomment the following in your conf_clock.h header file, - * commenting out all other definitions of the same symbol(s): - * \code - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK - * - * // Fpll0 = (Fclk * PLL_mul) / PLL_div - * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL - * #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL) - * #define CONFIG_PLL0_DIV 1 - * - * // Fbus = Fsys / BUS_div - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 - * \endcode - * - * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow - * -# Configure the main system clock to use the output of the PLL module as - * its source: - * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode - * -# Configure the PLL module to use the fast external fast crystal - * oscillator as its source: - * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode - * -# Configure the PLL module to multiply the external fast crystal - * oscillator frequency up to 120MHz: - * \code - * #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL) - * #define CONFIG_PLL0_DIV 1 - * \endcode - * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the - * board \c conf_board.h configuration - * file as the frequency of the fast crystal attached to the microcontroller. - * -# Configure the main clock to run at the full 120MHz, disable scaling of - * the main system clock speed: - * \code - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 - * \endcode - * \note Some dividers are powers of two, while others are integer division - * factors. Refer to the formulas in the conf_clock.h template commented - * above each division define. - */ - -/** - * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock - * Management (SAM4E) - * - * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus - * Clock Management - * This section will present a more advanced use case for the System Clock - * Management service. This use case will configure the main system clock to - * 96MHz, using an internal PLL module to multiply the frequency of a crystal - * attached to the microcontroller. The USB clock will be configured via the - * same PLL module. - * - * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites - * - None - * - * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code - * Add to the application initialization code: - * \code - * sysclk_init(); - * \endcode - * - * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow - * -# Configure the system clocks according to the settings in conf_clock.h: - * \code sysclk_init(); \endcode - * - * \subsection sysclk_quickstart_use_case_2_example_code Example code - * Add or uncomment the following in your conf_clock.h header file, - * commenting out all other definitions of the same symbol(s): - * \code - * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK - * - * // Fpll0 = (Fclk * PLL_mul) / PLL_div - * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL - * #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL) - * #define CONFIG_PLL0_DIV 1 - * - * // Fbus = Fsys / BUS_div - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 - * - * // Fusb = Fsys / USB_div - * #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 - * #define CONFIG_USBCLK_DIV 2 - * \endcode - * - * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow - * -# Configure the main system clock to use the output of the PLL0 module as - * its source: - * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode - * -# Configure the PLL0 module to use the fast external fast crystal - * oscillator as its source: - * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode - * -# Configure the PLL0 module to multiply the external fast crystal - * oscillator frequency up to 96MHz: - * \code - * #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL) - * #define CONFIG_PLL0_DIV 1 - * \endcode - * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the - * board \c conf_board.h configuration file as the frequency of the fast - * crystal attached to the microcontroller. - * -# Configure the main clock to run at the full 96MHz, disable scaling of - * the main system clock speed: - * \code - * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 - * \endcode - * \note Some dividers are powers of two, while others are integer division - * factors. Refer to the formulas in the conf_clock.h template commented - * above each division define. - * -# Configure the USB module clock to use the output of the PLL0 module as - * its source with division 2: - * \code - * #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 - * #define CONFIG_USBCLK_DIV 2 - * \endcode - */ - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \weakgroup sysclk_group - * @{ - */ - -//! \name Configuration Symbols -//@{ -/** - * \def CONFIG_SYSCLK_SOURCE - * \brief Initial/static main system clock source - * - * The main system clock will be configured to use this clock during - * initialization. - */ -#ifndef CONFIG_SYSCLK_SOURCE -# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC -#endif -/** - * \def CONFIG_SYSCLK_PRES - * \brief Initial CPU clock divider (mck) - * - * The MCK will run at - * \f[ - * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz} - * \f] - * after initialization. - */ -#ifndef CONFIG_SYSCLK_PRES -# define CONFIG_SYSCLK_PRES 0 -#endif - -//@} - -//! \name Master Clock Sources (MCK) -//@{ -#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock -#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock -#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock -#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock -#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock -#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock -#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock -#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock -#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock -//@} - -//! \name Master Clock Prescalers (MCK) -//@{ -#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1 -#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2 -#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4 -#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8 -#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16 -#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32 -#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64 -#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3 -//@} - -//! \name USB Clock Sources -//@{ -#define USBCLK_SRC_PLL0 0 //!< Use PLLA -//@} - -/** - * \def CONFIG_USBCLK_SOURCE - * \brief Configuration symbol for the USB generic clock source - * - * Sets the clock source to use for the USB. The source must also be properly - * configured. - * - * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if - * USB is not required. - */ -#ifdef __DOXYGEN__ -# define CONFIG_USBCLK_SOURCE -#endif - -/** - * \def CONFIG_USBCLK_DIV - * \brief Configuration symbol for the USB generic clock divider setting - * - * Sets the clock division for the USB generic clock. If a USB clock source is - * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be - * defined. - */ -#ifdef __DOXYGEN__ -# define CONFIG_USBCLK_DIV -#endif - -/** - * \name Querying the system clock - * - * The following functions may be used to query the current frequency of - * the system clock and the CPU and bus clocks derived from it. - * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be - * available on all platforms, although some platforms may define - * additional accessors for various chip-internal bus clocks. These are - * usually not intended to be queried directly by generic code. - */ -//@{ - -/** - * \brief Return the current rate in Hz of the main system clock - * - * \todo This function assumes that the main clock source never changes - * once it's been set up, and that PLL0 always runs at the compile-time - * configured default rate. While this is probably the most common - * configuration, which we want to support as a special case for - * performance reasons, we will at some point need to support more - * dynamic setups as well. - */ -#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) -extern uint32_t sysclk_initialized; -#endif -static inline uint32_t sysclk_get_main_hz(void) -{ -#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) - if (!sysclk_initialized ) { - return OSC_MAINCK_4M_RC_HZ; - } -#endif - - /* Config system clock setting */ - if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { - return OSC_SLCK_32K_RC_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { - return OSC_SLCK_32K_XTAL_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { - return OSC_SLCK_32K_BYPASS_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { - return OSC_MAINCK_4M_RC_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { - return OSC_MAINCK_8M_RC_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { - return OSC_MAINCK_12M_RC_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { - return OSC_MAINCK_XTAL_HZ; - } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { - return OSC_MAINCK_BYPASS_HZ; - } -#ifdef CONFIG_PLL0_SOURCE - else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { - return pll_get_default_rate(0); - } -#endif - - else { - /* unhandled_case(CONFIG_SYSCLK_SOURCE); */ - return 0; - } -} - -/** - * \brief Return the current rate in Hz of the CPU clock - * - * \todo This function assumes that the CPU always runs at the system - * clock frequency. We want to support at least two more scenarios: - * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus - * clock dividers (which may change at run time). Ditto for all the bus - * clocks. - * - * \return Frequency of the CPU clock, in Hz. - */ -static inline uint32_t sysclk_get_cpu_hz(void) -{ - /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ - /* prescaler, not an immediate value. */ - return sysclk_get_main_hz() / - ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : - (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))); -} - -/** - * \brief Retrieves the current rate in Hz of the peripheral clocks. - * - * \return Frequency of the peripheral clocks, in Hz. - */ -static inline uint32_t sysclk_get_peripheral_hz(void) -{ - /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ - /* prescaler, not an immediate value. */ - return sysclk_get_main_hz() / - ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : - (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))); -} - -/** - * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached - * to the specified peripheral. - * - * \param module Pointer to the module's base address. - * - * \return Frequency of the bus attached to the specified peripheral, in Hz. - */ -static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module) -{ - UNUSED(module); - return sysclk_get_peripheral_hz(); -} -//@} - -//! \name Enabling and disabling synchronous clocks -//@{ - -/** - * \brief Enable a peripheral's clock. - * - * \param ul_id Id (number) of the peripheral clock. - */ -static inline void sysclk_enable_peripheral_clock(uint32_t ul_id) -{ - pmc_enable_periph_clk(ul_id); -} - -/** - * \brief Disable a peripheral's clock. - * - * \param ul_id Id (number) of the peripheral clock. - */ -static inline void sysclk_disable_peripheral_clock(uint32_t ul_id) -{ - pmc_disable_periph_clk(ul_id); -} - -//@} - -//! \name System Clock Source and Prescaler configuration -//@{ - -extern void sysclk_set_prescalers(uint32_t ul_pres); -extern void sysclk_set_source(uint32_t ul_src); - -//@} - -extern void sysclk_enable_usb(void); -extern void sysclk_disable_usb(void); - -extern void sysclk_init(void); - -//! @} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CHIP_SYSCLK_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sysclk.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sysclk.h deleted file mode 100644 index 5221b8a36..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/clock/sysclk.h +++ /dev/null @@ -1,175 +0,0 @@ -/** - * \file - * - * \brief System clock management - * - * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef SYSCLK_H_INCLUDED -#define SYSCLK_H_INCLUDED - -#include "parts.h" -#include "conf_clock.h" - -#if SAM3S -# include "sam3s/sysclk.h" -#elif SAM3U -# include "sam3u/sysclk.h" -#elif SAM3N -# include "sam3n/sysclk.h" -#elif SAM3XA -# include "sam3x/sysclk.h" -#elif SAM4S -# include "sam4s/sysclk.h" -#elif SAM4E -# include "sam4e/sysclk.h" -#elif SAM4L -# include "sam4l/sysclk.h" -#elif SAM4N -# include "sam4n/sysclk.h" -#elif (UC3A0 || UC3A1) -# include "uc3a0_a1/sysclk.h" -#elif UC3A3 -# include "uc3a3_a4/sysclk.h" -#elif UC3B -# include "uc3b0_b1/sysclk.h" -#elif UC3C -# include "uc3c/sysclk.h" -#elif UC3D -# include "uc3d/sysclk.h" -#elif UC3L -# include "uc3l/sysclk.h" -#elif XMEGA -# include "xmega/sysclk.h" -#elif MEGA -# include "mega/sysclk.h" -#else -# error Unsupported chip type -#endif - -/** - * \defgroup clk_group Clock Management - */ - -/** - * \ingroup clk_group - * \defgroup sysclk_group System Clock Management - * - * See \ref sysclk_quickstart. - * - * The sysclk API covers the system clock and all - * clocks derived from it. The system clock is a chip-internal clock on - * which all synchronous clocks, i.e. CPU and bus/peripheral - * clocks, are based. The system clock is typically generated from one - * of a variety of sources, which may include crystal and RC oscillators - * as well as PLLs. The clocks derived from the system clock are - * sometimes also known as synchronous clocks, since they - * always run synchronously with respect to each other, as opposed to - * generic clocks which may run from different oscillators or - * PLLs. - * - * Most applications should simply call sysclk_init() to initialize - * everything related to the system clock and its source (oscillator, - * PLL or DFLL), and leave it at that. More advanced applications, and - * platform-specific drivers, may require additional services from the - * clock system, some of which may be platform-specific. - * - * \section sysclk_group_platform Platform Dependencies - * - * The sysclk API is partially chip- or platform-specific. While all - * platforms provide mostly the same functionality, there are some - * variations around how different bus types and clock tree structures - * are handled. - * - * The following functions are available on all platforms with the same - * parameters and functionality. These functions may be called freely by - * portable applications, drivers and services: - * - sysclk_init() - * - sysclk_set_source() - * - sysclk_get_main_hz() - * - sysclk_get_cpu_hz() - * - sysclk_get_peripheral_bus_hz() - * - * The following functions are available on all platforms, but there may - * be variations in the function signature (i.e. parameters) and - * behavior. These functions are typically called by platform-specific - * parts of drivers, and applications that aren't intended to be - * portable: - * - sysclk_enable_peripheral_clock() - * - sysclk_disable_peripheral_clock() - * - sysclk_enable_module() - * - sysclk_disable_module() - * - sysclk_module_is_enabled() - * - sysclk_set_prescalers() - * - * All other functions should be considered platform-specific. - * Enabling/disabling clocks to specific peripherals as well as - * determining the speed of these clocks should be done by calling - * functions provided by the driver for that peripheral. - * - * @{ - */ - -//! \name System Clock Initialization -//@{ -/** - * \fn void sysclk_init(void) - * \brief Initialize the synchronous clock system. - * - * This function will initialize the system clock and its source. This - * includes: - * - Mask all synchronous clocks except for any clocks which are - * essential for normal operation (for example internal memory - * clocks). - * - Set up the system clock prescalers as specified by the - * application's configuration file. - * - Enable the clock source specified by the application's - * configuration file (oscillator or PLL) and wait for it to become - * stable. - * - Set the main system clock source to the clock specified by the - * application's configuration file. - * - * Since all non-essential peripheral clocks are initially disabled, it - * is the responsibility of the peripheral driver to re-enable any - * clocks that are needed for normal operation. - */ -//@} - -//! @} - -#endif /* SYSCLK_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/ioport/ioport.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/ioport/ioport.h deleted file mode 100644 index 7cf38f77c..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/ioport/ioport.h +++ /dev/null @@ -1,538 +0,0 @@ -/** - * \file - * - * \brief Common IOPORT service main header file for AVR, UC3 and ARM - * architectures. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef IOPORT_H -#define IOPORT_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * \defgroup ioport_group Common IOPORT API - * - * See \ref ioport_quickstart. - * - * This is common IOPORT service for GPIO pin configuration and control in a - * standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices. - * - * Port pin control code is optimized for each platform, and should produce - * both compact and fast execution times when used with constant values. - * - * \section dependencies Dependencies - * This driver depends on the following modules: - * - \ref sysclk_group for clock speed and functions. - * @{ - */ - -/** - * \def IOPORT_CREATE_PIN(port, pin) - * \brief Create IOPORT pin number - * - * Create a IOPORT pin number for use with the IOPORT functions. - * - * \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen - * architecture) - * \param pin IOPORT zero-based index of the I/O pin - */ - -/** \brief IOPORT pin directions */ -enum ioport_direction { - IOPORT_DIR_INPUT, /*!< IOPORT input direction */ - IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */ -}; - -/** \brief IOPORT levels */ -enum ioport_value { - IOPORT_PIN_LEVEL_LOW, /*!< IOPORT pin value low */ - IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */ -}; - -#if MEGA_RF -/** \brief IOPORT edge sense modes */ -enum ioport_sense { - IOPORT_SENSE_LEVEL, /*!< IOPORT sense low level */ - IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ - IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ - IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ -}; -#elif SAM && !SAM4L -/** \brief IOPORT edge sense modes */ -enum ioport_sense { - IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ - IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ - IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ - IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */ - IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level */ -}; -#else -enum ioport_sense { - IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ - IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ - IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ -}; -#endif - - -#if XMEGA -# include "xmega/ioport.h" -# if defined(IOPORT_XMEGA_COMPAT) -# include "xmega/ioport_compat.h" -# endif -#elif MEGA -# include "mega/ioport.h" -#elif UC3 -# include "uc3/ioport.h" -#elif SAM -# if SAM4L -# include "sam/ioport_gpio.h" -# elif SAMD20 -# include "sam0/ioport.h" -# else -# include "sam/ioport_pio.h" -# endif -#endif - -/** - * \brief Initializes the IOPORT service, ready for use. - * - * This function must be called before using any other functions in the IOPORT - * service. - */ -static inline void ioport_init(void) -{ - arch_ioport_init(); -} - -/** - * \brief Enable an IOPORT pin, based on a pin created with \ref - * IOPORT_CREATE_PIN(). - * - * \param pin IOPORT pin to enable - */ -static inline void ioport_enable_pin(ioport_pin_t pin) -{ - arch_ioport_enable_pin(pin); -} - -/** - * \brief Enable multiple pins in a single IOPORT port. - * - * \param port IOPORT port to enable - * \param mask Mask of pins within the port to enable - */ -static inline void ioport_enable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_enable_port(port, mask); -} - -/** - * \brief Disable IOPORT pin, based on a pin created with \ref - * IOPORT_CREATE_PIN(). - * - * \param pin IOPORT pin to disable - */ -static inline void ioport_disable_pin(ioport_pin_t pin) -{ - arch_ioport_disable_pin(pin); -} - -/** - * \brief Disable multiple pins in a single IOPORT port. - * - * \param port IOPORT port to disable - * \param mask Pin mask of pins to disable - */ -static inline void ioport_disable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_disable_port(port, mask); -} - -/** - * \brief Set multiple pin modes in a single IOPORT port, such as pull-up, - * pull-down, etc. configuration. - * - * \param port IOPORT port to configure - * \param mask Pin mask of pins to configure - * \param mode Mode masks to configure for the specified pins (\ref - * ioport_modes) - */ -static inline void ioport_set_port_mode(ioport_port_t port, - ioport_port_mask_t mask, ioport_mode_t mode) -{ - arch_ioport_set_port_mode(port, mask, mode); -} - -/** - * \brief Set pin mode for one single IOPORT pin. - * - * \param pin IOPORT pin to configure - * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) - */ -static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode) -{ - arch_ioport_set_pin_mode(pin, mode); -} - -/** - * \brief Reset multiple pin modes in a specified IOPORT port to defaults. - * - * \param port IOPORT port to configure - * \param mask Mask of pins whose mode configuration is to be reset - */ -static inline void ioport_reset_port_mode(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_set_port_mode(port, mask, 0); -} - -/** - * \brief Reset pin mode configuration for a single IOPORT pin - * - * \param pin IOPORT pin to configure - */ -static inline void ioport_reset_pin_mode(ioport_pin_t pin) -{ - arch_ioport_set_pin_mode(pin, 0); -} - -/** - * \brief Set I/O direction for a group of pins in a single IOPORT. - * - * \param port IOPORT port to configure - * \param mask Pin mask of pins to configure - * \param dir Direction to set for the specified pins (\ref ioport_direction) - */ -static inline void ioport_set_port_dir(ioport_port_t port, - ioport_port_mask_t mask, enum ioport_direction dir) -{ - arch_ioport_set_port_dir(port, mask, dir); -} - -/** - * \brief Set direction for a single IOPORT pin. - * - * \param pin IOPORT pin to configure - * \param dir Direction to set for the specified pin (\ref ioport_direction) - */ -static inline void ioport_set_pin_dir(ioport_pin_t pin, - enum ioport_direction dir) -{ - arch_ioport_set_pin_dir(pin, dir); -} - -/** - * \brief Set an IOPORT pin to a specified logical value. - * - * \param pin IOPORT pin to configure - * \param level Logical value of the pin - */ -static inline void ioport_set_pin_level(ioport_pin_t pin, bool level) -{ - arch_ioport_set_pin_level(pin, level); -} - -/** - * \brief Set a group of IOPORT pins in a single port to a specified logical - * value. - * - * \param port IOPORT port to write to - * \param mask Pin mask of pins to modify - * \param level Level of the pins to be modified - */ -static inline void ioport_set_port_level(ioport_port_t port, - ioport_port_mask_t mask, ioport_port_mask_t level) -{ - arch_ioport_set_port_level(port, mask, level); -} - -/** - * \brief Get current value of an IOPORT pin, which has been configured as an - * input. - * - * \param pin IOPORT pin to read - * \return Current logical value of the specified pin - */ -static inline bool ioport_get_pin_level(ioport_pin_t pin) -{ - return arch_ioport_get_pin_level(pin); -} - -/** - * \brief Get current value of several IOPORT pins in a single port, which have - * been configured as an inputs. - * - * \param port IOPORT port to read - * \param mask Pin mask of pins to read - * \return Logical levels of the specified pins from the read port, returned as - * a mask. - */ -static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port, - ioport_port_mask_t mask) -{ - return arch_ioport_get_port_level(port, mask); -} - -/** - * \brief Toggle the value of an IOPORT pin, which has previously configured as - * an output. - * - * \param pin IOPORT pin to toggle - */ -static inline void ioport_toggle_pin_level(ioport_pin_t pin) -{ - arch_ioport_toggle_pin_level(pin); -} - -/** - * \brief Toggle the values of several IOPORT pins located in a single port. - * - * \param port IOPORT port to modify - * \param mask Pin mask of pins to toggle - */ -static inline void ioport_toggle_port_level(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_toggle_port_level(port, mask); -} - -/** - * \brief Set the pin sense mode of a single IOPORT pin. - * - * \param pin IOPORT pin to configure - * \param pin_sense Edge to sense for the pin (\ref ioport_sense) - */ -static inline void ioport_set_pin_sense_mode(ioport_pin_t pin, - enum ioport_sense pin_sense) -{ - arch_ioport_set_pin_sense_mode(pin, pin_sense); -} - -/** - * \brief Set the pin sense mode of a multiple IOPORT pins on a single port. - * - * \param port IOPORT port to configure - * \param mask Bitmask if pins whose edge sense is to be configured - * \param pin_sense Edge to sense for the pins (\ref ioport_sense) - */ -static inline void ioport_set_port_sense_mode(ioport_port_t port, - ioport_port_mask_t mask, - enum ioport_sense pin_sense) -{ - arch_ioport_set_port_sense_mode(port, mask, pin_sense); -} - -/** - * \brief Convert a pin ID into a its port ID. - * - * \param pin IOPORT pin ID to convert - * \retval Port ID for the given pin ID - */ -static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin) -{ - return arch_ioport_pin_to_port_id(pin); -} - -/** - * \brief Convert a pin ID into a bitmask mask for the given pin on its port. - * - * \param pin IOPORT pin ID to convert - * \retval Bitmask with a bit set that corresponds to the given pin ID in its port - */ -static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin) -{ - return arch_ioport_pin_to_mask(pin); -} - -/** @} */ - -/** - * \page ioport_quickstart Quick start guide for the common IOPORT service - * - * This is the quick start guide for the \ref ioport_group, with - * step-by-step instructions on how to configure and use the service in a - * selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section ioport_quickstart_basic Basic use case - * In this use case we will configure one IO pin for button input and one for - * LED control. Then it will read the button state and output it on the LED. - * - * \section ioport_quickstart_basic_setup Setup steps - * - * \subsection ioport_quickstart_basic_setup_code Example code - * \code - * #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) - * #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) - * - * ioport_init(); - * - * ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); - * ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); - * ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); - * \endcode - * - * \subsection ioport_quickstart_basic_setup_flow Workflow - * -# It's useful to give the GPIOs symbolic names and this can be done with - * the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a - * button. - * - \code - * #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) - * #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) - * \endcode - * - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names - * differ between architectures: - * - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions - * PORTA, PORTB ... - * - UC3: Most convenient to pick up the device header file pin definition - * and us it directly. E.g.: AVR32_PIN_PB06 - * - SAM: Most convenient to pick up the device header file pin definition - * and us it directly. E.g.: PIO_PA5_IDX
- * \ref IOPORT_CREATE_PIN can also be used with port definitions - * PIOA, PIOB ... - * -# Initialize the ioport service. This typically enables the IO module if - * needed. - * - \code ioport_init(); \endcode - * -# Set the LED GPIO as output: - * - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode - * -# Set the button GPIO as input: - * - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode - * -# Enable pull-up for the button GPIO: - * - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode - * - * \section ioport_quickstart_basic_usage Usage steps - * - * \subsection ioport_quickstart_basic_usage_code Example code - * \code - * bool value; - * - * value = ioport_get_pin_level(MY_BUTTON); - * ioport_set_pin_level(MY_LED, value); - * \endcode - * - * \subsection ioport_quickstart_basic_usage_flow Workflow - * -# Define a boolean variable for state storage: - * - \code bool value; \endcode - * -# Read out the button level into variable value: - * - \code value = ioport_get_pin_level(MY_BUTTON); \endcode - * -# Set the LED to read out value from the button: - * - \code ioport_set_pin_level(MY_LED, value); \endcode - * - * \section ioport_quickstart_advanced Advanced use cases - * - \subpage ioport_quickstart_use_case_1 : Port access - */ - -/** - * \page ioport_quickstart_use_case_1 Advanced use case doing port access - * - * In this case we will read out the pins from one whole port and write the - * read value to another port. - * - * \section ioport_quickstart_use_case_1_setup Setup steps - * - * \subsection ioport_quickstart_use_case_1_setup_code Example code - * \code - * #define IN_PORT IOPORT_PORTA - * #define OUT_PORT IOPORT_PORTB - * #define MASK 0x00000060 - * - * ioport_init(); - * - * ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); - * ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); - * \endcode - * - * \subsection ioport_quickstart_basic_setup_flow Workflow - * -# It's useful to give the ports symbolic names: - * - \code - * #define IN_PORT IOPORT_PORTA - * #define OUT_PORT IOPORT_PORTB - * \endcode - * - \note The port names differ between architectures: - * - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA, - * IOPORT_PORTB ... - * - UC3: Use the index value of the different IO blocks: 0, 1 ... - * - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB - * ... - * -# Also useful to define a mask for the bits to work with: - * - \code #define MASK 0x00000060 \endcode - * -# Initialize the ioport service. This typically enables the IO module if - * needed. - * - \code ioport_init(); \endcode - * -# Set one of the ports as input: - * - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode - * -# Set the other port as output: - * - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode - * - * \section ioport_quickstart_basic_usage Usage steps - * - * \subsection ioport_quickstart_basic_usage_code Example code - * \code - * ioport_port_mask_t value; - * - * value = ioport_get_port_level(IN_PORT, MASK); - * ioport_set_port_level(OUT_PORT, MASK, value); - * \endcode - * - * \subsection ioport_quickstart_basic_usage_flow Workflow - * -# Define a variable for port date storage: - * - \code ioport_port_mask_t value; \endcode - * -# Read out from one port: - * - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode - * -# Put the read data out on the other port: - * - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode - */ - -#ifdef __cplusplus -} -#endif - -#endif /* IOPORT_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/ioport/sam/ioport_pio.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/ioport/sam/ioport_pio.h deleted file mode 100644 index 20f97c0a1..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/services/ioport/sam/ioport_pio.h +++ /dev/null @@ -1,364 +0,0 @@ -/** - * \file - * - * \brief SAM architecture specific IOPORT service implementation header file. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef IOPORT_SAM_H -#define IOPORT_SAM_H - -#include - -#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 32 + (pin)) -#define IOPORT_BASE_ADDRESS (uintptr_t)PIOA -#define IOPORT_PIO_OFFSET ((uintptr_t)PIOB - (uintptr_t)PIOA) - -#define IOPORT_PIOA 0 -#define IOPORT_PIOB 1 -#define IOPORT_PIOC 2 -#define IOPORT_PIOD 3 -#define IOPORT_PIOE 4 -#define IOPORT_PIOF 5 - -/** - * \weakgroup ioport_group - * \section ioport_modes IOPORT Modes - * - * For details on these please see the SAM Manual. - * - * @{ - */ - -/** \name IOPORT Mode bit definitions */ -/** @{ */ -#define IOPORT_MODE_MUX_MASK (0x7 << 0) /*!< MUX bits mask */ -#define IOPORT_MODE_MUX_BIT0 ( 1 << 0) /*!< MUX BIT0 mask */ - -#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N -#define IOPORT_MODE_MUX_BIT1 ( 1 << 1) /*!< MUX BIT1 mask */ -#endif - -#define IOPORT_MODE_MUX_A ( 0 << 0) /*!< MUX function A */ -#define IOPORT_MODE_MUX_B ( 1 << 0) /*!< MUX function B */ - -#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N -#define IOPORT_MODE_MUX_C ( 2 << 0) /*!< MUX function C */ -#define IOPORT_MODE_MUX_D ( 3 << 0) /*!< MUX function D */ -#endif - -#define IOPORT_MODE_PULLUP ( 1 << 3) /*!< Pull-up */ - -#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N -#define IOPORT_MODE_PULLDOWN ( 1 << 4) /*!< Pull-down */ -#endif - -#define IOPORT_MODE_OPEN_DRAIN ( 1 << 5) /*!< Open drain */ - -#define IOPORT_MODE_GLITCH_FILTER ( 1 << 6) /*!< Glitch filter */ -#define IOPORT_MODE_DEBOUNCE ( 1 << 7) /*!< Input debounce */ -/** @} */ - -/** @} */ - -typedef uint32_t ioport_mode_t; -typedef uint32_t ioport_pin_t; -typedef uint32_t ioport_port_t; -typedef uint32_t ioport_port_mask_t; - -__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin) -{ - return pin >> 5; -} - -__always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port) -{ - return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + - (IOPORT_PIO_OFFSET * port)); -} - -__always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin) -{ - return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin)); -} - -__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin) -{ - return 1U << (pin & 0x1F); -} - -__always_inline static void arch_ioport_init(void) -{ -#ifdef ID_PIOA - sysclk_enable_peripheral_clock(ID_PIOA); -#endif -#ifdef ID_PIOB - sysclk_enable_peripheral_clock(ID_PIOB); -#endif -#ifdef ID_PIOC - sysclk_enable_peripheral_clock(ID_PIOC); -#endif -#ifdef ID_PIOD - sysclk_enable_peripheral_clock(ID_PIOD); -#endif -#ifdef ID_PIOE - sysclk_enable_peripheral_clock(ID_PIOE); -#endif -#ifdef ID_PIOF - sysclk_enable_peripheral_clock(ID_PIOF); -#endif -} - -__always_inline static void arch_ioport_enable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->PIO_PER = mask; -} - -__always_inline static void arch_ioport_disable_port(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->PIO_PDR = mask; -} - -__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin) -{ - arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin)); -} - -__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin) -{ - arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin)); -} - -__always_inline static void arch_ioport_set_port_mode(ioport_port_t port, - ioport_port_mask_t mask, ioport_mode_t mode) -{ - Pio *base = arch_ioport_port_to_base(port); - - if (mode & IOPORT_MODE_PULLUP) { - base->PIO_PUER = mask; - } else { - base->PIO_PUDR = mask; - } - -#if defined(IOPORT_MODE_PULLDOWN) - if (mode & IOPORT_MODE_PULLDOWN) { - base->PIO_PPDER = mask; - } else { - base->PIO_PPDDR = mask; - } -#endif - - if (mode & IOPORT_MODE_OPEN_DRAIN) { - base->PIO_MDER = mask; - } else { - base->PIO_MDDR = mask; - } - - if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) { - base->PIO_IFER = mask; - } else { - base->PIO_IFDR = mask; - } - - if (mode & IOPORT_MODE_DEBOUNCE) { -#if SAM3U || SAM3XA - base->PIO_DIFSR = mask; -#else - base->PIO_IFSCER = mask; -#endif - } else { -#if SAM3U || SAM3XA - base->PIO_SCIFSR = mask; -#else - base->PIO_IFSCDR = mask; -#endif - } - -#if !defined(IOPORT_MODE_MUX_BIT1) - if (mode & IOPORT_MODE_MUX_BIT0) { - base->PIO_ABSR |= mask; - } else { - base->PIO_ABSR &= ~mask; - } -#else - if (mode & IOPORT_MODE_MUX_BIT0) { - base->PIO_ABCDSR[0] |= mask; - } else { - base->PIO_ABCDSR[0] &= ~mask; - } - - if (mode & IOPORT_MODE_MUX_BIT1) { - base->PIO_ABCDSR[1] |= mask; - } else { - base->PIO_ABCDSR[1] &= ~mask; - } -#endif -} - -__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin, - ioport_mode_t mode) -{ - arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin), mode); -} - -__always_inline static void arch_ioport_set_port_dir(ioport_port_t port, - ioport_port_mask_t mask, enum ioport_direction group_direction) -{ - Pio *base = arch_ioport_port_to_base(port); - - if (group_direction == IOPORT_DIR_OUTPUT) { - base->PIO_OER = mask; - } else if (group_direction == IOPORT_DIR_INPUT) { - base->PIO_ODR = mask; - } - - base->PIO_OWER = mask; -} - -__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin, - enum ioport_direction dir) -{ - Pio *base = arch_ioport_pin_to_base(pin); - - if (dir == IOPORT_DIR_OUTPUT) { - base->PIO_OER = arch_ioport_pin_to_mask(pin); - } else if (dir == IOPORT_DIR_INPUT) { - base->PIO_ODR = arch_ioport_pin_to_mask(pin); - } - - base->PIO_OWER = arch_ioport_pin_to_mask(pin); -} - -__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin, - bool level) -{ - Pio *base = arch_ioport_pin_to_base(pin); - - if (level) { - base->PIO_SODR = arch_ioport_pin_to_mask(pin); - } else { - base->PIO_CODR = arch_ioport_pin_to_mask(pin); - } -} - -__always_inline static void arch_ioport_set_port_level(ioport_port_t port, - ioport_port_mask_t mask, ioport_port_mask_t level) -{ - Pio *base = arch_ioport_port_to_base(port); - - base->PIO_SODR = mask & level; - base->PIO_CODR = mask & ~level; -} - -__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin) -{ - return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin); -} - -__always_inline static ioport_port_mask_t arch_ioport_get_port_level( - ioport_port_t port, ioport_port_mask_t mask) -{ - return arch_ioport_port_to_base(port)->PIO_PDSR & mask; -} - -__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin) -{ - Pio *port = arch_ioport_pin_to_base(pin); - ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin); - - if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) { - port->PIO_CODR = mask; - } else { - port->PIO_SODR = mask; - } -} - -__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port, - ioport_port_mask_t mask) -{ - arch_ioport_port_to_base(port)->PIO_ODSR ^= mask; -} - -__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port, - ioport_port_mask_t mask, enum ioport_sense pin_sense) -{ - Pio *base = arch_ioport_port_to_base(port); - /* AIMMR ELSR FRLHSR - * 0 X X IOPORT_SENSE_BOTHEDGES (Default) - * 1 0 0 IOPORT_SENSE_FALLING - * 1 0 1 IOPORT_SENSE_RISING - * 1 1 0 IOPORT_SENSE_LEVEL_LOW - * 1 1 1 IOPORT_SENSE_LEVEL_HIGH - */ - switch(pin_sense) { - case IOPORT_SENSE_LEVEL_LOW: - base->PIO_LSR = mask; - base->PIO_FELLSR = mask; - break; - case IOPORT_SENSE_LEVEL_HIGH: - base->PIO_LSR = mask; - base->PIO_REHLSR = mask; - break; - case IOPORT_SENSE_FALLING: - base->PIO_ESR = mask; - base->PIO_FELLSR = mask; - break; - case IOPORT_SENSE_RISING: - base->PIO_ESR = mask; - base->PIO_REHLSR = mask; - break; - default: - base->PIO_AIMDR = mask; - return; - } - base->PIO_AIMER = mask; -} - -__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin, - enum ioport_sense pin_sense) -{ - arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin), - arch_ioport_pin_to_mask(pin), pin_sense); -} - -#endif /* IOPORT_SAM_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt.h deleted file mode 100644 index 677487989..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * \file - * - * \brief Global interrupt management for 8- and 32-bit AVR - * - * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef UTILS_INTERRUPT_H -#define UTILS_INTERRUPT_H - -#include - -#if XMEGA || MEGA || TINY -# include "interrupt/interrupt_avr8.h" -#elif UC3 -# include "interrupt/interrupt_avr32.h" -#elif SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4L || SAM4E || SAMD20 || SAM -# include "interrupt/interrupt_sam_nvic.h" -#else -# error Unsupported device. -#endif - -/** - * \defgroup interrupt_group Global interrupt management - * - * This is a driver for global enabling and disabling of interrupts. - * - * @{ - */ - -#if defined(__DOXYGEN__) -/** - * \def CONFIG_INTERRUPT_FORCE_INTC - * \brief Force usage of the ASF INTC driver - * - * Predefine this symbol when preprocessing to force the use of the ASF INTC driver. - * This is useful to ensure compatibility across compilers and shall be used only when required - * by the application needs. - */ -# define CONFIG_INTERRUPT_FORCE_INTC -#endif - -//! \name Global interrupt flags -//@{ -/** - * \typedef irqflags_t - * \brief Type used for holding state of interrupt flag - */ - -/** - * \def cpu_irq_enable - * \brief Enable interrupts globally - */ - -/** - * \def cpu_irq_disable - * \brief Disable interrupts globally - */ - -/** - * \fn irqflags_t cpu_irq_save(void) - * \brief Get and clear the global interrupt flags - * - * Use in conjunction with \ref cpu_irq_restore. - * - * \return Current state of interrupt flags. - * - * \note This function leaves interrupts disabled. - */ - -/** - * \fn void cpu_irq_restore(irqflags_t flags) - * \brief Restore global interrupt flags - * - * Use in conjunction with \ref cpu_irq_save. - * - * \param flags State to set interrupt flag to. - */ - -/** - * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags) - * \brief Check if interrupts are globally enabled in supplied flags - * - * \param flags Currents state of interrupt flags. - * - * \return True if interrupts are enabled. - */ - -/** - * \def cpu_irq_is_enabled - * \brief Check if interrupts are globally enabled - * - * \return True if interrupts are enabled. - */ -//@} - -//! @} - -/** - * \ingroup interrupt_group - * \defgroup interrupt_deprecated_group Deprecated interrupt definitions - */ - -#endif /* UTILS_INTERRUPT_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c deleted file mode 100644 index 37dd08398..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) - * - * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "interrupt_sam_nvic.h" - -#if !defined(__DOXYGEN__) -/* Deprecated - global flag to determine the global interrupt state. Required by - * QTouch library, however new applications should use cpu_irq_is_enabled() - * which probes the true global interrupt state from the CPU special registers. - */ -volatile bool g_interrupt_enabled = true; -#endif - -void cpu_irq_enter_critical(void) -{ - if (cpu_irq_critical_section_counter == 0) { - if (cpu_irq_is_enabled()) { - cpu_irq_disable(); - cpu_irq_prev_interrupt_state = true; - } else { - /* Make sure the to save the prev state as false */ - cpu_irq_prev_interrupt_state = false; - } - - } - - cpu_irq_critical_section_counter++; -} - -void cpu_irq_leave_critical(void) -{ - /* Check if the user is trying to leave a critical section when not in a critical section */ - Assert(cpu_irq_critical_section_counter > 0); - - cpu_irq_critical_section_counter--; - - /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag - was enabled when entering critical state */ - if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) { - cpu_irq_enable(); - } -} - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h deleted file mode 100644 index 8dbe15e01..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h +++ /dev/null @@ -1,178 +0,0 @@ -/** - * \file - * - * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) - * - * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef UTILS_INTERRUPT_INTERRUPT_H -#define UTILS_INTERRUPT_INTERRUPT_H - -#include -#include - -/** - * \weakgroup interrupt_group - * - * @{ - */ - -/** - * \name Interrupt Service Routine definition - * - * @{ - */ - -/** - * \brief Define service routine - * - * \note For NVIC devices the interrupt service routines are predefined to - * add to vector table in binary generation, so there is no service - * register at run time. The routine collections are in exceptions.h. - * - * Usage: - * \code - * ISR(foo_irq_handler) - * { - * // Function definition - * ... - * } - * \endcode - * - * \param func Name for the function. - */ -# define ISR(func) \ - void func (void) - -/** - * \brief Initialize interrupt vectors - * - * For NVIC the interrupt vectors are put in vector table. So nothing - * to do to initialize them, except defined the vector function with - * right name. - * - * This must be called prior to \ref irq_register_handler. - */ -# define irq_initialize_vectors() \ - do { \ - } while(0) - -/** - * \brief Register handler for interrupt - * - * For NVIC the interrupt vectors are put in vector table. So nothing - * to do to register them, except defined the vector function with - * right name. - * - * Usage: - * \code - * irq_initialize_vectors(); - * irq_register_handler(foo_irq_handler); - * \endcode - * - * \note The function \a func must be defined with the \ref ISR macro. - * \note The functions prototypes can be found in the device exception header - * files (exceptions.h). - */ -# define irq_register_handler(int_num, int_prio) \ - NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ - NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ - NVIC_EnableIRQ( (IRQn_Type)int_num); \ - -//@} - -# define cpu_irq_enable() \ - do { \ - g_interrupt_enabled = true; \ - __DMB(); \ - __enable_irq(); \ - } while (0) -# define cpu_irq_disable() \ - do { \ - __disable_irq(); \ - __DMB(); \ - g_interrupt_enabled = false; \ - } while (0) - -typedef uint32_t irqflags_t; - -#if !defined(__DOXYGEN__) -extern volatile bool g_interrupt_enabled; -#endif - -#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) - -static volatile uint32_t cpu_irq_critical_section_counter; -static volatile bool cpu_irq_prev_interrupt_state; - -static inline irqflags_t cpu_irq_save(void) -{ - irqflags_t flags = cpu_irq_is_enabled(); - cpu_irq_disable(); - return flags; -} - -static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) -{ - return (flags); -} - -static inline void cpu_irq_restore(irqflags_t flags) -{ - if (cpu_irq_is_enabled_flags(flags)) - cpu_irq_enable(); -} - -void cpu_irq_enter_critical(void); -void cpu_irq_leave_critical(void); - -/** - * \weakgroup interrupt_deprecated_group - * @{ - */ - -#define Enable_global_interrupt() cpu_irq_enable() -#define Disable_global_interrupt() cpu_irq_disable() -#define Is_global_interrupt_enabled() cpu_irq_is_enabled() - -//@} - -//@} - -#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/parts.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/parts.h deleted file mode 100644 index 4f063a553..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/common/utils/parts.h +++ /dev/null @@ -1,949 +0,0 @@ -/** - * \file - * - * \brief Atmel part identification macros - * - * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ATMEL_PARTS_H -#define ATMEL_PARTS_H - -/** - * \defgroup part_macros_group Atmel part identification macros - * - * This collection of macros identify which series and families that the various - * Atmel parts belong to. These can be used to select part-dependent sections of - * code at compile time. - * - * @{ - */ - -/** - * \name Convenience macros for part checking - * @{ - */ -/* ! Check GCC and IAR part definition for 8-bit AVR */ -#define AVR8_PART_IS_DEFINED(part) \ - (defined(__ ## part ## __) || defined(__AVR_ ## part ## __)) - -/* ! Check GCC and IAR part definition for 32-bit AVR */ -#define AVR32_PART_IS_DEFINED(part) \ - (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __)) - -/* ! Check GCC and IAR part definition for SAM */ -#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __)) -/** @} */ - -/** - * \defgroup uc3_part_macros_group AVR UC3 parts - * @{ - */ - -/** - * \name AVR UC3 A series - * @{ - */ -#define UC3A0 ( \ - AVR32_PART_IS_DEFINED(UC3A0128) || \ - AVR32_PART_IS_DEFINED(UC3A0256) || \ - AVR32_PART_IS_DEFINED(UC3A0512) \ - ) - -#define UC3A1 ( \ - AVR32_PART_IS_DEFINED(UC3A1128) || \ - AVR32_PART_IS_DEFINED(UC3A1256) || \ - AVR32_PART_IS_DEFINED(UC3A1512) \ - ) - -#define UC3A3 ( \ - AVR32_PART_IS_DEFINED(UC3A364) || \ - AVR32_PART_IS_DEFINED(UC3A364S) || \ - AVR32_PART_IS_DEFINED(UC3A3128) || \ - AVR32_PART_IS_DEFINED(UC3A3128S) || \ - AVR32_PART_IS_DEFINED(UC3A3256) || \ - AVR32_PART_IS_DEFINED(UC3A3256S) \ - ) - -#define UC3A4 ( \ - AVR32_PART_IS_DEFINED(UC3A464) || \ - AVR32_PART_IS_DEFINED(UC3A464S) || \ - AVR32_PART_IS_DEFINED(UC3A4128) || \ - AVR32_PART_IS_DEFINED(UC3A4128S) || \ - AVR32_PART_IS_DEFINED(UC3A4256) || \ - AVR32_PART_IS_DEFINED(UC3A4256S) \ - ) -/** @} */ - -/** - * \name AVR UC3 B series - * @{ - */ -#define UC3B0 ( \ - AVR32_PART_IS_DEFINED(UC3B064) || \ - AVR32_PART_IS_DEFINED(UC3B0128) || \ - AVR32_PART_IS_DEFINED(UC3B0256) || \ - AVR32_PART_IS_DEFINED(UC3B0512) \ - ) - -#define UC3B1 ( \ - AVR32_PART_IS_DEFINED(UC3B164) || \ - AVR32_PART_IS_DEFINED(UC3B1128) || \ - AVR32_PART_IS_DEFINED(UC3B1256) || \ - AVR32_PART_IS_DEFINED(UC3B1512) \ - ) -/** @} */ - -/** - * \name AVR UC3 C series - * @{ - */ -#define UC3C0 ( \ - AVR32_PART_IS_DEFINED(UC3C064C) || \ - AVR32_PART_IS_DEFINED(UC3C0128C) || \ - AVR32_PART_IS_DEFINED(UC3C0256C) || \ - AVR32_PART_IS_DEFINED(UC3C0512C) \ - ) - -#define UC3C1 ( \ - AVR32_PART_IS_DEFINED(UC3C164C) || \ - AVR32_PART_IS_DEFINED(UC3C1128C) || \ - AVR32_PART_IS_DEFINED(UC3C1256C) || \ - AVR32_PART_IS_DEFINED(UC3C1512C) \ - ) - -#define UC3C2 ( \ - AVR32_PART_IS_DEFINED(UC3C264C) || \ - AVR32_PART_IS_DEFINED(UC3C2128C) || \ - AVR32_PART_IS_DEFINED(UC3C2256C) || \ - AVR32_PART_IS_DEFINED(UC3C2512C) \ - ) -/** @} */ - -/** - * \name AVR UC3 D series - * @{ - */ -#define UC3D3 ( \ - AVR32_PART_IS_DEFINED(UC64D3) || \ - AVR32_PART_IS_DEFINED(UC128D3) \ - ) - -#define UC3D4 ( \ - AVR32_PART_IS_DEFINED(UC64D4) || \ - AVR32_PART_IS_DEFINED(UC128D4) \ - ) -/** @} */ - -/** - * \name AVR UC3 L series - * @{ - */ -#define UC3L0 ( \ - AVR32_PART_IS_DEFINED(UC3L016) || \ - AVR32_PART_IS_DEFINED(UC3L032) || \ - AVR32_PART_IS_DEFINED(UC3L064) \ - ) - -#define UC3L0128 ( \ - AVR32_PART_IS_DEFINED(UC3L0128) \ - ) - -#define UC3L0256 ( \ - AVR32_PART_IS_DEFINED(UC3L0256) \ - ) - -#define UC3L3 ( \ - AVR32_PART_IS_DEFINED(UC64L3U) || \ - AVR32_PART_IS_DEFINED(UC128L3U) || \ - AVR32_PART_IS_DEFINED(UC256L3U) \ - ) - -#define UC3L4 ( \ - AVR32_PART_IS_DEFINED(UC64L4U) || \ - AVR32_PART_IS_DEFINED(UC128L4U) || \ - AVR32_PART_IS_DEFINED(UC256L4U) \ - ) - -#define UC3L3_L4 (UC3L3 || UC3L4) -/** @} */ - -/** - * \name AVR UC3 families - * @{ - */ -/** AVR UC3 A family */ -#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4) - -/** AVR UC3 B family */ -#define UC3B (UC3B0 || UC3B1) - -/** AVR UC3 C family */ -#define UC3C (UC3C0 || UC3C1 || UC3C2) - -/** AVR UC3 D family */ -#define UC3D (UC3D3 || UC3D4) - -/** AVR UC3 L family */ -#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4) -/** @} */ - -/** AVR UC3 product line */ -#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L) - -/** @} */ - -/** - * \defgroup xmega_part_macros_group AVR XMEGA parts - * @{ - */ - -/** - * \name AVR XMEGA A series - * @{ - */ -#define XMEGA_A1 ( \ - AVR8_PART_IS_DEFINED(ATxmega64A1) || \ - AVR8_PART_IS_DEFINED(ATxmega128A1) \ - ) - -#define XMEGA_A3 ( \ - AVR8_PART_IS_DEFINED(ATxmega64A3) || \ - AVR8_PART_IS_DEFINED(ATxmega128A3) || \ - AVR8_PART_IS_DEFINED(ATxmega192A3) || \ - AVR8_PART_IS_DEFINED(ATxmega256A3) \ - ) - -#define XMEGA_A3B ( \ - AVR8_PART_IS_DEFINED(ATxmega256A3B) \ - ) - -#define XMEGA_A4 ( \ - AVR8_PART_IS_DEFINED(ATxmega16A4) || \ - AVR8_PART_IS_DEFINED(ATxmega32A4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA AU series - * @{ - */ -#define XMEGA_A1U ( \ - AVR8_PART_IS_DEFINED(ATxmega64A1U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A1U) \ - ) - -#define XMEGA_A3U ( \ - AVR8_PART_IS_DEFINED(ATxmega64A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega192A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega256A3U) \ - ) - -#define XMEGA_A3BU ( \ - AVR8_PART_IS_DEFINED(ATxmega256A3BU) \ - ) - -#define XMEGA_A4U ( \ - AVR8_PART_IS_DEFINED(ATxmega16A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega32A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega64A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A4U) \ - ) -/** @} */ - -/** - * \name AVR XMEGA B series - * @{ - */ -#define XMEGA_B1 ( \ - AVR8_PART_IS_DEFINED(ATxmega64B1) || \ - AVR8_PART_IS_DEFINED(ATxmega128B1) \ - ) - -#define XMEGA_B3 ( \ - AVR8_PART_IS_DEFINED(ATxmega64B3) || \ - AVR8_PART_IS_DEFINED(ATxmega128B3) \ - ) -/** @} */ - -/** - * \name AVR XMEGA C series - * @{ - */ -#define XMEGA_C3 ( \ - AVR8_PART_IS_DEFINED(ATxmega384C3) || \ - AVR8_PART_IS_DEFINED(ATxmega256C3) || \ - AVR8_PART_IS_DEFINED(ATxmega192C3) || \ - AVR8_PART_IS_DEFINED(ATxmega128C3) || \ - AVR8_PART_IS_DEFINED(ATxmega64C3) \ - ) - -#define XMEGA_C4 ( \ - AVR8_PART_IS_DEFINED(ATxmega32C4) || \ - AVR8_PART_IS_DEFINED(ATxmega16C4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA D series - * @{ - */ -#define XMEGA_D3 ( \ - AVR8_PART_IS_DEFINED(ATxmega64D3) || \ - AVR8_PART_IS_DEFINED(ATxmega128D3) || \ - AVR8_PART_IS_DEFINED(ATxmega192D3) || \ - AVR8_PART_IS_DEFINED(ATxmega256D3) || \ - AVR8_PART_IS_DEFINED(ATxmega384D3) \ - ) - -#define XMEGA_D4 ( \ - AVR8_PART_IS_DEFINED(ATxmega16D4) || \ - AVR8_PART_IS_DEFINED(ATxmega32D4) || \ - AVR8_PART_IS_DEFINED(ATxmega64D4) || \ - AVR8_PART_IS_DEFINED(ATxmega128D4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA E series - * @{ - */ -#define XMEGA_E5 ( \ - AVR8_PART_IS_DEFINED(ATxmega8E5) || \ - AVR8_PART_IS_DEFINED(ATxmega16E5) || \ - AVR8_PART_IS_DEFINED(ATxmega32E5) \ - ) -/** @} */ - - -/** - * \name AVR XMEGA families - * @{ - */ -/** AVR XMEGA A family */ -#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4) - -/** AVR XMEGA AU family */ -#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U) - -/** AVR XMEGA B family */ -#define XMEGA_B (XMEGA_B1 || XMEGA_B3) - -/** AVR XMEGA C family */ -#define XMEGA_C (XMEGA_C3 || XMEGA_C4) - -/** AVR XMEGA D family */ -#define XMEGA_D (XMEGA_D3 || XMEGA_D4) - -/** AVR XMEGA E family */ -#define XMEGA_E (XMEGA_E5) -/** @} */ - - -/** AVR XMEGA product line */ -#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E) - -/** @} */ - -/** - * \defgroup mega_part_macros_group megaAVR parts - * - * \note These megaAVR groupings are based on the groups in AVR Libc for the - * part header files. They are not names of official megaAVR device series or - * families. - * - * @{ - */ - -/** - * \name ATmegaxx0/xx1 subgroups - * @{ - */ -#define MEGA_XX0 ( \ - AVR8_PART_IS_DEFINED(ATmega640) || \ - AVR8_PART_IS_DEFINED(ATmega1280) || \ - AVR8_PART_IS_DEFINED(ATmega2560) \ - ) - -#define MEGA_XX1 ( \ - AVR8_PART_IS_DEFINED(ATmega1281) || \ - AVR8_PART_IS_DEFINED(ATmega2561) \ - ) -/** @} */ - -/** - * \name megaAVR groups - * @{ - */ -/** ATmegaxx0/xx1 group */ -#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1) - -/** ATmegaxx4 group */ -#define MEGA_XX4 ( \ - AVR8_PART_IS_DEFINED(ATmega164A) || \ - AVR8_PART_IS_DEFINED(ATmega164PA) || \ - AVR8_PART_IS_DEFINED(ATmega324A) || \ - AVR8_PART_IS_DEFINED(ATmega324PA) || \ - AVR8_PART_IS_DEFINED(ATmega644) || \ - AVR8_PART_IS_DEFINED(ATmega644A) || \ - AVR8_PART_IS_DEFINED(ATmega644PA) || \ - AVR8_PART_IS_DEFINED(ATmega1284P) || \ - AVR8_PART_IS_DEFINED(ATmega128RFA1) \ - ) - -/** ATmegaxx4 group */ -#define MEGA_XX4_A ( \ - AVR8_PART_IS_DEFINED(ATmega164A) || \ - AVR8_PART_IS_DEFINED(ATmega164PA) || \ - AVR8_PART_IS_DEFINED(ATmega324A) || \ - AVR8_PART_IS_DEFINED(ATmega324PA) || \ - AVR8_PART_IS_DEFINED(ATmega644A) || \ - AVR8_PART_IS_DEFINED(ATmega644PA) || \ - AVR8_PART_IS_DEFINED(ATmega1284P) \ - ) - -/** ATmegaxx8 group */ -#define MEGA_XX8 ( \ - AVR8_PART_IS_DEFINED(ATmega48) || \ - AVR8_PART_IS_DEFINED(ATmega48A) || \ - AVR8_PART_IS_DEFINED(ATmega48PA) || \ - AVR8_PART_IS_DEFINED(ATmega88) || \ - AVR8_PART_IS_DEFINED(ATmega88A) || \ - AVR8_PART_IS_DEFINED(ATmega88PA) || \ - AVR8_PART_IS_DEFINED(ATmega168) || \ - AVR8_PART_IS_DEFINED(ATmega168A) || \ - AVR8_PART_IS_DEFINED(ATmega168PA) || \ - AVR8_PART_IS_DEFINED(ATmega328) || \ - AVR8_PART_IS_DEFINED(ATmega328P) \ - ) - -/** ATmegaxx8A/P/PA group */ -#define MEGA_XX8_A ( \ - AVR8_PART_IS_DEFINED(ATmega48A) || \ - AVR8_PART_IS_DEFINED(ATmega48PA) || \ - AVR8_PART_IS_DEFINED(ATmega88A) || \ - AVR8_PART_IS_DEFINED(ATmega88PA) || \ - AVR8_PART_IS_DEFINED(ATmega168A) || \ - AVR8_PART_IS_DEFINED(ATmega168PA) || \ - AVR8_PART_IS_DEFINED(ATmega328P) \ - ) - -/** ATmegaxx group */ -#define MEGA_XX ( \ - AVR8_PART_IS_DEFINED(ATmega16) || \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32) || \ - AVR8_PART_IS_DEFINED(ATmega32A) || \ - AVR8_PART_IS_DEFINED(ATmega64) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) - -/** ATmegaxxA/P/PA group */ -#define MEGA_XX_A ( \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32A) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) -/** ATmegaxxRFA1 group */ -#define MEGA_RFA1 ( \ - AVR8_PART_IS_DEFINED(ATmega128RFA1) \ - ) - -/** ATmegaxxRFR2 group */ -#define MEGA_RFR2 ( \ - AVR8_PART_IS_DEFINED(ATmega64RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega128RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega256RFR2) \ - ) - - -/** ATmegaxxRFxx group */ -#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2) - -/** - * \name ATmegaxx_un0/un1/un2 subgroups - * @{ - */ -#define MEGA_XX_UN0 ( \ - AVR8_PART_IS_DEFINED(ATmega16) || \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32) || \ - AVR8_PART_IS_DEFINED(ATmega32A) \ - ) - -/** ATmegaxx group without power reduction and - * And interrupt sense register. - */ -#define MEGA_XX_UN1 ( \ - AVR8_PART_IS_DEFINED(ATmega64) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) - -/** ATmegaxx group without power reduction and - * And interrupt sense register. - */ -#define MEGA_XX_UN2 ( \ - AVR8_PART_IS_DEFINED(ATmega169P) || \ - AVR8_PART_IS_DEFINED(ATmega169PA) || \ - AVR8_PART_IS_DEFINED(ATmega329P) || \ - AVR8_PART_IS_DEFINED(ATmega329PA) \ - ) - -/** Devices added to complete megaAVR offering. - * Please do not use this group symbol as it is not intended - * to be permanent: the devices should be regrouped. - */ -#define MEGA_UNCATEGORIZED ( \ - AVR8_PART_IS_DEFINED(AT90CAN128) || \ - AVR8_PART_IS_DEFINED(AT90CAN32) || \ - AVR8_PART_IS_DEFINED(AT90CAN64) || \ - AVR8_PART_IS_DEFINED(AT90PWM1) || \ - AVR8_PART_IS_DEFINED(AT90PWM216) || \ - AVR8_PART_IS_DEFINED(AT90PWM2B) || \ - AVR8_PART_IS_DEFINED(AT90PWM316) || \ - AVR8_PART_IS_DEFINED(AT90PWM3B) || \ - AVR8_PART_IS_DEFINED(AT90PWM81) || \ - AVR8_PART_IS_DEFINED(AT90USB1286) || \ - AVR8_PART_IS_DEFINED(AT90USB1287) || \ - AVR8_PART_IS_DEFINED(AT90USB162) || \ - AVR8_PART_IS_DEFINED(AT90USB646) || \ - AVR8_PART_IS_DEFINED(AT90USB647) || \ - AVR8_PART_IS_DEFINED(AT90USB82) || \ - AVR8_PART_IS_DEFINED(ATmega1284) || \ - AVR8_PART_IS_DEFINED(ATmega162) || \ - AVR8_PART_IS_DEFINED(ATmega164P) || \ - AVR8_PART_IS_DEFINED(ATmega165A) || \ - AVR8_PART_IS_DEFINED(ATmega165P) || \ - AVR8_PART_IS_DEFINED(ATmega165PA) || \ - AVR8_PART_IS_DEFINED(ATmega168P) || \ - AVR8_PART_IS_DEFINED(ATmega169A) || \ - AVR8_PART_IS_DEFINED(ATmega16M1) || \ - AVR8_PART_IS_DEFINED(ATmega16U2) || \ - AVR8_PART_IS_DEFINED(ATmega16U4) || \ - AVR8_PART_IS_DEFINED(ATmega2564RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega256RFA2) || \ - AVR8_PART_IS_DEFINED(ATmega324P) || \ - AVR8_PART_IS_DEFINED(ATmega325) || \ - AVR8_PART_IS_DEFINED(ATmega3250) || \ - AVR8_PART_IS_DEFINED(ATmega3250A) || \ - AVR8_PART_IS_DEFINED(ATmega3250P) || \ - AVR8_PART_IS_DEFINED(ATmega3250PA) || \ - AVR8_PART_IS_DEFINED(ATmega325A) || \ - AVR8_PART_IS_DEFINED(ATmega325P) || \ - AVR8_PART_IS_DEFINED(ATmega325PA) || \ - AVR8_PART_IS_DEFINED(ATmega329) || \ - AVR8_PART_IS_DEFINED(ATmega3290) || \ - AVR8_PART_IS_DEFINED(ATmega3290A) || \ - AVR8_PART_IS_DEFINED(ATmega3290P) || \ - AVR8_PART_IS_DEFINED(ATmega3290PA) || \ - AVR8_PART_IS_DEFINED(ATmega329A) || \ - AVR8_PART_IS_DEFINED(ATmega32M1) || \ - AVR8_PART_IS_DEFINED(ATmega32U2) || \ - AVR8_PART_IS_DEFINED(ATmega32U4) || \ - AVR8_PART_IS_DEFINED(ATmega48P) || \ - AVR8_PART_IS_DEFINED(ATmega644P) || \ - AVR8_PART_IS_DEFINED(ATmega645) || \ - AVR8_PART_IS_DEFINED(ATmega6450) || \ - AVR8_PART_IS_DEFINED(ATmega6450A) || \ - AVR8_PART_IS_DEFINED(ATmega6450P) || \ - AVR8_PART_IS_DEFINED(ATmega645A) || \ - AVR8_PART_IS_DEFINED(ATmega645P) || \ - AVR8_PART_IS_DEFINED(ATmega649) || \ - AVR8_PART_IS_DEFINED(ATmega6490) || \ - AVR8_PART_IS_DEFINED(ATmega6490A) || \ - AVR8_PART_IS_DEFINED(ATmega6490P) || \ - AVR8_PART_IS_DEFINED(ATmega649A) || \ - AVR8_PART_IS_DEFINED(ATmega649P) || \ - AVR8_PART_IS_DEFINED(ATmega64M1) || \ - AVR8_PART_IS_DEFINED(ATmega64RFA2) || \ - AVR8_PART_IS_DEFINED(ATmega8) || \ - AVR8_PART_IS_DEFINED(ATmega8515) || \ - AVR8_PART_IS_DEFINED(ATmega8535) || \ - AVR8_PART_IS_DEFINED(ATmega88P) || \ - AVR8_PART_IS_DEFINED(ATmega8A) || \ - AVR8_PART_IS_DEFINED(ATmega8U2) \ - ) - -/** Unspecified group */ -#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \ - MEGA_UNCATEGORIZED) - -/** @} */ - -/** megaAVR product line */ -#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \ - MEGA_UNSPECIFIED) - -/** @} */ - -/** - * \defgroup tiny_part_macros_group tinyAVR parts - * - * @{ - */ - -/** - * \name tinyAVR groups - * @{ - */ - -/** Devices added to complete tinyAVR offering. - * Please do not use this group symbol as it is not intended - * to be permanent: the devices should be regrouped. - */ -#define TINY_UNCATEGORIZED ( \ - AVR8_PART_IS_DEFINED(ATtiny10) || \ - AVR8_PART_IS_DEFINED(ATtiny13) || \ - AVR8_PART_IS_DEFINED(ATtiny13A) || \ - AVR8_PART_IS_DEFINED(ATtiny1634) || \ - AVR8_PART_IS_DEFINED(ATtiny167) || \ - AVR8_PART_IS_DEFINED(ATtiny20) || \ - AVR8_PART_IS_DEFINED(ATtiny2313) || \ - AVR8_PART_IS_DEFINED(ATtiny2313A) || \ - AVR8_PART_IS_DEFINED(ATtiny24) || \ - AVR8_PART_IS_DEFINED(ATtiny24A) || \ - AVR8_PART_IS_DEFINED(ATtiny25) || \ - AVR8_PART_IS_DEFINED(ATtiny26) || \ - AVR8_PART_IS_DEFINED(ATtiny261) || \ - AVR8_PART_IS_DEFINED(ATtiny261A) || \ - AVR8_PART_IS_DEFINED(ATtiny4) || \ - AVR8_PART_IS_DEFINED(ATtiny40) || \ - AVR8_PART_IS_DEFINED(ATtiny4313) || \ - AVR8_PART_IS_DEFINED(ATtiny43U) || \ - AVR8_PART_IS_DEFINED(ATtiny44) || \ - AVR8_PART_IS_DEFINED(ATtiny44A) || \ - AVR8_PART_IS_DEFINED(ATtiny45) || \ - AVR8_PART_IS_DEFINED(ATtiny461) || \ - AVR8_PART_IS_DEFINED(ATtiny461A) || \ - AVR8_PART_IS_DEFINED(ATtiny48) || \ - AVR8_PART_IS_DEFINED(ATtiny5) || \ - AVR8_PART_IS_DEFINED(ATtiny828) || \ - AVR8_PART_IS_DEFINED(ATtiny84) || \ - AVR8_PART_IS_DEFINED(ATtiny84A) || \ - AVR8_PART_IS_DEFINED(ATtiny85) || \ - AVR8_PART_IS_DEFINED(ATtiny861) || \ - AVR8_PART_IS_DEFINED(ATtiny861A) || \ - AVR8_PART_IS_DEFINED(ATtiny87) || \ - AVR8_PART_IS_DEFINED(ATtiny88) || \ - AVR8_PART_IS_DEFINED(ATtiny9) \ - ) - -/** @} */ - -/** tinyAVR product line */ -#define TINY (TINY_UNCATEGORIZED) - -/** @} */ - -/** - * \defgroup sam_part_macros_group SAM parts - * @{ - */ - -/** - * \name SAM3S series - * @{ - */ -#define SAM3S1 ( \ - SAM_PART_IS_DEFINED(SAM3S1A) || \ - SAM_PART_IS_DEFINED(SAM3S1B) || \ - SAM_PART_IS_DEFINED(SAM3S1C) \ - ) - -#define SAM3S2 ( \ - SAM_PART_IS_DEFINED(SAM3S2A) || \ - SAM_PART_IS_DEFINED(SAM3S2B) || \ - SAM_PART_IS_DEFINED(SAM3S2C) \ - ) - -#define SAM3S4 ( \ - SAM_PART_IS_DEFINED(SAM3S4A) || \ - SAM_PART_IS_DEFINED(SAM3S4B) || \ - SAM_PART_IS_DEFINED(SAM3S4C) \ - ) - -#define SAM3S8 ( \ - SAM_PART_IS_DEFINED(SAM3S8B) || \ - SAM_PART_IS_DEFINED(SAM3S8C) \ - ) - -#define SAM3SD8 ( \ - SAM_PART_IS_DEFINED(SAM3SD8B) || \ - SAM_PART_IS_DEFINED(SAM3SD8C) \ - ) -/** @} */ - -/** - * \name SAM3U series - * @{ - */ -#define SAM3U1 ( \ - SAM_PART_IS_DEFINED(SAM3U1C) || \ - SAM_PART_IS_DEFINED(SAM3U1E) \ - ) - -#define SAM3U2 ( \ - SAM_PART_IS_DEFINED(SAM3U2C) || \ - SAM_PART_IS_DEFINED(SAM3U2E) \ - ) - -#define SAM3U4 ( \ - SAM_PART_IS_DEFINED(SAM3U4C) || \ - SAM_PART_IS_DEFINED(SAM3U4E) \ - ) -/** @} */ - -/** - * \name SAM3N series - * @{ - */ -#define SAM3N1 ( \ - SAM_PART_IS_DEFINED(SAM3N1A) || \ - SAM_PART_IS_DEFINED(SAM3N1B) || \ - SAM_PART_IS_DEFINED(SAM3N1C) \ - ) - -#define SAM3N2 ( \ - SAM_PART_IS_DEFINED(SAM3N2A) || \ - SAM_PART_IS_DEFINED(SAM3N2B) || \ - SAM_PART_IS_DEFINED(SAM3N2C) \ - ) - -#define SAM3N4 ( \ - SAM_PART_IS_DEFINED(SAM3N4A) || \ - SAM_PART_IS_DEFINED(SAM3N4B) || \ - SAM_PART_IS_DEFINED(SAM3N4C) \ - ) -/** @} */ - -/** - * \name SAM3X series - * @{ - */ -#define SAM3X4 ( \ - SAM_PART_IS_DEFINED(SAM3X4C) || \ - SAM_PART_IS_DEFINED(SAM3X4E) \ - ) - -#define SAM3X8 ( \ - SAM_PART_IS_DEFINED(SAM3X8C) || \ - SAM_PART_IS_DEFINED(SAM3X8E) || \ - SAM_PART_IS_DEFINED(SAM3X8H) \ - ) -/** @} */ - -/** - * \name SAM3A series - * @{ - */ -#define SAM3A4 ( \ - SAM_PART_IS_DEFINED(SAM3A4C) \ - ) - -#define SAM3A8 ( \ - SAM_PART_IS_DEFINED(SAM3A8C) \ - ) -/** @} */ - -/** - * \name SAM4S series - * @{ - */ -#define SAM4S8 ( \ - SAM_PART_IS_DEFINED(SAM4S8B) || \ - SAM_PART_IS_DEFINED(SAM4S8C) \ - ) - -#define SAM4S16 ( \ - SAM_PART_IS_DEFINED(SAM4S16B) || \ - SAM_PART_IS_DEFINED(SAM4S16C) \ - ) - -#define SAM4SA16 ( \ - SAM_PART_IS_DEFINED(SAM4SA16B) || \ - SAM_PART_IS_DEFINED(SAM4SA16C) \ - ) - -#define SAM4SD16 ( \ - SAM_PART_IS_DEFINED(SAM4SD16B) || \ - SAM_PART_IS_DEFINED(SAM4SD16C) \ - ) - -#define SAM4SD32 ( \ - SAM_PART_IS_DEFINED(SAM4SD32B) || \ - SAM_PART_IS_DEFINED(SAM4SD32C) \ - ) -/** @} */ - -/** - * \name SAM4L series - * @{ - */ -#define SAM4LS ( \ - SAM_PART_IS_DEFINED(SAM4LS2A) || \ - SAM_PART_IS_DEFINED(SAM4LS2B) || \ - SAM_PART_IS_DEFINED(SAM4LS2C) || \ - SAM_PART_IS_DEFINED(SAM4LS4A) || \ - SAM_PART_IS_DEFINED(SAM4LS4B) || \ - SAM_PART_IS_DEFINED(SAM4LS4C) || \ - SAM_PART_IS_DEFINED(SAM4LS8A) || \ - SAM_PART_IS_DEFINED(SAM4LS8B) || \ - SAM_PART_IS_DEFINED(SAM4LS8C) \ - ) - -#define SAM4LC ( \ - SAM_PART_IS_DEFINED(SAM4LC2A) || \ - SAM_PART_IS_DEFINED(SAM4LC2B) || \ - SAM_PART_IS_DEFINED(SAM4LC2C) || \ - SAM_PART_IS_DEFINED(SAM4LC4A) || \ - SAM_PART_IS_DEFINED(SAM4LC4B) || \ - SAM_PART_IS_DEFINED(SAM4LC4C) || \ - SAM_PART_IS_DEFINED(SAM4LC8A) || \ - SAM_PART_IS_DEFINED(SAM4LC8B) || \ - SAM_PART_IS_DEFINED(SAM4LC8C) \ - ) -/** @} */ - -/** - * \name SAMD20 series - * @{ - */ -#define SAMD20J ( \ - SAM_PART_IS_DEFINED(SAMD20J14) || \ - SAM_PART_IS_DEFINED(SAMD20J15) || \ - SAM_PART_IS_DEFINED(SAMD20J16) || \ - SAM_PART_IS_DEFINED(SAMD20J17) || \ - SAM_PART_IS_DEFINED(SAMD20J18) \ - ) - -#define SAMD20G ( \ - SAM_PART_IS_DEFINED(SAMD20G14) || \ - SAM_PART_IS_DEFINED(SAMD20G15) || \ - SAM_PART_IS_DEFINED(SAMD20G16) || \ - SAM_PART_IS_DEFINED(SAMD20G17) || \ - SAM_PART_IS_DEFINED(SAMD20G18) \ - ) - -#define SAMD20E ( \ - SAM_PART_IS_DEFINED(SAMD20E14) || \ - SAM_PART_IS_DEFINED(SAMD20E15) || \ - SAM_PART_IS_DEFINED(SAMD20E16) || \ - SAM_PART_IS_DEFINED(SAMD20E17) || \ - SAM_PART_IS_DEFINED(SAMD20E18) \ - ) -/** @} */ - -/** - * \name SAM4E series - * @{ - */ -#define SAM4E8 ( \ - SAM_PART_IS_DEFINED(SAM4E8E) \ - ) - -#define SAM4E16 ( \ - SAM_PART_IS_DEFINED(SAM4E16E) \ - ) -/** @} */ - -/** - * \name SAM4N series - * @{ - */ -#define SAM4N8 ( \ - SAM_PART_IS_DEFINED(SAM4N8A) || \ - SAM_PART_IS_DEFINED(SAM4N8B) || \ - SAM_PART_IS_DEFINED(SAM4N8C) \ - ) - -#define SAM4N16 ( \ - SAM_PART_IS_DEFINED(SAM4N16B) || \ - SAM_PART_IS_DEFINED(SAM4N16C) \ - ) -/** @} */ - -/** - * \name SAM families - * @{ - */ -/** SAM3S Family */ -#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8) - -/** SAM3U Family */ -#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4) - -/** SAM3N Family */ -#define SAM3N (SAM3N1 || SAM3N2 || SAM3N4) - -/** SAM3XA Family */ -#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8) - -/** SAM4S Family */ -#define SAM4S (SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32) - -/** SAM4L Family */ -#define SAM4L (SAM4LS || SAM4LC) - -/** SAMD20 Family */ -#define SAMD20 (SAMD20J || SAMD20G || SAMD20E) -/** @} */ - -/** SAM4E Family */ -#define SAM4E (SAM4E8 || SAM4E16) - -/** SAM4N Family */ -#define SAM4N (SAM4N8 || SAM4N16) - -/** @} */ - -/** SAM product line */ -#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || SAMD20 || SAM4N) - -/** @} */ - -/** @} */ - -/** @} */ - -#endif /* ATMEL_PARTS_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/init.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/init.c deleted file mode 100644 index f6dff4635..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/init.c +++ /dev/null @@ -1,370 +0,0 @@ -/** - * \file - * - * \brief SAM4E-EK board init. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "compiler.h" -#include "board.h" -#include "conf_board.h" -#include "ioport.h" - -/** - * \brief Set peripheral mode for IOPORT pins. - * It will configure port mode and disable pin mode (but enable peripheral). - * \param port IOPORT port to configure - * \param masks IOPORT pin masks to configure - * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) - */ -#define ioport_set_port_peripheral_mode(port, masks, mode) \ - do {\ - ioport_set_port_mode(port, masks, mode);\ - ioport_disable_port(port, masks);\ - } while (0) - -/** - * \brief Set peripheral mode for one single IOPORT pin. - * It will configure port mode and disable pin mode (but enable peripheral). - * \param pin IOPORT pin to configure - * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) - */ -#define ioport_set_pin_peripheral_mode(pin, mode) \ - do {\ - ioport_set_pin_mode(pin, mode);\ - ioport_disable_pin(pin);\ - } while (0) - -/** - * \brief Set input mode for one single IOPORT pin. - * It will configure port mode and disable pin mode (but enable peripheral). - * \param pin IOPORT pin to configure - * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) - * \param sense Sense for interrupt detection (\ref ioport_sense) - */ -#define ioport_set_pin_input_mode(pin, mode, sense) \ - do {\ - ioport_set_pin_dir(pin, IOPORT_DIR_INPUT);\ - ioport_set_pin_mode(pin, mode);\ - ioport_set_pin_sense_mode(pin, sense);\ - } while (0) - -void board_init(void) -{ -#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT - /* Disable the watchdog */ - WDT->WDT_MR = WDT_MR_WDDIS; -#endif - - /* Initialize IOPORTs */ - ioport_init(); - - /* Configure the pins connected to LEDs as output and set their - * default initial state to high (LEDs off). - */ - ioport_set_pin_dir(LED0_GPIO, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(LED0_GPIO, LED0_INACTIVE_LEVEL); - ioport_set_pin_dir(LED1_GPIO, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(LED1_GPIO, LED0_INACTIVE_LEVEL); - ioport_set_pin_dir(LED2_GPIO, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(LED2_GPIO, LED0_INACTIVE_LEVEL); - - /* Configure Push Button pins */ - ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS, - GPIO_PUSH_BUTTON_1_SENSE); - ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS, - GPIO_PUSH_BUTTON_2_SENSE); - ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_3, GPIO_PUSH_BUTTON_3_FLAGS, - GPIO_PUSH_BUTTON_3_SENSE); - ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_4, GPIO_PUSH_BUTTON_4_FLAGS, - GPIO_PUSH_BUTTON_4_SENSE); - -#ifdef CONF_BOARD_UART_CONSOLE - /* Configure UART pins */ - ioport_set_port_peripheral_mode(PINS_UART0_PORT, PINS_UART0, - PINS_UART0_MASK); -#endif - -#ifdef CONF_BOARD_PWM_LED0 - /* Configure PWM LED0 pin */ - ioport_set_pin_peripheral_mode(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS); -#endif - -#ifdef CONF_BOARD_PWM_LED1 - /* Configure PWM LED1 pin */ - ioport_set_pin_peripheral_mode(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS); -#endif - -#ifdef CONF_BOARD_PWM_LED2 - /* Configure PWM LED2 pin */ - ioport_set_pin_peripheral_mode(PIN_PWM_LED2_GPIO, PIN_PWM_LED2_FLAGS); -#endif - -#ifdef CONF_BOARD_PWM_LED3 - /* Configure PWM LED3 pin */ - ioport_set_pin_peripheral_mode(PIN_PWM_LED3_GPIO, PIN_PWM_LED3_FLAGS); -#endif - -#ifdef CONF_BOARD_USART_RXD - /* Configure USART RXD pin */ - ioport_set_pin_peripheral_mode(PIN_USART1_RXD_IDX, - PIN_USART1_RXD_FLAGS); -#endif - -#ifdef CONF_BOARD_USART_TXD - /* Configure USART TXD pin */ - ioport_set_pin_peripheral_mode(PIN_USART1_TXD_IDX, - PIN_USART1_TXD_FLAGS); -#endif - -#ifdef CONF_BOARD_USART_CTS - /* Configure USART CTS pin */ - ioport_set_pin_peripheral_mode(PIN_USART1_CTS_IDX, - PIN_USART1_CTS_FLAGS); -#endif - -#ifdef CONF_BOARD_USART_RTS - /* Configure USART RTS pin */ - ioport_set_pin_peripheral_mode(PIN_USART1_RTS_IDX, - PIN_USART1_RTS_FLAGS); -#endif - -#ifdef CONF_BOARD_USART_SCK - /* Configure USART synchronous communication SCK pin */ - ioport_set_pin_peripheral_mode(PIN_USART1_SCK_IDX, - PIN_USART1_SCK_FLAGS); -#endif - -#ifdef CONF_BOARD_ADM3312_EN - /* Configure ADM3312 enable pin */ - ioport_set_pin_dir(PIN_USART1_EN_IDX, IOPORT_DIR_OUTPUT); -#ifdef CONF_BOARD_ADM3312_EN_DISABLE_AT_INIT - ioport_set_pin_level(PIN_USART1_EN_IDX, PIN_USART1_EN_INACTIVE_LEVEL); -#else - ioport_set_pin_level(PIN_USART1_EN_IDX, PIN_USART1_EN_ACTIVE_LEVEL); -#endif -#endif - -#ifdef CONF_BOARD_ADS7843 - /* Configure Touchscreen SPI pins */ - ioport_set_pin_dir(BOARD_ADS7843_IRQ_GPIO, IOPORT_DIR_INPUT); - ioport_set_pin_mode(BOARD_ADS7843_IRQ_GPIO, BOARD_ADS7843_IRQ_FLAGS); - ioport_set_pin_dir(BOARD_ADS7843_BUSY_GPIO, IOPORT_DIR_INPUT); - ioport_set_pin_mode(BOARD_ADS7843_BUSY_GPIO, BOARD_ADS7843_BUSY_FLAGS); - ioport_set_pin_peripheral_mode(SPI_MISO_GPIO, SPI_MISO_FLAGS); - ioport_set_pin_peripheral_mode(SPI_MOSI_GPIO, SPI_MOSI_FLAGS); - ioport_set_pin_peripheral_mode(SPI_SPCK_GPIO, SPI_SPCK_FLAGS); - ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS); -#endif - -#ifdef CONF_BOARD_CAN0 - /* Configure the CAN0 TX and RX pins. */ - ioport_set_pin_peripheral_mode(PIN_CAN0_RX_IDX, PIN_CAN0_RX_FLAGS); - ioport_set_pin_peripheral_mode(PIN_CAN0_TX_IDX, PIN_CAN0_TX_FLAGS); - /* Configure the transiver0 RS & EN pins. */ - ioport_set_pin_dir(PIN_CAN0_TR_RS_IDX, IOPORT_DIR_OUTPUT); - ioport_set_pin_dir(PIN_CAN0_TR_EN_IDX, IOPORT_DIR_OUTPUT); -#endif - -#ifdef CONF_BOARD_CAN1 - /* Configure the CAN1 TX and RX pin. */ - ioport_set_pin_peripheral_mode(PIN_CAN1_RX_IDX, PIN_CAN1_RX_FLAGS); - ioport_set_pin_peripheral_mode(PIN_CAN1_TX_IDX, PIN_CAN1_TX_FLAGS); - /* Configure the transiver1 RS & EN pins. */ - ioport_set_pin_dir(PIN_CAN1_TR_RS_IDX, IOPORT_DIR_OUTPUT); - ioport_set_pin_dir(PIN_CAN1_TR_EN_IDX, IOPORT_DIR_OUTPUT); -#endif - -#if defined(CONF_BOARD_USB_PORT) -# if defined(CONF_BOARD_USB_VBUS_DETECT) - gpio_configure_pin(USB_VBUS_PIN, USB_VBUS_FLAGS); -# endif -#endif - -#ifdef CONF_BOARD_ILI93XX - /* Configure LCD EBI pins */ - ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D0,PIN_EBI_DATA_BUS_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D1,PIN_EBI_DATA_BUS_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D2,PIN_EBI_DATA_BUS_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D3,PIN_EBI_DATA_BUS_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D4,PIN_EBI_DATA_BUS_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D5,PIN_EBI_DATA_BUS_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D6,PIN_EBI_DATA_BUS_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D7,PIN_EBI_DATA_BUS_FLAGS); - - ioport_set_pin_peripheral_mode(PIN_EBI_NRD,PIN_EBI_NRD_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NWE,PIN_EBI_NWE_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NCS1,PIN_EBI_NCS1_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_LCD_RS,PIN_EBI_LCD_RS_FLAGS); -#endif - -#ifdef CONF_BOARD_AAT3155 - /* Configure Backlight control pin */ - ioport_set_pin_dir(BOARD_AAT31XX_SET_GPIO, IOPORT_DIR_OUTPUT); -#endif - -#ifdef CONF_BOARD_SPI - ioport_set_pin_peripheral_mode(SPI_MISO_GPIO, SPI_MISO_FLAGS); - ioport_set_pin_peripheral_mode(SPI_MOSI_GPIO, SPI_MOSI_FLAGS); - ioport_set_pin_peripheral_mode(SPI_SPCK_GPIO, SPI_SPCK_FLAGS); - -#ifdef CONF_BOARD_SPI_NPCS0 - ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS); -#endif - -#ifdef CONF_BOARD_SPI_NPCS3 -#if defined(CONF_BOARD_SPI_NPCS3_GPIO) && defined(CONF_BOARD_SPI_NPCS3_FLAGS) - ioport_set_pin_peripheral_mode(CONF_BOARD_SPI_NPCS3_GPIO, - CONF_BOARD_SPI_NPCS3_FLAGS); -#else - ioport_set_pin_peripheral_mode(SPI_NPCS3_PA5_GPIO, SPI_NPCS3_PA5_FLAGS); -#endif -#endif -#endif - -#if (defined(CONF_BOARD_TWI0) || defined(CONF_BOARD_QTOUCH)) - ioport_set_pin_peripheral_mode(TWI0_DATA_GPIO, TWI0_DATA_FLAGS); - ioport_set_pin_peripheral_mode(TWI0_CLK_GPIO, TWI0_CLK_FLAGS); -#endif - -#if defined (CONF_BOARD_SD_MMC_HSMCI) - /* Configure HSMCI pins */ - ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCDA_GPIO, PIN_HSMCI_MCCDA_FLAGS); - ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCK_GPIO, PIN_HSMCI_MCCK_FLAGS); - ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA0_GPIO, PIN_HSMCI_MCDA0_FLAGS); - ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA1_GPIO, PIN_HSMCI_MCDA1_FLAGS); - ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA2_GPIO, PIN_HSMCI_MCDA2_FLAGS); - ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA3_GPIO, PIN_HSMCI_MCDA3_FLAGS); - - /* Configure SD/MMC card detect pin */ - ioport_set_pin_peripheral_mode(SD_MMC_0_CD_GPIO, SD_MMC_0_CD_FLAGS); -#endif - -#ifdef CONF_BOARD_TWI1 - ioport_set_pin_peripheral_mode(TWI1_DATA_GPIO, TWI1_DATA_FLAGS); - ioport_set_pin_peripheral_mode(TWI1_CLK_GPIO, TWI1_CLK_FLAGS); -#endif - -#ifdef CONF_BOARD_KSZ8051MNL - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXC_IDX, - PIN_KSZ8051MNL_RXC_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXC_IDX, - PIN_KSZ8051MNL_TXC_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXEN_IDX, - PIN_KSZ8051MNL_TXEN_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXD3_IDX, - PIN_KSZ8051MNL_TXD3_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXD2_IDX, - PIN_KSZ8051MNL_TXD2_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXD1_IDX, - PIN_KSZ8051MNL_TXD1_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXD0_IDX, - PIN_KSZ8051MNL_TXD0_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXD3_IDX, - PIN_KSZ8051MNL_RXD3_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXD2_IDX, - PIN_KSZ8051MNL_RXD2_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXD1_IDX, - PIN_KSZ8051MNL_RXD1_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXD0_IDX, - PIN_KSZ8051MNL_RXD0_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXER_IDX, - PIN_KSZ8051MNL_RXER_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXDV_IDX, - PIN_KSZ8051MNL_RXDV_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_CRS_IDX, - PIN_KSZ8051MNL_CRS_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_COL_IDX, - PIN_KSZ8051MNL_COL_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_MDC_IDX, - PIN_KSZ8051MNL_MDC_FLAGS); - ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_MDIO_IDX, - PIN_KSZ8051MNL_MDIO_FLAGS); - ioport_set_pin_dir(PIN_KSZ8051MNL_INTRP_IDX, IOPORT_DIR_INPUT); -#endif - -#ifdef CONF_BOARD_TFDU4300_SD - /* Configure IrDA transceiver shutdown pin */ - ioport_set_pin_dir(PIN_IRDA_SD_IDX, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(PIN_IRDA_SD_IDX, IOPORT_PIN_LEVEL_HIGH); -#endif - -#ifdef CONF_BOARD_ADM3485_RE - /* Configure RS485 transceiver RE pin */ - ioport_set_pin_dir(PIN_RE_IDX, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(PIN_RE_IDX, IOPORT_PIN_LEVEL_LOW); -#endif - -#ifdef CONF_BOARD_ISO7816_RST - /* Configure ISO7816 card reset pin */ - ioport_set_pin_dir(PIN_ISO7816_RST_IDX, IOPORT_DIR_OUTPUT); - ioport_set_pin_level(PIN_ISO7816_RST_IDX, IOPORT_PIN_LEVEL_LOW); -#endif - -#ifdef CONF_BOARD_ISO7816 - /* Configure ISO7816 interface TXD & SCK pin */ - ioport_set_pin_peripheral_mode(PIN_USART1_TXD_IDX, PIN_USART1_TXD_FLAGS); - ioport_set_pin_peripheral_mode(PIN_USART1_SCK_IDX, PIN_USART1_SCK_FLAGS); -#endif - -#ifdef CONF_BOARD_NAND - ioport_set_pin_peripheral_mode(PIN_EBI_NANDOE, PIN_EBI_NANDOE_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDWE, PIN_EBI_NANDWE_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDCLE, PIN_EBI_NANDCLE_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDALE, PIN_EBI_NANDALE_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_0, PIN_EBI_NANDIO_0_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_1, PIN_EBI_NANDIO_1_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_2, PIN_EBI_NANDIO_2_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_3, PIN_EBI_NANDIO_3_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_4, PIN_EBI_NANDIO_4_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_5, PIN_EBI_NANDIO_5_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_6, PIN_EBI_NANDIO_6_FLAGS); - ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_7, PIN_EBI_NANDIO_7_FLAGS); - ioport_set_pin_dir(PIN_NF_CE_IDX, IOPORT_DIR_OUTPUT); - ioport_set_pin_dir(PIN_NF_RB_IDX, IOPORT_DIR_INPUT); - ioport_set_pin_mode(PIN_NF_RB_IDX, IOPORT_MODE_PULLUP); -#endif - - -#ifdef CONF_BOARD_QTOUCH - /* Configure CHANGE pin for QTouch device */ - ioport_set_pin_input_mode(BOARD_QT_CHANGE_PIN_IDX, BOARD_QT_CHANGE_PIN_FLAGS, - BOARD_QT_CHANGE_PIN_SENSE); -#endif -} diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/led.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/led.h deleted file mode 100644 index 22efbf248..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/led.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - * \file - * - * \brief SAM4E-EK LEDs support package. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef LED_H_INCLUDED -#define LED_H_INCLUDED - -#include "compiler.h" -#include "ioport.h" - -/** - * \brief Turns off the specified LEDs. - * - * \param led LED to turn off (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Off(led) ioport_set_pin_level(led##_GPIO, led##_INACTIVE_LEVEL) - -/** - * \brief Turns on the specified LEDs. - * - * \param led LED to turn on (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_On(led) ioport_set_pin_level(led##_GPIO, led##_ACTIVE_LEVEL) - -/** - * \brief Toggles the specified LEDs. - * - * \param led LED to toggle (LEDx_GPIO). - * - * \note The pins of the specified LEDs are set to GPIO output mode. - */ -#define LED_Toggle(led) ioport_toggle_pin_level(led##_GPIO) - - -#endif // LED_H_INCLUDED diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/sam4e_ek.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/sam4e_ek.h deleted file mode 100644 index 678c0fd6d..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/boards/sam4e_ek/sam4e_ek.h +++ /dev/null @@ -1,811 +0,0 @@ -/** - * \file - * - * \brief SAM4E-EK Board Definition. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_EK_H_ -#define _SAM4E_EK_H_ - -#include "compiler.h" -#include "system_sam4e.h" -#include "exceptions.h" - -/*----------------------------------------------------------------------------*/ -/** - * \page sam4e_ek_opfreq "SAM4E-EK - Operating frequencies" - * This page lists several definition related to the board operating frequency - * - * \section Definitions - * - \ref BOARD_FREQ_* - * - \ref BOARD_MCK - */ - -/** Board oscillator settings */ -#define BOARD_FREQ_SLCK_XTAL (32768U) -#define BOARD_FREQ_SLCK_BYPASS (32768U) -#define BOARD_FREQ_MAINCK_XTAL (12000000U) -#define BOARD_FREQ_MAINCK_BYPASS (12000000U) - -/** Master clock frequency */ -#define BOARD_MCK CHIP_FREQ_CPU_MAX - -/** board main clock xtal statup time */ -#define BOARD_OSC_STARTUP_US 15625 - -/*----------------------------------------------------------------------------*/ -/** - * \page sam4e_ek_board_info "SAM4E-EK - Board informations" - * This page lists several definition related to the board description. - * - * \section Definitions - * - \ref BOARD_NAME - */ - -/** Name of the board */ -#define BOARD_NAME "SAM4E-EK" -/** Board definition */ -#define sam4eek -/** Family definition (already defined) */ -#define sam4e -/** Core definition */ -#define cortexm4 - -/*----------------------------------------------------------------------------*/ - -/** UART0 pins (UTXD0 and URXD0) definitions, PA10,9. */ -#define PINS_UART0 (PIO_PA9A_URXD0 | PIO_PA10A_UTXD0) -#define PINS_UART0_FLAGS (IOPORT_MODE_MUX_A) - -#define PINS_UART0_PORT IOPORT_PIOA -#define PINS_UART0_MASK (PIO_PA9A_URXD0 | PIO_PA10A_UTXD0) -#define PINS_UART0_PIO PIOA -#define PINS_UART0_ID ID_PIOA -#define PINS_UART0_TYPE PIO_PERIPH_A -#define PINS_UART0_ATTR PIO_DEFAULT - -/** UART1 pins (UTXD1 and URXD1) definitions, PA6,5. */ -#define PINS_UART1 (PIO_PA6C_URXD1 | PIO_PA5C_UTXD1) -#define PINS_UART1_FLAGS (IOPORT_MODE_MUX_C) - -#define PINS_UART1_PORT IOPORT_PIOA -#define PINS_UART1_MASK (PIO_PA6C_URXD1 | PIO_PA5C_UTXD1) -#define PINS_UART1_PIO PIOA -#define PINS_UART1_ID ID_PIOA -#define PINS_UART1_TYPE PIO_PERIPH_C -#define PINS_UART1_ATTR PIO_DEFAULT - -/** LED #0 pin definition (Blue). */ -#define LED_0_NAME "Blue LED D2" -#define PIN_LED_0 {PIO_PA0, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -#define PIN_LED_0_MASK PIO_PA0 -#define PIN_LED_0_PIO PIOA -#define PIN_LED_0_ID ID_PIOA -#define PIN_LED_0_TYPE PIO_OUTPUT_1 -#define PIN_LED_0_ATTR PIO_DEFAULT - -#define LED0_GPIO (PIO_PA0_IDX) -#define LED0_FLAGS (0) -#define LED0_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW -#define LED0_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH - -/** LED #1 pin definition (Amber). */ -#define LED_1_NAME "Amber LED D3" -#define PIN_LED_1 {PIO_PD20, PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT} -#define PIN_LED_1_MASK PIO_PD20 -#define PIN_LED_1_PIO PIOD -#define PIN_LED_1_ID ID_PIOD -#define PIN_LED_1_TYPE PIO_OUTPUT_1 -#define PIN_LED_1_ATTR PIO_DEFAULT - -#define LED1_GPIO (PIO_PD20_IDX) -#define LED1_FLAGS (0) -#define LED1_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW -#define LED1_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH - -/** LED #2 pin definition (Green). */ -#define LED_2_NAME "Green LED D4" -#define PIN_LED_2_MASK PIO_PD21 -#define PIN_LED_2_PIO PIOD -#define PIN_LED_2_ID ID_PIOD -#define PIN_LED_2_TYPE PIO_OUTPUT_1 -#define PIN_LED_2_ATTR PIO_DEFAULT - -#define LED2_GPIO (PIO_PD21_IDX) -#define LED2_FLAGS (0) -#define LED2_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW -#define LED2_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH - -/** LED #3 pin definition (Red). */ -#define LED_3_NAME "Red LED D5" -#define PIN_LED_3_MASK PIO_PD22 -#define PIN_LED_3_PIO PIOD -#define PIN_LED_3_ID ID_PIOD -#define PIN_LED_3_TYPE PIO_OUTPUT_0 -#define PIN_LED_3_ATTR PIO_DEFAULT - -#define LED3_GPIO (PIO_PD22_IDX) -#define LED3_FLAGS (0) -#define LED3_ACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH -#define LED3_INACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW - -#define BOARD_NUM_OF_LED 4 - -/** HSMCI pins definition. */ -/*! Number of slot connected on HSMCI interface */ -#define SD_MMC_HSMCI_MEM_CNT 1 -#define SD_MMC_HSMCI_SLOT_0_SIZE 4 -#define PINS_HSMCI {0x3fUL << 26, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP} -/** HSMCI MCCDA pin definition. */ -#define PIN_HSMCI_MCCDA_GPIO (PIO_PA28_IDX) -#define PIN_HSMCI_MCCDA_FLAGS (IOPORT_MODE_MUX_C) -/** HSMCI MCCK pin definition. */ -#define PIN_HSMCI_MCCK_GPIO (PIO_PA29_IDX) -#define PIN_HSMCI_MCCK_FLAGS (IOPORT_MODE_MUX_C) -/** HSMCI MCDA0 pin definition. */ -#define PIN_HSMCI_MCDA0_GPIO (PIO_PA30_IDX) -#define PIN_HSMCI_MCDA0_FLAGS (IOPORT_MODE_MUX_C) -/** HSMCI MCDA1 pin definition. */ -#define PIN_HSMCI_MCDA1_GPIO (PIO_PA31_IDX) -#define PIN_HSMCI_MCDA1_FLAGS (IOPORT_MODE_MUX_C) -/** HSMCI MCDA2 pin definition. */ -#define PIN_HSMCI_MCDA2_GPIO (PIO_PA26_IDX) -#define PIN_HSMCI_MCDA2_FLAGS (IOPORT_MODE_MUX_C) -/** HSMCI MCDA3 pin definition. */ -#define PIN_HSMCI_MCDA3_GPIO (PIO_PA27_IDX) -#define PIN_HSMCI_MCDA3_FLAGS (IOPORT_MODE_MUX_C) - -/** SD/MMC card detect pin definition. */ -#define PIN_HSMCI_CD {PIO_PA6, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} -#define SD_MMC_0_CD_GPIO (PIO_PA6_IDX) -#define SD_MMC_0_CD_PIO_ID ID_PIOA -#define SD_MMC_0_CD_FLAGS (IOPORT_MODE_PULLUP) -#define SD_MMC_0_CD_DETECT_VALUE 0 - -/** - * Push button #0 definition. Attributes = pull-up + debounce + interrupt on - * rising edge. - */ -#define PUSHBUTTON_1_NAME "BP2 WAKU" -#define PUSHBUTTON_1_WKUP_LINE (9) -#define PUSHBUTTON_1_WKUP_FSTT (PMC_FSMR_FSTT9) -#define GPIO_PUSH_BUTTON_1 (PIO_PA19_IDX) -#define GPIO_PUSH_BUTTON_1_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) -#define GPIO_PUSH_BUTTON_1_SENSE (IOPORT_SENSE_RISING) - -#define PIN_PUSHBUTTON_1 {PIO_PA19, PIOA, ID_PIOA, PIO_INPUT, \ - PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define PIN_PUSHBUTTON_1_MASK PIO_PA19 -#define PIN_PUSHBUTTON_1_PIO PIOA -#define PIN_PUSHBUTTON_1_ID ID_PIOA -#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT -#define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) -#define PIN_PUSHBUTTON_1_IRQn PIOA_IRQn - -/** - * Push button #1 definition. Attributes = pull-up + debounce + interrupt on - * falling edge. - */ -#define PUSHBUTTON_2_NAME "BP3 TAMP" -#define PUSHBUTTON_2_WKUP_LINE (10) -#define PUSHBUTTON_2_WKUP_FSTT (PMC_FSMR_FSTT10) -#define GPIO_PUSH_BUTTON_2 (PIO_PA20_IDX) -#define GPIO_PUSH_BUTTON_2_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) -#define GPIO_PUSH_BUTTON_2_SENSE (IOPORT_SENSE_FALLING) - -#define PIN_PUSHBUTTON_2 {PIO_PA20, PIOA, ID_PIOA, PIO_INPUT, \ - PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} -#define PIN_PUSHBUTTON_2_MASK PIO_PA20 -#define PIN_PUSHBUTTON_2_PIO PIOA -#define PIN_PUSHBUTTON_2_ID ID_PIOA -#define PIN_PUSHBUTTON_2_TYPE PIO_INPUT -#define PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE) -#define PIN_PUSHBUTTON_2_IRQn PIOA_IRQn - -/** - * Push button #2 definition. Attributes = pull-up + debounce + interrupt on - * both edges. - */ -#define PUSHBUTTON_3_NAME "BP4 SCROLL-UP" -#define PUSHBUTTON_3_WKUP_LINE (1) -#define PUSHBUTTON_3_WKUP_FSTT (PMC_FSMR_FSTT1) -#define GPIO_PUSH_BUTTON_3 (PIO_PA1_IDX) -#define GPIO_PUSH_BUTTON_3_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) -#define GPIO_PUSH_BUTTON_3_SENSE (IOPORT_SENSE_BOTHEDGES) - -#define PIN_PUSHBUTTON_3 {PIO_PA1, PIOA, ID_PIOA, PIO_INPUT, \ - PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define PIN_PUSHBUTTON_3_MASK PIO_PA1 -#define PIN_PUSHBUTTON_3_PIO PIOA -#define PIN_PUSHBUTTON_3_ID ID_PIOA -#define PIN_PUSHBUTTON_3_TYPE PIO_INPUT -#define PIN_PUSHBUTTON_3_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) -#define PIN_PUSHBUTTON_3_IRQn PIOA_IRQn - -/** - * Push button #3 definition. Attributes = pull-up + debounce + interrupt on - * rising edge. - */ -#define PUSHBUTTON_4_NAME "BP5 SCROLL-DOWN" -#define PUSHBUTTON_4_WKUP_LINE (2) -#define PUSHBUTTON_4_WKUP_FSTT (PMC_FSMR_FSTT2) -#define GPIO_PUSH_BUTTON_4 (PIO_PA2_IDX) -#define GPIO_PUSH_BUTTON_4_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) -#define GPIO_PUSH_BUTTON_4_SENSE (IOPORT_SENSE_RISING) - -#define PIN_PUSHBUTTON_4 {PIO_PA2, PIOA, ID_PIOA, PIO_INPUT, \ - PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} -#define PIN_PUSHBUTTON_4_MASK PIO_PA2 -#define PIN_PUSHBUTTON_4_PIO PIOA -#define PIN_PUSHBUTTON_4_ID ID_PIOA -#define PIN_PUSHBUTTON_4_TYPE PIO_INPUT -#define PIN_PUSHBUTTON_4_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) -#define PIN_PUSHBUTTON_4_IRQn PIOA_IRQn - -/** List of all push button definitions. */ -#define PINS_PUSHBUTTONS {PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2,\ - PIN_PUSHBUTTON_3, PIN_PUSHBUTTON_4} - -#define PIN_TC0_TIOA0 (PIO_PA0_IDX) -#define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B) -#define PIN_TC0_TIOA0_FLAGS (IOPORT_MODE_MUX_B) - -#define PIN_TC0_TIOA1 (PIO_PA15_IDX) -#define PIN_TC0_TIOA1_MUX (IOPORT_MODE_MUX_B) -#define PIN_TC0_TIOA1_FLAGS (IOPORT_MODE_MUX_B) - -#define PIN_TC0_TIOA1_PIO PIOA -#define PIN_TC0_TIOA1_MASK PIO_PA15 -#define PIN_TC0_TIOA1_ID ID_PIOA -#define PIN_TC0_TIOA1_TYPE PIO_PERIPH_B -#define PIN_TC0_TIOA1_ATTR PIO_DEFAULT - -#define PIN_TC0_TIOA2 (PIO_PA26_IDX) -#define PIN_TC0_TIOA2_MUX (IOPORT_MODE_MUX_B) -#define PIN_TC0_TIOA2_FLAGS (IOPORT_MODE_MUX_B) - -#define PIN_TC0_TIOA2_PIO PIOA -#define PIN_TC0_TIOA2_MASK PIO_PA26 -#define PIN_TC0_TIOA2_ID ID_PIOA -#define PIN_TC0_TIOA2_TYPE PIO_PERIPH_B -#define PIN_TC0_TIOA2_ATTR PIO_DEFAULT - -/** PWM LED0 pin definitions. */ -#define PIN_PWM_LED0_GPIO PIO_PD20_IDX -#define PIN_PWM_LED0_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_0 - -/** PWM LED1 pin definitions. */ -#define PIN_PWM_LED1_GPIO PIO_PD21_IDX -#define PIN_PWM_LED1_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_1 - -/** PWM LED2 pin definitions. */ -#define PIN_PWM_LED2_GPIO PIO_PD22_IDX -#define PIN_PWM_LED2_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_PWM_LED2_CHANNEL PWM_CHANNEL_2 - -/** PWM LED3 pin definitions. */ -#define PIN_PWM_LED3_GPIO PIO_PA0_IDX -#define PIN_PWM_LED3_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_PWM_LED3_CHANNEL PWM_CHANNEL_0 - - -/** SPI MISO pin definition. */ -#define SPI_MISO_GPIO (PIO_PA12_IDX) -#define SPI_MISO_FLAGS (IOPORT_MODE_MUX_A) -/** SPI MOSI pin definition. */ -#define SPI_MOSI_GPIO (PIO_PA13_IDX) -#define SPI_MOSI_FLAGS (IOPORT_MODE_MUX_A) -/** SPI SPCK pin definition. */ -#define SPI_SPCK_GPIO (PIO_PA14_IDX) -#define SPI_SPCK_FLAGS (IOPORT_MODE_MUX_A) - -/** SPI chip select 0 pin definition. (Only one configuration is possible) */ -#define SPI_NPCS0_GPIO (PIO_PA11_IDX) -#define SPI_NPCS0_FLAGS (IOPORT_MODE_MUX_A) -/** SPI chip select 1 pin definition. (multiple configurations are possible) */ -#define SPI_NPCS1_PA9_GPIO (PIO_PA9_IDX) -#define SPI_NPCS1_PA9_FLAGS (IOPORT_MODE_MUX_B) -#define SPI_NPCS1_PA31_GPIO (PIO_PA31_IDX) -#define SPI_NPCS1_PA31_FLAGS (IOPORT_MODE_MUX_A) -#define SPI_NPCS1_PB14_GPIO (PIO_PB14_IDX) -#define SPI_NPCS1_PB14_FLAGS (IOPORT_MODE_MUX_A) -#define SPI_NPCS1_PC4_GPIO (PIO_PC4_IDX) -#define SPI_NPCS1_PC4_FLAGS (IOPORT_MODE_MUX_B) -/** SPI chip select 2 pin definition. (multiple configurations are possible) */ -#define SPI_NPCS2_PA10_GPIO (PIO_PA10_IDX) -#define SPI_NPCS2_PA10_FLAGS (IOPORT_MODE_MUX_B) -#define SPI_NPCS2_PA30_GPIO (PIO_PA30_IDX) -#define SPI_NPCS2_PA30_FLAGS (IOPORT_MODE_MUX_B) -#define SPI_NPCS2_PB2_GPIO (PIO_PB2_IDX) -#define SPI_NPCS2_PB2_FLAGS (IOPORT_MODE_MUX_B) -/** SPI chip select 3 pin definition. (multiple configurations are possible) */ -#define SPI_NPCS3_PA3_GPIO (PIO_PA3_IDX) -#define SPI_NPCS3_PA3_FLAGS (IOPORT_MODE_MUX_B) -#define SPI_NPCS3_PA5_GPIO (PIO_PA5_IDX) -#define SPI_NPCS3_PA5_FLAGS (IOPORT_MODE_MUX_B) -#define SPI_NPCS3_PA22_GPIO (PIO_PA22_IDX) -#define SPI_NPCS3_PA22_FLAGS (IOPORT_MODE_MUX_B) - -/* Select the SPI module that AT25DFx is connected to */ -#define AT25DFX_SPI_MODULE SPI - -/* Chip select used by AT25DFx components on the SPI module instance */ -#define AT25DFX_CS 3 - -/* Touch screen IRQ & Busy pin definition */ -#define BOARD_ADS7843_IRQ_GPIO (PIO_PA16_IDX) -#define BOARD_ADS7843_IRQ_FLAGS IOPORT_MODE_PULLUP -#define BOARD_ADS7843_BUSY_GPIO (PIO_PA17_IDX) -#define BOARD_ADS7843_BUSY_FLAGS IOPORT_MODE_PULLUP -/** -* SPI instance, which can be SPI, SPI0 or SPI1, depends on which SPI -* channel is used. -*/ -#define BOARD_ADS7843_SPI_BASE SPI -/* SPI chip select NO., depends on which SPI CS pin is used by ADS7843. */ -#define BOARD_ADS7843_SPI_NPCS 0 - -/** TWI0 pins definition */ -#define TWI0_DATA_GPIO PIO_PA3_IDX -#define TWI0_DATA_FLAGS (IOPORT_MODE_MUX_A) -#define TWI0_CLK_GPIO PIO_PA4_IDX -#define TWI0_CLK_FLAGS (IOPORT_MODE_MUX_A) - -/** TWI1 pins definition */ -#define TWI1_DATA_GPIO PIO_PB4_IDX -#define TWI1_DATA_FLAGS (IOPORT_MODE_MUX_A) -#define TWI1_CLK_GPIO PIO_PB5_IDX -#define TWI1_CLK_FLAGS (IOPORT_MODE_MUX_A) - -/** PCK0 pin definition (PA6) */ -#define PIN_PCK0 (PIO_PA6_IDX) -#define PIN_PCK0_MUX (IOPORT_MODE_MUX_B) -#define PIN_PCK0_FLAGS (IOPORT_MODE_MUX_B) -#define PIN_PCK0_PORT IOPORT_PIOA -#define PIN_PCK0_MASK PIO_PA6B_PCK0 -#define PIN_PCK0_PIO PIOA -#define PIN_PCK0_ID ID_PIOA -#define PIN_PCK0_TYPE PIO_PERIPH_B -#define PIN_PCK0_ATTR PIO_DEFAULT - -/** USART0 pin RX */ -#define PIN_USART0_RXD {PIO_PB0C_RXD0, PIOB, ID_PIOB, PIO_PERIPH_C, \ - PIO_DEFAULT} -#define PIN_USART0_RXD_IDX (PIO_PB0_IDX) -#define PIN_USART0_RXD_FLAGS (IOPORT_MODE_MUX_C) -/** USART0 pin TX */ -#define PIN_USART0_TXD {PIO_PB1C_TXD0, PIOB, ID_PIOB, PIO_PERIPH_C, \ - PIO_DEFAULT} -#define PIN_USART0_TXD_IDX (PIO_PB1_IDX) -#define PIN_USART0_TXD_FLAGS (IOPORT_MODE_MUX_C) -/** USART0 pin CTS */ -#define PIN_USART0_CTS {PIO_PB2C_CTS0, PIOB, ID_PIOB, PIO_PERIPH_C, \ - PIO_DEFAULT} -#define PIN_USART0_CTS_IDX (PIO_PB2_IDX) -#define PIN_USART0_CTS_FLAGS (IOPORT_MODE_MUX_C) -/** USART0 pin RTS */ -#define PIN_USART0_RTS {PIO_PB3C_RTS0, PIOB, ID_PIOB, PIO_PERIPH_C, \ - PIO_DEFAULT} -#define PIN_USART0_RTS_IDX (PIO_PB3_IDX) -#define PIN_USART0_RTS_FLAGS (IOPORT_MODE_MUX_C) -/** USART0 pin SCK */ -#define PIN_USART0_SCK {PIO_PB13C_SCK0, PIOB, ID_PIOB, PIO_PERIPH_C, \ - PIO_DEFAULT} -#define PIN_USART0_SCK_IDX (PIO_PB13_IDX) -#define PIN_USART0_SCK_FLAGS (IOPORT_MODE_MUX_C) - -/** USART1 pin RX */ -#define PIN_USART1_RXD {PIO_PA21A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, \ - PIO_DEFAULT} -#define PIN_USART1_RXD_IDX (PIO_PA21_IDX) -#define PIN_USART1_RXD_FLAGS (IOPORT_MODE_MUX_A) -/** USART1 pin TX */ -#define PIN_USART1_TXD {PIO_PA22A_TXD1, PIOA, ID_PIOA, PIO_PERIPH_A, \ - PIO_DEFAULT} -#define PIN_USART1_TXD_IDX (PIO_PA22_IDX) -#define PIN_USART1_TXD_FLAGS (IOPORT_MODE_MUX_A) -/** USART1 pin CTS */ -#define PIN_USART1_CTS {PIO_PA25A_CTS1, PIOA, ID_PIOA, PIO_PERIPH_A, \ - PIO_DEFAULT} -#define PIN_USART1_CTS_IDX (PIO_PA25_IDX) -#define PIN_USART1_CTS_FLAGS (IOPORT_MODE_MUX_A) -/** USART1 pin RTS */ -#define PIN_USART1_RTS {PIO_PA24A_RTS1, PIOA, ID_PIOA, PIO_PERIPH_A, \ - PIO_DEFAULT} -#define PIN_USART1_RTS_IDX (PIO_PA24_IDX) -#define PIN_USART1_RTS_FLAGS (IOPORT_MODE_MUX_A) -/** USART1 pin SCK */ -#define PIN_USART1_SCK {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_PERIPH_A, \ - PIO_DEFAULT} -#define PIN_USART1_SCK_IDX (PIO_PA23_IDX) -#define PIN_USART1_SCK_FLAGS (IOPORT_MODE_MUX_A) -/** USART1 pin ENABLE */ -#define PIN_USART1_EN {PIO_PA23, PIOA, ID_PIOA, PIO_OUTPUT_0, \ - PIO_DEFAULT} -#define PIN_USART1_EN_IDX (PIO_PA23_IDX) -#define PIN_USART1_EN_FLAGS (0) -#define PIN_USART1_EN_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW -#define PIN_USART1_EN_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH - -/** USB VBus monitoring pin definition. */ -#define PIN_USB_VBUS {PIO_PC21, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} -#define USB_VBUS_FLAGS (PIO_INPUT | PIO_DEBOUNCE | PIO_IT_EDGE) -#define USB_VBUS_PIN_IRQn (PIOC_IRQn) -#define USB_VBUS_PIN (PIO_PC21_IDX) -#define USB_VBUS_PIO_ID (ID_PIOC) -#define USB_VBUS_PIO_MASK (PIO_PC21) -/* This pin can not be used as fast wakeup source such as - * USB_VBUS_WKUP PMC_FSMR_FSTT7 */ - -/** USB D- pin (System function) */ -#define PIN_USB_DM {PIO_PB10} -/** USB D+ pin (System function) */ -#define PIN_USB_DP {PIO_PB11} - -/** EBI Data Bus pins */ -#define PIN_EBI_DATA_BUS_D0 PIO_PC0_IDX -#define PIN_EBI_DATA_BUS_D1 PIO_PC1_IDX -#define PIN_EBI_DATA_BUS_D2 PIO_PC2_IDX -#define PIN_EBI_DATA_BUS_D3 PIO_PC3_IDX -#define PIN_EBI_DATA_BUS_D4 PIO_PC4_IDX -#define PIN_EBI_DATA_BUS_D5 PIO_PC5_IDX -#define PIN_EBI_DATA_BUS_D6 PIO_PC6_IDX -#define PIN_EBI_DATA_BUS_D7 PIO_PC7_IDX -#define PIN_EBI_DATA_BUS_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP) - -#define PIN_EBI_NRD PIO_PC11_IDX -#define PIN_EBI_NRD_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP) -#define PIN_EBI_NWE PIO_PC8_IDX -#define PIN_EBI_NWE_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP) - -/** EBI pin for LCD CS and RS **/ -#define PIN_EBI_NCS1 PIO_PD18_IDX -#define PIN_EBI_NCS1_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP) -#define PIN_EBI_LCD_RS PIO_PC19_IDX -#define PIN_EBI_LCD_RS_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP) - -/** Indicates board has an ILI9325 external component to manage LCD. */ -#define BOARD_LCD_ILI93XX - -/** Backlight pin definition. */ -#define BOARD_AAT31XX_SET_GPIO PIO_PC13_IDX -/** Define ILI93xx base address. */ -#define BOARD_ILI93XX_ADDR 0x61000000 -/** Define ILI9325 register select signal. */ -#define BOARD_ILI93XX_RS (1 << 1) -/** Display width in pixels. */ -#define BOARD_LCD_WIDTH 240 -/** Display height in pixels. */ -#define BOARD_LCD_HEIGHT 320 - -/* KSZ8051MNL relate PIN definition */ -#define PIN_KSZ8051MNL_RXC_IDX PIO_PD14_IDX -#define PIN_KSZ8051MNL_RXC_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_TXC_IDX PIO_PD0_IDX -#define PIN_KSZ8051MNL_TXC_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_TXEN_IDX PIO_PD1_IDX -#define PIN_KSZ8051MNL_TXEN_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_TXD3_IDX PIO_PD16_IDX -#define PIN_KSZ8051MNL_TXD3_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_TXD2_IDX PIO_PD15_IDX -#define PIN_KSZ8051MNL_TXD2_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_TXD1_IDX PIO_PD3_IDX -#define PIN_KSZ8051MNL_TXD1_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_TXD0_IDX PIO_PD2_IDX -#define PIN_KSZ8051MNL_TXD0_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_RXD3_IDX PIO_PD12_IDX -#define PIN_KSZ8051MNL_RXD3_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_RXD2_IDX PIO_PD11_IDX -#define PIN_KSZ8051MNL_RXD2_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_RXD1_IDX PIO_PD6_IDX -#define PIN_KSZ8051MNL_RXD1_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_RXD0_IDX PIO_PD5_IDX -#define PIN_KSZ8051MNL_RXD0_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_RXER_IDX PIO_PD7_IDX -#define PIN_KSZ8051MNL_RXER_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_RXDV_IDX PIO_PD4_IDX -#define PIN_KSZ8051MNL_RXDV_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_CRS_IDX PIO_PD10_IDX -#define PIN_KSZ8051MNL_CRS_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_COL_IDX PIO_PD13_IDX -#define PIN_KSZ8051MNL_COL_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_MDC_IDX PIO_PD8_IDX -#define PIN_KSZ8051MNL_MDC_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_MDIO_IDX PIO_PD9_IDX -#define PIN_KSZ8051MNL_MDIO_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_KSZ8051MNL_INTRP_IDX PIO_PD28_IDX - -/** NandFlash pins definition: OE. */ -#define PIN_EBI_NANDOE (PIO_PC9_IDX) -#define PIN_EBI_NANDOE_FLAGS (IOPORT_MODE_MUX_A) - -/** NandFlash pins definition: WE. */ -#define PIN_EBI_NANDWE (PIO_PC10_IDX) -#define PIN_EBI_NANDWE_FLAGS (IOPORT_MODE_MUX_A) - -/** NandFlash pins definition: CLE. */ -#define PIN_EBI_NANDCLE (PIO_PC17_IDX) -#define PIN_EBI_NANDCLE_FLAGS (IOPORT_MODE_MUX_A) - -/** NandFlash pins definition: ALE. */ -#define PIN_EBI_NANDALE (PIO_PC16_IDX) -#define PIN_EBI_NANDALE_FLAGS (IOPORT_MODE_MUX_A) - -/** NandFlash pins definition: DATA. */ -#define PIN_EBI_NANDIO_0 (PIO_PC0_IDX) -#define PIN_EBI_NANDIO_0_FLAGS (IOPORT_MODE_MUX_A) - -#define PIN_EBI_NANDIO_1 (PIO_PC1_IDX) -#define PIN_EBI_NANDIO_1_FLAGS (IOPORT_MODE_MUX_A) - -#define PIN_EBI_NANDIO_2 (PIO_PC2_IDX) -#define PIN_EBI_NANDIO_2_FLAGS (IOPORT_MODE_MUX_A) - -#define PIN_EBI_NANDIO_3 (PIO_PC3_IDX) -#define PIN_EBI_NANDIO_3_FLAGS (IOPORT_MODE_MUX_A) - -#define PIN_EBI_NANDIO_4 (PIO_PC4_IDX) -#define PIN_EBI_NANDIO_4_FLAGS (IOPORT_MODE_MUX_A) - -#define PIN_EBI_NANDIO_5 (PIO_PC5_IDX) -#define PIN_EBI_NANDIO_5_FLAGS (IOPORT_MODE_MUX_A) - -#define PIN_EBI_NANDIO_6 (PIO_PC6_IDX) -#define PIN_EBI_NANDIO_6_FLAGS (IOPORT_MODE_MUX_A) - -#define PIN_EBI_NANDIO_7 (PIO_PC7_IDX) -#define PIN_EBI_NANDIO_7_FLAGS (IOPORT_MODE_MUX_A) - -/** Nandflash chip enable pin definition. */ -#define PIN_NF_CE_IDX (PIO_PC14_IDX) - -/** Nandflash ready/busy pin definition. */ -#define PIN_NF_RB_IDX (PIO_PC18_IDX) - -/* Chip select number for nand */ -#define BOARD_NAND_CS 0 - -/*----------------------------------------------------------------------------*/ -/** - * \page sam4e_ek_usb "SAM4E-EK - USB device" - * - * \section Definitions - * - \ref BOARD_USB_BMATTRIBUTES - * - \ref CHIP_USB_UDP - * - \ref CHIP_USB_PULLUP_INTERNAL - * - \ref CHIP_USB_NUMENDPOINTS - * - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE - * - \ref CHIP_USB_ENDPOINTS_BANKS - */ - -/** - * USB attributes configuration descriptor (bus or self powered, - * remote wakeup) - */ -#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP - -/** Indicates chip has an UDP Full Speed. */ -#define CHIP_USB_UDP - -/** Indicates chip has an internal pull-up. */ -#define CHIP_USB_PULLUP_INTERNAL - -/** Number of USB endpoints */ -#define CHIP_USB_NUMENDPOINTS 8 - -/** Endpoints max packet size */ -#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ - ((i == 0) ? 64 : \ - ((i == 1) ? 64 : \ - ((i == 2) ? 64 : \ - ((i == 3) ? 64 : \ - ((i == 4) ? 512 : \ - ((i == 5) ? 512 : \ - ((i == 6) ? 64 : \ - ((i == 7) ? 64 : 0 )))))))) - -/** Endpoints Number of Bank */ -#define CHIP_USB_ENDPOINTS_BANKS(i) \ - ((i == 0) ? 1 : \ - ((i == 1) ? 2 : \ - ((i == 2) ? 2 : \ - ((i == 3) ? 1 : \ - ((i == 4) ? 2 : \ - ((i == 5) ? 2 : \ - ((i == 6) ? 2 : \ - ((i == 7) ? 2 : 0 )))))))) - -/*----------------------------------------------------------------------------*/ -/** - * \page sam4e_ek_extcomp "SAM4E-EK - External components" - * This page lists the definitions related to external on-board components - * located in the board.h file for the SAM4E-EK. - * - * SD Card - * - \ref BOARD_SD_PINS - * - \ref BOARD_SD_PIN_CD - * - * QTouch component (QT2160) - * - \ref BOARD_QT_TWI_INSTANCE - * - \ref BOARD_QT_DEVICE_ADDRESS - * - \ref BOARD_QT_CHANGE_PIN_IDX - * - \ref BOARD_QT_CHANGE_PIN_FLAGS - * - \ref BOARD_QT_CHANGE_PIN_SENSE - */ - -/** HSMCI pins that shall be configured to access the SD card. */ -#define BOARD_SD_PINS PINS_HSMCI -/** HSMCI Card Detect pin. */ -#define BOARD_SD_PIN_CD PIN_HSMCI_CD - -/** TWI instance for QTouch device */ -#define BOARD_QT_TWI_INSTANCE TWI0 -/* QTouch device address (I2CA1 = I2CA0 = 0) */ -#define BOARD_QT_DEVICE_ADDRESS 0x0D -/** QTouch component pin definition */ -#define BOARD_QT_CHANGE_PIN_IDX (PIO_PE4_IDX) -#define BOARD_QT_CHANGE_PIN_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) -#define BOARD_QT_CHANGE_PIN_SENSE (IOPORT_SENSE_FALLING) - -/*----------------------------------------------------------------------------*/ -/** - * \page sam4e_ek_mem "SAM4E-EK - Memories" - * This page lists definitions related to internal & external on-board memories. - * - * \section NandFlash - * - \ref BOARD_NF_COMMAND_ADDR - * - \ref BOARD_NF_ADDRESS_ADDR - * - \ref BOARD_NF_DATA_ADDR - * - * \section NorFlash - * - \ref BOARD_NORFLASH_ADDR - * - \ref BOARD_NORFLASH_DFT_BUS_SIZE - */ - -/** Address for transferring command bytes to the nandflash. */ -#define BOARD_NF_COMMAND_ADDR 0x60400000 -/** Address for transferring address bytes to the nandflash. */ -#define BOARD_NF_ADDRESS_ADDR 0x60200000 -/** Address for transferring data bytes to the nandflash. */ -#define BOARD_NF_DATA_ADDR 0x60000000 -/* Bus width for NAND */ -#define CONF_NF_BUSWIDTH 8 -/* Access timing for NAND */ -#define CONF_NF_SETUP_TIMING (SMC_SETUP_NWE_SETUP(0) \ - | SMC_SETUP_NCS_WR_SETUP(1) \ - | SMC_SETUP_NRD_SETUP(0) \ - | SMC_SETUP_NCS_RD_SETUP(1)) -#define CONF_NF_PULSE_TIMING (SMC_PULSE_NWE_PULSE(2) \ - | SMC_PULSE_NCS_WR_PULSE(3) \ - | SMC_PULSE_NRD_PULSE(4) \ - | SMC_PULSE_NCS_RD_PULSE(4)) -#define CONF_NF_CYCLE_TIMING (SMC_CYCLE_NWE_CYCLE(4) \ - | SMC_CYCLE_NRD_CYCLE(7)) - -/** Address for transferring command bytes to the norflash. */ -#define BOARD_NORFLASH_ADDR 0x63000000 -/** Default NOR bus size after power up reset */ -#define BOARD_NORFLASH_DFT_BUS_SIZE 8 - -/*----------------------------------------------------------------------------*/ - -#define CONSOLE_UART UART0 -#define CONSOLE_UART_ID ID_UART0 - -/* RE pin. */ -#define PIN_RE_IDX PIN_USART1_CTS_IDX -#define PIN_RE_FLAGS (0) - -/* IRDA SD pin. */ -#define PIN_IRDA_SD_IDX PIN_USART1_CTS_IDX -#define PIN_IRDA_SD_FLAGS (0) - -/* TXD pin configuration. */ -#define PIN_USART_TXD_IDX PIN_USART1_TXD_IDX -#define PIN_USART_TXD_FLAGS (IOPORT_MODE_MUX_A) -#define PIN_USART_TXD_IO_FLAGS (0) - -/* ISO7816 example relate PIN definition. */ -#define ISO7816_USART_ID ID_USART1 -#define ISO7816_USART USART1 -#define PIN_ISO7816_RST_IDX PIO_PA15_IDX -#define PIN_ISO7816_RST_FLAG (0) - -/*----------------------------------------------------------------------------*/ -/* GMAC HW configurations */ -#define BOARD_GMAC_PHY_ADDR 0 - -/*----------------------------------------------------------------------------*/ -/** - * \page sam4e_ek_CAN "SAM4E-EK - CAN" - * This page lists definitions related to CAN0 and CAN1. - * - * CAN - * - \ref PIN_CAN0_TRANSCEIVER_RXEN - * - \ref PIN_CAN0_TRANSCEIVER_RS - * - \ref PIN_CAN0_TXD - * - \ref PIN_CAN0_RXD - * - \ref PINS_CAN0 - * - * - \ref PIN_CAN1_TRANSCEIVER_RXEN - * - \ref PIN_CAN1_TRANSCEIVER_RS - * - \ref PIN_CAN1_TXD - * - \ref PIN_CAN1_RXD - * - \ref PINS_CAN1 - */ -/** CAN0 transceiver PIN RS. */ -#define PIN_CAN0_TR_RS_IDX PIO_PE0_IDX -#define PIN_CAN0_TR_RS_FLAGS IOPORT_DIR_OUTPUT - -/** CAN0 transceiver PIN EN. */ -#define PIN_CAN0_TR_EN_IDX PIO_PE1_IDX -#define PIN_CAN0_TR_EN_FLAGS IOPORT_DIR_OUTPUT - -/** CAN0 PIN RX. */ -#define PIN_CAN0_RX_IDX PIO_PB3_IDX -#define PIN_CAN0_RX_FLAGS IOPORT_MODE_MUX_A - -/** CAN0 PIN TX. */ -#define PIN_CAN0_TX_IDX PIO_PB2_IDX -#define PIN_CAN0_TX_FLAGS IOPORT_MODE_MUX_A - -/** CAN1 transceiver PIN RS. */ -#define PIN_CAN1_TR_RS_IDX PIO_PE2_IDX -#define PIN_CAN1_TR_RS_FLAGS IOPORT_DIR_OUTPUT - -/** CAN1 transceiver PIN EN. */ -#define PIN_CAN1_TR_EN_IDX PIO_PE3_IDX -#define PIN_CAN1_TR_EN_FLAGS IOPORT_DIR_OUTPUT - -/** CAN1 PIN RX. */ -#define PIN_CAN1_RX_IDX PIO_PC12_IDX -#define PIN_CAN1_RX_FLAGS IOPORT_MODE_MUX_C - -/** CAN1 PIN TX. */ -#define PIN_CAN1_TX_IDX PIO_PC15_IDX -#define PIN_CAN1_TX_FLAGS IOPORT_MODE_MUX_C - -/** AFEC channel for potentiometer */ -#define AFEC_CHANNEL_POTENTIOMETER AFEC_CHANNEL_5 - -/*----------------------------------------------------------------------------*/ -#endif /* _SAM4E_EK_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/aat31xx/aat31xx.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/aat31xx/aat31xx.c deleted file mode 100644 index 6a5d4b387..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/aat31xx/aat31xx.c +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * \brief API driver for component aat31xx. - * - * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \defgroup aat31xx_display_group Display - AAT31XX Controller - * - * Low-level driver for the AAT31XX LCD backlight controller. This driver provides access to the main - * features of the AAT31XX controller. - * - * \{ - */ - -#include "board.h" -#include "ioport.h" -#include "aat31xx.h" -#include "conf_aat31xx.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -#define DELAY_PULSE (0x18u) -#define DELAY_ENABLE (0x20000u) -#define DELAY_DISABLE (0x20000u) - -/** - * \brief Set the LCD backlight level. - * - * \param ul_level backlight level. - * - * \note pin BOARD_AAT31XX_SET_GPIO must be configured before calling aat31xx_set_backlight. - */ -void aat31xx_set_backlight(uint32_t ul_level) -{ - volatile uint32_t ul_delay; - uint32_t i; - -#ifdef CONF_BOARD_AAT3155 - ul_level = AAT31XX_MAX_BACKLIGHT_LEVEL - ul_level + 1; -#endif - -#ifdef CONF_BOARD_AAT3193 - ul_level = AAT31XX_MAX_BACKLIGHT_LEVEL - ul_level + 1; -#endif - - /* Ensure valid level */ - ul_level = (ul_level > AAT31XX_MAX_BACKLIGHT_LEVEL) ? AAT31XX_MAX_BACKLIGHT_LEVEL : ul_level; - ul_level = (ul_level < AAT31XX_MIN_BACKLIGHT_LEVEL) ? AAT31XX_MIN_BACKLIGHT_LEVEL : ul_level; - - /* Set new backlight level */ - for (i = 0; i < ul_level; i++) { - ioport_set_pin_level(BOARD_AAT31XX_SET_GPIO, IOPORT_PIN_LEVEL_LOW); - ul_delay = DELAY_PULSE; - while (ul_delay--) { - } - - ioport_set_pin_level(BOARD_AAT31XX_SET_GPIO, IOPORT_PIN_LEVEL_HIGH); - - ul_delay = DELAY_PULSE; - while (ul_delay--) { - } - } - - ul_delay = DELAY_ENABLE; - while (ul_delay--) { - } -} - -/** - * \brief Switch off backlight. - */ -void aat31xx_disable_backlight(void) -{ - volatile uint32_t ul_delay; - - ioport_set_pin_level(BOARD_AAT31XX_SET_GPIO, IOPORT_PIN_LEVEL_LOW); - - ul_delay = DELAY_DISABLE; - while (ul_delay--) { - } -} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \} - */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/aat31xx/aat31xx.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/aat31xx/aat31xx.h deleted file mode 100644 index 8d0397ba6..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/aat31xx/aat31xx.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - * \file - * - * \brief API driver for component aat31xx. - * - * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef AAT31XX_H_INCLUDED -#define AAT31XX_H_INCLUDED - -#include "compiler.h" -#include "conf_board.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/* The minimum, average and maximum brightness level values */ -#ifdef CONF_BOARD_AAT3155 -#define AAT31XX_MIN_BACKLIGHT_LEVEL 1 -#define AAT31XX_AVG_BACKLIGHT_LEVEL 8 -#define AAT31XX_MAX_BACKLIGHT_LEVEL 16 -#endif -#ifdef CONF_BOARD_AAT3193 -#define AAT31XX_MIN_BACKLIGHT_LEVEL 1 -#define AAT31XX_AVG_BACKLIGHT_LEVEL 8 -#define AAT31XX_MAX_BACKLIGHT_LEVEL 16 -#endif -#ifdef CONF_BOARD_AAT3194 -#define AAT31XX_MIN_BACKLIGHT_LEVEL 1 -#define AAT31XX_AVG_BACKLIGHT_LEVEL 25 -#define AAT31XX_MAX_BACKLIGHT_LEVEL 32 -#endif - -/* No component found */ -#ifndef AAT31XX_MIN_BACKLIGHT_LEVEL -#warning Cannot configure AAT31XX. The component must be declared in conf_board.h first! -#define AAT31XX_MIN_BACKLIGHT_LEVEL 0 -#define AAT31XX_AVG_BACKLIGHT_LEVEL 0 -#define AAT31XX_MAX_BACKLIGHT_LEVEL 0 -#endif - -void aat31xx_set_backlight(uint32_t ul_level); -void aat31xx_disable_backlight(void); - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* AAT31XX_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili9325_regs.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili9325_regs.h deleted file mode 100644 index 6e0ac4fe0..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili9325_regs.h +++ /dev/null @@ -1,646 +0,0 @@ -/** - * \file - * - * \brief registers definition for ili9325 TFT display component. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ILI9325_REGS_H_INCLUDED -#define ILI9325_REGS_H_INCLUDED - -/** @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/** @endcond */ - -/** ili9325 LCD Registers */ - -/** Driver Code Read */ -#define ILI9325_DEVICE_CODE_REG (0x00u) - -/** ILI9325_START_OSC_CTRL : (Offset: 0x00) Start Oscillator Control*/ -#define ILI9325_START_OSC_CTRL (0x00u) -#define ILI9325_START_OSC_CTRL_EN (0x1u << 0) - -/** ILI9325_DRIVER_OUTPUT_CTRL1 : (Offset: 0x01) Driver Output Control 1*/ -#define ILI9325_DRIVER_OUTPUT_CTRL1 (0x01u) -#define ILI9325_DRIVER_OUTPUT_CTRL1_SS (0x1u << 8) -#define ILI9325_DRIVER_OUTPUT_CTRL1_SM (0x1u << 10) - -/** ILI9325_LCD_DRIVING_CTRL : (Offset: 0x02) LCD Driving Control */ -#define ILI9325_LCD_DRIVING_CTRL (0x02u) -#define ILI9325_LCD_DRIVING_CTRL_EOR (0x1u << 8) -#define ILI9325_LCD_DRIVING_CTRL_BC0 (0x1u << 9) -#define ILI9325_LCD_DRIVING_CTRL_BIT10 (0x1u << 10) - -/** ILI9325_ENTRY_MODE : (Offset: 0x03) Entry Mode*/ -#define ILI9325_ENTRY_MODE (0x03u) -#define ILI9325_ENTRY_MODE_AM (0x1u << 3) -#define ILI9325_ENTRY_MODE_ID_POS 4 -#define ILI9325_ENTRY_MODE_ID_MSK (0x3u << ILI9325_ENTRY_MODE_ID_POS) -#define ILI9325_ENTRY_MODE_ID(value) ((ILI9325_ENTRY_MODE_ID_MSK & \ - ((value) << ILI9325_ENTRY_MODE_ID_POS))) -#define ILI9325_ENTRY_MODE_ORG (0x1u << 7) -#define ILI9325_ENTRY_MODE_HWM (0x1u << 9) -#define ILI9325_ENTRY_MODE_BGR (0x1u << 12) -#define ILI9325_ENTRY_MODE_DFM (0x1u << 14) -#define ILI9325_ENTRY_MODE_TRI (0x1u << 15) - -/** ILI9325_RESIZE_CTRL : (Offset: 0x04) Resize Control */ -#define ILI9325_RESIZE_CTRL (0x04u) -#define ILI9325_RESIZE_CTRL_RSZ_POS 0 -#define ILI9325_RESIZE_CTRL_RSZ_MSK (0x3u << ILI9325_RESIZE_CTRL_RSZ_POS) -#define ILI9325_RESIZE_CTRL_RSZ(value) ((ILI9325_RESIZE_CTRL_RSZ_MSK & \ - ((value) << ILI9325_RESIZE_CTRL_RSZ_POS))) -#define ILI9325_RESIZE_CTRL_RCH_POS 4 -#define ILI9325_RESIZE_CTRL_RCH_MSK (0x3u << ILI9325_RESIZE_CTRL_RCH_POS) -#define ILI9325_RESIZE_CTRL_RCH(value) ((ILI9325_RESIZE_CTRL_RCH_MSK & \ - ((value) << ILI9325_RESIZE_CTRL_RCH_POS))) -#define ILI9325_RESIZE_CTRL_RCV_POS 8 -#define ILI9325_RESIZE_CTRL_RCV_MSK (0x3u << ILI9325_RESIZE_CTRL_RCV_POS) -#define ILI9325_RESIZE_CTRL_RCV(value) ((ILI9325_RESIZE_CTRL_RCV_MSK & \ - ((value) << ILI9325_RESIZE_CTRL_RCV_POS))) - -/** ILI9325_DISP_CTRL1 : (Offset: 0x07) Display Control 1 */ -#define ILI9325_DISP_CTRL1 (0x07u) -#define ILI9325_DISP_CTRL1_D_POS 0 -#define ILI9325_DISP_CTRL1_D_MSK (0x3u << ILI9325_DISP_CTRL1_D_POS) -#define ILI9325_DISP_CTRL1_D(value) ((ILI9325_DISP_CTRL1_D_MSK & \ - ((value) << ILI9325_DISP_CTRL1_D_POS))) -#define ILI9325_DISP_CTRL1_CL (0x1u << 3) -#define ILI9325_DISP_CTRL1_DTE (0x1u << 4) -#define ILI9325_DISP_CTRL1_GON (0x1u << 5) -#define ILI9325_DISP_CTRL1_BASEE (0x1u << 8) -#define ILI9325_DISP_CTRL1_PTDE_POS 12 -#define ILI9325_DISP_CTRL1_PTDE_MSK (0x3u << ILI9325_DISP_CTRL1_PTDE_POS) -#define ILI9325_DISP_CTRL1_PTDE(value) ((ILI9325_DISP_CTRL1_PTDE_MSK & \ - ((value) << ILI9325_DISP_CTRL1_PTDE_POS))) - -/** ILI9325_DISP_CTRL2 : (Offset: 0x08) Display Control 2 */ -#define ILI9325_DISP_CTRL2 (0x08u) -#define ILI9325_DISP_CTRL2_BP_POS 0 -#define ILI9325_DISP_CTRL2_BP_MSK (0xfu << ILI9325_DISP_CTRL2_BP_POS) -#define ILI9325_DISP_CTRL2_BP(value) ((ILI9325_DISP_CTRL2_BP_MSK & \ - ((value) << ILI9325_DISP_CTRL2_BP_POS))) -#define ILI9325_DISP_CTRL2_FP_POS 8 -#define ILI9325_DISP_CTRL2_FP_MSK (0xfu << ILI9325_DISP_CTRL2_FP_POS) -#define ILI9325_DISP_CTRL2_FP(value) ((ILI9325_DISP_CTRL2_FP_MSK & \ - ((value) << ILI9325_DISP_CTRL2_FP_POS))) - -/** ILI9325_DISP_CTRL3 : (Offset: 0x09) Display Control 3 */ -#define ILI9325_DISP_CTRL3 (0x09u) -#define ILI9325_DISP_CTRL3_ISC_POS 0 -#define ILI9325_DISP_CTRL3_ISC_MSK (0xfu << ILI9325_DISP_CTRL3_ISC_POS) -#define ILI9325_DISP_CTRL3_ISC(value) ((ILI9325_DISP_CTRL3_ISC_MSK & \ - ((value) << ILI9325_DISP_CTRL3_ISC_POS))) -#define ILI9325_DISP_CTRL3_PTG_POS 4 -#define ILI9325_DISP_CTRL3_PTG_MSK (0x3u << ILI9325_DISP_CTRL3_PTG_POS) -#define ILI9325_DISP_CTRL3_PTG(value) ((ILI9325_DISP_CTRL3_PTG_MSK & \ - ((value) << ILI9325_DISP_CTRL3_PTG_POS))) -#define ILI9325_DISP_CTRL3_PTS_POS 8 -#define ILI9325_DISP_CTRL3_PTS_MSK (0x7u << ILI9325_DISP_CTRL3_PTS_POS) -#define ILI9325_DISP_CTRL3_PTS(value) ((ILI9325_DISP_CTRL3_PTS_MSK & \ - ((value) << ILI9325_DISP_CTRL3_PTS_POS))) - -/** ILI9325_DISP_CTRL4 : (Offset: 0x0A) Display Control 4 */ -#define ILI9325_DISP_CTRL4 (0x0Au) -#define ILI9325_DISP_CTRL4_FMI_POS 0 -#define ILI9325_DISP_CTRL4_FMI_MSK (0x7u << ILI9325_DISP_CTRL4_FMI_POS) -#define ILI9325_DISP_CTRL4_FMI(value) ((ILI9325_DISP_CTRL4_FMI_MSK & \ - ((value) << ILI9325_DISP_CTRL4_FMI_POS))) -#define ILI9325_DISP_CTRL4_FMARKOE (0x1u << 3) - -/** ILI9325_RGB_DISP_INTERFACE_CTRL1 : (Offset: 0x0C) RGB Display - *Interface Control 1 */ -#define ILI9325_RGB_DISP_INTERFACE_CTRL1 (0x0Cu) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_POS 0 -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_MSK (0x3u << \ - ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_POS) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM(value) (( \ - ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_MSK & \ - ((value) << ILI9325_RGB_DISP_INTERFACE_CTRL1_RIM_POS))) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM0 (0x1u << 4) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM1 (0x1u << 5) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_POS 4 -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_MSK (0x3u << \ - ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_POS) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_DM(value) (( \ - ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_MSK & \ - ((value) << ILI9325_RGB_DISP_INTERFACE_CTRL1_DM_POS))) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_RM (0x1u << 8) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_POS 12 -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_MSK (0x7u << \ - ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_POS) -#define ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC(value) (( \ - ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_MSK & \ - ((value) < ILI9325_RGB_DISP_INTERFACE_CTRL1_ENC_POS))) - -/** ILI9325_FRAME_MAKER_POS : (Offset: 0x0D) Frame Maker Position */ -#define ILI9325_FRAME_MAKER_POS (0x0Du) -#define ILI9325_FRAME_MAKER_POS_FMP_POS 0 -#define ILI9325_FRAME_MAKER_POS_FMP_MSK (0x1ffu << \ - ILI9325_FRAME_MAKER_POS_FMP_POS) -#define ILI9325_FRAME_MAKER_POS_FMP(value) ((ILI9325_FRAME_MAKER_POS_FMP_MSK & \ - ((value) << ILI9325_FRAME_MAKER_POS_FMP_POS))) - -/** ILI9325_RGB_DISP_INTERFACE_CTRL2 : (Offset: 0x0F) RGB Display - * Interface Control 2 */ -#define ILI9325_RGB_DISP_INTERFACE_CTRL2 (0x0Fu) -#define ILI9325_RGB_DISP_INTERFACE_CTRL2_EPL (0x1u << 0) -#define ILI9325_RGB_DISP_INTERFACE_CTRL2_DPL (0x1u << 1) -#define ILI9325_RGB_DISP_INTERFACE_CTRL2_HSPL (0x1u << 3) -#define ILI9325_RGB_DISP_INTERFACE_CTRL2_VSPL (0x1u << 4) - -/** ILI9325_POWER_CTRL1 : (Offset: 0x10) Power Control 1 */ -#define ILI9325_POWER_CTRL1 (0x10u) -#define ILI9325_POWER_CTRL1_STB (0x1u << 0) -#define ILI9325_POWER_CTRL1_SLP (0x1u << 1) -#define ILI9325_POWER_CTRL1_DSTB (0x1u << 2) -#define ILI9325_POWER_CTRL1_AP_POS 4 -#define ILI9325_POWER_CTRL1_AP_MSK (0x7u << ILI9325_POWER_CTRL1_AP_POS) -#define ILI9325_POWER_CTRL1_AP(value) ((ILI9325_POWER_CTRL1_AP_MSK & \ - ((value) << ILI9325_POWER_CTRL1_AP_POS))) -#define ILI9325_POWER_CTRL1_APE (0x1u << 7) -#define ILI9325_POWER_CTRL1_BT_POS 8 -#define ILI9325_POWER_CTRL1_BT_MSK (0x7u << ILI9325_POWER_CTRL1_BT_POS) -#define ILI9325_POWER_CTRL1_BT(value) ((ILI9325_POWER_CTRL1_BT_MSK & \ - ((value) << ILI9325_POWER_CTRL1_BT_POS))) -#define ILI9325_POWER_CTRL1_SAP (0x1u << 12) - -/** ILI9325_POWER_CTRL2 : (Offset: 0x11) Power Control 2 */ -#define ILI9325_POWER_CTRL2 (0x11u) -#define ILI9325_POWER_CTRL2_VC_POS 0 -#define ILI9325_POWER_CTRL2_VC_MSK (0x7u << ILI9325_POWER_CTRL2_VC_POS) -#define ILI9325_POWER_CTRL2_VC(value) ((ILI9325_POWER_CTRL2_VC_MSK & \ - ((value) << ILI9325_POWER_CTRL2_VC_POS))) -#define ILI9325_POWER_CTRL2_DC0_POS 4 -#define ILI9325_POWER_CTRL2_DC0_MSK (0x7u << ILI9325_POWER_CTRL2_DC0_POS) -#define ILI9325_POWER_CTRL2_DC0(value) ((ILI9325_POWER_CTRL2_DC0_MSK & \ - ((value) << ILI9325_POWER_CTRL2_DC0_POS))) -#define ILI9325_POWER_CTRL2_DC1_POS 8 -#define ILI9325_POWER_CTRL2_DC1_MSK (0x7u << ILI9325_POWER_CTRL2_DC1_POS) -#define ILI9325_POWER_CTRL2_DC1(value) ((ILI9325_POWER_CTRL2_DC1_MSK & \ - ((value) << ILI9325_POWER_CTRL2_DC1_POS))) - -/** ILI9325_POWER_CTRL3 : (Offset: 0x12) Power Control 3 */ -#define ILI9325_POWER_CTRL3 (0x12u) -#define ILI9325_POWER_CTRL3_VRH_POS 0 -#define ILI9325_POWER_CTRL3_VRH_MSK (0xfu << ILI9325_POWER_CTRL3_VRH_POS) -#define ILI9325_POWER_CTRL3_VRH(value) ((ILI9325_POWER_CTRL3_VRH_MSK & \ - ((value) << ILI9325_POWER_CTRL3_VRH_POS))) -#define ILI9325_POWER_CTRL3_PON (0x1u << 4) -#define ILI9325_POWER_CTRL3_VCIRE (0x1u << 7) - -/** ILI9325_POWER_CTRL4 : (Offset: 0x13) Power Control 4 */ -#define ILI9325_POWER_CTRL4 (0x13u) -#define ILI9325_POWER_CTRL4_VDV_POS 8 -#define ILI9325_POWER_CTRL4_VDV_MSK (0x1fu << ILI9325_POWER_CTRL4_VDV_POS) -#define ILI9325_POWER_CTRL4_VDV(value) ((ILI9325_POWER_CTRL4_VDV_MSK & \ - ((value) << ILI9325_POWER_CTRL4_VDV_POS))) - -/** ILI9325_HORIZONTAL_GRAM_ADDR_SET : (Offset: 0x20) Horizontal GRAM - * Address Set */ -#define ILI9325_HORIZONTAL_GRAM_ADDR_SET (0x20u) -#define ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_POS 0 -#define ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_MSK (0xffu << \ - ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_POS) -#define ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD(value) (( \ - ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_MSK & \ - ((value) << ILI9325_HORIZONTAL_GRAM_ADDR_SET_AD_POS))) - -/** ILI9325_VERTICAL_GRAM_ADDR_SET : (Offset: 0x21) Vertical GRAM - * Address Set */ -#define ILI9325_VERTICAL_GRAM_ADDR_SET (0x21u) -#define ILI9325_VERTICAL_GRAM_ADDR_SET_AD_POS 0 -#define ILI9325_VERTICAL_GRAM_ADDR_SET_AD_MSK (0xffu << \ - ILI9325_VERTICAL_GRAM_ADDR_SET_AD_POS) -#define ILI9325_VERTICAL_GRAM_ADDR_SET_AD(value) (( \ - ILI9325_VERTICAL_GRAM_ADDR_SET_AD_MSK & \ - ((value) << ILI9325_VERTICAL_GRAM_ADDR_SET_AD_POS))) - -/** ILI9325_GRAM_DATA_REG : (Offset: 0x22) GRAM Data Register */ -#define ILI9325_GRAM_DATA_REG (0x22u) - -/** ILI9325_POWER_CTRL7 : (Offset: 0x29) Power Control 7 */ -#define ILI9325_POWER_CTRL7 (0x29u) -#define ILI9325_POWER_CTRL7_VCM_POS 0 -#define ILI9325_POWER_CTRL7_VCM_MSK (0x3fu << ILI9325_POWER_CTRL7_VCM_POS) -#define ILI9325_POWER_CTRL7_VCM(value) ((ILI9325_POWER_CTRL7_VCM_MSK & \ - ((value) << ILI9325_POWER_CTRL7_VCM_POS))) - -/** ILI9325_FRAME_RATE_AND_COLOR_CTRL : (Offset: 0x2B) Frame Rate and - * Color Control */ -#define ILI9325_FRAME_RATE_AND_COLOR_CTRL (0x2Bu) -#define ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_POS 0 -#define ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_MSK (0xfu << \ - ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_POS) -#define ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS(value) (( \ - ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_MSK & \ - ((value) << ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS_POS))) - -/** ILI9325_GAMMA_CTL1 : (Offset: 0x30) Gamma Control 1 */ -#define ILI9325_GAMMA_CTL1 (0x30u) -#define ILI9325_GAMMA_CTL1_KP0_POS 0 -#define ILI9325_GAMMA_CTL1_KP0_MSK (0x7u << ILI9325_GAMMA_CTL1_KP0_POS) -#define ILI9325_GAMMA_CTL1_KP0(value) ((ILI9325_GAMMA_CTL1_KP0_MSK & \ - ((value) << ILI9325_GAMMA_CTL1_KP0_POS))) -#define ILI9325_GAMMA_CTL1_KP1_POS 8 -#define ILI9325_GAMMA_CTL1_KP1_MSK (0x7u << ILI9325_GAMMA_CTL1_KP1_POS) -#define ILI9325_GAMMA_CTL1_KP1(value) ((ILI9325_GAMMA_CTL1_KP1_MSK & \ - ((value) << ILI9325_GAMMA_CTL1_KP1_POS))) - -/** ILI9325_GAMMA_CTL2 : (Offset: 0x31) Gamma Control 2 */ -#define ILI9325_GAMMA_CTL2 (0x31u) -#define ILI9325_GAMMA_CTL2_KP2_POS 0 -#define ILI9325_GAMMA_CTL2_KP2_MSK (0x7u << ILI9325_GAMMA_CTL2_KP2_POS) -#define ILI9325_GAMMA_CTL2_KP2(value) ((ILI9325_GAMMA_CTL2_KP2_MSK & \ - ((value) << ILI9325_GAMMA_CTL2_KP2_POS))) -#define ILI9325_GAMMA_CTL2_KP3_POS 8 -#define ILI9325_GAMMA_CTL2_KP3_MSK (0x7u << ILI9325_GAMMA_CTL2_KP3_POS) -#define ILI9325_GAMMA_CTL2_KP3(value) ((ILI9325_GAMMA_CTL2_KP3_MSK & \ - ((value) << ILI9325_GAMMA_CTL2_KP3_POS))) - -/** ILI9325_GAMMA_CTL3 : (Offset: 0x32) Gamma Control 3 */ -#define ILI9325_GAMMA_CTL3 (0x32u) -#define ILI9325_GAMMA_CTL3_KP4_POS 0 -#define ILI9325_GAMMA_CTL3_KP4_MSK (0x7u << ILI9325_GAMMA_CTL3_KP4_POS) -#define ILI9325_GAMMA_CTL3_KP4(value) ((ILI9325_GAMMA_CTL3_KP4_MSK & \ - ((value) << ILI9325_GAMMA_CTL3_KP4_POS))) -#define ILI9325_GAMMA_CTL3_KP5_POS 8 -#define ILI9325_GAMMA_CTL3_KP5_MSK (0x7u << ILI9325_GAMMA_CTL3_KP5_POS) -#define ILI9325_GAMMA_CTL3_KP5(value) ((ILI9325_GAMMA_CTL3_KP5_MSK & \ - ((value) << ILI9325_GAMMA_CTL3_KP5_POS))) - -/** ILI9325_GAMMA_CTL4 : (Offset: 0x35) Gamma Control 4 */ -#define ILI9325_GAMMA_CTL4 (0x35u) -#define ILI9325_GAMMA_CTL4_RP0_POS 0 -#define ILI9325_GAMMA_CTL4_RP0_MSK (0x7u << ILI9325_GAMMA_CTL4_RP0_POS) -#define ILI9325_GAMMA_CTL4_RP0(value) ((ILI9325_GAMMA_CTL4_RP0_MSK & \ - ((value) << ILI9325_GAMMA_CTL4_RP0_POS))) -#define ILI9325_GAMMA_CTL4_RP1_POS 8 -#define ILI9325_GAMMA_CTL4_RP1_MSK (0x7u << ILI9325_GAMMA_CTL4_RP1_POS) -#define ILI9325_GAMMA_CTL4_RP1(value) ((ILI9325_GAMMA_CTL4_RP1_MSK & \ - ((value) << ILI9325_GAMMA_CTL4_RP1_POS))) - -/** ILI9325_GAMMA_CTL5 : (Offset: 0x36) Gamma Control 5 */ -#define ILI9325_GAMMA_CTL5 (0x36u) -#define ILI9325_GAMMA_CTL5_VRP0_POS 0 -#define ILI9325_GAMMA_CTL5_VRP0_MSK (0xfu << ILI9325_GAMMA_CTL5_VRP0_POS) -#define ILI9325_GAMMA_CTL5_VRP0(value) ((ILI9325_GAMMA_CTL5_VRP0_MSK & \ - ((value) << ILI9325_GAMMA_CTL5_VRP0_POS))) -#define ILI9325_GAMMA_CTL5_VRP1_POS 8 -#define ILI9325_GAMMA_CTL5_VRP1_MSK (0x1fu << ILI9325_GAMMA_CTL5_VRP1_POS) -#define ILI9325_GAMMA_CTL5_VRP1(value) ((ILI9325_GAMMA_CTL5_VRP1_MSK & \ - ((value) << ILI9325_GAMMA_CTL5_VRP1_POS))) - -/** ILI9325_GAMMA_CTL6 : (Offset: 0x37) Gamma Control 6*/ -#define ILI9325_GAMMA_CTL6 (0x37u) -#define ILI9325_GAMMA_CTL6_KN0_POS 0 -#define ILI9325_GAMMA_CTL6_KN0_MSK (0x7u << ILI9325_GAMMA_CTL6_KN0_POS) -#define ILI9325_GAMMA_CTL6_KN0(value) ((ILI9325_GAMMA_CTL6_KN0_MSK & \ - ((value) << ILI9325_GAMMA_CTL6_KN0_POS))) -#define ILI9325_GAMMA_CTL6_KN1_POS 8 -#define ILI9325_GAMMA_CTL6_KN1_MSK (0x7u << ILI9325_GAMMA_CTL6_KN1_POS) -#define ILI9325_GAMMA_CTL6_KN1(value) ((ILI9325_GAMMA_CTL6_KN1_MSK \ - & ((value) << ILI9325_GAMMA_CTL6_KN1_POS))) - -/** ILI9325_GAMMA_CTL7 : (Offset: 0x38) Gamma Control 7*/ -#define ILI9325_GAMMA_CTL7 (0x38u) -#define ILI9325_GAMMA_CTL7_KN2_POS 0 -#define ILI9325_GAMMA_CTL7_KN2_MSK (0x7u << ILI9325_GAMMA_CTL7_KN2_POS) -#define ILI9325_GAMMA_CTL7_KN2(value) ((ILI9325_GAMMA_CTL7_KN2_MSK & \ - ((value) << ILI9325_GAMMA_CTL7_KN2_POS))) -#define ILI9325_GAMMA_CTL7_KN3_POS 8 -#define ILI9325_GAMMA_CTL7_KN3_MSK (0x7u << ILI9325_GAMMA_CTL7_KN3_POS) -#define ILI9325_GAMMA_CTL7_KN3(value) ((ILI9325_GAMMA_CTL7_KN3_MSK & \ - ((value) << ILI9325_GAMMA_CTL7_KN3_POS))) - -/** ILI9325_GAMMA_CTL8 : (Offset: 0x39) Gamma Control 8*/ -#define ILI9325_GAMMA_CTL8 (0x39u) -#define ILI9325_GAMMA_CTL8_KN4_POS 0 -#define ILI9325_GAMMA_CTL8_KN4_MSK (0x7u << ILI9325_GAMMA_CTL8_KN4_POS) -#define ILI9325_GAMMA_CTL8_KN4(value) ((ILI9325_GAMMA_CTL8_KN4_MSK & \ - ((value) << ILI9325_GAMMA_CTL8_KN4_POS))) -#define ILI9325_GAMMA_CTL8_KN5_POS 8 -#define ILI9325_GAMMA_CTL8_KN5_MSK (0x7u << ILI9325_GAMMA_CTL8_KN5_POS) -#define ILI9325_GAMMA_CTL8_KN5(value) ((ILI9325_GAMMA_CTL8_KN5_MSK & \ - ((value) << ILI9325_GAMMA_CTL8_KN5_POS))) - -/** ILI9325_GAMMA_CTL9 : (Offset: 0x3C) Gamma Control 9*/ -#define ILI9325_GAMMA_CTL9 (0x3Cu) -#define ILI9325_GAMMA_CTL9_RN0_POS 0 -#define ILI9325_GAMMA_CTL9_RN0_MSK (0x7u << ILI9325_GAMMA_CTL9_RN0_POS) -#define ILI9325_GAMMA_CTL9_RN0(value) ((ILI9325_GAMMA_CTL9_RN0_MSK & \ - ((value) << ILI9325_GAMMA_CTL9_RN0_POS))) -#define ILI9325_GAMMA_CTL9_RN1_POS 8 -#define ILI9325_GAMMA_CTL9_RN1_MSK (0x7u << ILI9325_GAMMA_CTL9_RN1_POS) -#define ILI9325_GAMMA_CTL9_RN1(value) ((ILI9325_GAMMA_CTL9_RN1_MSK & \ - ((value) << ILI9325_GAMMA_CTL9_RN1_POS))) - -/** ILI9325_GAMMA_CTL10 : (Offset: 0x3D) Gamma Control 10*/ -#define ILI9325_GAMMA_CTL10 (0x3Du) -#define ILI9325_GAMMA_CTL10_VRN0_POS 0 -#define ILI9325_GAMMA_CTL10_VRN0_MSK (0xfu << ILI9325_GAMMA_CTL10_VRN0_POS) -#define ILI9325_GAMMA_CTL10_VRN0(value) ((ILI9325_GAMMA_CTL10_VRN0_MSK & \ - ((value) << ILI9325_GAMMA_CTL10_VRN0_POS))) -#define ILI9325_GAMMA_CTL10_VRN1_POS 8 -#define ILI9325_GAMMA_CTL10_VRN1_MSK (0x1fu << \ - ILI9325_GAMMA_CTL10_VRN1_POS) -#define ILI9325_GAMMA_CTL10_VRN1(value) ((ILI9325_GAMMA_CTL10_VRN1_MSK & \ - ((value) << ILI9325_GAMMA_CTL10_VRN1_POS))) - -/** - * ILI9325_HORIZONTAL_ADDR_START : (Offset: 0x50) Horizontal Address - * Start Position - */ -#define ILI9325_HORIZONTAL_ADDR_START (0x50u) -#define ILI9325_HORIZONTAL_ADDR_START_HSA_POS 0 -#define ILI9325_HORIZONTAL_ADDR_START_HSA_MSK (0xffu << \ - ILI9325_HORIZONTAL_ADDR_START_HSA_POS) -#define ILI9325_HORIZONTAL_ADDR_START_HSA(value) (( \ - ILI9325_HORIZONTAL_ADDR_START_HSA_MSK & \ - ((value) << ILI9325_HORIZONTAL_ADDR_START_HSA_POS))) - -/** - * ILI9325_HORIZONTAL_ADDR_END : (Offset: 0x51) Horizontal Address End - * Position - */ -#define ILI9325_HORIZONTAL_ADDR_END (0x51u) -#define ILI9325_HORIZONTAL_ADDR_END_HEA_POS 0 -#define ILI9325_HORIZONTAL_ADDR_END_HEA_MSK (0xffu << \ - ILI9325_HORIZONTAL_ADDR_END_HEA_POS) -#define ILI9325_HORIZONTAL_ADDR_END_HEA(value) (( \ - ILI9325_HORIZONTAL_ADDR_END_HEA_MSK & \ - ((value) << ILI9325_HORIZONTAL_ADDR_END_HEA_POS))) - -/** - * ILI9325_VERTICAL_ADDR_START : (Offset: 0x52) Vertical Address Start - * Position - */ -#define ILI9325_VERTICAL_ADDR_START (0x52u) -#define ILI9325_VERTICAL_ADDR_START_VSA_POS 0 -#define ILI9325_VERTICAL_ADDR_START_VSA_MSK (0x1ffu << \ - ILI9325_VERTICAL_ADDR_START_VSA_POS) -#define ILI9325_VERTICAL_ADDR_START_VSA(value) (( \ - ILI9325_VERTICAL_ADDR_START_VSA_MSK & \ - ((value) << ILI9325_VERTICAL_ADDR_START_VSA_POS))) - -/** - * ILI9325_VERTICAL_ADDR_END : (Offset: 0x53) Vertical Address End - * Position - */ -#define ILI9325_VERTICAL_ADDR_END (0x53u) -#define ILI9325_VERTICAL_ADDR_END_VEA_POS 0 -#define ILI9325_VERTICAL_ADDR_END_VEA_MSK (0x1ffu << \ - ILI9325_VERTICAL_ADDR_END_VEA_POS) -#define ILI9325_VERTICAL_ADDR_END_VEA(value) ((ILI9325_VERTICAL_ADDR_END_VEA_MSK \ - & ((value) << ILI9325_VERTICAL_ADDR_END_VEA_POS))) - -/** - * ILI9325_DRIVER_OUTPUT_CTRL2 : (Offset: 0x60) Driver Output - * Control 2 - */ -#define ILI9325_DRIVER_OUTPUT_CTRL2 (0x60u) -#define ILI9325_DRIVER_OUTPUT_CTRL2_SCN_POS 0 -#define ILI9325_DRIVER_OUTPUT_CTRL2_SCN_MSK (0x3fu << \ - ILI9325_DRIVER_OUTPUT_CTRL2_SCN_POS) -#define ILI9325_DRIVER_OUTPUT_CTRL2_SCN(value) (( \ - ILI9325_DRIVER_OUTPUT_CTRL2_SCN_MSK & \ - ((value) << ILI9325_DRIVER_OUTPUT_CTRL2_SCN_POS))) -#define ILI9325_DRIVER_OUTPUT_CTRL2_NL_POS 8 -#define ILI9325_DRIVER_OUTPUT_CTRL2_NL_MSK (0x3fu << \ - ILI9325_DRIVER_OUTPUT_CTRL2_NL_POS) -#define ILI9325_DRIVER_OUTPUT_CTRL2_NL(value) (( \ - ILI9325_DRIVER_OUTPUT_CTRL2_NL_MSK & \ - ((value) << ILI9325_DRIVER_OUTPUT_CTRL2_NL_POS))) -#define ILI9325_DRIVER_OUTPUT_CTRL2_GS (0x1u << 15) - -/** - * ILI9325_BASE_IMG_DISP_CTRL : (Offset: 0x61) Base Image Display - * Control - */ -#define ILI9325_BASE_IMG_DISP_CTRL (0x61u) -#define ILI9325_BASE_IMG_DISP_CTRL_REV (0x1u << 0) -#define ILI9325_BASE_IMG_DISP_CTRL_VLE (0x1u << 1) -#define ILI9325_BASE_IMG_DISP_CTRL_NDL (0x1u << 2) - -/** - * ILI9325_VERTICAL_SCROLL_CTRL : (Offset: 0x6A) Vertical Scroll - * Control - */ -#define ILI9325_VERTICAL_SCROLL_CTRL (0x6Au) -#define ILI9325_VERTICAL_SCROLL_CTRL_VL_POS 0 -#define ILI9325_VERTICAL_SCROLL_CTRL_VL_MSK (0x1ffu << \ - ILI9325_VERTICAL_SCROLL_CTRL_VL_POS) -#define ILI9325_VERTICAL_SCROLL_CTRL_VL(value) (( \ - ILI9325_VERTICAL_SCROLL_CTRL_VL_MSK & \ - ((value) << ILI9325_VERTICAL_SCROLL_CTRL_VL_POS))) - -/** - * ILI9325_PARTIAL_IMG1_DISP_POS : (Offset: 0x80) Partial Image 1 - * Display Position - */ -#define ILI9325_PARTIAL_IMG1_DISP_POS (0x80u) -#define ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_POS 0 -#define ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_MSK (0x1ffu << \ - ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_POS) -#define ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0(value) (( \ - ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_MSK & \ - ((value) << ILI9325_PARTIAL_IMG1_DISP_POS_PTDP0_POS))) - -/** - * ILI9325_PARTIAL_IMG1_AREA_START_LINE : (Offset: 0x81) Partial Image - * 1 Area (Start Line) - */ -#define ILI9325_PARTIAL_IMG1_AREA_START_LINE (0x81u) -#define ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_POS 0 -#define ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_MSK (0x1ffu << \ - ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_POS) -#define ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0(value) (( \ - ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_MSK & \ - ((value) << \ - ILI9325_PARTIAL_IMG1_AREA_START_LINE_PTSA0_POS))) - -/** - * ILI9325_PARTIAL_IMG1_AREA_END_LINE : (Offset: 0x82) Partial Image 1 - * Area (End Line) - */ -#define ILI9325_PARTIAL_IMG1_AREA_END_LINE (0x82u) -#define ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_POS 0 -#define ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_MSK (0x1ffu << \ - ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_POS) -#define ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0(value) (( \ - ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_MSK & \ - ((value) << \ - ILI9325_PARTIAL_IMG1_AREA_END_LINE_PTEA0_POS))) - -/** - * ILI9325_PARTIAL_IMG2_DISP_POS : (Offset: 0x83) Partial Image 2 - * Display Position - */ -#define ILI9325_PARTIAL_IMG2_DISP_POS (0x83u) -#define ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_POS 0 -#define ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_MSK (0x1ffu << \ - ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_POS) -#define ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1(value) (( \ - ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_MSK & \ - ((value) << ILI9325_PARTIAL_IMG2_DISP_POS_PTDP1_POS))) - -/** - * ILI9325_PARTIAL_IMG2_AREA_START_LINE : (Offset: 0x84) Partial Image - * 2 Area (Start Line) - */ -#define ILI9325_PARTIAL_IMG2_AREA_START_LINE (0x84u) -#define ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_POS 0 -#define ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_MSK (0x1ffu << \ - ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_POS) -#define ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1(value) (( \ - ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_MSK & \ - ((value) << \ - ILI9325_PARTIAL_IMG2_AREA_START_LINE_PTSA1_POS))) - -/** - * ILI9325_PARTIAL_IMG2_AREA_END_LINE : (Offset: 0x85) Partial Image 2 - * Area (End Line) - */ -#define ILI9325_PARTIAL_IMG2_AREA_END_LINE (0x85u) -#define ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_POS 0 -#define ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_MSK (0x1ffu << \ - ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_POS) -#define ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1(value) (( \ - ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_MSK & \ - ((value) << \ - ILI9325_PARTIAL_IMG2_AREA_END_LINE_PTEA1_POS))) - -/** - * ILI9325_PANEL_INTERFACE_CTRL1 : (Offset: 0x90) Panel Interface - * Control 1 - */ -#define ILI9325_PANEL_INTERFACE_CTRL1 (0x90u) -#define ILI9325_PANEL_INTERFACE_CTRL1_RTNI_POS 0 -#define ILI9325_PANEL_INTERFACE_CTRL1_RTNI_MSK (0x1fu << \ - ILI9325_PANEL_INTERFACE_CTRL1_RTNI_POS) -#define ILI9325_PANEL_INTERFACE_CTRL1_RTNI(value) (( \ - ILI9325_PANEL_INTERFACE_CTRL1_RTNI_MSK & \ - ((value) << ILI9325_PANEL_INTERFACE_CTRL1_RTNI_POS))) -#define ILI9325_PANEL_INTERFACE_CTRL1_DIVI_POS 8 -#define ILI9325_PANEL_INTERFACE_CTRL1_DIVI_MSK (0x3u << \ - ILI9325_PANEL_INTERFACE_CTRL1_DIVI_POS) -#define ILI9325_PANEL_INTERFACE_CTRL1_DIVI(value) (( \ - ILI9325_PANEL_INTERFACE_CTRL1_DIVI_MSK & \ - ((value) << ILI9325_PANEL_INTERFACE_CTRL1_DIVI_POS))) - -/** - * ILI9325_PANEL_INTERFACE_CTRL2 : (Offset: 0x92) Panel Interface - * Control 2 - */ -#define ILI9325_PANEL_INTERFACE_CTRL2 (0x92u) -#define ILI9325_PANEL_INTERFACE_CTRL2_NOWI_POS 8 -#define ILI9325_PANEL_INTERFACE_CTRL2_NOWI_MSK (0x7u << \ - ILI9325_PANEL_INTERFACE_CTRL2_NOWI_POS) -#define ILI9325_PANEL_INTERFACE_CTRL2_NOWI(value) (( \ - ILI9325_PANEL_INTERFACE_CTRL2_NOWI_MSK & \ - ((value) << ILI9325_PANEL_INTERFACE_CTRL2_NOWI_POS))) - -/** - * ILI9325_PANEL_INTERFACE_CTRL4 : (Offset: 0x95) Panel Interface - * Control 4 - */ -#define ILI9325_PANEL_INTERFACE_CTRL4 (0x95u) -#define ILI9325_PANEL_INTERFACE_CTRL4_RTNE_POS 0 -#define ILI9325_PANEL_INTERFACE_CTRL4_RTNE_MSK (0x3fu << \ - ILI9325_PANEL_INTERFACE_CTRL4_RTNE_POS) -#define ILI9325_PANEL_INTERFACE_CTRL4_RTNE(value) (( \ - ILI9325_PANEL_INTERFACE_CTRL4_RTNE_MSK & \ - ((value) << ILI9325_PANEL_INTERFACE_CTRL4_RTNE_POS))) -#define ILI9325_PANEL_INTERFACE_CTRL4_DIVE_POS 8 -#define ILI9325_PANEL_INTERFACE_CTRL4_DIVE_MSK (0x3u << \ - ILI9325_PANEL_INTERFACE_CTRL4_DIVE_POS) -#define ILI9325_PANEL_INTERFACE_CTRL4_DIVE(value) (( \ - ILI9325_PANEL_INTERFACE_CTRL4_DIVE_MSK & \ - ((value) << ILI9325_PANEL_INTERFACE_CTRL4_DIVE_POS))) - -/** ILI9325_OTP_VCM_PROG_CTRL : (Offset: 0xA1) OTP VCM Programming Control */ -#define ILI9325_OTP_VCM_PROG_CTRL (0xA1u) -#define ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_POS 0 -#define ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_MSK (0x3fu << \ - ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_POS) -#define ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP(value) (( \ - ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_MSK & \ - ((value) << ILI9325_OTP_VCM_PROG_CTRL_VCM_OTP_POS))) -#define ILI9325_OTP_VCM_PROG_CTRL_OTP_PGM_EN (0x1u << 11) - -/** ILI9325_OTP_VCM_STATUS_AND_ENABLE : (Offset: 0xA2) OTP VCM Status - * and Enable */ -#define ILI9325_OTP_VCM_STATUS_AND_ENABLE (0xA2u) -#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_EN (0x1u << 0) -#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_POS 8 -#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_MSK (0x3fu << \ - ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_POS) -#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D(value) (( \ - ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_MSK & ((value) << \ - ILI9325_OTP_VCM_STATUS_AND_ENABLE_VCM_D_POS))) -#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_POS 14 -#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_MSK (0x3u << \ - ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_POS) -#define ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT(value) (( \ - ILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_MSK & \ - ((value) << \ - IILI9325_OTP_VCM_STATUS_AND_ENABLE_PGM_CNT_POS))) - -/** ILI9325_OTP_PROG_ID_KEY : (Offset: 0xA5) OTP Programming ID Key */ -#define ILI9325_OTP_PROG_ID_KEY (0xA5u) -#define ILI9325_OTP_PROG_ID_KEY_KEY_POS 0 -#define ILI9325_OTP_PROG_ID_KEY_KEY_MSK (0xffffu << \ - ILI9325_OTP_PROG_ID_KEY_KEY_POS) -#define ILI9325_OTP_PROG_ID_KEY_KEY(value) ((ILI9325_OTP_PROG_ID_KEY_KEY_MSK & \ - ((value) << ILI9325_OTP_PROG_ID_KEY_KEY_POS))) - -/** @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/** @endcond */ - -#endif /* ILI9325_REGS_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili9341_regs.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili9341_regs.h deleted file mode 100644 index ccbff8088..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili9341_regs.h +++ /dev/null @@ -1,245 +0,0 @@ -/** - * \file - * - * \brief registers definition for ili9341 TFT display component. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ILI9341_REGS_H_INCLUDED -#define ILI9341_REGS_H_INCLUDED - -/** @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/** @endcond */ - -/** ili9341 LCD Registers */ - -/** Level 1 Commands (from the display Datasheet) */ -/** Nop operation*/ -#define ILI9341_CMD_NOP 0x00 -/** Software reset*/ -#define ILI9341_CMD_SOFTWARE_RESET 0x01 -/** Read Display Identification information*/ -#define ILI9341_CMD_READ_DISP_ID 0x04 -/** Read display status*/ -#define ILI9341_CMD_READ_DISP_STATUS 0x09 -/** Read display power mode*/ -#define ILI9341_CMD_READ_DISP_POWER_MODE 0x0A -/** Read display MADCTL*/ -#define ILI9341_CMD_READ_DISP_MADCTRL 0x0B -/** Read display pixel format*/ -#define ILI9341_CMD_READ_DISP_PIXEL_FORMAT 0x0C -/** Read display image format*/ -#define ILI9341_CMD_READ_DISP_IMAGE_FORMAT 0x0D -/** Read display signal mode*/ -#define ILI9341_CMD_READ_DISP_SIGNAL_MODE 0x0E -/** read display self-diagnostic resutl*/ -#define ILI9341_CMD_READ_DISP_SELF_DIAGNOSTIC 0x0F -/** Enter sleep mode*/ -#define ILI9341_CMD_ENTER_SLEEP_MODE 0x10 -/** Sleep out*/ -#define ILI9341_CMD_SLEEP_OUT 0x11 -/** Partial mode on*/ -#define ILI9341_CMD_PARTIAL_MODE_ON 0x12 -/** Normal display mode on*/ -#define ILI9341_CMD_NORMAL_DISP_MODE_ON 0x13 -/** Display inversion off*/ -#define ILI9341_CMD_DISP_INVERSION_OFF 0x20 -/** Display inversion on*/ -#define ILI9341_CMD_DISP_INVERSION_ON 0x21 -/** Gamma set*/ -#define ILI9341_CMD_GAMMA_SET 0x26 -/** Display off*/ -#define ILI9341_CMD_DISPLAY_OFF 0x28 -/** Display on*/ -#define ILI9341_CMD_DISPLAY_ON 0x29 -/** Column address set*/ -#define ILI9341_CMD_COLUMN_ADDRESS_SET 0x2A -/** Page address set*/ -#define ILI9341_CMD_PAGE_ADDRESS_SET 0x2B -/** Memory write*/ -#define ILI9341_CMD_MEMORY_WRITE 0x2C -/** Color set*/ -#define ILI9341_CMD_COLOR_SET 0x2D -/** Memory read*/ -#define ILI9341_CMD_MEMORY_READ 0x2E -/** Partial area*/ -#define ILI9341_CMD_PARTIAL_AREA 0x30 -/** Vertical scrolling definition*/ -#define ILI9341_CMD_VERT_SCROLL_DEFINITION 0x33 -/** Tearing effect line off*/ -#define ILI9341_CMD_TEARING_EFFECT_LINE_OFF 0x34 -/** Tearing effect line on*/ -#define ILI9341_CMD_TEARING_EFFECT_LINE_ON 0x35 - -/** Memory Access control*/ -#define ILI9341_CMD_MEMORY_ACCESS_CONTROL 0x36 -#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_MY (0x1u << 7) -#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_MX (0x1u << 6) -#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_MV (0x1u << 5) -#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_ML (0x1u << 4) -#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_BGR (0x1u << 3) -#define ILI9341_CMD_MEMORY_ACCESS_CONTROL_MH (0x1u << 2) - -/** Vetical scrolling start address*/ -#define ILI9341_CMD_VERT_SCROLL_START_ADDRESS 0x37 -/** Idle mode off*/ -#define ILI9341_CMD_IDLE_MODE_OFF 0x38 -/** Idle mode on*/ -#define ILI9341_CMD_IDLE_MODE_ON 0x39 -/** Pixel Format set*/ -#define ILI9341_CMD_PIXEL_FORMAT_SET 0x3A -/** write memory continue*/ -#define ILI9341_CMD_WRITE_MEMORY_CONTINUE 0x3C -/** Read memory continue*/ -#define ILI9341_CMD_READ_MEMORY_CONTINUE 0x3E -/** set tear scanline*/ -#define ILI9341_CMD_SET_TEAR_SCANLINE 0x44 -/** get scanline*/ -#define ILI9341_CMD_GET_SCANLINE 0x45 -/** write display brightness*/ -#define ILI9341_CMD_WRITE_DISPLAY_BRIGHTNESS 0x51 -/** read display brightness*/ -#define ILI9341_CMD_READ_DISPLAY_BRIGHTNESS 0x52 -/** write control display*/ -#define ILI9341_CMD_WRITE_CTRL_DISPLAY 0x53 -/** read control display*/ -#define ILI9341_CMD_READ_CTRL_DISPLAY 0x54 -/** write content adaptive brightness control*/ -#define ILI9341_CMD_WRITE_CONTENT_ADAPT_BRIGHTNESS 0x55 -/** read content adaptive brightness control*/ -#define ILI9341_CMD_READ_CONTENT_ADAPT_BRIGHTNESS 0x56 -/** write CABC minimum brightness*/ -#define ILI9341_CMD_WRITE_MIN_CAB_LEVEL 0x5E -/** read CABC minimum brightness*/ -#define ILI9341_CMD_READ_MIN_CAB_LEVEL 0x5F -/** Read ID1*/ -#define ILI9341_CMD_READ_ID1 0xDA -/** Read ID2*/ -#define ILI9341_CMD_READ_ID2 0xDB -/** Read ID3*/ -#define ILI9341_CMD_READ_ID3 0xDC - -/** Level 2 Commands (from the display Datasheet) */ -/** RGB interface signal control*/ -#define ILI9341_CMD_RGB_SIGNAL_CONTROL 0xB0 -/** frame control*/ -#define ILI9341_CMD_FRAME_RATE_CONTROL_NORMAL 0xB1 -/** frame control in idle mode*/ -#define ILI9341_CMD_FRAME_RATE_CONTROL_IDLE_8COLOR 0xB2 -/** frame control in partial mode*/ -#define ILI9341_CMD_FRAME_RATE_CONTROL_PARTIAL 0xB3 -/** display inversion control*/ -#define ILI9341_CMD_DISPLAY_INVERSION_CONTROL 0xB4 -/** blanking porch control*/ -#define ILI9341_CMD_BLANKING_PORCH_CONTROL 0xB5 -/** display function control*/ -#define ILI9341_CMD_DISPLAY_FUNCTION_CTL 0xB6 -#define ILI9341_DISP_FUNC_CTL_REV (0x1u << 7) -#define ILI9341_DISP_FUNC_CTL_GS (0x1u << 6) -#define ILI9341_DISP_FUNC_CTL_SS (0x1u << 5) -#define ILI9341_DISP_FUNC_CTL_SM (0x1u << 4) -#define ILI9341_DISP_FUNC_CTL_ISC_POS 0 -#define ILI9341_DISP_FUNC_CTL_ISC_MSK (0x0F << 0) -#define ILI9341_DISP_FUNC_CTL_ISC(value) \ - (ILI9341_DISP_FUNC_CTL_ISC_MSK & \ - (value << ILI9341_DISP_FUNC_CTL_ISC_POS)) - -/** entry mode set*/ -#define ILI9341_CMD_ENTRY_MODE_SET 0xB7 -/** backlight control1*/ -#define ILI9341_CMD_BACKLIGHT_CONTROL_1 0xB8 -/** backlight control2*/ -#define ILI9341_CMD_BACKLIGHT_CONTROL_2 0xB9 -/** backlight control3*/ -#define ILI9341_CMD_BACKLIGHT_CONTROL_3 0xBA -/** backlight control 4*/ -#define ILI9341_CMD_BACKLIGHT_CONTROL_4 0xBB -/** backlight control 5*/ -#define ILI9341_CMD_BACKLIGHT_CONTROL_5 0xBC -/** backlight control 7*/ -#define ILI9341_CMD_BACKLIGHT_CONTROL_7 0xBE -/** backlight control 8*/ -#define ILI9341_CMD_BACKLIGHT_CONTROL_8 0xBF -/** power control 1*/ -#define ILI9341_CMD_POWER_CONTROL_1 0xC0 -/** power control 2*/ -#define ILI9341_CMD_POWER_CONTROL_2 0xC1 -/** VCOM control 1*/ -#define ILI9341_CMD_VCOM_CONTROL_1 0xC5 -/** VCOM control 2*/ -#define ILI9341_CMD_VCOM_CONTROL_2 0xC7 -/** Power control A*/ -#define ILI9341_CMD_POWER_CONTROL_A 0xCB -/** Power control B*/ -#define ILI9341_CMD_POWER_CONTROL_B 0xCF -/** NV memory write*/ -#define ILI9341_CMD_NVMEM_WRITE 0xD0 -/** NV memory protection key*/ -#define ILI9341_CMD_NVMEM_PROTECTION_KEY 0xD1 -/** NV memory status read*/ -#define ILI9341_CMD_NVMEM_STATUS_READ 0xD2 -/** Read ID4*/ -#define ILI9341_CMD_READ_ID4 0xD3 -/** positive gamma correction*/ -#define ILI9341_CMD_POSITIVE_GAMMA_CORRECTION 0xE0 -/** negative gamma correction*/ -#define ILI9341_CMD_NEGATIVE_GAMMA_CORRECTION 0xE1 -/** digital gamma control 1*/ -#define ILI9341_CMD_DIGITAL_GAMMA_CONTROL_1 0xE2 -/** digital gamma control 2*/ -#define ILI9341_CMD_DIGITAL_GAMMA_CONTROL_2 0xE3 -/** driver timing control A*/ -#define ILI9341_CMD_DRIVER_TIMING_CTL_A 0xE8 -/** driver timing control B*/ -#define ILI9341_CMD_DRIVER_TIMING_CTL_B 0xEA -/** power-on sequence control*/ -#define ILI9341_CMD_POWER_ON_SEQUENCE_CONTROL 0xED -/** enable 3g gamma control*/ -#define ILI9341_CMD_ENABLE_3_GAMMA_CONTROL 0xF2 -/** Interface control*/ -#define ILI9341_CMD_INTERFACE_CONTROL 0xF6 -/** pump ration control*/ -#define ILI9341_CMD_PUMP_RATIO_CONTROL 0xF7 - -#endif /* ILI9341_REGS_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili93xx.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili93xx.c deleted file mode 100644 index fb529482c..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili93xx.c +++ /dev/null @@ -1,1851 +0,0 @@ -/** - * \file - * - * \brief API driver for ILI93XX TFT display component. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \defgroup ili93xx_display_group Display - ILI93XX Controller - * - * Low-level driver for the ILI93XX LCD controller. This driver provides access - * to the main features of the ILI93XX controller. - * Now ILI9325 and ILI9341 are supported. - * - * \{ - */ - -#include -#include -#include -#include -#include "ili93xx.h" -#include "ili9341_regs.h" -#include "ili9325_regs.h" - -/** Device type*/ -static uint8_t g_uc_device_type = 0; - -/** Pixel cache used to speed up communication */ -#define LCD_DATA_CACHE_SIZE ILI93XX_LCD_WIDTH - -/** LCD X-axis and Y-axis length */ -static uint32_t g_ul_lcd_x_length = ILI93XX_LCD_WIDTH; -static uint32_t g_ul_lcd_y_length = ILI93XX_LCD_HEIGHT; - -static ili93xx_color_t g_ul_pixel_cache[LCD_DATA_CACHE_SIZE]; - -static volatile ili93xx_coord_t limit_start_x, limit_start_y; -static volatile ili93xx_coord_t limit_end_x, limit_end_y; - -/** Global variable describing the font size used by the driver */ -const struct ili93xx_font gfont = {10, 14}; - -/** - * Character set table for font 10x14 - * Coding format: - * Char height is 14 bits, which is coded using 2 bytes per column - * (2 unused bits). - * Char width is 10 bits. - */ -const uint8_t p_uc_charset10x14[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC, - 0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, - 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC, - 0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0, - 0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0, - 0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18, - 0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC, - 0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00, - 0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78, - 0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18, - 0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8, - 0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0, - 0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, - 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00, - 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0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C, - 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, - 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, - 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC -}; - -/** - * \brief Prepare to write GRAM data for ili93xx. - */ -static void ili93xx_write_ram_prepare(void) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** Write Data to GRAM (R22h) */ - LCD_IR(0); - LCD_IR(ILI9325_GRAM_DATA_REG); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - /** memory write command (R2Ch)*/ - LCD_IR(ILI9341_CMD_MEMORY_WRITE); - LCD_IR(0); - LCD_IR(ILI9341_CMD_WRITE_MEMORY_CONTINUE); - } -} - -/** - * \brief Write data to LCD GRAM. - * - * \param ul_color 24-bits RGB color. - */ -static void ili93xx_write_ram(ili93xx_color_t ul_color) -{ - LCD_WD((ul_color >> 16) & 0xFF); - LCD_WD((ul_color >> 8) & 0xFF); - LCD_WD(ul_color & 0xFF); -} - -/** - * \brief Write multiple data in buffer to LCD controller for ili93xx. - * - * \param p_ul_buf data buffer. - * \param ul_size size in pixels. - */ -static void ili93xx_write_ram_buffer(const ili93xx_color_t *p_ul_buf, - uint32_t ul_size) -{ - uint32_t ul_addr; - for (ul_addr = 0; ul_addr < (ul_size - ul_size % 8); ul_addr += 8) { - ili93xx_write_ram(p_ul_buf[ul_addr]); - ili93xx_write_ram(p_ul_buf[ul_addr + 1]); - ili93xx_write_ram(p_ul_buf[ul_addr + 2]); - ili93xx_write_ram(p_ul_buf[ul_addr + 3]); - ili93xx_write_ram(p_ul_buf[ul_addr + 4]); - ili93xx_write_ram(p_ul_buf[ul_addr + 5]); - ili93xx_write_ram(p_ul_buf[ul_addr + 6]); - ili93xx_write_ram(p_ul_buf[ul_addr + 7]); - } - for (; ul_addr < ul_size; ul_addr++) { - ili93xx_write_ram(p_ul_buf[ul_addr]); - } -} - -/** - * \brief Write a word (16bits)to LCD Register. - * - * \param uc_reg register address. - * \param us_data data to be written. - */ -static void ili93xx_write_register_word(uint8_t uc_reg, uint16_t us_data) -{ - LCD_IR(0); - LCD_IR(uc_reg); - LCD_WD((us_data >> 8) & 0xFF); - LCD_WD(us_data & 0xFF); -} - -/** - * \brief Write data to LCD Register for ili93xx. - * - * \param uc_reg register address. - * \param us_data data to be written. - */ -static void ili93xx_write_register(uint8_t uc_reg, uint8_t *p_data, - uint8_t uc_datacnt) -{ -uint8_t i; - - LCD_IR(0); - LCD_IR(uc_reg); - for (i = 0; i < uc_datacnt; i++) { - LCD_WD(p_data[i]); - } -} - -/** - * \brief Prepare to read GRAM data for ili93xx. - */ -static void ili93xx_read_ram_prepare(void) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - LCD_IR(0); - /** Write Data to GRAM (R22h) */ - LCD_IR(ILI9325_GRAM_DATA_REG); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - LCD_IR(0); - /** Write Data to GRAM (R2Eh) */ - LCD_IR(ILI9341_CMD_MEMORY_READ); - } -} - -/** - * \brief Read data to LCD GRAM for ili93xx. - * - * \note For ili9325, because pixel data LCD GRAM is 18-bits, so convertion - * to RGB 24-bits will cause low color bit lose. - * - * \return color 24-bits RGB color. - */ -static uint32_t ili93xx_read_ram(void) -{ - uint8_t value[3]; - uint32_t color; - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** dummy read*/ - value[0] = LCD_RD(); - value[1] = LCD_RD(); - /** data upper byte*/ - value[0] = LCD_RD(); - /** data lower byte */ - value[1] = LCD_RD(); - - /** Convert RGB565 to RGB888 */ - /** For BGR format */ - color = ((value[0] & 0xF8)) | ((value[0] & 0x07) << 13) | - ((value[1] & 0xE0) << 5) | - ((value[1] & 0x1F) << 19); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - /** dummy read */ - value[0] = LCD_RD(); - /** the highest byte - R byte*/ - value[0] = LCD_RD(); - /** the middle byte - G byte*/ - value[1] = LCD_RD(); - /** the lowest byte - B byte*/ - value[2] = LCD_RD(); - /** combine R, G, B byte to a color value */ - color = (value[0] << 16) | (value[1] << 8) | value[2]; - } - - return color; -} - -/** - * \brief Read data from LCD Register. - * - * \param uc_reg register address. - * \param p_data the pointer to the read data. - * \param uc_datacnt the number of the read data - */ -static void ili93xx_read_register(uint8_t uc_reg, uint8_t *p_data, - uint8_t uc_datacnt) -{ -uint8_t i; - - LCD_IR(0); - LCD_IR(uc_reg); - - for (i = 0; i < uc_datacnt; i++) { - p_data[i] = LCD_RD(); - } -} - -/** - * \brief Delay function. - */ -static void ili93xx_delay(uint32_t ul_ms) -{ - volatile uint32_t i; - - for (i = 0; i < ul_ms; i++) { - for (i = 0; i < 100000; i++) { - } - } -} - -/** - * \brief Check box coordinates. - * - * \param p_ul_x1 X coordinate of upper-left corner on LCD. - * \param p_ul_y1 Y coordinate of upper-left corner on LCD. - * \param p_ul_x2 X coordinate of lower-right corner on LCD. - * \param p_ul_y2 Y coordinate of lower-right corner on LCD. - */ -static void ili93xx_check_box_coordinates(uint32_t *p_ul_x1, uint32_t *p_ul_y1, - uint32_t *p_ul_x2, uint32_t *p_ul_y2) -{ - uint32_t dw; - - if (*p_ul_x1 >= g_ul_lcd_x_length) { - *p_ul_x1 = g_ul_lcd_x_length - 1; - } - - if (*p_ul_x2 >= g_ul_lcd_x_length) { - *p_ul_x2 = g_ul_lcd_x_length - 1; - } - - if (*p_ul_y1 >= g_ul_lcd_y_length) { - *p_ul_y1 = g_ul_lcd_y_length - 1; - } - - if (*p_ul_y2 >= g_ul_lcd_y_length) { - *p_ul_y2 = g_ul_lcd_y_length - 1; - } - - if (*p_ul_x1 > *p_ul_x2) { - dw = *p_ul_x1; - *p_ul_x1 = *p_ul_x2; - *p_ul_x2 = dw; - } - - if (*p_ul_y1 > *p_ul_y2) { - dw = *p_ul_y1; - *p_ul_y1 = *p_ul_y2; - *p_ul_y2 = dw; - } -} - -/** - * \brief Read device ID to idenfity the device - * ILI9325 device ID locates in Device Code Read (R00h) register. - * ILI9341 device ID locates in Read ID4 (RD3h) register. - * - * \return 0 if secceed in identifying device; otherwise fails. - */ -uint8_t ili93xx_device_type_identify(void) -{ - uint8_t paratable[6]; - uint16_t chipid; - - /** Read ID4 (RD4h) register to get device code for ILI9341*/ - ili93xx_read_register(ILI9341_CMD_READ_ID4, paratable, 4); - chipid = ((uint16_t)paratable[2] << 8) + paratable[3]; - - if (chipid == ILI9341_DEVICE_CODE) { - g_uc_device_type = DEVICE_TYPE_ILI9341; - return 0; - } - - /** Driver Code Read (R00h) for ILI9325*/ - ili93xx_read_register(ILI9325_DEVICE_CODE_REG, paratable, 2); - chipid = ((uint16_t)paratable[0] << 8) + paratable[1]; - if (chipid == ILI9325_DEVICE_CODE) { - g_uc_device_type = DEVICE_TYPE_ILI9325; - return 0; - } - - return 1; -} - -/** - * \brief Initialize the ILI93XX lcd driver. - * - * \note Make sure below works have been done before calling ili93xx_init() - * 1. ILI93xx related Pins have been initialized correctly. - * 2. SMC has been configured correctly for access ILI93xx (8-bit system - * interface for now). - * - * \param p_opt pointer to ILI93xx option structure. - * - * \return 0 if initialization succeeds, otherwise fails. - */ -uint32_t ili93xx_init(struct ili93xx_opt_t *p_opt) -{ - uint8_t paratable[15]; - - /** Identify the LCD driver device*/ - if (ili93xx_device_type_identify() != 0) { - return 1; - } - - g_ul_lcd_x_length = ILI93XX_LCD_WIDTH; - g_ul_lcd_y_length = ILI93XX_LCD_HEIGHT; - - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** Turn off LCD */ - ili93xx_write_register_word(ILI9325_DISP_CTRL1, ILI9325_DISP_CTRL1_GON | - ILI9325_DISP_CTRL1_DTE | ILI9325_DISP_CTRL1_D(0x03)); - - /** Start initial sequence */ - /** Disable sleep and standby mode*/ - ili93xx_write_register_word(ILI9325_POWER_CTRL1, 0x0000); - /** Start internal OSC */ - ili93xx_write_register_word(ILI9325_START_OSC_CTRL, - ILI9325_START_OSC_CTRL_EN); - /** Set SS bit and direction output from S720 to S1 */ - ili93xx_write_register_word(ILI9325_DRIVER_OUTPUT_CTRL1, - ILI9325_DRIVER_OUTPUT_CTRL1_SS); - /** Set 1 line inversion */ - ili93xx_write_register_word(ILI9325_LCD_DRIVING_CTRL, - ILI9325_LCD_DRIVING_CTRL_BIT10 | ILI9325_LCD_DRIVING_CTRL_EOR - | ILI9325_LCD_DRIVING_CTRL_BC0); - /** Disable resizing feature */ - ili93xx_write_register_word(ILI9325_RESIZE_CTRL, 0x0000); - /** Set the back porch and front porch */ - ili93xx_write_register_word(ILI9325_DISP_CTRL2, - ILI9325_DISP_CTRL2_BP( - 0x07) | ILI9325_DISP_CTRL2_FP(0x02)); - /** Set non-display area refresh cycle ISC[3:0] */ - ili93xx_write_register_word(ILI9325_DISP_CTRL3, 0x0000); - /** Disable FMARK function */ - ili93xx_write_register_word(ILI9325_DISP_CTRL4, 0x0000); - /** 18-bit RGB interface and writing display data by system - *interface */ - ili93xx_write_register_word(ILI9325_RGB_DISP_INTERFACE_CTRL1, - 0x0000); - /** Set the output position of frame cycle */ - ili93xx_write_register_word(ILI9325_FRAME_MAKER_POS, 0x0000); - /** RGB interface polarity */ - ili93xx_write_register_word(ILI9325_RGB_DISP_INTERFACE_CTRL2, - 0x0000); - - /** Power on sequence */ - /** Disable sleep and standby mode */ - ili93xx_write_register_word(ILI9325_POWER_CTRL1, 0x0000); - - /** - * Selects the operating frequency of the step-up circuit 1,2 - * and Sets the ratio factor of Vci. - */ - ili93xx_write_register_word(ILI9325_POWER_CTRL2, 0x0000); - /** Set VREG1OUT voltage */ - ili93xx_write_register_word(ILI9325_POWER_CTRL3, 0x0000); - /** Set VCOM amplitude */ - ili93xx_write_register_word(ILI9325_POWER_CTRL4, 0x0000); - ili93xx_delay(200); - - /** Enable power supply and source driver */ - - /** - * Adjusts the constant current and Sets the factor used - * in the step-up circuits. - */ - ili93xx_write_register_word(ILI9325_POWER_CTRL1, - ILI9325_POWER_CTRL1_SAP | ILI9325_POWER_CTRL1_BT(0x02) | - ILI9325_POWER_CTRL1_APE | - ILI9325_POWER_CTRL1_AP(0x01)); - - /** - * Select the operating frequency of the step-up circuit 1,2 and - * Sets the ratio factor of Vci - */ - ili93xx_write_register_word(ILI9325_POWER_CTRL2, - ILI9325_POWER_CTRL2_DC1(0x02) | - ILI9325_POWER_CTRL2_DC0(0x02) | ILI9325_POWER_CTRL2_VC(0x07)); - ili93xx_delay(50); - /** Internal reference voltage= Vci */ - ili93xx_write_register_word(ILI9325_POWER_CTRL3, - ILI9325_POWER_CTRL3_PON | ILI9325_POWER_CTRL3_VRH(0x0B)); - ili93xx_delay(50); - /** Set VDV[4:0] for VCOM amplitude */ - ili93xx_write_register_word(ILI9325_POWER_CTRL4, - ILI9325_POWER_CTRL4_VDV(0x11)); - /** Set VCM[5:0] for VCOMH */ - ili93xx_write_register_word(ILI9325_POWER_CTRL7, - ILI9325_POWER_CTRL7_VCM(0x19)); - /** Set Frame Rate */ - ili93xx_write_register_word(ILI9325_FRAME_RATE_AND_COLOR_CTRL, - ILI9325_FRAME_RATE_AND_COLOR_CTRL_FRS(0x0D)); - ili93xx_delay(50); - - /** Adjust the Gamma Curve */ - ili93xx_write_register_word(ILI9325_GAMMA_CTL1, 0x0000); - ili93xx_write_register_word(ILI9325_GAMMA_CTL2, - ILI9325_GAMMA_CTL2_KP3(0x02) | - ILI9325_GAMMA_CTL2_KP2(0x04)); - ili93xx_write_register_word(ILI9325_GAMMA_CTL3, - ILI9325_GAMMA_CTL3_KP5(0x02) | - ILI9325_GAMMA_CTL3_KP4(0x00)); - ili93xx_write_register_word(ILI9325_GAMMA_CTL4, - ILI9325_GAMMA_CTL4_RP1(0x00) | - ILI9325_GAMMA_CTL4_RP0(0x07)); - ili93xx_write_register_word(ILI9325_GAMMA_CTL5, - ILI9325_GAMMA_CTL5_VRP1(0x14) | - ILI9325_GAMMA_CTL5_VRP0(0x04)); - ili93xx_write_register_word(ILI9325_GAMMA_CTL6, - ILI9325_GAMMA_CTL6_KN1(0x07) | - ILI9325_GAMMA_CTL6_KN0(0x05)); - ili93xx_write_register_word(ILI9325_GAMMA_CTL7, - ILI9325_GAMMA_CTL7_KN3(0x03) | - ILI9325_GAMMA_CTL7_KN2(0x05)); - ili93xx_write_register_word(ILI9325_GAMMA_CTL8, - ILI9325_GAMMA_CTL8_KN5(0x07) | - ILI9325_GAMMA_CTL8_KN4(0x07)); - ili93xx_write_register_word(ILI9325_GAMMA_CTL9, - ILI9325_GAMMA_CTL9_RN1(0x07) | - ILI9325_GAMMA_CTL9_RN0(0x01)); - ili93xx_write_register_word(ILI9325_GAMMA_CTL10, - ILI9325_GAMMA_CTL10_VRN1(0x00) | - ILI9325_GAMMA_CTL10_VRN0(0x0E)); - /** - * Use the high speed write mode (HWM=1) - * When TRI = 1, data are transferred to the internal RAM in - * 8-bit x 3 transfers mode via the 8-bit interface. - * DFM Set the mode of transferring data to the internal RAM - * when TRI = 1. - * I/D[1:0] = 11 Horizontal : increment Vertical : increment, - * AM=0:Horizontal - */ - ili93xx_write_register_word(ILI9325_ENTRY_MODE, - ILI9325_ENTRY_MODE_TRI | ILI9325_ENTRY_MODE_DFM | - ILI9325_ENTRY_MODE_ID(0x01) | ILI9325_ENTRY_MODE_BGR); - /** - * Sets the number of lines to drive the LCD at an interval of 8 - * lines. The scan direction is from G320 to G1 - */ - ili93xx_write_register_word(ILI9325_DRIVER_OUTPUT_CTRL2, - ILI9325_DRIVER_OUTPUT_CTRL2_GS | - ILI9325_DRIVER_OUTPUT_CTRL2_NL(0x27)); - - /** Vertical Scrolling */ - /** Disable scrolling and enable the grayscale inversion */ - ili93xx_write_register_word(ILI9325_BASE_IMG_DISP_CTRL, - ILI9325_BASE_IMG_DISP_CTRL_REV); - ili93xx_write_register_word(ILI9325_VERTICAL_SCROLL_CTRL, - 0x0000); - - /** Disable Partial Display */ - ili93xx_write_register_word(ILI9325_PARTIAL_IMG1_DISP_POS, - 0x0000); - ili93xx_write_register_word( - ILI9325_PARTIAL_IMG1_AREA_START_LINE, - 0x0000); - ili93xx_write_register_word(ILI9325_PARTIAL_IMG1_AREA_END_LINE, - 0x0000); - ili93xx_write_register_word(ILI9325_PARTIAL_IMG2_DISP_POS, - 0x0000); - ili93xx_write_register_word( - ILI9325_PARTIAL_IMG2_AREA_START_LINE, - 0x0000); - ili93xx_write_register_word(ILI9325_PARTIAL_IMG2_AREA_END_LINE, - 0x0000); - - /** Panel Control */ - ili93xx_write_register_word(ILI9325_PANEL_INTERFACE_CTRL1, - ILI9325_PANEL_INTERFACE_CTRL1_RTNI(0x10)); - ili93xx_write_register_word(ILI9325_PANEL_INTERFACE_CTRL2, - ILI9325_PANEL_INTERFACE_CTRL2_NOWI(0x06)); - ili93xx_write_register_word(ILI9325_PANEL_INTERFACE_CTRL4, - ILI9325_PANEL_INTERFACE_CTRL4_DIVE(0x01) | - ILI9325_PANEL_INTERFACE_CTRL4_RTNE(0x10)); - - ili93xx_set_window(0, 0, p_opt->ul_width, p_opt->ul_height); - ili93xx_set_foreground_color(p_opt->foreground_color); - ili93xx_set_cursor_position(0, 0); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - /** init for ILI9341 **/ - /** power control A configuration*/ - paratable[0] = 0x39; - paratable[1] = 0x2C; - paratable[2] = 0x00; - paratable[3] = 0x34; - paratable[4] = 0x02; - ili93xx_write_register(ILI9341_CMD_POWER_CONTROL_A, paratable, 5); - - /** power control B configuration */ - paratable[0] = 0; - paratable[1] = 0xAA; - paratable[2] = 0xB0; - ili93xx_write_register(ILI9341_CMD_POWER_CONTROL_B, paratable, 3); - - /** Pump Ratio Control configuration */ - paratable[0] = 0x30; - ili93xx_write_register(ILI9341_CMD_PUMP_RATIO_CONTROL, - paratable, 1); - - /** Power Control 1 configuration*/ - paratable[0] = 0x25; - ili93xx_write_register(ILI9341_CMD_POWER_CONTROL_1, paratable, 1); - - /** Power Control 2 configuration*/ - paratable[0] = 0x11; - ili93xx_write_register(ILI9341_CMD_POWER_CONTROL_2, paratable, 1); - - /** VOM Control 1 configuration*/ - paratable[0] = 0x5C; - paratable[1] = 0x4C; - ili93xx_write_register(ILI9341_CMD_VCOM_CONTROL_1, paratable, 2); - - /** VOM control 2 configuration*/ - paratable[0] = 0x94; - ili93xx_write_register(ILI9341_CMD_VCOM_CONTROL_2, paratable, 1); - - /** Driver Timing Control A configuration*/ - paratable[0] = 0x85; - paratable[1] = 0x01; - paratable[2] = 0x78; - ili93xx_write_register(ILI9341_CMD_DRIVER_TIMING_CTL_A, paratable, 3); - - /** Driver Timing Control B configuration*/ - paratable[0] = 0x00; - paratable[1] = 0x00; - ili93xx_write_register(ILI9341_CMD_DRIVER_TIMING_CTL_B, paratable, 2); - - /** Memory Access Control configuration*/ - paratable[0] = ILI9341_CMD_MEMORY_ACCESS_CONTROL_MX | - ILI9341_CMD_MEMORY_ACCESS_CONTROL_BGR; - ili93xx_write_register(ILI9341_CMD_MEMORY_ACCESS_CONTROL, - paratable, 1); - - /** Colmod Pixel Format Set configuation*/ - paratable[0] = 0x06; - ili93xx_write_register(ILI9341_CMD_PIXEL_FORMAT_SET, paratable, 1); - - /** Display Function Control */ - paratable[0] = 0x02; - paratable[1] = 0x82; - paratable[2] = 0x27; - paratable[3] = 0x00; - ili93xx_write_register(ILI9341_CMD_DISPLAY_FUNCTION_CTL, - paratable, 4); - - paratable[0] = 0x00; - ili93xx_write_register(ILI9341_CMD_ENABLE_3_GAMMA_CONTROL, - paratable,1); - - paratable[0] = 0x01; - ili93xx_write_register(ILI9341_CMD_GAMMA_SET, paratable,1); - - /** set gamma curve parameters*/ - paratable[0]=0x0F; - paratable[1]=0x31; - paratable[2]=0x2B; - paratable[3]=0x0C; - paratable[4]=0x0E; - paratable[5]=0x08; - paratable[6]=0x4E; - paratable[7]=0xF1; - paratable[8]=0x37; - paratable[9]=0x07; - paratable[10]=0x10; - paratable[11]=0x03; - paratable[12]=0x0E; - paratable[13]=0x09; - paratable[14]=0x00; - ili93xx_write_register(ILI9341_CMD_POSITIVE_GAMMA_CORRECTION, - paratable, 15); - paratable[0]=0x00; - paratable[1]=0x0E; - paratable[2]=0x14; - paratable[3]=0x03; - paratable[4]=0x11; - paratable[5]=0x07; - paratable[6]=0x31; - paratable[7]=0xC1; - paratable[8]=0x48; - paratable[9]=0x08; - paratable[10]=0x0F; - paratable[11]=0x0C; - paratable[12]=0x31; - paratable[13]=0x36; - paratable[14]=0x0F; - ili93xx_write_register(ILI9341_CMD_NEGATIVE_GAMMA_CORRECTION, - paratable, 15); - - /** set window area*/ - ili93xx_set_window(0, 0, p_opt->ul_width, p_opt->ul_height); - ili93xx_set_foreground_color(p_opt->foreground_color); - /** Leave sleep mode*/ - ili93xx_write_register(ILI9341_CMD_SLEEP_OUT, paratable, 0); - ili93xx_delay(10); - /** Display on*/ - ili93xx_write_register(ILI9341_CMD_DISPLAY_ON, paratable, 0); - } else { - /** exit with return value 1 if device type is not supported.*/ - return 1; - } - - return 0; -} - -/** - * \brief get the device type. - */ -uint8_t ili93xx_device_type(void) -{ - return g_uc_device_type; -} - -/** - * \brief Turn on the LCD. - */ -void ili93xx_display_on(void) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - ili93xx_write_register_word(ILI9325_DISP_CTRL1, - ILI9325_DISP_CTRL1_BASEE | - ILI9325_DISP_CTRL1_GON | - ILI9325_DISP_CTRL1_DTE | - ILI9325_DISP_CTRL1_D(0x03)); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - ili93xx_write_register(ILI9341_CMD_DISPLAY_ON, NULL, 0); - } -} - -/** - * \brief Turn off the LCD. - */ -void ili93xx_display_off(void) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - ili93xx_write_register_word(ILI9325_DISP_CTRL1, 0x00); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - ili93xx_write_register(ILI9341_CMD_DISPLAY_OFF, NULL, 0); - } -} - -/** - * \brief Set foreground color. - * - * \param ul_color foreground color. - */ -void ili93xx_set_foreground_color(ili93xx_color_t ul_color) -{ - uint32_t i; - - /** Fill the cache with selected color */ - for (i = 0; i < LCD_DATA_CACHE_SIZE; ++i) { - g_ul_pixel_cache[i] = ul_color; - } -} - -/** - * \brief Fill the LCD buffer with the specified color. - * - * \param ul_color fill color. - */ -void ili93xx_fill(ili93xx_color_t ul_color) -{ - uint32_t dw; - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - ili93xx_set_cursor_position(0, 0); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - ili93xx_set_window(0, 0, g_ul_lcd_x_length, g_ul_lcd_y_length); - } - - ili93xx_write_ram_prepare(); - - for (dw = ILI93XX_LCD_WIDTH * ILI93XX_LCD_HEIGHT; dw > 0; dw--) { - ili93xx_write_ram(ul_color); - } -} - -/** - * \brief Set display window. - * - * \param ul_x Horizontal address start position - * \param ul_y Vertical address start position - * \param ul_width The width of the window. - * \param ul_height The height of the window. - */ -void ili93xx_set_window(uint32_t ul_x, uint32_t ul_y, uint32_t ul_width, - uint32_t ul_height) -{ - Assert(ul_x <= (g_ul_lcd_x_length - 1)); - Assert(ul_y <= (g_ul_lcd_y_length - 1)); - Assert(ul_width <= (g_ul_lcd_x_length - ul_x)); - Assert(ul_height <= (g_ul_lcd_y_length - ul_y)); - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** Set Horizontal Address Start Position */ - ili93xx_write_register_word(ILI9325_HORIZONTAL_ADDR_START, - (uint16_t)ul_x); - - /** Set Horizontal Address End Position */ - ili93xx_write_register_word(ILI9325_HORIZONTAL_ADDR_END, - (uint16_t)(ul_x + ul_width - 1)); - - /** Set Vertical Address Start Position */ - ili93xx_write_register_word(ILI9325_VERTICAL_ADDR_START, - (uint16_t)ul_y); - - /** Set Vertical Address End Position */ - ili93xx_write_register_word(ILI9325_VERTICAL_ADDR_END, - (uint16_t)(ul_y + ul_height - 1)); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - uint8_t paratable[4]; - - /** Set Column Address Position */ - paratable[0] = (ul_x >> 8) & 0xFF; - paratable[1] = ul_x & 0xFF; - paratable[2] = ((ul_x + ul_width - 1) >> 8) & 0xFF; - paratable[3] = (ul_x + ul_width - 1) & 0xFF; - ili93xx_write_register(ILI9341_CMD_COLUMN_ADDRESS_SET, - paratable, 4); - - /** Set Page Address Position */ - paratable[0] = (ul_y >> 8) & 0xFF; - paratable[1] = ul_y & 0xFF; - paratable[2] = ((ul_y + ul_height - 1) >> 8) & 0xFF; - paratable[3] = (ul_y + ul_height - 1) & 0xFF; - ili93xx_write_register(ILI9341_CMD_PAGE_ADDRESS_SET, - paratable, 4); - } -} - -/** - * \brief Set cursor of LCD screen. - * - * \param us_x X coordinate of upper-left corner on LCD. - * \param us_y Y coordinate of upper-left corner on LCD. - */ -void ili93xx_set_cursor_position(uint16_t us_x, uint16_t us_y) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** GRAM Horizontal/Vertical Address Set (R20h, R21h) */ - ili93xx_write_register_word(ILI9325_HORIZONTAL_GRAM_ADDR_SET, us_x); - ili93xx_write_register_word(ILI9325_VERTICAL_GRAM_ADDR_SET, us_y); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - /** There is no corresponding operation for ILI9341. */ - } -} - -/** - * \brief Scroll up/down for the number of specified lines. - * - * \param ul_lines number of lines to scroll. - */ -void ili93xx_scroll(int32_t ul_lines) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - ili93xx_write_register_word(ILI9325_VERTICAL_SCROLL_CTRL, ul_lines); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - uint8_t paratable[2]; - - paratable[0] = (ul_lines >> 8) & 0xFF; - paratable[1] = ul_lines & 0xFF; - ili93xx_write_register(ILI9341_CMD_VERT_SCROLL_START_ADDRESS, - paratable, 2); - } -} - -/** - * \brief Vertical Scroll area definition for ili9341. - * - * \param us_tfa the top fixed area (the No. of lines) - * \param us_vsa the height of the vetical scrolling area - * \param us_bfa the bottom fixed area (the No. of lines) - */ -void ili93xx_vscroll_area_define(uint16_t us_tfa, uint16_t us_vsa, - uint16_t us_bfa) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - uint8_t paratable[6]; - - paratable[0] = (us_tfa >> 8) & 0xFF; - paratable[1] = us_tfa & 0xFF; - paratable[2] = (us_vsa >> 8) & 0xFF; - paratable[3] = us_vsa & 0xFF; - paratable[4] = (us_bfa >> 8) & 0xFF; - paratable[5] = us_bfa & 0xFF; - ili93xx_write_register(ILI9341_CMD_VERT_SCROLL_DEFINITION, - paratable, 6); - } -} - -/** - * \brief Enable the scrolling feature. - */ -void ili93xx_enable_scroll(void) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - ili93xx_write_register_word(ILI9325_BASE_IMG_DISP_CTRL, - ILI9325_BASE_IMG_DISP_CTRL_REV | - ILI9325_BASE_IMG_DISP_CTRL_VLE); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - /** no operation needed for ILI9341*/ - } -} - -/** - * \brief Disable the scrolling feature. - */ -void ili93xx_disable_scroll(void) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - ili93xx_write_register_word(ILI9325_BASE_IMG_DISP_CTRL, - ILI9325_BASE_IMG_DISP_CTRL_REV); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - ili93xx_display_off(); - ili93xx_write_register(ILI9341_CMD_NORMAL_DISP_MODE_ON, NULL, 0); - ili93xx_display_on(); - } -} - -/** - * \brief Set display direction. - * - * \param e_dd 0: horizontal direction, 1: vertical direction - * \param e_shd: horizontal increase(0) or decrease(1) - * \param e_scd: vertical increase(1) or decrease(0) - */ -void ili93xx_set_display_direction(enum ili93xx_display_direction e_dd, - enum ili93xx_shift_direction e_shd, - enum ili93xx_scan_direction e_scd) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - if (e_dd == LANDSCAPE) { - ili93xx_write_register_word(ILI9325_ENTRY_MODE, - ILI9325_ENTRY_MODE_BGR | ILI9325_ENTRY_MODE_TRI | - ILI9325_ENTRY_MODE_DFM | ILI9325_ENTRY_MODE_ID(0x00)| - ILI9325_ENTRY_MODE_AM); - g_ul_lcd_x_length = ILI93XX_LCD_HEIGHT; - g_ul_lcd_y_length = ILI93XX_LCD_WIDTH; - } else { - ili93xx_write_register_word(ILI9325_ENTRY_MODE, - ILI9325_ENTRY_MODE_BGR | ILI9325_ENTRY_MODE_TRI | - ILI9325_ENTRY_MODE_DFM | ILI9325_ENTRY_MODE_ID(0x01)); - g_ul_lcd_x_length = ILI93XX_LCD_WIDTH; - g_ul_lcd_y_length = ILI93XX_LCD_HEIGHT; - } - - if (e_shd == H_INCREASE) { - ili93xx_write_register_word(ILI9325_DRIVER_OUTPUT_CTRL1, 0x0000); - } else { - ili93xx_write_register_word(ILI9325_DRIVER_OUTPUT_CTRL1, - ILI9325_DRIVER_OUTPUT_CTRL1_SS); - } - - if (e_scd == V_INCREASE) { - ili93xx_write_register_word(ILI9325_DRIVER_OUTPUT_CTRL2, - ILI9325_DRIVER_OUTPUT_CTRL2_NL(0x27)); - } else { - ili93xx_write_register_word(ILI9325_DRIVER_OUTPUT_CTRL2, - ILI9325_DRIVER_OUTPUT_CTRL2_GS | - ILI9325_DRIVER_OUTPUT_CTRL2_NL(0x27)); - } - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - if (e_dd == LANDSCAPE) { - uint8_t paratable[1]; - paratable[0] = ILI9341_CMD_MEMORY_ACCESS_CONTROL_MV | - ILI9341_CMD_MEMORY_ACCESS_CONTROL_BGR; - ili93xx_write_register( - ILI9341_CMD_MEMORY_ACCESS_CONTROL, - paratable, 1); - g_ul_lcd_x_length = ILI93XX_LCD_HEIGHT; - g_ul_lcd_y_length = ILI93XX_LCD_WIDTH; - } else { - uint8_t paratable[1]; - paratable[0] = ILI9341_CMD_MEMORY_ACCESS_CONTROL_BGR | - ILI9341_CMD_MEMORY_ACCESS_CONTROL_MX; - ili93xx_write_register( - ILI9341_CMD_MEMORY_ACCESS_CONTROL, - paratable, 1); - g_ul_lcd_x_length = ILI93XX_LCD_WIDTH; - g_ul_lcd_y_length = ILI93XX_LCD_HEIGHT; - } - } -} - -/** - * \brief Draw a pixel on LCD. - * - * \param ul_x X coordinate of pixel. - * \param ul_y Y coordinate of pixel. - * - * \return 0 if succeeds, otherwise fails. - */ -uint32_t ili93xx_draw_pixel(uint32_t ul_x, uint32_t ul_y) -{ - if ((ul_x >= g_ul_lcd_x_length) || (ul_y >= g_ul_lcd_y_length)) { - return 1; - } - - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** Set cursor */ - ili93xx_set_cursor_position(ul_x, ul_y); - /** Prepare to write in GRAM */ - ili93xx_write_ram_prepare(); - ili93xx_write_ram(*g_ul_pixel_cache); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - ili93xx_set_window(ul_x, ul_y, 0, 0); - /** Prepare to write in GRAM */ - ili93xx_write_ram_prepare(); - ili93xx_write_ram(*g_ul_pixel_cache); - } - - return 0; -} - -/** - * \brief Get a pixel from LCD. - * - * \param ul_x X coordinate of pixel. - * \param ul_y Y coordinate of pixel. - * - * \return the pixel color. - */ -ili93xx_color_t ili93xx_get_pixel(uint32_t ul_x, uint32_t ul_y) -{ - Assert(ul_x <= g_ul_lcd_x_length); - Assert(ul_y <= g_ul_lcd_y_length); - - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** Set cursor */ - ili93xx_set_cursor_position(ul_x, ul_y); - /** Prepare to write in GRAM */ - ili93xx_read_ram_prepare(); - return ili93xx_read_ram(); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - ili93xx_set_window(ul_x, ul_y, 0, 0); - /** Prepare to write in GRAM */ - ili93xx_read_ram_prepare(); - return ili93xx_read_ram(); - } - - return 0; -} - -/** - * \brief Draw a line on LCD, which is not horizontal or vertical. - * - * \param ul_x1 X coordinate of line start. - * \param ul_y1 Y coordinate of line start. - * \param ul_x2 X coordinate of line end. - * \param ul_y2 Y coordinate of line endl. - */ -static void ili93xx_draw_line_bresenham(uint32_t ul_x1, uint32_t ul_y1, - uint32_t ul_x2, uint32_t ul_y2) -{ - int dx, dy; - int i; - int xinc, yinc, cumul; - int x, y; - - x = ul_x1; - y = ul_y1; - dx = ul_x2 - ul_x1; - dy = ul_y2 - ul_y1; - xinc = (dx > 0) ? 1 : -1; - yinc = (dy > 0) ? 1 : -1; - dx = abs(ul_x2 - ul_x1); - dy = abs(ul_y2 - ul_y1); - - ili93xx_draw_pixel(x, y); - - if (dx > dy) { - cumul = dx >> 1; - - for (i = 1; i <= dx; i++) { - x += xinc; - cumul += dy; - - if (cumul >= dx) { - cumul -= dx; - y += yinc; - } - - ili93xx_draw_pixel(x, y); - } - } else { - cumul = dy >> 1; - - for (i = 1; i <= dy; i++) { - y += yinc; - cumul += dx; - - if (cumul >= dy) { - cumul -= dy; - x += xinc; - } - - ili93xx_draw_pixel(x, y); - } - } -} - -/** - * \brief Draw a line on LCD. - * - * \param ul_x1 X coordinate of line start. - * \param ul_y1 Y coordinate of line start. - * \param ul_x2 X coordinate of line end. - * \param ul_y2 Y coordinate of line end. - */ -void ili93xx_draw_line(uint32_t ul_x1, uint32_t ul_y1, - uint32_t ul_x2, uint32_t ul_y2) -{ - if ((ul_y1 == ul_y2) || (ul_x1 == ul_x2)) { - ili93xx_draw_filled_rectangle(ul_x1, ul_y1, ul_x2, ul_y2); - } else { - ili93xx_draw_line_bresenham(ul_x1, ul_y1, ul_x2, ul_y2); - } -} - -/** - * \brief Draw a rectangle on LCD. - * - * \param ul_x1 X coordinate of upper-left corner on LCD. - * \param ul_y1 Y coordinate of upper-left corner on LCD. - * \param ul_x2 X coordinate of lower-right corner on LCD. - * \param ul_y2 Y coordinate of lower-right corner on LCD. - */ -void ili93xx_draw_rectangle(uint32_t ul_x1, uint32_t ul_y1, - uint32_t ul_x2, uint32_t ul_y2) -{ - ili93xx_check_box_coordinates(&ul_x1, &ul_y1, &ul_x2, &ul_y2); - - ili93xx_draw_filled_rectangle(ul_x1, ul_y1, ul_x2, ul_y1); - ili93xx_draw_filled_rectangle(ul_x1, ul_y2, ul_x2, ul_y2); - - ili93xx_draw_filled_rectangle(ul_x1, ul_y1, ul_x1, ul_y2); - ili93xx_draw_filled_rectangle(ul_x2, ul_y1, ul_x2, ul_y2); -} - -/** - * \brief Draw a filled rectangle on LCD. - * - * \param ul_x1 X coordinate of upper-left corner on LCD. - * \param ul_y1 Y coordinate of upper-left corner on LCD. - * \param ul_x2 X coordinate of lower-right corner on LCD. - * \param ul_y2 Y coordinate of lower-right corner on LCD. - */ -void ili93xx_draw_filled_rectangle(uint32_t ul_x1, uint32_t ul_y1, - uint32_t ul_x2, uint32_t ul_y2) -{ - uint32_t size, blocks; - - /** Swap coordinates if necessary */ - ili93xx_check_box_coordinates(&ul_x1, &ul_y1, &ul_x2, &ul_y2); - - /** Determine the refresh window area */ - ili93xx_set_window(ul_x1, ul_y1, (ul_x2 - ul_x1) + 1, - (ul_y2 - ul_y1) + 1); - - /** Set cursor */ - ili93xx_set_cursor_position(ul_x1, ul_y1); - - /** Prepare to write in Graphic RAM */ - ili93xx_write_ram_prepare(); - - size = (ul_x2 - ul_x1 + 1) * (ul_y2 - ul_y1 + 1); - - /** Send pixels blocks => one SPI IT / block */ - blocks = size / LCD_DATA_CACHE_SIZE; - while (blocks--) { - ili93xx_write_ram_buffer(g_ul_pixel_cache, - LCD_DATA_CACHE_SIZE); - } - - /** Send remaining pixels */ - ili93xx_write_ram_buffer(g_ul_pixel_cache, - size % LCD_DATA_CACHE_SIZE); - - /** Reset the refresh window area */ - ili93xx_set_window(0, 0, g_ul_lcd_x_length, g_ul_lcd_y_length); -} - -/** - * \brief Draw a circle on LCD. - * - * \param ul_x X coordinate of circle center. - * \param ul_y Y coordinate of circle center. - * \param ul_r circle radius. - * - * \return 0 if succeeds, otherwise fails. - */ -uint32_t ili93xx_draw_circle(uint32_t ul_x, uint32_t ul_y, uint32_t ul_r) -{ - int32_t d; - uint32_t curX; - uint32_t curY; - - if (ul_r == 0) { - return 1; - } - - d = 3 - (ul_r << 1); - curX = 0; - curY = ul_r; - - while (curX <= curY) { - ili93xx_draw_pixel(ul_x + curX, ul_y + curY); - ili93xx_draw_pixel(ul_x + curX, ul_y - curY); - ili93xx_draw_pixel(ul_x - curX, ul_y + curY); - ili93xx_draw_pixel(ul_x - curX, ul_y - curY); - ili93xx_draw_pixel(ul_x + curY, ul_y + curX); - ili93xx_draw_pixel(ul_x + curY, ul_y - curX); - ili93xx_draw_pixel(ul_x - curY, ul_y + curX); - ili93xx_draw_pixel(ul_x - curY, ul_y - curX); - - if (d < 0) { - d += (curX << 2) + 6; - } else { - d += ((curX - curY) << 2) + 10; - curY--; - } - - curX++; - } - - return 0; -} - -/** - * \brief Draw a filled circle on LCD. - * - * \param ul_x X coordinate of circle center. - * \param ul_y Y coordinate of circle center. - * \param ul_r circle radius. - * - * \return 0 if succeeds, otherwise fails. - */ -uint32_t ili93xx_draw_filled_circle(uint32_t ul_x, uint32_t ul_y, uint32_t ul_r) -{ - signed int d; /* Decision Variable */ - uint32_t dwCurX; /* Current X Value */ - uint32_t dwCurY; /* Current Y Value */ - uint32_t dwXmin, dwYmin; - - if (ul_r == 0) { - return 1; - } - - d = 3 - (ul_r << 1); - dwCurX = 0; - dwCurY = ul_r; - - while (dwCurX <= dwCurY) { - dwXmin = (dwCurX > ul_x) ? 0 : ul_x - dwCurX; - dwYmin = (dwCurY > ul_y) ? 0 : ul_y - dwCurY; - ili93xx_draw_filled_rectangle(dwXmin, dwYmin, ul_x + dwCurX, - dwYmin); - ili93xx_draw_filled_rectangle(dwXmin, ul_y + dwCurY, - ul_x + dwCurX, ul_y + dwCurY); - dwXmin = (dwCurY > ul_x) ? 0 : ul_x - dwCurY; - dwYmin = (dwCurX > ul_y) ? 0 : ul_y - dwCurX; - ili93xx_draw_filled_rectangle(dwXmin, dwYmin, ul_x + dwCurY, - dwYmin); - ili93xx_draw_filled_rectangle(dwXmin, ul_y + dwCurX, - ul_x + dwCurY, ul_y + dwCurX); - - if (d < 0) { - d += (dwCurX << 2) + 6; - } else { - d += ((dwCurX - dwCurY) << 2) + 10; - dwCurY--; - } - - dwCurX++; - } - - return 0; -} - -/** - * \brief Draw an ASCII character on LCD. - * - * \param ul_x X coordinate of character upper-left corner. - * \param ul_y Y coordinate of character upper-left corner. - * \param uc_c character to print. - */ -static void ili93xx_draw_char(uint32_t ul_x, uint32_t ul_y, uint8_t uc_c) -{ - uint32_t row, col; - uint32_t offset, offset0, offset1; - - /** - * Compute offset according of the specified ASCII character - * Note: the first 32 characters of the ASCII table are not handled - */ - offset = ((uint32_t)uc_c - 0x20) * 20; - - for (col = 0; col < 10; col++) { - /** Compute the first and second byte offset of a column */ - offset0 = offset + col * 2; - offset1 = offset0 + 1; - - /** - * Draw pixel on screen depending on the corresponding bit value - * from the charset - */ - for (row = 0; row < 8; row++) { - if ((p_uc_charset10x14[offset0] >> (7 - row)) & 0x1) { - ili93xx_draw_pixel(ul_x + col, ul_y + row); - } - } - - for (row = 0; row < 6; row++) { - if ((p_uc_charset10x14[offset1] >> (7 - row)) & 0x1) { - ili93xx_draw_pixel(ul_x + col, ul_y + row + 8); - } - } - } -} - -/** - * \brief Draw a string on LCD. - * - * \param ul_x X coordinate of string top-left corner. - * \param ul_y Y coordinate of string top-left corner. - * \param p_str String to display. - */ -void ili93xx_draw_string(uint32_t ul_x, uint32_t ul_y, const uint8_t *p_str) -{ - uint32_t xorg = ul_x; - - while (*p_str != 0) { - /** If newline, jump to the next line (font height + 2) */ - if (*p_str == '\n') { - ul_y += gfont.height + 2; - ul_x = xorg; - } else { - /** - * Draw the character and place cursor right after (font - * width + 2) - */ - ili93xx_draw_char(ul_x, ul_y, *p_str); - ul_x += gfont.width + 2; - } - - p_str++; - } -} - -/** - * \brief Draw a pixmap on LCD. - * - * \param ul_x X coordinate of upper-left corner on LCD. - * \param ul_y Y coordinate of upper-left corner on LCD. - * \param ul_width width of the picture. - * \param ul_height height of the picture. - * \param p_ul_pixmap pixmap of the image. - */ -void ili93xx_draw_pixmap(uint32_t ul_x, uint32_t ul_y, uint32_t ul_width, - uint32_t ul_height, const ili93xx_color_t *p_ul_pixmap) -{ - uint32_t size; - uint32_t dwX1, dwY1, dwX2, dwY2; - dwX1 = ul_x; - dwY1 = ul_y; - dwX2 = ul_x + ul_width; - dwY2 = ul_y + ul_height; - - /** Swap coordinates if necessary */ - ili93xx_check_box_coordinates(&dwX1, &dwY1, &dwX2, &dwY2); - - /** Determine the refresh window area */ - ili93xx_set_window(dwX1, dwY1, (dwX2 - dwX1 + 1), (dwY2 - dwY1 + 1)); - - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** Set cursor */ - ili93xx_set_cursor_position(dwX1, dwY1); - /** Prepare to write in GRAM */ - ili93xx_write_ram_prepare(); - - size = (dwX2 - dwX1) * (dwY2 - dwY1); - - ili93xx_write_ram_buffer(p_ul_pixmap, size); - - /** Reset the refresh window area */ - ili93xx_set_window(0, 0, g_ul_lcd_x_length, g_ul_lcd_y_length); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - /** Prepare to write in GRAM */ - ili93xx_write_ram_prepare(); - - size = (dwX2 - dwX1) * (dwY2 - dwY1); - - ili93xx_write_ram_buffer(p_ul_pixmap, size); - - /** Reset the refresh window area */ - ili93xx_set_window(0, 0, g_ul_lcd_x_length, g_ul_lcd_y_length); - } -} - -/** - * \internal - * \brief Helper function to send the drawing limits (boundaries) to the display - * - * This function is used to send the currently set upper-left and lower-right - * drawing limits to the display, as set through the various limit functions. - * - * \param send_end_limits True to also send the lower-right drawing limits - */ -static inline void ili93xx_send_draw_limits(const bool send_end_limits) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** Set Horizontal Address Start Position */ - ili93xx_write_register_word(ILI9325_HORIZONTAL_ADDR_START, - (uint16_t)limit_start_x); - - if (send_end_limits) { - /** Set Horizontal Address End Position */ - ili93xx_write_register_word(ILI9325_HORIZONTAL_ADDR_END, - (uint16_t)(limit_end_x)); - } - - /** Set Vertical Address Start Position */ - ili93xx_write_register_word(ILI9325_VERTICAL_ADDR_START, - (uint16_t)limit_start_y); - if (send_end_limits) { - /** Set Vertical Address End Position */ - ili93xx_write_register_word(ILI9325_VERTICAL_ADDR_END, - (uint16_t)(limit_end_y)); - } - - /** GRAM Horizontal/Vertical Address Set (R20h, R21h) */ - ili93xx_write_register_word(ILI9325_HORIZONTAL_GRAM_ADDR_SET, - limit_start_x); - ili93xx_write_register_word(ILI9325_VERTICAL_GRAM_ADDR_SET, - limit_start_y); - - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - /** Set Horizontal Address Start Position */ - ili93xx_write_register_word(ILI9341_CMD_COLUMN_ADDRESS_SET, - (uint16_t)limit_start_x); - - if (send_end_limits) { - /** Set Horizontal Address End Position */ - ili93xx_write_register_word( - ILI9341_CMD_COLUMN_ADDRESS_SET, - (uint16_t)(limit_end_x)); - } - - ili93xx_write_register(0, NULL, 0); - - /** Set Vertical Address Start Position */ - ili93xx_write_register_word(ILI9341_CMD_PAGE_ADDRESS_SET, - (uint16_t)limit_start_y); - if (send_end_limits) { - /** Set Vertical Address End Position */ - ili93xx_write_register_word( - ILI9341_CMD_PAGE_ADDRESS_SET, - (uint16_t)(limit_end_y)); - } - - ili93xx_write_register(0, NULL, 0); - } -} - -/** - * \brief Set the display top left drawing limit - * - * Use this function to set the top left limit of the drawing limit box. - * - * \param x The x coordinate of the top left corner - * \param y The y coordinate of the top left corner - */ -void ili93xx_set_top_left_limit(ili93xx_coord_t x, ili93xx_coord_t y) -{ - limit_start_x = x; - limit_start_y = y; - - ili93xx_send_draw_limits(false); -} - -/** - * \brief Set the display bottom right drawing limit - * - * Use this function to set the bottom right corner of the drawing limit box. - * - * \param x The x coordinate of the bottom right corner - * \param y The y coordinate of the bottom right corner - */ -void ili93xx_set_bottom_right_limit(ili93xx_coord_t x, ili93xx_coord_t y) -{ - limit_end_x = x; - limit_end_y = y; - - ili93xx_send_draw_limits(true); -} - -/** - * \brief Set the full display drawing limits - * - * Use this function to set the full drawing limit box. - * - * \param start_x The x coordinate of the top left corner - * \param start_y The y coordinate of the top left corner - * \param end_x The x coordinate of the bottom right corner - * \param end_y The y coordinate of the bottom right corner - */ -void ili93xx_set_limits(ili93xx_coord_t start_x, ili93xx_coord_t start_y, - ili93xx_coord_t end_x, ili93xx_coord_t end_y) -{ - limit_start_x = start_x; - limit_start_y = start_y; - limit_end_x = end_x; - limit_end_y = end_y; - - ili93xx_send_draw_limits(true); -} - -/** - * \brief Read a single color from the graphical memory - * - * Use this function to read a color from the graphical memory of the - * controller. - * - * \retval ili93xx_color_t The read color pixel - */ -ili93xx_color_t ili93xx_read_gram(void) -{ - uint8_t value[3]; - ili93xx_color_t color; - - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - LCD_IR(0); - /** Write Data to GRAM (R22h) */ - LCD_IR(ILI9325_GRAM_DATA_REG); - /** two dummy read */ - value[0] = LCD_RD(); - value[1] = LCD_RD(); - /** data upper byte */ - value[0] = LCD_RD(); - /** data lower byte */ - value[1] = LCD_RD(); - - /** Convert RGB565 to RGB888 */ - /** For BGR format */ - color = ((value[0] & 0xF8)) | - ((value[0] & 0x07) << 13) | ((value[1] & 0xE0) << 5) | - ((value[1] & 0x1F) << 19); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - LCD_IR(0); - /** Write Data to GRAM (R2Eh) */ - LCD_IR(ILI9341_CMD_MEMORY_READ); - /** dummy read */ - value[0] = LCD_RD(); - /** the highest byte - R byte*/ - value[0] = LCD_RD(); - /** the middle byte - G byte*/ - value[1] = LCD_RD(); - /** the lowest byte - B byte*/ - value[2] = LCD_RD(); - /** combine R, G, B byte to a color value */ - color = (value[0] << 16) | (value[1] << 8) | value[2]; - } - return color; -} - -/** - * \brief Write the graphical memory with a single color pixel - * - * Use this function to write a single color pixel to the controller memory. - * - * \param color The color pixel to write to the screen - */ -void ili93xx_write_gram(ili93xx_color_t color) -{ - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - LCD_IR(0); - /** Write Data to GRAM (R22h) */ - LCD_IR(ILI9325_GRAM_DATA_REG); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - /** memory write command (R2Ch)*/ - LCD_IR(ILI9341_CMD_MEMORY_WRITE); - LCD_IR(0); - LCD_IR(ILI9341_CMD_WRITE_MEMORY_CONTINUE); - } - LCD_WD((color >> 16) & 0xFF); - LCD_WD((color >> 8) & 0xFF); - LCD_WD(color & 0xFF); -} - -/** - * \brief Copy pixels from SRAM to the screen - * - * Used to copy a large quantitative of data to the screen in one go. - * - * \param pixels Pointer to the pixel data - * \param count Number of pixels to copy to the screen - */ -void ili93xx_copy_pixels_to_screen(const ili93xx_color_t *pixels, - uint32_t count) -{ - /** Sanity check to make sure that the pixel count is not zero */ - Assert(count > 0); - - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - LCD_IR(0); - LCD_IR(ILI9325_GRAM_DATA_REG); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - LCD_IR(ILI9341_CMD_MEMORY_WRITE); - LCD_IR(0); - LCD_IR(ILI9341_CMD_WRITE_MEMORY_CONTINUE); - } - - while (count--) { - LCD_WD((*pixels >> 16) & 0xFF); - LCD_WD((*pixels >> 8) & 0xFF); - LCD_WD(*pixels & 0xFF); - pixels++; - } -} - -/** - * \brief Copy pixels from SRAM to the screen - * - * Used to copy a large quantitative of data to the screen in one go. - * - * \param pixels Pointer to the pixel data - * \param count Number of pixels to copy to the screen - */ -void ili93xx_copy_raw_pixel_24bits_to_screen(const uint8_t *raw_pixels, - uint32_t count) -{ - ili93xx_color_t pixels; - - /** Sanity check to make sure that the pixel count is not zero */ - Assert(count > 0); - - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - LCD_IR(0); - LCD_IR(ILI9325_GRAM_DATA_REG); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - LCD_IR(ILI9341_CMD_MEMORY_WRITE); - LCD_IR(0); - LCD_IR(ILI9341_CMD_WRITE_MEMORY_CONTINUE); - } - while (count--) { - pixels = (*raw_pixels) | - (*(raw_pixels +1)) << 8 | - (*(raw_pixels + 2)) << 16; - LCD_WD((pixels >> 16) & 0xFF); - LCD_WD((pixels >> 8) & 0xFF); - LCD_WD(pixels & 0xFF); - raw_pixels += 3; - } -} - -/** - * \brief Set a given number of pixels to the same color - * - * Use this function to write a certain number of pixels to the same color - * within a set limit. - * - * \param color The color to write to the display - * \param count The number of pixels to write with this color - */ -void ili93xx_duplicate_pixel(const ili93xx_color_t color, uint32_t count) -{ - /** Sanity check to make sure that the pixel count is not zero */ - Assert(count > 0); - - if (g_uc_device_type == DEVICE_TYPE_ILI9325) { - /** Write Data to GRAM (R22h) */ - LCD_IR(0); - LCD_IR(ILI9325_GRAM_DATA_REG); - } else if (g_uc_device_type == DEVICE_TYPE_ILI9341) { - LCD_IR(ILI9341_CMD_MEMORY_WRITE); - LCD_IR(0); - LCD_IR(ILI9341_CMD_WRITE_MEMORY_CONTINUE); - } - - while (count--) { - LCD_WD((color >> 16) & 0xFF); - LCD_WD((color >> 8) & 0xFF); - LCD_WD(color & 0xFF); - } -} - -/** - * \brief Copy pixels from the screen to a pixel buffer - * - * Use this function to copy pixels from the display to an internal SRAM buffer. - * - * \param pixels Pointer to the pixel buffer to read to - * \param count Number of pixels to read - */ -void ili93xx_copy_pixels_from_screen(ili93xx_color_t *pixels, uint32_t count) -{ - /** Remove warnings */ - UNUSED(pixels); - UNUSED(count); -} - -/** - * \} - */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili93xx.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili93xx.h deleted file mode 100644 index 61ba2140d..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/display/ili93xx/ili93xx.h +++ /dev/null @@ -1,349 +0,0 @@ -/** - * \file - * - * \brief API driver for ili93xx TFT display component. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ILI93XX_H_INCLUDED -#define ILI93XX_H_INCLUDED - -/** - * \defgroup ili93xx_display_group - LCD with ili93xx component driver - * - * This is a driver for LCD with ili93xx. Now this driver supports ili9325 and - * ili9341.This component is custom LCD used for SAM4E-EK. - * The driver provides functions for initializtion and control of the LCD. - * - * See \ref sam_component_ili93xx_quickstart. - * - * \{ - */ - -#include "compiler.h" -#include "board.h" -#include "conf_ili93xx.h" - -/** @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/** @endcond */ - -/** Type define for an integer type large enough to store a pixel color. */ -typedef uint32_t ili93xx_color_t; - -/** Type define for an integer type large enough to store a pixel coordinate. - */ -typedef int16_t ili93xx_coord_t; - -/** This macro generates a 16-bit native color for the display from a - * 24-bit RGB value. - */ -#define ili93xx_COLOR(r, g, b) ((r << 16) | (g << 8) | b) - -typedef ili93xx_color_t gfx_color_t; -typedef int16_t gfx_coord_t; - -/** ili93xx screen size */ -#define ILI93XX_LCD_WIDTH 240 -#define ILI93XX_LCD_HEIGHT 320 - -/** ili93xx ID code */ -#define ILI9325_DEVICE_CODE (0x9325u) -#define ILI9341_DEVICE_CODE (0x9341u) -#define DEVICE_TYPE_ILI9325 1 -#define DEVICE_TYPE_ILI9341 2 -/** Define EBI access for ILI93xx 8-bit System Interface.*/ -#if defined(BOARD_ILI93XX_ADDR) && defined (BOARD_ILI93XX_RS) -static inline void LCD_IR(uint8_t lcd_index) -{ - /** ILI9325 index register address */ - *((volatile uint8_t *)(BOARD_ILI93XX_ADDR)) = lcd_index; -} - -static inline void LCD_WD(uint8_t lcd_data) -{ - *((volatile uint8_t *)((BOARD_ILI93XX_ADDR) | (BOARD_ILI93XX_RS))) = - lcd_data; -} - -static inline uint8_t LCD_RD(void) -{ - return *((volatile uint8_t *)((BOARD_ILI93XX_ADDR) |(BOARD_ILI93XX_RS))); -} - -#else - #error "Missing module configuration for ILI93xx!" -#endif - -/** RGB 24-bits color table definition (RGB888). */ -#define COLOR_BLACK (0x000000u) -#define COLOR_WHITE (0xFFFFFFu) -#define COLOR_BLUE (0x0000FFu) -#define COLOR_GREEN (0x00FF00u) -#define COLOR_RED (0xFF0000u) -#define COLOR_NAVY (0x000080u) -#define COLOR_DARKBLUE (0x00008Bu) -#define COLOR_DARKGREEN (0x006400u) -#define COLOR_DARKCYAN (0x008B8Bu) -#define COLOR_CYAN (0x00FFFFu) -#define COLOR_TURQUOISE (0x40E0D0u) -#define COLOR_INDIGO (0x4B0082u) -#define COLOR_DARKRED (0x800000u) -#define COLOR_OLIVE (0x808000u) -#define COLOR_GRAY (0x808080u) -#define COLOR_SKYBLUE (0x87CEEBu) -#define COLOR_BLUEVIOLET (0x8A2BE2u) -#define COLOR_LIGHTGREEN (0x90EE90u) -#define COLOR_DARKVIOLET (0x9400D3u) -#define COLOR_YELLOWGREEN (0x9ACD32u) -#define COLOR_BROWN (0xA52A2Au) -#define COLOR_DARKGRAY (0xA9A9A9u) -#define COLOR_SIENNA (0xA0522Du) -#define COLOR_LIGHTBLUE (0xADD8E6u) -#define COLOR_GREENYELLOW (0xADFF2Fu) -#define COLOR_SILVER (0xC0C0C0u) -#define COLOR_LIGHTGREY (0xD3D3D3u) -#define COLOR_LIGHTCYAN (0xE0FFFFu) -#define COLOR_VIOLET (0xEE82EEu) -#define COLOR_AZUR (0xF0FFFFu) -#define COLOR_BEIGE (0xF5F5DCu) -#define COLOR_MAGENTA (0xFF00FFu) -#define COLOR_TOMATO (0xFF6347u) -#define COLOR_GOLD (0xFFD700u) -#define COLOR_ORANGE (0xFFA500u) -#define COLOR_SNOW (0xFFFAFAu) -#define COLOR_YELLOW (0xFFFF00u) - -/** - * Input parameters when initializing ili9325 driver. - */ -struct ili93xx_opt_t { - /** LCD width in pixel*/ - uint32_t ul_width; - /** LCD height in pixel*/ - uint32_t ul_height; - /** LCD foreground color*/ - uint32_t foreground_color; - /** LCD background color*/ - uint32_t background_color; -}; - -/** - * Font structure - */ -struct ili93xx_font { - /** Font width in pixels. */ - uint8_t width; - /** Font height in pixels. */ - uint8_t height; -}; - -/** - * Display direction option - */ -enum ili93xx_display_direction { - LANDSCAPE = 0, - PORTRAIT = 1 -}; - -/** - * Shift direction option - */ -enum ili93xx_shift_direction { - H_INCREASE = 0, - H_DECREASE = 1 -}; - -/** - * Scan direction option - */ -enum ili93xx_scan_direction { - V_INCREASE = 0, - V_DEREASE = 1 -}; - -uint32_t ili93xx_init(struct ili93xx_opt_t *p_opt); -void ili93xx_display_on(void); -void ili93xx_display_off(void); -void ili93xx_set_foreground_color(ili93xx_color_t ul_color); -void ili93xx_fill(ili93xx_color_t ul_color); -void ili93xx_set_window(uint32_t ul_x, uint32_t ul_y, - uint32_t ul_width, uint32_t ul_height); -void ili93xx_set_cursor_position(uint16_t us_x, uint16_t us_y); -void ili93xx_scroll(int32_t ul_lines); -void ili93xx_enable_scroll(void); -void ili93xx_disable_scroll(void); -void ili93xx_set_display_direction(enum ili93xx_display_direction e_dd, - enum ili93xx_shift_direction e_shd, - enum ili93xx_scan_direction e_scd); -uint32_t ili93xx_draw_pixel(uint32_t ul_x, uint32_t ul_y); -ili93xx_color_t ili93xx_get_pixel(uint32_t ul_x, uint32_t ul_y); -void ili93xx_draw_line(uint32_t ul_x1, uint32_t ul_y1, - uint32_t ul_x2, uint32_t ul_y2); -void ili93xx_draw_rectangle(uint32_t ul_x1, uint32_t ul_y1, - uint32_t ul_x2, uint32_t ul_y2); -void ili93xx_draw_filled_rectangle(uint32_t ul_x1, uint32_t ul_y1, - uint32_t ul_x2, uint32_t ul_y2); -uint32_t ili93xx_draw_circle(uint32_t ul_x, uint32_t ul_y, uint32_t ul_r); -uint32_t ili93xx_draw_filled_circle(uint32_t ul_x, uint32_t ul_y, - uint32_t ul_r); -void ili93xx_draw_string(uint32_t ul_x, uint32_t ul_y, const uint8_t *p_str); -void ili93xx_draw_pixmap(uint32_t ul_x, uint32_t ul_y, uint32_t ul_width, - uint32_t ul_height, const ili93xx_color_t *p_ul_pixmap); -void ili93xx_set_top_left_limit(ili93xx_coord_t x, ili93xx_coord_t y); -void ili93xx_set_bottom_right_limit(ili93xx_coord_t x, ili93xx_coord_t y); -void ili93xx_set_limits(ili93xx_coord_t start_x, ili93xx_coord_t start_y, - ili93xx_coord_t end_x, ili93xx_coord_t end_y); -ili93xx_color_t ili93xx_read_gram(void); -void ili93xx_write_gram(ili93xx_color_t color); -void ili93xx_copy_pixels_to_screen(const ili93xx_color_t *pixels, - uint32_t count); -void ili93xx_copy_raw_pixel_24bits_to_screen(const uint8_t *raw_pixels, - uint32_t count); -void ili93xx_duplicate_pixel(const ili93xx_color_t color, uint32_t count); -void ili93xx_copy_pixels_from_screen(ili93xx_color_t *pixels, uint32_t count); -uint8_t ili93xx_device_type(void); -void ili93xx_vscroll_area_define(uint16_t us_tfa, uint16_t us_vsa, - uint16_t us_bfa); -uint8_t ili93xx_device_type_identify(void); - -/** @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/** @endcond */ - -/** - * \} - */ - -/** - * \page sam_component_ili93xx_quickstart Quick Start Guide for the ILI93XX - * LCD Glass component. - * - * This is the quick start guide for the \ref ili93xx_display_group, with - * step-by-step instructions on how to configure and use the driver for - * a specific use case.The code examples can be copied into e.g the main - * application loop or any other function that will need to control the - * ili93xx LCD Glass component module. Now ili9325 and ili9341 are supported. - * - * \section ili93xx_qs_use_cases Use cases - * - \ref ili93xx_basic - * - * \section ili93xx_basic ili93xx LCD Glass basic usage - * - * This use case will demonstrate how to initialize the ili93xx LCD Glass - * module. - * - * - * \section ili93xx_basic_setup Setup steps - * - * \subsection ili93xx_basic_prereq Prerequisites - * - * This module requires the following driver - * - \ref smc_group - * - * \subsection ili93xx_basic_setup_code - * - * Add this to the main loop or a setup function: - * \code - * struct ili93xx_opt_t g_ili93xx_display_opt; - * g_ili93xx_display_opt.ul_width = ILI93XX_LCD_WIDTH; - * g_ili93xx_display_opt.ul_height = ILI93XX_LCD_HEIGHT; - * g_ili93xx_display_opt.foreground_color = COLOR_BLACK; - * g_ili93xx_display_opt.background_color = COLOR_WHITE; - * ili93xx_init(&g_ili93xx_display_opt); - * \endcode - * - * \subsection ili93xx_basic_setup_workflow - * -\ref ili93xx_basic_setup_code - * - * \section ili93xx_basic_usage Usage steps - * - * \subsection ili93xx_basic_usage_code - * - * -# Set display on - * \code - * ili93xx_display_on(); - * \endcode - * - * -# Turn display off - * \code - * ili93xx_display_off(); - * \endcode - * - * -# Draw a pixel - * \code - * ili93xx_set_foreground_color(COLOR_RED); - * ili93xx_draw_pixel(60, 60); - * \endcode - * - * -# Draw a line and circle - * \code - * ili93xx_set_foreground_color(COLOR_BLUE); - * ili93xx_draw_circle(180, 160, 40); - * ili93xx_set_foreground_color(COLOR_VIOLET); - * ili93xx_draw_line(0, 0, 240, 320); - * \endcode - * - * -# Draw a string of text - * \code - * ili93xx_set_foreground_color(COLOR_BLACK); - * ili93xx_draw_string(10, 20, (uint8_t *)"ili93xx_lcd example"); - * \endcode - * - * -# Fill a rectangle with one certain color - * \code - * ili93xx_set_foreground_color(COLOR_BLUE); - * ili93xx_draw_filled_rectangle(0, 0, ILI93XX_LCD_WIDTH, ILI93XX_LCD_HEIGHT); - * \endcode - * - * -# Get device type - * \code - * ili93xx_device_type(); - * \endcode - */ - -#endif /* ILI93XX_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/documentation.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/documentation.h deleted file mode 100644 index 63837b095..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/documentation.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * \file - * - * \brief Ethernet Phy management - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * - * \defgroup ethernet_phy_group Ethernet Phy - * - * This is the common API for Ethernet Phy on ARMs. Additional features are available - * in the documentation of the specific modules. - * - * \section ethernet_phy_group_platform Platform Dependencies - * - * The ethernet_phy API is partially chip- or platform-specific. While all - * platforms provide mostly the same functionality, there are some - * variations around how different bus types and clock tree structures - * are handled. - * - * The following functions are available on all platforms, but there may - * be variations in the function signature (i.e. parameters) and - * behaviour. These functions are typically called by platform-specific - * parts of drivers, and applications that aren't intended to be - * portable: - * - ethernet_phy_init() - * - ethernet_phy_set_link() - * - ethernet_phy_auto_negotiate() - * - ethernet_phy_reset() - * - * @{ - */ - -//! @} - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/ksz8051mnl/ethernet_phy.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/ksz8051mnl/ethernet_phy.c deleted file mode 100644 index 790f9dfb9..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/ksz8051mnl/ethernet_phy.c +++ /dev/null @@ -1,428 +0,0 @@ - /** - * \file - * - * \brief API driver for KSZ8051MNL PHY component. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "ethernet_phy.h" -#include "gmac.h" -#include "conf_eth.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \defgroup ksz8051mnl_ethernet_phy_group PHY component (KSZ8051MNL) - * - * Driver for the ksz8051mnl component. This driver provides access to the main - * features of the PHY. - * - * \section dependencies Dependencies - * This driver depends on the following modules: - * - \ref gmac_group Ethernet Media Access Controller (GMAC) module. - * - * @{ - */ - -/* Max PHY number */ -#define ETH_PHY_MAX_ADDR 31 - -/* Ethernet PHY operation max retry count */ -#define ETH_PHY_RETRY_MAX 1000000 - -/* Ethernet PHY operation timeout */ -#define ETH_PHY_TIMEOUT 10 - -/** - * \brief Find a valid PHY Address ( from addrStart to 31 ). - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * \param uc_start_addr Start address of the PHY to be searched. - * - * \return 0xFF when no valid PHY address is found. - */ -static uint8_t ethernet_phy_find_valid(Gmac *p_gmac, uint8_t uc_phy_addr, - uint8_t uc_start_addr) -{ - uint32_t ul_value = 0; - uint8_t uc_rc = 0; - uint8_t uc_cnt; - uint8_t uc_phy_address = uc_phy_addr; - - gmac_enable_management(p_gmac, true); - - /* Check the current PHY address */ - gmac_phy_read(p_gmac, uc_phy_addr, GMII_PHYID1, &ul_value); - - /* Find another one */ - if (ul_value != GMII_OUI_LSB) { - uc_rc = 0xFF; - for (uc_cnt = uc_start_addr; uc_cnt <= ETH_PHY_MAX_ADDR; uc_cnt++) { - uc_phy_address = (uc_phy_address + 1) & 0x1F; - gmac_phy_read(p_gmac, uc_phy_address, GMII_PHYID1, &ul_value); - if (ul_value == GMII_OUI_MSB) { - uc_rc = uc_phy_address; - break; - } - } - } - - gmac_enable_management(p_gmac, false); - - if (uc_rc != 0xFF) { - gmac_phy_read(p_gmac, uc_phy_address, GMII_BMSR, &ul_value); - } - return uc_rc; -} - - -/** - * \brief Perform a HW initialization to the PHY and set up clocks. - * - * This should be called only once to initialize the PHY pre-settings. - * The PHY address is the reset status of CRS, RXD[3:0] (the emacPins' pullups). - * The COL pin is used to select MII mode on reset (pulled up for Reduced MII). - * The RXDV pin is used to select test mode on reset (pulled up for test mode). - * The above pins should be predefined for corresponding settings in resetPins. - * The GMAC peripheral pins are configured after the reset is done. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * \param ul_mck GMAC MCK. - * - * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t ethernet_phy_init(Gmac *p_gmac, uint8_t uc_phy_addr, uint32_t mck) -{ - uint8_t uc_rc = GMAC_TIMEOUT; - uint8_t uc_phy; - - ethernet_phy_reset(GMAC,uc_phy_addr); - - /* Configure GMAC runtime clock */ - uc_rc = gmac_set_mdc_clock(p_gmac, mck); - if (uc_rc != GMAC_OK) { - return 0; - } - - /* Check PHY Address */ - uc_phy = ethernet_phy_find_valid(p_gmac, uc_phy_addr, 0); - if (uc_phy == 0xFF) { - return 0; - } - if (uc_phy != uc_phy_addr) { - ethernet_phy_reset(p_gmac, uc_phy_addr); - } - - return uc_rc; -} - - -/** - * \brief Get the Link & speed settings, and automatically set up the GMAC with the - * settings. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply. - * - * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t ethernet_phy_set_link(Gmac *p_gmac, uint8_t uc_phy_addr, - uint8_t uc_apply_setting_flag) -{ - uint32_t ul_stat1; - uint32_t ul_stat2; - uint8_t uc_phy_address, uc_speed, uc_fd; - uint8_t uc_rc = GMAC_TIMEOUT; - - gmac_enable_management(p_gmac, true); - - uc_phy_address = uc_phy_addr; - - uc_rc = gmac_phy_read(p_gmac, uc_phy_address, GMII_BMSR, &ul_stat1); - if (uc_rc != GMAC_OK) { - /* Disable PHY management and start the GMAC transfer */ - gmac_enable_management(p_gmac, false); - - return uc_rc; - } - - if ((ul_stat1 & GMII_LINK_STATUS) == 0) { - /* Disable PHY management and start the GMAC transfer */ - gmac_enable_management(p_gmac, false); - - return GMAC_INVALID; - } - - if (uc_apply_setting_flag == 0) { - /* Disable PHY management and start the GMAC transfer */ - gmac_enable_management(p_gmac, false); - - return uc_rc; - } - - /* Read advertisement */ - uc_rc = gmac_phy_read(p_gmac, uc_phy_address, GMII_ANAR, &ul_stat2); - if (uc_rc != GMAC_OK) { - /* Disable PHY management and start the GMAC transfer */ - gmac_enable_management(p_gmac, false); - - return uc_rc; - } - - if ((ul_stat1 & GMII_100BASE_TX_FD) && (ul_stat2 & GMII_100TX_FDX)) { - /* Set GMAC for 100BaseTX and Full Duplex */ - uc_speed = true; - uc_fd = true; - } - - if ((ul_stat1 & GMII_10BASE_T_FD) && (ul_stat2 & GMII_10_FDX)) { - /* Set MII for 10BaseT and Full Duplex */ - uc_speed = false; - uc_fd = true; - } - - if ((ul_stat1 & GMII_100BASE_T4_HD) && (ul_stat2 & GMII_100TX_HDX)) { - /* Set MII for 100BaseTX and Half Duplex */ - uc_speed = true; - uc_fd = false; - } - - if ((ul_stat1 & GMII_10BASE_T_HD) && (ul_stat2 & GMII_10_HDX)) { - /* Set MII for 10BaseT and Half Duplex */ - uc_speed = false; - uc_fd = false; - } - - gmac_set_speed(p_gmac, uc_speed); - gmac_enable_full_duplex(p_gmac, uc_fd); - - /* Start the GMAC transfers */ - gmac_enable_management(p_gmac, false); - return uc_rc; -} - - -/** - * \brief Issue an auto negotiation of the PHY. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * - * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t ethernet_phy_auto_negotiate(Gmac *p_gmac, uint8_t uc_phy_addr) -{ - uint32_t ul_retry_max = ETH_PHY_RETRY_MAX; - uint32_t ul_value; - uint32_t ul_phy_anar; - uint32_t ul_phy_analpar; - uint32_t ul_retry_count = 0; - uint8_t uc_speed = 0; - uint8_t uc_fd=0; - uint8_t uc_rc = GMAC_TIMEOUT; - - gmac_enable_management(p_gmac, true); - - /* Set up control register */ - uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMCR, &ul_value); - if (uc_rc != GMAC_OK) { - gmac_enable_management(p_gmac, false); - return uc_rc; - } - - ul_value &= ~(uint32_t)GMII_AUTONEG; /* Remove auto-negotiation enable */ - ul_value &= ~(uint32_t)(GMII_LOOPBACK | GMII_POWER_DOWN); - ul_value |= (uint32_t)GMII_ISOLATE; /* Electrically isolate PHY */ - uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value); - if (uc_rc != GMAC_OK) { - gmac_enable_management(p_gmac, false); - return uc_rc; - } - - /* - * Set the Auto_negotiation Advertisement Register. - * MII advertising for Next page. - * 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3. - */ - ul_phy_anar = GMII_100TX_FDX | GMII_100TX_HDX | GMII_10_FDX | GMII_10_HDX | - GMII_AN_IEEE_802_3; - uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_ANAR, ul_phy_anar); - if (uc_rc != GMAC_OK) { - gmac_enable_management(p_gmac, false); - return uc_rc; - } - - /* Read & modify control register */ - uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMCR, &ul_value); - if (uc_rc != GMAC_OK) { - gmac_enable_management(p_gmac, false); - return uc_rc; - } - - ul_value |= GMII_SPEED_SELECT | GMII_AUTONEG | GMII_DUPLEX_MODE; - uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value); - if (uc_rc != GMAC_OK) { - gmac_enable_management(p_gmac, false); - return uc_rc; - } - - /* Restart auto negotiation */ - ul_value |= (uint32_t)GMII_RESTART_AUTONEG; - ul_value &= ~(uint32_t)GMII_ISOLATE; - uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value); - if (uc_rc != GMAC_OK) { - gmac_enable_management(p_gmac, false); - return uc_rc; - } - - /* Check if auto negotiation is completed */ - while (1) { - uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMSR, &ul_value); - if (uc_rc != GMAC_OK) { - gmac_enable_management(p_gmac, false); - return uc_rc; - } - /* Done successfully */ - if (ul_value & GMII_AUTONEG_COMP) { - break; - } - - /* Timeout check */ - if (ul_retry_max) { - if (++ul_retry_count >= ul_retry_max) { - gmac_enable_management(p_gmac, false); - return GMAC_TIMEOUT; - } - } - } - - /* Get the auto negotiate link partner base page */ - uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_PCR1, &ul_phy_analpar); - if (uc_rc != GMAC_OK) { - gmac_enable_management(p_gmac, false); - return uc_rc; - } - - - /* Set up the GMAC link speed */ - if ((ul_phy_anar & ul_phy_analpar) & GMII_100TX_FDX) { - /* Set MII for 100BaseTX and Full Duplex */ - uc_speed = true; - uc_fd = true; - } else if ((ul_phy_anar & ul_phy_analpar) & GMII_10_FDX) { - /* Set MII for 10BaseT and Full Duplex */ - uc_speed = false; - uc_fd = true; - } else if ((ul_phy_anar & ul_phy_analpar) & GMII_100TX_HDX) { - /* Set MII for 100BaseTX and half Duplex */ - uc_speed = true; - uc_fd = false; - } else if ((ul_phy_anar & ul_phy_analpar) & GMII_10_HDX) { - /* Set MII for 10BaseT and half Duplex */ - uc_speed = false; - uc_fd = false; - } - - gmac_set_speed(p_gmac, uc_speed); - gmac_enable_full_duplex(p_gmac, uc_fd); - - /* Select Media Independent Interface type */ - gmac_select_mii_mode(p_gmac, ETH_PHY_MODE); - - gmac_enable_transmit(GMAC, true); - gmac_enable_receive(GMAC, true); - - gmac_enable_management(p_gmac, false); - return uc_rc; -} - -/** - * \brief Issue a SW reset to reset all registers of the PHY. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * - * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t ethernet_phy_reset(Gmac *p_gmac, uint8_t uc_phy_addr) -{ - uint32_t ul_bmcr = GMII_RESET; - uint8_t uc_phy_address = uc_phy_addr; - uint32_t ul_timeout = ETH_PHY_TIMEOUT; - uint8_t uc_rc = GMAC_TIMEOUT; - - gmac_enable_management(p_gmac, true); - - ul_bmcr = GMII_RESET; - gmac_phy_write(p_gmac, uc_phy_address, GMII_BMCR, ul_bmcr); - - do { - gmac_phy_read(p_gmac, uc_phy_address, GMII_BMCR, &ul_bmcr); - ul_timeout--; - } while ((ul_bmcr & GMII_RESET) && ul_timeout); - - gmac_enable_management(p_gmac, false); - - if (!ul_timeout) { - uc_rc = GMAC_OK; - } - - return (uc_rc); -} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \} - */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/ksz8051mnl/ethernet_phy.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/ksz8051mnl/ethernet_phy.h deleted file mode 100644 index bb6c1bffa..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/components/ethernet_phy/ksz8051mnl/ethernet_phy.h +++ /dev/null @@ -1,211 +0,0 @@ -/** - * \file - * - * \brief KSZ8051MNL (Ethernet PHY) driver for SAM. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ETHERNET_PHY_H_INCLUDED -#define ETHERNET_PHY_H_INCLUDED - -#include "compiler.h" - -// IEEE defined Registers -#define GMII_BMCR 0x00 // Basic Control -#define GMII_BMSR 0x01 // Basic Status -#define GMII_PHYID1 0x02 // PHY Idendifier 1 -#define GMII_PHYID2 0x03 // PHY Idendifier 2 -#define GMII_ANAR 0x04 // Auto_Negotiation Advertisement -#define GMII_ANLPAR 0x05 // Auto_negotiation Link Partner Ability -#define GMII_ANER 0x06 // Auto-negotiation Expansion -#define GMII_ANNPR 0x07 // Auto-negotiation Next Page -#define GMII_ANLPNPAR 0x08 // Link Partner Next Page Ability -//#define GMII_1000BTCR 9 // 1000Base-T Control // Reserved -//#define GMII_1000BTSR 10 // 1000Base-T Status // Reserved -#define GMII_AFECR1 0x11 // AFE Control 1 -//#define GMII_ERDWR 12 // Extend Register - Data Write Register -//#define GMII_ERDRR 13 // Extend Register - Data Read Register -//14 reserved -#define GMII_RXERCR 0x15 // RXER Counter - -#define GMII_OMSOR 0x16 // Operation Mode Strap Override -#define GMII_OMSSR 0x17 // Operation Mode Strap Status -#define GMII_ECR 0x18 // Expanded Control -//#define GMII_DPPSR 19 // Digital PMA/PCS Status -//20 reserved -//#define GMII_RXERCR 21 // RXER Counter Register -//22-26 reserved -#define GMII_ICSR 0x1B // Interrupt Control/Status -//#define GMII_DDC1R 28 // Digital Debug Control 1 Register -#define GMII_LCSR 0x1D // LinkMD Control/Status - -//29-30 reserved -#define GMII_PCR1 0x1E // PHY Control 1 -#define GMII_PCR2 0x1F // PHY Control 2 - -/* -//Extend Registers -#define GMII_CCR 256 // Common Control Register -#define GMII_SSR 257 // Strap Status Register -#define GMII_OMSOR 258 // Operation Mode Strap Override Register -#define GMII_OMSSR 259 // Operation Mode Strap Status Register -#define GMII_RCCPSR 260 // RGMII Clock and Control Pad Skew Register -#define GMII_RRDPSR 261 // RGMII RX Data Pad Skew Register -#define GMII_ATR 263 // Analog Test Register -*/ - - -// Bit definitions: GMII_BMCR 0x00 Basic Control -#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation -#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation -#define GMII_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps -#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable -#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation -#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation -#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation -#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation -#define GMII_COLLISION_TEST (1 << 7) // 1 = Enable COL test; 0 = Disable COL test -//#define GMII_SPEED_SELECT_MSB (1 << 6) // Reserved -// Reserved 6 to 0 // Read as 0, ignore on write - -// Bit definitions: GMII_BMSR 0x01 Basic Status -#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable -#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable -#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable -#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable -#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable -// Reserved 10 to79 // Read as 0, ignore on write -//#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15 -// Reserved 7 -#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression -#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete -#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault -#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability -#define GMII_LINK_STATUS (1 << 2) // Link Status -#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect -#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability - - -// Bit definitions: GMII_PHYID1 0x02 PHY Idendifier 1 -// Bit definitions: GMII_PHYID2 0x03 PHY Idendifier 2 -#define GMII_LSB_MASK 0x3F -#define GMII_OUI_MSB 0x0022 -#define GMII_OUI_LSB 0x05 - - -// Bit definitions: GMII_ANAR 0x04 Auto_Negotiation Advertisement -// Bit definitions: GMII_ANLPAR 0x05 Auto_negotiation Link Partner Ability -#define GMII_NP (1 << 15) // Next page Indication -// Reserved 7 -#define GMII_RF (1 << 13) // Remote Fault -// Reserved 12 // Write as 0, ignore on read -#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) - // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) -#define GMII_100T4 (1 << 9) // 100BASE-T4 Support -#define GMII_100TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support -#define GMII_100TX_HDX (1 << 7) // 100BASE-TX Support -#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support -#define GMII_10_HDX (1 << 5) // 10BASE-T Support -// Selector 4 to 0 // Protocol Selection Bits -#define GMII_AN_IEEE_802_3 0x0001 // [00001] = IEEE 802.3 - - -// Bit definitions: GMII_ANER 0x06 Auto-negotiation Expansion -// Reserved 15 to 5 // Read as 0, ignore on write -#define GMII_PDF (1 << 4) // Local Device Parallel Detection Fault -#define GMII_LP_NP_ABLE (1 << 3) // Link Partner Next Page Able -#define GMII_NP_ABLE (1 << 2) // Local Device Next Page Able -#define GMII_PAGE_RX (1 << 1) // New Page Received -#define GMII_LP_AN_ABLE (1 << 0) // Link Partner Auto-negotiation Able - -/** - * \brief Perform a HW initialization to the PHY and set up clocks. - * - * This should be called only once to initialize the PHY pre-settings. - * The PHY address is the reset status of CRS, RXD[3:0] (the GmacPins' pullups). - * The COL pin is used to select MII mode on reset (pulled up for Reduced MII). - * The RXDV pin is used to select test mode on reset (pulled up for test mode). - * The above pins should be predefined for corresponding settings in resetPins. - * The GMAC peripheral pins are configured after the reset is done. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * \param ul_mck GMAC MCK. - * - * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t ethernet_phy_init(Gmac *p_gmac, uint8_t uc_phy_addr, uint32_t ul_mck); - - -/** - * \brief Get the Link & speed settings, and automatically set up the GMAC with the - * settings. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply. - * - * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t ethernet_phy_set_link(Gmac *p_gmac, uint8_t uc_phy_addr, - uint8_t uc_apply_setting_flag); - - -/** - * \brief Issue an auto negotiation of the PHY. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * - * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t ethernet_phy_auto_negotiate(Gmac *p_gmac, uint8_t uc_phy_addr); - -/** - * \brief Issue a SW reset to reset all registers of the PHY. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * - * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t ethernet_phy_reset(Gmac *p_gmac, uint8_t uc_phy_addr); - -#endif /* #ifndef ETHERNET_PHY_H_INCLUDED */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/ebi/smc/smc.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/ebi/smc/smc.c deleted file mode 100644 index 4e18e6f16..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/ebi/smc/smc.c +++ /dev/null @@ -1,429 +0,0 @@ -/** - * \file - * - * \brief Static Memory Controller (SMC) driver for SAM. - * - * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "smc.h" -#include "board.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \defgroup sam_drivers_smc_group Static Memory Controller (SMC) - * - * Driver for the Static Memory Controller. It provides functions for configuring - * and using the on-chip SMC. - * - * @{ - */ - -#if ((SAM3S) || (SAM3U) || (SAM3XA) || (SAM4S) || (SAM4E)) -#define SMC_WPKEY_VALUE (0x534D43) -/** - * \brief Configure the SMC Setup timing for the specified Chip Select. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_cs Chip Select number to be set. - * \param ul_setup_timing Setup timing for NWE, NCS, NRD. - */ -void smc_set_setup_timing(Smc *p_smc, uint32_t ul_cs, - uint32_t ul_setup_timing) -{ - p_smc->SMC_CS_NUMBER[ul_cs].SMC_SETUP = ul_setup_timing; -} - -/** - * \brief Configure the SMC pulse timing for the specified Chip Select. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_cs Chip Select number to be set. - * \param ul_pulse_timing Pulse timing for NWE,NCS,NRD. - */ -void smc_set_pulse_timing(Smc *p_smc, uint32_t ul_cs, - uint32_t ul_pulse_timing) -{ - p_smc->SMC_CS_NUMBER[ul_cs].SMC_PULSE = ul_pulse_timing; -} - -/** - * \brief Configure the SMC cycle timing for the specified Chip Select. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_cs Chip Select number to be set. - * \param ul_cycle_timing Cycle timing for NWE and NRD. - */ -void smc_set_cycle_timing(Smc *p_smc, uint32_t ul_cs, - uint32_t ul_cycle_timing) -{ - p_smc->SMC_CS_NUMBER[ul_cs].SMC_CYCLE = ul_cycle_timing; -} - -/** - * \brief Configure the SMC mode for the specified Chip Select. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_cs Chip select number to be set. - * \param ul_mode SMC mode. - */ -void smc_set_mode(Smc *p_smc, uint32_t ul_cs, uint32_t ul_mode) -{ - p_smc->SMC_CS_NUMBER[ul_cs].SMC_MODE = ul_mode; -} - -/** - * \brief Get the SMC mode of the specified Chip Select. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_cs Chip select number to be set. - * - * \return SMC mode. - */ -uint32_t smc_get_mode(Smc *p_smc, uint32_t ul_cs) -{ - return p_smc->SMC_CS_NUMBER[ul_cs].SMC_MODE; -} - -/** - * \brief Set write protection of SMC registers. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_enable 1 to enable, 0 to disable. - */ -void smc_enable_writeprotect(Smc *p_smc, uint32_t ul_enable) -{ -#if (SAM3S || SAM4S || SAM4E) - if (ul_enable) - p_smc->SMC_WPMR = - SMC_WPMR_WPKEY(SMC_WPKEY_VALUE) | SMC_WPMR_WPEN; - else - p_smc->SMC_WPMR = SMC_WPMR_WPKEY(SMC_WPKEY_VALUE); -#else - if (ul_enable) - p_smc->SMC_WPCR = - SMC_WPCR_WP_KEY(SMC_WPKEY_VALUE) | - SMC_WPCR_WP_EN; - else - p_smc->SMC_WPCR = SMC_WPCR_WP_KEY(SMC_WPKEY_VALUE); -#endif -} - -/** - * \brief Get the status of SMC write protection register. - * - * \param p_smc Pointer to an SMC instance. - * - * \return Write protect status. - */ -uint32_t smc_get_writeprotect_status(Smc *p_smc) -{ - return p_smc->SMC_WPSR; -} -#endif /* ((SAM3S) || (SAM3U) || (SAM3XA)) */ - -#if ((SAM3U) || (SAM3XA)) -/** - * \brief Configure the SMC nand timing for the specified Chip Select. - * \param p_smc Pointer to an SMC instance. - * \param ul_cs Chip Select number to be set. - * \param ul_nand_timing nand timing for related signal. - */ -void smc_set_nand_timing(Smc *p_smc, uint32_t ul_cs, - uint32_t ul_nand_timing) -{ - p_smc->SMC_CS_NUMBER[ul_cs].SMC_TIMINGS= ul_nand_timing; -} - -/** - * \brief Initialize NFC configuration. - * \param p_smc Pointer to an SMC instance. - * \param ul_config SMC NFC Configuration. - */ -void smc_nfc_init(Smc *p_smc, uint32_t ul_config) -{ - p_smc->SMC_CFG = ul_config; -} - -/** - * \brief Set NFC page size. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_page_size Use pattern defined in the device header file. - */ -void smc_nfc_set_page_size(Smc *p_smc, uint32_t ul_page_size) -{ - p_smc->SMC_CFG &= (~SMC_CFG_PAGESIZE_Msk); - p_smc->SMC_CFG |= ul_page_size; -} - -/** - * \brief Enable NFC controller to read both main and spare area in read mode. - * - * \param p_smc Pointer to an SMC instance. - */ -void smc_nfc_enable_spare_read(Smc *p_smc) -{ - p_smc->SMC_CFG |= SMC_CFG_RSPARE; -} - -/** - * \brief Prevent NFC controller from reading the spare area in read mode. - * - * \param p_smc Pointer to an SMC instance. - */ -void smc_nfc_disable_spare_read(Smc *p_smc) -{ - p_smc->SMC_CFG &= (~SMC_CFG_RSPARE); -} - -/** - * \brief Enable NFC controller to write both main and spare area in write mode. - * - * \param p_smc Pointer to an SMC instance. - */ -void smc_nfc_enable_spare_write(Smc *p_smc) -{ - p_smc->SMC_CFG |= SMC_CFG_WSPARE; -} - -/** - * \brief Prevent NFC controller from writing the spare area in read mode. - * - * \param p_smc Pointer to an SMC instance. - */ -void smc_nfc_disable_spare_write(Smc *p_smc) -{ - p_smc->SMC_CFG &= (~SMC_CFG_WSPARE); -} - -/** - * \brief Enable NFC controller. - * - * \param p_smc Pointer to an SMC instance. - */ -void smc_nfc_enable(Smc *p_smc) -{ - p_smc->SMC_CTRL = SMC_CTRL_NFCEN; -} - -/** - * \brief Disable NFC controller. - * - * \param p_smc Pointer to an SMC instance. - */ -void smc_nfc_disable(Smc *p_smc) -{ - p_smc->SMC_CTRL = SMC_CTRL_NFCDIS; -} - -/** - * \brief Get the NFC Status. - * - * \param p_smc Pointer to an SMC instance. - * - * \return Returns the current status register of SMC NFC Status Register. - * This resets the internal value of the status register, so further - * read may yield different values. - */ -uint32_t smc_nfc_get_status(Smc *p_smc) -{ - return p_smc->SMC_SR; -} - -/** - * \brief Enable SMC interrupts. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_sources Interrupt source bitmap. - */ -void smc_nfc_enable_interrupt(Smc *p_smc, uint32_t ul_sources) -{ - p_smc->SMC_IER = ul_sources; -} - -/** - * \brief Disable SMC interrupts. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_sources Interrupt source bitmap. - */ -void smc_nfc_disable_interrupt(Smc *p_smc, uint32_t ul_sources) -{ - p_smc->SMC_IDR = ul_sources; -} - -/** - * \brief Get the interrupt mask. - * - * \param p_smc Pointer to an SMC instance. - * - * \return Interrupt mask bitmap. - */ -uint32_t smc_nfc_get_interrupt_mask(Smc *p_smc) -{ - return p_smc->SMC_IMR; -} - -/** - * \brief Set flash cycle 0 address. - * - * \param p_smc Pointer to an SMC instance. - * \param uc_address0 Address cycle 0 in 5 address cycles. - */ -void smc_nfc_set_address0(Smc *p_smc, uint8_t uc_address0) -{ - p_smc->SMC_ADDR = uc_address0; -} - -/** - * \brief Set NFC sram bank. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_bank NFC sram bank. - */ -void smc_nfc_set_bank(Smc *p_smc, uint32_t ul_bank) -{ - p_smc->SMC_BANK = SMC_BANK_BANK(ul_bank); -} - -/** - * \brief Use the HOST nandflash controller to send a command. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_cmd Command to send. - * \param ul_address_cycle Address cycle when command access is decoded. - * \param ul_cycle0 Address at first cycle. - */ -void smc_nfc_send_command(Smc *p_smc, uint32_t ul_cmd, - uint32_t ul_address_cycle, uint32_t ul_cycle0) -{ - volatile uint32_t *p_command_address; - - /* Wait until host controller is not busy. */ - while (((*((volatile uint32_t *)(BOARD_NF_DATA_ADDR + NFCADDR_CMD_NFCCMD))) - & NFC_BUSY_FLAG) == NFC_BUSY_FLAG) { - } - /* Send the command plus the ADDR_CYCLE. */ - p_command_address = (volatile uint32_t *)(ul_cmd + BOARD_NF_DATA_ADDR); - p_smc->SMC_ADDR = ul_cycle0; - *p_command_address = ul_address_cycle; - while (!((p_smc->SMC_SR & SMC_SR_CMDDONE) == SMC_SR_CMDDONE)) { - } -} - -/** - * \brief Initialize ECC mode. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_type Type of correction, use pattern defined in the device header file. - * \param ul_pagesize Page size of NAND Flash device, use pattern defined in - * the device header file. - */ -void smc_ecc_init(Smc *p_smc, uint32_t ul_type, uint32_t ul_pagesize) -{ - /* Software Reset ECC. */ - p_smc->SMC_ECC_CTRL = SMC_ECC_CTRL_SWRST; - p_smc->SMC_ECC_MD = ul_type | ul_pagesize; -} - -/** - * \brief Get ECC status by giving ecc number. - * - * \param p_smc Pointer to an SMC instance. - * \param ul_parity_number ECC parity number from 0 to 15. - * - * \return ECC status by giving ECC number. - */ -uint32_t smc_ecc_get_status(Smc *p_smc, uint32_t ul_parity_number) -{ - uint32_t status; - - if (ul_parity_number < 8) { - status = p_smc->SMC_ECC_SR1; - } else { - status = p_smc->SMC_ECC_SR2; - ul_parity_number -= 8; - } - - return ((status >> (ul_parity_number * 4)) & ECC_STATUS_MASK); -} - -/** - * \brief Get all ECC parity registers value. - * - * \param p_smc Pointer to an SMC instance. - * \param p_ecc Pointer to a parity buffer. - */ -void smc_ecc_get_value(Smc *p_smc, uint32_t *p_ecc) -{ - p_ecc[0] = p_smc->SMC_ECC_PR0; - p_ecc[1] = p_smc->SMC_ECC_PR1; - p_ecc[2] = p_smc->SMC_ECC_PR2; - p_ecc[3] = p_smc->SMC_ECC_PR3; - p_ecc[4] = p_smc->SMC_ECC_PR4; - p_ecc[5] = p_smc->SMC_ECC_PR5; - p_ecc[6] = p_smc->SMC_ECC_PR6; - p_ecc[7] = p_smc->SMC_ECC_PR7; - p_ecc[8] = p_smc->SMC_ECC_PR8; - p_ecc[9] = p_smc->SMC_ECC_PR9; - p_ecc[10] = p_smc->SMC_ECC_PR10; - p_ecc[11] = p_smc->SMC_ECC_PR11; - p_ecc[12] = p_smc->SMC_ECC_PR12; - p_ecc[13] = p_smc->SMC_ECC_PR13; - p_ecc[14] = p_smc->SMC_ECC_PR14; - p_ecc[15] = p_smc->SMC_ECC_PR15; -} -#endif /* ((SAM3U) || (SAM3XA)) */ - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/ebi/smc/smc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/ebi/smc/smc.h deleted file mode 100644 index 5ba786ba5..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/ebi/smc/smc.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * \file - * - * \brief Static Memory Controller (SMC) driver for SAM. - * - * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef SMC_H_INCLUDED -#define SMC_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -#if ((SAM3S) || (SAM3U) || (SAM3XA) || (SAM4S) || (SAM4E)) -void smc_set_setup_timing(Smc *p_smc, uint32_t ul_cs, uint32_t ul_setup_timing); -void smc_set_pulse_timing(Smc *p_smc, uint32_t ul_cs, uint32_t ul_pulse_timing); -void smc_set_cycle_timing(Smc *p_smc, uint32_t ul_cs, uint32_t ul_cycle_timing); -void smc_set_mode(Smc *p_smc, uint32_t ul_cs, uint32_t ul_mode); -uint32_t smc_get_mode(Smc *p_smc, uint32_t ul_cs); -void smc_enable_writeprotect(Smc *p_smc, uint32_t ul_enable); -uint32_t smc_get_writeprotect_status(Smc *p_smc); -#endif /* ((SAM3S) || (SAM3U) || (SAM3XA)) */ - -#if ((SAM3U) || (SAM3XA)) -/* NFCADDR_CMD : NFC Address Command */ -#define NFCADDR_CMD_CMD1 (0xFFu << 2) /* Command Register Value for Cycle 1 */ -#define NFCADDR_CMD_CMD2 (0xFFu << 10) /* Command Register Value for Cycle 2 */ -#define NFCADDR_CMD_VCMD2 (0x1u << 18) /* Valid Cycle 2 Command */ -#define NFCADDR_CMD_ACYCLE (0x7u << 19) /* Number of Address required for the current command */ -#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) /* No address cycle */ -#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) /* One address cycle */ -#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) /* Two address cycles */ -#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) /* Three address cycles */ -#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) /* Four address cycles */ -#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) /* Five address cycles */ -#define NFCADDR_CMD_CSID_Pos 22 -#define NFCADDR_CMD_CSID_Msk (0x7u << NFCADDR_CMD_CSID_Pos) /* Chip Select Identifier */ -#define NFCADDR_CMD_CSID(value) ((NFCADDR_CMD_CSID_Msk & ((value) << NFCADDR_CMD_CSID_Pos))) -#define NFCADDR_CMD_NFCEN (0x1u << 25) /* NFC Enable */ -#define NFCADDR_CMD_NFC_READ (0x0u << 26) /* NFC Write Enable */ -#define NFCADDR_CMD_NFC_WIRTE (0x1u << 26) /* NFC Write Enable */ -#define NFCADDR_CMD_NFCCMD (0x1u << 27) /* NFC Command Enable */ - -#define NFC_BUSY_FLAG 0x8000000 -#define ECC_STATUS_MASK 0x07 - -void smc_set_nand_timing(Smc * p_smc, uint32_t ul_cs, - uint32_t ul_nand_timing); -void smc_nfc_init(Smc *p_smc, uint32_t ul_config); -void smc_nfc_set_page_size(Smc *p_smc, uint32_t ul_page_size); -void smc_nfc_enable_spare_read(Smc *p_smc); -void smc_nfc_disable_spare_read(Smc *p_smc); -void smc_nfc_enable_spare_write(Smc *p_smc); -void smc_nfc_disable_spare_write(Smc *p_smc); -void smc_nfc_enable(Smc *p_smc); -void smc_nfc_disable(Smc *p_smc); -uint32_t smc_nfc_get_status(Smc * p_smc); -void smc_nfc_enable_interrupt(Smc *p_smc, uint32_t ul_sources); -void smc_nfc_disable_interrupt(Smc *p_smc, uint32_t ul_sources); -uint32_t smc_nfc_get_interrupt_mask(Smc *p_smc); -void smc_nfc_set_address0(Smc *p_smc, uint8_t uc_address0); -void smc_nfc_set_bank(Smc *p_smc, uint32_t ul_bank); -void smc_nfc_send_command(Smc *p_smc, uint32_t ul_cmd, uint32_t ul_address_cycle, uint32_t ul_cycle0); -void smc_ecc_init(Smc *p_smc, uint32_t ul_type, uint32_t ul_pagesize); -uint32_t smc_ecc_get_status(Smc *p_smc, uint32_t ul_parity_number); -void smc_ecc_get_value(Smc *p_smc, uint32_t *p_ecc); -#endif /* ((SAM3U) || (SAM3XA)) */ - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* SMC_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/gmac/gmac.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/gmac/gmac.c deleted file mode 100644 index 07e1c5a97..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/gmac/gmac.c +++ /dev/null @@ -1,783 +0,0 @@ - /** - * \file - * - * \brief GMAC (Ethernet MAC) driver for SAM. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "compiler.h" -#include "gmac.h" -#include -#include "conf_eth.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \defgroup gmac_group Ethernet Media Access Controller - * - * See \ref gmac_quickstart. - * - * Driver for the GMAC (Ethernet Media Access Controller). - * This file contains basic functions for the GMAC, with support for all modes, settings - * and clock speeds. - * - * \section dependencies Dependencies - * This driver does not depend on other modules. - * - * @{ - */ - -/** TX descriptor lists */ -COMPILER_ALIGNED(8) -static gmac_tx_descriptor_t gs_tx_desc[GMAC_TX_BUFFERS]; -/** TX callback lists */ -static gmac_dev_tx_cb_t gs_tx_callback[GMAC_TX_BUFFERS]; -/** RX descriptors lists */ -COMPILER_ALIGNED(8) -static gmac_rx_descriptor_t gs_rx_desc[GMAC_RX_BUFFERS]; -/** Send Buffer. Section 3.6 of AMBA 2.0 spec states that burst should not cross the - * 1K Boundaries. Receive buffer manager write operations are burst of 2 words => 3 lsb bits - * of the address shall be set to 0. - */ -COMPILER_ALIGNED(8) -static uint8_t gs_uc_tx_buffer[GMAC_TX_BUFFERS * GMAC_TX_UNITSIZE]; - -/** Receive Buffer */ -COMPILER_ALIGNED(8) -static uint8_t gs_uc_rx_buffer[GMAC_RX_BUFFERS * GMAC_RX_UNITSIZE]; - -/** - * GMAC device memory management struct. - */ -typedef struct gmac_dev_mem { - /* Pointer to allocated buffer for RX. The address should be 8-byte aligned - and the size should be GMAC_RX_UNITSIZE * wRxSize. */ - uint8_t *p_rx_buffer; - /* Pointer to allocated RX descriptor list. */ - gmac_rx_descriptor_t *p_rx_dscr; - /* RX size, in number of registered units (RX descriptors). */ - uint16_t us_rx_size; - /* Pointer to allocated buffer for TX. The address should be 8-byte aligned - and the size should be GMAC_TX_UNITSIZE * wTxSize. */ - uint8_t *p_tx_buffer; - /* Pointer to allocated TX descriptor list. */ - gmac_tx_descriptor_t *p_tx_dscr; - /* TX size, in number of registered units (TX descriptors). */ - uint16_t us_tx_size; -} gmac_dev_mem_t; - -/** Return count in buffer */ -#define CIRC_CNT(head,tail,size) (((head) - (tail)) % (size)) - -/* - * Return space available, from 0 to size-1. - * Always leave one free char as a completely full buffer that has (head == tail), - * which is the same as empty. - */ -#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) - -/** Circular buffer is empty ? */ -#define CIRC_EMPTY(head, tail) (head == tail) -/** Clear circular buffer */ -#define CIRC_CLEAR(head, tail) (head = tail = 0) - -/** Increment head or tail */ -static void circ_inc(uint16_t *headortail, uint32_t size) -{ - (*headortail)++; - if((*headortail) >= size) { - (*headortail) = 0; - } -} - -/** - * \brief Wait PHY operation to be completed. - * - * \param p_gmac HW controller address. - * \param ul_retry The retry times, 0 to wait forever until completeness. - * - * Return GMAC_OK if the operation is completed successfully. - */ -static uint8_t gmac_wait_phy(Gmac* p_gmac, const uint32_t ul_retry) -{ - volatile uint32_t ul_retry_count = 0; - - while (!gmac_is_phy_idle(p_gmac)) { - if (ul_retry == 0) { - continue; - } - - ul_retry_count++; - - if (ul_retry_count >= ul_retry) { - return GMAC_TIMEOUT; - } - } - return GMAC_OK; -} - -/** - * \brief Disable transfer, reset registers and descriptor lists. - * - * \param p_dev Pointer to GMAC driver instance. - * - */ -static void gmac_reset_tx_mem(gmac_device_t* p_dev) -{ - Gmac *p_hw = p_dev->p_hw; - uint8_t *p_tx_buff = p_dev->p_tx_buffer; - gmac_tx_descriptor_t *p_td = p_dev->p_tx_dscr; - - uint32_t ul_index; - uint32_t ul_address; - - /* Disable TX */ - gmac_enable_transmit(p_hw, 0); - - /* Set up the TX descriptors */ - CIRC_CLEAR(p_dev->us_tx_head, p_dev->us_tx_tail); - for (ul_index = 0; ul_index < p_dev->us_tx_list_size; ul_index++) { - ul_address = (uint32_t) (&(p_tx_buff[ul_index * GMAC_TX_UNITSIZE])); - p_td[ul_index].addr = ul_address; - p_td[ul_index].status.val = GMAC_TXD_USED; - } - p_td[p_dev->us_tx_list_size - 1].status.val = - GMAC_TXD_USED | GMAC_TXD_WRAP; - - /* Set transmit buffer queue */ - gmac_set_tx_queue(p_hw, (uint32_t) p_td); -} - -/** - * \brief Disable receiver, reset registers and descriptor list. - * - * \param p_drv Pointer to GMAC Driver instance. - */ -static void gmac_reset_rx_mem(gmac_device_t* p_dev) -{ - Gmac *p_hw = p_dev->p_hw; - uint8_t *p_rx_buff = p_dev->p_rx_buffer; - gmac_rx_descriptor_t *pRd = p_dev->p_rx_dscr; - - uint32_t ul_index; - uint32_t ul_address; - - /* Disable RX */ - gmac_enable_receive(p_hw, 0); - - /* Set up the RX descriptors */ - p_dev->us_rx_idx = 0; - for (ul_index = 0; ul_index < p_dev->us_rx_list_size; ul_index++) { - ul_address = (uint32_t) (&(p_rx_buff[ul_index * GMAC_RX_UNITSIZE])); - pRd[ul_index].addr.val = ul_address & GMAC_RXD_ADDR_MASK; - pRd[ul_index].status.val = 0; - } - pRd[p_dev->us_rx_list_size - 1].addr.val |= GMAC_RXD_WRAP; - - /* Set receive buffer queue */ - gmac_set_rx_queue(p_hw, (uint32_t) pRd); -} - - -/** - * \brief Initialize the allocated buffer lists for GMAC driver to transfer data. - * Must be invoked after gmac_dev_init() but before RX/TX starts. - * - * \note If input address is not 8-byte aligned, the address is automatically - * adjusted and the list size is reduced by one. - * - * \param p_gmac Pointer to GMAC instance. - * \param p_gmac_dev Pointer to GMAC device instance. - * \param p_dev_mm Pointer to the GMAC memory management control block. - * \param p_tx_cb Pointer to allocated TX callback list. - * - * \return GMAC_OK or GMAC_PARAM. - */ -static uint8_t gmac_init_mem(Gmac* p_gmac, gmac_device_t* p_gmac_dev, - gmac_dev_mem_t* p_dev_mm, - gmac_dev_tx_cb_t* p_tx_cb) -{ - if (p_dev_mm->us_rx_size <= 1 || p_dev_mm->us_tx_size <= 1 || p_tx_cb == NULL) { - return GMAC_PARAM; - } - - /* Assign RX buffers */ - if (((uint32_t) p_dev_mm->p_rx_buffer & 0x7) - || ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) { - p_dev_mm->us_rx_size--; - } - p_gmac_dev->p_rx_buffer = - (uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8); - p_gmac_dev->p_rx_dscr = - (gmac_rx_descriptor_t *) ((uint32_t) p_dev_mm->p_rx_dscr - & 0xFFFFFFF8); - p_gmac_dev->us_rx_list_size = p_dev_mm->us_rx_size; - - /* Assign TX buffers */ - if (((uint32_t) p_dev_mm->p_tx_buffer & 0x7) - || ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) { - p_dev_mm->us_tx_size--; - } - p_gmac_dev->p_tx_buffer = - (uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8); - p_gmac_dev->p_tx_dscr = - (gmac_tx_descriptor_t *) ((uint32_t) p_dev_mm->p_tx_dscr - & 0xFFFFFFF8); - p_gmac_dev->us_tx_list_size = p_dev_mm->us_tx_size; - p_gmac_dev->func_tx_cb_list = p_tx_cb; - - /* Reset TX & RX */ - gmac_reset_rx_mem(p_gmac_dev); - gmac_reset_tx_mem(p_gmac_dev); - - /* Enable Rx and Tx, plus the statistics register */ - gmac_enable_transmit(p_gmac, true); - gmac_enable_receive(p_gmac, true); - gmac_enable_statistics_write(p_gmac, true); - - /* Set up the interrupts for transmission and errors */ - gmac_enable_interrupt(p_gmac, - GMAC_IER_RXUBR | /* Enable receive used bit read interrupt. */ - GMAC_IER_TUR | /* Enable transmit underrun interrupt. */ - GMAC_IER_RLEX | /* Enable retry limit exceeded interrupt. */ - GMAC_IER_TFC | /* Enable transmit buffers exhausted in mid-frame interrupt. */ - GMAC_IER_TCOMP | /* Enable transmit complete interrupt. */ - GMAC_IER_ROVR | /* Enable receive overrun interrupt. */ - GMAC_IER_HRESP | /* Enable Hresp not OK interrupt. */ - GMAC_IER_PFNZ | /* Enable pause frame received interrupt. */ - GMAC_IER_PTZ); /* Enable pause time zero interrupt. */ - - return GMAC_OK; -} - -/** - * \brief Read the PHY register. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_address PHY address. - * \param uc_address Register address. - * \param p_value Pointer to a 32-bit location to store read data. - * - * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address, - uint32_t* p_value) -{ - gmac_maintain_phy(p_gmac, uc_phy_address, uc_address, 1, 0); - - if (gmac_wait_phy(p_gmac, MAC_PHY_RETRY_MAX) == GMAC_TIMEOUT) { - return GMAC_TIMEOUT; - } - *p_value = gmac_get_phy_data(p_gmac); - return GMAC_OK; -} - -/** - * \brief Write the PHY register. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_address PHY Address. - * \param uc_address Register Address. - * \param ul_value Data to write, actually 16-bit data. - * - * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. - */ -uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address, - uint8_t uc_address, uint32_t ul_value) -{ - gmac_maintain_phy(p_gmac, uc_phy_address, uc_address, 0, ul_value); - - if (gmac_wait_phy(p_gmac, MAC_PHY_RETRY_MAX) == GMAC_TIMEOUT) { - return GMAC_TIMEOUT; - } - return GMAC_OK; -} - -/** - * \brief Initialize the GMAC driver. - * - * \param p_gmac Pointer to the GMAC instance. - * \param p_gmac_dev Pointer to the GMAC device instance. - * \param p_opt GMAC configure options. - */ -void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev, - gmac_options_t* p_opt) -{ - gmac_dev_mem_t gmac_dev_mm; - - /* Disable TX & RX and more */ - gmac_network_control(p_gmac, 0); - gmac_disable_interrupt(p_gmac, ~0u); - - - gmac_clear_statistics(p_gmac); - - /* Clear all status bits in the receive status register. */ - gmac_clear_rx_status(p_gmac, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA); - - /* Clear all status bits in the transmit status register */ - gmac_clear_tx_status(p_gmac, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE - | GMAC_TSR_TFC | GMAC_TSR_TXCOMP | GMAC_TSR_UND); - - /* Clear interrupts */ - gmac_get_interrupt_status(p_gmac); - - /* Enable the copy of data into the buffers - ignore broadcasts, and not copy FCS. */ - gmac_set_configure(p_gmac, - gmac_get_configure(p_gmac) | GMAC_NCFGR_IRXFCS| GMAC_NCFGR_PEN); - - gmac_enable_copy_all(p_gmac, p_opt->uc_copy_all_frame); - gmac_disable_broadcast(p_gmac, p_opt->uc_no_boardcast); - - /* Fill in GMAC device memory management */ - gmac_dev_mm.p_rx_buffer = gs_uc_rx_buffer; - gmac_dev_mm.p_rx_dscr = gs_rx_desc; - gmac_dev_mm.us_rx_size = GMAC_RX_BUFFERS; - - gmac_dev_mm.p_tx_buffer = gs_uc_tx_buffer; - gmac_dev_mm.p_tx_dscr = gs_tx_desc; - gmac_dev_mm.us_tx_size = GMAC_TX_BUFFERS; - - gmac_init_mem(p_gmac, p_gmac_dev, &gmac_dev_mm, gs_tx_callback); - - gmac_set_address(p_gmac, 0, p_opt->uc_mac_addr); - -} - -/** - * \brief Frames can be read from the GMAC in multiple sections. - * Read ul_frame_size bytes from the GMAC receive buffers to pcTo. - * p_rcv_size is the size of the entire frame. Generally gmac_read - * will be repeatedly called until the sum of all the ul_frame_size equals - * the value of p_rcv_size. - * - * \param p_gmac_dev Pointer to the GMAC device instance. - * \param p_frame Address of the frame buffer. - * \param ul_frame_size Length of the frame. - * \param p_rcv_size Received frame size. - * - * \return GMAC_OK if receiving frame successfully, otherwise failed. - */ -uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame, - uint32_t ul_frame_size, uint32_t* p_rcv_size) -{ - uint16_t us_buffer_length; - uint32_t tmp_ul_frame_size = 0; - uint8_t *p_tmp_frame = 0; - uint16_t us_tmp_idx = p_gmac_dev->us_rx_idx; - gmac_rx_descriptor_t *p_rx_td = - &p_gmac_dev->p_rx_dscr[p_gmac_dev->us_rx_idx]; - int8_t c_is_frame = 0; - - if (p_frame == NULL) - return GMAC_PARAM; - - /* Set the default return value */ - *p_rcv_size = 0; - - /* Process received RX descriptor */ - while ((p_rx_td->addr.val & GMAC_RXD_OWNERSHIP) == GMAC_RXD_OWNERSHIP) { - /* A start of frame has been received, discard previous fragments */ - if ((p_rx_td->status.val & GMAC_RXD_SOF) == GMAC_RXD_SOF) { - /* Skip previous fragment */ - while (us_tmp_idx != p_gmac_dev->us_rx_idx) { - p_rx_td = &p_gmac_dev->p_rx_dscr[p_gmac_dev->us_rx_idx]; - p_rx_td->addr.val &= ~(GMAC_RXD_OWNERSHIP); - - circ_inc(&p_gmac_dev->us_rx_idx, p_gmac_dev->us_rx_list_size); - } - /* Reset the temporary frame pointer */ - p_tmp_frame = p_frame; - tmp_ul_frame_size = 0; - /* Start to gather buffers in a frame */ - c_is_frame = 1; - } - - /* Increment the pointer */ - circ_inc(&us_tmp_idx, p_gmac_dev->us_rx_list_size); - - /* Copy data in the frame buffer */ - if (c_is_frame) { - if (us_tmp_idx == p_gmac_dev->us_rx_idx) { - do { - p_rx_td = &p_gmac_dev->p_rx_dscr[p_gmac_dev->us_rx_idx]; - p_rx_td->addr.val &= ~(GMAC_RXD_OWNERSHIP); - circ_inc(&p_gmac_dev->us_rx_idx, p_gmac_dev->us_rx_list_size); - - } while (us_tmp_idx != p_gmac_dev->us_rx_idx); - - return GMAC_RX_NULL; - } - /* Copy the buffer into the application frame */ - us_buffer_length = GMAC_RX_UNITSIZE; - if ((tmp_ul_frame_size + us_buffer_length) > ul_frame_size) { - us_buffer_length = ul_frame_size - tmp_ul_frame_size; - } - - memcpy(p_tmp_frame, - (void *)(p_rx_td->addr.val & GMAC_RXD_ADDR_MASK), - us_buffer_length); - p_tmp_frame += us_buffer_length; - tmp_ul_frame_size += us_buffer_length; - - /* An end of frame has been received, return the data */ - if ((p_rx_td->status.val & GMAC_RXD_EOF) == GMAC_RXD_EOF) { - /* Frame size from the GMAC */ - *p_rcv_size = (p_rx_td->status.val & GMAC_RXD_LEN_MASK); - - /* All data have been copied in the application frame buffer => release TD */ - while (p_gmac_dev->us_rx_idx != us_tmp_idx) { - p_rx_td = &p_gmac_dev->p_rx_dscr[p_gmac_dev->us_rx_idx]; - p_rx_td->addr.val &= ~(GMAC_RXD_OWNERSHIP); - circ_inc(&p_gmac_dev->us_rx_idx, p_gmac_dev->us_rx_list_size); - } - - /* Application frame buffer is too small so that all data have not been copied */ - if (tmp_ul_frame_size < *p_rcv_size) { - return GMAC_SIZE_TOO_SMALL; - } - - return GMAC_OK; - } - } - /* SOF has not been detected, skip the fragment */ - else { - p_rx_td->addr.val &= ~(GMAC_RXD_OWNERSHIP); - p_gmac_dev->us_rx_idx = us_tmp_idx; - } - - /* Process the next buffer */ - p_rx_td = &p_gmac_dev->p_rx_dscr[us_tmp_idx]; - } - - return GMAC_RX_NULL; -} - -/** - * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the - * GMAC Tx buffers, and then indicates to the GMAC that the buffer is ready. - * If lEndOfFrame is true then the data being copied is the end of the frame - * and the frame can be transmitted. - * - * \param p_gmac_dev Pointer to the GMAC device instance. - * \param p_buffer Pointer to the data buffer. - * \param ul_size Length of the frame. - * \param func_tx_cb Transmit callback function. - * - * \return Length sent. - */ -uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer, - uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb) -{ - - volatile gmac_tx_descriptor_t *p_tx_td; - volatile gmac_dev_tx_cb_t *p_func_tx_cb; - - Gmac *p_hw = p_gmac_dev->p_hw; - - - /* Check parameter */ - if (ul_size > GMAC_TX_UNITSIZE) { - return GMAC_PARAM; - } - - /* Pointers to the current transmit descriptor */ - p_tx_td = &p_gmac_dev->p_tx_dscr[p_gmac_dev->us_tx_head]; - - /* If no free TxTd, buffer can't be sent, schedule the wakeup callback */ - if (CIRC_SPACE(p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_tail, - p_gmac_dev->us_tx_list_size) == 0) { - if (p_tx_td[p_gmac_dev->us_tx_head].status.val & GMAC_TXD_USED) - return GMAC_TX_BUSY; - } - - /* Pointers to the current Tx callback */ - p_func_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->us_tx_head]; - - /* Set up/copy data to transmission buffer */ - if (p_buffer && ul_size) { - /* Driver manages the ring buffer */ - memcpy((void *)p_tx_td->addr, p_buffer, ul_size); - } - - /* Tx callback */ - *p_func_tx_cb = func_tx_cb; - - /* Update transmit descriptor status */ - - /* The buffer size defined is the length of ethernet frame, - so it's always the last buffer of the frame. */ - if (p_gmac_dev->us_tx_head == p_gmac_dev->us_tx_list_size - 1) { - p_tx_td->status.val = - (ul_size & GMAC_TXD_LEN_MASK) | GMAC_TXD_LAST - | GMAC_TXD_WRAP; - } else { - p_tx_td->status.val = - (ul_size & GMAC_TXD_LEN_MASK) | GMAC_TXD_LAST; - } - - circ_inc(&p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_list_size); - - /* Now start to transmit if it is still not done */ - gmac_start_transmission(p_hw); - - return GMAC_OK; -} - -/** - * \brief Get current load of transmit. - * - * \param p_gmac_dev Pointer to the GMAC device instance. - * - * \return Current load of transmit. - */ -uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev) -{ - uint16_t us_head = p_gmac_dev->us_tx_head; - uint16_t us_tail = p_gmac_dev->us_tx_tail; - return CIRC_CNT(us_head, us_tail, p_gmac_dev->us_tx_list_size); -} - -/** - * \brief Register/Clear RX callback. Callback will be invoked after the next received - * frame. - * - * When gmac_dev_read() returns GMAC_RX_NULL, the application task calls - * gmac_dev_set_rx_callback() to register func_rx_cb() callback and enters suspend state. - * The callback is in charge to resume the task once a new frame has been - * received. The next time gmac_dev_read() is called, it will be successful. - * - * This function is usually invoked from the RX callback itself with NULL - * callback, to unregister. Once the callback has resumed the application task, - * there is no need to invoke the callback again. - * - * \param p_gmac_dev Pointer to the GMAC device instance. - * \param func_tx_cb Receive callback function. - */ -void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev, - gmac_dev_tx_cb_t func_rx_cb) -{ - Gmac *p_hw = p_gmac_dev->p_hw; - - if (func_rx_cb == NULL) { - gmac_disable_interrupt(p_hw, GMAC_IDR_RCOMP); - p_gmac_dev->func_rx_cb = NULL; - } else { - p_gmac_dev->func_rx_cb = func_rx_cb; - gmac_enable_interrupt(p_hw, GMAC_IER_RCOMP); - } -} - -/** - * \brief Register/Clear TX wakeup callback. - * - * When gmac_dev_write() returns GMAC_TX_BUSY (all transmit descriptor busy), the application - * task calls gmac_dev_set_tx_wakeup_callback() to register func_wakeup() callback and - * enters suspend state. The callback is in charge to resume the task once - * several transmit descriptors have been released. The next time gmac_dev_write() will be called, - * it shall be successful. - * - * This function is usually invoked with NULL callback from the TX wakeup - * callback itself, to unregister. Once the callback has resumed the - * application task, there is no need to invoke the callback again. - * - * \param p_gmac_dev Pointer to GMAC device instance. - * \param func_wakeup Pointer to wakeup callback function. - * \param uc_threshold Number of free transmit descriptor before wakeup callback invoked. - * - * \return GMAC_OK, GMAC_PARAM on parameter error. - */ -uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev, - gmac_dev_wakeup_cb_t func_wakeup_cb, uint8_t uc_threshold) -{ - if (func_wakeup_cb == NULL) { - p_gmac_dev->func_wakeup_cb = NULL; - } else { - if (uc_threshold <= p_gmac_dev->us_tx_list_size) { - p_gmac_dev->func_wakeup_cb = func_wakeup_cb; - p_gmac_dev->uc_wakeup_threshold = uc_threshold; - } else { - return GMAC_PARAM; - } - } - - return GMAC_OK; -} - - -/** - * \brief Reset TX & RX queue & statistics. - * - * \param p_gmac_dev Pointer to GMAC device instance. - */ -void gmac_dev_reset(gmac_device_t* p_gmac_dev) -{ - Gmac *p_hw = p_gmac_dev->p_hw; - - gmac_reset_rx_mem(p_gmac_dev); - gmac_reset_tx_mem(p_gmac_dev); - gmac_network_control(p_hw, GMAC_NCR_TXEN | GMAC_NCR_RXEN - | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT); -} - - -/** - * \brief GMAC Interrupt handler. - * - * \param p_gmac_dev Pointer to GMAC device instance. - */ -void gmac_handler(gmac_device_t* p_gmac_dev) -{ - Gmac *p_hw = p_gmac_dev->p_hw; - - gmac_tx_descriptor_t *p_tx_td; - gmac_dev_tx_cb_t *p_tx_cb; - volatile uint32_t ul_isr; - volatile uint32_t ul_rsr; - volatile uint32_t ul_tsr; - uint32_t ul_rx_status_flag; - uint32_t ul_tx_status_flag; - - ul_isr = gmac_get_interrupt_status(p_hw); - ul_rsr = gmac_get_rx_status(p_hw); - ul_tsr = gmac_get_tx_status(p_hw); - - ul_isr &= ~(gmac_get_interrupt_mask(p_hw) | 0xF8030300); - - /* RX packet */ - if ((ul_isr & GMAC_ISR_RCOMP) || (ul_rsr & GMAC_RSR_REC)) { - ul_rx_status_flag = GMAC_RSR_REC; - - /* Check OVR */ - if (ul_rsr & GMAC_RSR_RXOVR) { - ul_rx_status_flag |= GMAC_RSR_RXOVR; - } - /* Check BNA */ - if (ul_rsr & GMAC_RSR_BNA) { - ul_rx_status_flag |= GMAC_RSR_BNA; - } - /* Clear status */ - gmac_clear_rx_status(p_hw, ul_rx_status_flag); - - /* Invoke callbacks */ - if (p_gmac_dev->func_rx_cb) { - p_gmac_dev->func_rx_cb(ul_rx_status_flag); - } - } - - /* TX packet */ - if ((ul_isr & GMAC_ISR_TCOMP) || (ul_tsr & GMAC_TSR_TXCOMP)) { - - ul_tx_status_flag = GMAC_TSR_TXCOMP; - - /* A frame transmitted */ - - /* Check RLE */ - if (ul_tsr & GMAC_TSR_RLE) { - /* Status RLE & Number of discarded buffers */ - ul_tx_status_flag = GMAC_TSR_RLE | CIRC_CNT(p_gmac_dev->us_tx_head, - p_gmac_dev->us_tx_tail, p_gmac_dev->us_tx_list_size); - p_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->us_tx_tail]; - gmac_reset_tx_mem(p_gmac_dev); - gmac_enable_transmit(p_hw, 1); - } - /* Check COL */ - if (ul_tsr & GMAC_TSR_COL) { - ul_tx_status_flag |= GMAC_TSR_COL; - } - /* Check UND */ - if (ul_tsr & GMAC_TSR_UND) { - ul_tx_status_flag |= GMAC_TSR_UND; - } - /* Clear status */ - gmac_clear_tx_status(p_hw, ul_tx_status_flag); - - if (!CIRC_EMPTY(p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_tail)) { - /* Check the buffers */ - do { - p_tx_td = &p_gmac_dev->p_tx_dscr[p_gmac_dev->us_tx_tail]; - p_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->us_tx_tail]; - /* Any error? Exit if buffer has not been sent yet */ - if ((p_tx_td->status.val & GMAC_TXD_USED) == 0) { - break; - } - - /* Notify upper layer that a packet has been sent */ - if (*p_tx_cb) { - (*p_tx_cb) (ul_tx_status_flag); - } - - circ_inc(&p_gmac_dev->us_tx_tail, p_gmac_dev->us_tx_list_size); - } while (CIRC_CNT(p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_tail, - p_gmac_dev->us_tx_list_size)); - } - - if (ul_tsr & GMAC_TSR_RLE) { - /* Notify upper layer RLE */ - if (*p_tx_cb) { - (*p_tx_cb) (ul_tx_status_flag); - } - } - - /* If a wakeup has been scheduled, notify upper layer that it can - send other packets, and the sending will be successful. */ - if ((CIRC_SPACE(p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_tail, - p_gmac_dev->us_tx_list_size) >= p_gmac_dev->uc_wakeup_threshold) - && p_gmac_dev->func_wakeup_cb) { - p_gmac_dev->func_wakeup_cb(); - } - } -} - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/gmac/gmac.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/gmac/gmac.h deleted file mode 100644 index 2e1504d52..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/gmac/gmac.h +++ /dev/null @@ -1,1252 +0,0 @@ - /** - * \file - * - * \brief GMAC (Ethernet MAC) driver for SAM. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef GMAC_H_INCLUDED -#define GMAC_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** The buffer addresses written into the descriptors must be aligned, so the - last few bits are zero. These bits have special meaning for the GMAC - peripheral and cannot be used as part of the address. */ -#define GMAC_RXD_ADDR_MASK 0xFFFFFFFC -#define GMAC_RXD_WRAP (1ul << 1) /**< Wrap bit */ -#define GMAC_RXD_OWNERSHIP (1ul << 0) /**< Ownership bit */ - -#define GMAC_RXD_BROADCAST (1ul << 31) /**< Broadcast detected */ -#define GMAC_RXD_MULTIHASH (1ul << 30) /**< Multicast hash match */ -#define GMAC_RXD_UNIHASH (1ul << 29) /**< Unicast hash match */ -#define GMAC_RXD_ADDR_FOUND (1ul << 27) /**< Specific address match found */ -#define GMAC_RXD_ADDR (3ul << 25) /**< Address match */ -#define GMAC_RXD_RXCOEN (1ul << 24) /**< RXCOEN related function */ -#define GMAC_RXD_TYPE (3ul << 22) /**< Type ID match */ -#define GMAC_RXD_VLAN (1ul << 21) /**< VLAN tag detected */ -#define GMAC_RXD_PRIORITY (1ul << 20) /**< Priority tag detected */ -#define GMAC_RXD_PRIORITY_MASK (3ul << 17) /**< VLAN priority */ -#define GMAC_RXD_CFI (1ul << 16) /**< Concatenation Format Indicator only if bit 21 is set */ -#define GMAC_RXD_EOF (1ul << 15) /**< End of frame */ -#define GMAC_RXD_SOF (1ul << 14) /**< Start of frame */ -#define GMAC_RXD_FCS (1ul << 13) /**< Frame check sequence */ -#define GMAC_RXD_OFFSET_MASK /**< Receive buffer offset */ -#define GMAC_RXD_LEN_MASK (0xFFF) /**< Length of frame including FCS (if selected) */ -#define GMAC_RXD_LENJUMBO_MASK (0x3FFF) /**< Jumbo frame length */ - -#define GMAC_TXD_USED (1ul << 31) /**< Frame is transmitted */ -#define GMAC_TXD_WRAP (1ul << 30) /**< Last descriptor */ -#define GMAC_TXD_ERROR (1ul << 29) /**< Retry limit exceeded, error */ -#define GMAC_TXD_UNDERRUN (1ul << 28) /**< Transmit underrun */ -#define GMAC_TXD_EXHAUSTED (1ul << 27) /**< Buffer exhausted */ -#define GMAC_TXD_LATE (1ul << 26) /**< Late collision,transmit error */ -#define GMAC_TXD_CHECKSUM_ERROR (7ul << 20) /**< Checksum error */ -#define GMAC_TXD_NOCRC (1ul << 16) /**< No CRC */ -#define GMAC_TXD_LAST (1ul << 15) /**< Last buffer in frame */ -#define GMAC_TXD_LEN_MASK (0x1FFF) /**< Length of buffer */ - -/** The MAC can support frame lengths up to 1536 bytes */ -#define GMAC_FRAME_LENTGH_MAX 1536 - -#define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */ -#define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */ - -/** GMAC clock speed */ -#define GMAC_MCK_SPEED_240MHZ (240*1000*1000) -#define GMAC_MCK_SPEED_160MHZ (160*1000*1000) -#define GMAC_MCK_SPEED_120MHZ (120*1000*1000) -#define GMAC_MCK_SPEED_80MHZ (80*1000*1000) -#define GMAC_MCK_SPEED_40MHZ (40*1000*1000) -#define GMAC_MCK_SPEED_20MHZ (20*1000*1000) - -/** GMAC maintain code default value*/ -#define GMAC_MAN_CODE_VALUE (10) - -/** GMAC maintain start of frame default value*/ -#define GMAC_MAN_SOF_VALUE (1) - -/** GMAC maintain read/write*/ -#define GMAC_MAN_RW_TYPE (2) - -/** GMAC maintain read only*/ -#define GMAC_MAN_READ_ONLY (1) - -/** GMAC address length */ -#define GMAC_ADDR_LENGTH (6) - - -#define GMAC_DUPLEX_HALF 0 -#define GMAC_DUPLEX_FULL 1 - -#define GMAC_SPEED_10M 0 -#define GMAC_SPEED_100M 1 - -/** - * \brief Return codes for GMAC APIs. - */ -typedef enum { - GMAC_OK = 0, /** Operation OK */ - GMAC_TIMEOUT = 1, /** GMAC operation timeout */ - GMAC_TX_BUSY, /** TX in progress */ - GMAC_RX_NULL, /** No data received */ - GMAC_SIZE_TOO_SMALL, /** Buffer size not enough */ - GMAC_PARAM, /** Parameter error, TX packet invalid or RX size too small */ - GMAC_INVALID = 0xFF, /* Invalid */ -} gmac_status_t; - -/** - * \brief Media Independent Interface (MII) type. - */ -typedef enum { - GMAC_PHY_MII = 0, /** MII mode */ - GMAC_PHY_RMII = 1, /** Reduced MII mode */ - GMAC_PHY_INVALID = 0xFF, /* Invalid mode*/ -} gmac_mii_mode_t; - -/** Receive buffer descriptor struct */ -COMPILER_PACK_SET(8) -typedef struct gmac_rx_descriptor { - union gmac_rx_addr { - uint32_t val; - struct gmac_rx_addr_bm { - uint32_t b_ownership:1, /**< User clear, GMAC sets this to 1 once it has successfully written a frame to memory */ - b_wrap:1, /**< Marks last descriptor in receive buffer */ - addr_dw:30; /**< Address in number of DW */ - } bm; - } addr; /**< Address, Wrap & Ownership */ - union gmac_rx_status { - uint32_t val; - struct gmac_rx_status_bm { - uint32_t len:13, /** Length of frame including FCS */ - b_fcs:1, /** Receive buffer offset, bits 13:12 of frame length for jumbo frame */ - b_sof:1, /** Start of frame */ - b_eof:1, /** End of frame */ - b_cfi:1, /** Concatenation Format Indicator */ - vlan_priority:3, /** VLAN priority (if VLAN detected) */ - b_priority_detected:1, /** Priority tag detected */ - b_vlan_detected:1, /**< VLAN tag detected */ - b_type_id_match:2, /**< Type ID match */ - b_checksumoffload:1, /**< Checksum offload specific function */ - b_addrmatch:2, /**< Address register match */ - b_ext_addr_match:1, /**< External address match found */ - reserved:1, - b_uni_hash_match:1, /**< Unicast hash match */ - b_multi_hash_match:1, /**< Multicast hash match */ - b_boardcast_detect:1; /**< Global broadcast address detected */ - } bm; - } status; -} gmac_rx_descriptor_t; - -/** Transmit buffer descriptor struct */ -COMPILER_PACK_SET(8) -typedef struct gmac_tx_descriptor { - uint32_t addr; - union gmac_tx_status { - uint32_t val; - struct gmac_tx_status_bm { - uint32_t len:14, /**< Length of buffer */ - reserved:1, - b_last_buffer:1, /**< Last buffer (in the current frame) */ - b_no_crc:1, /**< No CRC */ - reserved1:3, - b_checksumoffload:3, /**< Transmit checksum generation offload errors */ - reserved2:3, - b_lco:1, /**< Late collision, transmit error detected */ - b_exhausted:1, /**< Buffer exhausted in mid frame */ - b_underrun:1, /**< Transmit underrun */ - b_error:1, /**< Retry limit exceeded, error detected */ - b_wrap:1, /**< Marks last descriptor in TD list */ - b_used:1; /**< User clear, GMAC sets this to 1 once a frame has been successfully transmitted */ - } bm; - } status; -} gmac_tx_descriptor_t; - -COMPILER_PACK_RESET() - -/** - * \brief Input parameters when initializing the gmac module mode. - */ -typedef struct gmac_options { - /* Enable/Disable CopyAllFrame */ - uint8_t uc_copy_all_frame; - /* Enable/Disable NoBroadCast */ - uint8_t uc_no_boardcast; - /* MAC address */ - uint8_t uc_mac_addr[GMAC_ADDR_LENGTH]; -} gmac_options_t; - -/** RX callback */ -typedef void (*gmac_dev_tx_cb_t) (uint32_t ul_status); -/** Wakeup callback */ -typedef void (*gmac_dev_wakeup_cb_t) (void); - -/** - * GMAC driver structure. - */ -typedef struct gmac_device { - - /** Pointer to HW register base */ - Gmac *p_hw; - /** - * Pointer to allocated TX buffer. - * Section 3.6 of AMBA 2.0 spec states that burst should not cross - * 1K Boundaries. - * Receive buffer manager writes are burst of 2 words => 3 lsb bits - * of the address shall be set to 0. - */ - uint8_t *p_tx_buffer; - /** Pointer to allocated RX buffer */ - uint8_t *p_rx_buffer; - /** Pointer to Rx TDs (must be 8-byte aligned) */ - gmac_rx_descriptor_t *p_rx_dscr; - /** Pointer to Tx TDs (must be 8-byte aligned) */ - gmac_tx_descriptor_t *p_tx_dscr; - /** Optional callback to be invoked once a frame has been received */ - gmac_dev_tx_cb_t func_rx_cb; - /** Optional callback to be invoked once several TDs have been released */ - gmac_dev_wakeup_cb_t func_wakeup_cb; - /** Optional callback list to be invoked once TD has been processed */ - gmac_dev_tx_cb_t *func_tx_cb_list; - /** RX TD list size */ - uint16_t us_rx_list_size; - /** RX index for current processing TD */ - uint16_t us_rx_idx; - /** TX TD list size */ - uint16_t us_tx_list_size; - /** Circular buffer head pointer by upper layer (buffer to be sent) */ - uint16_t us_tx_head; - /** Circular buffer tail pointer incremented by handlers (buffer sent) */ - uint16_t us_tx_tail; - - /** Number of free TD before wakeup callback is invoked */ - uint8_t uc_wakeup_threshold; -} gmac_device_t; - -/** - * \brief Write network control value. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_ncr Network control value. - */ -static inline void gmac_network_control(Gmac* p_gmac, uint32_t ul_ncr) -{ - p_gmac->GMAC_NCR = ul_ncr; -} - -/** - * \brief Get network control value. - * - * \param p_gmac Pointer to the GMAC instance. - */ - -static inline uint32_t gmac_get_network_control(Gmac* p_gmac) -{ - return p_gmac->GMAC_NCR; -} - -/** - * \brief Enable/Disable GMAC receive. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable GMAC receiver, else to enable it. - */ -static inline void gmac_enable_receive(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCR |= GMAC_NCR_RXEN; - } else { - p_gmac->GMAC_NCR &= ~GMAC_NCR_RXEN; - } -} - -/** - * \brief Enable/Disable GMAC transmit. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable GMAC transmit, else to enable it. - */ -static inline void gmac_enable_transmit(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCR |= GMAC_NCR_TXEN; - } else { - p_gmac->GMAC_NCR &= ~GMAC_NCR_TXEN; - } -} - -/** - * \brief Enable/Disable GMAC management. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable GMAC management, else to enable it. - */ -static inline void gmac_enable_management(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCR |= GMAC_NCR_MPE; - } else { - p_gmac->GMAC_NCR &= ~GMAC_NCR_MPE; - } -} - -/** - * \brief Clear all statistics registers. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_clear_statistics(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_CLRSTAT; -} - -/** - * \brief Increase all statistics registers. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_increase_statistics(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_INCSTAT; -} - -/** - * \brief Enable/Disable statistics registers writing. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable the statistics registers writing, else to enable it. - */ -static inline void gmac_enable_statistics_write(Gmac* p_gmac, - uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCR |= GMAC_NCR_WESTAT; - } else { - p_gmac->GMAC_NCR &= ~GMAC_NCR_WESTAT; - } -} - -/** - * \brief In half-duplex mode, forces collisions on all received frames. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable the back pressure, else to enable it. - */ -static inline void gmac_enable_back_pressure(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCR |= GMAC_NCR_BP; - } else { - p_gmac->GMAC_NCR &= ~GMAC_NCR_BP; - } -} - -/** - * \brief Start transmission. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_start_transmission(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_TSTART; -} - -/** - * \brief Halt transmission. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_halt_transmission(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_THALT; -} - -/** - * \brief Transmit pause frame. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_tx_pause_frame(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_TXPF; -} - -/** - * \brief Transmit zero quantum pause frame. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_tx_pause_zero_quantum_frame(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_TXZQPF; -} - -/** - * \brief Read snapshot. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_read_snapshot(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_RDS; -} - -/** - * \brief Store receivetime stamp to memory. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to normal operation, else to enable the store. - */ -static inline void gmac_store_rx_time_stamp(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCR |= GMAC_NCR_SRTSM; - } else { - p_gmac->GMAC_NCR &= ~GMAC_NCR_SRTSM; - } -} - -/** - * \brief Enable PFC priority-based pause reception. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 1 to set the reception, 0 to disable. - */ -static inline void gmac_enable_pfc_pause_frame(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCR |= GMAC_NCR_ENPBPR; - } else { - p_gmac->GMAC_NCR &= ~GMAC_NCR_ENPBPR; - } -} - -/** - * \brief Transmit PFC priority-based pause reception. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_transmit_pfc_pause_frame(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_TXPBPF; -} - -/** - * \brief Flush next packet. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_flush_next_packet(Gmac* p_gmac) -{ - p_gmac->GMAC_NCR |= GMAC_NCR_FNP; -} - -/** - * \brief Set up network configuration register. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_cfg Network configuration value. - */ -static inline void gmac_set_configure(Gmac* p_gmac, uint32_t ul_cfg) -{ - p_gmac->GMAC_NCFGR = ul_cfg; -} - -/** - * \brief Get network configuration. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return Network configuration. - */ -static inline uint32_t gmac_get_configure(Gmac* p_gmac) -{ - return p_gmac->GMAC_NCFGR; -} - -/** - * \brief Set speed. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps. - */ -static inline void gmac_set_speed(Gmac* p_gmac, uint8_t uc_speed) -{ - if (uc_speed) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_SPD; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD; - } -} - -/** - * \brief Enable/Disable Full-Duplex mode. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it. - */ -static inline void gmac_enable_full_duplex(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_FD; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD; - } -} - -/** - * \brief Enable/Disable Copy(Receive) All Valid Frames. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable copying all valid frames, else to enable it. - */ -static inline void gmac_enable_copy_all(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_CAF; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_CAF; - } -} - -/** - * \brief Enable/Disable jumbo frames (up to 10240 bytes). - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable the jumbo frames, else to enable it. - */ -static inline void gmac_enable_jumbo_frames(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_JFRAME; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_JFRAME; - } -} - -/** - * \brief Disable/Enable broadcast receiving. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 1 to disable the broadcast, else to enable it. - */ -static inline void gmac_disable_broadcast(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_NBC; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_NBC; - } -} - -/** - * \brief Enable/Disable multicast hash. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable the multicast hash, else to enable it. - */ -static inline void gmac_enable_multicast_hash(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN; - } -} - -/** - * \brief Enable/Disable big frames (over 1518, up to 1536). - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable big frames else to enable it. - */ -static inline void gmac_enable_big_frame(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_MAXFS; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_MAXFS; - } -} - -/** - * \brief Set MDC clock divider. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_mck GMAC MCK. - * - * \return GMAC_OK if successfully. - */ -static inline uint8_t gmac_set_mdc_clock(Gmac* p_gmac, uint32_t ul_mck) -{ - uint32_t ul_clk; - - if (ul_mck > GMAC_MCK_SPEED_240MHZ) { - return GMAC_INVALID; - } else if (ul_mck > GMAC_MCK_SPEED_160MHZ) { - ul_clk = GMAC_NCFGR_CLK_MCK_96; - } else if (ul_mck > GMAC_MCK_SPEED_120MHZ) { - ul_clk = GMAC_NCFGR_CLK_MCK_64; - } else if (ul_mck > GMAC_MCK_SPEED_80MHZ) { - ul_clk = GMAC_NCFGR_CLK_MCK_48; - } else if (ul_mck > GMAC_MCK_SPEED_40MHZ) { - ul_clk = GMAC_NCFGR_CLK_MCK_32; - } else if (ul_mck > GMAC_MCK_SPEED_20MHZ) { - ul_clk = GMAC_NCFGR_CLK_MCK_16; - } else { - ul_clk = GMAC_NCFGR_CLK_MCK_8; - } - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_CLK_Msk; - p_gmac->GMAC_NCFGR |= ul_clk; - return GMAC_OK; -} - -/** - * \brief Enable/Disable retry test. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable the GMAC receiver, else to enable it. - */ -static inline void gmac_enable_retry_test(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RTY; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RTY; - } -} - -/** - * \brief Enable/Disable pause (when a valid pause frame is received). - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable pause frame, else to enable it. - */ -static inline void gmac_enable_pause_frame(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_PEN; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_PEN; - } -} - -/** - * \brief Set receive buffer offset to 0 ~ 3. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline void gmac_set_rx_buffer_offset(Gmac* p_gmac, uint8_t uc_offset) -{ - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RXBUFO_Msk; - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RXBUFO(uc_offset); -} - -/** - * \brief Enable/Disable receive length field checking. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable receive length field checking, else to enable it. - */ -static inline void gmac_enable_rx_length_check(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_LFERD; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_LFERD; - } -} - -/** - * \brief Enable/Disable discarding FCS field of received frames. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable discarding FCS field of received frames, else to enable it. - */ -static inline void gmac_enable_discard_fcs(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RFCS; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RFCS; - } -} - - -/** - * \brief Enable/Disable frames to be received in half-duplex mode - * while transmitting. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable the received in half-duplex mode, else to enable it. - */ -static inline void gmac_enable_efrhd(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_EFRHD; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_EFRHD; - } -} - -/** - * \brief Enable/Disable ignore RX FCS. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_enable 0 to disable ignore RX FCS, else to enable it. - */ -static inline void gmac_enable_ignore_rx_fcs(Gmac* p_gmac, uint8_t uc_enable) -{ - if (uc_enable) { - p_gmac->GMAC_NCFGR |= GMAC_NCFGR_IRXFCS; - } else { - p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_IRXFCS; - } -} - -/** - * \brief Get Network Status. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return Network status. - */ -static inline uint32_t gmac_get_status(Gmac* p_gmac) -{ - return p_gmac->GMAC_NSR; -} - -/** - * \brief Get MDIO IN pin status. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return MDIO IN pin status. - */ -static inline uint8_t gmac_get_MDIO(Gmac* p_gmac) -{ - return ((p_gmac->GMAC_NSR & GMAC_NSR_MDIO) > 0); -} - -/** - * \brief Check if PHY is idle. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return 1 if PHY is idle. - */ -static inline uint8_t gmac_is_phy_idle(Gmac* p_gmac) -{ - return ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) > 0); -} - -/** - * \brief Return transmit status. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return Transmit status. - */ -static inline uint32_t gmac_get_tx_status(Gmac* p_gmac) -{ - return p_gmac->GMAC_TSR; -} - -/** - * \brief Clear transmit status. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_status Transmit status. - */ -static inline void gmac_clear_tx_status(Gmac* p_gmac, uint32_t ul_status) -{ - p_gmac->GMAC_TSR = ul_status; -} - -/** - * \brief Return receive status. - * - * \param p_gmac Pointer to the GMAC instance. - */ -static inline uint32_t gmac_get_rx_status(Gmac* p_gmac) -{ - return p_gmac->GMAC_RSR; -} - -/** - * \brief Clear receive status. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_status Receive status. - */ -static inline void gmac_clear_rx_status(Gmac* p_gmac, uint32_t ul_status) -{ - p_gmac->GMAC_RSR = ul_status; -} - -/** - * \brief Set Rx Queue. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_addr Rx queue address. - */ -static inline void gmac_set_rx_queue(Gmac* p_gmac, uint32_t ul_addr) -{ - p_gmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & ul_addr; -} - -/** - * \brief Get Rx Queue Address. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return Rx queue address. - */ -static inline uint32_t gmac_get_rx_queue(Gmac* p_gmac) -{ - return p_gmac->GMAC_RBQB; -} - -/** - * \brief Set Tx Queue. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_addr Tx queue address. - */ -static inline void gmac_set_tx_queue(Gmac* p_gmac, uint32_t ul_addr) -{ - p_gmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & ul_addr; -} - -/** - * \brief Get Tx Queue. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return Rx queue address. - */ -static inline uint32_t gmac_get_tx_queue(Gmac* p_gmac) -{ - return p_gmac->GMAC_TBQB; -} - -/** - * \brief Enable interrupt(s). - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_source Interrupt source(s) to be enabled. - */ -static inline void gmac_enable_interrupt(Gmac* p_gmac, uint32_t ul_source) -{ - p_gmac->GMAC_IER = ul_source; -} - -/** - * \brief Disable interrupt(s). - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_source Interrupt source(s) to be disabled. - */ -static inline void gmac_disable_interrupt(Gmac* p_gmac, uint32_t ul_source) -{ - p_gmac->GMAC_IDR = ul_source; -} - -/** - * \brief Return interrupt status. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return Interrupt status. - */ -static inline uint32_t gmac_get_interrupt_status(Gmac* p_gmac) -{ - return p_gmac->GMAC_ISR; -} - -/** - * \brief Return interrupt mask. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return Interrupt mask. - */ -static inline uint32_t gmac_get_interrupt_mask(Gmac* p_gmac) -{ - return p_gmac->GMAC_IMR; -} - -/** - * \brief Execute PHY maintenance command. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_phy_addr PHY address. - * \param uc_reg_addr Register address. - * \param uc_rw 1 to Read, 0 to write. - * \param us_data Data to be performed, write only. - */ -static inline void gmac_maintain_phy(Gmac* p_gmac, - uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw, - uint16_t us_data) -{ - /* Wait until bus idle */ - while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); - /* Write maintain register */ - p_gmac->GMAC_MAN = GMAC_MAN_WTN(GMAC_MAN_CODE_VALUE) - | GMAC_MAN_CLTTO - | GMAC_MAN_PHYA(uc_phy_addr) - | GMAC_MAN_REGA(uc_reg_addr) - | GMAC_MAN_OP((uc_rw ? GMAC_MAN_RW_TYPE : GMAC_MAN_READ_ONLY)) - | GMAC_MAN_DATA(us_data); -} - -/** - * \brief Get PHY maintenance data returned. - * - * \param p_gmac Pointer to the GMAC instance. - * - * \return Get PHY data. - */ -static inline uint16_t gmac_get_phy_data(Gmac* p_gmac) -{ - /* Wait until bus idle */ - while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); - /* Return data */ - return (uint16_t) (p_gmac->GMAC_MAN & GMAC_MAN_DATA_Msk); -} - -/** - * \brief Set Hash. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ul_hash_top Hash top. - * \param ul_hash_bottom Hash bottom. - */ -static inline void gmac_set_hash(Gmac* p_gmac, uint32_t ul_hash_top, - uint32_t ul_hash_bottom) -{ - p_gmac->GMAC_HRB = ul_hash_bottom; - p_gmac->GMAC_HRT = ul_hash_top; -} - -/** - * \brief Set 64 bits Hash. - * - * \param p_gmac Pointer to the GMAC instance. - * \param ull_hash 64 bits hash value. - */ -static inline void gmac_set_hash64(Gmac* p_gmac, uint64_t ull_hash) -{ - p_gmac->GMAC_HRB = (uint32_t) ull_hash; - p_gmac->GMAC_HRT = (uint32_t) (ull_hash >> 32); -} - -/** - * \brief Set MAC Address. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_index GMAC specific address register index. - * \param p_mac_addr GMAC address. - */ -static inline void gmac_set_address(Gmac* p_gmac, uint8_t uc_index, - uint8_t* p_mac_addr) -{ - p_gmac->GMAC_SA[uc_index].GMAC_SAB = (p_mac_addr[3] << 24) - | (p_mac_addr[2] << 16) - | (p_mac_addr[1] << 8) - | (p_mac_addr[0]); - p_gmac->GMAC_SA[uc_index].GMAC_SAT = (p_mac_addr[5] << 8) - | (p_mac_addr[4]); -} - -/** - * \brief Set MAC Address via 2 dword. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_index GMAC specific address register index. - * \param ul_mac_top GMAC top address. - * \param ul_mac_bottom GMAC bottom address. - */ -static inline void gmac_set_address32(Gmac* p_gmac, uint8_t uc_index, - uint32_t ul_mac_top, uint32_t ul_mac_bottom) -{ - p_gmac->GMAC_SA[uc_index].GMAC_SAB = ul_mac_bottom; - p_gmac->GMAC_SA[uc_index].GMAC_SAT = ul_mac_top; -} - -/** - * \brief Set MAC Address via int64. - * - * \param p_gmac Pointer to the GMAC instance. - * \param uc_index GMAC specific address register index. - * \param ull_mac 64-bit GMAC address. - */ -static inline void gmac_set_address64(Gmac* p_gmac, uint8_t uc_index, - uint64_t ull_mac) -{ - p_gmac->GMAC_SA[uc_index].GMAC_SAB = (uint32_t) ull_mac; - p_gmac->GMAC_SA[uc_index].GMAC_SAT = (uint32_t) (ull_mac >> 32); -} - -/** - * \brief Select media independent interface mode. - * - * \param p_gmac Pointer to the GMAC instance. - * \param mode Media independent interface mode. - */ -static inline void gmac_select_mii_mode(Gmac* p_gmac, gmac_mii_mode_t mode) -{ - switch (mode) { - case GMAC_PHY_MII: - case GMAC_PHY_RMII: - p_gmac->GMAC_UR |= GMAC_UR_RMIIMII; - break; - - default: - p_gmac->GMAC_UR &= ~GMAC_UR_RMIIMII; - break; - } -} - -uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address, - uint32_t* p_value); -uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address, - uint8_t uc_address, uint32_t ul_value); -void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev, - gmac_options_t* p_opt); -uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame, - uint32_t ul_frame_size, uint32_t* p_rcv_size); -uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer, - uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb); -uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev); -void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev, - gmac_dev_tx_cb_t func_rx_cb); -uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev, - gmac_dev_wakeup_cb_t func_wakeup, uint8_t uc_threshold); -void gmac_dev_reset(gmac_device_t* p_gmac_dev); -void gmac_handler(gmac_device_t* p_gmac_dev); - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \page gmac_quickstart Quickstart guide for GMAC driver. - * - * This is the quickstart guide for the \ref gmac_group "Ethernet MAC", - * with step-by-step instructions on how to configure and use the driver in a - * selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section gmac_basic_use_case Basic use case - * In the basic use case, the GMAC driver are configured for: - * - PHY component KSZ8051MNL is used - * - GMAC uses MII mode - * - The number of receive buffer is 16 - * - The number of transfer buffer is 8 - * - MAC address is set to 00-04-25-1c-a0-02 - * - IP address is set to 192.168.0.2 - * - IP address is set to 192.168.0.2 - * - Gateway is set to 192.168.0.1 - * - Network mask is 255.255.255.0 - * - PHY operation max retry count is 1000000 - * - GMAC is configured to not support copy all frame and support broadcast - * - The data will be read from the ethernet - * - * \section gmac_basic_use_case_setup Setup steps - * - * \subsection gmac_basic_use_case_setup_prereq Prerequisites - * -# \ref sysclk_group "System Clock Management (sysclock)" - * -# \ref pmc_group "Power Management Controller (pmc)" - * -# \ref ksz8051mnl_ethernet_phy_group "PHY component (KSZ8051MNL)" - * - * \subsection gmac_basic_use_case_setup_code Example code - * Content of conf_eth.h - * \code - * #define GMAC_RX_BUFFERS 16 - * #define GMAC_TX_BUFFERS 8 - * #define MAC_PHY_RETRY_MAX 1000000 - * #define ETHERNET_CONF_ETHADDR0 0x00 - * #define ETHERNET_CONF_ETHADDR0 0x00 - * #define ETHERNET_CONF_ETHADDR1 0x04 - * #define ETHERNET_CONF_ETHADDR2 0x25 - * #define ETHERNET_CONF_ETHADDR3 0x1C - * #define ETHERNET_CONF_ETHADDR4 0xA0 - * #define ETHERNET_CONF_ETHADDR5 0x02 - * #define ETHERNET_CONF_IPADDR0 192 - * #define ETHERNET_CONF_IPADDR1 168 - * #define ETHERNET_CONF_IPADDR2 0 - * #define ETHERNET_CONF_IPADDR3 2 - * #define ETHERNET_CONF_GATEWAY_ADDR0 192 - * #define ETHERNET_CONF_GATEWAY_ADDR1 168 - * #define ETHERNET_CONF_GATEWAY_ADDR2 0 - * #define ETHERNET_CONF_GATEWAY_ADDR3 1 - * #define ETHERNET_CONF_NET_MASK0 255 - * #define ETHERNET_CONF_NET_MASK1 255 - * #define ETHERNET_CONF_NET_MASK2 255 - * #define ETHERNET_CONF_NET_MASK3 0 - * #define ETH_PHY_MODE ETH_PHY_MODE - * \endcode - * - * A specific gmac device and the receive data buffer must be defined; another ul_frm_size should be defined - * to trace the actual size of the data received. - * \code - * static gmac_device_t gs_gmac_dev; - * static volatile uint8_t gs_uc_eth_buffer[GMAC_FRAME_LENTGH_MAX]; - * - * uint32_t ul_frm_size; - * \endcode - * - * Add to application C-file: - * \code - * void gmac_init(void) - * { - * sysclk_init(); - * - * board_init(); - * - * pmc_enable_periph_clk(ID_GMAC); - * - * gmac_option.uc_copy_all_frame = 0; - * gmac_option.uc_no_boardcast = 0; - * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); - * gs_gmac_dev.p_hw = GMAC; - * - * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); - * - * NVIC_EnableIRQ(GMAC_IRQn); - * - * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()); - * - * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR); - * - * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1); - * \endcode - * - * \subsection gmac_basic_use_case_setup_flow Workflow - * -# Ensure that conf_eth.h is present and contains the - * following configuration symbol. This configuration file is used - * by the driver and should not be included by the user. - * - \code - * #define GMAC_RX_BUFFERS 16 - * #define GMAC_TX_BUFFERS 8 - * #define MAC_PHY_RETRY_MAX 1000000 - * #define ETHERNET_CONF_ETHADDR0 0x00 - * #define ETHERNET_CONF_ETHADDR0 0x00 - * #define ETHERNET_CONF_ETHADDR1 0x04 - * #define ETHERNET_CONF_ETHADDR2 0x25 - * #define ETHERNET_CONF_ETHADDR3 0x1C - * #define ETHERNET_CONF_ETHADDR4 0xA0 - * #define ETHERNET_CONF_ETHADDR5 0x02 - * #define ETHERNET_CONF_IPADDR0 192 - * #define ETHERNET_CONF_IPADDR1 168 - * #define ETHERNET_CONF_IPADDR2 0 - * #define ETHERNET_CONF_IPADDR3 2 - * #define ETHERNET_CONF_GATEWAY_ADDR0 192 - * #define ETHERNET_CONF_GATEWAY_ADDR1 168 - * #define ETHERNET_CONF_GATEWAY_ADDR2 0 - * #define ETHERNET_CONF_GATEWAY_ADDR3 1 - * #define ETHERNET_CONF_NET_MASK0 255 - * #define ETHERNET_CONF_NET_MASK1 255 - * #define ETHERNET_CONF_NET_MASK2 255 - * #define ETHERNET_CONF_NET_MASK3 0 - * #define ETH_PHY_MODE GMAC_PHY_MII - * \endcode - * -# Enable the system clock: - * - \code sysclk_init(); \endcode - * -# Enable PIO configurations for GMAC: - * - \code board_init(); \endcode - * -# Enable PMC clock for GMAC: - * - \code pmc_enable_periph_clk(ID_GMAC); \endcode - * -# Set the GMAC options; it's set to copy all frame and support broadcast: - * - \code - * gmac_option.uc_copy_all_frame = 0; - * gmac_option.uc_no_boardcast = 0; - * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); - * gs_gmac_dev.p_hw = GMAC; - * \endcode - * -# Initialize GMAC device with the filled option: - * - \code - * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); - * \endcode - * -# Enable the interrupt service for GMAC: - * - \code - * NVIC_EnableIRQ(GMAC_IRQn); - * \endcode - * -# Initialize the PHY component: - * - \code - * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()); - * \endcode - * -# The link will be established based on auto negotiation. - * - \code - * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR); - * \endcode - * -# Establish the ethernet link; the network can be worked from now on: - * - \code - * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1); - * \endcode - * - * \section gmac_basic_use_case_usage Usage steps - * \subsection gmac_basic_use_case_usage_code Example code - * Add to, e.g., main loop in application C-file: - * \code - * gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); - * \endcode - * - * \subsection gmac_basic_use_case_usage_flow Workflow - * -# Start reading the data from the ethernet: - * - \code gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); \endcode - */ - -#endif /* GMAC_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/pmc.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/pmc.c deleted file mode 100644 index 28565bbbe..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/pmc.c +++ /dev/null @@ -1,1294 +0,0 @@ -/** - * \file - * - * \brief Power Management Controller (PMC) driver for SAM. - * - * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "pmc.h" - -#if (SAM3N) -# define MAX_PERIPH_ID 31 -#elif (SAM3XA) -# define MAX_PERIPH_ID 44 -#elif (SAM3U) -# define MAX_PERIPH_ID 29 -#elif (SAM3S || SAM4S) -# define MAX_PERIPH_ID 34 -#elif (SAM4E) -# define MAX_PERIPH_ID 47 -#elif (SAM4N) -# define MAX_PERIPH_ID 31 -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** - * \defgroup sam_drivers_pmc_group Power Management Controller (PMC) - * - * \par Purpose - * - * The Power Management Controller (PMC) optimizes power consumption by - * controlling all system and user peripheral clocks. The PMC enables/disables - * the clock inputs to many of the peripherals and the Cortex-M Processor. - * - * @{ - */ - -/** - * \brief Set the prescaler of the MCK. - * - * \param ul_pres Prescaler value. - */ -void pmc_mck_set_prescaler(uint32_t ul_pres) -{ - PMC->PMC_MCKR = - (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); -} - -/** - * \brief Set the source of the MCK. - * - * \param ul_source Source selection value. - */ -void pmc_mck_set_source(uint32_t ul_source) -{ - PMC->PMC_MCKR = - (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); -} - -/** - * \brief Switch master clock source selection to slow clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_SLOW_CLK; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Switch master clock source selection to main clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_MAIN_CLK; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Switch master clock source selection to PLLA clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_PLLA_CLK; - - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -#if (SAM3S || SAM4S) -/** - * \brief Switch master clock source selection to PLLB clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_PLLB_CLK; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} -#endif - -#if (SAM3XA || SAM3U) -/** - * \brief Switch master clock source selection to UPLL clock. - * - * \param ul_pres Processor clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | - PMC_MCKR_CSS_UPLL_CLK; - for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} -#endif - -/** - * \brief Switch slow clock source selection to external 32k (Xtal or Bypass). - * - * \note This function disables the PLLs. - * - * \note Switching SCLK back to 32krc is only possible by shutting down the - * VDDIO power supply. - * - * \param ul_bypass 0 for Xtal, 1 for bypass. - */ -void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass) -{ - /* Set Bypass mode if required */ - if (ul_bypass == 1) { - SUPC->SUPC_MR |= SUPC_MR_KEY(SUPC_KEY_VALUE) | - SUPC_MR_OSCBYPASS; - } - - SUPC->SUPC_CR = SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_XTALSEL; -} - -/** - * \brief Check if the external 32k Xtal is ready. - * - * \retval 1 External 32k Xtal is ready. - * \retval 0 External 32k Xtal is not ready. - */ -uint32_t pmc_osc_is_ready_32kxtal(void) -{ - return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) - && (PMC->PMC_SR & PMC_SR_OSCSELS)); -} - -/** - * \brief Switch main clock source selection to internal fast RC. - * - * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz). - * - * \retval 0 Success. - * \retval 1 Timeout error. - * \retval 2 Invalid frequency. - */ -void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf) -{ - uint32_t ul_needXTEN = 0; - - /* Enable Fast RC oscillator but DO NOT switch to RC now */ - if (PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN) { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | - PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN | - ul_moscrcf; - } else { - ul_needXTEN = 1; - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | - PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN | - CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST_Msk | - ul_moscrcf; - } - - /* Wait the Fast RC to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); - - /* Switch to Fast RC */ - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | - PMC_CKGR_MOR_KEY_VALUE; - - /* Disable xtal oscillator */ - if (ul_needXTEN) { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | - PMC_CKGR_MOR_KEY_VALUE; - } -} - -/** - * \brief Enable fast RC oscillator. - * - * \param ul_rc Fast RC oscillator(4/8/12Mhz). - */ -void pmc_osc_enable_fastrc(uint32_t ul_rc) -{ - /* Enable Fast RC oscillator but DO NOT switch to RC now. - * Keep MOSCSEL to 1 */ - PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL | - CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN | ul_rc; - /* Wait the Fast RC to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); -} - -/** - * \brief Disable the internal fast RC. - */ -void pmc_osc_disable_fastrc(void) -{ - /* Disable Fast RC oscillator */ - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & - ~CKGR_MOR_MOSCRCF_Msk) - | PMC_CKGR_MOR_KEY_VALUE; -} - -/** - * \brief Check if the main fastrc is ready. - * - * \retval 0 Xtal is not ready, otherwise ready. - */ -uint32_t pmc_osc_is_ready_fastrc(void) -{ - return (PMC->PMC_SR & PMC_SR_MOSCRCS); -} - -/** - * \brief Enable main XTAL oscillator. - * - * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks. - */ -void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time) -{ - uint32_t mor = PMC->CKGR_MOR; - mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); - mor |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN | - CKGR_MOR_MOSCXTST(ul_xtal_startup_time); - PMC->CKGR_MOR = mor; - /* Wait the main Xtal to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); -} - -/** - * \brief Bypass main XTAL. - */ -void pmc_osc_bypass_main_xtal(void) -{ - uint32_t mor = PMC->CKGR_MOR; - mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); - mor |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY; - /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */ - PMC->CKGR_MOR = mor; - /* The MOSCXTS in PMC_SR is automatically set */ -} - -/** - * \brief Disable the main Xtal. - */ -void pmc_osc_disable_main_xtal(void) -{ - uint32_t mor = PMC->CKGR_MOR; - mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); - PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | mor; -} - -/** - * \brief Check if the main crystal is bypassed. - * - * \retval 0 Xtal is bypassed, otherwise not. - */ -uint32_t pmc_osc_is_bypassed_main_xtal(void) -{ - return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY); -} - -/** - * \brief Check if the main crystal is ready. - * - * \note If main crystal is bypassed, it's always ready. - * - * \retval 0 main crystal is not ready, otherwise ready. - */ -uint32_t pmc_osc_is_ready_main_xtal(void) -{ - return (PMC->PMC_SR & PMC_SR_MOSCXTS); -} - -/** - * \brief Switch main clock source selection to external Xtal/Bypass. - * - * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid - * any system crash. - * - * \note If used in Xtal mode, the Xtal is automatically enabled. - * - * \param ul_bypass 0 for Xtal, 1 for bypass. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, - uint32_t ul_xtal_startup_time) -{ - /* Enable Main Xtal oscillator */ - if (ul_bypass) { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | - PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY | - CKGR_MOR_MOSCSEL; - } else { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | - PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN | - CKGR_MOR_MOSCXTST(ul_xtal_startup_time); - /* Wait the Xtal to stabilize */ - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); - - PMC->CKGR_MOR |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL; - } -} - -/** - * \brief Disable the external Xtal. - * - * \param ul_bypass 0 for Xtal, 1 for bypass. - */ -void pmc_osc_disable_xtal(uint32_t ul_bypass) -{ - /* Disable xtal oscillator */ - if (ul_bypass) { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | - PMC_CKGR_MOR_KEY_VALUE; - } else { - PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | - PMC_CKGR_MOR_KEY_VALUE; - } -} - -/** - * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one - * of Xtal, bypass or internal RC. - * - * \retval 1 Xtal is ready. - * \retval 0 Xtal is not ready. - */ -uint32_t pmc_osc_is_ready_mainck(void) -{ - return PMC->PMC_SR & PMC_SR_MOSCSELS; -} - -/** - * \brief Select Main Crystal or internal RC as main clock source. - * - * \note This function will not enable/disable RC or Main Crystal. - * - * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal. - */ -void pmc_mainck_osc_select(uint32_t ul_xtal_rc) -{ - uint32_t mor = PMC->CKGR_MOR; - if (ul_xtal_rc) { - mor |= CKGR_MOR_MOSCSEL; - } else { - mor &= ~CKGR_MOR_MOSCSEL; - } - PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | mor; -} - -/** - * \brief Enable PLLA clock. - * - * \param mula PLLA multiplier. - * \param pllacount PLLA counter. - * \param diva Divider. - */ -void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva) -{ - /* first disable the PLL to unlock the lock */ - pmc_disable_pllack(); - - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) | - CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); - while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0); -} - -/** - * \brief Disable PLLA clock. - */ -void pmc_disable_pllack(void) -{ - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0); -} - -/** - * \brief Is PLLA locked? - * - * \retval 0 Not locked. - * \retval 1 Locked. - */ -uint32_t pmc_is_locked_pllack(void) -{ - return (PMC->PMC_SR & PMC_SR_LOCKA); -} - -#if (SAM3S || SAM4S) -/** - * \brief Enable PLLB clock. - * - * \param mulb PLLB multiplier. - * \param pllbcount PLLB counter. - * \param divb Divider. - */ -void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb) -{ - /* first disable the PLL to unlock the lock */ - pmc_disable_pllbck(); - - PMC->CKGR_PLLBR = - CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount) - | CKGR_PLLBR_MULB(mulb); - while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0); -} - -/** - * \brief Disable PLLB clock. - */ -void pmc_disable_pllbck(void) -{ - PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0); -} - -/** - * \brief Is PLLB locked? - * - * \retval 0 Not locked. - * \retval 1 Locked. - */ -uint32_t pmc_is_locked_pllbck(void) -{ - return (PMC->PMC_SR & PMC_SR_LOCKB); -} -#endif - -#if (SAM3XA || SAM3U) -/** - * \brief Enable UPLL clock. - */ -void pmc_enable_upll_clock(void) -{ - PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN; - - /* Wait UTMI PLL Lock Status */ - while (!(PMC->PMC_SR & PMC_SR_LOCKU)); -} - -/** - * \brief Disable UPLL clock. - */ -void pmc_disable_upll_clock(void) -{ - PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; -} - -/** - * \brief Is UPLL locked? - * - * \retval 0 Not locked. - * \retval 1 Locked. - */ -uint32_t pmc_is_locked_upll(void) -{ - return (PMC->PMC_SR & PMC_SR_LOCKU); -} -#endif - -/** - * \brief Enable the specified peripheral clock. - * - * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). - * - * \param ul_id Peripheral ID (ID_xxx). - * - * \retval 0 Success. - * \retval 1 Invalid parameter. - */ -uint32_t pmc_enable_periph_clk(uint32_t ul_id) -{ - if (ul_id > MAX_PERIPH_ID) { - return 1; - } - - if (ul_id < 32) { - if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { - PMC->PMC_PCER0 = 1 << ul_id; - } -#if (SAM3S || SAM3XA || SAM4S || SAM4E) - } else { - ul_id -= 32; - if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { - PMC->PMC_PCER1 = 1 << ul_id; - } -#endif - } - - return 0; -} - -/** - * \brief Disable the specified peripheral clock. - * - * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). - * - * \param ul_id Peripheral ID (ID_xxx). - * - * \retval 0 Success. - * \retval 1 Invalid parameter. - */ -uint32_t pmc_disable_periph_clk(uint32_t ul_id) -{ - if (ul_id > MAX_PERIPH_ID) { - return 1; - } - - if (ul_id < 32) { - if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) { - PMC->PMC_PCDR0 = 1 << ul_id; - } -#if (SAM3S || SAM3XA || SAM4S || SAM4E) - } else { - ul_id -= 32; - if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) { - PMC->PMC_PCDR1 = 1 << ul_id; - } -#endif - } - return 0; -} - -/** - * \brief Enable all peripheral clocks. - */ -void pmc_enable_all_periph_clk(void) -{ - PMC->PMC_PCER0 = PMC_MASK_STATUS0; - while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0); - -#if (SAM3S || SAM3XA || SAM4S || SAM4E) - PMC->PMC_PCER1 = PMC_MASK_STATUS1; - while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1); -#endif -} - -/** - * \brief Disable all peripheral clocks. - */ -void pmc_disable_all_periph_clk(void) -{ - PMC->PMC_PCDR0 = PMC_MASK_STATUS0; - while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0); - -#if (SAM3S || SAM3XA || SAM4S || SAM4E) - PMC->PMC_PCDR1 = PMC_MASK_STATUS1; - while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0); -#endif -} - -/** - * \brief Check if the specified peripheral clock is enabled. - * - * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). - * - * \param ul_id Peripheral ID (ID_xxx). - * - * \retval 0 Peripheral clock is disabled or unknown. - * \retval 1 Peripheral clock is enabled. - */ -uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id) -{ - if (ul_id > MAX_PERIPH_ID) { - return 0; - } - -#if (SAM3S || SAM3XA || SAM4S || SAM4E) - if (ul_id < 32) { -#endif - if ((PMC->PMC_PCSR0 & (1u << ul_id))) { - return 1; - } else { - return 0; - } -#if (SAM3S || SAM3XA || SAM4S || SAM4E) - } else { - ul_id -= 32; - if ((PMC->PMC_PCSR1 & (1u << ul_id))) { - return 1; - } else { - return 0; - } - } -#endif -} - -/** - * \brief Set the prescaler for the specified programmable clock. - * - * \param ul_id Peripheral ID. - * \param ul_pres Prescaler value. - */ -void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres) -{ - PMC->PMC_PCK[ul_id] = - (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres; - while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) - && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); -} - -/** - * \brief Set the source oscillator for the specified programmable clock. - * - * \param ul_id Peripheral ID. - * \param ul_source Source selection value. - */ -void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source) -{ - PMC->PMC_PCK[ul_id] = - (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source; - while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) - && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); -} - -/** - * \brief Switch programmable clock source selection to slow clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Switch programmable clock source selection to main clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -/** - * \brief Switch programmable clock source selection to PLLA clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} - -#if (SAM3S || SAM4S) -/** - * \brief Switch programmable clock source selection to PLLB clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} -#endif - -#if (SAM3XA || SAM3U) -/** - * \brief Switch programmable clock source selection to UPLL clock. - * - * \param ul_id Id of the programmable clock. - * \param ul_pres Programmable clock prescaler. - * - * \retval 0 Success. - * \retval 1 Timeout error. - */ -uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres) -{ - uint32_t ul_timeout; - - PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres; - for (ul_timeout = PMC_TIMEOUT; - !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); - --ul_timeout) { - if (ul_timeout == 0) { - return 1; - } - } - - return 0; -} -#endif - -/** - * \brief Enable the specified programmable clock. - * - * \param ul_id Id of the programmable clock. - */ -void pmc_enable_pck(uint32_t ul_id) -{ - PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id; -} - -/** - * \brief Disable the specified programmable clock. - * - * \param ul_id Id of the programmable clock. - */ -void pmc_disable_pck(uint32_t ul_id) -{ - PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id; -} - -/** - * \brief Enable all programmable clocks. - */ -void pmc_enable_all_pck(void) -{ - PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2; -} - -/** - * \brief Disable all programmable clocks. - */ -void pmc_disable_all_pck(void) -{ - PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; -} - -/** - * \brief Check if the specified programmable clock is enabled. - * - * \param ul_id Id of the programmable clock. - * - * \retval 0 Programmable clock is disabled or unknown. - * \retval 1 Programmable clock is enabled. - */ -uint32_t pmc_is_pck_enabled(uint32_t ul_id) -{ - if (ul_id > 2) { - return 0; - } - - return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id)); -} - -#if (SAM3S || SAM3XA || SAM4S || SAM4E) -/** - * \brief Switch UDP (USB) clock source selection to PLLA clock. - * - * \param ul_usbdiv Clock divisor. - */ -void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv) -{ - PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); -} -#endif - -#if (SAM3S || SAM4S) -/** - * \brief Switch UDP (USB) clock source selection to PLLB clock. - * - * \param ul_usbdiv Clock divisor. - */ -void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv) -{ - PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; -} -#endif - -#if (SAM3XA) -/** - * \brief Switch UDP (USB) clock source selection to UPLL clock. - * - * \param dw_usbdiv Clock divisor. - */ -void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv) -{ - PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv); -} -#endif - -#if (SAM3S || SAM3XA || SAM4S || SAM4E) -/** - * \brief Enable UDP (USB) clock. - */ -void pmc_enable_udpck(void) -{ -# if (SAM3S || SAM4S || SAM4E) - PMC->PMC_SCER = PMC_SCER_UDP; -# else - PMC->PMC_SCER = PMC_SCER_UOTGCLK; -# endif -} - -/** - * \brief Disable UDP (USB) clock. - */ -void pmc_disable_udpck(void) -{ -# if (SAM3S || SAM4S || SAM4E) - PMC->PMC_SCDR = PMC_SCDR_UDP; -# else - PMC->PMC_SCDR = PMC_SCDR_UOTGCLK; -# endif -} -#endif - -/** - * \brief Enable PMC interrupts. - * - * \param ul_sources Interrupt sources bit map. - */ -void pmc_enable_interrupt(uint32_t ul_sources) -{ - PMC->PMC_IER = ul_sources; -} - -/** - * \brief Disable PMC interrupts. - * - * \param ul_sources Interrupt sources bit map. - */ -void pmc_disable_interrupt(uint32_t ul_sources) -{ - PMC->PMC_IDR = ul_sources; -} - -/** - * \brief Get PMC interrupt mask. - * - * \return The interrupt mask value. - */ -uint32_t pmc_get_interrupt_mask(void) -{ - return PMC->PMC_IMR; -} - -/** - * \brief Get current status. - * - * \return The current PMC status. - */ -uint32_t pmc_get_status(void) -{ - return PMC->PMC_SR; -} - -/** - * \brief Set the wake-up inputs for fast startup mode registers - * (event generation). - * - * \param ul_inputs Wake up inputs to enable. - */ -void pmc_set_fast_startup_input(uint32_t ul_inputs) -{ - ul_inputs &= PMC_FAST_STARTUP_Msk; - PMC->PMC_FSMR |= ul_inputs; -} - -/** - * \brief Clear the wake-up inputs for fast startup mode registers - * (remove event generation). - * - * \param ul_inputs Wake up inputs to disable. - */ -void pmc_clr_fast_startup_input(uint32_t ul_inputs) -{ - ul_inputs &= PMC_FAST_STARTUP_Msk; - PMC->PMC_FSMR &= ~ul_inputs; -} - -/** - * \brief Enable Sleep Mode. - * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0) - * - * \param uc_type 0 for wait for interrupt, 1 for wait for event. - * \note For SAM4S and SAM4E series, since only WFI is effective, uc_type = 1 - * will be treated as uc_type = 0. - */ -void pmc_enable_sleepmode(uint8_t uc_type) -{ -#if !defined(SAM4S) || !defined(SAM4E) || !defined(SAM4N) - PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode -#endif - SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep - -#if (SAM4S || SAM4E || SAM4N) - UNUSED(uc_type); - __WFI(); -#else - if (uc_type == 0) { - __WFI(); - } else { - __WFE(); - } -#endif -} - -#if (SAM4S || SAM4E || SAM4N) -static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN; -/** - * \brief Set the embedded flash state in wait mode - * - * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode, - * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode. - */ -void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state) -{ - ul_flash_in_wait_mode = ul_flash_state; -} - -/** - * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + - * (SLEEPDEEP bit = 0) + FLPM - */ -void pmc_enable_waitmode(void) -{ - uint32_t i; - - /* Flash in Deep Power Down mode */ - i = PMC->PMC_FSMR; - i &= ~PMC_FSMR_FLPM_Msk; - i |= ul_flash_in_wait_mode; - PMC->PMC_FSMR = i; - - /* Clear SLEEPDEEP bit */ - SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; - - /* Backup FWS setting and set Flash Wait State at 0 */ -#if defined(ID_EFC) - uint32_t fmr_backup; - fmr_backup = EFC->EEFC_FMR; - EFC->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk; -#endif -#if defined(ID_EFC0) - uint32_t fmr0_backup; - fmr0_backup = EFC0->EEFC_FMR; - EFC0->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk; -#endif -#if defined(ID_EFC1) - uint32_t fmr1_backup; - fmr1_backup = EFC1->EEFC_FMR; - EFC1->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk; -#endif - - /* Set the WAITMODE bit = 1 */ - PMC->CKGR_MOR |= CKGR_MOR_KEY(0x37u) | CKGR_MOR_WAITMODE; - - /* Waiting for Master Clock Ready MCKRDY = 1 */ - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); - - /* Waiting for MOSCRCEN bit cleared is strongly recommended - * to ensure that the core will not execute undesired instructions - */ - for (i = 0; i < 500; i++) { - __NOP(); - } - while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); - - /* Restore EFC FMR setting */ -#if defined(ID_EFC) - EFC->EEFC_FMR = fmr_backup; -#endif -#if defined(ID_EFC0) - EFC0->EEFC_FMR = fmr0_backup; -#endif -#if defined(ID_EFC1) - EFC1->EEFC_FMR = fmr1_backup; -#endif -} -#else -/** - * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) + - * (LPM bit = 1) - */ -void pmc_enable_waitmode(void) -{ - uint32_t i; - - PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */ - SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */ - __WFE(); - - /* Waiting for MOSCRCEN bit cleared is strongly recommended - * to ensure that the core will not execute undesired instructions - */ - for (i = 0; i < 500; i++) { - __NOP(); - } - while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); -} -#endif - -/** - * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) + - * (SLEEPDEEP bit = 1) - */ -void pmc_enable_backupmode(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -#if (SAM4S || SAM4E || SAM4N) - SUPC->SUPC_CR = SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_VROFF_STOP_VREG; -#else - __WFE(); -#endif -} - -/** - * \brief Enable Clock Failure Detector. - */ -void pmc_enable_clock_failure_detector(void) -{ - uint32_t ul_reg = PMC->CKGR_MOR; - - PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_CFDEN | ul_reg; -} - -/** - * \brief Disable Clock Failure Detector. - */ -void pmc_disable_clock_failure_detector(void) -{ - uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN); - - PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | ul_reg; -} - -#if SAM4N -/** - * \brief Enable Slow Crystal Oscillator Frequency Monitoring. - */ -void pmc_enable_sclk_osc_freq_monitor(void) -{ - uint32_t ul_reg = PMC->CKGR_MOR; - - PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_XT32KFME | ul_reg; -} - -/** - * \brief Disable Slow Crystal Oscillator Frequency Monitoring. - */ -void pmc_disable_sclk_osc_freq_monitor(void) -{ - uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME); - - PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | ul_reg; -} -#endif - -/** - * \brief Enable or disable write protect of PMC registers. - * - * \param ul_enable 1 to enable, 0 to disable. - */ -void pmc_set_writeprotect(uint32_t ul_enable) -{ - if (ul_enable) { - PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE | PMC_WPMR_WPEN; - } else { - PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE; - } -} - -/** - * \brief Return write protect status. - * - * \retval 0 Protection disabled. - * \retval 1 Protection enabled. - */ -uint32_t pmc_get_writeprotect_status(void) -{ - return PMC->PMC_WPMR & PMC_WPMR_WPEN; -} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/pmc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/pmc.h deleted file mode 100644 index 2d2c34a9e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/pmc.h +++ /dev/null @@ -1,484 +0,0 @@ -/** - * \file - * - * \brief Power Management Controller (PMC) driver for SAM. - * - * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef PMC_H_INCLUDED -#define PMC_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -/** Bit mask for peripheral clocks (PCER0) */ -#define PMC_MASK_STATUS0 (0xFFFFFFFC) - -/** Bit mask for peripheral clocks (PCER1) */ -#define PMC_MASK_STATUS1 (0xFFFFFFFF) - -/** Loop counter timeout value */ -#define PMC_TIMEOUT (2048) - -/** Key to unlock CKGR_MOR register */ -#define PMC_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) - -/** Key used to write SUPC registers */ -#define SUPC_KEY_VALUE ((uint32_t) 0xA5) - -/** Mask to access fast startup input */ -#define PMC_FAST_STARTUP_Msk (0x7FFFFu) - -/** PMC_WPMR Write Protect KEY, unlock it */ -#define PMC_WPMR_WPKEY_VALUE PMC_WPMR_WPKEY((uint32_t) 0x504D43) - -/** Using external oscillator */ -#define PMC_OSC_XTAL 0 - -/** Oscillator in bypass mode */ -#define PMC_OSC_BYPASS 1 - -#define PMC_PCK_0 0 /* PCK0 ID */ -#define PMC_PCK_1 1 /* PCK1 ID */ -#define PMC_PCK_2 2 /* PCK2 ID */ - -#if SAM4S || SAM4E || SAM4N -/** Flash state in Wait Mode */ -#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY -#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN -#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE -#endif - -/** Convert startup time from us to MOSCXTST */ -#define pmc_us_to_moscxtst(startup_us, slowck_freq) \ - ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \ - (startup_us * slowck_freq / 8 / 1000000) : 0xFF) - -/** - * \name Master clock (MCK) Source and Prescaler configuration - * - * \note The following functions may be used to select the clock source and - * prescaler for the master clock. - */ -//@{ - -void pmc_mck_set_prescaler(uint32_t ul_pres); -void pmc_mck_set_source(uint32_t ul_source); -uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres); -uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres); -uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres); -#if (SAM3S || SAM4S) -uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres); -#endif -#if (SAM3XA || SAM3U) -uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres); -#endif -#if (SAM4S || SAM4E || SAM4N) -void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state); -#endif - - -//@} - -/** - * \name Slow clock (SLCK) oscillator and configuration - * - */ -//@{ - -void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass); -uint32_t pmc_osc_is_ready_32kxtal(void); - -//@} - -/** - * \name Main Clock (MAINCK) oscillator and configuration - * - */ -//@{ - -void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf); -void pmc_osc_enable_fastrc(uint32_t ul_rc); -void pmc_osc_disable_fastrc(void); -uint32_t pmc_osc_is_ready_fastrc(void); -void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time); -void pmc_osc_bypass_main_xtal(void); -void pmc_osc_disable_main_xtal(void); -uint32_t pmc_osc_is_bypassed_main_xtal(void); -uint32_t pmc_osc_is_ready_main_xtal(void); -void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, - uint32_t ul_xtal_startup_time); -void pmc_osc_disable_xtal(uint32_t ul_bypass); -uint32_t pmc_osc_is_ready_mainck(void); -void pmc_mainck_osc_select(uint32_t ul_xtal_rc); - -//@} - -/** - * \name PLL oscillator and configuration - * - */ -//@{ - -void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva); -void pmc_disable_pllack(void); -uint32_t pmc_is_locked_pllack(void); - -#if (SAM3S || SAM4S) -void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb); -void pmc_disable_pllbck(void); -uint32_t pmc_is_locked_pllbck(void); -#endif - -#if (SAM3XA || SAM3U) -void pmc_enable_upll_clock(void); -void pmc_disable_upll_clock(void); -uint32_t pmc_is_locked_upll(void); -#endif - -//@} - -/** - * \name Peripherals clock configuration - * - */ -//@{ - -uint32_t pmc_enable_periph_clk(uint32_t ul_id); -uint32_t pmc_disable_periph_clk(uint32_t ul_id); -void pmc_enable_all_periph_clk(void); -void pmc_disable_all_periph_clk(void); -uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id); - -//@} - -/** - * \name Programmable clock Source and Prescaler configuration - * - * The following functions may be used to select the clock source and - * prescaler for the specified programmable clock. - */ -//@{ - -void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres); -void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source); -uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres); -uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres); -uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres); -#if (SAM3S || SAM4S) -uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres); -#endif -#if (SAM3XA || SAM3U) -uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres); -#endif -void pmc_enable_pck(uint32_t ul_id); -void pmc_disable_pck(uint32_t ul_id); -void pmc_enable_all_pck(void); -void pmc_disable_all_pck(void); -uint32_t pmc_is_pck_enabled(uint32_t ul_id); - -//@} - -/** - * \name USB clock configuration - * - */ -//@{ - -#if (SAM3S || SAM3XA || SAM4S || SAM4E) -void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv); -#endif -#if (SAM3S || SAM4S) -void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv); -#endif -#if (SAM3XA) -void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv); -#endif -#if (SAM3S || SAM3XA || SAM4S || SAM4E) -void pmc_enable_udpck(void); -void pmc_disable_udpck(void); -#endif - -//@} - -/** - * \name Interrupt and status management - * - */ -//@{ - -void pmc_enable_interrupt(uint32_t ul_sources); -void pmc_disable_interrupt(uint32_t ul_sources); -uint32_t pmc_get_interrupt_mask(void); -uint32_t pmc_get_status(void); - -//@} - -/** - * \name Power management - * - * The following functions are used to configure sleep mode and additional - * wake up inputs. - */ -//@{ - -void pmc_set_fast_startup_input(uint32_t ul_inputs); -void pmc_clr_fast_startup_input(uint32_t ul_inputs); -void pmc_enable_sleepmode(uint8_t uc_type); -void pmc_enable_waitmode(void); -void pmc_enable_backupmode(void); - -//@} - -/** - * \name Failure detector - * - */ -//@{ - -void pmc_enable_clock_failure_detector(void); -void pmc_disable_clock_failure_detector(void); - -//@} - -#if SAM4N -/** - * \name Slow Crystal Oscillator Frequency Monitoring - * - */ -//@{ - -void pmc_enable_sclk_osc_freq_monitor(void); -void pmc_disable_sclk_osc_freq_monitor(void); - -//@} -#endif - -/** - * \name Write protection - * - */ -//@{ - -void pmc_set_writeprotect(uint32_t ul_enable); -uint32_t pmc_get_writeprotect_status(void); - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -//! @} - -/** - * \page sam_pmc_quickstart Quick start guide for the SAM PMC module - * - * This is the quick start guide for the \ref pmc_group "PMC module", with - * step-by-step instructions on how to configure and use the driver in a - * selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section pmc_use_cases PMC use cases - * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources - * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks - * - * \section pmc_basic_use_case Basic use case - Switch Main Clock sources - * In this use case, the PMC module is configured for a variety of system clock - * sources and speeds. A LED is used to visually indicate the current clock - * speed as the source is switched. - * - * \section pmc_basic_use_case_setup Setup - * - * \subsection pmc_basic_use_case_setup_prereq Prerequisites - * -# \ref gpio_group "General Purpose I/O Management (gpio)" - * - * \subsection pmc_basic_use_case_setup_code Code - * The following function needs to be added to the user application, to flash a - * board LED a variable number of times at a rate given in CPU ticks. - * - * \code - * #define FLASH_TICK_COUNT 0x00012345 - * - * void flash_led(uint32_t tick_count, uint8_t flash_count) - * { - * SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; - * SysTick->LOAD = tick_count; - * - * while (flash_count--) - * { - * gpio_toggle_pin(LED0_GPIO); - * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); - * gpio_toggle_pin(LED0_GPIO); - * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); - * } - * } - * \endcode - * - * \section pmc_basic_use_case_usage Use case - * - * \subsection pmc_basic_use_case_usage_code Example code - * Add to application C-file: - * \code - * for (;;) - * { - * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); - * flash_led(FLASH_TICK_COUNT, 5); - * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); - * flash_led(FLASH_TICK_COUNT, 5); - * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); - * flash_led(FLASH_TICK_COUNT, 5); - * pmc_switch_mainck_to_xtal(0); - * flash_led(FLASH_TICK_COUNT, 5); - * } - * \endcode - * - * \subsection pmc_basic_use_case_usage_flow Workflow - * -# Wrap the code in an infinite loop: - * \code - * for (;;) - * \endcode - * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash - * a LED on the board several times: - * \code - * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); - * flash_led(FLASH_TICK_COUNT, 5); - * \endcode - * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash - * a LED on the board several times: - * \code - * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); - * flash_led(FLASH_TICK_COUNT, 5); - * \endcode - * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash - * a LED on the board several times: - * \code - * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); - * flash_led(FLASH_TICK_COUNT, 5); - * \endcode - * -# Switch the Master CPU frequency to the external crystal oscillator, flash - * a LED on the board several times: - * \code - * pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US); - * flash_led(FLASH_TICK_COUNT, 5); - * \endcode - */ - -/** - * \page pmc_use_case_2 Use case #2 - Configure Programmable Clocks - * In this use case, the PMC module is configured to start the Slow Clock from - * an attached 32KHz crystal, and start one of the Programmable Clock modules - * sourced from the Slow Clock divided down with a prescale factor of 64. - * - * \section pmc_use_case_2_setup Setup - * - * \subsection pmc_use_case_2_setup_prereq Prerequisites - * -# \ref pio_group "Parallel Input/Output Controller (pio)" - * - * \subsection pmc_use_case_2_setup_code Code - * The following code must be added to the user application: - * \code - * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); - * \endcode - * - * \subsection pmc_use_case_2_setup_code_workflow Workflow - * -# Configure the PCK1 pin to output on a specific port pin (in this case, - * PIOA pin 17) of the microcontroller. - * \code - * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); - * \endcode - * \note The peripheral selection and pin will vary according to your selected - * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O - * Lines" of your device's datasheet. - * - * \section pmc_use_case_2_usage Use case - * The generated PCK1 clock output can be viewed on an oscilloscope attached to - * the correct pin of the microcontroller. - * - * \subsection pmc_use_case_2_usage_code Example code - * Add to application C-file: - * \code - * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); - * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); - * pmc_enable_pck(PMC_PCK_1); - * - * for (;;) - * { - * // Do Nothing - * } - * \endcode - * - * \subsection pmc_use_case_2_usage_flow Workflow - * -# Switch the Slow Clock source input to an external 32KHz crystal: - * \code - * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); - * \endcode - * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock, - * with a prescaler of 64: - * \code - * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); - * \endcode - * -# Enable Programmable Clock module PCK1: - * \code - * pmc_enable_pck(PMC_PCK_1); - * \endcode - * -# Enter an infinite loop: - * \code - * for (;;) - * { - * // Do Nothing - * } - * \endcode - */ - -#endif /* PMC_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/sleep.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/sleep.c deleted file mode 100644 index 23985453c..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/sleep.c +++ /dev/null @@ -1,251 +0,0 @@ -/** - * \file - * - * \brief Sleep mode access - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include "sleep.h" - -/* SAM3 and SAM4 series */ -#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N) -# include "pmc.h" -# include "board.h" - -/* Checking board configuration of main clock xtal statup time */ -#if !defined(BOARD_OSC_STARTUP_US) -# warning The board main clock xtal statup time has not been defined. Using default settings. -# define BOARD_OSC_STARTUP_US (15625UL) -#endif - -/** - * Save clock settings and shutdown PLLs - */ -__always_inline static void pmc_save_clock_settings( - uint32_t *p_osc_setting, - uint32_t *p_pll0_setting, - uint32_t *p_pll1_setting, - uint32_t *p_mck_setting) -{ - if (p_osc_setting) { - *p_osc_setting = PMC->CKGR_MOR; - } - if (p_pll0_setting) { - *p_pll0_setting = PMC->CKGR_PLLAR; - } - if (p_pll1_setting) { -#if (SAM3S || SAM4S) - *p_pll1_setting = PMC->CKGR_PLLBR; -#elif (SAM3U || SAM3XA) - *p_pll1_setting = PMC->CKGR_UCKR; -#else - *p_pll1_setting = 0; -#endif - } - if (p_mck_setting) { - *p_mck_setting = PMC->PMC_MCKR; - } - - /* Switch MCK to internal 4/8/12M RC for fast wakeup - and disable unused clock for power saving. */ - pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); - pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); - pmc_osc_disable_xtal(0); - pmc_disable_pllack(); -#if (SAM3S || SAM4S) - pmc_disable_pllbck(); -#elif (SAM3U || SAM3XA) - pmc_disable_upll_clock(); -#endif - pmc_switch_mck_to_mainck(PMC_MCKR_PRES_CLK_1); -} - -/** - * Restore clock settings - */ -__always_inline static void pmc_restore_clock_setting( - uint32_t osc_setting, - uint32_t pll0_setting, - uint32_t pll1_setting, - uint32_t mck_setting) -{ - uint32_t mckr; - uint32_t pll_sr = 0; - - /* Switch MCK to slow clock */ - pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); - /* Switch mainck to external xtal */ - if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) { - /* Bypass mode */ - pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS, - pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, - CHIP_FREQ_SLCK_RC)); - pmc_osc_disable_fastrc(); - } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) { - /* External XTAL */ - pmc_switch_mainck_to_xtal(PMC_OSC_XTAL, - pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, - CHIP_FREQ_SLCK_RC)); - pmc_osc_disable_fastrc(); - } - - if (pll0_setting & CKGR_PLLAR_MULA_Msk) { - PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting; - pll_sr |= PMC_SR_LOCKA; - } -#if (SAM3S || SAM4S) - if (pll1_setting & CKGR_PLLBR_MULB_Msk) { - PMC->CKGR_PLLBR = pll1_setting; - pll_sr |= PMC_SR_LOCKB; - } -#elif (SAM3U || SAM3XA) - if (pll1_setting & CKGR_UCKR_UPLLEN) { - PMC->CKGR_UCKR = pll1_setting; - pll_sr |= PMC_SR_LOCKU; - } -#else - UNUSED(pll1_setting); -#endif - /* Wait MCK source ready */ - switch(mck_setting & PMC_MCKR_CSS_Msk) { - case PMC_MCKR_CSS_PLLA_CLK: - while (!(PMC->PMC_SR & PMC_SR_LOCKA)); - break; -#if (SAM3S || SAM4S) - case PMC_MCKR_CSS_PLLB_CLK: - while (!(PMC->PMC_SR & PMC_SR_LOCKB)); - break; -#elif (SAM3U || SAM3XA) - case PMC_MCKR_CSS_UPLL_CLK: - while (!(PMC->PMC_SR & PMC_SR_LOCKU)); - break; -#endif - } - - /* Switch to faster clock */ - mckr = PMC->PMC_MCKR; - /* Set PRES */ - PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk) - | (mck_setting & PMC_MCKR_PRES_Msk); - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); - /* Set CSS and others */ - PMC->PMC_MCKR = mck_setting; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); - /* Waiting all restored PLLs ready */ - while (!(PMC->PMC_SR & pll_sr)); -} - -/** If clocks are switched to FASTRC for WAIT mode */ -static volatile bool b_is_fastrc_used = false; -/** Callback invoked once when clocks are restored */ -static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL; - -void pmc_sleep(int sleep_mode) -{ - switch (sleep_mode) { - case SAM_PM_SMODE_SLEEP_WFI: - case SAM_PM_SMODE_SLEEP_WFE: -#if (SAM4S || SAM4E || SAM4N) - SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; - cpu_irq_enable(); - __WFI(); - break; -#else - PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM; - SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; - cpu_irq_enable(); - if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI) - __WFI(); - else - __WFE(); - break; -#endif - case SAM_PM_SMODE_WAIT: { - uint32_t mor, pllr0, pllr1, mckr; - cpu_irq_disable(); - b_is_fastrc_used = true; - pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr); - - /* Enter wait mode */ - cpu_irq_enable(); - pmc_enable_waitmode(); - - cpu_irq_disable(); - pmc_restore_clock_setting(mor, pllr0, pllr1, mckr); - b_is_fastrc_used = false; - if (callback_clocks_restored) { - callback_clocks_restored(); - callback_clocks_restored = NULL; - } - cpu_irq_enable(); - break; - } - - case SAM_PM_SMODE_BACKUP: - SCB->SCR |= SCR_SLEEPDEEP; -#if (SAM4S || SAM4E || SAM4N) - SUPC->SUPC_CR = SUPC_CR_KEY(0xA5u) | SUPC_CR_VROFF_STOP_VREG; - cpu_irq_enable(); - __WFI() ; -#else - cpu_irq_enable(); - __WFE() ; -#endif - break; - } -} - -bool pmc_is_wakeup_clocks_restored(void) -{ - return !b_is_fastrc_used; -} - -void pmc_wait_wakeup_clocks_restore( - pmc_callback_wakeup_clocks_restored_t callback) -{ - if (b_is_fastrc_used) { - cpu_irq_disable(); - callback_clocks_restored = callback; - } else if (callback) { - callback(); - } -} - -#endif /* #if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N) */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/sleep.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/sleep.h deleted file mode 100644 index cbfad6bfe..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/pmc/sleep.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - * \file - * - * \brief Sleep mode access - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef SLEEP_H -#define SLEEP_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * \defgroup sleep_group Power Manager (PM) - * - * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr - * service. - * - * \note To minimize the code overhead, these functions do not feature - * interrupt-protected access since they are likely to be called inside - * interrupt handlers or in applications where such protection is not - * necessary. If such protection is needed, it must be ensured by the calling - * code. - * - * @{ - */ - -#if defined(__DOXYGEN__) -/** - * \brief Sets the MCU in the specified sleep mode - * \param sleep_mode Sleep mode to set. - */ -#endif -/* SAM3 and SAM4 series */ -#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N) - -# define SAM_PM_SMODE_ACTIVE 0 /**< Active */ -# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */ -# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */ -# define SAM_PM_SMODE_WAIT 3 /**< Wait Mode */ -# define SAM_PM_SMODE_BACKUP 4 /**< Backup Mode */ - -/** (SCR) Sleep deep bit */ -#define SCR_SLEEPDEEP (0x1 << 2) - -/** - * Clocks restored callback function type. - * Registered by routine pmc_wait_wakeup_clocks_restore() - * Callback called when all clocks are restored. - */ -typedef void (*pmc_callback_wakeup_clocks_restored_t) (void); - -/** - * Enter sleep mode - * \param sleep_mode Sleep mode to enter - */ -void pmc_sleep(int sleep_mode); - -/** - * Check if clocks are restored after wakeup - * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC. - * After wakeup clocks should be restored, before that some of the - * ISR should not be served, otherwise there may be timing or clock issue.) - */ -bool pmc_is_wakeup_clocks_restored(void); - -/** - * - * \return true if start waiting - */ -void pmc_wait_wakeup_clocks_restore( - pmc_callback_wakeup_clocks_restored_t callback); - -#endif - -//! @} - -#ifdef __cplusplus -} -#endif - -#endif /* SLEEP_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/tc/tc.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/tc/tc.c deleted file mode 100644 index dd95a52ea..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/tc/tc.c +++ /dev/null @@ -1,596 +0,0 @@ -/** - * \file - * - * \brief Timer Counter (TC) driver for SAM. - * - * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include "tc.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -#define TC_WPMR_WPKEY_VALUE TC_WPMR_WPKEY((uint32_t)0x54494D) - -/** - * \defgroup sam_drivers_tc_group Timer Counter (TC) - * - * The Timer Counter (TC) includes three identical 32-bit Timer Counter - * channels. Each channel can be independently programmed to perform a wide - * range of functions including frequency measurement, event counting, - * interval measurement, pulse generation, delay timing and pulse width - * modulation. - * - * @{ - */ - -/** - * \brief Configure TC for timer, waveform generation or capture. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * \param ul_mode Control mode register value to set. - * - * \attention If the TC is configured for waveform generation, the external - * event selection (EEVT) should only be set to \c TC_CMR_EEVT_TIOB or the - * equivalent value \c 0 if it really is the intention to use TIOB as an - * external event trigger.\n - * This is because the setting forces TIOB to be an input even if the - * external event trigger has not been enabled with \c TC_CMR_ENETRG, and - * thus prevents normal operation of TIOB. - */ -void tc_init(Tc *p_tc, uint32_t ul_channel, uint32_t ul_mode) -{ - TcChannel *tc_channel; - - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - - /* Disable TC clock. */ - tc_channel->TC_CCR = TC_CCR_CLKDIS; - - /* Disable interrupts. */ - tc_channel->TC_IDR = 0xFFFFFFFF; - - /* Clear status register. */ - tc_channel->TC_SR; - - /* Set mode. */ - tc_channel->TC_CMR = ul_mode; -} - -/** - * \brief Asserts a SYNC signal to generate a software trigger to - * all channels. - * - * \param p_tc Pointer to a TC instance. - * - */ -void tc_sync_trigger(Tc *p_tc) -{ - p_tc->TC_BCR = TC_BCR_SYNC; -} - -/** - * \brief Configure TC Block mode. - * \note tc_init() must be called first. - * - * \param p_tc Pointer to a TC instance. - * \param ul_blockmode Block mode register value to set. - * - */ -void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode) -{ - p_tc->TC_BMR = ul_blockmode; -} - -#if (!SAM3U) - -/** - * \brief Configure TC for 2-bit Gray Counter for Stepper Motor. - * \note tc_init() must be called first. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * \param ul_steppermode Stepper motor mode register value to set. - * - * \return 0 for OK. - */ -uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_steppermode) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_SMMR = ul_steppermode; - return 0; -} - -#endif - -/** - * \brief Start TC clock counter on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - */ -void tc_start(Tc *p_tc, uint32_t ul_channel) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG; -} - -/** - * \brief Stop TC clock counter on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - */ -void tc_stop(Tc *p_tc, uint32_t ul_channel) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKDIS; -} - -/** - * \brief Read counter value on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * - * \return Counter value. - */ -uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - return p_tc->TC_CHANNEL[ul_channel].TC_CV; -} - -/** - * \brief Read RA TC counter on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * - * \return RA value. - */ -uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - return p_tc->TC_CHANNEL[ul_channel].TC_RA; -} - -/** - * \brief Read RB TC counter on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * - * \return RB value. - */ -uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - return p_tc->TC_CHANNEL[ul_channel].TC_RB; -} - -/** - * \brief Read RC TC counter on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * - * \return RC value. - */ -uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - return p_tc->TC_CHANNEL[ul_channel].TC_RC; -} - -/** - * \brief Write RA TC counter on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * \param ul_value Value to set in register. - */ -void tc_write_ra(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_RA = ul_value; -} - -/** - * \brief Write RB TC counter on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * \param ul_value Value to set in register. - */ -void tc_write_rb(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_RB = ul_value; -} - -/** - * \brief Write RC TC counter on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * \param ul_value Value to set in register. - */ -void tc_write_rc(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value) -{ - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - - p_tc->TC_CHANNEL[ul_channel].TC_RC = ul_value; -} - -/** - * \brief Enable TC interrupts on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * \param ul_sources Interrupt sources bit map. - */ -void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_sources) -{ - TcChannel *tc_channel; - - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - tc_channel->TC_IER = ul_sources; -} - -/** - * \brief Disable TC interrupts on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * \param ul_sources Interrupt sources bit map. - */ -void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_sources) -{ - TcChannel *tc_channel; - - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - tc_channel->TC_IDR = ul_sources; -} - -/** - * \brief Read TC interrupt mask on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * - * \return The interrupt mask value. - */ -uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel) -{ - TcChannel *tc_channel; - - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - return tc_channel->TC_IMR; -} - -/** - * \brief Get current status on the selected channel. - * - * \param p_tc Pointer to a TC instance. - * \param ul_channel Channel to configure. - * - * \return The current TC status. - */ -uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel) -{ - TcChannel *tc_channel; - - Assert(ul_channel < - (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); - tc_channel = p_tc->TC_CHANNEL + ul_channel; - return tc_channel->TC_SR; -} - -/* TC divisor used to find the lowest acceptable timer frequency */ -#define TC_DIV_FACTOR 65536 - -#if (!SAM4L) - -#ifndef FREQ_SLOW_CLOCK_EXT -#define FREQ_SLOW_CLOCK_EXT 32768 /* External slow clock frequency (hz) */ -#endif - -/** - * \brief Find the best MCK divisor. - * - * Finds the best MCK divisor given the timer frequency and MCK. The result - * is guaranteed to satisfy the following equation: - * \code - * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) - * \endcode - * with DIV being the lowest possible value, - * to maximize timing adjust resolution. - * - * \param ul_freq Desired timer frequency. - * \param ul_mck Master clock frequency. - * \param p_uldiv Divisor value. - * \param p_ultcclks TCCLKS field value for divisor. - * \param ul_boardmck Board clock frequency. - * - * \return 1 if a proper divisor has been found, otherwise 0. - */ -uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, - uint32_t *p_uldiv, uint32_t *p_ultcclks, uint32_t ul_boardmck) -{ - const uint32_t divisors[5] = { 2, 8, 32, 128, - ul_boardmck / FREQ_SLOW_CLOCK_EXT }; - uint32_t ul_index; - uint32_t ul_high, ul_low; - - /* Satisfy frequency bound. */ - for (ul_index = 0; - ul_index < (sizeof(divisors) / sizeof(divisors[0])); - ul_index++) { - ul_high = ul_mck / divisors[ul_index]; - ul_low = ul_high / TC_DIV_FACTOR; - if (ul_freq > ul_high) { - return 0; - } else if (ul_freq >= ul_low) { - break; - } - } - if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) { - return 0; - } - - /* Store results. */ - if (p_uldiv) { - *p_uldiv = divisors[ul_index]; - } - - if (p_ultcclks) { - *p_ultcclks = ul_index; - } - - return 1; -} - -#endif - -#if (SAM4L) -/** - * \brief Find the best PBA clock divisor. - * - * Finds the best divisor given the timer frequency and PBA clock. The result - * is guaranteed to satisfy the following equation: - * \code - * (ul_pbaclk / (2* DIV * 65536)) <= freq <= (ul_pbaclk / (2* DIV)) - * \endcode - * with DIV being the lowest possible value, - * to maximize timing adjust resolution. - * - * \param ul_freq Desired timer frequency. - * \param ul_mck PBA clock frequency. - * \param p_uldiv Divisor value. - * \param p_ultcclks TCCLKS field value for divisor. - * \param ul_boardmck useless here. - * - * \return 1 if a proper divisor has been found, otherwise 0. - */ -uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, - uint32_t *p_uldiv, uint32_t *p_ultcclks, uint32_t ul_boardmck) -{ - const uint32_t divisors[5] = { 0, 2, 8, 32, 128}; - uint32_t ul_index; - uint32_t ul_high, ul_low; - - UNUSED(ul_boardmck); - - /* Satisfy frequency bound. */ - for (ul_index = 1; - ul_index < (sizeof(divisors) / sizeof(divisors[0])); - ul_index++) { - ul_high = ul_mck / divisors[ul_index]; - ul_low = ul_high / TC_DIV_FACTOR; - if (ul_freq > ul_high) { - return 0; - } else if (ul_freq >= ul_low) { - break; - } - } - if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) { - return 0; - } - - /* Store results. */ - if (p_uldiv) { - *p_uldiv = divisors[ul_index]; - } - - if (p_ultcclks) { - *p_ultcclks = ul_index; - } - - return 1; -} - -#endif - -#if (!SAM4L) - -/** - * \brief Enable TC QDEC interrupts. - * - * \param p_tc Pointer to a TC instance. - * \param ul_sources Interrupts to be enabled. - */ -void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources) -{ - p_tc->TC_QIER = ul_sources; -} - -/** - * \brief Disable TC QDEC interrupts. - * - * \param p_tc Pointer to a TC instance. - * \param ul_sources Interrupts to be disabled. - */ -void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources) -{ - p_tc->TC_QIDR = ul_sources; -} - -/** - * \brief Read TC QDEC interrupt mask. - * - * \param p_tc Pointer to a TC instance. - * - * \return The interrupt mask value. - */ -uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc) -{ - return p_tc->TC_QIMR; -} - -/** - * \brief Get current QDEC status. - * - * \param p_tc Pointer to a TC instance. - * - * \return The current TC status. - */ -uint32_t tc_get_qdec_interrupt_status(Tc *p_tc) -{ - return p_tc->TC_QISR; -} - -#endif - -#if (!SAM3U) - -/** - * \brief Enable or disable write protection of TC registers. - * - * \param p_tc Pointer to a TC instance. - * \param ul_enable 1 to enable, 0 to disable. - */ -void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable) -{ - if (ul_enable) { - p_tc->TC_WPMR = TC_WPMR_WPKEY_VALUE | TC_WPMR_WPEN; - } else { - p_tc->TC_WPMR = TC_WPMR_WPKEY_VALUE; - } -} - -#endif - -#if SAM4L - -/** - * \brief Indicate features. - * - * \param p_tc Pointer to a TC instance. - * - * \return TC_FEATURES value. - */ -uint32_t tc_get_feature(Tc *p_tc) -{ - return p_tc->TC_FEATURES; -} - -/** - * \brief Indicate version. - * - * \param p_tc Pointer to a TC instance. - * - * \return TC_VERSION value. - */ -uint32_t tc_get_version(Tc *p_tc) -{ - return p_tc->TC_VERSION; -} - -#endif - -//@} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/tc/tc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/tc/tc.h deleted file mode 100644 index 5dd169019..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/tc/tc.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * \brief Timer Counter (TC) driver for SAM. - * - * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef TC_H_INCLUDED -#define TC_H_INCLUDED - -#include "compiler.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -void tc_init(Tc *p_tc, uint32_t ul_Channel, uint32_t ul_Mode); -void tc_sync_trigger(Tc *p_tc); -void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode); - -#if (!SAM3U) -uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_steppermode); -#endif - -void tc_start(Tc *p_tc, uint32_t ul_channel); -void tc_stop(Tc *p_tc, uint32_t ul_channel); - -uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel); -uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel); -uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel); -uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel); - -void tc_write_ra(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value); -void tc_write_rb(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value); -void tc_write_rc(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_value); - -uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, - uint32_t *p_uldiv, uint32_t *ul_tcclks, uint32_t ul_boardmck); -void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_sources); -void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, - uint32_t ul_sources); -uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel); -uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel); -#if (!SAM4L) -void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources); -void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources); -uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc); -uint32_t tc_get_qdec_interrupt_status(Tc *p_tc); -#endif - -#if (!SAM3U) -void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable); -#endif - -#if SAM4L -uint32_t tc_get_feature(Tc *p_tc); -uint32_t tc_get_version(Tc *p_tc); - -#endif - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* TC_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/acc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/acc.h deleted file mode 100644 index c6b3a47db..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/acc.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_ACC_COMPONENT_ -#define _SAM4E_ACC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_ACC Analog Comparator Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Acc hardware registers */ -typedef struct { - WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ - RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ - RoReg Reserved1[7]; - WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ - WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ - RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ - RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ - RoReg Reserved2[24]; - RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ - RoReg Reserved3[19]; - RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ - RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ -} Acc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ -#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ -/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ -#define ACC_MR_SELMINUS_Pos 0 -#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */ -#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */ -#define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */ -#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ -#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ -#define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */ -#define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */ -#define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */ -#define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */ -#define ACC_MR_SELPLUS_Pos 4 -#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */ -#define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */ -#define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */ -#define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */ -#define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */ -#define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */ -#define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */ -#define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */ -#define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */ -#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */ -#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */ -#define ACC_MR_EDGETYP_Pos 9 -#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */ -#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */ -#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */ -#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */ -#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */ -#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */ -#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */ -#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */ -#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */ -#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */ -/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ -#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ -/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ -#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ -/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ -/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ -#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */ -#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ -#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) */ -/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ -#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */ -#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */ -#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */ -#define ACC_ACR_HYST_Pos 1 -#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */ -#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) -/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ -#define ACC_WPMR_WPKEY_Pos 8 -#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */ -#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) -/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ -#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ - -/*@}*/ - - -#endif /* _SAM4E_ACC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/aes.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/aes.h deleted file mode 100644 index 7b7856374..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/aes.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_AES_COMPONENT_ -#define _SAM4E_AES_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ -/* ============================================================================= */ -/** \addtogroup SAM4E_AES Advanced Encryption Standard */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Aes hardware registers */ -typedef struct { - WoReg AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ - RwReg AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ - RoReg Reserved1[2]; - WoReg AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ - WoReg AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ - RoReg AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ - RoReg AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ - WoReg AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ - WoReg AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ - RoReg AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ - WoReg AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ -#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ -#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ -/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ -#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ -#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input BUFFer */ -#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ -#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */ -#define AES_MR_PROCDLY_Pos 4 -#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ -#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) -#define AES_MR_SMOD_Pos 8 -#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ -#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ -#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ -#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode */ -#define AES_MR_KEYSIZE_Pos 10 -#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ -#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ -#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ -#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ -#define AES_MR_OPMOD_Pos 12 -#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ -#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ -#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ -#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ -#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ -#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ -#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ -#define AES_MR_CFBS_Pos 16 -#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ -#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ -#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ -#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ -#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ -#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ -#define AES_MR_CKEY_Pos 20 -#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */ -#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) -/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ -#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ -#define AES_IER_ENDRX (0x1u << 1) /**< \brief (AES_IER) End of Receive Buffer Interrupt Enable */ -#define AES_IER_ENDTX (0x1u << 2) /**< \brief (AES_IER) End of Transmit Buffer Interrupt Enable */ -#define AES_IER_RXBUFF (0x1u << 3) /**< \brief (AES_IER) Receive Buffer Full Interrupt Enable */ -#define AES_IER_TXBUFE (0x1u << 4) /**< \brief (AES_IER) Transmit Buffer Empty Interrupt Enable */ -#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ -/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ -#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ -#define AES_IDR_ENDRX (0x1u << 1) /**< \brief (AES_IDR) End of Receive Buffer Interrupt Disable */ -#define AES_IDR_ENDTX (0x1u << 2) /**< \brief (AES_IDR) End of Transmit Buffer Interrupt Disable */ -#define AES_IDR_RXBUFF (0x1u << 3) /**< \brief (AES_IDR) Receive Buffer Full Interrupt Disable */ -#define AES_IDR_TXBUFE (0x1u << 4) /**< \brief (AES_IDR) Transmit Buffer Empty Interrupt Disable */ -#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ -/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ -#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ -#define AES_IMR_ENDRX (0x1u << 1) /**< \brief (AES_IMR) End of Receive Buffer Interrupt Mask */ -#define AES_IMR_ENDTX (0x1u << 2) /**< \brief (AES_IMR) End of Transmit Buffer Interrupt Mask */ -#define AES_IMR_RXBUFF (0x1u << 3) /**< \brief (AES_IMR) Receive Buffer Full Interrupt Mask */ -#define AES_IMR_TXBUFE (0x1u << 4) /**< \brief (AES_IMR) Transmit Buffer Empty Interrupt Mask */ -#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ -/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ -#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready */ -#define AES_ISR_ENDRX (0x1u << 1) /**< \brief (AES_ISR) End of RX Buffer */ -#define AES_ISR_ENDTX (0x1u << 2) /**< \brief (AES_ISR) End of TX Buffer */ -#define AES_ISR_RXBUFF (0x1u << 3) /**< \brief (AES_ISR) RX Buffer Full */ -#define AES_ISR_TXBUFE (0x1u << 4) /**< \brief (AES_ISR) TX Buffer Empty */ -#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status */ -#define AES_ISR_URAT_Pos 12 -#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access: */ -#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD=0x2 mode. */ -#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ -#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ -#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ -#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ -#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ -/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ -#define AES_KEYWR_KEYW_Pos 0 -#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ -#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) -/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ -#define AES_IDATAR_IDATA_Pos 0 -#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ -#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) -/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ -#define AES_ODATAR_ODATA_Pos 0 -#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ -/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ -#define AES_IVR_IV_Pos 0 -#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ -#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) - -/*@}*/ - - -#endif /* _SAM4E_AES_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/afec.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/afec.h deleted file mode 100644 index 24e2a90ee..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/afec.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_AFEC_COMPONENT_ -#define _SAM4E_AFEC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-Front-End Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_AFEC Analog-Front-End Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Afec hardware registers */ -typedef struct { - WoReg AFEC_CR; /**< \brief (Afec Offset: 0x00) Control Register */ - RwReg AFEC_MR; /**< \brief (Afec Offset: 0x04) Mode Register */ - RwReg AFEC_EMR; /**< \brief (Afec Offset: 0x08) Extended Mode Register */ - RwReg AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) Channel Sequence 1 Register */ - RwReg AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) Channel Sequence 2 Register */ - WoReg AFEC_CHER; /**< \brief (Afec Offset: 0x14) Channel Enable Register */ - WoReg AFEC_CHDR; /**< \brief (Afec Offset: 0x18) Channel Disable Register */ - RoReg AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) Channel Status Register */ - RoReg AFEC_LCDR; /**< \brief (Afec Offset: 0x20) Last Converted Data Register */ - WoReg AFEC_IER; /**< \brief (Afec Offset: 0x24) Interrupt Enable Register */ - WoReg AFEC_IDR; /**< \brief (Afec Offset: 0x28) Interrupt Disable Register */ - RoReg AFEC_IMR; /**< \brief (Afec Offset: 0x2C) Interrupt Mask Register */ - RoReg AFEC_ISR; /**< \brief (Afec Offset: 0x30) Interrupt Status Register */ - RoReg Reserved1[6]; - RoReg AFEC_OVER; /**< \brief (Afec Offset: 0x4C) Overrun Status Register */ - RwReg AFEC_CWR; /**< \brief (Afec Offset: 0x50) Compare Window Register */ - RwReg AFEC_CGR; /**< \brief (Afec Offset: 0x54) Channel Gain Register */ - RoReg Reserved2[1]; - RwReg AFEC_CDOR; /**< \brief (Afec Offset: 0x5C) Channel Calibration DC Offset Register */ - RwReg AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) Channel Differential Register */ - RwReg AFEC_CSELR; /**< \brief (Afec Offset: 0x64) Channel Register Selection */ - RoReg AFEC_CDR; /**< \brief (Afec Offset: 0x68) Channel Data Register */ - RwReg AFEC_COCR; /**< \brief (Afec Offset: 0x6C) Channel Offset Compensation Register */ - RwReg AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) Temperature Sensor Mode Register */ - RwReg AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) Temperature Compare Window Register */ - RoReg Reserved3[7]; - RwReg AFEC_ACR; /**< \brief (Afec Offset: 0x94) Analog Control Register */ - RoReg Reserved4[19]; - RwReg AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) Write Protect Mode Register */ - RoReg AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) Write Protect Status Register */ - RoReg Reserved5[5]; - RwReg AFEC_RPR; /**< \brief (Afec Offset: 0x100) Receive Pointer Register */ - RwReg AFEC_RCR; /**< \brief (Afec Offset: 0x104) Receive Counter Register */ - RoReg Reserved6[2]; - RwReg AFEC_RNPR; /**< \brief (Afec Offset: 0x110) Receive Next Pointer Register */ - RwReg AFEC_RNCR; /**< \brief (Afec Offset: 0x114) Receive Next Counter Register */ - RoReg Reserved7[2]; - WoReg AFEC_PTCR; /**< \brief (Afec Offset: 0x120) Transfer Control Register */ - RoReg AFEC_PTSR; /**< \brief (Afec Offset: 0x124) Transfer Status Register */ -} Afec; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- AFEC_CR : (AFEC Offset: 0x00) Control Register -------- */ -#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ -#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ -#define AFEC_CR_AUTOCAL (0x1u << 3) /**< \brief (AFEC_CR) Automatic Calibration of AFEC */ -/* -------- AFEC_MR : (AFEC Offset: 0x04) Mode Register -------- */ -#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ -#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ -#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ -#define AFEC_MR_TRGSEL_Pos 1 -#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ -#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) ADTRG pin */ -#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 0 */ -#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 1 */ -#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 2 */ -#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM Event Line 0 */ -#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM Event Line 1 */ -#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ -#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal Mode: The AFEC Core and reference voltage circuitry are kept ON between conversions */ -#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode: The AFEC Core and reference voltage circuitry are OFF between conversions */ -#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake Up */ -#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */ -#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and AFEC Core is OFF */ -#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ -#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal Mode */ -#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode: Never wait for any trigger. */ -#define AFEC_MR_PRESCAL_Pos 8 -#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ -#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) -#define AFEC_MR_STARTUP_Pos 16 -#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start Up Time */ -#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFEClock */ -#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFEClock */ -#define AFEC_MR_SETTLING_Pos 20 -#define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) /**< \brief (AFEC_MR) Analog Settling Time */ -#define AFEC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (AFEC_MR) 3 periods of AFEClock */ -#define AFEC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (AFEC_MR) 5 periods of AFEClock */ -#define AFEC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (AFEC_MR) 9 periods of AFEClock */ -#define AFEC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (AFEC_MR) 17 periods of AFEClock */ -#define AFEC_MR_ANACH (0x1u << 23) /**< \brief (AFEC_MR) Analog Change */ -#define AFEC_MR_ANACH_NONE (0x0u << 23) /**< \brief (AFEC_MR) No analog change on channel switching: DIFF0, GAIN0 are used for all channels */ -#define AFEC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (AFEC_MR) Allows different analog settings for each channel. See AFEC_CGR Register. */ -#define AFEC_MR_TRACKTIM_Pos 24 -#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ -#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) -#define AFEC_MR_TRANSFER_Pos 28 -#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ -#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) -#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) Use Sequence Enable */ -#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal Mode: The controller converts channels in a simple numeric order. */ -#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Mode: The sequence respects what is defined in AFEC_SEQR1 and AFEC_SEQR2 registers. */ -/* -------- AFEC_EMR : (AFEC Offset: 0x08) Extended Mode Register -------- */ -#define AFEC_EMR_CMPMODE_Pos 0 -#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ -#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ -#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ -#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ -#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ -#define AFEC_EMR_CMPSEL_Pos 3 -#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ -#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) -#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ -#define AFEC_EMR_CMPFILTER_Pos 12 -#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ -#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) -#define AFEC_EMR_RES_Pos 16 -#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ -#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFEC sample rate is maximum (no averaging). */ -#define AFEC_EMR_RES_LOW_RES (0x1u << 16) /**< \brief (AFEC_EMR) 10-bit resolution, AFEC sample rate is maximum (no averaging). */ -#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFEC sample rate divided by 4 (averaging). */ -#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFEC sample rate divided by 16 (averaging). */ -#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFEC sample rate divided by 64 (averaging). */ -#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFEC sample rate divided by 256 (averaging). */ -#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of AFEC_LDCR register */ -#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ -/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) Channel Sequence 1 Register -------- */ -#define AFEC_SEQ1R_USCH0_Pos 0 -#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ -#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) -#define AFEC_SEQ1R_USCH1_Pos 4 -#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ -#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) -#define AFEC_SEQ1R_USCH2_Pos 8 -#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ -#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) -#define AFEC_SEQ1R_USCH3_Pos 12 -#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ -#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) -#define AFEC_SEQ1R_USCH4_Pos 16 -#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ -#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) -#define AFEC_SEQ1R_USCH5_Pos 20 -#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ -#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) -#define AFEC_SEQ1R_USCH6_Pos 24 -#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ -#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) -#define AFEC_SEQ1R_USCH7_Pos 28 -#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ -#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) -/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) Channel Sequence 2 Register -------- */ -#define AFEC_SEQ2R_USCH8_Pos 0 -#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ -#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) -#define AFEC_SEQ2R_USCH9_Pos 4 -#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ -#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) -#define AFEC_SEQ2R_USCH10_Pos 8 -#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ -#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) -#define AFEC_SEQ2R_USCH11_Pos 12 -#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ -#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) -#define AFEC_SEQ2R_USCH12_Pos 16 -#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ -#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) -#define AFEC_SEQ2R_USCH13_Pos 20 -#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ -#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) -#define AFEC_SEQ2R_USCH14_Pos 24 -#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ -#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) -#define AFEC_SEQ2R_USCH15_Pos 28 -#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ -#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) -/* -------- AFEC_CHER : (AFEC Offset: 0x14) Channel Enable Register -------- */ -#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ -#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ -#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ -#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ -#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ -#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ -#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ -#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ -#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ -#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ -#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ -#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ -#define AFEC_CHER_CH12 (0x1u << 12) /**< \brief (AFEC_CHER) Channel 12 Enable */ -#define AFEC_CHER_CH13 (0x1u << 13) /**< \brief (AFEC_CHER) Channel 13 Enable */ -#define AFEC_CHER_CH14 (0x1u << 14) /**< \brief (AFEC_CHER) Channel 14 Enable */ -#define AFEC_CHER_CH15 (0x1u << 15) /**< \brief (AFEC_CHER) Channel 15 Enable */ -/* -------- AFEC_CHDR : (AFEC Offset: 0x18) Channel Disable Register -------- */ -#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ -#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ -#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ -#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ -#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ -#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ -#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ -#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ -#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ -#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ -#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ -#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ -#define AFEC_CHDR_CH12 (0x1u << 12) /**< \brief (AFEC_CHDR) Channel 12 Disable */ -#define AFEC_CHDR_CH13 (0x1u << 13) /**< \brief (AFEC_CHDR) Channel 13 Disable */ -#define AFEC_CHDR_CH14 (0x1u << 14) /**< \brief (AFEC_CHDR) Channel 14 Disable */ -#define AFEC_CHDR_CH15 (0x1u << 15) /**< \brief (AFEC_CHDR) Channel 15 Disable */ -/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) Channel Status Register -------- */ -#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ -#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ -#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ -#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ -#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ -#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ -#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ -#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ -#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ -#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ -#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ -#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ -#define AFEC_CHSR_CH12 (0x1u << 12) /**< \brief (AFEC_CHSR) Channel 12 Status */ -#define AFEC_CHSR_CH13 (0x1u << 13) /**< \brief (AFEC_CHSR) Channel 13 Status */ -#define AFEC_CHSR_CH14 (0x1u << 14) /**< \brief (AFEC_CHSR) Channel 14 Status */ -#define AFEC_CHSR_CH15 (0x1u << 15) /**< \brief (AFEC_CHSR) Channel 15 Status */ -/* -------- AFEC_LCDR : (AFEC Offset: 0x20) Last Converted Data Register -------- */ -#define AFEC_LCDR_LDATA_Pos 0 -#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ -#define AFEC_LCDR_CHNB_Pos 24 -#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ -/* -------- AFEC_IER : (AFEC Offset: 0x24) Interrupt Enable Register -------- */ -#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ -#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ -#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ -#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ -#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ -#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ -#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ -#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ -#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ -#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ -#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ -#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ -#define AFEC_IER_EOC12 (0x1u << 12) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 12 */ -#define AFEC_IER_EOC13 (0x1u << 13) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 13 */ -#define AFEC_IER_EOC14 (0x1u << 14) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 14 */ -#define AFEC_IER_EOC15 (0x1u << 15) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 15 */ -#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ -#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ -#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable+ */ -#define AFEC_IER_ENDRX (0x1u << 27) /**< \brief (AFEC_IER) End of Receive Buffer Interrupt Enable */ -#define AFEC_IER_RXBUFF (0x1u << 28) /**< \brief (AFEC_IER) Receive Buffer Full Interrupt Enable */ -#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ -#define AFEC_IER_EOCAL (0x1u << 31) /**< \brief (AFEC_IER) End of Calibration Sequence Interrupt Enable */ -/* -------- AFEC_IDR : (AFEC Offset: 0x28) Interrupt Disable Register -------- */ -#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ -#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ -#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ -#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ -#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ -#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ -#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ -#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ -#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ -#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ -#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ -#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ -#define AFEC_IDR_EOC12 (0x1u << 12) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 12 */ -#define AFEC_IDR_EOC13 (0x1u << 13) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 13 */ -#define AFEC_IDR_EOC14 (0x1u << 14) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 14 */ -#define AFEC_IDR_EOC15 (0x1u << 15) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 15 */ -#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ -#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ -#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ -#define AFEC_IDR_ENDRX (0x1u << 27) /**< \brief (AFEC_IDR) End of Receive Buffer Interrupt Disable */ -#define AFEC_IDR_RXBUFF (0x1u << 28) /**< \brief (AFEC_IDR) Receive Buffer Full Interrupt Disable */ -#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ -#define AFEC_IDR_EOCAL (0x1u << 31) /**< \brief (AFEC_IDR) End of Calibration Sequence Interrupt Disable */ -/* -------- AFEC_IMR : (AFEC Offset: 0x2C) Interrupt Mask Register -------- */ -#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ -#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ -#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ -#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ -#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ -#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ -#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ -#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ -#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ -#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ -#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ -#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ -#define AFEC_IMR_EOC12 (0x1u << 12) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 12 */ -#define AFEC_IMR_EOC13 (0x1u << 13) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 13 */ -#define AFEC_IMR_EOC14 (0x1u << 14) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 14 */ -#define AFEC_IMR_EOC15 (0x1u << 15) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 15 */ -#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ -#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ -#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ -#define AFEC_IMR_ENDRX (0x1u << 27) /**< \brief (AFEC_IMR) End of Receive Buffer Interrupt Mask */ -#define AFEC_IMR_RXBUFF (0x1u << 28) /**< \brief (AFEC_IMR) Receive Buffer Full Interrupt Mask */ -#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ -#define AFEC_IMR_EOCAL (0x1u << 31) /**< \brief (AFEC_IMR) End of Calibration Sequence Interrupt Mask */ -/* -------- AFEC_ISR : (AFEC Offset: 0x30) Interrupt Status Register -------- */ -#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 */ -#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 */ -#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 */ -#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 */ -#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 */ -#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 */ -#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 */ -#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 */ -#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 */ -#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 */ -#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 */ -#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 */ -#define AFEC_ISR_EOC12 (0x1u << 12) /**< \brief (AFEC_ISR) End of Conversion 12 */ -#define AFEC_ISR_EOC13 (0x1u << 13) /**< \brief (AFEC_ISR) End of Conversion 13 */ -#define AFEC_ISR_EOC14 (0x1u << 14) /**< \brief (AFEC_ISR) End of Conversion 14 */ -#define AFEC_ISR_EOC15 (0x1u << 15) /**< \brief (AFEC_ISR) End of Conversion 15 */ -#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready */ -#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error */ -#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error */ -#define AFEC_ISR_ENDRX (0x1u << 27) /**< \brief (AFEC_ISR) End of RX Buffer */ -#define AFEC_ISR_RXBUFF (0x1u << 28) /**< \brief (AFEC_ISR) RX Buffer Full */ -#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change */ -#define AFEC_ISR_EOCAL (0x1u << 31) /**< \brief (AFEC_ISR) End of Calibration Sequence */ -/* -------- AFEC_OVER : (AFEC Offset: 0x4C) Overrun Status Register -------- */ -#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ -#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ -#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ -#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ -#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ -#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ -#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ -#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ -#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ -#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ -#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ -#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ -#define AFEC_OVER_OVRE12 (0x1u << 12) /**< \brief (AFEC_OVER) Overrun Error 12 */ -#define AFEC_OVER_OVRE13 (0x1u << 13) /**< \brief (AFEC_OVER) Overrun Error 13 */ -#define AFEC_OVER_OVRE14 (0x1u << 14) /**< \brief (AFEC_OVER) Overrun Error 14 */ -#define AFEC_OVER_OVRE15 (0x1u << 15) /**< \brief (AFEC_OVER) Overrun Error 15 */ -/* -------- AFEC_CWR : (AFEC Offset: 0x50) Compare Window Register -------- */ -#define AFEC_CWR_LOWTHRES_Pos 0 -#define AFEC_CWR_LOWTHRES_Msk (0xfffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ -#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) -#define AFEC_CWR_HIGHTHRES_Pos 16 -#define AFEC_CWR_HIGHTHRES_Msk (0xfffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ -#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) -/* -------- AFEC_CGR : (AFEC Offset: 0x54) Channel Gain Register -------- */ -#define AFEC_CGR_GAIN0_Pos 0 -#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for channel 0 */ -#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) -#define AFEC_CGR_GAIN1_Pos 2 -#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for channel 1 */ -#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) -#define AFEC_CGR_GAIN2_Pos 4 -#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for channel 2 */ -#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) -#define AFEC_CGR_GAIN3_Pos 6 -#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for channel 3 */ -#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) -#define AFEC_CGR_GAIN4_Pos 8 -#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for channel 4 */ -#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) -#define AFEC_CGR_GAIN5_Pos 10 -#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for channel 5 */ -#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) -#define AFEC_CGR_GAIN6_Pos 12 -#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for channel 6 */ -#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) -#define AFEC_CGR_GAIN7_Pos 14 -#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for channel 7 */ -#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) -#define AFEC_CGR_GAIN8_Pos 16 -#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for channel 8 */ -#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) -#define AFEC_CGR_GAIN9_Pos 18 -#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for channel 9 */ -#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) -#define AFEC_CGR_GAIN10_Pos 20 -#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for channel 10 */ -#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) -#define AFEC_CGR_GAIN11_Pos 22 -#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for channel 11 */ -#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) -#define AFEC_CGR_GAIN12_Pos 24 -#define AFEC_CGR_GAIN12_Msk (0x3u << AFEC_CGR_GAIN12_Pos) /**< \brief (AFEC_CGR) Gain for channel 12 */ -#define AFEC_CGR_GAIN12(value) ((AFEC_CGR_GAIN12_Msk & ((value) << AFEC_CGR_GAIN12_Pos))) -#define AFEC_CGR_GAIN13_Pos 26 -#define AFEC_CGR_GAIN13_Msk (0x3u << AFEC_CGR_GAIN13_Pos) /**< \brief (AFEC_CGR) Gain for channel 13 */ -#define AFEC_CGR_GAIN13(value) ((AFEC_CGR_GAIN13_Msk & ((value) << AFEC_CGR_GAIN13_Pos))) -#define AFEC_CGR_GAIN14_Pos 28 -#define AFEC_CGR_GAIN14_Msk (0x3u << AFEC_CGR_GAIN14_Pos) /**< \brief (AFEC_CGR) Gain for channel 14 */ -#define AFEC_CGR_GAIN14(value) ((AFEC_CGR_GAIN14_Msk & ((value) << AFEC_CGR_GAIN14_Pos))) -#define AFEC_CGR_GAIN15_Pos 30 -#define AFEC_CGR_GAIN15_Msk (0x3u << AFEC_CGR_GAIN15_Pos) /**< \brief (AFEC_CGR) Gain for channel 15 */ -#define AFEC_CGR_GAIN15(value) ((AFEC_CGR_GAIN15_Msk & ((value) << AFEC_CGR_GAIN15_Pos))) -/* -------- AFEC_CDOR : (AFEC Offset: 0x5C) Channel Calibration DC Offset Register -------- */ -#define AFEC_CDOR_OFF0 (0x1u << 0) /**< \brief (AFEC_CDOR) Offset for channel 0, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF1 (0x1u << 1) /**< \brief (AFEC_CDOR) Offset for channel 1, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF2 (0x1u << 2) /**< \brief (AFEC_CDOR) Offset for channel 2, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF3 (0x1u << 3) /**< \brief (AFEC_CDOR) Offset for channel 3, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF4 (0x1u << 4) /**< \brief (AFEC_CDOR) Offset for channel 4, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF5 (0x1u << 5) /**< \brief (AFEC_CDOR) Offset for channel 5, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF6 (0x1u << 6) /**< \brief (AFEC_CDOR) Offset for channel 6, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF7 (0x1u << 7) /**< \brief (AFEC_CDOR) Offset for channel 7, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF8 (0x1u << 8) /**< \brief (AFEC_CDOR) Offset for channel 8, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF9 (0x1u << 9) /**< \brief (AFEC_CDOR) Offset for channel 9, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF10 (0x1u << 10) /**< \brief (AFEC_CDOR) Offset for channel 10, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF11 (0x1u << 11) /**< \brief (AFEC_CDOR) Offset for channel 11, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF12 (0x1u << 12) /**< \brief (AFEC_CDOR) Offset for channel 12, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF13 (0x1u << 13) /**< \brief (AFEC_CDOR) Offset for channel 13, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF14 (0x1u << 14) /**< \brief (AFEC_CDOR) Offset for channel 14, used in automatic calibration procedure */ -#define AFEC_CDOR_OFF15 (0x1u << 15) /**< \brief (AFEC_CDOR) Offset for channel 15, used in automatic calibration procedure */ -/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) Channel Differential Register -------- */ -#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ -#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ -#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ -#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ -#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ -#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ -#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ -#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ -#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ -#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ -#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ -#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ -#define AFEC_DIFFR_DIFF12 (0x1u << 12) /**< \brief (AFEC_DIFFR) Differential inputs for channel 12 */ -#define AFEC_DIFFR_DIFF13 (0x1u << 13) /**< \brief (AFEC_DIFFR) Differential inputs for channel 13 */ -#define AFEC_DIFFR_DIFF14 (0x1u << 14) /**< \brief (AFEC_DIFFR) Differential inputs for channel 14 */ -#define AFEC_DIFFR_DIFF15 (0x1u << 15) /**< \brief (AFEC_DIFFR) Differential inputs for channel 15 */ -/* -------- AFEC_CSELR : (AFEC Offset: 0x64) Channel Register Selection -------- */ -#define AFEC_CSELR_CSEL_Pos 0 -#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ -#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) -/* -------- AFEC_CDR : (AFEC Offset: 0x68) Channel Data Register -------- */ -#define AFEC_CDR_DATA_Pos 0 -#define AFEC_CDR_DATA_Msk (0xfffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ -/* -------- AFEC_COCR : (AFEC Offset: 0x6C) Channel Offset Compensation Register -------- */ -#define AFEC_COCR_AOFF_Pos 0 -#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ -#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) -/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) Temperature Sensor Mode Register -------- */ -#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger mode */ -#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 -#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ -#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ -#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ -#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ -#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ -/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) Temperature Compare Window Register -------- */ -#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 -#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ -#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) -#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 -#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ -#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) -/* -------- AFEC_ACR : (AFEC Offset: 0x94) Analog Control Register -------- */ -#define AFEC_ACR_IBCTL_Pos 8 -#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFEC Bias Current Control */ -#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) -/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) Write Protect Mode Register -------- */ -#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protect Enable */ -#define AFEC_WPMR_WPKEY_Pos 8 -#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ -#define AFEC_WPMR_WPKEY_ADC (0x414443u << 8) /**< \brief (AFEC_WPMR) Should be written at value 0x414443 ("ADC" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ -/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) Write Protect Status Register -------- */ -#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ -#define AFEC_WPSR_WPVSRC_Pos 8 -#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ -/* -------- AFEC_RPR : (AFEC Offset: 0x100) Receive Pointer Register -------- */ -#define AFEC_RPR_RXPTR_Pos 0 -#define AFEC_RPR_RXPTR_Msk (0xffffffffu << AFEC_RPR_RXPTR_Pos) /**< \brief (AFEC_RPR) Receive Pointer Register */ -#define AFEC_RPR_RXPTR(value) ((AFEC_RPR_RXPTR_Msk & ((value) << AFEC_RPR_RXPTR_Pos))) -/* -------- AFEC_RCR : (AFEC Offset: 0x104) Receive Counter Register -------- */ -#define AFEC_RCR_RXCTR_Pos 0 -#define AFEC_RCR_RXCTR_Msk (0xffffu << AFEC_RCR_RXCTR_Pos) /**< \brief (AFEC_RCR) Receive Counter Register */ -#define AFEC_RCR_RXCTR(value) ((AFEC_RCR_RXCTR_Msk & ((value) << AFEC_RCR_RXCTR_Pos))) -/* -------- AFEC_RNPR : (AFEC Offset: 0x110) Receive Next Pointer Register -------- */ -#define AFEC_RNPR_RXNPTR_Pos 0 -#define AFEC_RNPR_RXNPTR_Msk (0xffffffffu << AFEC_RNPR_RXNPTR_Pos) /**< \brief (AFEC_RNPR) Receive Next Pointer */ -#define AFEC_RNPR_RXNPTR(value) ((AFEC_RNPR_RXNPTR_Msk & ((value) << AFEC_RNPR_RXNPTR_Pos))) -/* -------- AFEC_RNCR : (AFEC Offset: 0x114) Receive Next Counter Register -------- */ -#define AFEC_RNCR_RXNCTR_Pos 0 -#define AFEC_RNCR_RXNCTR_Msk (0xffffu << AFEC_RNCR_RXNCTR_Pos) /**< \brief (AFEC_RNCR) Receive Next Counter */ -#define AFEC_RNCR_RXNCTR(value) ((AFEC_RNCR_RXNCTR_Msk & ((value) << AFEC_RNCR_RXNCTR_Pos))) -/* -------- AFEC_PTCR : (AFEC Offset: 0x120) Transfer Control Register -------- */ -#define AFEC_PTCR_RXTEN (0x1u << 0) /**< \brief (AFEC_PTCR) Receiver Transfer Enable */ -#define AFEC_PTCR_RXTDIS (0x1u << 1) /**< \brief (AFEC_PTCR) Receiver Transfer Disable */ -#define AFEC_PTCR_TXTEN (0x1u << 8) /**< \brief (AFEC_PTCR) Transmitter Transfer Enable */ -#define AFEC_PTCR_TXTDIS (0x1u << 9) /**< \brief (AFEC_PTCR) Transmitter Transfer Disable */ -/* -------- AFEC_PTSR : (AFEC Offset: 0x124) Transfer Status Register -------- */ -#define AFEC_PTSR_RXTEN (0x1u << 0) /**< \brief (AFEC_PTSR) Receiver Transfer Enable */ -#define AFEC_PTSR_TXTEN (0x1u << 8) /**< \brief (AFEC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_AFEC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/can.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/can.h deleted file mode 100644 index 3417afcec..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/can.h +++ /dev/null @@ -1,304 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CAN_COMPONENT_ -#define _SAM4E_CAN_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Controller Area Network */ -/* ============================================================================= */ -/** \addtogroup SAM4E_CAN Controller Area Network */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief CanMb hardware registers */ -typedef struct { - RwReg CAN_MMR; /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */ - RwReg CAN_MAM; /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */ - RwReg CAN_MID; /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */ - RwReg CAN_MFID; /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */ - RwReg CAN_MSR; /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */ - RwReg CAN_MDL; /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */ - RwReg CAN_MDH; /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */ - RwReg CAN_MCR; /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */ -} CanMb; -/** \brief Can hardware registers */ -#define CANMB_NUMBER 8 -typedef struct { - RwReg CAN_MR; /**< \brief (Can Offset: 0x0000) Mode Register */ - WoReg CAN_IER; /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */ - WoReg CAN_IDR; /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */ - RoReg CAN_IMR; /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */ - RoReg CAN_SR; /**< \brief (Can Offset: 0x0010) Status Register */ - RwReg CAN_BR; /**< \brief (Can Offset: 0x0014) Baudrate Register */ - RoReg CAN_TIM; /**< \brief (Can Offset: 0x0018) Timer Register */ - RoReg CAN_TIMESTP; /**< \brief (Can Offset: 0x001C) Timestamp Register */ - RoReg CAN_ECR; /**< \brief (Can Offset: 0x0020) Error Counter Register */ - WoReg CAN_TCR; /**< \brief (Can Offset: 0x0024) Transfer Command Register */ - WoReg CAN_ACR; /**< \brief (Can Offset: 0x0028) Abort Command Register */ - RoReg Reserved1[46]; - RwReg CAN_WPMR; /**< \brief (Can Offset: 0x00E4) Write Protect Mode Register */ - RoReg CAN_WPSR; /**< \brief (Can Offset: 0x00E8) Write Protect Status Register */ - RoReg Reserved2[69]; - CanMb CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */ -} Can; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */ -#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */ -#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */ -#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */ -#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */ -#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */ -#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */ -#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */ -#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */ -/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */ -#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */ -#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */ -#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */ -#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */ -#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */ -#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */ -#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */ -#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */ -#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */ -#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */ -#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */ -#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */ -#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */ -#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */ -#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */ -#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */ -#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */ -#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */ -#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */ -#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */ -#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */ -/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */ -#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */ -#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */ -#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */ -#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */ -#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */ -#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */ -#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */ -#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */ -#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */ -#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */ -#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */ -#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */ -#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */ -#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */ -#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */ -#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */ -#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */ -#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */ -#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */ -#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */ -#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */ -/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */ -#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */ -#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */ -#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */ -#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */ -#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */ -#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */ -#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */ -#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */ -#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */ -#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */ -#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */ -#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */ -#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */ -#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */ -#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */ -#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */ -#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */ -#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */ -#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */ -#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */ -#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */ -/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */ -#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */ -#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */ -#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */ -#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */ -#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */ -#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */ -#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */ -#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */ -#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */ -#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */ -#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */ -#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */ -#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */ -#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */ -#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */ -#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR) */ -#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */ -#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */ -#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */ -#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */ -#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */ -#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */ -#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */ -#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */ -/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */ -#define CAN_BR_PHASE2_Pos 0 -#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */ -#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos))) -#define CAN_BR_PHASE1_Pos 4 -#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */ -#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos))) -#define CAN_BR_PROPAG_Pos 8 -#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */ -#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos))) -#define CAN_BR_SJW_Pos 12 -#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */ -#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos))) -#define CAN_BR_BRP_Pos 16 -#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */ -#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos))) -#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */ -#define CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */ -#define CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */ -/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */ -#define CAN_TIM_TIMER_Pos 0 -#define CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) /**< \brief (CAN_TIM) Timer */ -/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */ -#define CAN_TIMESTP_MTIMESTAMP_Pos 0 -#define CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) /**< \brief (CAN_TIMESTP) Timestamp */ -/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */ -#define CAN_ECR_REC_Pos 0 -#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */ -#define CAN_ECR_TEC_Pos 16 -#define CAN_ECR_TEC_Msk (0x1ffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */ -/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */ -#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */ -#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */ -#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */ -#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */ -#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */ -#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */ -#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */ -#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */ -#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */ -/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */ -#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */ -#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */ -#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */ -#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */ -#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */ -#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */ -#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */ -#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */ -/* -------- CAN_WPMR : (CAN Offset: 0x00E4) Write Protect Mode Register -------- */ -#define CAN_WPMR_WPEN (0x1u << 0) /**< \brief (CAN_WPMR) Write Protection Enable */ -#define CAN_WPMR_WPKEY_Pos 8 -#define CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) /**< \brief (CAN_WPMR) SPI Write Protection Key Password */ -#define CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos))) -/* -------- CAN_WPSR : (CAN Offset: 0x00E8) Write Protect Status Register -------- */ -#define CAN_WPSR_WPVS (0x1u << 0) /**< \brief (CAN_WPSR) Write Protection Violation Status */ -#define CAN_WPSR_WPVSRC_Pos 8 -#define CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) /**< \brief (CAN_WPSR) Write Protection Violation Source */ -/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */ -#define CAN_MMR_MTIMEMARK_Pos 0 -#define CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) /**< \brief (CAN_MMR) Mailbox Timemark */ -#define CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos))) -#define CAN_MMR_PRIOR_Pos 16 -#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */ -#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos))) -#define CAN_MMR_MOT_Pos 24 -#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */ -#define CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */ -#define CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */ -#define CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */ -#define CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */ -#define CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */ -#define CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */ -/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */ -#define CAN_MAM_MIDvB_Pos 0 -#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */ -#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos))) -#define CAN_MAM_MIDvA_Pos 18 -#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */ -#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos))) -#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */ -/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */ -#define CAN_MID_MIDvB_Pos 0 -#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */ -#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos))) -#define CAN_MID_MIDvA_Pos 18 -#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */ -#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos))) -#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */ -/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */ -#define CAN_MFID_MFID_Pos 0 -#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */ -/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */ -#define CAN_MSR_MTIMESTAMP_Pos 0 -#define CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) /**< \brief (CAN_MSR) Timer value */ -#define CAN_MSR_MDLC_Pos 16 -#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */ -#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */ -#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */ -#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */ -#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */ -/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */ -#define CAN_MDL_MDL_Pos 0 -#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */ -#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos))) -/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */ -#define CAN_MDH_MDH_Pos 0 -#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */ -#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos))) -/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */ -#define CAN_MCR_MDLC_Pos 16 -#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */ -#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos))) -#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */ -#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */ -#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */ - -/*@}*/ - - -#endif /* _SAM4E_CAN_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/chipid.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/chipid.h deleted file mode 100644 index 1c7897ab6..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/chipid.h +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CHIPID_COMPONENT_ -#define _SAM4E_CHIPID_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup SAM4E_CHIPID Chip Identifier */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION_Pos 0 -#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC_Pos 5 -#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ -#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ -#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ -#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ -#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ -#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ -#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ -#define CHIPID_CIDR_NVPSIZ_Pos 8 -#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ -#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ -#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_Pos 12 -#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ -#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ -#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_Pos 16 -#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ -#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ -#define CHIPID_CIDR_ARCH_Pos 20 -#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */ -#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */ -#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */ -#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */ -#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */ -#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */ -#define CHIPID_CIDR_ARCH_SAM4E (0x3Cu << 20) /**< \brief (CHIPID_CIDR) SAM4E Series */ -#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */ -#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */ -#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */ -#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */ -#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */ -#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */ -#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */ -#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */ -#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */ -#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */ -#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */ -#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */ -#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */ -#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */ -#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */ -#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */ -#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */ -#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */ -#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */ -#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */ -#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */ -#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */ -#define CHIPID_CIDR_ARCH_SAM4LxA (0xB0u << 20) /**< \brief (CHIPID_CIDR) SAM4LxA Series (48-pin version) */ -#define CHIPID_CIDR_ARCH_SAM4LxB (0xB1u << 20) /**< \brief (CHIPID_CIDR) SAM4LxB Series (64-pin version) */ -#define CHIPID_CIDR_ARCH_SAM4LxC (0xB2u << 20) /**< \brief (CHIPID_CIDR) SAM4LxC Series (100-pin version) */ -#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */ -#define CHIPID_CIDR_NVPTYP_Pos 28 -#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ -#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ -#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ -#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */ -#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ -#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID_Pos 0 -#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - - -#endif /* _SAM4E_CHIPID_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/cmcc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/cmcc.h deleted file mode 100644 index 2d9bc4681..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/cmcc.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CMCC_COMPONENT_ -#define _SAM4E_CMCC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cortex M Cache Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_CMCC Cortex M Cache Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Cmcc hardware registers */ -typedef struct { - RoReg CMCC_TYPE; /**< \brief (Cmcc Offset: 0x00) Cache Type Register */ - RwReg CMCC_CFG; /**< \brief (Cmcc Offset: 0x04) Cache Configuration Register */ - WoReg CMCC_CTRL; /**< \brief (Cmcc Offset: 0x08) Cache Control Register */ - RoReg CMCC_SR; /**< \brief (Cmcc Offset: 0x0C) Cache Status Register */ - RoReg Reserved1[4]; - WoReg CMCC_MAINT0; /**< \brief (Cmcc Offset: 0x20) Cache Maintenance Register 0 */ - WoReg CMCC_MAINT1; /**< \brief (Cmcc Offset: 0x24) Cache Maintenance Register 1 */ - RwReg CMCC_MCFG; /**< \brief (Cmcc Offset: 0x28) Cache Monitor Configuration Register */ - RwReg CMCC_MEN; /**< \brief (Cmcc Offset: 0x2C) Cache Monitor Enable Register */ - WoReg CMCC_MCTRL; /**< \brief (Cmcc Offset: 0x30) Cache Monitor Control Register */ - RoReg CMCC_MSR; /**< \brief (Cmcc Offset: 0x34) Cache Monitor Status Register */ -} Cmcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- CMCC_TYPE : (CMCC Offset: 0x00) Cache Type Register -------- */ -#define CMCC_TYPE_AP (0x1u << 0) /**< \brief (CMCC_TYPE) Access Port Access Allowed */ -#define CMCC_TYPE_GCLK (0x1u << 1) /**< \brief (CMCC_TYPE) Dynamic Clock Gating Supported */ -#define CMCC_TYPE_RANDP (0x1u << 2) /**< \brief (CMCC_TYPE) Random Selection Policy Supported */ -#define CMCC_TYPE_LRUP (0x1u << 3) /**< \brief (CMCC_TYPE) Least Recently Used Policy Supported */ -#define CMCC_TYPE_RRP (0x1u << 4) /**< \brief (CMCC_TYPE) Random Selection Policy Supported */ -#define CMCC_TYPE_WAYNUM_Pos 5 -#define CMCC_TYPE_WAYNUM_Msk (0x3u << CMCC_TYPE_WAYNUM_Pos) /**< \brief (CMCC_TYPE) Number of Way */ -#define CMCC_TYPE_WAYNUM_DMAPPED (0x0u << 5) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY (0x1u << 5) /**< \brief (CMCC_TYPE) 2-WAY set associative */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY (0x2u << 5) /**< \brief (CMCC_TYPE) 4-WAY set associative */ -#define CMCC_TYPE_WAYNUM_ARCH8WAY (0x3u << 5) /**< \brief (CMCC_TYPE) 8-WAY set associative */ -#define CMCC_TYPE_LCKDOWN (0x1u << 7) /**< \brief (CMCC_TYPE) Lock Down Supported */ -#define CMCC_TYPE_CSIZE_Pos 8 -#define CMCC_TYPE_CSIZE_Msk (0x7u << CMCC_TYPE_CSIZE_Pos) /**< \brief (CMCC_TYPE) Cache Size */ -#define CMCC_TYPE_CSIZE_CSIZE_1KB (0x0u << 8) /**< \brief (CMCC_TYPE) Cache Size 1 Kbytes */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB (0x1u << 8) /**< \brief (CMCC_TYPE) Cache Size 2 Kbytes */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB (0x2u << 8) /**< \brief (CMCC_TYPE) Cache Size 4 Kbytes */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB (0x3u << 8) /**< \brief (CMCC_TYPE) Cache Size 8 Kbytes */ -#define CMCC_TYPE_CLSIZE_Pos 11 -#define CMCC_TYPE_CLSIZE_Msk (0x7u << CMCC_TYPE_CLSIZE_Pos) /**< \brief (CMCC_TYPE) Cache Size */ -#define CMCC_TYPE_CLSIZE_CLSIZE_1KB (0x0u << 11) /**< \brief (CMCC_TYPE) 4 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_2KB (0x1u << 11) /**< \brief (CMCC_TYPE) 8 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_4KB (0x2u << 11) /**< \brief (CMCC_TYPE) 16 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8KB (0x3u << 11) /**< \brief (CMCC_TYPE) 32 bytes */ -/* -------- CMCC_CFG : (CMCC Offset: 0x04) Cache Configuration Register -------- */ -#define CMCC_CFG_GCLKDIS (0x1u << 0) /**< \brief (CMCC_CFG) Disable Clock Gating */ -/* -------- CMCC_CTRL : (CMCC Offset: 0x08) Cache Control Register -------- */ -#define CMCC_CTRL_CEN (0x1u << 0) /**< \brief (CMCC_CTRL) Cache Controller Enable */ -/* -------- CMCC_SR : (CMCC Offset: 0x0C) Cache Status Register -------- */ -#define CMCC_SR_CSTS (0x1u << 0) /**< \brief (CMCC_SR) Cache Controller Status */ -/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) Cache Maintenance Register 0 -------- */ -#define CMCC_MAINT0_INVALL (0x1u << 0) /**< \brief (CMCC_MAINT0) Cache Controller Invalidate All */ -/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) Cache Maintenance Register 1 -------- */ -#define CMCC_MAINT1_INDEX_Pos 4 -#define CMCC_MAINT1_INDEX_Msk (0x1fu << CMCC_MAINT1_INDEX_Pos) /**< \brief (CMCC_MAINT1) Invalidate Index */ -#define CMCC_MAINT1_INDEX(value) ((CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))) -#define CMCC_MAINT1_WAY_Pos 30 -#define CMCC_MAINT1_WAY_Msk (0x3u << CMCC_MAINT1_WAY_Pos) /**< \brief (CMCC_MAINT1) Invalidate Way */ -#define CMCC_MAINT1_WAY_WAY0 (0x0u << 30) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY1 (0x1u << 30) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY2 (0x2u << 30) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY3 (0x3u << 30) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ -/* -------- CMCC_MCFG : (CMCC Offset: 0x28) Cache Monitor Configuration Register -------- */ -#define CMCC_MCFG_MODE_Pos 0 -#define CMCC_MCFG_MODE_Msk (0x3u << CMCC_MCFG_MODE_Pos) /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ -#define CMCC_MCFG_MODE_CYCLE_COUNT (0x0u << 0) /**< \brief (CMCC_MCFG) Cycle counter */ -#define CMCC_MCFG_MODE_IHIT_COUNT (0x1u << 0) /**< \brief (CMCC_MCFG) Instruction hit counter */ -#define CMCC_MCFG_MODE_DHIT_COUNT (0x2u << 0) /**< \brief (CMCC_MCFG) Data hit counter */ -/* -------- CMCC_MEN : (CMCC Offset: 0x2C) Cache Monitor Enable Register -------- */ -#define CMCC_MEN_MENABLE (0x1u << 0) /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ -/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) Cache Monitor Control Register -------- */ -#define CMCC_MCTRL_SWRST (0x1u << 0) /**< \brief (CMCC_MCTRL) Monitor */ -/* -------- CMCC_MSR : (CMCC Offset: 0x34) Cache Monitor Status Register -------- */ -#define CMCC_MSR_EVENT_CNT_Pos 0 -#define CMCC_MSR_EVENT_CNT_Msk (0xffffffffu << CMCC_MSR_EVENT_CNT_Pos) /**< \brief (CMCC_MSR) Monitor Event Counter */ - -/*@}*/ - - -#endif /* _SAM4E_CMCC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/crccu.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/crccu.h deleted file mode 100644 index a10fff8e1..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/crccu.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CRCCU_COMPONENT_ -#define _SAM4E_CRCCU_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup SAM4E_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Crccu hardware registers */ -typedef struct { - RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ - RoReg Reserved1[1]; - WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ - WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ - RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ - WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ - WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ - RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ - RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ - RoReg Reserved2[4]; - WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ - RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ - RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ - WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ - WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ - RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ - RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR_Pos 9 -#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos))) -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE_Pos 2 -#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER_Pos 4 -#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */ -#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos))) -/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC_Pos 0 -#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - - -#endif /* _SAM4E_CRCCU_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/dacc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/dacc.h deleted file mode 100644 index 9739b1276..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/dacc.h +++ /dev/null @@ -1,225 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_DACC_COMPONENT_ -#define _SAM4E_DACC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_DACC Digital-to-Analog Converter Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Dacc hardware registers */ -typedef struct { - WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ - RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ - RoReg Reserved1[2]; - WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ - WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ - RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ - RoReg Reserved2[1]; - WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ - WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ - WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ - RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ - RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ - RoReg Reserved3[24]; - RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ - RoReg Reserved4[19]; - RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ - RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ - RoReg Reserved5[7]; - RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ - RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ - RoReg Reserved6[2]; - RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ - RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ - WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ - RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ -} Dacc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ -#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ -/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ -#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */ -#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */ -#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */ -#define DACC_MR_TRGSEL_Pos 1 -#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */ -#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos))) -#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */ -#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */ -#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ -#define DACC_MR_REFRESH_Pos 8 -#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ -#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) -#define DACC_MR_USER_SEL_Pos 16 -#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */ -#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */ -#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */ -#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */ -#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */ -#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */ -#define DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */ -#define DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */ -#define DACC_MR_CLKDIV (0x1u << 22) /**< \brief (DACC_MR) Clock Divider */ -#define DACC_MR_CLKDIV_DIV_2 (0x0u << 22) /**< \brief (DACC_MR) The DAC clock is MCK divided by 2 */ -#define DACC_MR_CLKDIV_DIV_4 (0x1u << 22) /**< \brief (DACC_MR) The DAC clock is MCK divided by 4 (to be used when MCK frequency is above 100MHz) */ -#define DACC_MR_STARTUP_Pos 24 -#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */ -#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */ -#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */ -#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */ -#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */ -#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */ -#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */ -#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */ -#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */ -#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */ -#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */ -#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */ -#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */ -#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */ -#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */ -#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */ -#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */ -#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */ -#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */ -#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */ -#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */ -#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */ -#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */ -#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */ -#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */ -#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */ -#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */ -#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */ -#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */ -#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */ -#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */ -#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */ -#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */ -/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ -#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ -#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ -/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ -#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ -#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ -/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ -#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ -#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ -/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ -#define DACC_CDR_DATA_Pos 0 -#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */ -#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos))) -/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ -#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ -#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ -#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ -#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ -#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ -#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ -#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ -#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ -#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ -#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ -#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ -#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ -#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ -#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ -#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ -/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ -#define DACC_ACR_IBCTLCH0_Pos 0 -#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) -#define DACC_ACR_IBCTLCH1_Pos 2 -#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) -#define DACC_ACR_IBCTLDACCORE_Pos 8 -#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ -#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos))) -/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ -#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ -#define DACC_WPMR_WPKEY_Pos 8 -#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */ -#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) -/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ -#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */ -#define DACC_WPSR_WPROTADDR_Pos 8 -#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */ -/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ -#define DACC_TPR_TXPTR_Pos 0 -#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */ -#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos))) -/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ -#define DACC_TCR_TXCTR_Pos 0 -#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */ -#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos))) -/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define DACC_TNPR_TXNPTR_Pos 0 -#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */ -#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos))) -/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define DACC_TNCR_TXNCTR_Pos 0 -#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */ -#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos))) -/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ -#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ -#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ -#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ -#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ -/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ -#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ -#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_DACC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/dmac.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/dmac.h deleted file mode 100644 index e507ce609..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/dmac.h +++ /dev/null @@ -1,305 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_DMAC_COMPONENT_ -#define _SAM4E_DMAC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR DMA Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_DMAC DMA Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief DmacCh_num hardware registers */ -typedef struct { - RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */ - RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */ - RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */ - RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */ - RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */ - RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */ - RoReg Reserved1[4]; -} DmacCh_num; -/** \brief Dmac hardware registers */ -#define DMACCH_NUM_NUMBER 4 -typedef struct { - RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */ - RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */ - RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */ - RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */ - RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */ - RoReg Reserved1[1]; - WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ - WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ - RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ - RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ - WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */ - WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */ - RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */ - RoReg Reserved2[2]; - DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */ - RoReg Reserved3[66]; - RwReg DMAC_WPMR; /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */ - RoReg DMAC_WPSR; /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */ -} Dmac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */ -#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */ -#define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */ -#define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */ -/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */ -#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) General Enable of DMA */ -/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */ -#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */ -#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */ -#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */ -#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */ -#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */ -#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */ -#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */ -#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */ -/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */ -#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */ -#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */ -#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */ -#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */ -#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */ -#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */ -#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */ -#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */ -/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */ -#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */ -#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */ -#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */ -#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */ -#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */ -#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */ -#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */ -#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */ -/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */ -#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [3:0] */ -#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [3:0] */ -#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [3:0] */ -#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [3:0] */ -/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */ -#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */ -#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */ -#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */ -#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */ -/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */ -#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */ -#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */ -#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */ -#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */ -/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */ -#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */ -#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */ -#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [3:0] */ -#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [3:0] */ -#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [3:0] */ -#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [3:0] */ -/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */ -#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [3:0] */ -#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [3:0] */ -#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [3:0] */ -#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [3:0] */ -#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [3:0] */ -#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [3:0] */ -#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [3:0] */ -#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [3:0] */ -#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [3:0] */ -#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [3:0] */ -#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [3:0] */ -#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [3:0] */ -/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */ -#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [3:0] */ -#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [3:0] */ -#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [3:0] */ -#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [3:0] */ -#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [3:0] */ -#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [3:0] */ -#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [3:0] */ -#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [3:0] */ -/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */ -#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [3:0] */ -#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [3:0] */ -#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [3:0] */ -#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [3:0] */ -#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [3:0] */ -#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [3:0] */ -#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [3:0] */ -#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [3:0] */ -#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [3:0] */ -#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [3:0] */ -#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [3:0] */ -#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [3:0] */ -#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [3:0] */ -#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [3:0] */ -#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [3:0] */ -#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [3:0] */ -/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */ -#define DMAC_SADDR_SADDR_Pos 0 -#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */ -#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos))) -/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */ -#define DMAC_DADDR_DADDR_Pos 0 -#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */ -#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos))) -/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */ -#define DMAC_DSCR_DSCR_Pos 2 -#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */ -#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos))) -/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */ -#define DMAC_CTRLA_BTSIZE_Pos 0 -#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */ -#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos))) -#define DMAC_CTRLA_SRC_WIDTH_Pos 24 -#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */ -#define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */ -#define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */ -#define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */ -#define DMAC_CTRLA_DST_WIDTH_Pos 28 -#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */ -#define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */ -#define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */ -#define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */ -#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) Current Descriptor Stop Command and Transfer Completed Memory Indicator */ -/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */ -#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */ -#define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */ -#define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */ -#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */ -#define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */ -#define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */ -#define DMAC_CTRLB_FC_Pos 21 -#define DMAC_CTRLB_FC_Msk (0x3u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */ -#define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */ -#define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */ -#define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */ -#define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */ -#define DMAC_CTRLB_SRC_INCR_Pos 24 -#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */ -#define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */ -#define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */ -#define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */ -#define DMAC_CTRLB_DST_INCR_Pos 28 -#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */ -#define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */ -#define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */ -#define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */ -#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) Interrupt Enable Not */ -/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */ -#define DMAC_CFG_SRC_PER_Pos 0 -#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */ -#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos))) -#define DMAC_CFG_DST_PER_Pos 4 -#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */ -#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos))) -#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */ -#define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */ -#define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */ -#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */ -#define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */ -#define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */ -#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */ -#define DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */ -#define DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */ -#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */ -#define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */ -#define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */ -#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */ -#define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */ -#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */ -#define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */ -#define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */ -#define DMAC_CFG_AHB_PROT_Pos 24 -#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */ -#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos))) -#define DMAC_CFG_FIFOCFG_Pos 28 -#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */ -#define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */ -#define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */ -#define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */ -/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */ -#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */ -#define DMAC_WPMR_WPKEY_Pos 8 -#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */ -#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos))) -/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */ -#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */ -#define DMAC_WPSR_WPVSRC_Pos 8 -#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */ - -/*@}*/ - - -#endif /* _SAM4E_DMAC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/efc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/efc.h deleted file mode 100644 index d5d039100..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/efc.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_EFC_COMPONENT_ -#define _SAM4E_EFC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_EFC Embedded Flash Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS_Pos 8 -#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) -#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ -#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loops Optimization Enable */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD_Pos 0 -#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash Descriptor */ -#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ -#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ -#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ -#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ -#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ -#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase Pages */ -#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set Lock Bit */ -#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear Lock Bit */ -#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get Lock Bit */ -#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM Bit */ -#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM Bit */ -#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM Bit */ -#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start Read Unique Identifier */ -#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop Read Unique Identifier */ -#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB Bit */ -#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase Sector */ -#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write User Signature */ -#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase User Signature */ -#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start Read User Signature */ -#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop Read User Signature */ -#define EEFC_FCR_FARG_Pos 8 -#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) -#define EEFC_FCR_FKEY_Pos 24 -#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE_Pos 0 -#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - - -#endif /* _SAM4E_EFC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/gmac.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/gmac.h deleted file mode 100644 index 164b397ca..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/gmac.h +++ /dev/null @@ -1,627 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_GMAC_COMPONENT_ -#define _SAM4E_GMAC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ -/* ============================================================================= */ -/** \addtogroup SAM4E_GMAC Gigabit Ethernet MAC */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief GmacSa hardware registers */ -typedef struct { - RwReg GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom [31:0] Register */ - RwReg GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top [47:32] Register */ -} GmacSa; -/** \brief Gmac hardware registers */ -#define GMACSA_NUMBER 4 -typedef struct { - RwReg GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ - RwReg GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ - RoReg GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ - RwReg GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ - RwReg GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ - RwReg GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ - RwReg GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address */ - RwReg GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address */ - RwReg GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ - RoReg GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ - WoReg GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ - WoReg GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ - RoReg GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ - RwReg GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ - RoReg GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ - RwReg GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ - RoReg Reserved1[16]; - RwReg GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom [31:0] */ - RwReg GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top [63:32] */ - GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ - RwReg GMAC_TIDM[4]; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ - RoReg Reserved2[1]; - RwReg GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ - RwReg GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ - RwReg GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ - RwReg GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register */ - RwReg GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register */ - RoReg Reserved3[12]; - RoReg GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted [31:0] Register */ - RoReg GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted [47:32] Register */ - RoReg GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ - RoReg GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ - RoReg GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ - RoReg GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ - RoReg GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ - RoReg GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ - RoReg GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ - RoReg GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ - RoReg GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ - RoReg GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ - RoReg GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ - RoReg GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Under Runs Register */ - RoReg GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ - RoReg GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ - RoReg GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ - RoReg GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ - RoReg GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ - RoReg GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ - RoReg GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received [31:0] Received */ - RoReg GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received [47:32] Received */ - RoReg GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ - RoReg GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ - RoReg GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ - RoReg GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ - RoReg GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ - RoReg GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ - RoReg GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ - RoReg GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511Byte Frames Received Register */ - RoReg GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ - RoReg GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ - RoReg GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ - RoReg GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ - RoReg GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ - RoReg GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ - RoReg GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ - RoReg GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ - RoReg GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ - RoReg GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ - RoReg GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ - RoReg GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ - RoReg GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ - RoReg GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ - RoReg GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ - RoReg Reserved4[5]; - RwReg GMAC_TSSS; /**< \brief (Gmac Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register */ - RwReg GMAC_TSSN; /**< \brief (Gmac Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register */ - RwReg GMAC_TS; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Register */ - RwReg GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ - WoReg GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ - RwReg GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ - RoReg GMAC_EFTS; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds */ - RoReg GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds */ - RoReg GMAC_EFRS; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds */ - RoReg GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds */ - RoReg GMAC_PEFTS; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds */ - RoReg GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds */ - RoReg GMAC_PEFRS; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds */ - RoReg GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds */ -} Gmac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ -#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ -#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ -#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ -#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ -#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ -#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ -#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ -#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ -#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ -#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ -#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ -#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ -#define GMAC_NCR_RDS (0x1u << 14) /**< \brief (GMAC_NCR) Read Snapshot */ -#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ -#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ -#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ -#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ -/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ -#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ -#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ -#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ -#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ -#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ -#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ -#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ -#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ -#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ -#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ -#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ -#define GMAC_NCFGR_RXBUFO_Pos 14 -#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ -#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) -#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ -#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ -#define GMAC_NCFGR_CLK_Pos 18 -#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ -#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ -#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ -#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ -#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120MHz) */ -#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ -#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ -#define GMAC_NCFGR_DBW_Pos 21 -#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ -#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) -#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ -#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ -#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ -#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ -#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ -#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ -#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ -/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ -#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ -#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ -/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ -#define GMAC_UR_RMIIMII (0x1u << 0) /**< \brief (GMAC_UR) */ -/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ -#define GMAC_DCFGR_FBLDO_Pos 0 -#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ -#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ -#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ -#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ -#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ -#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ -#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ -#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ -#define GMAC_DCFGR_DRBS_Pos 16 -#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ -#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) -/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ -#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ -#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ -#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ -#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ -#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption due to AHB error */ -#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ -#define GMAC_TSR_UND (0x1u << 6) /**< \brief (GMAC_TSR) Transmit Under Run */ -#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ -/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address -------- */ -#define GMAC_RBQB_ADDR_Pos 2 -#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive buffer queue base address */ -#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) -/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address -------- */ -#define GMAC_TBQB_ADDR_Pos 2 -#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ -#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) -/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ -#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ -#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ -#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ -#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ -/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ -#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ -#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ -#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ -#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ -#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Under Run */ -#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ -#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption due to AHB error */ -#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ -#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ -#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ -#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ -#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ -#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ -#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ -#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ -#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ -#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ -#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ -#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ -#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ -#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ -#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ -#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ -/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ -#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ -#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ -#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ -#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ -#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Under Run */ -#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ -#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption due to AHB error */ -#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ -#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ -#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ -#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ -#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ -#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ -#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ -#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ -#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ -#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ -#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ -#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ -#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ -#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ -#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ -#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ -#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ -/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ -#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ -#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ -#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ -#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ -#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Under Run */ -#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ -#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption due to AHB error */ -#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ -#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ -#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ -#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ -#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ -#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ -#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ -#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ -#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ -#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ -#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ -#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ -#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ -#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ -#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ -#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ -#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ -/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ -#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ -#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ -#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ -#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ -#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Under Run */ -#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ -#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption due to AHB error */ -#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ -#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ -#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ -#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ -#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ -#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ -#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ -#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ -#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ -#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ -#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ -#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ -#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ -#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ -#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ -/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ -#define GMAC_MAN_DATA_Pos 0 -#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ -#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) -#define GMAC_MAN_WTN_Pos 16 -#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ -#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) -#define GMAC_MAN_REGA_Pos 18 -#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ -#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) -#define GMAC_MAN_PHYA_Pos 23 -#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ -#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) -#define GMAC_MAN_OP_Pos 28 -#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ -#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) -#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ -#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ -/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ -#define GMAC_RPQ_RPQ_Pos 0 -#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ -/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ -#define GMAC_TPQ_TPQ_Pos 0 -#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ -#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) -/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom [31:0] -------- */ -#define GMAC_HRB_ADDR_Pos 0 -#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ -#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) -/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top [63:32] -------- */ -#define GMAC_HRT_ADDR_Pos 0 -#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ -#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) -/* -------- GMAC_SAB1 : (GMAC Offset: 0x088) Specific Address 1 Bottom [31:0] Register -------- */ -#define GMAC_SAB1_ADDR_Pos 0 -#define GMAC_SAB1_ADDR_Msk (0xffffffffu << GMAC_SAB1_ADDR_Pos) /**< \brief (GMAC_SAB1) Specific Address 1 */ -#define GMAC_SAB1_ADDR(value) ((GMAC_SAB1_ADDR_Msk & ((value) << GMAC_SAB1_ADDR_Pos))) -/* -------- GMAC_SAT1 : (GMAC Offset: 0x08C) Specific Address 1 Top [47:32] Register -------- */ -#define GMAC_SAT1_ADDR_Pos 0 -#define GMAC_SAT1_ADDR_Msk (0xffffu << GMAC_SAT1_ADDR_Pos) /**< \brief (GMAC_SAT1) Specific Address 1 */ -#define GMAC_SAT1_ADDR(value) ((GMAC_SAT1_ADDR_Msk & ((value) << GMAC_SAT1_ADDR_Pos))) -/* -------- GMAC_SAB2 : (GMAC Offset: 0x090) Specific Address 2 Bottom [31:0] Register -------- */ -#define GMAC_SAB2_ADDR_Pos 0 -#define GMAC_SAB2_ADDR_Msk (0xffffffffu << GMAC_SAB2_ADDR_Pos) /**< \brief (GMAC_SAB2) Specific Address 2 */ -#define GMAC_SAB2_ADDR(value) ((GMAC_SAB2_ADDR_Msk & ((value) << GMAC_SAB2_ADDR_Pos))) -/* -------- GMAC_SAT2 : (GMAC Offset: 0x094) Specific Address 2 Top [47:32] Register -------- */ -#define GMAC_SAT2_ADDR_Pos 0 -#define GMAC_SAT2_ADDR_Msk (0xffffu << GMAC_SAT2_ADDR_Pos) /**< \brief (GMAC_SAT2) Specific Address 2 */ -#define GMAC_SAT2_ADDR(value) ((GMAC_SAT2_ADDR_Msk & ((value) << GMAC_SAT2_ADDR_Pos))) -/* -------- GMAC_SAB3 : (GMAC Offset: 0x098) Specific Address 3 Bottom [31:0] Register -------- */ -#define GMAC_SAB3_ADDR_Pos 0 -#define GMAC_SAB3_ADDR_Msk (0xffffffffu << GMAC_SAB3_ADDR_Pos) /**< \brief (GMAC_SAB3) Specific Address 3 */ -#define GMAC_SAB3_ADDR(value) ((GMAC_SAB3_ADDR_Msk & ((value) << GMAC_SAB3_ADDR_Pos))) -/* -------- GMAC_SAT3 : (GMAC Offset: 0x09C) Specific Address 3 Top [47:32] Register -------- */ -#define GMAC_SAT3_ADDR_Pos 0 -#define GMAC_SAT3_ADDR_Msk (0xffffu << GMAC_SAT3_ADDR_Pos) /**< \brief (GMAC_SAT3) Specific Address 3 */ -#define GMAC_SAT3_ADDR(value) ((GMAC_SAT3_ADDR_Msk & ((value) << GMAC_SAT3_ADDR_Pos))) -/* -------- GMAC_SAB4 : (GMAC Offset: 0x0A0) Specific Address 4 Bottom [31:0] Register -------- */ -#define GMAC_SAB4_ADDR_Pos 0 -#define GMAC_SAB4_ADDR_Msk (0xffffffffu << GMAC_SAB4_ADDR_Pos) /**< \brief (GMAC_SAB4) Specific Address 4 */ -#define GMAC_SAB4_ADDR(value) ((GMAC_SAB4_ADDR_Msk & ((value) << GMAC_SAB4_ADDR_Pos))) -/* -------- GMAC_SAT4 : (GMAC Offset: 0x0A4) Specific Address 4 Top [47:32] Register -------- */ -#define GMAC_SAT4_ADDR_Pos 0 -#define GMAC_SAT4_ADDR_Msk (0xffffu << GMAC_SAT4_ADDR_Pos) /**< \brief (GMAC_SAT4) Specific Address 4 */ -#define GMAC_SAT4_ADDR(value) ((GMAC_SAT4_ADDR_Msk & ((value) << GMAC_SAT4_ADDR_Pos))) -/* -------- GMAC_TIDM[4] : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ -#define GMAC_TIDM_TID_Pos 0 -#define GMAC_TIDM_TID_Msk (0xffffu << GMAC_TIDM_TID_Pos) /**< \brief (GMAC_TIDM[4]) Type ID Match 1 */ -#define GMAC_TIDM_TID(value) ((GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))) -/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ -#define GMAC_IPGS_FL_Pos 0 -#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ -#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) -/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ -#define GMAC_SVLAN_VLAN_TYPE_Pos 0 -#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ -#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) -#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ -/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ -#define GMAC_TPFCP_PEV_Pos 0 -#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ -#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) -#define GMAC_TPFCP_PQ_Pos 8 -#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ -#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) -/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register -------- */ -#define GMAC_SAMB1_ADDR_Pos 0 -#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ -#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) -/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register -------- */ -#define GMAC_SAMT1_ADDR_Pos 0 -#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ -#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) -/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted [31:0] Register -------- */ -#define GMAC_OTLO_TXO_Pos 0 -#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ -/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted [47:32] Register -------- */ -#define GMAC_OTHI_TXO_Pos 0 -#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ -/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ -#define GMAC_FT_FTX_Pos 0 -#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ -/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ -#define GMAC_BCFT_BFTX_Pos 0 -#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ -/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ -#define GMAC_MFT_MFTX_Pos 0 -#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ -/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ -#define GMAC_PFT_PFTX_Pos 0 -#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ -/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ -#define GMAC_BFT64_NFTX_Pos 0 -#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ -/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ -#define GMAC_TBFT127_NFTX_Pos 0 -#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ -/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ -#define GMAC_TBFT255_NFTX_Pos 0 -#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ -/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ -#define GMAC_TBFT511_NFTX_Pos 0 -#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ -/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ -#define GMAC_TBFT1023_NFTX_Pos 0 -#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ -/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ -#define GMAC_TBFT1518_NFTX_Pos 0 -#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ -/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ -#define GMAC_GTBFT1518_NFTX_Pos 0 -#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ -/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Under Runs Register -------- */ -#define GMAC_TUR_TXUNR_Pos 0 -#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Under Runs */ -/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ -#define GMAC_SCF_SCOL_Pos 0 -#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ -/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ -#define GMAC_MCF_MCOL_Pos 0 -#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ -/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ -#define GMAC_EC_XCOL_Pos 0 -#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ -/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ -#define GMAC_LC_LCOL_Pos 0 -#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ -/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ -#define GMAC_DTF_DEFT_Pos 0 -#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ -/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ -#define GMAC_CSE_CSR_Pos 0 -#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ -/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received [31:0] Received -------- */ -#define GMAC_ORLO_RXO_Pos 0 -#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ -/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received [47:32] Received -------- */ -#define GMAC_ORHI_RXO_Pos 0 -#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ -/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ -#define GMAC_FR_FRX_Pos 0 -#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ -/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ -#define GMAC_BCFR_BFRX_Pos 0 -#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ -/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ -#define GMAC_MFR_MFRX_Pos 0 -#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ -/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ -#define GMAC_PFR_PFRX_Pos 0 -#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ -/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ -#define GMAC_BFR64_NFRX_Pos 0 -#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ -/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ -#define GMAC_TBFR127_NFRX_Pos 0 -#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ -/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ -#define GMAC_TBFR255_NFRX_Pos 0 -#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ -/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511Byte Frames Received Register -------- */ -#define GMAC_TBFR511_NFRX_Pos 0 -#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ -/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ -#define GMAC_TBFR1023_NFRX_Pos 0 -#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ -/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ -#define GMAC_TBFR1518_NFRX_Pos 0 -#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ -/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ -#define GMAC_TMXBFR_NFRX_Pos 0 -#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ -/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ -#define GMAC_UFR_UFRX_Pos 0 -#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ -/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ -#define GMAC_OFR_OFRX_Pos 0 -#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ -/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ -#define GMAC_JR_JRX_Pos 0 -#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ -/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ -#define GMAC_FCSE_FCKR_Pos 0 -#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ -/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ -#define GMAC_LFFE_LFER_Pos 0 -#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ -/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ -#define GMAC_RSE_RXSE_Pos 0 -#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ -/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ -#define GMAC_AE_AER_Pos 0 -#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ -/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ -#define GMAC_RRE_RXRER_Pos 0 -#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ -/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ -#define GMAC_ROE_RXOVR_Pos 0 -#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ -/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ -#define GMAC_IHCE_HCKER_Pos 0 -#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ -/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ -#define GMAC_TCE_TCKER_Pos 0 -#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ -/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ -#define GMAC_UCE_UCKER_Pos 0 -#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ -/* -------- GMAC_TSSS : (GMAC Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register -------- */ -#define GMAC_TSSS_VTS_Pos 0 -#define GMAC_TSSS_VTS_Msk (0xffffffffu << GMAC_TSSS_VTS_Pos) /**< \brief (GMAC_TSSS) Value of Timer Seconds Register Capture */ -#define GMAC_TSSS_VTS(value) ((GMAC_TSSS_VTS_Msk & ((value) << GMAC_TSSS_VTS_Pos))) -/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register -------- */ -#define GMAC_TSSN_VTN_Pos 0 -#define GMAC_TSSN_VTN_Msk (0x3fffffffu << GMAC_TSSN_VTN_Pos) /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */ -#define GMAC_TSSN_VTN(value) ((GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))) -/* -------- GMAC_TS : (GMAC Offset: 0x1D0) 1588 Timer Seconds Register -------- */ -#define GMAC_TS_TCS_Pos 0 -#define GMAC_TS_TCS_Msk (0xffffffffu << GMAC_TS_TCS_Pos) /**< \brief (GMAC_TS) Timer Count in Seconds */ -#define GMAC_TS_TCS(value) ((GMAC_TS_TCS_Msk & ((value) << GMAC_TS_TCS_Pos))) -/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ -#define GMAC_TN_TNS_Pos 0 -#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ -#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) -/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ -#define GMAC_TA_ITDT_Pos 0 -#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ -#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) -#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ -/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ -#define GMAC_TI_CNS_Pos 0 -#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ -#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) -#define GMAC_TI_ACNS_Pos 8 -#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ -#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) -#define GMAC_TI_NIT_Pos 16 -#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ -#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) -/* -------- GMAC_EFTS : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds -------- */ -#define GMAC_EFTS_RUD_Pos 0 -#define GMAC_EFTS_RUD_Msk (0xffffffffu << GMAC_EFTS_RUD_Pos) /**< \brief (GMAC_EFTS) Register Update */ -/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds -------- */ -#define GMAC_EFTN_RUD_Pos 0 -#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ -/* -------- GMAC_EFRS : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds -------- */ -#define GMAC_EFRS_RUD_Pos 0 -#define GMAC_EFRS_RUD_Msk (0xffffffffu << GMAC_EFRS_RUD_Pos) /**< \brief (GMAC_EFRS) Register Update */ -/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds -------- */ -#define GMAC_EFRN_RUD_Pos 0 -#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ -/* -------- GMAC_PEFTS : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds -------- */ -#define GMAC_PEFTS_RUD_Pos 0 -#define GMAC_PEFTS_RUD_Msk (0xffffffffu << GMAC_PEFTS_RUD_Pos) /**< \brief (GMAC_PEFTS) Register Update */ -/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds -------- */ -#define GMAC_PEFTN_RUD_Pos 0 -#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ -/* -------- GMAC_PEFRS : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds -------- */ -#define GMAC_PEFRS_RUD_Pos 0 -#define GMAC_PEFRS_RUD_Msk (0xffffffffu << GMAC_PEFRS_RUD_Pos) /**< \brief (GMAC_PEFRS) Register Update */ -/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds -------- */ -#define GMAC_PEFRN_RUD_Pos 0 -#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ - -/*@}*/ - - -#endif /* _SAM4E_GMAC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/gpbr.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/gpbr.h deleted file mode 100644 index c379442bf..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/gpbr.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_GPBR_COMPONENT_ -#define _SAM4E_GPBR_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup SAM4E_GPBR General Purpose Backup Register */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR[20]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ -} Gpbr; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- SYS_GPBR[20] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ -#define SYS_GPBR_GPBR_VALUE_Pos 0 -#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[20]) Value of GPBR x */ -#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) - -/*@}*/ - - -#endif /* _SAM4E_GPBR_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/hsmci.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/hsmci.h deleted file mode 100644 index a5b95d7b2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/hsmci.h +++ /dev/null @@ -1,395 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_HSMCI_COMPONENT_ -#define _SAM4E_HSMCI_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup SAM4E_HSMCI High Speed MultiMedia Card Interface */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RoReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RoReg Reserved2[1]; - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RoReg Reserved3[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ - RoReg Reserved4[5]; - RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ - RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ - RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ - RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ - RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ - RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ - RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ - RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ - WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ - RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ - RoReg Reserved5[54]; - RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ -} Hsmci; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV_Pos 0 -#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) -#define HSMCI_MR_PWSDIV_Pos 8 -#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) -#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ -#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ -#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC_Pos 0 -#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) -#define HSMCI_DTOR_DTOMUL_Pos 4 -#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ -#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ -#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ -#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ -#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ -#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ -#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ -#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL_Pos 0 -#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ -#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCBUS_Pos 6 -#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ -#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ -#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG_Pos 0 -#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ -#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB_Pos 0 -#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) -#define HSMCI_CMDR_RSPTYP_Pos 6 -#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ -#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ -#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ -#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ -#define HSMCI_CMDR_SPCMD_Pos 8 -#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ -#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ -#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ -#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ -#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ -#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ -#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ -#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ -#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ -#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ -#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ -#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ -#define HSMCI_CMDR_TRCMD_Pos 16 -#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ -#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ -#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ -#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ -#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ -#define HSMCI_CMDR_TRTYP_Pos 19 -#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ -#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ -#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ -#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ -#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ -#define HSMCI_CMDR_IOSPCMD_Pos 24 -#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ -#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ -#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ -#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ -#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT_Pos 0 -#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) -#define HSMCI_BLKR_BLKLEN_Pos 16 -#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ -#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC_Pos 0 -#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) -#define HSMCI_CSTOR_CSTOMUL_Pos 4 -#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ -#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ -#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ -#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ -#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ -#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ -#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ -#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP_Pos 0 -#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA_Pos 0 -#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA_Pos 0 -#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ -#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ -#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ -#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ -#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ -#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ -#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ -#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ -#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ -#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ -#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ -#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ -#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ -#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ -#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ -#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ -#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ -#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ -#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ -#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY_Pos 8 -#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos))) -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS_Pos 0 -#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */ -#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */ -#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */ -#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */ -#define HSMCI_WPSR_WP_VSRC_Pos 8 -#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ -/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ -#define HSMCI_RPR_RXPTR_Pos 0 -#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */ -#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos))) -/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ -#define HSMCI_RCR_RXCTR_Pos 0 -#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */ -#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos))) -/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ -#define HSMCI_TPR_TXPTR_Pos 0 -#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */ -#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos))) -/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ -#define HSMCI_TCR_TXCTR_Pos 0 -#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */ -#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos))) -/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ -#define HSMCI_RNPR_RXNPTR_Pos 0 -#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ -#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos))) -/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ -#define HSMCI_RNCR_RXNCTR_Pos 0 -#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */ -#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos))) -/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define HSMCI_TNPR_TXNPTR_Pos 0 -#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ -#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos))) -/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define HSMCI_TNCR_TXNCTR_Pos 0 -#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ -#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos))) -/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ -#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ -#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ -#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ -#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ -/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ -#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ -#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_HSMCI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/matrix.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/matrix.h deleted file mode 100644 index f14688aa4..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/matrix.h +++ /dev/null @@ -1,261 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_MATRIX_COMPONENT_ -#define _SAM4E_MATRIX_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup SAM4E_MATRIX Bus Matrix */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[7]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RoReg Reserved1[9]; - RwReg MATRIX_SCFG[6]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RoReg Reserved2[10]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RoReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RoReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RoReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RoReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RoReg Reserved7[1]; - RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */ - RoReg Reserved8[1]; - RoReg Reserved9[20]; - RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ - RoReg Reserved10[4]; - RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration Register */ - RoReg Reserved11[3]; - RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ - RoReg Reserved12[47]; - RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protect Mode Register */ - RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protect Status Register */ -} Matrix; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- MATRIX_MCFG[7] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT_Pos 0 -#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[7]) Undefined Length Burst Type */ -#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) -/* -------- MATRIX_SCFG[6] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 -#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[6]) Maximum Bus Grant Duration for Masters */ -#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) -#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 -#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[6]) Default Master Type */ -#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) -#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 -#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[6]) Fixed Default Master */ -#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR_Pos 0 -#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) -#define MATRIX_PRAS0_M1PR_Pos 4 -#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) -#define MATRIX_PRAS0_M2PR_Pos 8 -#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) -#define MATRIX_PRAS0_M3PR_Pos 12 -#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) -#define MATRIX_PRAS0_M4PR_Pos 16 -#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) -#define MATRIX_PRAS0_M5PR_Pos 20 -#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */ -#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos))) -#define MATRIX_PRAS0_M6PR_Pos 24 -#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos) /**< \brief (MATRIX_PRAS0) Master 6 Priority */ -#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos))) -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR_Pos 0 -#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) -#define MATRIX_PRAS1_M1PR_Pos 4 -#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) -#define MATRIX_PRAS1_M2PR_Pos 8 -#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) -#define MATRIX_PRAS1_M3PR_Pos 12 -#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) -#define MATRIX_PRAS1_M4PR_Pos 16 -#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) -#define MATRIX_PRAS1_M5PR_Pos 20 -#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */ -#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos))) -#define MATRIX_PRAS1_M6PR_Pos 24 -#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos) /**< \brief (MATRIX_PRAS1) Master 6 Priority */ -#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos))) -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR_Pos 0 -#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) -#define MATRIX_PRAS2_M1PR_Pos 4 -#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) -#define MATRIX_PRAS2_M2PR_Pos 8 -#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) -#define MATRIX_PRAS2_M3PR_Pos 12 -#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) -#define MATRIX_PRAS2_M4PR_Pos 16 -#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) -#define MATRIX_PRAS2_M5PR_Pos 20 -#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */ -#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos))) -#define MATRIX_PRAS2_M6PR_Pos 24 -#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos) /**< \brief (MATRIX_PRAS2) Master 6 Priority */ -#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos))) -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR_Pos 0 -#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) -#define MATRIX_PRAS3_M1PR_Pos 4 -#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) -#define MATRIX_PRAS3_M2PR_Pos 8 -#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) -#define MATRIX_PRAS3_M3PR_Pos 12 -#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) -#define MATRIX_PRAS3_M4PR_Pos 16 -#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) -#define MATRIX_PRAS3_M5PR_Pos 20 -#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */ -#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos))) -#define MATRIX_PRAS3_M6PR_Pos 24 -#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos) /**< \brief (MATRIX_PRAS3) Master 6 Priority */ -#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos))) -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR_Pos 0 -#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) -#define MATRIX_PRAS4_M1PR_Pos 4 -#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) -#define MATRIX_PRAS4_M2PR_Pos 8 -#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) -#define MATRIX_PRAS4_M3PR_Pos 12 -#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) -#define MATRIX_PRAS4_M4PR_Pos 16 -#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) -#define MATRIX_PRAS4_M5PR_Pos 20 -#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */ -#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos))) -#define MATRIX_PRAS4_M6PR_Pos 24 -#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos) /**< \brief (MATRIX_PRAS4) Master 6 Priority */ -#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos))) -/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */ -#define MATRIX_PRAS5_M0PR_Pos 0 -#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */ -#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos))) -#define MATRIX_PRAS5_M1PR_Pos 4 -#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */ -#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos))) -#define MATRIX_PRAS5_M2PR_Pos 8 -#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */ -#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos))) -#define MATRIX_PRAS5_M3PR_Pos 12 -#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */ -#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos))) -#define MATRIX_PRAS5_M4PR_Pos 16 -#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */ -#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos))) -#define MATRIX_PRAS5_M5PR_Pos 20 -#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */ -#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos))) -#define MATRIX_PRAS5_M6PR_Pos 24 -#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos) /**< \brief (MATRIX_PRAS5) Master 6 Priority */ -#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos))) -/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ -#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ -#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ -#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ -#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ -#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ -#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ -#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ -#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protect Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect Enable */ -#define MATRIX_WPMR_WPKEY_Pos 8 -#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ -#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protect Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ -#define MATRIX_WPSR_WPVSRC_Pos 8 -#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ - -/*@}*/ - - -#endif /* _SAM4E_MATRIX_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pdc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pdc.h deleted file mode 100644 index e2db44e7a..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pdc.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PDC_COMPONENT_ -#define _SAM4E_PDC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_PDC Peripheral DMA Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Pdc hardware registers */ -typedef struct { - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x00) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x04) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x08) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x0C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */ -} Pdc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- PERIPH_RPR : (PDC Offset: 0x00) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR_Pos 0 -#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) -/* -------- PERIPH_RCR : (PDC Offset: 0x04) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR_Pos 0 -#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */ -#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) -/* -------- PERIPH_TPR : (PDC Offset: 0x08) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR_Pos 0 -#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) -/* -------- PERIPH_TCR : (PDC Offset: 0x0C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR_Pos 0 -#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) -/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR_Pos 0 -#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) -/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR_Pos 0 -#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) -/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR_Pos 0 -#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) -/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR_Pos 0 -#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) -/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_PDC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pio.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pio.h deleted file mode 100644 index f60d41906..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pio.h +++ /dev/null @@ -1,1683 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PIO_COMPONENT_ -#define _SAM4E_PIO_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_PIO Parallel Input/Output Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RoReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RoReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RoReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RoReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RoReg Reserved5[1]; - RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - RoReg Reserved6[2]; - WoReg PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ - WoReg PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ - RoReg PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - RoReg Reserved7[1]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RoReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RoReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RoReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RoReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ - RoReg Reserved12[5]; - RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - RoReg Reserved13[3]; - RwReg PIO_DELAYR; /**< \brief (Pio Offset: 0x0110) IO Delay Register */ - RoReg Reserved14[15]; - RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ - WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ - WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ - RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ - RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ - RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ - RwReg PIO_RPR; /**< \brief (Pio Offset: 0x168) Receive Pointer Register */ - RwReg PIO_RCR; /**< \brief (Pio Offset: 0x16C) Receive Counter Register */ - RoReg Reserved15[2]; - RwReg PIO_RNPR; /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */ - RwReg PIO_RNCR; /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */ - RoReg Reserved16[2]; - WoReg PIO_PTCR; /**< \brief (Pio Offset: 0x188) Transfer Control Register */ - RoReg PIO_PTSR; /**< \brief (Pio Offset: 0x18C) Transfer Status Register */ -} Pio; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ -#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ -/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ -#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ -/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ -#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV_Pos 0 -#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY_Pos 8 -#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */ -#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC_Pos 8 -#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) */ -/* -------- PIO_DELAYR : (PIO Offset: 0x0110) IO Delay Register -------- */ -#define PIO_DELAYR_Delay0_Pos 0 -#define PIO_DELAYR_Delay0_Msk (0xfu << PIO_DELAYR_Delay0_Pos) /**< \brief (PIO_DELAYR) */ -#define PIO_DELAYR_Delay0(value) ((PIO_DELAYR_Delay0_Msk & ((value) << PIO_DELAYR_Delay0_Pos))) -#define PIO_DELAYR_Delay1_Pos 4 -#define PIO_DELAYR_Delay1_Msk (0xfu << PIO_DELAYR_Delay1_Pos) /**< \brief (PIO_DELAYR) */ -#define PIO_DELAYR_Delay1(value) ((PIO_DELAYR_Delay1_Msk & ((value) << PIO_DELAYR_Delay1_Pos))) -#define PIO_DELAYR_Delay2_Pos 8 -#define PIO_DELAYR_Delay2_Msk (0xfu << PIO_DELAYR_Delay2_Pos) /**< \brief (PIO_DELAYR) */ -#define PIO_DELAYR_Delay2(value) ((PIO_DELAYR_Delay2_Msk & ((value) << PIO_DELAYR_Delay2_Pos))) -#define PIO_DELAYR_Delay3_Pos 12 -#define PIO_DELAYR_Delay3_Msk (0xfu << PIO_DELAYR_Delay3_Pos) /**< \brief (PIO_DELAYR) */ -#define PIO_DELAYR_Delay3(value) ((PIO_DELAYR_Delay3_Msk & ((value) << PIO_DELAYR_Delay3_Pos))) -#define PIO_DELAYR_Delay4_Pos 16 -#define PIO_DELAYR_Delay4_Msk (0xfu << PIO_DELAYR_Delay4_Pos) /**< \brief (PIO_DELAYR) */ -#define PIO_DELAYR_Delay4(value) ((PIO_DELAYR_Delay4_Msk & ((value) << PIO_DELAYR_Delay4_Pos))) -#define PIO_DELAYR_Delay5_Pos 20 -#define PIO_DELAYR_Delay5_Msk (0xfu << PIO_DELAYR_Delay5_Pos) /**< \brief (PIO_DELAYR) */ -#define PIO_DELAYR_Delay5(value) ((PIO_DELAYR_Delay5_Msk & ((value) << PIO_DELAYR_Delay5_Pos))) -#define PIO_DELAYR_Delay6_Pos 24 -#define PIO_DELAYR_Delay6_Msk (0xfu << PIO_DELAYR_Delay6_Pos) /**< \brief (PIO_DELAYR) */ -#define PIO_DELAYR_Delay6(value) ((PIO_DELAYR_Delay6_Msk & ((value) << PIO_DELAYR_Delay6_Pos))) -#define PIO_DELAYR_Delay7_Pos 28 -#define PIO_DELAYR_Delay7_Msk (0xfu << PIO_DELAYR_Delay7_Pos) /**< \brief (PIO_DELAYR) */ -#define PIO_DELAYR_Delay7(value) ((PIO_DELAYR_Delay7_Msk & ((value) << PIO_DELAYR_Delay7_Pos))) -/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ -#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ -#define PIO_PCMR_DSIZE_Pos 4 -#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ -#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a BYTE (8-bit) */ -#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) */ -#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a WORD (32-bit) */ -#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ -#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ -#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ -/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ -#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ -#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ -#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ -#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ -/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ -#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ -#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ -#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ -#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ -/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ -#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ -#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ -#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ -#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ -/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ -#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ -#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ -#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ -#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ -/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ -#define PIO_PCRHR_RDATA_Pos 0 -#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ -/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */ -#define PIO_RPR_RXPTR_Pos 0 -#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */ -#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos))) -/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */ -#define PIO_RCR_RXCTR_Pos 0 -#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */ -#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos))) -/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */ -#define PIO_RNPR_RXNPTR_Pos 0 -#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */ -#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos))) -/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */ -#define PIO_RNCR_RXNCTR_Pos 0 -#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */ -#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos))) -/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */ -#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */ -#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */ -#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */ -#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */ -/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */ -#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */ -#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_PIO_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pmc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pmc.h deleted file mode 100644 index 10a2a10fa..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pmc.h +++ /dev/null @@ -1,413 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PMC_COMPONENT_ -#define _SAM4E_PMC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_PMC Power Management Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RoReg Reserved1[1]; - WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - RoReg Reserved2[1]; - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RwReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RoReg Reserved3[1]; - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RoReg Reserved4[1]; - RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - RoReg Reserved5[1]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RoReg Reserved6[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Start-up Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Start-up Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - RoReg Reserved7[26]; - RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ - RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RoReg Reserved8[5]; - WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - RoReg Reserved9[1]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ -} Pmc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ -#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ -#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF_Pos 4 -#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */ -#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */ -#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */ -#define CKGR_MOR_MOSCXTST_Pos 8 -#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) -#define CKGR_MOR_KEY_Pos 16 -#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) -#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF_Pos 0 -#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) -#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA_Pos 0 -#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) -#define CKGR_PLLAR_PLLACOUNT_Pos 8 -#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) -#define CKGR_PLLAR_MULA_Pos 16 -#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) -#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS_Pos 0 -#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_PRES_Pos 4 -#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ -#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBDIV_Pos 8 -#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ -#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS_Pos 0 -#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ -#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ -#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */ -#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ -#define PMC_PCK_PRES_Pos 4 -#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ -#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ -#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ -#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ -#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ -#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ -#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Start-up Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_FLPM_Pos 21 -#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low Power Mode */ -#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ -#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in deep power down mode when system enters Wait Mode */ -#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) idle mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Start-up Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ -#define PMC_WPMR_WPKEY_Pos 8 -#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */ -#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ -#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC_Pos 8 -#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL4_Pos 0 -#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ -#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) -#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ -#define PMC_OCR_CAL8_Pos 8 -#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ -#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) -#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ -#define PMC_OCR_CAL12_Pos 16 -#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ -#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) -#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ - -/*@}*/ - - -#endif /* _SAM4E_PMC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pwm.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pwm.h deleted file mode 100644 index 4a164d403..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/pwm.h +++ /dev/null @@ -1,612 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PWM_COMPONENT_ -#define _SAM4E_PWM_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief PwmCh_num_0x400 hardware registers */ -typedef struct { - RwReg PWM_CMUPD; /**< \brief (PwmCh_num_0x400 Offset: 0x0) PWM Channel Mode Update Register */ - RwReg PWM_CAE; /**< \brief (PwmCh_num_0x400 Offset: 0x4) PWM Channel Additional Edge Register */ - RwReg PWM_CAEUPD; /**< \brief (PwmCh_num_0x400 Offset: 0x8) PWM Channel Additional Edge Update Register */ - RoReg Reserved1[5]; -} PwmCh_num_0x400; -/** \brief PwmCmp hardware registers */ -typedef struct { - RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ - RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ - RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ -} PwmCmp; -/** \brief Pwm hardware registers */ -#define PWMCMP_NUMBER 8 -#define PWMCH_NUM_NUMBER 4 -#define PWMCH_NUM_0X400_NUMBER 4 -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RoReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RoReg Reserved2[3]; - RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RoReg Reserved3[7]; - RwReg PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ - WoReg PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ - RoReg Reserved4[2]; - RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ - RoReg Reserved5[3]; - RwReg PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ - RoReg Reserved6[8]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RoReg Reserved7[7]; - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RoReg Reserved8[2]; - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RoReg Reserved9[2]; - PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ - RoReg Reserved10[20]; - PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ - RoReg Reserved11[96]; - PwmCh_num_0x400 PWM_CH_NUM_0X400[PWMCH_NUM_0X400_NUMBER]; /**< \brief (Pwm Offset: 0x400) ch_num = 0 .. 3 */ -} Pwm; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA_Pos 0 -#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) -#define PWM_CLK_PREA_Pos 8 -#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) -#define PWM_CLK_DIVB_Pos 16 -#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) -#define PWM_CLK_PREB_Pos 24 -#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM_Pos 16 -#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ -#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ -#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */ -#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS_Pos 21 -#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR_Pos 0 -#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) -#define PWM_SCUP_UPRCNT_Pos 4 -#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ -#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD_Pos 0 -#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ -#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL_Pos 0 -#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 7) */ -#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) -#define PWM_FMR_FMOD_Pos 8 -#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 7) */ -#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) -#define PWM_FMR_FFIL_Pos 16 -#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 7) */ -#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV_Pos 0 -#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 7) */ -#define PWM_FSR_FS_Pos 8 -#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 7) */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR_Pos 0 -#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 7) */ -#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) -/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ -#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0_Pos 0 -#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 7) */ -#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) -#define PWM_FPE_FPE1_Pos 8 -#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 7) */ -#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) -#define PWM_FPE_FPE2_Pos 16 -#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 7) */ -#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) -#define PWM_FPE_FPE3_Pos 24 -#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 7) */ -#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) -/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ -#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ -#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ -#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ -#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ -#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ -#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ -#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ -/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ -#define PWM_SSPR_SPRD_Pos 0 -#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ -#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) -#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ -/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ -#define PWM_SSPUP_SPRDUP_Pos 0 -#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ -#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) -/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ -#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ -#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ -/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ -#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ -#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ -#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ -#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ -#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ -#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ -#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ -#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD_Pos 0 -#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) -#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY_Pos 8 -#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */ -#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC_Pos 16 -#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR_Pos 0 -#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */ -#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos))) -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR_Pos 0 -#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */ -#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos))) -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR_Pos 0 -#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos))) -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR_Pos 0 -#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */ -#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos))) -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ -#define PWM_CMPV_CV_Pos 0 -#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ -#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) -#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ -/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMPVUPD_CVUPD_Pos 0 -#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ -#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) -#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ -#define PWM_CMPM_CTR_Pos 4 -#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ -#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) -#define PWM_CMPM_CPR_Pos 8 -#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ -#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) -#define PWM_CMPM_CPRCNT_Pos 12 -#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ -#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) -#define PWM_CMPM_CUPR_Pos 16 -#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ -#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) -#define PWM_CMPM_CUPRCNT_Pos 20 -#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ -#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) -/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ -#define PWM_CMPMUPD_CTRUPD_Pos 4 -#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ -#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) -#define PWM_CMPMUPD_CPRUPD_Pos 8 -#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ -#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) -#define PWM_CMPMUPD_CUPRUPD_Pos 16 -#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ -#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) -/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ -#define PWM_CMR_CPRE_Pos 0 -#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ -#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */ -#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */ -#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */ -#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */ -#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */ -#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */ -#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */ -#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */ -#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */ -#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */ -#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */ -#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ -#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ -#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ -#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ -#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ -#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ -#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ -#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ -#define PWM_CDTY_CDTY_Pos 0 -#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ -#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) -/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ -#define PWM_CDTYUPD_CDTYUPD_Pos 0 -#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ -#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) -/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ -#define PWM_CPRD_CPRD_Pos 0 -#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ -#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) -/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ -#define PWM_CPRDUPD_CPRDUPD_Pos 0 -#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ -#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) -/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ -#define PWM_CCNT_CNT_Pos 0 -#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ -/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ -#define PWM_DT_DTH_Pos 0 -#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ -#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) -#define PWM_DT_DTL_Pos 16 -#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ -#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) -/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ -#define PWM_DTUPD_DTHUPD_Pos 0 -#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) -#define PWM_DTUPD_DTLUPD_Pos 16 -#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ -#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) -/* -------- PWM_CMUPD : (PWM Offset: N/A) PWM Channel Mode Update Register -------- */ -#define PWM_CMUPD_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD) Channel Polarity Update */ -#define PWM_CMUPD_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD) Channel Polarity Inversion Update */ -/* -------- PWM_CAE : (PWM Offset: N/A) PWM Channel Additional Edge Register -------- */ -#define PWM_CAE_ADEDGV_Pos 0 -#define PWM_CAE_ADEDGV_Msk (0xffffffu << PWM_CAE_ADEDGV_Pos) /**< \brief (PWM_CAE) Channel Additional Edge Value */ -#define PWM_CAE_ADEDGV(value) ((PWM_CAE_ADEDGV_Msk & ((value) << PWM_CAE_ADEDGV_Pos))) -#define PWM_CAE_ADEDGM_Pos 24 -#define PWM_CAE_ADEDGM_Msk (0x3u << PWM_CAE_ADEDGM_Pos) /**< \brief (PWM_CAE) Channel Additional Edge Mode */ -#define PWM_CAE_ADEDGM_INC (0x0u << 24) /**< \brief (PWM_CAE) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */ -#define PWM_CAE_ADEDGM_DEC (0x1u << 24) /**< \brief (PWM_CAE) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */ -#define PWM_CAE_ADEDGM_BOTH (0x2u << 24) /**< \brief (PWM_CAE) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV, whether the counter is incrementing or not. */ -/* -------- PWM_CAEUPD : (PWM Offset: N/A) PWM Channel Additional Edge Update Register -------- */ -#define PWM_CAEUPD_ADEDGVUP_Pos 0 -#define PWM_CAEUPD_ADEDGVUP_Msk (0xffffffu << PWM_CAEUPD_ADEDGVUP_Pos) /**< \brief (PWM_CAEUPD) Channel Additional Edge Value Update */ -#define PWM_CAEUPD_ADEDGVUP(value) ((PWM_CAEUPD_ADEDGVUP_Msk & ((value) << PWM_CAEUPD_ADEDGVUP_Pos))) -#define PWM_CAEUPD_ADEDGMUP_Pos 24 -#define PWM_CAEUPD_ADEDGMUP_Msk (0x3u << PWM_CAEUPD_ADEDGMUP_Pos) /**< \brief (PWM_CAEUPD) Channel Additional Edge Mode Update */ -#define PWM_CAEUPD_ADEDGMUP_INC (0x0u << 24) /**< \brief (PWM_CAEUPD) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */ -#define PWM_CAEUPD_ADEDGMUP_DEC (0x1u << 24) /**< \brief (PWM_CAEUPD) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */ -#define PWM_CAEUPD_ADEDGMUP_BOTH (0x2u << 24) /**< \brief (PWM_CAEUPD) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP, whether the counter is incrementing or not. */ - -/*@}*/ - - -#endif /* _SAM4E_PWM_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rstc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rstc.h deleted file mode 100644 index abc1b6350..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rstc.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_RSTC_COMPONENT_ -#define _SAM4E_RSTC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_RSTC Reset Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY_Pos 24 -#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ -#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP_Pos 8 -#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL_Pos 8 -#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) -#define RSTC_MR_KEY_Pos 24 -#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */ -#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) - -/*@}*/ - - -#endif /* _SAM4E_RSTC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rswdt.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rswdt.h deleted file mode 100644 index 2f728db10..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rswdt.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_RSWDT_COMPONENT_ -#define _SAM4E_RSWDT_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup SAM4E_RSWDT Reinforced Safety Watchdog Timer */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Rswdt hardware registers */ -typedef struct { - WoReg RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ - RwReg RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ - RoReg RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ -} Rswdt; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ -#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ -#define RSWDT_CR_KEY_Pos 24 -#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ -#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) -/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ -#define RSWDT_MR_WDV_Pos 0 -#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ -#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) -#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ -#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ -#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ -#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ -#define RSWDT_MR_WDD_Pos 16 -#define RSWDT_MR_WDD_Msk (0xfffu << RSWDT_MR_WDD_Pos) /**< \brief (RSWDT_MR) Watchdog Delta Value */ -#define RSWDT_MR_WDD(value) ((RSWDT_MR_WDD_Msk & ((value) << RSWDT_MR_WDD_Pos))) -#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ -#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ -/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ -#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ -#define RSWDT_SR_WDERR (0x1u << 1) /**< \brief (RSWDT_SR) Watchdog Error */ - -/*@}*/ - - -#endif /* _SAM4E_RSWDT_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rtc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rtc.h deleted file mode 100644 index 94d9303fa..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rtc.h +++ /dev/null @@ -1,231 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_RTC_COMPONENT_ -#define _SAM4E_RTC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup SAM4E_RTC Real-time Clock */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL_Pos 8 -#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ -#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ -#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ -#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ -#define RTC_CR_CALEVSEL_Pos 16 -#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ -#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ -#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ -#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ -#define RTC_MR_CORRECTION_Pos 8 -#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ -#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) -#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ -#define RTC_MR_OUT0_Pos 16 -#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ -#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */ -#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ -#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ -#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ -#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ -#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */ -#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */ -#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */ -#define RTC_MR_OUT1_Pos 20 -#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ -#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */ -#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ -#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ -#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ -#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ -#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */ -#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */ -#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */ -#define RTC_MR_THIGH_Pos 24 -#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ -#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ -#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ -#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 Mms */ -#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ -#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ -#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ -#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ -#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ -#define RTC_MR_TPERIOD_Pos 28 -#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ -#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ -#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ -#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ -#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC_Pos 0 -#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) -#define RTC_TIMR_MIN_Pos 8 -#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) -#define RTC_TIMR_HOUR_Pos 16 -#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) -#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT_Pos 0 -#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) -#define RTC_CALR_YEAR_Pos 8 -#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) -#define RTC_CALR_MONTH_Pos 16 -#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) -#define RTC_CALR_DAY_Pos 21 -#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) -#define RTC_CALR_DATE_Pos 24 -#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ -#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC_Pos 0 -#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) -#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN_Pos 8 -#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) -#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR_Pos 16 -#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) -#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH_Pos 16 -#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) -#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE_Pos 24 -#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) -#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ -#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ -#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ -#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ -#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ -#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ -#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ -#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ -#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ -#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ -#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ -#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ -#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of RTC_SR. */ -#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - - -#endif /* _SAM4E_RTC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rtt.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rtt.h deleted file mode 100644 index c22057a31..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/rtt.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_RTT_COMPONENT_ -#define _SAM4E_RTT_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup SAM4E_RTT Real-time Timer */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES_Pos 0 -#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) -#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ -#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV_Pos 0 -#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ -#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV_Pos 0 -#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - - -#endif /* _SAM4E_RTT_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/smc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/smc.h deleted file mode 100644 index 93dbf7510..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/smc.h +++ /dev/null @@ -1,151 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_SMC_COMPONENT_ -#define _SAM4E_SMC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_SMC Static Memory Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -#define SMCCS_NUMBER_NUMBER 4 -typedef struct { - SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ - RoReg Reserved1[16]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ - RoReg Reserved2[22]; - RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ -} Smc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ -#define SMC_SETUP_NWE_SETUP_Pos 0 -#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ -#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) -#define SMC_SETUP_NCS_WR_SETUP_Pos 8 -#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ -#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) -#define SMC_SETUP_NRD_SETUP_Pos 16 -#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ -#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) -#define SMC_SETUP_NCS_RD_SETUP_Pos 24 -#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ -#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) -/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ -#define SMC_PULSE_NWE_PULSE_Pos 0 -#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ -#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) -#define SMC_PULSE_NCS_WR_PULSE_Pos 8 -#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) -#define SMC_PULSE_NRD_PULSE_Pos 16 -#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ -#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) -#define SMC_PULSE_NCS_RD_PULSE_Pos 24 -#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ -#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) -/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ -#define SMC_CYCLE_NWE_CYCLE_Pos 0 -#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ -#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) -#define SMC_CYCLE_NRD_CYCLE_Pos 16 -#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ -#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) -/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */ -#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */ -#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */ -#define SMC_MODE_EXNW_MODE_Pos 4 -#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ -#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ -#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ -#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ -#define SMC_MODE_TDF_CYCLES_Pos 16 -#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ -#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) -#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ -#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ -#define SMC_MODE_PS_Pos 28 -#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ -#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ -#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ -#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ -#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ -/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ -#define SMC_KEY1_KEY1_Pos 0 -#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) -/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ -#define SMC_KEY2_KEY2_Pos 0 -#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) -/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ -#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ -#define SMC_WPMR_WPKEY_Pos 8 -#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */ -#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) -/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ -#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ -#define SMC_WPSR_WPVSRC_Pos 8 -#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */ - -/*@}*/ - - -#endif /* _SAM4E_SMC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/spi.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/spi.h deleted file mode 100644 index e42695864..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/spi.h +++ /dev/null @@ -1,238 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_SPI_COMPONENT_ -#define _SAM4E_SPI_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup SAM4E_SPI Serial Peripheral Interface */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RoReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RoReg Reserved2[41]; - RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ - RoReg Reserved3[5]; - RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS_Pos 16 -#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) -#define SPI_MR_DLYBCS_Pos 24 -#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ -#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD_Pos 0 -#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS_Pos 16 -#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD_Pos 0 -#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) -#define SPI_TDR_PCS_Pos 16 -#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) -#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */ -#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */ -#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */ -#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */ -#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ -#define SPI_CSR_BITS_Pos 4 -#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ -#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ -#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ -#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ -#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ -#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ -#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ -#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ -#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ -#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ -#define SPI_CSR_SCBR_Pos 8 -#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) -#define SPI_CSR_DLYBS_Pos 16 -#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) -#define SPI_CSR_DLYBCT_Pos 24 -#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) -/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ -#define SPI_WPMR_WPKEY_Pos 8 -#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */ -#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ -#define SPI_WPSR_WPVSRC_Pos 8 -#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR_Pos 0 -#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */ -#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos))) -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR_Pos 0 -#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */ -#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos))) -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR_Pos 0 -#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */ -#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos))) -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR_Pos 0 -#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */ -#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos))) -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR_Pos 0 -#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */ -#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos))) -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR_Pos 0 -#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */ -#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos))) -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR_Pos 0 -#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos))) -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR_Pos 0 -#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */ -#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos))) -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_SPI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/supc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/supc.h deleted file mode 100644 index 903ab9c8c..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/supc.h +++ /dev/null @@ -1,336 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_SUPC_COMPONENT_ -#define _SAM4E_SUPC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup SAM4E_SUPC Supply Controller */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY_Pos 24 -#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ -#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH_Pos 0 -#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) -#define SUPC_SMMR_SMSMPL_Pos 8 -#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ -#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used) */ -#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) internal voltage regulator is used */ -#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY_Pos 24 -#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ -#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ -#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake-up Enable */ -#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake-up pin has no wake-up effect. */ -#define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake-up pin low forces the wake-up of the core power supply. */ -#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake-up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake-up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake-up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake-up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake-up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake-up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake-up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake-up of the core power supply. */ -#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */ -#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */ -#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force a core wake-up. */ -#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */ -#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */ -#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force a core wake-up. */ -#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */ -#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on first half GPBR registers. */ -#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. */ -#define SUPC_WUMR_FWUPDBC_Pos 8 -#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake-up Debouncer Period */ -#define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_Pos 12 -#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ -#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ -#define SUPC_WUMR_LPDBC_Pos 16 -#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */ -#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */ -#define SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */ -#define SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */ -#define SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */ -#define SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */ -#define SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */ -#define SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */ -#define SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake-up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake-up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 */ -#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 1 */ -#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 2 */ -#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 3 */ -#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 4 */ -#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 5 */ -#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 6 */ -#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 7 */ -#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 8 */ -#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 9 */ -#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 10 */ -#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 11 */ -#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 12 */ -#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 13 */ -#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake-up Input Type 14 */ -#define SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake-up Input Type 15 */ -#define SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake-up Status */ -#define SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status */ -#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status */ -#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */ -#define SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */ -#define SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */ -#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake-up Status on WKUP0 */ -#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake-up Status on WKUP1 */ -#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ - -/*@}*/ - - -#endif /* _SAM4E_SUPC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/tc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/tc.h deleted file mode 100644 index 6f7e607df..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/tc.h +++ /dev/null @@ -1,383 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_TC_COMPONENT_ -#define _SAM4E_TC_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup SAM4E_TC Timer Counter */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ - RwReg TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ - RoReg Reserved1[3]; -} TcChannel; -/** \brief TcPdc hardware registers */ -typedef struct { - RwReg TC_RPR; /**< \brief (TcPdc Offset: 0x0) Receive Pointer Register */ - RwReg TC_RCR; /**< \brief (TcPdc Offset: 0x4) Receive Counter Register */ - RoReg Reserved2[2]; - RwReg TC_RNPR; /**< \brief (TcPdc Offset: 0x10) Receive Next Pointer Register */ - RwReg TC_RNCR; /**< \brief (TcPdc Offset: 0x14) Receive Next Counter Register */ - RoReg Reserved3[2]; - RwReg TC_PTCR; /**< \brief (TcPdc Offset: 0x20) Transfer Control Register */ - RwReg TC_PTSR; /**< \brief (TcPdc Offset: 0x24) Transfer Status Register */ - RoReg Reserved4[6]; -} TcPdc; -/** \brief Tc hardware registers */ -#define TCCHANNEL_NUMBER 3 -#define TCPDC_NUMBER 3 -typedef struct { - TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ - RoReg Reserved1[2]; - RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ - RoReg Reserved2[6]; - TcPdc TC_PDC[TCPDC_NUMBER]; /**< \brief (Tc Offset: 0x100) pdc = 0 .. 2 */ -} Tc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ -#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ -#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ -#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ -/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ -#define TC_CMR_TCCLKS_Pos 0 -#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ -#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */ -#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */ -#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */ -#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */ -#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */ -#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ -#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ -#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ -#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ -#define TC_CMR_BURST_Pos 4 -#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ -#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ -#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ -#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ -#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ -#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ -#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ -#define TC_CMR_ETRGEDG_Pos 8 -#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ -#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ -#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ -#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ -#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ -#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ -#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ -#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ -#define TC_CMR_LDRA_Pos 16 -#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ -#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ -#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ -#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ -#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ -#define TC_CMR_LDRB_Pos 18 -#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ -#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ -#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ -#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ -#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ -#define TC_CMR_SBSMPLR_Pos 20 -#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ -#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ -#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ -#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ -#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ -#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ -#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ -#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ -#define TC_CMR_EEVTEDG_Pos 8 -#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ -#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ -#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ -#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ -#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ -#define TC_CMR_EEVT_Pos 10 -#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ -#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ -#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ -#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ -#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ -#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ -#define TC_CMR_WAVSEL_Pos 13 -#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ -#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ -#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ -#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ -#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ -#define TC_CMR_ACPA_Pos 16 -#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ -#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ -#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ -#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_ACPC_Pos 18 -#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ -#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ -#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ -#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_AEEVT_Pos 20 -#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ -#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ -#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ -#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_ASWTRG_Pos 22 -#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ -#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ -#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ -#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_BCPB_Pos 24 -#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ -#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ -#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ -#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_BCPC_Pos 26 -#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ -#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ -#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ -#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_BEEVT_Pos 28 -#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ -#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ -#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ -#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ -#define TC_CMR_BSWTRG_Pos 30 -#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ -#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ -#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ -#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ -#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ -/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ -#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ -#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */ -/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ -#define TC_RAB_RAB_Pos 0 -#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ -/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ -#define TC_CV_CV_Pos 0 -#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ -/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ -#define TC_RA_RA_Pos 0 -#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ -#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) -/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ -#define TC_RB_RB_Pos 0 -#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ -#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) -/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ -#define TC_RC_RC_Pos 0 -#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ -#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) -/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ -#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */ -#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */ -#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */ -#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */ -#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */ -#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */ -#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */ -#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */ -#define TC_SR_ENDRX (0x1u << 8) /**< \brief (TC_SR) End of Receiver Transfer */ -#define TC_SR_RXBUFF (0x1u << 9) /**< \brief (TC_SR) Reception Buffer Full */ -#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ -#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ -#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ -/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ -#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ -#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ -#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ -#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ -#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ -#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ -#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ -#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ -#define TC_IER_ENDRX (0x1u << 8) /**< \brief (TC_IER) End of Receiver Transfer */ -#define TC_IER_RXBUFF (0x1u << 9) /**< \brief (TC_IER) Reception Buffer Full */ -/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ -#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ -#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ -#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ -#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ -#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ -#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ -#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ -#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ -#define TC_IDR_ENDRX (0x1u << 8) /**< \brief (TC_IDR) End of Receiver Transfer */ -#define TC_IDR_RXBUFF (0x1u << 9) /**< \brief (TC_IDR) Reception Buffer Full */ -/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ -#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ -#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ -#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ -#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ -#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ -#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ -#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ -#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ -#define TC_IMR_ENDRX (0x1u << 8) /**< \brief (TC_IMR) End of Receiver Transfer */ -#define TC_IMR_RXBUFF (0x1u << 9) /**< \brief (TC_IMR) Reception Buffer Full */ -/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ -#define TC_EMR_TRIGSRCA_Pos 0 -#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) TRIGger SouRCe for input A */ -#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) the trigger/capture input A is driven by external pin TIOAx */ -#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) the trigger/capture input A is driven internally by PWMx */ -#define TC_EMR_TRIGSRCB_Pos 4 -#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) TRIGger SouRCe for input B */ -#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) the trigger/capture input B is driven by external pin TIOBx */ -#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) the trigger/capture input B is driven internally by PWMx */ -#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) NO DIVided CLocK */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S_Pos 0 -#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ -#define TC_BMR_TC1XC1S_Pos 2 -#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ -#define TC_BMR_TC2XC2S_Pos 4 -#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ -#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */ -#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT_Pos 20 -#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */ -#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */ -/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ -#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ -#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ -#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */ -#define TC_WPMR_WPKEY_Pos 8 -#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */ -#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) -/* -------- TC_RPR : (TC Offset: N/A) Receive Pointer Register -------- */ -#define TC_RPR_RXPTR_Pos 0 -#define TC_RPR_RXPTR_Msk (0xffffffffu << TC_RPR_RXPTR_Pos) /**< \brief (TC_RPR) Receive Pointer Register */ -#define TC_RPR_RXPTR(value) ((TC_RPR_RXPTR_Msk & ((value) << TC_RPR_RXPTR_Pos))) -/* -------- TC_RCR : (TC Offset: N/A) Receive Counter Register -------- */ -#define TC_RCR_RXCTR_Pos 0 -#define TC_RCR_RXCTR_Msk (0xffffu << TC_RCR_RXCTR_Pos) /**< \brief (TC_RCR) Receive Counter Register */ -#define TC_RCR_RXCTR(value) ((TC_RCR_RXCTR_Msk & ((value) << TC_RCR_RXCTR_Pos))) -/* -------- TC_RNPR : (TC Offset: N/A) Receive Next Pointer Register -------- */ -#define TC_RNPR_RXNPTR_Pos 0 -#define TC_RNPR_RXNPTR_Msk (0xffffffffu << TC_RNPR_RXNPTR_Pos) /**< \brief (TC_RNPR) Receive Next Pointer */ -#define TC_RNPR_RXNPTR(value) ((TC_RNPR_RXNPTR_Msk & ((value) << TC_RNPR_RXNPTR_Pos))) -/* -------- TC_RNCR : (TC Offset: N/A) Receive Next Counter Register -------- */ -#define TC_RNCR_RXNCTR_Pos 0 -#define TC_RNCR_RXNCTR_Msk (0xffffu << TC_RNCR_RXNCTR_Pos) /**< \brief (TC_RNCR) Receive Next Counter */ -#define TC_RNCR_RXNCTR(value) ((TC_RNCR_RXNCTR_Msk & ((value) << TC_RNCR_RXNCTR_Pos))) -/* -------- TC_PTCR : (TC Offset: N/A) Transfer Control Register -------- */ -#define TC_PTCR_RXTEN (0x1u << 0) /**< \brief (TC_PTCR) Receiver Transfer Enable */ -#define TC_PTCR_RXTDIS (0x1u << 1) /**< \brief (TC_PTCR) Receiver Transfer Disable */ -#define TC_PTCR_TXTEN (0x1u << 8) /**< \brief (TC_PTCR) Transmitter Transfer Enable */ -#define TC_PTCR_TXTDIS (0x1u << 9) /**< \brief (TC_PTCR) Transmitter Transfer Disable */ -/* -------- TC_PTSR : (TC Offset: N/A) Transfer Status Register -------- */ -#define TC_PTSR_RXTEN (0x1u << 0) /**< \brief (TC_PTSR) Receiver Transfer Enable */ -#define TC_PTSR_TXTEN (0x1u << 8) /**< \brief (TC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_TC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/twi.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/twi.h deleted file mode 100644 index f340cad05..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/twi.h +++ /dev/null @@ -1,241 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_TWI_COMPONENT_ -#define _SAM4E_TWI_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup SAM4E_TWI Two-wire Interface */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RoReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RoReg Reserved2[43]; - RwReg TWI_WPROT_MODE; /**< \brief (Twi Offset: 0xE4) Protection Mode Register */ - RoReg TWI_WPROT_STATUS; /**< \brief (Twi Offset: 0xE8) Protection Status Register */ - RoReg Reserved3[5]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ_Pos 8 -#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR_Pos 16 -#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ -#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR_Pos 16 -#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ -#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR_Pos 0 -#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ -#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV_Pos 0 -#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) -#define TWI_CWGR_CHDIV_Pos 8 -#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) -#define TWI_CWGR_CKDIV_Pos 16 -#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ -#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA_Pos 0 -#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA_Pos 0 -#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) -/* -------- TWI_WPROT_MODE : (TWI Offset: 0xE4) Protection Mode Register -------- */ -#define TWI_WPROT_MODE_WPROT (0x1u << 0) /**< \brief (TWI_WPROT_MODE) Write protection bit */ -#define TWI_WPROT_MODE_SECURITY_CODE_Pos 8 -#define TWI_WPROT_MODE_SECURITY_CODE_Msk (0xffffffu << TWI_WPROT_MODE_SECURITY_CODE_Pos) /**< \brief (TWI_WPROT_MODE) Write protection mode security code */ -#define TWI_WPROT_MODE_SECURITY_CODE(value) ((TWI_WPROT_MODE_SECURITY_CODE_Msk & ((value) << TWI_WPROT_MODE_SECURITY_CODE_Pos))) -/* -------- TWI_WPROT_STATUS : (TWI Offset: 0xE8) Protection Status Register -------- */ -#define TWI_WPROT_STATUS_WPROTERR (0x1u << 0) /**< \brief (TWI_WPROT_STATUS) Write Protection Error */ -#define TWI_WPROT_STATUS_WPROTADDR_Pos 8 -#define TWI_WPROT_STATUS_WPROTADDR_Msk (0xffffffu << TWI_WPROT_STATUS_WPROTADDR_Pos) /**< \brief (TWI_WPROT_STATUS) Write Protection Error Address */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR_Pos 0 -#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */ -#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR_Pos 0 -#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */ -#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR_Pos 0 -#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */ -#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR_Pos 0 -#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */ -#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR_Pos 0 -#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */ -#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR_Pos 0 -#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */ -#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR_Pos 0 -#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR_Pos 0 -#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */ -#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_TWI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/uart.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/uart.h deleted file mode 100644 index 663624fe2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/uart.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_UART_COMPONENT_ -#define _SAM4E_UART_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup SAM4E_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RoReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR_Pos 9 -#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ -#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ -#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ -#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ -#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No Parity */ -#define UART_MR_CHMODE_Pos 14 -#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ -#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */ -#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */ -#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */ -#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR_Pos 0 -#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR_Pos 0 -#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ -#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD_Pos 0 -#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ -#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR_Pos 0 -#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */ -#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos))) -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR_Pos 0 -#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */ -#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos))) -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR_Pos 0 -#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */ -#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos))) -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR_Pos 0 -#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */ -#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos))) -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR_Pos 0 -#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */ -#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos))) -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR_Pos 0 -#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */ -#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos))) -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR_Pos 0 -#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */ -#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos))) -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR_Pos 0 -#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */ -#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos))) -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_UART_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/udp.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/udp.h deleted file mode 100644 index e7928061f..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/udp.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_UDP_COMPONENT_ -#define _SAM4E_UDP_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup SAM4E_UDP USB Device Port */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Udp hardware registers */ -typedef struct { - RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - RoReg Reserved1[1]; - WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - RoReg Reserved2[1]; - RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - RoReg Reserved3[1]; - RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */ - RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */ - RoReg Reserved4[1]; - RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM_Pos 0 -#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD_Pos 0 -#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos))) -#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ -#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ -#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ -#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ -#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ -#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ -#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ -#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ -#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ -/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */ -#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */ -#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent */ -#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE_Pos 8 -#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT_Pos 16 -#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ -#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos))) -#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) A CRC error has been detected in an isochronous transfer */ -/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */ -#define UDP_FDR_FIFO_DATA_Pos 0 -#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */ -#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos))) -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pull-up On */ - -/*@}*/ - - -#endif /* _SAM4E_UDP_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/usart.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/usart.h deleted file mode 100644 index 159142e94..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/usart.h +++ /dev/null @@ -1,368 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_USART_COMPONENT_ -#define _SAM4E_USART_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup SAM4E_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RoReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RoReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RoReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RoReg Reserved4[5]; - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ -#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ -#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */ -#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */ -#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ -#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE_Pos 0 -#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ -#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ -#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ -#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ -#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ -#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ -#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ -#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ -#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */ -#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ -#define US_MR_USCLKS_Pos 4 -#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */ -#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */ -#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */ -#define US_MR_CHRL_Pos 6 -#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */ -#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ -#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ -#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ -#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ -#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ -#define US_MR_PAR_Pos 9 -#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ -#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ -#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ -#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ -#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ -#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ -#define US_MR_NBSTOP_Pos 12 -#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ -#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ -#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ -#define US_MR_CHMODE_Pos 14 -#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */ -#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ -#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ -#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ -#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ -#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ -#define US_MR_MAX_ITERATION_Pos 24 -#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ -#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) -#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ -#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ -#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ -#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation) */ -#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation) */ -#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ -#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation) */ -#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation) */ -#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */ -#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ -#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ -#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ -#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation) */ -#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation) */ -#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ -#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ -#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation) */ -#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation) */ -#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */ -#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ -#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ -#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ -#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation) */ -#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation) */ -#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ -#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation) */ -#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation) */ -#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */ -#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ -#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ -#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ -#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) MaxNumber of Repetitions Reached */ -#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */ -#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ -#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ -#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ -#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ -#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ -#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ -#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */ -#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR_Pos 0 -#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR_Pos 0 -#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) -#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD_Pos 0 -#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) -#define US_BRGR_FP_Pos 16 -#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ -#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO_Pos 0 -#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ -#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG_Pos 0 -#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ -#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO_Pos 0 -#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS_Pos 0 -#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER_Pos 0 -#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ -#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL_Pos 0 -#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) -#define US_MAN_TX_PP_Pos 8 -#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ -#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ -#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ -#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ -#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL_Pos 16 -#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) -#define US_MAN_RX_PP_Pos 24 -#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ -#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ -#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ -#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ -#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ -#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY_Pos 8 -#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */ -#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC_Pos 8 -#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR_Pos 0 -#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */ -#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos))) -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR_Pos 0 -#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */ -#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos))) -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR_Pos 0 -#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */ -#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos))) -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR_Pos 0 -#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */ -#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos))) -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR_Pos 0 -#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */ -#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos))) -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR_Pos 0 -#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */ -#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos))) -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR_Pos 0 -#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */ -#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos))) -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR_Pos 0 -#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */ -#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos))) -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - - -#endif /* _SAM4E_USART_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/wdt.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/wdt.h deleted file mode 100644 index 3933e331e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/component/wdt.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_WDT_COMPONENT_ -#define _SAM4E_WDT_COMPONENT_ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup SAM4E_WDT Watchdog Timer */ -/*@{*/ - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY_Pos 24 -#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ -#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV_Pos 0 -#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) -#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD_Pos 16 -#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) -#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - - -#endif /* _SAM4E_WDT_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/acc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/acc.h deleted file mode 100644 index 4e67ce412..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/acc.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_ACC_INSTANCE_ -#define _SAM4E_ACC_INSTANCE_ - -/* ========== Register definition for ACC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_ACC_CR (0x400BC000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR (0x400BC004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER (0x400BC024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR (0x400BC028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR (0x400BC02CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR (0x400BC030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR (0x400BC094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR (0x400BC0E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR (0x400BC0E8U) /**< \brief (ACC) Write Protect Status Register */ -#else -#define REG_ACC_CR (*(WoReg*)0x400BC000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR (*(RwReg*)0x400BC004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER (*(WoReg*)0x400BC024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR (*(WoReg*)0x400BC028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR (*(RoReg*)0x400BC02CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR (*(RoReg*)0x400BC030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR (*(RwReg*)0x400BC094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR (*(RwReg*)0x400BC0E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR (*(RoReg*)0x400BC0E8U) /**< \brief (ACC) Write Protect Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_ACC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/aes.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/aes.h deleted file mode 100644 index dd1d459a8..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/aes.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_AES_INSTANCE_ -#define _SAM4E_AES_INSTANCE_ - -/* ========== Register definition for AES peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AES_CR (0x40004000U) /**< \brief (AES) Control Register */ -#define REG_AES_MR (0x40004004U) /**< \brief (AES) Mode Register */ -#define REG_AES_IER (0x40004010U) /**< \brief (AES) Interrupt Enable Register */ -#define REG_AES_IDR (0x40004014U) /**< \brief (AES) Interrupt Disable Register */ -#define REG_AES_IMR (0x40004018U) /**< \brief (AES) Interrupt Mask Register */ -#define REG_AES_ISR (0x4000401CU) /**< \brief (AES) Interrupt Status Register */ -#define REG_AES_KEYWR (0x40004020U) /**< \brief (AES) Key Word Register */ -#define REG_AES_IDATAR (0x40004040U) /**< \brief (AES) Input Data Register */ -#define REG_AES_ODATAR (0x40004050U) /**< \brief (AES) Output Data Register */ -#define REG_AES_IVR (0x40004060U) /**< \brief (AES) Initialization Vector Register */ -#else -#define REG_AES_CR (*(WoReg*)0x40004000U) /**< \brief (AES) Control Register */ -#define REG_AES_MR (*(RwReg*)0x40004004U) /**< \brief (AES) Mode Register */ -#define REG_AES_IER (*(WoReg*)0x40004010U) /**< \brief (AES) Interrupt Enable Register */ -#define REG_AES_IDR (*(WoReg*)0x40004014U) /**< \brief (AES) Interrupt Disable Register */ -#define REG_AES_IMR (*(RoReg*)0x40004018U) /**< \brief (AES) Interrupt Mask Register */ -#define REG_AES_ISR (*(RoReg*)0x4000401CU) /**< \brief (AES) Interrupt Status Register */ -#define REG_AES_KEYWR (*(WoReg*)0x40004020U) /**< \brief (AES) Key Word Register */ -#define REG_AES_IDATAR (*(WoReg*)0x40004040U) /**< \brief (AES) Input Data Register */ -#define REG_AES_ODATAR (*(RoReg*)0x40004050U) /**< \brief (AES) Output Data Register */ -#define REG_AES_IVR (*(WoReg*)0x40004060U) /**< \brief (AES) Initialization Vector Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_AES_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/afec0.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/afec0.h deleted file mode 100644 index 3f6116c74..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/afec0.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_AFEC0_INSTANCE_ -#define _SAM4E_AFEC0_INSTANCE_ - -/* ========== Register definition for AFEC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AFEC0_CR (0x400B0000U) /**< \brief (AFEC0) Control Register */ -#define REG_AFEC0_MR (0x400B0004U) /**< \brief (AFEC0) Mode Register */ -#define REG_AFEC0_EMR (0x400B0008U) /**< \brief (AFEC0) Extended Mode Register */ -#define REG_AFEC0_SEQ1R (0x400B000CU) /**< \brief (AFEC0) Channel Sequence 1 Register */ -#define REG_AFEC0_SEQ2R (0x400B0010U) /**< \brief (AFEC0) Channel Sequence 2 Register */ -#define REG_AFEC0_CHER (0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */ -#define REG_AFEC0_CHDR (0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */ -#define REG_AFEC0_CHSR (0x400B001CU) /**< \brief (AFEC0) Channel Status Register */ -#define REG_AFEC0_LCDR (0x400B0020U) /**< \brief (AFEC0) Last Converted Data Register */ -#define REG_AFEC0_IER (0x400B0024U) /**< \brief (AFEC0) Interrupt Enable Register */ -#define REG_AFEC0_IDR (0x400B0028U) /**< \brief (AFEC0) Interrupt Disable Register */ -#define REG_AFEC0_IMR (0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */ -#define REG_AFEC0_ISR (0x400B0030U) /**< \brief (AFEC0) Interrupt Status Register */ -#define REG_AFEC0_OVER (0x400B004CU) /**< \brief (AFEC0) Overrun Status Register */ -#define REG_AFEC0_CWR (0x400B0050U) /**< \brief (AFEC0) Compare Window Register */ -#define REG_AFEC0_CGR (0x400B0054U) /**< \brief (AFEC0) Channel Gain Register */ -#define REG_AFEC0_CDOR (0x400B005CU) /**< \brief (AFEC0) Channel Calibration DC Offset Register */ -#define REG_AFEC0_DIFFR (0x400B0060U) /**< \brief (AFEC0) Channel Differential Register */ -#define REG_AFEC0_CSELR (0x400B0064U) /**< \brief (AFEC0) Channel Register Selection */ -#define REG_AFEC0_CDR (0x400B0068U) /**< \brief (AFEC0) Channel Data Register */ -#define REG_AFEC0_COCR (0x400B006CU) /**< \brief (AFEC0) Channel Offset Compensation Register */ -#define REG_AFEC0_TEMPMR (0x400B0070U) /**< \brief (AFEC0) Temperature Sensor Mode Register */ -#define REG_AFEC0_TEMPCWR (0x400B0074U) /**< \brief (AFEC0) Temperature Compare Window Register */ -#define REG_AFEC0_ACR (0x400B0094U) /**< \brief (AFEC0) Analog Control Register */ -#define REG_AFEC0_WPMR (0x400B00E4U) /**< \brief (AFEC0) Write Protect Mode Register */ -#define REG_AFEC0_WPSR (0x400B00E8U) /**< \brief (AFEC0) Write Protect Status Register */ -#define REG_AFEC0_RPR (0x400B0100U) /**< \brief (AFEC0) Receive Pointer Register */ -#define REG_AFEC0_RCR (0x400B0104U) /**< \brief (AFEC0) Receive Counter Register */ -#define REG_AFEC0_RNPR (0x400B0110U) /**< \brief (AFEC0) Receive Next Pointer Register */ -#define REG_AFEC0_RNCR (0x400B0114U) /**< \brief (AFEC0) Receive Next Counter Register */ -#define REG_AFEC0_PTCR (0x400B0120U) /**< \brief (AFEC0) Transfer Control Register */ -#define REG_AFEC0_PTSR (0x400B0124U) /**< \brief (AFEC0) Transfer Status Register */ -#else -#define REG_AFEC0_CR (*(WoReg*)0x400B0000U) /**< \brief (AFEC0) Control Register */ -#define REG_AFEC0_MR (*(RwReg*)0x400B0004U) /**< \brief (AFEC0) Mode Register */ -#define REG_AFEC0_EMR (*(RwReg*)0x400B0008U) /**< \brief (AFEC0) Extended Mode Register */ -#define REG_AFEC0_SEQ1R (*(RwReg*)0x400B000CU) /**< \brief (AFEC0) Channel Sequence 1 Register */ -#define REG_AFEC0_SEQ2R (*(RwReg*)0x400B0010U) /**< \brief (AFEC0) Channel Sequence 2 Register */ -#define REG_AFEC0_CHER (*(WoReg*)0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */ -#define REG_AFEC0_CHDR (*(WoReg*)0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */ -#define REG_AFEC0_CHSR (*(RoReg*)0x400B001CU) /**< \brief (AFEC0) Channel Status Register */ -#define REG_AFEC0_LCDR (*(RoReg*)0x400B0020U) /**< \brief (AFEC0) Last Converted Data Register */ -#define REG_AFEC0_IER (*(WoReg*)0x400B0024U) /**< \brief (AFEC0) Interrupt Enable Register */ -#define REG_AFEC0_IDR (*(WoReg*)0x400B0028U) /**< \brief (AFEC0) Interrupt Disable Register */ -#define REG_AFEC0_IMR (*(RoReg*)0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */ -#define REG_AFEC0_ISR (*(RoReg*)0x400B0030U) /**< \brief (AFEC0) Interrupt Status Register */ -#define REG_AFEC0_OVER (*(RoReg*)0x400B004CU) /**< \brief (AFEC0) Overrun Status Register */ -#define REG_AFEC0_CWR (*(RwReg*)0x400B0050U) /**< \brief (AFEC0) Compare Window Register */ -#define REG_AFEC0_CGR (*(RwReg*)0x400B0054U) /**< \brief (AFEC0) Channel Gain Register */ -#define REG_AFEC0_CDOR (*(RwReg*)0x400B005CU) /**< \brief (AFEC0) Channel Calibration DC Offset Register */ -#define REG_AFEC0_DIFFR (*(RwReg*)0x400B0060U) /**< \brief (AFEC0) Channel Differential Register */ -#define REG_AFEC0_CSELR (*(RwReg*)0x400B0064U) /**< \brief (AFEC0) Channel Register Selection */ -#define REG_AFEC0_CDR (*(RoReg*)0x400B0068U) /**< \brief (AFEC0) Channel Data Register */ -#define REG_AFEC0_COCR (*(RwReg*)0x400B006CU) /**< \brief (AFEC0) Channel Offset Compensation Register */ -#define REG_AFEC0_TEMPMR (*(RwReg*)0x400B0070U) /**< \brief (AFEC0) Temperature Sensor Mode Register */ -#define REG_AFEC0_TEMPCWR (*(RwReg*)0x400B0074U) /**< \brief (AFEC0) Temperature Compare Window Register */ -#define REG_AFEC0_ACR (*(RwReg*)0x400B0094U) /**< \brief (AFEC0) Analog Control Register */ -#define REG_AFEC0_WPMR (*(RwReg*)0x400B00E4U) /**< \brief (AFEC0) Write Protect Mode Register */ -#define REG_AFEC0_WPSR (*(RoReg*)0x400B00E8U) /**< \brief (AFEC0) Write Protect Status Register */ -#define REG_AFEC0_RPR (*(RwReg*)0x400B0100U) /**< \brief (AFEC0) Receive Pointer Register */ -#define REG_AFEC0_RCR (*(RwReg*)0x400B0104U) /**< \brief (AFEC0) Receive Counter Register */ -#define REG_AFEC0_RNPR (*(RwReg*)0x400B0110U) /**< \brief (AFEC0) Receive Next Pointer Register */ -#define REG_AFEC0_RNCR (*(RwReg*)0x400B0114U) /**< \brief (AFEC0) Receive Next Counter Register */ -#define REG_AFEC0_PTCR (*(WoReg*)0x400B0120U) /**< \brief (AFEC0) Transfer Control Register */ -#define REG_AFEC0_PTSR (*(RoReg*)0x400B0124U) /**< \brief (AFEC0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_AFEC0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/afec1.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/afec1.h deleted file mode 100644 index cc9dfb049..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/afec1.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_AFEC1_INSTANCE_ -#define _SAM4E_AFEC1_INSTANCE_ - -/* ========== Register definition for AFEC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AFEC1_CR (0x400B4000U) /**< \brief (AFEC1) Control Register */ -#define REG_AFEC1_MR (0x400B4004U) /**< \brief (AFEC1) Mode Register */ -#define REG_AFEC1_EMR (0x400B4008U) /**< \brief (AFEC1) Extended Mode Register */ -#define REG_AFEC1_SEQ1R (0x400B400CU) /**< \brief (AFEC1) Channel Sequence 1 Register */ -#define REG_AFEC1_SEQ2R (0x400B4010U) /**< \brief (AFEC1) Channel Sequence 2 Register */ -#define REG_AFEC1_CHER (0x400B4014U) /**< \brief (AFEC1) Channel Enable Register */ -#define REG_AFEC1_CHDR (0x400B4018U) /**< \brief (AFEC1) Channel Disable Register */ -#define REG_AFEC1_CHSR (0x400B401CU) /**< \brief (AFEC1) Channel Status Register */ -#define REG_AFEC1_LCDR (0x400B4020U) /**< \brief (AFEC1) Last Converted Data Register */ -#define REG_AFEC1_IER (0x400B4024U) /**< \brief (AFEC1) Interrupt Enable Register */ -#define REG_AFEC1_IDR (0x400B4028U) /**< \brief (AFEC1) Interrupt Disable Register */ -#define REG_AFEC1_IMR (0x400B402CU) /**< \brief (AFEC1) Interrupt Mask Register */ -#define REG_AFEC1_ISR (0x400B4030U) /**< \brief (AFEC1) Interrupt Status Register */ -#define REG_AFEC1_OVER (0x400B404CU) /**< \brief (AFEC1) Overrun Status Register */ -#define REG_AFEC1_CWR (0x400B4050U) /**< \brief (AFEC1) Compare Window Register */ -#define REG_AFEC1_CGR (0x400B4054U) /**< \brief (AFEC1) Channel Gain Register */ -#define REG_AFEC1_CDOR (0x400B405CU) /**< \brief (AFEC1) Channel Calibration DC Offset Register */ -#define REG_AFEC1_DIFFR (0x400B4060U) /**< \brief (AFEC1) Channel Differential Register */ -#define REG_AFEC1_CSELR (0x400B4064U) /**< \brief (AFEC1) Channel Register Selection */ -#define REG_AFEC1_CDR (0x400B4068U) /**< \brief (AFEC1) Channel Data Register */ -#define REG_AFEC1_COCR (0x400B406CU) /**< \brief (AFEC1) Channel Offset Compensation Register */ -#define REG_AFEC1_TEMPMR (0x400B4070U) /**< \brief (AFEC1) Temperature Sensor Mode Register */ -#define REG_AFEC1_TEMPCWR (0x400B4074U) /**< \brief (AFEC1) Temperature Compare Window Register */ -#define REG_AFEC1_ACR (0x400B4094U) /**< \brief (AFEC1) Analog Control Register */ -#define REG_AFEC1_WPMR (0x400B40E4U) /**< \brief (AFEC1) Write Protect Mode Register */ -#define REG_AFEC1_WPSR (0x400B40E8U) /**< \brief (AFEC1) Write Protect Status Register */ -#define REG_AFEC1_RPR (0x400B4100U) /**< \brief (AFEC1) Receive Pointer Register */ -#define REG_AFEC1_RCR (0x400B4104U) /**< \brief (AFEC1) Receive Counter Register */ -#define REG_AFEC1_RNPR (0x400B4110U) /**< \brief (AFEC1) Receive Next Pointer Register */ -#define REG_AFEC1_RNCR (0x400B4114U) /**< \brief (AFEC1) Receive Next Counter Register */ -#define REG_AFEC1_PTCR (0x400B4120U) /**< \brief (AFEC1) Transfer Control Register */ -#define REG_AFEC1_PTSR (0x400B4124U) /**< \brief (AFEC1) Transfer Status Register */ -#else -#define REG_AFEC1_CR (*(WoReg*)0x400B4000U) /**< \brief (AFEC1) Control Register */ -#define REG_AFEC1_MR (*(RwReg*)0x400B4004U) /**< \brief (AFEC1) Mode Register */ -#define REG_AFEC1_EMR (*(RwReg*)0x400B4008U) /**< \brief (AFEC1) Extended Mode Register */ -#define REG_AFEC1_SEQ1R (*(RwReg*)0x400B400CU) /**< \brief (AFEC1) Channel Sequence 1 Register */ -#define REG_AFEC1_SEQ2R (*(RwReg*)0x400B4010U) /**< \brief (AFEC1) Channel Sequence 2 Register */ -#define REG_AFEC1_CHER (*(WoReg*)0x400B4014U) /**< \brief (AFEC1) Channel Enable Register */ -#define REG_AFEC1_CHDR (*(WoReg*)0x400B4018U) /**< \brief (AFEC1) Channel Disable Register */ -#define REG_AFEC1_CHSR (*(RoReg*)0x400B401CU) /**< \brief (AFEC1) Channel Status Register */ -#define REG_AFEC1_LCDR (*(RoReg*)0x400B4020U) /**< \brief (AFEC1) Last Converted Data Register */ -#define REG_AFEC1_IER (*(WoReg*)0x400B4024U) /**< \brief (AFEC1) Interrupt Enable Register */ -#define REG_AFEC1_IDR (*(WoReg*)0x400B4028U) /**< \brief (AFEC1) Interrupt Disable Register */ -#define REG_AFEC1_IMR (*(RoReg*)0x400B402CU) /**< \brief (AFEC1) Interrupt Mask Register */ -#define REG_AFEC1_ISR (*(RoReg*)0x400B4030U) /**< \brief (AFEC1) Interrupt Status Register */ -#define REG_AFEC1_OVER (*(RoReg*)0x400B404CU) /**< \brief (AFEC1) Overrun Status Register */ -#define REG_AFEC1_CWR (*(RwReg*)0x400B4050U) /**< \brief (AFEC1) Compare Window Register */ -#define REG_AFEC1_CGR (*(RwReg*)0x400B4054U) /**< \brief (AFEC1) Channel Gain Register */ -#define REG_AFEC1_CDOR (*(RwReg*)0x400B405CU) /**< \brief (AFEC1) Channel Calibration DC Offset Register */ -#define REG_AFEC1_DIFFR (*(RwReg*)0x400B4060U) /**< \brief (AFEC1) Channel Differential Register */ -#define REG_AFEC1_CSELR (*(RwReg*)0x400B4064U) /**< \brief (AFEC1) Channel Register Selection */ -#define REG_AFEC1_CDR (*(RoReg*)0x400B4068U) /**< \brief (AFEC1) Channel Data Register */ -#define REG_AFEC1_COCR (*(RwReg*)0x400B406CU) /**< \brief (AFEC1) Channel Offset Compensation Register */ -#define REG_AFEC1_TEMPMR (*(RwReg*)0x400B4070U) /**< \brief (AFEC1) Temperature Sensor Mode Register */ -#define REG_AFEC1_TEMPCWR (*(RwReg*)0x400B4074U) /**< \brief (AFEC1) Temperature Compare Window Register */ -#define REG_AFEC1_ACR (*(RwReg*)0x400B4094U) /**< \brief (AFEC1) Analog Control Register */ -#define REG_AFEC1_WPMR (*(RwReg*)0x400B40E4U) /**< \brief (AFEC1) Write Protect Mode Register */ -#define REG_AFEC1_WPSR (*(RoReg*)0x400B40E8U) /**< \brief (AFEC1) Write Protect Status Register */ -#define REG_AFEC1_RPR (*(RwReg*)0x400B4100U) /**< \brief (AFEC1) Receive Pointer Register */ -#define REG_AFEC1_RCR (*(RwReg*)0x400B4104U) /**< \brief (AFEC1) Receive Counter Register */ -#define REG_AFEC1_RNPR (*(RwReg*)0x400B4110U) /**< \brief (AFEC1) Receive Next Pointer Register */ -#define REG_AFEC1_RNCR (*(RwReg*)0x400B4114U) /**< \brief (AFEC1) Receive Next Counter Register */ -#define REG_AFEC1_PTCR (*(WoReg*)0x400B4120U) /**< \brief (AFEC1) Transfer Control Register */ -#define REG_AFEC1_PTSR (*(RoReg*)0x400B4124U) /**< \brief (AFEC1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_AFEC1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/can0.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/can0.h deleted file mode 100644 index c90bc95b8..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/can0.h +++ /dev/null @@ -1,204 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CAN0_INSTANCE_ -#define _SAM4E_CAN0_INSTANCE_ - -/* ========== Register definition for CAN0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CAN0_MR (0x40010000U) /**< \brief (CAN0) Mode Register */ -#define REG_CAN0_IER (0x40010004U) /**< \brief (CAN0) Interrupt Enable Register */ -#define REG_CAN0_IDR (0x40010008U) /**< \brief (CAN0) Interrupt Disable Register */ -#define REG_CAN0_IMR (0x4001000CU) /**< \brief (CAN0) Interrupt Mask Register */ -#define REG_CAN0_SR (0x40010010U) /**< \brief (CAN0) Status Register */ -#define REG_CAN0_BR (0x40010014U) /**< \brief (CAN0) Baudrate Register */ -#define REG_CAN0_TIM (0x40010018U) /**< \brief (CAN0) Timer Register */ -#define REG_CAN0_TIMESTP (0x4001001CU) /**< \brief (CAN0) Timestamp Register */ -#define REG_CAN0_ECR (0x40010020U) /**< \brief (CAN0) Error Counter Register */ -#define REG_CAN0_TCR (0x40010024U) /**< \brief (CAN0) Transfer Command Register */ -#define REG_CAN0_ACR (0x40010028U) /**< \brief (CAN0) Abort Command Register */ -#define REG_CAN0_WPMR (0x400100E4U) /**< \brief (CAN0) Write Protect Mode Register */ -#define REG_CAN0_WPSR (0x400100E8U) /**< \brief (CAN0) Write Protect Status Register */ -#define REG_CAN0_MMR0 (0x40010200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ -#define REG_CAN0_MAM0 (0x40010204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ -#define REG_CAN0_MID0 (0x40010208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ -#define REG_CAN0_MFID0 (0x4001020CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ -#define REG_CAN0_MSR0 (0x40010210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ -#define REG_CAN0_MDL0 (0x40010214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ -#define REG_CAN0_MDH0 (0x40010218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ -#define REG_CAN0_MCR0 (0x4001021CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ -#define REG_CAN0_MMR1 (0x40010220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ -#define REG_CAN0_MAM1 (0x40010224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ -#define REG_CAN0_MID1 (0x40010228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ -#define REG_CAN0_MFID1 (0x4001022CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ -#define REG_CAN0_MSR1 (0x40010230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ -#define REG_CAN0_MDL1 (0x40010234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ -#define REG_CAN0_MDH1 (0x40010238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ -#define REG_CAN0_MCR1 (0x4001023CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ -#define REG_CAN0_MMR2 (0x40010240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ -#define REG_CAN0_MAM2 (0x40010244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ -#define REG_CAN0_MID2 (0x40010248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ -#define REG_CAN0_MFID2 (0x4001024CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ -#define REG_CAN0_MSR2 (0x40010250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ -#define REG_CAN0_MDL2 (0x40010254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ -#define REG_CAN0_MDH2 (0x40010258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ -#define REG_CAN0_MCR2 (0x4001025CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ -#define REG_CAN0_MMR3 (0x40010260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ -#define REG_CAN0_MAM3 (0x40010264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ -#define REG_CAN0_MID3 (0x40010268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ -#define REG_CAN0_MFID3 (0x4001026CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ -#define REG_CAN0_MSR3 (0x40010270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ -#define REG_CAN0_MDL3 (0x40010274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ -#define REG_CAN0_MDH3 (0x40010278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ -#define REG_CAN0_MCR3 (0x4001027CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ -#define REG_CAN0_MMR4 (0x40010280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ -#define REG_CAN0_MAM4 (0x40010284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ -#define REG_CAN0_MID4 (0x40010288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ -#define REG_CAN0_MFID4 (0x4001028CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ -#define REG_CAN0_MSR4 (0x40010290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ -#define REG_CAN0_MDL4 (0x40010294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ -#define REG_CAN0_MDH4 (0x40010298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ -#define REG_CAN0_MCR4 (0x4001029CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ -#define REG_CAN0_MMR5 (0x400102A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ -#define REG_CAN0_MAM5 (0x400102A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ -#define REG_CAN0_MID5 (0x400102A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ -#define REG_CAN0_MFID5 (0x400102ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ -#define REG_CAN0_MSR5 (0x400102B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ -#define REG_CAN0_MDL5 (0x400102B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ -#define REG_CAN0_MDH5 (0x400102B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ -#define REG_CAN0_MCR5 (0x400102BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ -#define REG_CAN0_MMR6 (0x400102C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ -#define REG_CAN0_MAM6 (0x400102C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ -#define REG_CAN0_MID6 (0x400102C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ -#define REG_CAN0_MFID6 (0x400102CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ -#define REG_CAN0_MSR6 (0x400102D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ -#define REG_CAN0_MDL6 (0x400102D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ -#define REG_CAN0_MDH6 (0x400102D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ -#define REG_CAN0_MCR6 (0x400102DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ -#define REG_CAN0_MMR7 (0x400102E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ -#define REG_CAN0_MAM7 (0x400102E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ -#define REG_CAN0_MID7 (0x400102E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ -#define REG_CAN0_MFID7 (0x400102ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ -#define REG_CAN0_MSR7 (0x400102F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ -#define REG_CAN0_MDL7 (0x400102F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ -#define REG_CAN0_MDH7 (0x400102F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ -#define REG_CAN0_MCR7 (0x400102FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ -#else -#define REG_CAN0_MR (*(RwReg*)0x40010000U) /**< \brief (CAN0) Mode Register */ -#define REG_CAN0_IER (*(WoReg*)0x40010004U) /**< \brief (CAN0) Interrupt Enable Register */ -#define REG_CAN0_IDR (*(WoReg*)0x40010008U) /**< \brief (CAN0) Interrupt Disable Register */ -#define REG_CAN0_IMR (*(RoReg*)0x4001000CU) /**< \brief (CAN0) Interrupt Mask Register */ -#define REG_CAN0_SR (*(RoReg*)0x40010010U) /**< \brief (CAN0) Status Register */ -#define REG_CAN0_BR (*(RwReg*)0x40010014U) /**< \brief (CAN0) Baudrate Register */ -#define REG_CAN0_TIM (*(RoReg*)0x40010018U) /**< \brief (CAN0) Timer Register */ -#define REG_CAN0_TIMESTP (*(RoReg*)0x4001001CU) /**< \brief (CAN0) Timestamp Register */ -#define REG_CAN0_ECR (*(RoReg*)0x40010020U) /**< \brief (CAN0) Error Counter Register */ -#define REG_CAN0_TCR (*(WoReg*)0x40010024U) /**< \brief (CAN0) Transfer Command Register */ -#define REG_CAN0_ACR (*(WoReg*)0x40010028U) /**< \brief (CAN0) Abort Command Register */ -#define REG_CAN0_WPMR (*(RwReg*)0x400100E4U) /**< \brief (CAN0) Write Protect Mode Register */ -#define REG_CAN0_WPSR (*(RoReg*)0x400100E8U) /**< \brief (CAN0) Write Protect Status Register */ -#define REG_CAN0_MMR0 (*(RwReg*)0x40010200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ -#define REG_CAN0_MAM0 (*(RwReg*)0x40010204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ -#define REG_CAN0_MID0 (*(RwReg*)0x40010208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ -#define REG_CAN0_MFID0 (*(RoReg*)0x4001020CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ -#define REG_CAN0_MSR0 (*(RoReg*)0x40010210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ -#define REG_CAN0_MDL0 (*(RwReg*)0x40010214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ -#define REG_CAN0_MDH0 (*(RwReg*)0x40010218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ -#define REG_CAN0_MCR0 (*(WoReg*)0x4001021CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ -#define REG_CAN0_MMR1 (*(RwReg*)0x40010220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ -#define REG_CAN0_MAM1 (*(RwReg*)0x40010224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ -#define REG_CAN0_MID1 (*(RwReg*)0x40010228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ -#define REG_CAN0_MFID1 (*(RoReg*)0x4001022CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ -#define REG_CAN0_MSR1 (*(RoReg*)0x40010230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ -#define REG_CAN0_MDL1 (*(RwReg*)0x40010234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ -#define REG_CAN0_MDH1 (*(RwReg*)0x40010238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ -#define REG_CAN0_MCR1 (*(WoReg*)0x4001023CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ -#define REG_CAN0_MMR2 (*(RwReg*)0x40010240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ -#define REG_CAN0_MAM2 (*(RwReg*)0x40010244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ -#define REG_CAN0_MID2 (*(RwReg*)0x40010248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ -#define REG_CAN0_MFID2 (*(RoReg*)0x4001024CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ -#define REG_CAN0_MSR2 (*(RoReg*)0x40010250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ -#define REG_CAN0_MDL2 (*(RwReg*)0x40010254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ -#define REG_CAN0_MDH2 (*(RwReg*)0x40010258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ -#define REG_CAN0_MCR2 (*(WoReg*)0x4001025CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ -#define REG_CAN0_MMR3 (*(RwReg*)0x40010260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ -#define REG_CAN0_MAM3 (*(RwReg*)0x40010264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ -#define REG_CAN0_MID3 (*(RwReg*)0x40010268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ -#define REG_CAN0_MFID3 (*(RoReg*)0x4001026CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ -#define REG_CAN0_MSR3 (*(RoReg*)0x40010270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ -#define REG_CAN0_MDL3 (*(RwReg*)0x40010274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ -#define REG_CAN0_MDH3 (*(RwReg*)0x40010278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ -#define REG_CAN0_MCR3 (*(WoReg*)0x4001027CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ -#define REG_CAN0_MMR4 (*(RwReg*)0x40010280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ -#define REG_CAN0_MAM4 (*(RwReg*)0x40010284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ -#define REG_CAN0_MID4 (*(RwReg*)0x40010288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ -#define REG_CAN0_MFID4 (*(RoReg*)0x4001028CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ -#define REG_CAN0_MSR4 (*(RoReg*)0x40010290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ -#define REG_CAN0_MDL4 (*(RwReg*)0x40010294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ -#define REG_CAN0_MDH4 (*(RwReg*)0x40010298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ -#define REG_CAN0_MCR4 (*(WoReg*)0x4001029CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ -#define REG_CAN0_MMR5 (*(RwReg*)0x400102A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ -#define REG_CAN0_MAM5 (*(RwReg*)0x400102A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ -#define REG_CAN0_MID5 (*(RwReg*)0x400102A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ -#define REG_CAN0_MFID5 (*(RoReg*)0x400102ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ -#define REG_CAN0_MSR5 (*(RoReg*)0x400102B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ -#define REG_CAN0_MDL5 (*(RwReg*)0x400102B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ -#define REG_CAN0_MDH5 (*(RwReg*)0x400102B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ -#define REG_CAN0_MCR5 (*(WoReg*)0x400102BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ -#define REG_CAN0_MMR6 (*(RwReg*)0x400102C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ -#define REG_CAN0_MAM6 (*(RwReg*)0x400102C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ -#define REG_CAN0_MID6 (*(RwReg*)0x400102C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ -#define REG_CAN0_MFID6 (*(RoReg*)0x400102CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ -#define REG_CAN0_MSR6 (*(RoReg*)0x400102D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ -#define REG_CAN0_MDL6 (*(RwReg*)0x400102D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ -#define REG_CAN0_MDH6 (*(RwReg*)0x400102D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ -#define REG_CAN0_MCR6 (*(WoReg*)0x400102DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ -#define REG_CAN0_MMR7 (*(RwReg*)0x400102E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ -#define REG_CAN0_MAM7 (*(RwReg*)0x400102E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ -#define REG_CAN0_MID7 (*(RwReg*)0x400102E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ -#define REG_CAN0_MFID7 (*(RoReg*)0x400102ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ -#define REG_CAN0_MSR7 (*(RoReg*)0x400102F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ -#define REG_CAN0_MDL7 (*(RwReg*)0x400102F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ -#define REG_CAN0_MDH7 (*(RwReg*)0x400102F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ -#define REG_CAN0_MCR7 (*(WoReg*)0x400102FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_CAN0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/can1.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/can1.h deleted file mode 100644 index df97b2be9..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/can1.h +++ /dev/null @@ -1,204 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CAN1_INSTANCE_ -#define _SAM4E_CAN1_INSTANCE_ - -/* ========== Register definition for CAN1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CAN1_MR (0x40014000U) /**< \brief (CAN1) Mode Register */ -#define REG_CAN1_IER (0x40014004U) /**< \brief (CAN1) Interrupt Enable Register */ -#define REG_CAN1_IDR (0x40014008U) /**< \brief (CAN1) Interrupt Disable Register */ -#define REG_CAN1_IMR (0x4001400CU) /**< \brief (CAN1) Interrupt Mask Register */ -#define REG_CAN1_SR (0x40014010U) /**< \brief (CAN1) Status Register */ -#define REG_CAN1_BR (0x40014014U) /**< \brief (CAN1) Baudrate Register */ -#define REG_CAN1_TIM (0x40014018U) /**< \brief (CAN1) Timer Register */ -#define REG_CAN1_TIMESTP (0x4001401CU) /**< \brief (CAN1) Timestamp Register */ -#define REG_CAN1_ECR (0x40014020U) /**< \brief (CAN1) Error Counter Register */ -#define REG_CAN1_TCR (0x40014024U) /**< \brief (CAN1) Transfer Command Register */ -#define REG_CAN1_ACR (0x40014028U) /**< \brief (CAN1) Abort Command Register */ -#define REG_CAN1_WPMR (0x400140E4U) /**< \brief (CAN1) Write Protect Mode Register */ -#define REG_CAN1_WPSR (0x400140E8U) /**< \brief (CAN1) Write Protect Status Register */ -#define REG_CAN1_MMR0 (0x40014200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ -#define REG_CAN1_MAM0 (0x40014204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ -#define REG_CAN1_MID0 (0x40014208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ -#define REG_CAN1_MFID0 (0x4001420CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ -#define REG_CAN1_MSR0 (0x40014210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ -#define REG_CAN1_MDL0 (0x40014214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ -#define REG_CAN1_MDH0 (0x40014218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ -#define REG_CAN1_MCR0 (0x4001421CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ -#define REG_CAN1_MMR1 (0x40014220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ -#define REG_CAN1_MAM1 (0x40014224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ -#define REG_CAN1_MID1 (0x40014228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ -#define REG_CAN1_MFID1 (0x4001422CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ -#define REG_CAN1_MSR1 (0x40014230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ -#define REG_CAN1_MDL1 (0x40014234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ -#define REG_CAN1_MDH1 (0x40014238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ -#define REG_CAN1_MCR1 (0x4001423CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ -#define REG_CAN1_MMR2 (0x40014240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ -#define REG_CAN1_MAM2 (0x40014244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ -#define REG_CAN1_MID2 (0x40014248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ -#define REG_CAN1_MFID2 (0x4001424CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ -#define REG_CAN1_MSR2 (0x40014250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ -#define REG_CAN1_MDL2 (0x40014254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ -#define REG_CAN1_MDH2 (0x40014258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ -#define REG_CAN1_MCR2 (0x4001425CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ -#define REG_CAN1_MMR3 (0x40014260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ -#define REG_CAN1_MAM3 (0x40014264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ -#define REG_CAN1_MID3 (0x40014268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ -#define REG_CAN1_MFID3 (0x4001426CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ -#define REG_CAN1_MSR3 (0x40014270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ -#define REG_CAN1_MDL3 (0x40014274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ -#define REG_CAN1_MDH3 (0x40014278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ -#define REG_CAN1_MCR3 (0x4001427CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ -#define REG_CAN1_MMR4 (0x40014280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ -#define REG_CAN1_MAM4 (0x40014284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ -#define REG_CAN1_MID4 (0x40014288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ -#define REG_CAN1_MFID4 (0x4001428CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ -#define REG_CAN1_MSR4 (0x40014290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ -#define REG_CAN1_MDL4 (0x40014294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ -#define REG_CAN1_MDH4 (0x40014298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ -#define REG_CAN1_MCR4 (0x4001429CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ -#define REG_CAN1_MMR5 (0x400142A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ -#define REG_CAN1_MAM5 (0x400142A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ -#define REG_CAN1_MID5 (0x400142A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ -#define REG_CAN1_MFID5 (0x400142ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ -#define REG_CAN1_MSR5 (0x400142B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ -#define REG_CAN1_MDL5 (0x400142B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ -#define REG_CAN1_MDH5 (0x400142B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ -#define REG_CAN1_MCR5 (0x400142BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ -#define REG_CAN1_MMR6 (0x400142C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ -#define REG_CAN1_MAM6 (0x400142C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ -#define REG_CAN1_MID6 (0x400142C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ -#define REG_CAN1_MFID6 (0x400142CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ -#define REG_CAN1_MSR6 (0x400142D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ -#define REG_CAN1_MDL6 (0x400142D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ -#define REG_CAN1_MDH6 (0x400142D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ -#define REG_CAN1_MCR6 (0x400142DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ -#define REG_CAN1_MMR7 (0x400142E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ -#define REG_CAN1_MAM7 (0x400142E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ -#define REG_CAN1_MID7 (0x400142E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ -#define REG_CAN1_MFID7 (0x400142ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ -#define REG_CAN1_MSR7 (0x400142F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ -#define REG_CAN1_MDL7 (0x400142F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ -#define REG_CAN1_MDH7 (0x400142F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ -#define REG_CAN1_MCR7 (0x400142FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ -#else -#define REG_CAN1_MR (*(RwReg*)0x40014000U) /**< \brief (CAN1) Mode Register */ -#define REG_CAN1_IER (*(WoReg*)0x40014004U) /**< \brief (CAN1) Interrupt Enable Register */ -#define REG_CAN1_IDR (*(WoReg*)0x40014008U) /**< \brief (CAN1) Interrupt Disable Register */ -#define REG_CAN1_IMR (*(RoReg*)0x4001400CU) /**< \brief (CAN1) Interrupt Mask Register */ -#define REG_CAN1_SR (*(RoReg*)0x40014010U) /**< \brief (CAN1) Status Register */ -#define REG_CAN1_BR (*(RwReg*)0x40014014U) /**< \brief (CAN1) Baudrate Register */ -#define REG_CAN1_TIM (*(RoReg*)0x40014018U) /**< \brief (CAN1) Timer Register */ -#define REG_CAN1_TIMESTP (*(RoReg*)0x4001401CU) /**< \brief (CAN1) Timestamp Register */ -#define REG_CAN1_ECR (*(RoReg*)0x40014020U) /**< \brief (CAN1) Error Counter Register */ -#define REG_CAN1_TCR (*(WoReg*)0x40014024U) /**< \brief (CAN1) Transfer Command Register */ -#define REG_CAN1_ACR (*(WoReg*)0x40014028U) /**< \brief (CAN1) Abort Command Register */ -#define REG_CAN1_WPMR (*(RwReg*)0x400140E4U) /**< \brief (CAN1) Write Protect Mode Register */ -#define REG_CAN1_WPSR (*(RoReg*)0x400140E8U) /**< \brief (CAN1) Write Protect Status Register */ -#define REG_CAN1_MMR0 (*(RwReg*)0x40014200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ -#define REG_CAN1_MAM0 (*(RwReg*)0x40014204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ -#define REG_CAN1_MID0 (*(RwReg*)0x40014208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ -#define REG_CAN1_MFID0 (*(RoReg*)0x4001420CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ -#define REG_CAN1_MSR0 (*(RoReg*)0x40014210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ -#define REG_CAN1_MDL0 (*(RwReg*)0x40014214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ -#define REG_CAN1_MDH0 (*(RwReg*)0x40014218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ -#define REG_CAN1_MCR0 (*(WoReg*)0x4001421CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ -#define REG_CAN1_MMR1 (*(RwReg*)0x40014220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ -#define REG_CAN1_MAM1 (*(RwReg*)0x40014224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ -#define REG_CAN1_MID1 (*(RwReg*)0x40014228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ -#define REG_CAN1_MFID1 (*(RoReg*)0x4001422CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ -#define REG_CAN1_MSR1 (*(RoReg*)0x40014230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ -#define REG_CAN1_MDL1 (*(RwReg*)0x40014234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ -#define REG_CAN1_MDH1 (*(RwReg*)0x40014238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ -#define REG_CAN1_MCR1 (*(WoReg*)0x4001423CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ -#define REG_CAN1_MMR2 (*(RwReg*)0x40014240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ -#define REG_CAN1_MAM2 (*(RwReg*)0x40014244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ -#define REG_CAN1_MID2 (*(RwReg*)0x40014248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ -#define REG_CAN1_MFID2 (*(RoReg*)0x4001424CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ -#define REG_CAN1_MSR2 (*(RoReg*)0x40014250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ -#define REG_CAN1_MDL2 (*(RwReg*)0x40014254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ -#define REG_CAN1_MDH2 (*(RwReg*)0x40014258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ -#define REG_CAN1_MCR2 (*(WoReg*)0x4001425CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ -#define REG_CAN1_MMR3 (*(RwReg*)0x40014260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ -#define REG_CAN1_MAM3 (*(RwReg*)0x40014264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ -#define REG_CAN1_MID3 (*(RwReg*)0x40014268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ -#define REG_CAN1_MFID3 (*(RoReg*)0x4001426CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ -#define REG_CAN1_MSR3 (*(RoReg*)0x40014270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ -#define REG_CAN1_MDL3 (*(RwReg*)0x40014274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ -#define REG_CAN1_MDH3 (*(RwReg*)0x40014278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ -#define REG_CAN1_MCR3 (*(WoReg*)0x4001427CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ -#define REG_CAN1_MMR4 (*(RwReg*)0x40014280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ -#define REG_CAN1_MAM4 (*(RwReg*)0x40014284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ -#define REG_CAN1_MID4 (*(RwReg*)0x40014288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ -#define REG_CAN1_MFID4 (*(RoReg*)0x4001428CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ -#define REG_CAN1_MSR4 (*(RoReg*)0x40014290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ -#define REG_CAN1_MDL4 (*(RwReg*)0x40014294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ -#define REG_CAN1_MDH4 (*(RwReg*)0x40014298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ -#define REG_CAN1_MCR4 (*(WoReg*)0x4001429CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ -#define REG_CAN1_MMR5 (*(RwReg*)0x400142A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ -#define REG_CAN1_MAM5 (*(RwReg*)0x400142A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ -#define REG_CAN1_MID5 (*(RwReg*)0x400142A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ -#define REG_CAN1_MFID5 (*(RoReg*)0x400142ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ -#define REG_CAN1_MSR5 (*(RoReg*)0x400142B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ -#define REG_CAN1_MDL5 (*(RwReg*)0x400142B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ -#define REG_CAN1_MDH5 (*(RwReg*)0x400142B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ -#define REG_CAN1_MCR5 (*(WoReg*)0x400142BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ -#define REG_CAN1_MMR6 (*(RwReg*)0x400142C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ -#define REG_CAN1_MAM6 (*(RwReg*)0x400142C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ -#define REG_CAN1_MID6 (*(RwReg*)0x400142C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ -#define REG_CAN1_MFID6 (*(RoReg*)0x400142CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ -#define REG_CAN1_MSR6 (*(RoReg*)0x400142D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ -#define REG_CAN1_MDL6 (*(RwReg*)0x400142D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ -#define REG_CAN1_MDH6 (*(RwReg*)0x400142D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ -#define REG_CAN1_MCR6 (*(WoReg*)0x400142DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ -#define REG_CAN1_MMR7 (*(RwReg*)0x400142E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ -#define REG_CAN1_MAM7 (*(RwReg*)0x400142E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ -#define REG_CAN1_MID7 (*(RwReg*)0x400142E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ -#define REG_CAN1_MFID7 (*(RoReg*)0x400142ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ -#define REG_CAN1_MSR7 (*(RoReg*)0x400142F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ -#define REG_CAN1_MDL7 (*(RwReg*)0x400142F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ -#define REG_CAN1_MDH7 (*(RwReg*)0x400142F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ -#define REG_CAN1_MCR7 (*(WoReg*)0x400142FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_CAN1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/chipid.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/chipid.h deleted file mode 100644 index 54c13a729..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/chipid.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CHIPID_INSTANCE_ -#define _SAM4E_CHIPID_INSTANCE_ - -/* ========== Register definition for CHIPID peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -#else -#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_CHIPID_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/cmcc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/cmcc.h deleted file mode 100644 index cee4353ce..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/cmcc.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CMCC_INSTANCE_ -#define _SAM4E_CMCC_INSTANCE_ - -/* ========== Register definition for CMCC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CMCC_TYPE (0x400C4000U) /**< \brief (CMCC) Cache Type Register */ -#define REG_CMCC_CFG (0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */ -#define REG_CMCC_CTRL (0x400C4008U) /**< \brief (CMCC) Cache Control Register */ -#define REG_CMCC_SR (0x400C400CU) /**< \brief (CMCC) Cache Status Register */ -#define REG_CMCC_MAINT0 (0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */ -#define REG_CMCC_MAINT1 (0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */ -#define REG_CMCC_MCFG (0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */ -#define REG_CMCC_MEN (0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */ -#define REG_CMCC_MCTRL (0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */ -#define REG_CMCC_MSR (0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */ -#else -#define REG_CMCC_TYPE (*(RoReg*)0x400C4000U) /**< \brief (CMCC) Cache Type Register */ -#define REG_CMCC_CFG (*(RwReg*)0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */ -#define REG_CMCC_CTRL (*(WoReg*)0x400C4008U) /**< \brief (CMCC) Cache Control Register */ -#define REG_CMCC_SR (*(RoReg*)0x400C400CU) /**< \brief (CMCC) Cache Status Register */ -#define REG_CMCC_MAINT0 (*(WoReg*)0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */ -#define REG_CMCC_MAINT1 (*(WoReg*)0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */ -#define REG_CMCC_MCFG (*(RwReg*)0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */ -#define REG_CMCC_MEN (*(RwReg*)0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */ -#define REG_CMCC_MCTRL (*(WoReg*)0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */ -#define REG_CMCC_MSR (*(RoReg*)0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_CMCC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/crccu.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/crccu.h deleted file mode 100644 index 9856dc73a..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/crccu.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_CRCCU_INSTANCE_ -#define _SAM4E_CRCCU_INSTANCE_ - -/* ========== Register definition for CRCCU peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CRCCU_DSCR (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -#else -#define REG_CRCCU_DSCR (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_CRCCU_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/dacc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/dacc.h deleted file mode 100644 index bfaf0cd80..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/dacc.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_DACC_INSTANCE_ -#define _SAM4E_DACC_INSTANCE_ - -/* ========== Register definition for DACC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DACC_CR (0x400B8000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR (0x400B8004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER (0x400B8010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR (0x400B8014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR (0x400B8018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR (0x400B8020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER (0x400B8024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR (0x400B8028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR (0x400B802CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR (0x400B8030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR (0x400B8094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR (0x400B80E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR (0x400B80E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_TPR (0x400B8108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR (0x400B810CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_TNPR (0x400B8118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR (0x400B811CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR (0x400B8120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR (0x400B8124U) /**< \brief (DACC) Transfer Status Register */ -#else -#define REG_DACC_CR (*(WoReg*)0x400B8000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR (*(RwReg*)0x400B8004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER (*(WoReg*)0x400B8010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR (*(WoReg*)0x400B8014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR (*(RoReg*)0x400B8018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR (*(WoReg*)0x400B8020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER (*(WoReg*)0x400B8024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR (*(WoReg*)0x400B8028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR (*(RoReg*)0x400B802CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR (*(RoReg*)0x400B8030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR (*(RwReg*)0x400B8094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR (*(RwReg*)0x400B80E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR (*(RoReg*)0x400B80E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_TPR (*(RwReg*)0x400B8108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR (*(RwReg*)0x400B810CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_TNPR (*(RwReg*)0x400B8118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR (*(RwReg*)0x400B811CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR (*(WoReg*)0x400B8120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR (*(RoReg*)0x400B8124U) /**< \brief (DACC) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_DACC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/dmac.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/dmac.h deleted file mode 100644 index 9c812599d..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/dmac.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_DMAC_INSTANCE_ -#define _SAM4E_DMAC_INSTANCE_ - -/* ========== Register definition for DMAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DMAC_GCFG (0x400C0000U) /**< \brief (DMAC) DMAC Global Configuration Register */ -#define REG_DMAC_EN (0x400C0004U) /**< \brief (DMAC) DMAC Enable Register */ -#define REG_DMAC_SREQ (0x400C0008U) /**< \brief (DMAC) DMAC Software Single Request Register */ -#define REG_DMAC_CREQ (0x400C000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ -#define REG_DMAC_LAST (0x400C0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ -#define REG_DMAC_EBCIER (0x400C0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ -#define REG_DMAC_EBCIDR (0x400C001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ -#define REG_DMAC_EBCIMR (0x400C0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ -#define REG_DMAC_EBCISR (0x400C0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ -#define REG_DMAC_CHER (0x400C0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ -#define REG_DMAC_CHDR (0x400C002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ -#define REG_DMAC_CHSR (0x400C0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ -#define REG_DMAC_SADDR0 (0x400C003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ -#define REG_DMAC_DADDR0 (0x400C0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ -#define REG_DMAC_DSCR0 (0x400C0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ -#define REG_DMAC_CTRLA0 (0x400C0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ -#define REG_DMAC_CTRLB0 (0x400C004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ -#define REG_DMAC_CFG0 (0x400C0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ -#define REG_DMAC_SADDR1 (0x400C0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ -#define REG_DMAC_DADDR1 (0x400C0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ -#define REG_DMAC_DSCR1 (0x400C006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ -#define REG_DMAC_CTRLA1 (0x400C0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ -#define REG_DMAC_CTRLB1 (0x400C0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ -#define REG_DMAC_CFG1 (0x400C0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ -#define REG_DMAC_SADDR2 (0x400C008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ -#define REG_DMAC_DADDR2 (0x400C0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ -#define REG_DMAC_DSCR2 (0x400C0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ -#define REG_DMAC_CTRLA2 (0x400C0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ -#define REG_DMAC_CTRLB2 (0x400C009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ -#define REG_DMAC_CFG2 (0x400C00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ -#define REG_DMAC_SADDR3 (0x400C00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ -#define REG_DMAC_DADDR3 (0x400C00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ -#define REG_DMAC_DSCR3 (0x400C00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ -#define REG_DMAC_CTRLA3 (0x400C00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ -#define REG_DMAC_CTRLB3 (0x400C00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ -#define REG_DMAC_CFG3 (0x400C00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ -#define REG_DMAC_WPMR (0x400C01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */ -#define REG_DMAC_WPSR (0x400C01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */ -#else -#define REG_DMAC_GCFG (*(RwReg*)0x400C0000U) /**< \brief (DMAC) DMAC Global Configuration Register */ -#define REG_DMAC_EN (*(RwReg*)0x400C0004U) /**< \brief (DMAC) DMAC Enable Register */ -#define REG_DMAC_SREQ (*(RwReg*)0x400C0008U) /**< \brief (DMAC) DMAC Software Single Request Register */ -#define REG_DMAC_CREQ (*(RwReg*)0x400C000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ -#define REG_DMAC_LAST (*(RwReg*)0x400C0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ -#define REG_DMAC_EBCIER (*(WoReg*)0x400C0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ -#define REG_DMAC_EBCIDR (*(WoReg*)0x400C001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ -#define REG_DMAC_EBCIMR (*(RoReg*)0x400C0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ -#define REG_DMAC_EBCISR (*(RoReg*)0x400C0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ -#define REG_DMAC_CHER (*(WoReg*)0x400C0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ -#define REG_DMAC_CHDR (*(WoReg*)0x400C002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ -#define REG_DMAC_CHSR (*(RoReg*)0x400C0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ -#define REG_DMAC_SADDR0 (*(RwReg*)0x400C003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ -#define REG_DMAC_DADDR0 (*(RwReg*)0x400C0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ -#define REG_DMAC_DSCR0 (*(RwReg*)0x400C0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ -#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ -#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ -#define REG_DMAC_CFG0 (*(RwReg*)0x400C0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ -#define REG_DMAC_SADDR1 (*(RwReg*)0x400C0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ -#define REG_DMAC_DADDR1 (*(RwReg*)0x400C0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ -#define REG_DMAC_DSCR1 (*(RwReg*)0x400C006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ -#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ -#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ -#define REG_DMAC_CFG1 (*(RwReg*)0x400C0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ -#define REG_DMAC_SADDR2 (*(RwReg*)0x400C008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ -#define REG_DMAC_DADDR2 (*(RwReg*)0x400C0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ -#define REG_DMAC_DSCR2 (*(RwReg*)0x400C0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ -#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ -#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ -#define REG_DMAC_CFG2 (*(RwReg*)0x400C00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ -#define REG_DMAC_SADDR3 (*(RwReg*)0x400C00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ -#define REG_DMAC_DADDR3 (*(RwReg*)0x400C00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ -#define REG_DMAC_DSCR3 (*(RwReg*)0x400C00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ -#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ -#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ -#define REG_DMAC_CFG3 (*(RwReg*)0x400C00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ -#define REG_DMAC_WPMR (*(RwReg*)0x400C01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */ -#define REG_DMAC_WPSR (*(RoReg*)0x400C01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_DMAC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/efc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/efc.h deleted file mode 100644 index 611399e28..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/efc.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_EFC_INSTANCE_ -#define _SAM4E_EFC_INSTANCE_ - -/* ========== Register definition for EFC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -#else -#define REG_EFC_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_EFC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/gmac.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/gmac.h deleted file mode 100644 index ad41815ef..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/gmac.h +++ /dev/null @@ -1,232 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_GMAC_INSTANCE_ -#define _SAM4E_GMAC_INSTANCE_ - -/* ========== Register definition for GMAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_GMAC_NCR (0x40034000U) /**< \brief (GMAC) Network Control Register */ -#define REG_GMAC_NCFGR (0x40034004U) /**< \brief (GMAC) Network Configuration Register */ -#define REG_GMAC_NSR (0x40034008U) /**< \brief (GMAC) Network Status Register */ -#define REG_GMAC_UR (0x4003400CU) /**< \brief (GMAC) User Register */ -#define REG_GMAC_DCFGR (0x40034010U) /**< \brief (GMAC) DMA Configuration Register */ -#define REG_GMAC_TSR (0x40034014U) /**< \brief (GMAC) Transmit Status Register */ -#define REG_GMAC_RBQB (0x40034018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */ -#define REG_GMAC_TBQB (0x4003401CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */ -#define REG_GMAC_RSR (0x40034020U) /**< \brief (GMAC) Receive Status Register */ -#define REG_GMAC_ISR (0x40034024U) /**< \brief (GMAC) Interrupt Status Register */ -#define REG_GMAC_IER (0x40034028U) /**< \brief (GMAC) Interrupt Enable Register */ -#define REG_GMAC_IDR (0x4003402CU) /**< \brief (GMAC) Interrupt Disable Register */ -#define REG_GMAC_IMR (0x40034030U) /**< \brief (GMAC) Interrupt Mask Register */ -#define REG_GMAC_MAN (0x40034034U) /**< \brief (GMAC) PHY Maintenance Register */ -#define REG_GMAC_RPQ (0x40034038U) /**< \brief (GMAC) Received Pause Quantum Register */ -#define REG_GMAC_TPQ (0x4003403CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ -#define REG_GMAC_HRB (0x40034080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */ -#define REG_GMAC_HRT (0x40034084U) /**< \brief (GMAC) Hash Register Top [63:32] */ -#define REG_GMAC_SAB1 (0x40034088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */ -#define REG_GMAC_SAT1 (0x4003408CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */ -#define REG_GMAC_SAB2 (0x40034090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */ -#define REG_GMAC_SAT2 (0x40034094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */ -#define REG_GMAC_SAB3 (0x40034098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */ -#define REG_GMAC_SAT3 (0x4003409CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */ -#define REG_GMAC_SAB4 (0x400340A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */ -#define REG_GMAC_SAT4 (0x400340A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */ -#define REG_GMAC_TIDM (0x400340A8U) /**< \brief (GMAC) Type ID Match 1 Register */ -#define REG_GMAC_IPGS (0x400340BCU) /**< \brief (GMAC) IPG Stretch Register */ -#define REG_GMAC_SVLAN (0x400340C0U) /**< \brief (GMAC) Stacked VLAN Register */ -#define REG_GMAC_TPFCP (0x400340C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ -#define REG_GMAC_SAMB1 (0x400340C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */ -#define REG_GMAC_SAMT1 (0x400340CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */ -#define REG_GMAC_OTLO (0x40034100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */ -#define REG_GMAC_OTHI (0x40034104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */ -#define REG_GMAC_FT (0x40034108U) /**< \brief (GMAC) Frames Transmitted Register */ -#define REG_GMAC_BCFT (0x4003410CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ -#define REG_GMAC_MFT (0x40034110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ -#define REG_GMAC_PFT (0x40034114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ -#define REG_GMAC_BFT64 (0x40034118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT127 (0x4003411CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT255 (0x40034120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT511 (0x40034124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT1023 (0x40034128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT1518 (0x4003412CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ -#define REG_GMAC_GTBFT1518 (0x40034130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ -#define REG_GMAC_TUR (0x40034134U) /**< \brief (GMAC) Transmit Under Runs Register */ -#define REG_GMAC_SCF (0x40034138U) /**< \brief (GMAC) Single Collision Frames Register */ -#define REG_GMAC_MCF (0x4003413CU) /**< \brief (GMAC) Multiple Collision Frames Register */ -#define REG_GMAC_EC (0x40034140U) /**< \brief (GMAC) Excessive Collisions Register */ -#define REG_GMAC_LC (0x40034144U) /**< \brief (GMAC) Late Collisions Register */ -#define REG_GMAC_DTF (0x40034148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ -#define REG_GMAC_CSE (0x4003414CU) /**< \brief (GMAC) Carrier Sense Errors Register */ -#define REG_GMAC_ORLO (0x40034150U) /**< \brief (GMAC) Octets Received [31:0] Received */ -#define REG_GMAC_ORHI (0x40034154U) /**< \brief (GMAC) Octets Received [47:32] Received */ -#define REG_GMAC_FR (0x40034158U) /**< \brief (GMAC) Frames Received Register */ -#define REG_GMAC_BCFR (0x4003415CU) /**< \brief (GMAC) Broadcast Frames Received Register */ -#define REG_GMAC_MFR (0x40034160U) /**< \brief (GMAC) Multicast Frames Received Register */ -#define REG_GMAC_PFR (0x40034164U) /**< \brief (GMAC) Pause Frames Received Register */ -#define REG_GMAC_BFR64 (0x40034168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ -#define REG_GMAC_TBFR127 (0x4003416CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ -#define REG_GMAC_TBFR255 (0x40034170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ -#define REG_GMAC_TBFR511 (0x40034174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */ -#define REG_GMAC_TBFR1023 (0x40034178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ -#define REG_GMAC_TBFR1518 (0x4003417CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ -#define REG_GMAC_TMXBFR (0x40034180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ -#define REG_GMAC_UFR (0x40034184U) /**< \brief (GMAC) Undersize Frames Received Register */ -#define REG_GMAC_OFR (0x40034188U) /**< \brief (GMAC) Oversize Frames Received Register */ -#define REG_GMAC_JR (0x4003418CU) /**< \brief (GMAC) Jabbers Received Register */ -#define REG_GMAC_FCSE (0x40034190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ -#define REG_GMAC_LFFE (0x40034194U) /**< \brief (GMAC) Length Field Frame Errors Register */ -#define REG_GMAC_RSE (0x40034198U) /**< \brief (GMAC) Receive Symbol Errors Register */ -#define REG_GMAC_AE (0x4003419CU) /**< \brief (GMAC) Alignment Errors Register */ -#define REG_GMAC_RRE (0x400341A0U) /**< \brief (GMAC) Receive Resource Errors Register */ -#define REG_GMAC_ROE (0x400341A4U) /**< \brief (GMAC) Receive Overrun Register */ -#define REG_GMAC_IHCE (0x400341A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ -#define REG_GMAC_TCE (0x400341ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ -#define REG_GMAC_UCE (0x400341B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ -#define REG_GMAC_TSSS (0x400341C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */ -#define REG_GMAC_TSSN (0x400341CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */ -#define REG_GMAC_TS (0x400341D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */ -#define REG_GMAC_TN (0x400341D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ -#define REG_GMAC_TA (0x400341D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ -#define REG_GMAC_TI (0x400341DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ -#define REG_GMAC_EFTS (0x400341E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */ -#define REG_GMAC_EFTN (0x400341E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */ -#define REG_GMAC_EFRS (0x400341E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */ -#define REG_GMAC_EFRN (0x400341ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */ -#define REG_GMAC_PEFTS (0x400341F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */ -#define REG_GMAC_PEFTN (0x400341F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */ -#define REG_GMAC_PEFRS (0x400341F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */ -#define REG_GMAC_PEFRN (0x400341FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */ -#else -#define REG_GMAC_NCR (*(RwReg*)0x40034000U) /**< \brief (GMAC) Network Control Register */ -#define REG_GMAC_NCFGR (*(RwReg*)0x40034004U) /**< \brief (GMAC) Network Configuration Register */ -#define REG_GMAC_NSR (*(RoReg*)0x40034008U) /**< \brief (GMAC) Network Status Register */ -#define REG_GMAC_UR (*(RwReg*)0x4003400CU) /**< \brief (GMAC) User Register */ -#define REG_GMAC_DCFGR (*(RwReg*)0x40034010U) /**< \brief (GMAC) DMA Configuration Register */ -#define REG_GMAC_TSR (*(RwReg*)0x40034014U) /**< \brief (GMAC) Transmit Status Register */ -#define REG_GMAC_RBQB (*(RwReg*)0x40034018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */ -#define REG_GMAC_TBQB (*(RwReg*)0x4003401CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */ -#define REG_GMAC_RSR (*(RwReg*)0x40034020U) /**< \brief (GMAC) Receive Status Register */ -#define REG_GMAC_ISR (*(RoReg*)0x40034024U) /**< \brief (GMAC) Interrupt Status Register */ -#define REG_GMAC_IER (*(WoReg*)0x40034028U) /**< \brief (GMAC) Interrupt Enable Register */ -#define REG_GMAC_IDR (*(WoReg*)0x4003402CU) /**< \brief (GMAC) Interrupt Disable Register */ -#define REG_GMAC_IMR (*(RoReg*)0x40034030U) /**< \brief (GMAC) Interrupt Mask Register */ -#define REG_GMAC_MAN (*(RwReg*)0x40034034U) /**< \brief (GMAC) PHY Maintenance Register */ -#define REG_GMAC_RPQ (*(RoReg*)0x40034038U) /**< \brief (GMAC) Received Pause Quantum Register */ -#define REG_GMAC_TPQ (*(RwReg*)0x4003403CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ -#define REG_GMAC_HRB (*(RwReg*)0x40034080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */ -#define REG_GMAC_HRT (*(RwReg*)0x40034084U) /**< \brief (GMAC) Hash Register Top [63:32] */ -#define REG_GMAC_SAB1 (*(RwReg*)0x40034088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */ -#define REG_GMAC_SAT1 (*(RwReg*)0x4003408CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */ -#define REG_GMAC_SAB2 (*(RwReg*)0x40034090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */ -#define REG_GMAC_SAT2 (*(RwReg*)0x40034094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */ -#define REG_GMAC_SAB3 (*(RwReg*)0x40034098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */ -#define REG_GMAC_SAT3 (*(RwReg*)0x4003409CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */ -#define REG_GMAC_SAB4 (*(RwReg*)0x400340A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */ -#define REG_GMAC_SAT4 (*(RwReg*)0x400340A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */ -#define REG_GMAC_TIDM (*(RwReg*)0x400340A8U) /**< \brief (GMAC) Type ID Match 1 Register */ -#define REG_GMAC_IPGS (*(RwReg*)0x400340BCU) /**< \brief (GMAC) IPG Stretch Register */ -#define REG_GMAC_SVLAN (*(RwReg*)0x400340C0U) /**< \brief (GMAC) Stacked VLAN Register */ -#define REG_GMAC_TPFCP (*(RwReg*)0x400340C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ -#define REG_GMAC_SAMB1 (*(RwReg*)0x400340C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */ -#define REG_GMAC_SAMT1 (*(RwReg*)0x400340CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */ -#define REG_GMAC_OTLO (*(RoReg*)0x40034100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */ -#define REG_GMAC_OTHI (*(RoReg*)0x40034104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */ -#define REG_GMAC_FT (*(RoReg*)0x40034108U) /**< \brief (GMAC) Frames Transmitted Register */ -#define REG_GMAC_BCFT (*(RoReg*)0x4003410CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ -#define REG_GMAC_MFT (*(RoReg*)0x40034110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ -#define REG_GMAC_PFT (*(RoReg*)0x40034114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ -#define REG_GMAC_BFT64 (*(RoReg*)0x40034118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT127 (*(RoReg*)0x4003411CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT255 (*(RoReg*)0x40034120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT511 (*(RoReg*)0x40034124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT1023 (*(RoReg*)0x40034128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ -#define REG_GMAC_TBFT1518 (*(RoReg*)0x4003412CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ -#define REG_GMAC_GTBFT1518 (*(RoReg*)0x40034130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ -#define REG_GMAC_TUR (*(RoReg*)0x40034134U) /**< \brief (GMAC) Transmit Under Runs Register */ -#define REG_GMAC_SCF (*(RoReg*)0x40034138U) /**< \brief (GMAC) Single Collision Frames Register */ -#define REG_GMAC_MCF (*(RoReg*)0x4003413CU) /**< \brief (GMAC) Multiple Collision Frames Register */ -#define REG_GMAC_EC (*(RoReg*)0x40034140U) /**< \brief (GMAC) Excessive Collisions Register */ -#define REG_GMAC_LC (*(RoReg*)0x40034144U) /**< \brief (GMAC) Late Collisions Register */ -#define REG_GMAC_DTF (*(RoReg*)0x40034148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ -#define REG_GMAC_CSE (*(RoReg*)0x4003414CU) /**< \brief (GMAC) Carrier Sense Errors Register */ -#define REG_GMAC_ORLO (*(RoReg*)0x40034150U) /**< \brief (GMAC) Octets Received [31:0] Received */ -#define REG_GMAC_ORHI (*(RoReg*)0x40034154U) /**< \brief (GMAC) Octets Received [47:32] Received */ -#define REG_GMAC_FR (*(RoReg*)0x40034158U) /**< \brief (GMAC) Frames Received Register */ -#define REG_GMAC_BCFR (*(RoReg*)0x4003415CU) /**< \brief (GMAC) Broadcast Frames Received Register */ -#define REG_GMAC_MFR (*(RoReg*)0x40034160U) /**< \brief (GMAC) Multicast Frames Received Register */ -#define REG_GMAC_PFR (*(RoReg*)0x40034164U) /**< \brief (GMAC) Pause Frames Received Register */ -#define REG_GMAC_BFR64 (*(RoReg*)0x40034168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ -#define REG_GMAC_TBFR127 (*(RoReg*)0x4003416CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ -#define REG_GMAC_TBFR255 (*(RoReg*)0x40034170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ -#define REG_GMAC_TBFR511 (*(RoReg*)0x40034174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */ -#define REG_GMAC_TBFR1023 (*(RoReg*)0x40034178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ -#define REG_GMAC_TBFR1518 (*(RoReg*)0x4003417CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ -#define REG_GMAC_TMXBFR (*(RoReg*)0x40034180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ -#define REG_GMAC_UFR (*(RoReg*)0x40034184U) /**< \brief (GMAC) Undersize Frames Received Register */ -#define REG_GMAC_OFR (*(RoReg*)0x40034188U) /**< \brief (GMAC) Oversize Frames Received Register */ -#define REG_GMAC_JR (*(RoReg*)0x4003418CU) /**< \brief (GMAC) Jabbers Received Register */ -#define REG_GMAC_FCSE (*(RoReg*)0x40034190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ -#define REG_GMAC_LFFE (*(RoReg*)0x40034194U) /**< \brief (GMAC) Length Field Frame Errors Register */ -#define REG_GMAC_RSE (*(RoReg*)0x40034198U) /**< \brief (GMAC) Receive Symbol Errors Register */ -#define REG_GMAC_AE (*(RoReg*)0x4003419CU) /**< \brief (GMAC) Alignment Errors Register */ -#define REG_GMAC_RRE (*(RoReg*)0x400341A0U) /**< \brief (GMAC) Receive Resource Errors Register */ -#define REG_GMAC_ROE (*(RoReg*)0x400341A4U) /**< \brief (GMAC) Receive Overrun Register */ -#define REG_GMAC_IHCE (*(RoReg*)0x400341A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ -#define REG_GMAC_TCE (*(RoReg*)0x400341ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ -#define REG_GMAC_UCE (*(RoReg*)0x400341B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ -#define REG_GMAC_TSSS (*(RwReg*)0x400341C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */ -#define REG_GMAC_TSSN (*(RwReg*)0x400341CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */ -#define REG_GMAC_TS (*(RwReg*)0x400341D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */ -#define REG_GMAC_TN (*(RwReg*)0x400341D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ -#define REG_GMAC_TA (*(WoReg*)0x400341D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ -#define REG_GMAC_TI (*(RwReg*)0x400341DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ -#define REG_GMAC_EFTS (*(RoReg*)0x400341E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */ -#define REG_GMAC_EFTN (*(RoReg*)0x400341E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */ -#define REG_GMAC_EFRS (*(RoReg*)0x400341E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */ -#define REG_GMAC_EFRN (*(RoReg*)0x400341ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */ -#define REG_GMAC_PEFTS (*(RoReg*)0x400341F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */ -#define REG_GMAC_PEFTN (*(RoReg*)0x400341F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */ -#define REG_GMAC_PEFRS (*(RoReg*)0x400341F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */ -#define REG_GMAC_PEFRN (*(RoReg*)0x400341FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_GMAC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/gpbr.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/gpbr.h deleted file mode 100644 index 143e37bc2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/gpbr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_GPBR_INSTANCE_ -#define _SAM4E_GPBR_INSTANCE_ - -/* ========== Register definition for GPBR peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ -#else -#define REG_GPBR_GPBR (*(RwReg*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_GPBR_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/hsmci.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/hsmci.h deleted file mode 100644 index 413b78611..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/hsmci.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_HSMCI_INSTANCE_ -#define _SAM4E_HSMCI_INSTANCE_ - -/* ========== Register definition for HSMCI peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_HSMCI_CR (0x40080000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR (0x40080004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR (0x40080008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR (0x4008000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR (0x40080010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR (0x40080014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR (0x40080018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR (0x4008001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR (0x40080020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR (0x40080030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR (0x40080034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR (0x40080040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER (0x40080044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR (0x40080048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR (0x4008004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG (0x40080054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR (0x400800E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR (0x400800E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR (0x40080100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR (0x40080104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR (0x40080108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR (0x4008010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR (0x40080110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR (0x40080114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR (0x40080118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR (0x4008011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR (0x40080120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR (0x40080124U) /**< \brief (HSMCI) Transfer Status Register */ -#define REG_HSMCI_FIFO (0x40080200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ -#else -#define REG_HSMCI_CR (*(WoReg*)0x40080000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR (*(RwReg*)0x40080004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR (*(RwReg*)0x40080008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR (*(RwReg*)0x4008000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR (*(RwReg*)0x40080010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR (*(WoReg*)0x40080014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR (*(RwReg*)0x40080018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR (*(RwReg*)0x4008001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR (*(RoReg*)0x40080020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR (*(RoReg*)0x40080030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR (*(WoReg*)0x40080034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR (*(RoReg*)0x40080040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER (*(WoReg*)0x40080044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR (*(WoReg*)0x40080048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR (*(RoReg*)0x4008004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG (*(RwReg*)0x40080054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR (*(RwReg*)0x400800E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR (*(RoReg*)0x400800E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR (*(RwReg*)0x40080100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR (*(RwReg*)0x40080104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR (*(RwReg*)0x40080108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR (*(RwReg*)0x4008010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR (*(RwReg*)0x40080110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR (*(RwReg*)0x40080114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR (*(RwReg*)0x40080118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR (*(RwReg*)0x4008011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR (*(WoReg*)0x40080120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR (*(RoReg*)0x40080124U) /**< \brief (HSMCI) Transfer Status Register */ -#define REG_HSMCI_FIFO (*(RwReg*)0x40080200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_HSMCI_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/matrix.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/matrix.h deleted file mode 100644 index e996ba229..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/matrix.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_MATRIX_INSTANCE_ -#define _SAM4E_MATRIX_INSTANCE_ - -/* ========== Register definition for MATRIX peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_PRAS5 (0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ -#define REG_MATRIX_MRCR (0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */ -#define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration Register */ -#define REG_CCFG_SMCNFCS (0x400E0324U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ -#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -#else -#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ -#define REG_MATRIX_MRCR (*(RwReg*)0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */ -#define REG_CCFG_SYSIO (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration Register */ -#define REG_CCFG_SMCNFCS (*(RwReg*)0x400E0324U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ -#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_MATRIX_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioa.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioa.h deleted file mode 100644 index 61db8ab85..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioa.h +++ /dev/null @@ -1,170 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PIOA_INSTANCE_ -#define _SAM4E_PIOA_INSTANCE_ - -/* ========== Register definition for PIOA peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ -#define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ -#define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ -#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_DELAYR (0x400E0F10U) /**< \brief (PIOA) IO Delay Register */ -#define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -#define REG_PIOA_RPR (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */ -#define REG_PIOA_RCR (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */ -#define REG_PIOA_RNPR (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */ -#define REG_PIOA_RNCR (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */ -#define REG_PIOA_PTCR (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */ -#define REG_PIOA_PTSR (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */ -#else -#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_IFSCDR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ -#define REG_PIOA_IFSCER (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ -#define REG_PIOA_IFSCSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ -#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_DELAYR (*(RwReg*)0x400E0F10U) /**< \brief (PIOA) IO Delay Register */ -#define REG_PIOA_PCMR (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -#define REG_PIOA_RPR (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */ -#define REG_PIOA_RCR (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */ -#define REG_PIOA_RNPR (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */ -#define REG_PIOA_RNCR (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */ -#define REG_PIOA_PTCR (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */ -#define REG_PIOA_PTSR (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_PIOA_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/piob.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/piob.h deleted file mode 100644 index 46b342a7e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/piob.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PIOB_INSTANCE_ -#define _SAM4E_PIOB_INSTANCE_ - -/* ========== Register definition for PIOB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ -#define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ -#define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ -#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_DELAYR (0x400E1110U) /**< \brief (PIOB) IO Delay Register */ -#define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -#else -#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_IFSCDR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ -#define REG_PIOB_IFSCER (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ -#define REG_PIOB_IFSCSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ -#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_DELAYR (*(RwReg*)0x400E1110U) /**< \brief (PIOB) IO Delay Register */ -#define REG_PIOB_PCMR (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_PIOB_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioc.h deleted file mode 100644 index c6e81e49f..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioc.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PIOC_INSTANCE_ -#define _SAM4E_PIOC_INSTANCE_ - -/* ========== Register definition for PIOC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ -#define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ -#define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ -#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_DELAYR (0x400E1310U) /**< \brief (PIOC) IO Delay Register */ -#define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -#else -#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_IFSCDR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ -#define REG_PIOC_IFSCER (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ -#define REG_PIOC_IFSCSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ -#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_DELAYR (*(RwReg*)0x400E1310U) /**< \brief (PIOC) IO Delay Register */ -#define REG_PIOC_PCMR (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_PIOC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/piod.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/piod.h deleted file mode 100644 index 2e5288326..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/piod.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PIOD_INSTANCE_ -#define _SAM4E_PIOD_INSTANCE_ - -/* ========== Register definition for PIOD peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ -#define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ -#define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */ -#define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */ -#define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */ -#define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */ -#define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ -#define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ -#define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ -#define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ -#define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ -#define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ -#define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ -#define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ -#define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ -#define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ -#define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ -#define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ -#define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ -#define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ -#define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ -#define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ -#define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ -#define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ -#define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ -#define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ -#define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ -#define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ -#define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ -#define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ -#define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ -#define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ -#define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ -#define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ -#define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ -#define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ -#define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ -#define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ -#define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */ -#define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ -#define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ -#define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ -#define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ -#define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */ -#define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */ -#define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */ -#define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ -#define REG_PIOD_DELAYR (0x400E1510U) /**< \brief (PIOD) IO Delay Register */ -#define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ -#define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ -#define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ -#define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ -#define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ -#define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ -#else -#define REG_PIOD_PER (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ -#define REG_PIOD_PDR (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ -#define REG_PIOD_PSR (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */ -#define REG_PIOD_OER (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */ -#define REG_PIOD_ODR (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */ -#define REG_PIOD_OSR (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */ -#define REG_PIOD_IFER (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ -#define REG_PIOD_IFDR (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ -#define REG_PIOD_IFSR (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ -#define REG_PIOD_SODR (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ -#define REG_PIOD_CODR (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ -#define REG_PIOD_ODSR (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ -#define REG_PIOD_PDSR (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ -#define REG_PIOD_IER (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ -#define REG_PIOD_IDR (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ -#define REG_PIOD_IMR (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ -#define REG_PIOD_ISR (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ -#define REG_PIOD_MDER (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ -#define REG_PIOD_MDDR (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ -#define REG_PIOD_MDSR (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ -#define REG_PIOD_PUDR (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ -#define REG_PIOD_PUER (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ -#define REG_PIOD_PUSR (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ -#define REG_PIOD_ABCDSR (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ -#define REG_PIOD_IFSCDR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ -#define REG_PIOD_IFSCER (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ -#define REG_PIOD_IFSCSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ -#define REG_PIOD_SCDR (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ -#define REG_PIOD_PPDDR (*(WoReg*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ -#define REG_PIOD_PPDER (*(WoReg*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ -#define REG_PIOD_PPDSR (*(RoReg*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ -#define REG_PIOD_OWER (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ -#define REG_PIOD_OWDR (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ -#define REG_PIOD_OWSR (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ -#define REG_PIOD_AIMER (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ -#define REG_PIOD_AIMDR (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ -#define REG_PIOD_AIMMR (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ -#define REG_PIOD_ESR (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ -#define REG_PIOD_LSR (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */ -#define REG_PIOD_ELSR (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ -#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ -#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ -#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ -#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */ -#define REG_PIOD_WPMR (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */ -#define REG_PIOD_WPSR (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */ -#define REG_PIOD_SCHMITT (*(RwReg*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ -#define REG_PIOD_DELAYR (*(RwReg*)0x400E1510U) /**< \brief (PIOD) IO Delay Register */ -#define REG_PIOD_PCMR (*(RwReg*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ -#define REG_PIOD_PCIER (*(WoReg*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ -#define REG_PIOD_PCIDR (*(WoReg*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ -#define REG_PIOD_PCIMR (*(RoReg*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ -#define REG_PIOD_PCISR (*(RoReg*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ -#define REG_PIOD_PCRHR (*(RoReg*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_PIOD_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioe.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioe.h deleted file mode 100644 index 549afa1aa..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pioe.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PIOE_INSTANCE_ -#define _SAM4E_PIOE_INSTANCE_ - -/* ========== Register definition for PIOE peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ -#define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ -#define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */ -#define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */ -#define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */ -#define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */ -#define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ -#define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ -#define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ -#define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ -#define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ -#define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ -#define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ -#define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ -#define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ -#define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ -#define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ -#define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ -#define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ -#define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ -#define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ -#define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ -#define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ -#define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ -#define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ -#define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ -#define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ -#define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ -#define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ -#define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ -#define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ -#define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ -#define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ -#define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ -#define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ -#define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ -#define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ -#define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ -#define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */ -#define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ -#define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ -#define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ -#define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ -#define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */ -#define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */ -#define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */ -#define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ -#define REG_PIOE_DELAYR (0x400E1710U) /**< \brief (PIOE) IO Delay Register */ -#define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ -#define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ -#define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ -#define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ -#define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ -#define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ -#else -#define REG_PIOE_PER (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ -#define REG_PIOE_PDR (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ -#define REG_PIOE_PSR (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */ -#define REG_PIOE_OER (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */ -#define REG_PIOE_ODR (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */ -#define REG_PIOE_OSR (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */ -#define REG_PIOE_IFER (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ -#define REG_PIOE_IFDR (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ -#define REG_PIOE_IFSR (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ -#define REG_PIOE_SODR (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ -#define REG_PIOE_CODR (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ -#define REG_PIOE_ODSR (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ -#define REG_PIOE_PDSR (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ -#define REG_PIOE_IER (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ -#define REG_PIOE_IDR (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ -#define REG_PIOE_IMR (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ -#define REG_PIOE_ISR (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ -#define REG_PIOE_MDER (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ -#define REG_PIOE_MDDR (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ -#define REG_PIOE_MDSR (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ -#define REG_PIOE_PUDR (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ -#define REG_PIOE_PUER (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ -#define REG_PIOE_PUSR (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ -#define REG_PIOE_ABCDSR (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ -#define REG_PIOE_IFSCDR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ -#define REG_PIOE_IFSCER (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ -#define REG_PIOE_IFSCSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ -#define REG_PIOE_SCDR (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ -#define REG_PIOE_PPDDR (*(WoReg*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ -#define REG_PIOE_PPDER (*(WoReg*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ -#define REG_PIOE_PPDSR (*(RoReg*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ -#define REG_PIOE_OWER (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ -#define REG_PIOE_OWDR (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ -#define REG_PIOE_OWSR (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ -#define REG_PIOE_AIMER (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ -#define REG_PIOE_AIMDR (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ -#define REG_PIOE_AIMMR (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ -#define REG_PIOE_ESR (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ -#define REG_PIOE_LSR (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */ -#define REG_PIOE_ELSR (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ -#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ -#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ -#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ -#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */ -#define REG_PIOE_WPMR (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */ -#define REG_PIOE_WPSR (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */ -#define REG_PIOE_SCHMITT (*(RwReg*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ -#define REG_PIOE_DELAYR (*(RwReg*)0x400E1710U) /**< \brief (PIOE) IO Delay Register */ -#define REG_PIOE_PCMR (*(RwReg*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ -#define REG_PIOE_PCIER (*(WoReg*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ -#define REG_PIOE_PCIDR (*(WoReg*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ -#define REG_PIOE_PCIMR (*(RoReg*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ -#define REG_PIOE_PCISR (*(RoReg*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ -#define REG_PIOE_PCRHR (*(RoReg*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_PIOE_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pmc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pmc.h deleted file mode 100644 index 69a38e88f..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pmc.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PMC_INSTANCE_ -#define _SAM4E_PMC_INSTANCE_ - -/* ========== Register definition for PMC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Start-up Mode Register */ -#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Start-up Polarity Register */ -#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -#else -#define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_CKGR_MCFR (*(RwReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Start-up Mode Register */ -#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Start-up Polarity Register */ -#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_PMC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pwm.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pwm.h deleted file mode 100644 index 938a52e32..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/pwm.h +++ /dev/null @@ -1,282 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_PWM_INSTANCE_ -#define _SAM4E_PWM_INSTANCE_ - -/* ========== Register definition for PWM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PWM_CLK (0x40000000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA (0x40000004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS (0x40000008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR (0x4000000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 (0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 (0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 (0x40000018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 (0x4000001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM (0x40000020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC (0x40000028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP (0x4000002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD (0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 (0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 (0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 (0x4000003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 (0x40000040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV (0x40000044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS (0x40000048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS (0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC (0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD (0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD (0x40000058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR (0x4000005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR (0x40000060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR (0x40000064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV1 (0x40000068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */ -#define REG_PWM_FPE (0x4000006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELMR (0x4000007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SSPR (0x400000A0U) /**< \brief (PWM) PWM Spread Spectrum Register */ -#define REG_PWM_SSPUP (0x400000A4U) /**< \brief (PWM) PWM Spread Spectrum Update Register */ -#define REG_PWM_SMMR (0x400000B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_FPV2 (0x400000C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */ -#define REG_PWM_WPCR (0x400000E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR (0x400000E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_TPR (0x40000108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR (0x4000010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_TNPR (0x40000118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR (0x4000011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR (0x40000120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR (0x40000124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMPV0 (0x40000130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMPVUPD0 (0x40000134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMPM0 (0x40000138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMPMUPD0 (0x4000013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMPV1 (0x40000140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMPVUPD1 (0x40000144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMPM1 (0x40000148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMPMUPD1 (0x4000014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMPV2 (0x40000150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMPVUPD2 (0x40000154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMPM2 (0x40000158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMPMUPD2 (0x4000015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMPV3 (0x40000160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMPVUPD3 (0x40000164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMPM3 (0x40000168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMPMUPD3 (0x4000016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMPV4 (0x40000170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMPVUPD4 (0x40000174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMPM4 (0x40000178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMPMUPD4 (0x4000017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMPV5 (0x40000180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMPVUPD5 (0x40000184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMPM5 (0x40000188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMPMUPD5 (0x4000018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMPV6 (0x40000190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMPVUPD6 (0x40000194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMPM6 (0x40000198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMPMUPD6 (0x4000019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMPV7 (0x400001A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMPVUPD7 (0x400001A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMPM7 (0x400001A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMPMUPD7 (0x400001ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 (0x40000200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 (0x40000204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 (0x40000208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 (0x4000020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 (0x40000210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 (0x40000214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 (0x40000218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 (0x4000021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 (0x40000220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 (0x40000224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 (0x40000228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 (0x4000022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 (0x40000230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 (0x40000234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 (0x40000238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 (0x4000023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 (0x40000240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 (0x40000244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 (0x40000248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 (0x4000024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 (0x40000250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 (0x40000254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 (0x40000258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 (0x4000025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 (0x40000260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 (0x40000264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 (0x40000268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 (0x4000026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 (0x40000270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 (0x40000274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 (0x40000278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 (0x4000027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -#define REG_PWM_CMUPD0 (0x40000400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */ -#define REG_PWM_CAE0 (0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 0) */ -#define REG_PWM_CAEUPD0 (0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 0) */ -#define REG_PWM_CMUPD1 (0x40000420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */ -#define REG_PWM_CAE1 (0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 1) */ -#define REG_PWM_CAEUPD1 (0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 1) */ -#define REG_PWM_CMUPD2 (0x40000440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */ -#define REG_PWM_CAE2 (0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 2) */ -#define REG_PWM_CAEUPD2 (0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 2) */ -#define REG_PWM_CMUPD3 (0x40000460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */ -#define REG_PWM_CAE3 (0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 3) */ -#define REG_PWM_CAEUPD3 (0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 3) */ -#else -#define REG_PWM_CLK (*(RwReg*)0x40000000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA (*(WoReg*)0x40000004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS (*(WoReg*)0x40000008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR (*(RoReg*)0x4000000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 (*(WoReg*)0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 (*(WoReg*)0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 (*(RoReg*)0x40000018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 (*(RoReg*)0x4000001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM (*(RwReg*)0x40000020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC (*(RwReg*)0x40000028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP (*(RwReg*)0x4000002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD (*(WoReg*)0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 (*(WoReg*)0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 (*(WoReg*)0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 (*(RoReg*)0x4000003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 (*(RoReg*)0x40000040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV (*(RwReg*)0x40000044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS (*(RwReg*)0x40000048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS (*(WoReg*)0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC (*(WoReg*)0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD (*(WoReg*)0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD (*(WoReg*)0x40000058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR (*(RwReg*)0x4000005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR (*(RoReg*)0x40000060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR (*(WoReg*)0x40000064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV1 (*(RwReg*)0x40000068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */ -#define REG_PWM_FPE (*(RwReg*)0x4000006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELMR (*(RwReg*)0x4000007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SSPR (*(RwReg*)0x400000A0U) /**< \brief (PWM) PWM Spread Spectrum Register */ -#define REG_PWM_SSPUP (*(WoReg*)0x400000A4U) /**< \brief (PWM) PWM Spread Spectrum Update Register */ -#define REG_PWM_SMMR (*(RwReg*)0x400000B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_FPV2 (*(RwReg*)0x400000C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */ -#define REG_PWM_WPCR (*(WoReg*)0x400000E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR (*(RoReg*)0x400000E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_TPR (*(RwReg*)0x40000108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR (*(RwReg*)0x4000010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_TNPR (*(RwReg*)0x40000118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR (*(RwReg*)0x4000011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR (*(WoReg*)0x40000120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR (*(RoReg*)0x40000124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMPV0 (*(RwReg*)0x40000130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40000134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMPM0 (*(RwReg*)0x40000138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4000013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMPV1 (*(RwReg*)0x40000140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40000144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMPM1 (*(RwReg*)0x40000148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4000014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMPV2 (*(RwReg*)0x40000150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40000154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMPM2 (*(RwReg*)0x40000158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4000015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMPV3 (*(RwReg*)0x40000160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40000164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMPM3 (*(RwReg*)0x40000168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4000016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMPV4 (*(RwReg*)0x40000170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40000174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMPM4 (*(RwReg*)0x40000178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4000017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMPV5 (*(RwReg*)0x40000180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40000184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMPM5 (*(RwReg*)0x40000188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4000018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMPV6 (*(RwReg*)0x40000190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40000194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMPM6 (*(RwReg*)0x40000198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4000019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMPV7 (*(RwReg*)0x400001A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400001A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMPM7 (*(RwReg*)0x400001A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400001ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 (*(RwReg*)0x40000200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 (*(RwReg*)0x40000204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40000208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 (*(RwReg*)0x4000020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40000210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 (*(RoReg*)0x40000214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 (*(RwReg*)0x40000218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 (*(WoReg*)0x4000021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 (*(RwReg*)0x40000220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 (*(RwReg*)0x40000224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40000228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 (*(RwReg*)0x4000022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40000230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 (*(RoReg*)0x40000234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 (*(RwReg*)0x40000238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 (*(WoReg*)0x4000023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 (*(RwReg*)0x40000240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 (*(RwReg*)0x40000244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40000248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 (*(RwReg*)0x4000024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40000250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 (*(RoReg*)0x40000254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 (*(RwReg*)0x40000258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 (*(WoReg*)0x4000025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 (*(RwReg*)0x40000260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 (*(RwReg*)0x40000264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40000268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 (*(RwReg*)0x4000026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40000270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 (*(RoReg*)0x40000274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 (*(RwReg*)0x40000278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 (*(WoReg*)0x4000027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -#define REG_PWM_CMUPD0 (*(WoReg*)0x40000400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */ -#define REG_PWM_CAE0 (*(RwReg*)0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 0) */ -#define REG_PWM_CAEUPD0 (*(WoReg*)0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 0) */ -#define REG_PWM_CMUPD1 (*(WoReg*)0x40000420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */ -#define REG_PWM_CAE1 (*(RwReg*)0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 1) */ -#define REG_PWM_CAEUPD1 (*(WoReg*)0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 1) */ -#define REG_PWM_CMUPD2 (*(WoReg*)0x40000440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */ -#define REG_PWM_CAE2 (*(RwReg*)0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 2) */ -#define REG_PWM_CAEUPD2 (*(WoReg*)0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 2) */ -#define REG_PWM_CMUPD3 (*(WoReg*)0x40000460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */ -#define REG_PWM_CAE3 (*(RwReg*)0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 3) */ -#define REG_PWM_CAEUPD3 (*(WoReg*)0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 3) */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_PWM_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rstc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rstc.h deleted file mode 100644 index 9321bea4a..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rstc.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_RSTC_INSTANCE_ -#define _SAM4E_RSTC_INSTANCE_ - -/* ========== Register definition for RSTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */ -#else -#define REG_RSTC_CR (*(WoReg*)0x400E1800U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR (*(RoReg*)0x400E1804U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR (*(RwReg*)0x400E1808U) /**< \brief (RSTC) Mode Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_RSTC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rswdt.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rswdt.h deleted file mode 100644 index b6454d2e4..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rswdt.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_RSWDT_INSTANCE_ -#define _SAM4E_RSWDT_INSTANCE_ - -/* ========== Register definition for RSWDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RSWDT_CR (0x400E1900U) /**< \brief (RSWDT) Control Register */ -#define REG_RSWDT_MR (0x400E1904U) /**< \brief (RSWDT) Mode Register */ -#define REG_RSWDT_SR (0x400E1908U) /**< \brief (RSWDT) Status Register */ -#else -#define REG_RSWDT_CR (*(WoReg*)0x400E1900U) /**< \brief (RSWDT) Control Register */ -#define REG_RSWDT_MR (*(RwReg*)0x400E1904U) /**< \brief (RSWDT) Mode Register */ -#define REG_RSWDT_SR (*(RoReg*)0x400E1908U) /**< \brief (RSWDT) Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_RSWDT_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rtc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rtc.h deleted file mode 100644 index fa9743d38..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rtc.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_RTC_INSTANCE_ -#define _SAM4E_RTC_INSTANCE_ - -/* ========== Register definition for RTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */ -#else -#define REG_RTC_CR (*(RwReg*)0x400E1860U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR (*(RwReg*)0x400E1864U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR (*(RwReg*)0x400E1868U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR (*(RwReg*)0x400E186CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR (*(RwReg*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR (*(RwReg*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR (*(RoReg*)0x400E1878U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR (*(WoReg*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER (*(WoReg*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR (*(WoReg*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR (*(RoReg*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER (*(RoReg*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_RTC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rtt.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rtt.h deleted file mode 100644 index f8ac96ca0..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/rtt.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_RTT_INSTANCE_ -#define _SAM4E_RTT_INSTANCE_ - -/* ========== Register definition for RTT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */ -#else -#define REG_RTT_MR (*(RwReg*)0x400E1830U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR (*(RwReg*)0x400E1834U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR (*(RoReg*)0x400E1838U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR (*(RoReg*)0x400E183CU) /**< \brief (RTT) Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_RTT_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/smc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/smc.h deleted file mode 100644 index 3906fdd33..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/smc.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_SMC_INSTANCE_ -#define _SAM4E_SMC_INSTANCE_ - -/* ========== Register definition for SMC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SMC_SETUP0 (0x40060000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 (0x40060004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 (0x40060008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 (0x4006000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 (0x40060010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 (0x40060014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 (0x40060018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 (0x4006001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 (0x40060020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 (0x40060024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 (0x40060028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 (0x4006002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 (0x40060030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 (0x40060034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 (0x40060038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 (0x4006003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_OCMS (0x40060080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 (0x40060084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 (0x40060088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR (0x400600E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR (0x400600E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -#else -#define REG_SMC_SETUP0 (*(RwReg*)0x40060000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 (*(RwReg*)0x40060004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 (*(RwReg*)0x40060008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 (*(RwReg*)0x4006000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 (*(RwReg*)0x40060010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 (*(RwReg*)0x40060014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 (*(RwReg*)0x40060018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 (*(RwReg*)0x4006001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 (*(RwReg*)0x40060020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 (*(RwReg*)0x40060024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 (*(RwReg*)0x40060028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 (*(RwReg*)0x4006002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 (*(RwReg*)0x40060030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 (*(RwReg*)0x40060034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 (*(RwReg*)0x40060038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 (*(RwReg*)0x4006003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_OCMS (*(RwReg*)0x40060080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 (*(WoReg*)0x40060084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 (*(WoReg*)0x40060088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR (*(RwReg*)0x400600E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR (*(RoReg*)0x400600E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_SMC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/spi.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/spi.h deleted file mode 100644 index 4deb7aea2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/spi.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_SPI_INSTANCE_ -#define _SAM4E_SPI_INSTANCE_ - -/* ========== Register definition for SPI peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SPI_CR (0x40088000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR (0x40088004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR (0x40088008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR (0x4008800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR (0x40088010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER (0x40088014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR (0x40088018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR (0x4008801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR (0x40088030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR (0x400880E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR (0x400880E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR (0x40088100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR (0x40088104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR (0x40088108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR (0x4008810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR (0x40088110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR (0x40088114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR (0x40088118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR (0x4008811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR (0x40088120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR (0x40088124U) /**< \brief (SPI) Transfer Status Register */ -#else -#define REG_SPI_CR (*(WoReg*)0x40088000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR (*(RwReg*)0x40088004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR (*(RoReg*)0x40088008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR (*(WoReg*)0x4008800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR (*(RoReg*)0x40088010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER (*(WoReg*)0x40088014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR (*(WoReg*)0x40088018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR (*(RoReg*)0x4008801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR (*(RwReg*)0x40088030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR (*(RwReg*)0x400880E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR (*(RoReg*)0x400880E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR (*(RwReg*)0x40088100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR (*(RwReg*)0x40088104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR (*(RwReg*)0x40088108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR (*(RwReg*)0x4008810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR (*(RwReg*)0x40088110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR (*(RwReg*)0x40088114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR (*(RwReg*)0x40088118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR (*(RwReg*)0x4008811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR (*(WoReg*)0x40088120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR (*(RoReg*)0x40088124U) /**< \brief (SPI) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_SPI_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/supc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/supc.h deleted file mode 100644 index f38b847b9..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/supc.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_SUPC_INSTANCE_ -#define _SAM4E_SUPC_INSTANCE_ - -/* ========== Register definition for SUPC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ -#define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ -#define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ -#else -#define REG_SUPC_CR (*(WoReg*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR (*(RwReg*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR (*(RwReg*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR (*(RwReg*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ -#define REG_SUPC_WUIR (*(RwReg*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ -#define REG_SUPC_SR (*(RoReg*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_SUPC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc0.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc0.h deleted file mode 100644 index 4da15b553..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc0.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_TC0_INSTANCE_ -#define _SAM4E_TC0_INSTANCE_ - -/* ========== Register definition for TC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC0_CCR0 (0x40090000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 (0x40090004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_SMMR0 (0x40090008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC0_RAB0 (0x4009000CU) /**< \brief (TC0) Register AB (channel = 0) */ -#define REG_TC0_CV0 (0x40090010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 (0x40090014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 (0x40090018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 (0x4009001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 (0x40090020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 (0x40090024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 (0x40090028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 (0x4009002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_EMR0 (0x40090030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ -#define REG_TC0_CCR1 (0x40090040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 (0x40090044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_SMMR1 (0x40090048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC0_RAB1 (0x4009004CU) /**< \brief (TC0) Register AB (channel = 1) */ -#define REG_TC0_CV1 (0x40090050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 (0x40090054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 (0x40090058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 (0x4009005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 (0x40090060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 (0x40090064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 (0x40090068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 (0x4009006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_EMR1 (0x40090070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ -#define REG_TC0_CCR2 (0x40090080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 (0x40090084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_SMMR2 (0x40090088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC0_RAB2 (0x4009008CU) /**< \brief (TC0) Register AB (channel = 2) */ -#define REG_TC0_CV2 (0x40090090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 (0x40090094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 (0x40090098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 (0x4009009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 (0x400900A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 (0x400900A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 (0x400900A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 (0x400900ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_EMR2 (0x400900B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ -#define REG_TC0_BCR (0x400900C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR (0x400900C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER (0x400900C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR (0x400900CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR (0x400900D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR (0x400900D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR (0x400900D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR (0x400900E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_RPR0 (0x40090100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */ -#define REG_TC0_RCR0 (0x40090104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */ -#define REG_TC0_RNPR0 (0x40090110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */ -#define REG_TC0_RNCR0 (0x40090114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */ -#define REG_TC0_PTCR0 (0x40090120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */ -#define REG_TC0_PTSR0 (0x40090124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */ -#define REG_TC0_RPR1 (0x40090140U) /**< \brief (TC0) Receive Pointer Register (pdc = 1) */ -#define REG_TC0_RCR1 (0x40090144U) /**< \brief (TC0) Receive Counter Register (pdc = 1) */ -#define REG_TC0_RNPR1 (0x40090150U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 1) */ -#define REG_TC0_RNCR1 (0x40090154U) /**< \brief (TC0) Receive Next Counter Register (pdc = 1) */ -#define REG_TC0_PTCR1 (0x40090160U) /**< \brief (TC0) Transfer Control Register (pdc = 1) */ -#define REG_TC0_PTSR1 (0x40090164U) /**< \brief (TC0) Transfer Status Register (pdc = 1) */ -#define REG_TC0_RPR2 (0x40090180U) /**< \brief (TC0) Receive Pointer Register (pdc = 2) */ -#define REG_TC0_RCR2 (0x40090184U) /**< \brief (TC0) Receive Counter Register (pdc = 2) */ -#define REG_TC0_RNPR2 (0x40090190U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 2) */ -#define REG_TC0_RNCR2 (0x40090194U) /**< \brief (TC0) Receive Next Counter Register (pdc = 2) */ -#define REG_TC0_PTCR2 (0x400901A0U) /**< \brief (TC0) Transfer Control Register (pdc = 2) */ -#define REG_TC0_PTSR2 (0x400901A4U) /**< \brief (TC0) Transfer Status Register (pdc = 2) */ -#else -#define REG_TC0_CCR0 (*(WoReg*)0x40090000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 (*(RwReg*)0x40090004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_SMMR0 (*(RwReg*)0x40090008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC0_RAB0 (*(RoReg*)0x4009000CU) /**< \brief (TC0) Register AB (channel = 0) */ -#define REG_TC0_CV0 (*(RoReg*)0x40090010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 (*(RwReg*)0x40090014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 (*(RwReg*)0x40090018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 (*(RwReg*)0x4009001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 (*(RoReg*)0x40090020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 (*(WoReg*)0x40090024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 (*(WoReg*)0x40090028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 (*(RoReg*)0x4009002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_EMR0 (*(RwReg*)0x40090030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ -#define REG_TC0_CCR1 (*(WoReg*)0x40090040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 (*(RwReg*)0x40090044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_SMMR1 (*(RwReg*)0x40090048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC0_RAB1 (*(RoReg*)0x4009004CU) /**< \brief (TC0) Register AB (channel = 1) */ -#define REG_TC0_CV1 (*(RoReg*)0x40090050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 (*(RwReg*)0x40090054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 (*(RwReg*)0x40090058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 (*(RwReg*)0x4009005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 (*(RoReg*)0x40090060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 (*(WoReg*)0x40090064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 (*(WoReg*)0x40090068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 (*(RoReg*)0x4009006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_EMR1 (*(RwReg*)0x40090070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ -#define REG_TC0_CCR2 (*(WoReg*)0x40090080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 (*(RwReg*)0x40090084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_SMMR2 (*(RwReg*)0x40090088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC0_RAB2 (*(RoReg*)0x4009008CU) /**< \brief (TC0) Register AB (channel = 2) */ -#define REG_TC0_CV2 (*(RoReg*)0x40090090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 (*(RwReg*)0x40090094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 (*(RwReg*)0x40090098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 (*(RwReg*)0x4009009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 (*(RoReg*)0x400900A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 (*(WoReg*)0x400900A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 (*(WoReg*)0x400900A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 (*(RoReg*)0x400900ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_EMR2 (*(RwReg*)0x400900B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ -#define REG_TC0_BCR (*(WoReg*)0x400900C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR (*(RwReg*)0x400900C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER (*(WoReg*)0x400900C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR (*(WoReg*)0x400900CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR (*(RoReg*)0x400900D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR (*(RoReg*)0x400900D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR (*(RwReg*)0x400900D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR (*(RwReg*)0x400900E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_RPR0 (*(RwReg*)0x40090100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */ -#define REG_TC0_RCR0 (*(RwReg*)0x40090104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */ -#define REG_TC0_RNPR0 (*(RwReg*)0x40090110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */ -#define REG_TC0_RNCR0 (*(RwReg*)0x40090114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */ -#define REG_TC0_PTCR0 (*(WoReg*)0x40090120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */ -#define REG_TC0_PTSR0 (*(RoReg*)0x40090124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */ -#define REG_TC0_RPR1 (*(RwReg*)0x40090140U) /**< \brief (TC0) Receive Pointer Register (pdc = 1) */ -#define REG_TC0_RCR1 (*(RwReg*)0x40090144U) /**< \brief (TC0) Receive Counter Register (pdc = 1) */ -#define REG_TC0_RNPR1 (*(RwReg*)0x40090150U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 1) */ -#define REG_TC0_RNCR1 (*(RwReg*)0x40090154U) /**< \brief (TC0) Receive Next Counter Register (pdc = 1) */ -#define REG_TC0_PTCR1 (*(WoReg*)0x40090160U) /**< \brief (TC0) Transfer Control Register (pdc = 1) */ -#define REG_TC0_PTSR1 (*(RoReg*)0x40090164U) /**< \brief (TC0) Transfer Status Register (pdc = 1) */ -#define REG_TC0_RPR2 (*(RwReg*)0x40090180U) /**< \brief (TC0) Receive Pointer Register (pdc = 2) */ -#define REG_TC0_RCR2 (*(RwReg*)0x40090184U) /**< \brief (TC0) Receive Counter Register (pdc = 2) */ -#define REG_TC0_RNPR2 (*(RwReg*)0x40090190U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 2) */ -#define REG_TC0_RNCR2 (*(RwReg*)0x40090194U) /**< \brief (TC0) Receive Next Counter Register (pdc = 2) */ -#define REG_TC0_PTCR2 (*(WoReg*)0x400901A0U) /**< \brief (TC0) Transfer Control Register (pdc = 2) */ -#define REG_TC0_PTSR2 (*(RoReg*)0x400901A4U) /**< \brief (TC0) Transfer Status Register (pdc = 2) */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_TC0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc1.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc1.h deleted file mode 100644 index 2c3c5534a..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc1.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_TC1_INSTANCE_ -#define _SAM4E_TC1_INSTANCE_ - -/* ========== Register definition for TC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC1_CCR0 (0x40094000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 (0x40094004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_SMMR0 (0x40094008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC1_RAB0 (0x4009400CU) /**< \brief (TC1) Register AB (channel = 0) */ -#define REG_TC1_CV0 (0x40094010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 (0x40094014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 (0x40094018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 (0x4009401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 (0x40094020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 (0x40094024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 (0x40094028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 (0x4009402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_EMR0 (0x40094030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ -#define REG_TC1_CCR1 (0x40094040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 (0x40094044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_SMMR1 (0x40094048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC1_RAB1 (0x4009404CU) /**< \brief (TC1) Register AB (channel = 1) */ -#define REG_TC1_CV1 (0x40094050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 (0x40094054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 (0x40094058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 (0x4009405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 (0x40094060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 (0x40094064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 (0x40094068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 (0x4009406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_EMR1 (0x40094070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ -#define REG_TC1_CCR2 (0x40094080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 (0x40094084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_SMMR2 (0x40094088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC1_RAB2 (0x4009408CU) /**< \brief (TC1) Register AB (channel = 2) */ -#define REG_TC1_CV2 (0x40094090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 (0x40094094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 (0x40094098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 (0x4009409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 (0x400940A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 (0x400940A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 (0x400940A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 (0x400940ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_EMR2 (0x400940B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ -#define REG_TC1_BCR (0x400940C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR (0x400940C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER (0x400940C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR (0x400940CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR (0x400940D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR (0x400940D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR (0x400940D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR (0x400940E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_RPR0 (0x40094100U) /**< \brief (TC1) Receive Pointer Register (pdc = 0) */ -#define REG_TC1_RCR0 (0x40094104U) /**< \brief (TC1) Receive Counter Register (pdc = 0) */ -#define REG_TC1_RNPR0 (0x40094110U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 0) */ -#define REG_TC1_RNCR0 (0x40094114U) /**< \brief (TC1) Receive Next Counter Register (pdc = 0) */ -#define REG_TC1_PTCR0 (0x40094120U) /**< \brief (TC1) Transfer Control Register (pdc = 0) */ -#define REG_TC1_PTSR0 (0x40094124U) /**< \brief (TC1) Transfer Status Register (pdc = 0) */ -#define REG_TC1_RPR1 (0x40094140U) /**< \brief (TC1) Receive Pointer Register (pdc = 1) */ -#define REG_TC1_RCR1 (0x40094144U) /**< \brief (TC1) Receive Counter Register (pdc = 1) */ -#define REG_TC1_RNPR1 (0x40094150U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 1) */ -#define REG_TC1_RNCR1 (0x40094154U) /**< \brief (TC1) Receive Next Counter Register (pdc = 1) */ -#define REG_TC1_PTCR1 (0x40094160U) /**< \brief (TC1) Transfer Control Register (pdc = 1) */ -#define REG_TC1_PTSR1 (0x40094164U) /**< \brief (TC1) Transfer Status Register (pdc = 1) */ -#define REG_TC1_RPR2 (0x40094180U) /**< \brief (TC1) Receive Pointer Register (pdc = 2) */ -#define REG_TC1_RCR2 (0x40094184U) /**< \brief (TC1) Receive Counter Register (pdc = 2) */ -#define REG_TC1_RNPR2 (0x40094190U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 2) */ -#define REG_TC1_RNCR2 (0x40094194U) /**< \brief (TC1) Receive Next Counter Register (pdc = 2) */ -#define REG_TC1_PTCR2 (0x400941A0U) /**< \brief (TC1) Transfer Control Register (pdc = 2) */ -#define REG_TC1_PTSR2 (0x400941A4U) /**< \brief (TC1) Transfer Status Register (pdc = 2) */ -#else -#define REG_TC1_CCR0 (*(WoReg*)0x40094000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 (*(RwReg*)0x40094004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_SMMR0 (*(RwReg*)0x40094008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC1_RAB0 (*(RoReg*)0x4009400CU) /**< \brief (TC1) Register AB (channel = 0) */ -#define REG_TC1_CV0 (*(RoReg*)0x40094010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 (*(RwReg*)0x40094014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 (*(RwReg*)0x40094018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 (*(RwReg*)0x4009401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 (*(RoReg*)0x40094020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 (*(WoReg*)0x40094024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 (*(WoReg*)0x40094028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 (*(RoReg*)0x4009402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_EMR0 (*(RwReg*)0x40094030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ -#define REG_TC1_CCR1 (*(WoReg*)0x40094040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 (*(RwReg*)0x40094044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_SMMR1 (*(RwReg*)0x40094048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC1_RAB1 (*(RoReg*)0x4009404CU) /**< \brief (TC1) Register AB (channel = 1) */ -#define REG_TC1_CV1 (*(RoReg*)0x40094050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 (*(RwReg*)0x40094054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 (*(RwReg*)0x40094058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 (*(RwReg*)0x4009405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 (*(RoReg*)0x40094060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 (*(WoReg*)0x40094064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 (*(WoReg*)0x40094068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 (*(RoReg*)0x4009406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_EMR1 (*(RwReg*)0x40094070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ -#define REG_TC1_CCR2 (*(WoReg*)0x40094080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 (*(RwReg*)0x40094084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_SMMR2 (*(RwReg*)0x40094088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC1_RAB2 (*(RoReg*)0x4009408CU) /**< \brief (TC1) Register AB (channel = 2) */ -#define REG_TC1_CV2 (*(RoReg*)0x40094090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 (*(RwReg*)0x40094094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 (*(RwReg*)0x40094098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 (*(RwReg*)0x4009409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 (*(RoReg*)0x400940A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 (*(WoReg*)0x400940A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 (*(WoReg*)0x400940A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 (*(RoReg*)0x400940ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_EMR2 (*(RwReg*)0x400940B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ -#define REG_TC1_BCR (*(WoReg*)0x400940C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR (*(RwReg*)0x400940C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER (*(WoReg*)0x400940C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR (*(WoReg*)0x400940CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR (*(RoReg*)0x400940D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR (*(RoReg*)0x400940D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR (*(RwReg*)0x400940D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR (*(RwReg*)0x400940E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_RPR0 (*(RwReg*)0x40094100U) /**< \brief (TC1) Receive Pointer Register (pdc = 0) */ -#define REG_TC1_RCR0 (*(RwReg*)0x40094104U) /**< \brief (TC1) Receive Counter Register (pdc = 0) */ -#define REG_TC1_RNPR0 (*(RwReg*)0x40094110U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 0) */ -#define REG_TC1_RNCR0 (*(RwReg*)0x40094114U) /**< \brief (TC1) Receive Next Counter Register (pdc = 0) */ -#define REG_TC1_PTCR0 (*(WoReg*)0x40094120U) /**< \brief (TC1) Transfer Control Register (pdc = 0) */ -#define REG_TC1_PTSR0 (*(RoReg*)0x40094124U) /**< \brief (TC1) Transfer Status Register (pdc = 0) */ -#define REG_TC1_RPR1 (*(RwReg*)0x40094140U) /**< \brief (TC1) Receive Pointer Register (pdc = 1) */ -#define REG_TC1_RCR1 (*(RwReg*)0x40094144U) /**< \brief (TC1) Receive Counter Register (pdc = 1) */ -#define REG_TC1_RNPR1 (*(RwReg*)0x40094150U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 1) */ -#define REG_TC1_RNCR1 (*(RwReg*)0x40094154U) /**< \brief (TC1) Receive Next Counter Register (pdc = 1) */ -#define REG_TC1_PTCR1 (*(WoReg*)0x40094160U) /**< \brief (TC1) Transfer Control Register (pdc = 1) */ -#define REG_TC1_PTSR1 (*(RoReg*)0x40094164U) /**< \brief (TC1) Transfer Status Register (pdc = 1) */ -#define REG_TC1_RPR2 (*(RwReg*)0x40094180U) /**< \brief (TC1) Receive Pointer Register (pdc = 2) */ -#define REG_TC1_RCR2 (*(RwReg*)0x40094184U) /**< \brief (TC1) Receive Counter Register (pdc = 2) */ -#define REG_TC1_RNPR2 (*(RwReg*)0x40094190U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 2) */ -#define REG_TC1_RNCR2 (*(RwReg*)0x40094194U) /**< \brief (TC1) Receive Next Counter Register (pdc = 2) */ -#define REG_TC1_PTCR2 (*(WoReg*)0x400941A0U) /**< \brief (TC1) Transfer Control Register (pdc = 2) */ -#define REG_TC1_PTSR2 (*(RoReg*)0x400941A4U) /**< \brief (TC1) Transfer Status Register (pdc = 2) */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_TC1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc2.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc2.h deleted file mode 100644 index 73d8f3fa5..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/tc2.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_TC2_INSTANCE_ -#define _SAM4E_TC2_INSTANCE_ - -/* ========== Register definition for TC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC2_CCR0 (0x40098000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ -#define REG_TC2_CMR0 (0x40098004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ -#define REG_TC2_SMMR0 (0x40098008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC2_RAB0 (0x4009800CU) /**< \brief (TC2) Register AB (channel = 0) */ -#define REG_TC2_CV0 (0x40098010U) /**< \brief (TC2) Counter Value (channel = 0) */ -#define REG_TC2_RA0 (0x40098014U) /**< \brief (TC2) Register A (channel = 0) */ -#define REG_TC2_RB0 (0x40098018U) /**< \brief (TC2) Register B (channel = 0) */ -#define REG_TC2_RC0 (0x4009801CU) /**< \brief (TC2) Register C (channel = 0) */ -#define REG_TC2_SR0 (0x40098020U) /**< \brief (TC2) Status Register (channel = 0) */ -#define REG_TC2_IER0 (0x40098024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ -#define REG_TC2_IDR0 (0x40098028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ -#define REG_TC2_IMR0 (0x4009802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ -#define REG_TC2_EMR0 (0x40098030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ -#define REG_TC2_CCR1 (0x40098040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ -#define REG_TC2_CMR1 (0x40098044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ -#define REG_TC2_SMMR1 (0x40098048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC2_RAB1 (0x4009804CU) /**< \brief (TC2) Register AB (channel = 1) */ -#define REG_TC2_CV1 (0x40098050U) /**< \brief (TC2) Counter Value (channel = 1) */ -#define REG_TC2_RA1 (0x40098054U) /**< \brief (TC2) Register A (channel = 1) */ -#define REG_TC2_RB1 (0x40098058U) /**< \brief (TC2) Register B (channel = 1) */ -#define REG_TC2_RC1 (0x4009805CU) /**< \brief (TC2) Register C (channel = 1) */ -#define REG_TC2_SR1 (0x40098060U) /**< \brief (TC2) Status Register (channel = 1) */ -#define REG_TC2_IER1 (0x40098064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ -#define REG_TC2_IDR1 (0x40098068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ -#define REG_TC2_IMR1 (0x4009806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ -#define REG_TC2_EMR1 (0x40098070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ -#define REG_TC2_CCR2 (0x40098080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ -#define REG_TC2_CMR2 (0x40098084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ -#define REG_TC2_SMMR2 (0x40098088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC2_RAB2 (0x4009808CU) /**< \brief (TC2) Register AB (channel = 2) */ -#define REG_TC2_CV2 (0x40098090U) /**< \brief (TC2) Counter Value (channel = 2) */ -#define REG_TC2_RA2 (0x40098094U) /**< \brief (TC2) Register A (channel = 2) */ -#define REG_TC2_RB2 (0x40098098U) /**< \brief (TC2) Register B (channel = 2) */ -#define REG_TC2_RC2 (0x4009809CU) /**< \brief (TC2) Register C (channel = 2) */ -#define REG_TC2_SR2 (0x400980A0U) /**< \brief (TC2) Status Register (channel = 2) */ -#define REG_TC2_IER2 (0x400980A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ -#define REG_TC2_IDR2 (0x400980A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ -#define REG_TC2_IMR2 (0x400980ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ -#define REG_TC2_EMR2 (0x400980B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ -#define REG_TC2_BCR (0x400980C0U) /**< \brief (TC2) Block Control Register */ -#define REG_TC2_BMR (0x400980C4U) /**< \brief (TC2) Block Mode Register */ -#define REG_TC2_QIER (0x400980C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ -#define REG_TC2_QIDR (0x400980CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ -#define REG_TC2_QIMR (0x400980D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ -#define REG_TC2_QISR (0x400980D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ -#define REG_TC2_FMR (0x400980D8U) /**< \brief (TC2) Fault Mode Register */ -#define REG_TC2_WPMR (0x400980E4U) /**< \brief (TC2) Write Protect Mode Register */ -#else -#define REG_TC2_CCR0 (*(WoReg*)0x40098000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ -#define REG_TC2_CMR0 (*(RwReg*)0x40098004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ -#define REG_TC2_SMMR0 (*(RwReg*)0x40098008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ -#define REG_TC2_RAB0 (*(RoReg*)0x4009800CU) /**< \brief (TC2) Register AB (channel = 0) */ -#define REG_TC2_CV0 (*(RoReg*)0x40098010U) /**< \brief (TC2) Counter Value (channel = 0) */ -#define REG_TC2_RA0 (*(RwReg*)0x40098014U) /**< \brief (TC2) Register A (channel = 0) */ -#define REG_TC2_RB0 (*(RwReg*)0x40098018U) /**< \brief (TC2) Register B (channel = 0) */ -#define REG_TC2_RC0 (*(RwReg*)0x4009801CU) /**< \brief (TC2) Register C (channel = 0) */ -#define REG_TC2_SR0 (*(RoReg*)0x40098020U) /**< \brief (TC2) Status Register (channel = 0) */ -#define REG_TC2_IER0 (*(WoReg*)0x40098024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ -#define REG_TC2_IDR0 (*(WoReg*)0x40098028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ -#define REG_TC2_IMR0 (*(RoReg*)0x4009802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ -#define REG_TC2_EMR0 (*(RwReg*)0x40098030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ -#define REG_TC2_CCR1 (*(WoReg*)0x40098040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ -#define REG_TC2_CMR1 (*(RwReg*)0x40098044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ -#define REG_TC2_SMMR1 (*(RwReg*)0x40098048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ -#define REG_TC2_RAB1 (*(RoReg*)0x4009804CU) /**< \brief (TC2) Register AB (channel = 1) */ -#define REG_TC2_CV1 (*(RoReg*)0x40098050U) /**< \brief (TC2) Counter Value (channel = 1) */ -#define REG_TC2_RA1 (*(RwReg*)0x40098054U) /**< \brief (TC2) Register A (channel = 1) */ -#define REG_TC2_RB1 (*(RwReg*)0x40098058U) /**< \brief (TC2) Register B (channel = 1) */ -#define REG_TC2_RC1 (*(RwReg*)0x4009805CU) /**< \brief (TC2) Register C (channel = 1) */ -#define REG_TC2_SR1 (*(RoReg*)0x40098060U) /**< \brief (TC2) Status Register (channel = 1) */ -#define REG_TC2_IER1 (*(WoReg*)0x40098064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ -#define REG_TC2_IDR1 (*(WoReg*)0x40098068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ -#define REG_TC2_IMR1 (*(RoReg*)0x4009806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ -#define REG_TC2_EMR1 (*(RwReg*)0x40098070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ -#define REG_TC2_CCR2 (*(WoReg*)0x40098080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ -#define REG_TC2_CMR2 (*(RwReg*)0x40098084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ -#define REG_TC2_SMMR2 (*(RwReg*)0x40098088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ -#define REG_TC2_RAB2 (*(RoReg*)0x4009808CU) /**< \brief (TC2) Register AB (channel = 2) */ -#define REG_TC2_CV2 (*(RoReg*)0x40098090U) /**< \brief (TC2) Counter Value (channel = 2) */ -#define REG_TC2_RA2 (*(RwReg*)0x40098094U) /**< \brief (TC2) Register A (channel = 2) */ -#define REG_TC2_RB2 (*(RwReg*)0x40098098U) /**< \brief (TC2) Register B (channel = 2) */ -#define REG_TC2_RC2 (*(RwReg*)0x4009809CU) /**< \brief (TC2) Register C (channel = 2) */ -#define REG_TC2_SR2 (*(RoReg*)0x400980A0U) /**< \brief (TC2) Status Register (channel = 2) */ -#define REG_TC2_IER2 (*(WoReg*)0x400980A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ -#define REG_TC2_IDR2 (*(WoReg*)0x400980A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ -#define REG_TC2_IMR2 (*(RoReg*)0x400980ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ -#define REG_TC2_EMR2 (*(RwReg*)0x400980B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ -#define REG_TC2_BCR (*(WoReg*)0x400980C0U) /**< \brief (TC2) Block Control Register */ -#define REG_TC2_BMR (*(RwReg*)0x400980C4U) /**< \brief (TC2) Block Mode Register */ -#define REG_TC2_QIER (*(WoReg*)0x400980C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ -#define REG_TC2_QIDR (*(WoReg*)0x400980CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ -#define REG_TC2_QIMR (*(RoReg*)0x400980D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ -#define REG_TC2_QISR (*(RoReg*)0x400980D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ -#define REG_TC2_FMR (*(RwReg*)0x400980D8U) /**< \brief (TC2) Fault Mode Register */ -#define REG_TC2_WPMR (*(RwReg*)0x400980E4U) /**< \brief (TC2) Write Protect Mode Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_TC2_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/twi0.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/twi0.h deleted file mode 100644 index 88fe9eff5..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/twi0.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_TWI0_INSTANCE_ -#define _SAM4E_TWI0_INSTANCE_ - -/* ========== Register definition for TWI0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI0_CR (0x400A8000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR (0x400A8004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR (0x400A8008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR (0x400A800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR (0x400A8010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR (0x400A8020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER (0x400A8024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR (0x400A8028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR (0x400A802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR (0x400A8030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR (0x400A8034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_WPROT_MODE (0x400A80E4U) /**< \brief (TWI0) Protection Mode Register */ -#define REG_TWI0_WPROT_STATUS (0x400A80E8U) /**< \brief (TWI0) Protection Status Register */ -#define REG_TWI0_RPR (0x400A8100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR (0x400A8104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR (0x400A8108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR (0x400A810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR (0x400A8110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR (0x400A8114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR (0x400A8118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR (0x400A811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR (0x400A8120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR (0x400A8124U) /**< \brief (TWI0) Transfer Status Register */ -#else -#define REG_TWI0_CR (*(WoReg*)0x400A8000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR (*(RwReg*)0x400A8004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR (*(RwReg*)0x400A8008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR (*(RwReg*)0x400A800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR (*(RwReg*)0x400A8010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR (*(RoReg*)0x400A8020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER (*(WoReg*)0x400A8024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR (*(WoReg*)0x400A8028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR (*(RoReg*)0x400A802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR (*(RoReg*)0x400A8030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR (*(WoReg*)0x400A8034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_WPROT_MODE (*(RwReg*)0x400A80E4U) /**< \brief (TWI0) Protection Mode Register */ -#define REG_TWI0_WPROT_STATUS (*(RoReg*)0x400A80E8U) /**< \brief (TWI0) Protection Status Register */ -#define REG_TWI0_RPR (*(RwReg*)0x400A8100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR (*(RwReg*)0x400A8104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR (*(RwReg*)0x400A8108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR (*(RwReg*)0x400A810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR (*(RwReg*)0x400A8110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR (*(RwReg*)0x400A8114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR (*(RwReg*)0x400A8118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR (*(RwReg*)0x400A811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR (*(WoReg*)0x400A8120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR (*(RoReg*)0x400A8124U) /**< \brief (TWI0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_TWI0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/twi1.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/twi1.h deleted file mode 100644 index 172adb13e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/twi1.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_TWI1_INSTANCE_ -#define _SAM4E_TWI1_INSTANCE_ - -/* ========== Register definition for TWI1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TWI1_CR (0x400AC000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR (0x400AC004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR (0x400AC008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR (0x400AC00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR (0x400AC010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR (0x400AC020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER (0x400AC024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR (0x400AC028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR (0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR (0x400AC030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR (0x400AC034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_WPROT_MODE (0x400AC0E4U) /**< \brief (TWI1) Protection Mode Register */ -#define REG_TWI1_WPROT_STATUS (0x400AC0E8U) /**< \brief (TWI1) Protection Status Register */ -#define REG_TWI1_RPR (0x400AC100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR (0x400AC104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR (0x400AC108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR (0x400AC10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR (0x400AC110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR (0x400AC114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR (0x400AC118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR (0x400AC11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR (0x400AC120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR (0x400AC124U) /**< \brief (TWI1) Transfer Status Register */ -#else -#define REG_TWI1_CR (*(WoReg*)0x400AC000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR (*(RwReg*)0x400AC004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR (*(RwReg*)0x400AC008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR (*(RwReg*)0x400AC00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR (*(RwReg*)0x400AC010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR (*(RoReg*)0x400AC020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER (*(WoReg*)0x400AC024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR (*(WoReg*)0x400AC028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR (*(RoReg*)0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR (*(RoReg*)0x400AC030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR (*(WoReg*)0x400AC034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_WPROT_MODE (*(RwReg*)0x400AC0E4U) /**< \brief (TWI1) Protection Mode Register */ -#define REG_TWI1_WPROT_STATUS (*(RoReg*)0x400AC0E8U) /**< \brief (TWI1) Protection Status Register */ -#define REG_TWI1_RPR (*(RwReg*)0x400AC100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR (*(RwReg*)0x400AC104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR (*(RwReg*)0x400AC108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR (*(RwReg*)0x400AC10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR (*(RwReg*)0x400AC110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR (*(RwReg*)0x400AC114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR (*(RwReg*)0x400AC118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR (*(RwReg*)0x400AC11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR (*(WoReg*)0x400AC120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR (*(RoReg*)0x400AC124U) /**< \brief (TWI1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_TWI1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/uart0.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/uart0.h deleted file mode 100644 index 56877b7c8..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/uart0.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_UART0_INSTANCE_ -#define _SAM4E_UART0_INSTANCE_ - -/* ========== Register definition for UART0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -#else -#define REG_UART0_CR (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_UART0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/uart1.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/uart1.h deleted file mode 100644 index 2cd603110..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/uart1.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_UART1_INSTANCE_ -#define _SAM4E_UART1_INSTANCE_ - -/* ========== Register definition for UART1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_UART1_CR (0x40060600U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR (0x40060604U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER (0x40060608U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR (0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR (0x40060610U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR (0x40060614U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR (0x40060618U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR (0x4006061CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR (0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR (0x40060700U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR (0x40060704U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR (0x40060708U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR (0x4006070CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR (0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR (0x40060714U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR (0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR (0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR (0x40060720U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR (0x40060724U) /**< \brief (UART1) Transfer Status Register */ -#else -#define REG_UART1_CR (*(WoReg*)0x40060600U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR (*(RwReg*)0x40060604U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER (*(WoReg*)0x40060608U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR (*(WoReg*)0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR (*(RoReg*)0x40060610U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR (*(RoReg*)0x40060614U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR (*(RoReg*)0x40060618U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR (*(WoReg*)0x4006061CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR (*(RwReg*)0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR (*(RwReg*)0x40060700U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR (*(RwReg*)0x40060704U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR (*(RwReg*)0x40060708U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR (*(RwReg*)0x4006070CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR (*(RwReg*)0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR (*(RwReg*)0x40060714U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR (*(RwReg*)0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR (*(RwReg*)0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR (*(WoReg*)0x40060720U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR (*(RoReg*)0x40060724U) /**< \brief (UART1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_UART1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/udp.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/udp.h deleted file mode 100644 index a9f2115c8..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/udp.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_UDP_INSTANCE_ -#define _SAM4E_UDP_INSTANCE_ - -/* ========== Register definition for UDP peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_UDP_FRM_NUM (0x40084000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT (0x40084004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR (0x40084008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER (0x40084010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR (0x40084014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR (0x40084018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR (0x4008401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR (0x40084020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP (0x40084028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR (0x40084030U) /**< \brief (UDP) Endpoint Control and Status Register */ -#define REG_UDP_FDR (0x40084050U) /**< \brief (UDP) Endpoint FIFO Data Register */ -#define REG_UDP_TXVC (0x40084074U) /**< \brief (UDP) Transceiver Control Register */ -#else -#define REG_UDP_FRM_NUM (*(RoReg*)0x40084000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT (*(RwReg*)0x40084004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR (*(RwReg*)0x40084008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER (*(WoReg*)0x40084010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR (*(WoReg*)0x40084014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR (*(RoReg*)0x40084018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR (*(RoReg*)0x4008401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR (*(WoReg*)0x40084020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP (*(RwReg*)0x40084028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR (*(RwReg*)0x40084030U) /**< \brief (UDP) Endpoint Control and Status Register */ -#define REG_UDP_FDR (*(RwReg*)0x40084050U) /**< \brief (UDP) Endpoint FIFO Data Register */ -#define REG_UDP_TXVC (*(RwReg*)0x40084074U) /**< \brief (UDP) Transceiver Control Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_UDP_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/usart0.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/usart0.h deleted file mode 100644 index 6f9ae128d..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/usart0.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_USART0_INSTANCE_ -#define _SAM4E_USART0_INSTANCE_ - -/* ========== Register definition for USART0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART0_CR (0x400A0000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR (0x400A0004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER (0x400A0008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR (0x400A000CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR (0x400A0010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR (0x400A0014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR (0x400A0018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR (0x400A001CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR (0x400A0020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR (0x400A0024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR (0x400A0028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI (0x400A0040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER (0x400A0044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF (0x400A004CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN (0x400A0050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR (0x400A00E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR (0x400A00E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_RPR (0x400A0100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR (0x400A0104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR (0x400A0108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR (0x400A010CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR (0x400A0110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR (0x400A0114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR (0x400A0118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR (0x400A011CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR (0x400A0120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR (0x400A0124U) /**< \brief (USART0) Transfer Status Register */ -#else -#define REG_USART0_CR (*(WoReg*)0x400A0000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR (*(RwReg*)0x400A0004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER (*(WoReg*)0x400A0008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR (*(WoReg*)0x400A001CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER (*(RoReg*)0x400A0044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF (*(RwReg*)0x400A004CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART0) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_USART0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/usart1.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/usart1.h deleted file mode 100644 index 54385ee4b..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/usart1.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_USART1_INSTANCE_ -#define _SAM4E_USART1_INSTANCE_ - -/* ========== Register definition for USART1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USART1_CR (0x400A4000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR (0x400A4004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER (0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR (0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR (0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR (0x400A4014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR (0x400A4018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR (0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR (0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR (0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR (0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI (0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER (0x400A4044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF (0x400A404CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN (0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR (0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR (0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_RPR (0x400A4100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR (0x400A4104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR (0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR (0x400A410CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR (0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR (0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR (0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR (0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR (0x400A4120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR (0x400A4124U) /**< \brief (USART1) Transfer Status Register */ -#else -#define REG_USART1_CR (*(WoReg*)0x400A4000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR (*(RwReg*)0x400A4004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER (*(WoReg*)0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR (*(WoReg*)0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER (*(RoReg*)0x400A4044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF (*(RwReg*)0x400A404CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART1) Transfer Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_USART1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/wdt.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/wdt.h deleted file mode 100644 index 11d837506..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/instance/wdt.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_WDT_INSTANCE_ -#define _SAM4E_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */ -#else -#define REG_WDT_CR (*(WoReg*)0x400E1850U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR (*(RwReg*)0x400E1854U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR (*(RoReg*)0x400E1858U) /**< \brief (WDT) Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_WDT_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e16c.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e16c.h deleted file mode 100644 index 019224f3a..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e16c.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E16C_PIO_ -#define _SAM4E16C_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -/* ========== Pio definition for AFEC0 peripheral ========== */ -#define PIO_PA17X1_AFE0_AD0 (1u << 17) /**< \brief Afec0 signal: AFE0_AD0 */ -#define PIO_PA18X1_AFE0_AD1 (1u << 18) /**< \brief Afec0 signal: AFE0_AD1 */ -#define PIO_PC30X1_AFE0_AD10 (1u << 30) /**< \brief Afec0 signal: AFE0_AD10 */ -#define PIO_PC31X1_AFE0_AD11 (1u << 31) /**< \brief Afec0 signal: AFE0_AD11 */ -#define PIO_PC26X1_AFE0_AD12 (1u << 26) /**< \brief Afec0 signal: AFE0_AD12 */ -#define PIO_PC27X1_AFE0_AD13 (1u << 27) /**< \brief Afec0 signal: AFE0_AD13 */ -#define PIO_PC0X1_AFE0_AD14 (1u << 0) /**< \brief Afec0 signal: AFE0_AD14 */ -#define PIO_PA19X1_AFE0_AD2 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */ -#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */ -#define PIO_PA20X1_AFE0_AD3 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */ -#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */ -#define PIO_PB0X1_AFE0_AD4 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */ -#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */ -#define PIO_PB1X1_AFE0_AD5 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */ -#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */ -#define PIO_PC13X1_AFE0_AD6 (1u << 13) /**< \brief Afec0 signal: AFE0_AD6 */ -#define PIO_PC15X1_AFE0_AD7 (1u << 15) /**< \brief Afec0 signal: AFE0_AD7 */ -#define PIO_PC12X1_AFE0_AD8 (1u << 12) /**< \brief Afec0 signal: AFE0_AD8 */ -#define PIO_PC29X1_AFE0_AD9 (1u << 29) /**< \brief Afec0 signal: AFE0_AD9 */ -#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ -/* ========== Pio definition for AFEC1 peripheral ========== */ -#define PIO_PB2X1_AFE1_AD0 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */ -#define PIO_PB3X1_AFE1_AD1 (1u << 3) /**< \brief Afec1 signal: AFE1_AD1 */ -#define PIO_PA21X1_AFE1_AD2 (1u << 21) /**< \brief Afec1 signal: AFE1_AD2 */ -#define PIO_PA22X1_AFE1_AD3 (1u << 22) /**< \brief Afec1 signal: AFE1_AD3 */ -#define PIO_PC1X1_AFE1_AD4 (1u << 1) /**< \brief Afec1 signal: AFE1_AD4 */ -#define PIO_PC2X1_AFE1_AD5 (1u << 2) /**< \brief Afec1 signal: AFE1_AD5 */ -#define PIO_PC3X1_AFE1_AD6 (1u << 3) /**< \brief Afec1 signal: AFE1_AD6 */ -#define PIO_PC4X1_AFE1_AD7 (1u << 4) /**< \brief Afec1 signal: AFE1_AD7 */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PC15C_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for GMAC peripheral ========== */ -#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ -#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ -#define PIO_PD4A_GCRSDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */ -#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */ -#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ -#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ -#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ -#define PIO_PD6A_GRX0 (1u << 6) /**< \brief Gmac signal: GRX0 */ -#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ -#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ -#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ -#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ -#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ -#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ -#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ -#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ -#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */ -#define PIO_PD0A_GREFCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */ -#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ -#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA31X1_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA30X1_WKUP11 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */ -#define PIO_PA30X1_PIODC6 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */ -#define PIO_PA15X1_WKUP14 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */ -#define PIO_PA15X1_PIODCEN1 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */ -#define PIO_PA16X1_WKUP15 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */ -#define PIO_PA16X1_PIODCEN2 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PD20A_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PD21A_PWMH1 (1u << 21) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PD22A_PWMH2 (1u << 22) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PD23A_PWMH3 (1u << 23) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PD24A_PWML0 (1u << 24) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PD25A_PWML1 (1u << 25) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PD26A_PWML2 (1u << 26) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PD27A_PWML3 (1u << 27) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PC31_IDX 95 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PD31_IDX 127 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 - -#endif /* _SAM4E16C_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e16e.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e16e.h deleted file mode 100644 index 2036936ef..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e16e.h +++ /dev/null @@ -1,537 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E16E_PIO_ -#define _SAM4E16E_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -/* ========== Pio definition for AFEC0 peripheral ========== */ -#define PIO_PA17X1_AFE0_AD0 (1u << 17) /**< \brief Afec0 signal: AFE0_AD0 */ -#define PIO_PA18X1_AFE0_AD1 (1u << 18) /**< \brief Afec0 signal: AFE0_AD1 */ -#define PIO_PC30X1_AFE0_AD10 (1u << 30) /**< \brief Afec0 signal: AFE0_AD10 */ -#define PIO_PC31X1_AFE0_AD11 (1u << 31) /**< \brief Afec0 signal: AFE0_AD11 */ -#define PIO_PC26X1_AFE0_AD12 (1u << 26) /**< \brief Afec0 signal: AFE0_AD12 */ -#define PIO_PC27X1_AFE0_AD13 (1u << 27) /**< \brief Afec0 signal: AFE0_AD13 */ -#define PIO_PC0X1_AFE0_AD14 (1u << 0) /**< \brief Afec0 signal: AFE0_AD14 */ -#define PIO_PA19X1_AFE0_AD2 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */ -#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */ -#define PIO_PA20X1_AFE0_AD3 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */ -#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */ -#define PIO_PB0X1_AFE0_AD4 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */ -#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */ -#define PIO_PB1X1_AFE0_AD5 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */ -#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */ -#define PIO_PC13X1_AFE0_AD6 (1u << 13) /**< \brief Afec0 signal: AFE0_AD6 */ -#define PIO_PC15X1_AFE0_AD7 (1u << 15) /**< \brief Afec0 signal: AFE0_AD7 */ -#define PIO_PC12X1_AFE0_AD8 (1u << 12) /**< \brief Afec0 signal: AFE0_AD8 */ -#define PIO_PC29X1_AFE0_AD9 (1u << 29) /**< \brief Afec0 signal: AFE0_AD9 */ -#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ -/* ========== Pio definition for AFEC1 peripheral ========== */ -#define PIO_PB2X1_AFE1_AD0 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */ -#define PIO_PB3X1_AFE1_AD1 (1u << 3) /**< \brief Afec1 signal: AFE1_AD1 */ -#define PIO_PA21X1_AFE1_AD2 (1u << 21) /**< \brief Afec1 signal: AFE1_AD2 */ -#define PIO_PA22X1_AFE1_AD3 (1u << 22) /**< \brief Afec1 signal: AFE1_AD3 */ -#define PIO_PC1X1_AFE1_AD4 (1u << 1) /**< \brief Afec1 signal: AFE1_AD4 */ -#define PIO_PC2X1_AFE1_AD5 (1u << 2) /**< \brief Afec1 signal: AFE1_AD5 */ -#define PIO_PC3X1_AFE1_AD6 (1u << 3) /**< \brief Afec1 signal: AFE1_AD6 */ -#define PIO_PC4X1_AFE1_AD7 (1u << 4) /**< \brief Afec1 signal: AFE1_AD7 */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PC15C_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EBI peripheral ========== */ -#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */ -#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ -#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ -#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ -#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ -#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ -#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ -#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ -#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */ -#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */ -#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ -#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ -#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ -#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ -#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ -#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ -#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ -#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ -#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ -#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ -#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ -#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ -#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ -#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ -#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ -#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ -#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ -#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ -#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ -#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ -#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ -#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ -#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ -#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */ -#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1 */ -#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ -#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ -#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ -#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ -#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ -#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */ -/* ========== Pio definition for GMAC peripheral ========== */ -#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ -#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ -#define PIO_PD4A_GCRSDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */ -#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */ -#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ -#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ -#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ -#define PIO_PD6A_GRX0 (1u << 6) /**< \brief Gmac signal: GRX0 */ -#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ -#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ -#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ -#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ -#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ -#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ -#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ -#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ -#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */ -#define PIO_PD0A_GREFCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */ -#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ -#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA31X1_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA30X1_WKUP11 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */ -#define PIO_PA30X1_PIODC6 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */ -#define PIO_PA15X1_WKUP14 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */ -#define PIO_PA15X1_PIODCEN1 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */ -#define PIO_PA16X1_WKUP15 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */ -#define PIO_PA16X1_PIODCEN2 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PD20A_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PD21A_PWMH1 (1u << 21) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PD22A_PWMH2 (1u << 22) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PD23A_PWMH3 (1u << 23) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PD24A_PWML0 (1u << 24) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PD25A_PWML1 (1u << 25) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PD26A_PWML2 (1u << 26) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PD27A_PWML3 (1u << 27) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PC31_IDX 95 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PD31_IDX 127 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 - -#endif /* _SAM4E16E_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e8c.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e8c.h deleted file mode 100644 index 0db996918..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e8c.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E8C_PIO_ -#define _SAM4E8C_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -/* ========== Pio definition for AFEC0 peripheral ========== */ -#define PIO_PA17X1_AFE0_AD0 (1u << 17) /**< \brief Afec0 signal: AFE0_AD0 */ -#define PIO_PA18X1_AFE0_AD1 (1u << 18) /**< \brief Afec0 signal: AFE0_AD1 */ -#define PIO_PC30X1_AFE0_AD10 (1u << 30) /**< \brief Afec0 signal: AFE0_AD10 */ -#define PIO_PC31X1_AFE0_AD11 (1u << 31) /**< \brief Afec0 signal: AFE0_AD11 */ -#define PIO_PC26X1_AFE0_AD12 (1u << 26) /**< \brief Afec0 signal: AFE0_AD12 */ -#define PIO_PC27X1_AFE0_AD13 (1u << 27) /**< \brief Afec0 signal: AFE0_AD13 */ -#define PIO_PC0X1_AFE0_AD14 (1u << 0) /**< \brief Afec0 signal: AFE0_AD14 */ -#define PIO_PA19X1_AFE0_AD2 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */ -#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */ -#define PIO_PA20X1_AFE0_AD3 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */ -#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */ -#define PIO_PB0X1_AFE0_AD4 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */ -#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */ -#define PIO_PB1X1_AFE0_AD5 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */ -#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */ -#define PIO_PC13X1_AFE0_AD6 (1u << 13) /**< \brief Afec0 signal: AFE0_AD6 */ -#define PIO_PC15X1_AFE0_AD7 (1u << 15) /**< \brief Afec0 signal: AFE0_AD7 */ -#define PIO_PC12X1_AFE0_AD8 (1u << 12) /**< \brief Afec0 signal: AFE0_AD8 */ -#define PIO_PC29X1_AFE0_AD9 (1u << 29) /**< \brief Afec0 signal: AFE0_AD9 */ -#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ -/* ========== Pio definition for AFEC1 peripheral ========== */ -#define PIO_PB2X1_AFE1_AD0 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */ -#define PIO_PB3X1_AFE1_AD1 (1u << 3) /**< \brief Afec1 signal: AFE1_AD1 */ -#define PIO_PA21X1_AFE1_AD2 (1u << 21) /**< \brief Afec1 signal: AFE1_AD2 */ -#define PIO_PA22X1_AFE1_AD3 (1u << 22) /**< \brief Afec1 signal: AFE1_AD3 */ -#define PIO_PC1X1_AFE1_AD4 (1u << 1) /**< \brief Afec1 signal: AFE1_AD4 */ -#define PIO_PC2X1_AFE1_AD5 (1u << 2) /**< \brief Afec1 signal: AFE1_AD5 */ -#define PIO_PC3X1_AFE1_AD6 (1u << 3) /**< \brief Afec1 signal: AFE1_AD6 */ -#define PIO_PC4X1_AFE1_AD7 (1u << 4) /**< \brief Afec1 signal: AFE1_AD7 */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PC15C_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for GMAC peripheral ========== */ -#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ -#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ -#define PIO_PD4A_GCRSDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */ -#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */ -#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ -#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ -#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ -#define PIO_PD6A_GRX0 (1u << 6) /**< \brief Gmac signal: GRX0 */ -#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ -#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ -#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ -#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ -#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ -#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ -#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ -#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ -#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */ -#define PIO_PD0A_GREFCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */ -#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ -#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA31X1_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA30X1_WKUP11 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */ -#define PIO_PA30X1_PIODC6 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */ -#define PIO_PA15X1_WKUP14 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */ -#define PIO_PA15X1_PIODCEN1 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */ -#define PIO_PA16X1_WKUP15 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */ -#define PIO_PA16X1_PIODCEN2 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PD20A_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PD21A_PWMH1 (1u << 21) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PD22A_PWMH2 (1u << 22) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PD23A_PWMH3 (1u << 23) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PD24A_PWML0 (1u << 24) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PD25A_PWML1 (1u << 25) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PD26A_PWML2 (1u << 26) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PD27A_PWML3 (1u << 27) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PC31_IDX 95 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PD31_IDX 127 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 - -#endif /* _SAM4E8C_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e8e.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e8e.h deleted file mode 100644 index c9af41d46..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e8e.h +++ /dev/null @@ -1,537 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E8E_PIO_ -#define _SAM4E8E_PIO_ - -#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ -#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ -#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ -#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ -#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ -#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ -#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ -#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ -#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ -#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ -#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ -#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ -#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ -#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ -#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ -#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ -#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ -#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ -#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ -#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ -#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ -#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ -#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ -#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ -#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ -#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ -#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ -#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ -#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ -#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ -#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ -#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ -#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ -#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ -#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ -#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ -#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ -#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ -#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ -/* ========== Pio definition for AFEC0 peripheral ========== */ -#define PIO_PA17X1_AFE0_AD0 (1u << 17) /**< \brief Afec0 signal: AFE0_AD0 */ -#define PIO_PA18X1_AFE0_AD1 (1u << 18) /**< \brief Afec0 signal: AFE0_AD1 */ -#define PIO_PC30X1_AFE0_AD10 (1u << 30) /**< \brief Afec0 signal: AFE0_AD10 */ -#define PIO_PC31X1_AFE0_AD11 (1u << 31) /**< \brief Afec0 signal: AFE0_AD11 */ -#define PIO_PC26X1_AFE0_AD12 (1u << 26) /**< \brief Afec0 signal: AFE0_AD12 */ -#define PIO_PC27X1_AFE0_AD13 (1u << 27) /**< \brief Afec0 signal: AFE0_AD13 */ -#define PIO_PC0X1_AFE0_AD14 (1u << 0) /**< \brief Afec0 signal: AFE0_AD14 */ -#define PIO_PA19X1_AFE0_AD2 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */ -#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */ -#define PIO_PA20X1_AFE0_AD3 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */ -#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */ -#define PIO_PB0X1_AFE0_AD4 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */ -#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */ -#define PIO_PB1X1_AFE0_AD5 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */ -#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */ -#define PIO_PC13X1_AFE0_AD6 (1u << 13) /**< \brief Afec0 signal: AFE0_AD6 */ -#define PIO_PC15X1_AFE0_AD7 (1u << 15) /**< \brief Afec0 signal: AFE0_AD7 */ -#define PIO_PC12X1_AFE0_AD8 (1u << 12) /**< \brief Afec0 signal: AFE0_AD8 */ -#define PIO_PC29X1_AFE0_AD9 (1u << 29) /**< \brief Afec0 signal: AFE0_AD9 */ -#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ -/* ========== Pio definition for AFEC1 peripheral ========== */ -#define PIO_PB2X1_AFE1_AD0 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */ -#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */ -#define PIO_PB3X1_AFE1_AD1 (1u << 3) /**< \brief Afec1 signal: AFE1_AD1 */ -#define PIO_PA21X1_AFE1_AD2 (1u << 21) /**< \brief Afec1 signal: AFE1_AD2 */ -#define PIO_PA22X1_AFE1_AD3 (1u << 22) /**< \brief Afec1 signal: AFE1_AD3 */ -#define PIO_PC1X1_AFE1_AD4 (1u << 1) /**< \brief Afec1 signal: AFE1_AD4 */ -#define PIO_PC2X1_AFE1_AD5 (1u << 2) /**< \brief Afec1 signal: AFE1_AD5 */ -#define PIO_PC3X1_AFE1_AD6 (1u << 3) /**< \brief Afec1 signal: AFE1_AD6 */ -#define PIO_PC4X1_AFE1_AD7 (1u << 4) /**< \brief Afec1 signal: AFE1_AD7 */ -/* ========== Pio definition for CAN0 peripheral ========== */ -#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Can0 signal: CANRX0 */ -#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Can0 signal: CANTX0 */ -/* ========== Pio definition for CAN1 peripheral ========== */ -#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Can1 signal: CANRX1 */ -#define PIO_PC15C_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for EBI peripheral ========== */ -#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */ -#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ -#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ -#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ -#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ -#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ -#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ -#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ -#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */ -#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */ -#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ -#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ -#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ -#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ -#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ -#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ -#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ -#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ -#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ -#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ -#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ -#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ -#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ -#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ -#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ -#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ -#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ -#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ -#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ -#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ -#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ -#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ -#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ -#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ -#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ -#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */ -#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1 */ -#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ -#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ -#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ -#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ -#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ -#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */ -/* ========== Pio definition for GMAC peripheral ========== */ -#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ -#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ -#define PIO_PD4A_GCRSDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */ -#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */ -#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ -#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ -#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ -#define PIO_PD6A_GRX0 (1u << 6) /**< \brief Gmac signal: GRX0 */ -#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ -#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ -#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ -#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ -#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ -#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ -#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ -#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ -#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */ -#define PIO_PD0A_GREFCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */ -#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ -#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA31X1_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA30X1_WKUP11 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */ -#define PIO_PA30X1_PIODC6 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */ -#define PIO_PA15X1_WKUP14 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */ -#define PIO_PA15X1_PIODCEN1 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */ -#define PIO_PA16X1_WKUP15 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */ -#define PIO_PA16X1_PIODCEN2 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PD20A_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PD21A_PWMH1 (1u << 21) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PD22A_PWMH2 (1u << 22) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PD23A_PWMH3 (1u << 23) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PD24A_PWML0 (1u << 24) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PD25A_PWML1 (1u << 25) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PD26A_PWML2 (1u << 26) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PD27A_PWML3 (1u << 27) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TC2 peripheral ========== */ -#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ -#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ -#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ -#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ -#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ -#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ -#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ -#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ -#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio indexes ========== */ -#define PIO_PA0_IDX 0 -#define PIO_PA1_IDX 1 -#define PIO_PA2_IDX 2 -#define PIO_PA3_IDX 3 -#define PIO_PA4_IDX 4 -#define PIO_PA5_IDX 5 -#define PIO_PA6_IDX 6 -#define PIO_PA7_IDX 7 -#define PIO_PA8_IDX 8 -#define PIO_PA9_IDX 9 -#define PIO_PA10_IDX 10 -#define PIO_PA11_IDX 11 -#define PIO_PA12_IDX 12 -#define PIO_PA13_IDX 13 -#define PIO_PA14_IDX 14 -#define PIO_PA15_IDX 15 -#define PIO_PA16_IDX 16 -#define PIO_PA17_IDX 17 -#define PIO_PA18_IDX 18 -#define PIO_PA19_IDX 19 -#define PIO_PA20_IDX 20 -#define PIO_PA21_IDX 21 -#define PIO_PA22_IDX 22 -#define PIO_PA23_IDX 23 -#define PIO_PA24_IDX 24 -#define PIO_PA25_IDX 25 -#define PIO_PA26_IDX 26 -#define PIO_PA27_IDX 27 -#define PIO_PA28_IDX 28 -#define PIO_PA29_IDX 29 -#define PIO_PA30_IDX 30 -#define PIO_PA31_IDX 31 -#define PIO_PB0_IDX 32 -#define PIO_PB1_IDX 33 -#define PIO_PB2_IDX 34 -#define PIO_PB3_IDX 35 -#define PIO_PB4_IDX 36 -#define PIO_PB5_IDX 37 -#define PIO_PB6_IDX 38 -#define PIO_PB7_IDX 39 -#define PIO_PB8_IDX 40 -#define PIO_PB9_IDX 41 -#define PIO_PB10_IDX 42 -#define PIO_PB11_IDX 43 -#define PIO_PB12_IDX 44 -#define PIO_PB13_IDX 45 -#define PIO_PB14_IDX 46 -#define PIO_PC0_IDX 64 -#define PIO_PC1_IDX 65 -#define PIO_PC2_IDX 66 -#define PIO_PC3_IDX 67 -#define PIO_PC4_IDX 68 -#define PIO_PC5_IDX 69 -#define PIO_PC6_IDX 70 -#define PIO_PC7_IDX 71 -#define PIO_PC8_IDX 72 -#define PIO_PC9_IDX 73 -#define PIO_PC10_IDX 74 -#define PIO_PC11_IDX 75 -#define PIO_PC12_IDX 76 -#define PIO_PC13_IDX 77 -#define PIO_PC14_IDX 78 -#define PIO_PC15_IDX 79 -#define PIO_PC16_IDX 80 -#define PIO_PC17_IDX 81 -#define PIO_PC18_IDX 82 -#define PIO_PC19_IDX 83 -#define PIO_PC20_IDX 84 -#define PIO_PC21_IDX 85 -#define PIO_PC22_IDX 86 -#define PIO_PC23_IDX 87 -#define PIO_PC24_IDX 88 -#define PIO_PC25_IDX 89 -#define PIO_PC26_IDX 90 -#define PIO_PC27_IDX 91 -#define PIO_PC28_IDX 92 -#define PIO_PC29_IDX 93 -#define PIO_PC30_IDX 94 -#define PIO_PC31_IDX 95 -#define PIO_PD0_IDX 96 -#define PIO_PD1_IDX 97 -#define PIO_PD2_IDX 98 -#define PIO_PD3_IDX 99 -#define PIO_PD4_IDX 100 -#define PIO_PD5_IDX 101 -#define PIO_PD6_IDX 102 -#define PIO_PD7_IDX 103 -#define PIO_PD8_IDX 104 -#define PIO_PD9_IDX 105 -#define PIO_PD10_IDX 106 -#define PIO_PD11_IDX 107 -#define PIO_PD12_IDX 108 -#define PIO_PD13_IDX 109 -#define PIO_PD14_IDX 110 -#define PIO_PD15_IDX 111 -#define PIO_PD16_IDX 112 -#define PIO_PD17_IDX 113 -#define PIO_PD18_IDX 114 -#define PIO_PD19_IDX 115 -#define PIO_PD20_IDX 116 -#define PIO_PD21_IDX 117 -#define PIO_PD22_IDX 118 -#define PIO_PD23_IDX 119 -#define PIO_PD24_IDX 120 -#define PIO_PD25_IDX 121 -#define PIO_PD26_IDX 122 -#define PIO_PD27_IDX 123 -#define PIO_PD28_IDX 124 -#define PIO_PD29_IDX 125 -#define PIO_PD30_IDX 126 -#define PIO_PD31_IDX 127 -#define PIO_PE0_IDX 128 -#define PIO_PE1_IDX 129 -#define PIO_PE2_IDX 130 -#define PIO_PE3_IDX 131 -#define PIO_PE4_IDX 132 -#define PIO_PE5_IDX 133 - -#endif /* _SAM4E8E_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e.h deleted file mode 100644 index 304248ebe..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E_ -#define _SAM4E_ - -#if defined __SAM4E8C__ - #include "sam4e8c.h" -#elif defined __SAM4E8E__ - #include "sam4e8e.h" -#elif defined __SAM4E16C__ - #include "sam4e16c.h" -#elif defined __SAM4E16E__ - #include "sam4e16e.h" -#else - #error Library does not support the specified device. -#endif - -#endif /* _SAM4E_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e16c.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e16c.h deleted file mode 100644 index 908b7ca39..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e16c.h +++ /dev/null @@ -1,590 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E16C_ -#define _SAM4E16C_ - -/** \addtogroup SAM4E16C_definitions SAM4E16C definitions - This file defines all structures and symbols for SAM4E16C: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM4E16C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16C_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ -/****** SAM4E16C specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM4E16C Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM4E16C Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM4E16C Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM4E16C Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM4E16C Watchdog/Dual Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM4E16C Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAM4E16C Enhanced Embedded Flash Controller (EFC) */ - UART0_IRQn = 7, /**< 7 SAM4E16C UART 0 (UART0) */ - PIOA_IRQn = 9, /**< 9 SAM4E16C Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 10, /**< 10 SAM4E16C Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 11, /**< 11 SAM4E16C Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 SAM4E16C USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 SAM4E16C USART 1 (USART1) */ - HSMCI_IRQn = 16, /**< 16 SAM4E16C Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 17, /**< 17 SAM4E16C Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 18, /**< 18 SAM4E16C Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 19, /**< 19 SAM4E16C Serial Peripheral Interface (SPI) */ - DMAC_IRQn = 20, /**< 20 SAM4E16C DMAC (DMAC) */ - TC0_IRQn = 21, /**< 21 SAM4E16C Timer/Counter 0 (TC0) */ - TC1_IRQn = 22, /**< 22 SAM4E16C Timer/Counter 1 (TC1) */ - TC2_IRQn = 23, /**< 23 SAM4E16C Timer/Counter 2 (TC2) */ - TC3_IRQn = 24, /**< 24 SAM4E16C Timer/Counter 3 (TC3) */ - TC4_IRQn = 25, /**< 25 SAM4E16C Timer/Counter 4 (TC4) */ - TC5_IRQn = 26, /**< 26 SAM4E16C Timer/Counter 5 (TC5) */ - TC6_IRQn = 27, /**< 27 SAM4E16C Timer/Counter 6 (TC6) */ - TC7_IRQn = 28, /**< 28 SAM4E16C Timer/Counter 7 (TC7) */ - TC8_IRQn = 29, /**< 29 SAM4E16C Timer/Counter 8 (TC8) */ - AFEC0_IRQn = 30, /**< 30 SAM4E16C Analog Front End 0 (AFEC0) */ - AFEC1_IRQn = 31, /**< 31 SAM4E16C Analog Front End 1 (AFEC1) */ - DACC_IRQn = 32, /**< 32 SAM4E16C Digital To Analog Converter (DACC) */ - ACC_IRQn = 33, /**< 33 SAM4E16C Analog Comparator (ACC) */ - ARM_IRQn = 34, /**< 34 SAM4E16C FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ - UDP_IRQn = 35, /**< 35 SAM4E16C USB DEVICE (UDP) */ - PWM_IRQn = 36, /**< 36 SAM4E16C PWM (PWM) */ - CAN0_IRQn = 37, /**< 37 SAM4E16C CAN0 (CAN0) */ - CAN1_IRQn = 38, /**< 38 SAM4E16C CAN1 (CAN1) */ - AES_IRQn = 39, /**< 39 SAM4E16C AES (AES) */ - UART1_IRQn = 45, /**< 45 SAM4E16C UART (UART1) */ - - PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ - void* pfnUART0_Handler; /* 7 UART 0 */ - void* pvReserved8; - void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */ - void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */ - void* pvReserved12; - void* pvReserved13; - void* pfnUSART0_Handler; /* 14 USART 0 */ - void* pfnUSART1_Handler; /* 15 USART 1 */ - void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */ - void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */ - void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */ - void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */ - void* pfnDMAC_Handler; /* 20 DMAC */ - void* pfnTC0_Handler; /* 21 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 22 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 23 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 24 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 25 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 26 Timer/Counter 5 */ - void* pfnTC6_Handler; /* 27 Timer/Counter 6 */ - void* pfnTC7_Handler; /* 28 Timer/Counter 7 */ - void* pfnTC8_Handler; /* 29 Timer/Counter 8 */ - void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */ - void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */ - void* pfnDACC_Handler; /* 32 Digital To Analog Converter */ - void* pfnACC_Handler; /* 33 Analog Comparator */ - void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */ - void* pfnUDP_Handler; /* 35 USB DEVICE */ - void* pfnPWM_Handler; /* 36 PWM */ - void* pfnCAN0_Handler; /* 37 CAN0 */ - void* pfnCAN1_Handler; /* 38 CAN1 */ - void* pfnAES_Handler; /* 39 AES */ - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnUART1_Handler; /* 45 UART */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ACC_Handler ( void ); -void AES_Handler ( void ); -void AFEC0_Handler ( void ); -void AFEC1_Handler ( void ); -void ARM_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void DACC_Handler ( void ); -void DMAC_Handler ( void ); -void EFC_Handler ( void ); -void HSMCI_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PIOC_Handler ( void ); -void PMC_Handler ( void ); -void PWM_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SPI_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void TC8_Handler ( void ); -void TWI0_Handler ( void ); -void TWI1_Handler ( void ); -void UART0_Handler ( void ); -void UART1_Handler ( void ); -void UDP_Handler ( void ); -void USART0_Handler ( void ); -void USART1_Handler ( void ); -void WDT_Handler ( void ); - -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0000 /**< SAM4E16C core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 0 /**< SAM4E16C does not provide a MPU */ -#define __FPU_PRESENT 1 /**< SAM4E16C does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM4E16C uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_sam4e.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E16C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16C_api Peripheral Software API */ -/*@{*/ - -#include "component/acc.h" -#include "component/aes.h" -#include "component/afec.h" -#include "component/can.h" -#include "component/chipid.h" -#include "component/cmcc.h" -#include "component/crccu.h" -#include "component/dacc.h" -#include "component/dmac.h" -#include "component/efc.h" -#include "component/gpbr.h" -#include "component/hsmci.h" -#include "component/matrix.h" -#include "component/pdc.h" -#include "component/pio.h" -#include "component/pmc.h" -#include "component/pwm.h" -#include "component/rstc.h" -#include "component/rswdt.h" -#include "component/rtc.h" -#include "component/rtt.h" -#include "component/spi.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/twi.h" -#include "component/uart.h" -#include "component/udp.h" -#include "component/usart.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM4E16C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16C_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/pwm.h" -#include "instance/aes.h" -#include "instance/can0.h" -#include "instance/can1.h" -#include "instance/crccu.h" -#include "instance/uart1.h" -#include "instance/hsmci.h" -#include "instance/udp.h" -#include "instance/spi.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/usart0.h" -#include "instance/usart1.h" -#include "instance/twi0.h" -#include "instance/twi1.h" -#include "instance/afec0.h" -#include "instance/afec1.h" -#include "instance/dacc.h" -#include "instance/acc.h" -#include "instance/dmac.h" -#include "instance/cmcc.h" -#include "instance/matrix.h" -#include "instance/pmc.h" -#include "instance/uart0.h" -#include "instance/chipid.h" -#include "instance/efc.h" -#include "instance/pioa.h" -#include "instance/piob.h" -#include "instance/pioc.h" -#include "instance/rstc.h" -#include "instance/supc.h" -#include "instance/rtt.h" -#include "instance/wdt.h" -#include "instance/rtc.h" -#include "instance/gpbr.h" -#include "instance/rswdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM4E16C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16C_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ -#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ -#define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_DMAC (20) /**< \brief DMAC (DMAC) */ -#define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */ -#define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */ -#define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */ -#define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */ -#define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */ -#define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ -#define ID_UDP (35) /**< \brief USB DEVICE (UDP) */ -#define ID_PWM (36) /**< \brief PWM (PWM) */ -#define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */ -#define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */ -#define ID_AES (39) /**< \brief AES (AES) */ -#define ID_UART1 (45) /**< \brief UART (UART1) */ - -#define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM4E16C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16C_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define PWM (0x40000000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */ -#define AES (0x40004000U) /**< \brief (AES ) Base Address */ -#define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */ -#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ -#define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define UDP (0x40084000U) /**< \brief (UDP ) Base Address */ -#define SPI (0x40088000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */ -#define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ -#define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */ -#define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */ -#define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */ -#define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ -#define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */ -#define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ -#define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */ -#define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */ -#define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ -#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ -#else -#define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */ -#define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */ -#define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */ -#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ -#define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */ -#define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */ -#define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ -#define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */ -#define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */ -#define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */ -#define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ -#define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */ -#define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ -#define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */ -#define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */ -#define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ -#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM4E16C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16C_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/sam4e16c.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM4E16C */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x100000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (2048u) -#define IFLASH_NB_OF_LOCK_BITS (128u) -#define IRAM_SIZE (0x20000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAM4E16C */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3703FUL) -#define CHIP_CIDR (0xA3CC0CE0UL) -#define CHIP_EXID (0x00110201UL) -#define NB_CH_AFE0 (6UL) -#define NB_CH_AFE1 (4UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM4E16C */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) -#define CHIP_FREQ_XTAL_12M (12000000UL) - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (6U) - -/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM4E16C_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e16e.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e16e.h deleted file mode 100644 index 8a1437d3b..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e16e.h +++ /dev/null @@ -1,614 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E16E_ -#define _SAM4E16E_ - -/** \addtogroup SAM4E16E_definitions SAM4E16E definitions - This file defines all structures and symbols for SAM4E16E: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM4E16E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16E_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ -/****** SAM4E16E specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM4E16E Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM4E16E Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM4E16E Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM4E16E Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM4E16E Watchdog/Dual Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM4E16E Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAM4E16E Enhanced Embedded Flash Controller (EFC) */ - UART0_IRQn = 7, /**< 7 SAM4E16E UART 0 (UART0) */ - PIOA_IRQn = 9, /**< 9 SAM4E16E Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 10, /**< 10 SAM4E16E Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 11, /**< 11 SAM4E16E Parallel I/O Controller C (PIOC) */ - PIOD_IRQn = 12, /**< 12 SAM4E16E Parallel I/O Controller D (PIOD) */ - PIOE_IRQn = 13, /**< 13 SAM4E16E Parallel I/O Controller E (PIOE) */ - USART0_IRQn = 14, /**< 14 SAM4E16E USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 SAM4E16E USART 1 (USART1) */ - HSMCI_IRQn = 16, /**< 16 SAM4E16E Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 17, /**< 17 SAM4E16E Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 18, /**< 18 SAM4E16E Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 19, /**< 19 SAM4E16E Serial Peripheral Interface (SPI) */ - DMAC_IRQn = 20, /**< 20 SAM4E16E DMAC (DMAC) */ - TC0_IRQn = 21, /**< 21 SAM4E16E Timer/Counter 0 (TC0) */ - TC1_IRQn = 22, /**< 22 SAM4E16E Timer/Counter 1 (TC1) */ - TC2_IRQn = 23, /**< 23 SAM4E16E Timer/Counter 2 (TC2) */ - TC3_IRQn = 24, /**< 24 SAM4E16E Timer/Counter 3 (TC3) */ - TC4_IRQn = 25, /**< 25 SAM4E16E Timer/Counter 4 (TC4) */ - TC5_IRQn = 26, /**< 26 SAM4E16E Timer/Counter 5 (TC5) */ - TC6_IRQn = 27, /**< 27 SAM4E16E Timer/Counter 6 (TC6) */ - TC7_IRQn = 28, /**< 28 SAM4E16E Timer/Counter 7 (TC7) */ - TC8_IRQn = 29, /**< 29 SAM4E16E Timer/Counter 8 (TC8) */ - AFEC0_IRQn = 30, /**< 30 SAM4E16E Analog Front End 0 (AFEC0) */ - AFEC1_IRQn = 31, /**< 31 SAM4E16E Analog Front End 1 (AFEC1) */ - DACC_IRQn = 32, /**< 32 SAM4E16E Digital To Analog Converter (DACC) */ - ACC_IRQn = 33, /**< 33 SAM4E16E Analog Comparator (ACC) */ - ARM_IRQn = 34, /**< 34 SAM4E16E FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ - UDP_IRQn = 35, /**< 35 SAM4E16E USB DEVICE (UDP) */ - PWM_IRQn = 36, /**< 36 SAM4E16E PWM (PWM) */ - CAN0_IRQn = 37, /**< 37 SAM4E16E CAN0 (CAN0) */ - CAN1_IRQn = 38, /**< 38 SAM4E16E CAN1 (CAN1) */ - AES_IRQn = 39, /**< 39 SAM4E16E AES (AES) */ - GMAC_IRQn = 44, /**< 44 SAM4E16E EMAC (GMAC) */ - UART1_IRQn = 45, /**< 45 SAM4E16E UART (UART1) */ - - PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ - void* pfnUART0_Handler; /* 7 UART 0 */ - void* pvReserved8; - void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */ - void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */ - void* pfnPIOD_Handler; /* 12 Parallel I/O Controller D */ - void* pfnPIOE_Handler; /* 13 Parallel I/O Controller E */ - void* pfnUSART0_Handler; /* 14 USART 0 */ - void* pfnUSART1_Handler; /* 15 USART 1 */ - void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */ - void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */ - void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */ - void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */ - void* pfnDMAC_Handler; /* 20 DMAC */ - void* pfnTC0_Handler; /* 21 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 22 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 23 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 24 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 25 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 26 Timer/Counter 5 */ - void* pfnTC6_Handler; /* 27 Timer/Counter 6 */ - void* pfnTC7_Handler; /* 28 Timer/Counter 7 */ - void* pfnTC8_Handler; /* 29 Timer/Counter 8 */ - void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */ - void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */ - void* pfnDACC_Handler; /* 32 Digital To Analog Converter */ - void* pfnACC_Handler; /* 33 Analog Comparator */ - void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */ - void* pfnUDP_Handler; /* 35 USB DEVICE */ - void* pfnPWM_Handler; /* 36 PWM */ - void* pfnCAN0_Handler; /* 37 CAN0 */ - void* pfnCAN1_Handler; /* 38 CAN1 */ - void* pfnAES_Handler; /* 39 AES */ - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pfnGMAC_Handler; /* 44 EMAC */ - void* pfnUART1_Handler; /* 45 UART */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ACC_Handler ( void ); -void AES_Handler ( void ); -void AFEC0_Handler ( void ); -void AFEC1_Handler ( void ); -void ARM_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void DACC_Handler ( void ); -void DMAC_Handler ( void ); -void EFC_Handler ( void ); -void GMAC_Handler ( void ); -void HSMCI_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PIOC_Handler ( void ); -void PIOD_Handler ( void ); -void PIOE_Handler ( void ); -void PMC_Handler ( void ); -void PWM_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SPI_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void TC8_Handler ( void ); -void TWI0_Handler ( void ); -void TWI1_Handler ( void ); -void UART0_Handler ( void ); -void UART1_Handler ( void ); -void UDP_Handler ( void ); -void USART0_Handler ( void ); -void USART1_Handler ( void ); -void WDT_Handler ( void ); - -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0000 /**< SAM4E16E core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 0 /**< SAM4E16E does not provide a MPU */ -#define __FPU_PRESENT 1 /**< SAM4E16E does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM4E16E uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_sam4e.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E16E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16E_api Peripheral Software API */ -/*@{*/ - -#include "component/acc.h" -#include "component/aes.h" -#include "component/afec.h" -#include "component/can.h" -#include "component/chipid.h" -#include "component/cmcc.h" -#include "component/crccu.h" -#include "component/dacc.h" -#include "component/dmac.h" -#include "component/efc.h" -#include "component/gmac.h" -#include "component/gpbr.h" -#include "component/hsmci.h" -#include "component/matrix.h" -#include "component/pdc.h" -#include "component/pio.h" -#include "component/pmc.h" -#include "component/pwm.h" -#include "component/rstc.h" -#include "component/rswdt.h" -#include "component/rtc.h" -#include "component/rtt.h" -#include "component/smc.h" -#include "component/spi.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/twi.h" -#include "component/uart.h" -#include "component/udp.h" -#include "component/usart.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM4E16E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16E_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/pwm.h" -#include "instance/aes.h" -#include "instance/can0.h" -#include "instance/can1.h" -#include "instance/gmac.h" -#include "instance/crccu.h" -#include "instance/smc.h" -#include "instance/uart1.h" -#include "instance/hsmci.h" -#include "instance/udp.h" -#include "instance/spi.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/usart0.h" -#include "instance/usart1.h" -#include "instance/twi0.h" -#include "instance/twi1.h" -#include "instance/afec0.h" -#include "instance/afec1.h" -#include "instance/dacc.h" -#include "instance/acc.h" -#include "instance/dmac.h" -#include "instance/cmcc.h" -#include "instance/matrix.h" -#include "instance/pmc.h" -#include "instance/uart0.h" -#include "instance/chipid.h" -#include "instance/efc.h" -#include "instance/pioa.h" -#include "instance/piob.h" -#include "instance/pioc.h" -#include "instance/piod.h" -#include "instance/pioe.h" -#include "instance/rstc.h" -#include "instance/supc.h" -#include "instance/rtt.h" -#include "instance/wdt.h" -#include "instance/rtc.h" -#include "instance/gpbr.h" -#include "instance/rswdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM4E16E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16E_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ -#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ -#define ID_SMC ( 8) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_PIOD (12) /**< \brief Parallel I/O Controller D (PIOD) */ -#define ID_PIOE (13) /**< \brief Parallel I/O Controller E (PIOE) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_DMAC (20) /**< \brief DMAC (DMAC) */ -#define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */ -#define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */ -#define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */ -#define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */ -#define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */ -#define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ -#define ID_UDP (35) /**< \brief USB DEVICE (UDP) */ -#define ID_PWM (36) /**< \brief PWM (PWM) */ -#define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */ -#define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */ -#define ID_AES (39) /**< \brief AES (AES) */ -#define ID_GMAC (44) /**< \brief EMAC (GMAC) */ -#define ID_UART1 (45) /**< \brief UART (UART1) */ - -#define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM4E16E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16E_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define PWM (0x40000000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */ -#define AES (0x40004000U) /**< \brief (AES ) Base Address */ -#define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */ -#define GMAC (0x40034000U) /**< \brief (GMAC ) Base Address */ -#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC (0x40060000U) /**< \brief (SMC ) Base Address */ -#define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ -#define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define UDP (0x40084000U) /**< \brief (UDP ) Base Address */ -#define SPI (0x40088000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */ -#define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ -#define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */ -#define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */ -#define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */ -#define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ -#define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */ -#define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ -#define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */ -#define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */ -#define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ -#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ -#else -#define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */ -#define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */ -#define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */ -#define GMAC ((Gmac *)0x40034000U) /**< \brief (GMAC ) Base Address */ -#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC ((Smc *)0x40060000U) /**< \brief (SMC ) Base Address */ -#define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ -#define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */ -#define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */ -#define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ -#define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */ -#define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */ -#define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */ -#define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ -#define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */ -#define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ -#define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */ -#define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */ -#define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ -#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM4E16E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E16E_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/sam4e16e.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM4E16E */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x100000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (2048u) -#define IFLASH_NB_OF_LOCK_BITS (128u) -#define IRAM_SIZE (0x20000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAM4E16E */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3703FUL) -#define CHIP_CIDR (0xA3CC0CE0UL) -#define CHIP_EXID (0x00120200UL) -#define NB_CH_AFE0 (16UL) -#define NB_CH_AFE1 (8UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM4E16E */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) -#define CHIP_FREQ_XTAL_12M (12000000UL) - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (6U) - -/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM4E16E_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e8c.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e8c.h deleted file mode 100644 index c1e34cab2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e8c.h +++ /dev/null @@ -1,590 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E8C_ -#define _SAM4E8C_ - -/** \addtogroup SAM4E8C_definitions SAM4E8C definitions - This file defines all structures and symbols for SAM4E8C: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM4E8C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8C_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ -/****** SAM4E8C specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM4E8C Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM4E8C Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM4E8C Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM4E8C Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM4E8C Watchdog/Dual Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM4E8C Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAM4E8C Enhanced Embedded Flash Controller (EFC) */ - UART0_IRQn = 7, /**< 7 SAM4E8C UART 0 (UART0) */ - PIOA_IRQn = 9, /**< 9 SAM4E8C Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 10, /**< 10 SAM4E8C Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 11, /**< 11 SAM4E8C Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 SAM4E8C USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 SAM4E8C USART 1 (USART1) */ - HSMCI_IRQn = 16, /**< 16 SAM4E8C Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 17, /**< 17 SAM4E8C Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 18, /**< 18 SAM4E8C Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 19, /**< 19 SAM4E8C Serial Peripheral Interface (SPI) */ - DMAC_IRQn = 20, /**< 20 SAM4E8C DMAC (DMAC) */ - TC0_IRQn = 21, /**< 21 SAM4E8C Timer/Counter 0 (TC0) */ - TC1_IRQn = 22, /**< 22 SAM4E8C Timer/Counter 1 (TC1) */ - TC2_IRQn = 23, /**< 23 SAM4E8C Timer/Counter 2 (TC2) */ - TC3_IRQn = 24, /**< 24 SAM4E8C Timer/Counter 3 (TC3) */ - TC4_IRQn = 25, /**< 25 SAM4E8C Timer/Counter 4 (TC4) */ - TC5_IRQn = 26, /**< 26 SAM4E8C Timer/Counter 5 (TC5) */ - TC6_IRQn = 27, /**< 27 SAM4E8C Timer/Counter 6 (TC6) */ - TC7_IRQn = 28, /**< 28 SAM4E8C Timer/Counter 7 (TC7) */ - TC8_IRQn = 29, /**< 29 SAM4E8C Timer/Counter 8 (TC8) */ - AFEC0_IRQn = 30, /**< 30 SAM4E8C Analog Front End 0 (AFEC0) */ - AFEC1_IRQn = 31, /**< 31 SAM4E8C Analog Front End 1 (AFEC1) */ - DACC_IRQn = 32, /**< 32 SAM4E8C Digital To Analog Converter (DACC) */ - ACC_IRQn = 33, /**< 33 SAM4E8C Analog Comparator (ACC) */ - ARM_IRQn = 34, /**< 34 SAM4E8C FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ - UDP_IRQn = 35, /**< 35 SAM4E8C USB DEVICE (UDP) */ - PWM_IRQn = 36, /**< 36 SAM4E8C PWM (PWM) */ - CAN0_IRQn = 37, /**< 37 SAM4E8C CAN0 (CAN0) */ - CAN1_IRQn = 38, /**< 38 SAM4E8C CAN1 (CAN1) */ - AES_IRQn = 39, /**< 39 SAM4E8C AES (AES) */ - UART1_IRQn = 45, /**< 45 SAM4E8C UART (UART1) */ - - PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ - void* pfnUART0_Handler; /* 7 UART 0 */ - void* pvReserved8; - void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */ - void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */ - void* pvReserved12; - void* pvReserved13; - void* pfnUSART0_Handler; /* 14 USART 0 */ - void* pfnUSART1_Handler; /* 15 USART 1 */ - void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */ - void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */ - void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */ - void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */ - void* pfnDMAC_Handler; /* 20 DMAC */ - void* pfnTC0_Handler; /* 21 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 22 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 23 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 24 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 25 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 26 Timer/Counter 5 */ - void* pfnTC6_Handler; /* 27 Timer/Counter 6 */ - void* pfnTC7_Handler; /* 28 Timer/Counter 7 */ - void* pfnTC8_Handler; /* 29 Timer/Counter 8 */ - void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */ - void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */ - void* pfnDACC_Handler; /* 32 Digital To Analog Converter */ - void* pfnACC_Handler; /* 33 Analog Comparator */ - void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */ - void* pfnUDP_Handler; /* 35 USB DEVICE */ - void* pfnPWM_Handler; /* 36 PWM */ - void* pfnCAN0_Handler; /* 37 CAN0 */ - void* pfnCAN1_Handler; /* 38 CAN1 */ - void* pfnAES_Handler; /* 39 AES */ - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnUART1_Handler; /* 45 UART */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ACC_Handler ( void ); -void AES_Handler ( void ); -void AFEC0_Handler ( void ); -void AFEC1_Handler ( void ); -void ARM_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void DACC_Handler ( void ); -void DMAC_Handler ( void ); -void EFC_Handler ( void ); -void HSMCI_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PIOC_Handler ( void ); -void PMC_Handler ( void ); -void PWM_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SPI_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void TC8_Handler ( void ); -void TWI0_Handler ( void ); -void TWI1_Handler ( void ); -void UART0_Handler ( void ); -void UART1_Handler ( void ); -void UDP_Handler ( void ); -void USART0_Handler ( void ); -void USART1_Handler ( void ); -void WDT_Handler ( void ); - -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0000 /**< SAM4E8C core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 0 /**< SAM4E8C does not provide a MPU */ -#define __FPU_PRESENT 1 /**< SAM4E8C does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM4E8C uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_sam4e.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E8C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8C_api Peripheral Software API */ -/*@{*/ - -#include "component/acc.h" -#include "component/aes.h" -#include "component/afec.h" -#include "component/can.h" -#include "component/chipid.h" -#include "component/cmcc.h" -#include "component/crccu.h" -#include "component/dacc.h" -#include "component/dmac.h" -#include "component/efc.h" -#include "component/gpbr.h" -#include "component/hsmci.h" -#include "component/matrix.h" -#include "component/pdc.h" -#include "component/pio.h" -#include "component/pmc.h" -#include "component/pwm.h" -#include "component/rstc.h" -#include "component/rswdt.h" -#include "component/rtc.h" -#include "component/rtt.h" -#include "component/spi.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/twi.h" -#include "component/uart.h" -#include "component/udp.h" -#include "component/usart.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM4E8C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8C_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/pwm.h" -#include "instance/aes.h" -#include "instance/can0.h" -#include "instance/can1.h" -#include "instance/crccu.h" -#include "instance/uart1.h" -#include "instance/hsmci.h" -#include "instance/udp.h" -#include "instance/spi.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/usart0.h" -#include "instance/usart1.h" -#include "instance/twi0.h" -#include "instance/twi1.h" -#include "instance/afec0.h" -#include "instance/afec1.h" -#include "instance/dacc.h" -#include "instance/acc.h" -#include "instance/dmac.h" -#include "instance/cmcc.h" -#include "instance/matrix.h" -#include "instance/pmc.h" -#include "instance/uart0.h" -#include "instance/chipid.h" -#include "instance/efc.h" -#include "instance/pioa.h" -#include "instance/piob.h" -#include "instance/pioc.h" -#include "instance/rstc.h" -#include "instance/supc.h" -#include "instance/rtt.h" -#include "instance/wdt.h" -#include "instance/rtc.h" -#include "instance/gpbr.h" -#include "instance/rswdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM4E8C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8C_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ -#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ -#define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_DMAC (20) /**< \brief DMAC (DMAC) */ -#define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */ -#define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */ -#define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */ -#define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */ -#define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */ -#define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ -#define ID_UDP (35) /**< \brief USB DEVICE (UDP) */ -#define ID_PWM (36) /**< \brief PWM (PWM) */ -#define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */ -#define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */ -#define ID_AES (39) /**< \brief AES (AES) */ -#define ID_UART1 (45) /**< \brief UART (UART1) */ - -#define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM4E8C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8C_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define PWM (0x40000000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */ -#define AES (0x40004000U) /**< \brief (AES ) Base Address */ -#define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */ -#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ -#define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define UDP (0x40084000U) /**< \brief (UDP ) Base Address */ -#define SPI (0x40088000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */ -#define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ -#define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */ -#define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */ -#define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */ -#define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ -#define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */ -#define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ -#define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */ -#define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */ -#define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ -#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ -#else -#define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */ -#define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */ -#define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */ -#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ -#define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */ -#define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */ -#define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ -#define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */ -#define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */ -#define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */ -#define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ -#define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */ -#define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ -#define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */ -#define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */ -#define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ -#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM4E8C */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8C_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/sam4e8c.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM4E8C */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x80000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (1024u) -#define IFLASH_NB_OF_LOCK_BITS (128u) -#define IRAM_SIZE (0x20000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAM4E8C */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3703FUL) -#define CHIP_CIDR (0xA3CC0CE0UL) -#define CHIP_EXID (0x00110209UL) -#define NB_CH_AFE0 (6UL) -#define NB_CH_AFE1 (4UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM4E8C */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) -#define CHIP_FREQ_XTAL_12M (12000000UL) - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (6U) - -/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM4E8C_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e8e.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e8e.h deleted file mode 100644 index add9c353b..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/include/sam4e8e.h +++ /dev/null @@ -1,614 +0,0 @@ -/** - * \file - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM4E8E_ -#define _SAM4E8E_ - -/** \addtogroup SAM4E8E_definitions SAM4E8E definitions - This file defines all structures and symbols for SAM4E8E: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#endif - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAM4E8E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8E_cmsis CMSIS Definitions */ -/*@{*/ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ -/****** SAM4E8E specific Interrupt Numbers *********************************/ - - SUPC_IRQn = 0, /**< 0 SAM4E8E Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 SAM4E8E Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 SAM4E8E Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 SAM4E8E Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 SAM4E8E Watchdog/Dual Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 SAM4E8E Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 SAM4E8E Enhanced Embedded Flash Controller (EFC) */ - UART0_IRQn = 7, /**< 7 SAM4E8E UART 0 (UART0) */ - PIOA_IRQn = 9, /**< 9 SAM4E8E Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 10, /**< 10 SAM4E8E Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 11, /**< 11 SAM4E8E Parallel I/O Controller C (PIOC) */ - PIOD_IRQn = 12, /**< 12 SAM4E8E Parallel I/O Controller D (PIOD) */ - PIOE_IRQn = 13, /**< 13 SAM4E8E Parallel I/O Controller E (PIOE) */ - USART0_IRQn = 14, /**< 14 SAM4E8E USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 SAM4E8E USART 1 (USART1) */ - HSMCI_IRQn = 16, /**< 16 SAM4E8E Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 17, /**< 17 SAM4E8E Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 18, /**< 18 SAM4E8E Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 19, /**< 19 SAM4E8E Serial Peripheral Interface (SPI) */ - DMAC_IRQn = 20, /**< 20 SAM4E8E DMAC (DMAC) */ - TC0_IRQn = 21, /**< 21 SAM4E8E Timer/Counter 0 (TC0) */ - TC1_IRQn = 22, /**< 22 SAM4E8E Timer/Counter 1 (TC1) */ - TC2_IRQn = 23, /**< 23 SAM4E8E Timer/Counter 2 (TC2) */ - TC3_IRQn = 24, /**< 24 SAM4E8E Timer/Counter 3 (TC3) */ - TC4_IRQn = 25, /**< 25 SAM4E8E Timer/Counter 4 (TC4) */ - TC5_IRQn = 26, /**< 26 SAM4E8E Timer/Counter 5 (TC5) */ - TC6_IRQn = 27, /**< 27 SAM4E8E Timer/Counter 6 (TC6) */ - TC7_IRQn = 28, /**< 28 SAM4E8E Timer/Counter 7 (TC7) */ - TC8_IRQn = 29, /**< 29 SAM4E8E Timer/Counter 8 (TC8) */ - AFEC0_IRQn = 30, /**< 30 SAM4E8E Analog Front End 0 (AFEC0) */ - AFEC1_IRQn = 31, /**< 31 SAM4E8E Analog Front End 1 (AFEC1) */ - DACC_IRQn = 32, /**< 32 SAM4E8E Digital To Analog Converter (DACC) */ - ACC_IRQn = 33, /**< 33 SAM4E8E Analog Comparator (ACC) */ - ARM_IRQn = 34, /**< 34 SAM4E8E FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ - UDP_IRQn = 35, /**< 35 SAM4E8E USB DEVICE (UDP) */ - PWM_IRQn = 36, /**< 36 SAM4E8E PWM (PWM) */ - CAN0_IRQn = 37, /**< 37 SAM4E8E CAN0 (CAN0) */ - CAN1_IRQn = 38, /**< 38 SAM4E8E CAN1 (CAN1) */ - AES_IRQn = 39, /**< 39 SAM4E8E AES (AES) */ - GMAC_IRQn = 44, /**< 44 SAM4E8E EMAC (GMAC) */ - UART1_IRQn = 45, /**< 45 SAM4E8E UART (UART1) */ - - PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pfnReserved1_Handler; - void* pfnReserved2_Handler; - void* pfnReserved3_Handler; - void* pfnReserved4_Handler; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pfnReserved5_Handler; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSUPC_Handler; /* 0 Supply Controller */ - void* pfnRSTC_Handler; /* 1 Reset Controller */ - void* pfnRTC_Handler; /* 2 Real Time Clock */ - void* pfnRTT_Handler; /* 3 Real Time Timer */ - void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */ - void* pfnPMC_Handler; /* 5 Power Management Controller */ - void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ - void* pfnUART0_Handler; /* 7 UART 0 */ - void* pvReserved8; - void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */ - void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */ - void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */ - void* pfnPIOD_Handler; /* 12 Parallel I/O Controller D */ - void* pfnPIOE_Handler; /* 13 Parallel I/O Controller E */ - void* pfnUSART0_Handler; /* 14 USART 0 */ - void* pfnUSART1_Handler; /* 15 USART 1 */ - void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */ - void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */ - void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */ - void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */ - void* pfnDMAC_Handler; /* 20 DMAC */ - void* pfnTC0_Handler; /* 21 Timer/Counter 0 */ - void* pfnTC1_Handler; /* 22 Timer/Counter 1 */ - void* pfnTC2_Handler; /* 23 Timer/Counter 2 */ - void* pfnTC3_Handler; /* 24 Timer/Counter 3 */ - void* pfnTC4_Handler; /* 25 Timer/Counter 4 */ - void* pfnTC5_Handler; /* 26 Timer/Counter 5 */ - void* pfnTC6_Handler; /* 27 Timer/Counter 6 */ - void* pfnTC7_Handler; /* 28 Timer/Counter 7 */ - void* pfnTC8_Handler; /* 29 Timer/Counter 8 */ - void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */ - void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */ - void* pfnDACC_Handler; /* 32 Digital To Analog Converter */ - void* pfnACC_Handler; /* 33 Analog Comparator */ - void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */ - void* pfnUDP_Handler; /* 35 USB DEVICE */ - void* pfnPWM_Handler; /* 36 PWM */ - void* pfnCAN0_Handler; /* 37 CAN0 */ - void* pfnCAN1_Handler; /* 38 CAN1 */ - void* pfnAES_Handler; /* 39 AES */ - void* pvReserved40; - void* pvReserved41; - void* pvReserved42; - void* pvReserved43; - void* pfnGMAC_Handler; /* 44 EMAC */ - void* pfnUART1_Handler; /* 45 UART */ -} DeviceVectors; - -/* Cortex-M4 core handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void ACC_Handler ( void ); -void AES_Handler ( void ); -void AFEC0_Handler ( void ); -void AFEC1_Handler ( void ); -void ARM_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void DACC_Handler ( void ); -void DMAC_Handler ( void ); -void EFC_Handler ( void ); -void GMAC_Handler ( void ); -void HSMCI_Handler ( void ); -void PIOA_Handler ( void ); -void PIOB_Handler ( void ); -void PIOC_Handler ( void ); -void PIOD_Handler ( void ); -void PIOE_Handler ( void ); -void PMC_Handler ( void ); -void PWM_Handler ( void ); -void RSTC_Handler ( void ); -void RTC_Handler ( void ); -void RTT_Handler ( void ); -void SPI_Handler ( void ); -void SUPC_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void TC8_Handler ( void ); -void TWI0_Handler ( void ); -void TWI1_Handler ( void ); -void UART0_Handler ( void ); -void UART1_Handler ( void ); -void UDP_Handler ( void ); -void USART0_Handler ( void ); -void USART1_Handler ( void ); -void WDT_Handler ( void ); - -/** - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 0x0000 /**< SAM4E8E core revision number ([15:8] revision number, [7:0] patch number) */ -#define __MPU_PRESENT 0 /**< SAM4E8E does not provide a MPU */ -#define __FPU_PRESENT 1 /**< SAM4E8E does provide a FPU */ -#define __NVIC_PRIO_BITS 4 /**< SAM4E8E uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/* - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_sam4e.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E8E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8E_api Peripheral Software API */ -/*@{*/ - -#include "component/acc.h" -#include "component/aes.h" -#include "component/afec.h" -#include "component/can.h" -#include "component/chipid.h" -#include "component/cmcc.h" -#include "component/crccu.h" -#include "component/dacc.h" -#include "component/dmac.h" -#include "component/efc.h" -#include "component/gmac.h" -#include "component/gpbr.h" -#include "component/hsmci.h" -#include "component/matrix.h" -#include "component/pdc.h" -#include "component/pio.h" -#include "component/pmc.h" -#include "component/pwm.h" -#include "component/rstc.h" -#include "component/rswdt.h" -#include "component/rtc.h" -#include "component/rtt.h" -#include "component/smc.h" -#include "component/spi.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/twi.h" -#include "component/uart.h" -#include "component/udp.h" -#include "component/usart.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR SAM4E8E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8E_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/pwm.h" -#include "instance/aes.h" -#include "instance/can0.h" -#include "instance/can1.h" -#include "instance/gmac.h" -#include "instance/crccu.h" -#include "instance/smc.h" -#include "instance/uart1.h" -#include "instance/hsmci.h" -#include "instance/udp.h" -#include "instance/spi.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/usart0.h" -#include "instance/usart1.h" -#include "instance/twi0.h" -#include "instance/twi1.h" -#include "instance/afec0.h" -#include "instance/afec1.h" -#include "instance/dacc.h" -#include "instance/acc.h" -#include "instance/dmac.h" -#include "instance/cmcc.h" -#include "instance/matrix.h" -#include "instance/pmc.h" -#include "instance/uart0.h" -#include "instance/chipid.h" -#include "instance/efc.h" -#include "instance/pioa.h" -#include "instance/piob.h" -#include "instance/pioc.h" -#include "instance/piod.h" -#include "instance/pioe.h" -#include "instance/rstc.h" -#include "instance/supc.h" -#include "instance/rtt.h" -#include "instance/wdt.h" -#include "instance/rtc.h" -#include "instance/gpbr.h" -#include "instance/rswdt.h" -/*@}*/ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAM4E8E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8E_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ -#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ -#define ID_SMC ( 8) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_PIOD (12) /**< \brief Parallel I/O Controller D (PIOD) */ -#define ID_PIOE (13) /**< \brief Parallel I/O Controller E (PIOE) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_DMAC (20) /**< \brief DMAC (DMAC) */ -#define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */ -#define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */ -#define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */ -#define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */ -#define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */ -#define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ -#define ID_UDP (35) /**< \brief USB DEVICE (UDP) */ -#define ID_PWM (36) /**< \brief PWM (PWM) */ -#define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */ -#define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */ -#define ID_AES (39) /**< \brief AES (AES) */ -#define ID_GMAC (44) /**< \brief EMAC (GMAC) */ -#define ID_UART1 (45) /**< \brief UART (UART1) */ - -#define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAM4E8E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8E_base Peripheral Base Address Definitions */ -/*@{*/ - -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define PWM (0x40000000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */ -#define AES (0x40004000U) /**< \brief (AES ) Base Address */ -#define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */ -#define GMAC (0x40034000U) /**< \brief (GMAC ) Base Address */ -#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC (0x40060000U) /**< \brief (SMC ) Base Address */ -#define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ -#define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define UDP (0x40084000U) /**< \brief (UDP ) Base Address */ -#define SPI (0x40088000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */ -#define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ -#define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */ -#define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */ -#define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */ -#define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ -#define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */ -#define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ -#define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */ -#define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */ -#define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */ -#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ -#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ -#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ -#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ -#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ -#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ -#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ -#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ -#else -#define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */ -#define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */ -#define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */ -#define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */ -#define GMAC ((Gmac *)0x40034000U) /**< \brief (GMAC ) Base Address */ -#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC ((Smc *)0x40060000U) /**< \brief (SMC ) Base Address */ -#define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ -#define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */ -#define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */ -#define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ -#define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */ -#define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ -#define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */ -#define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */ -#define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */ -#define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ -#define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */ -#define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ -#define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */ -#define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */ -#define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */ -#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ -#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ -#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ -#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ -#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ -#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ -#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ -#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ -#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ -#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAM4E8E */ -/* ************************************************************************** */ -/** \addtogroup SAM4E8E_pio Peripheral Pio Definitions */ -/*@{*/ - -#include "pio/sam4e8e.h" -/*@}*/ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAM4E8E */ -/* ************************************************************************** */ - -#define IFLASH_SIZE (0x80000u) -#define IFLASH_PAGE_SIZE (512u) -#define IFLASH_LOCK_REGION_SIZE (8192u) -#define IFLASH_NB_OF_PAGES (1024u) -#define IFLASH_NB_OF_LOCK_BITS (128u) -#define IRAM_SIZE (0x20000u) - -#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ -#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ -#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ -#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ -#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ -#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ -#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ - -/* ************************************************************************** */ -/* MISCELLANEOUS DEFINITIONS FOR SAM4E8E */ -/* ************************************************************************** */ - -#define CHIP_JTAGID (0x05B3703FUL) -#define CHIP_CIDR (0xA3CC0CE0UL) -#define CHIP_EXID (0x00120208UL) -#define NB_CH_AFE0 (16UL) -#define NB_CH_AFE1 (8UL) - -/* ************************************************************************** */ -/* ELECTRICAL DEFINITIONS FOR SAM4E8E */ -/* ************************************************************************** */ - -/* Device characteristics */ -#define CHIP_FREQ_SLCK_RC_MIN (20000UL) -#define CHIP_FREQ_SLCK_RC (32000UL) -#define CHIP_FREQ_SLCK_RC_MAX (44000UL) -#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) -#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) -#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) -#define CHIP_FREQ_CPU_MAX (120000000UL) -#define CHIP_FREQ_XTAL_32K (32768UL) -#define CHIP_FREQ_XTAL_12M (12000000UL) - -/* Embedded Flash Write Wait State */ -#define CHIP_FLASH_WRITE_WAIT_STATE (6U) - -/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ -#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ -#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ -#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ -#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ -#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ -#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _SAM4E8E_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/exceptions.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/exceptions.c deleted file mode 100644 index 57990ba5a..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/exceptions.c +++ /dev/null @@ -1,202 +0,0 @@ -/** - * \file - * - * \brief This file contains the default exception handlers. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \par Purpose - * - * This file provides basic support for Cortex-M processor based - * microcontrollers. - * - * \note - * The exception handler has weak aliases. - * As they are weak aliases, any function with the same name will override - * this definition. - * - */ - -#include "exceptions.h" - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/* @endcond */ - -#ifdef __GNUC__ -void Dummy_Hardfault_Handler( void ); -/* Cortex-M4 core handlers */ -void Reset_Handler (void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Hardfault_Handler"))); -void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TWI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TWI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ARM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UDP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PWM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif /* __GNUC__ */ - -#ifdef __ICCARM__ -/* Cortex-M4 core handlers */ -#pragma weak Reset_Handler=Dummy_Handler -#pragma weak NMI_Handler=Dummy_Handler -#pragma weak HardFault_Handler=Dummy_Handler -#pragma weak MemManage_Handler=Dummy_Handler -#pragma weak BusFault_Handler=Dummy_Handler -#pragma weak UsageFault_Handler=Dummy_Handler -#pragma weak SVC_Handler=Dummy_Handler -#pragma weak DebugMon_Handler=Dummy_Handler -#pragma weak PendSV_Handler=Dummy_Handler -#pragma weak SysTick_Handler=Dummy_Handler - -/* Peripherals handlers */ -#pragma weak SUPC_Handler=Dummy_Handler -#pragma weak RSTC_Handler=Dummy_Handler -#pragma weak RTC_Handler=Dummy_Handler -#pragma weak RTT_Handler=Dummy_Handler -#pragma weak WDT_Handler=Dummy_Handler -#pragma weak PMC_Handler=Dummy_Handler -#pragma weak EFC_Handler=Dummy_Handler -#pragma weak UART0_Handler=Dummy_Handler -#pragma weak SMC_Handler=Dummy_Handler -#pragma weak PIOA_Handler=Dummy_Handler -#pragma weak PIOB_Handler=Dummy_Handler -#pragma weak PIOC_Handler=Dummy_Handler -#pragma weak PIOD_Handler=Dummy_Handler -#pragma weak PIOE_Handler=Dummy_Handler -#pragma weak USART0_Handler=Dummy_Handler -#pragma weak USART1_Handler=Dummy_Handler -#pragma weak HSMCI_Handler=Dummy_Handler -#pragma weak TWI0_Handler=Dummy_Handler -#pragma weak TWI1_Handler=Dummy_Handler -#pragma weak SPI_Handler=Dummy_Handler -#pragma weak DMAC_Handler=Dummy_Handler -#pragma weak TC0_Handler=Dummy_Handler -#pragma weak TC1_Handler=Dummy_Handler -#pragma weak TC2_Handler=Dummy_Handler -#pragma weak TC3_Handler=Dummy_Handler -#pragma weak TC4_Handler=Dummy_Handler -#pragma weak TC5_Handler=Dummy_Handler -#pragma weak TC6_Handler=Dummy_Handler -#pragma weak TC7_Handler=Dummy_Handler -#pragma weak TC8_Handler=Dummy_Handler -#pragma weak AFEC0_Handler=Dummy_Handler -#pragma weak AFEC1_Handler=Dummy_Handler -#pragma weak DACC_Handler=Dummy_Handler -#pragma weak ACC_Handler=Dummy_Handler -#pragma weak ARM_Handler=Dummy_Handler -#pragma weak UDP_Handler=Dummy_Handler -#pragma weak PWM_Handler=Dummy_Handler -#pragma weak CAN0_Handler=Dummy_Handler -#pragma weak CAN1_Handler=Dummy_Handler -#pragma weak AES_Handler=Dummy_Handler -#pragma weak GMAC_Handler=Dummy_Handler -#pragma weak UART1_Handler=Dummy_Handler -#endif /* __ICCARM__ */ - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} - -void Dummy_Hardfault_Handler(void) -{ - while (1) { - } -} - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/* @endcond */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/exceptions.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/exceptions.h deleted file mode 100644 index 5682a29fd..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/exceptions.h +++ /dev/null @@ -1,71 +0,0 @@ -/** - * \file - * - * \brief This file contains the interface for default exception handlers. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef EXCEPTIONS_H_INCLUDED -#define EXCEPTIONS_H_INCLUDED - -#include "sam4e.h" - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/* @endcond */ - -/* Function prototype for exception table items (interrupt handler). */ -typedef void (*IntFunc) (void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/* @endcond */ - -#endif /* EXCEPTIONS_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/gcc/startup_sam4e.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/gcc/startup_sam4e.c deleted file mode 100644 index 56ee3ec82..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/gcc/startup_sam4e.c +++ /dev/null @@ -1,191 +0,0 @@ -/** - * \file - * - * \brief Startup file for SAM4E. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "sam4e.h" -#include "exceptions.h" -#include "system_sam4e.h" -#if __FPU_USED /* CMSIS defined value to indicate usage of FPU */ -#include "fpu.h" -#endif - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (void*) (&_estack), - - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) MemManage_Handler, - (void*) BusFault_Handler, - (void*) UsageFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) DebugMon_Handler, - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) SUPC_Handler, /* 0 Supply Controller */ - (void*) RSTC_Handler, /* 1 Reset Controller */ - (void*) RTC_Handler, /* 2 Real Time Clock */ - (void*) RTT_Handler, /* 3 Real Time Timer */ - (void*) WDT_Handler, /* 4 Watchdog/Dual Watchdog Timer */ - (void*) PMC_Handler, /* 5 Power Management Controller */ - (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */ - (void*) UART0_Handler, /* 7 UART 0 */ - (void*) Dummy_Handler, - (void*) PIOA_Handler, /* 9 Parallel I/O Controller A */ - (void*) PIOB_Handler, /* 10 Parallel I/O Controller B */ - (void*) PIOC_Handler, /* 11 Parallel I/O Controller C */ -#ifdef _SAM4E_PIOD_INSTANCE_ - (void*) PIOD_Handler, /* 12 Parallel I/O Controller D */ -#else - (void*) Dummy_Handler, -#endif -#ifdef _SAM4E_PIOE_INSTANCE_ - (void*) PIOE_Handler, /* 13 Parallel I/O Controller E */ -#else - (void*) Dummy_Handler, -#endif - (void*) USART0_Handler, /* 14 USART 0 */ - (void*) USART1_Handler, /* 15 USART 1 */ - (void*) HSMCI_Handler, /* 16 Multimedia Card Interface */ - (void*) TWI0_Handler, /* 17 Two Wire Interface 0 */ - (void*) TWI1_Handler, /* 18 Two Wire Interface 1 */ - (void*) SPI_Handler, /* 19 Serial Peripheral Interface */ - (void*) DMAC_Handler, /* 20 DMAC */ - (void*) TC0_Handler, /* 21 Timer/Counter 0 */ - (void*) TC1_Handler, /* 22 Timer/Counter 1 */ - (void*) TC2_Handler, /* 23 Timer/Counter 2 */ - (void*) TC3_Handler, /* 24 Timer/Counter 3 */ - (void*) TC4_Handler, /* 25 Timer/Counter 4 */ - (void*) TC5_Handler, /* 26 Timer/Counter 5 */ - (void*) TC6_Handler, /* 27 Timer/Counter 6 */ - (void*) TC7_Handler, /* 28 Timer/Counter 7 */ - (void*) TC8_Handler, /* 29 Timer/Counter 8 */ - (void*) AFEC0_Handler, /* 30 Analog Front End 0 */ - (void*) AFEC1_Handler, /* 31 Analog Front End 1 */ - (void*) DACC_Handler, /* 32 Digital To Analog Converter */ - (void*) ACC_Handler, /* 33 Analog Comparator */ - (void*) ARM_Handler, /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */ - (void*) UDP_Handler, /* 35 USB DEVICE */ - (void*) PWM_Handler, /* 36 PWM */ - (void*) CAN0_Handler, /* 37 CAN0 */ - (void*) CAN1_Handler, /* 38 CAN1 */ - (void*) AES_Handler, /* 39 AES */ - (void*) Dummy_Handler, - (void*) Dummy_Handler, - (void*) Dummy_Handler, - (void*) Dummy_Handler, -#ifdef _SAM4E_GMAC_INSTANCE_ - (void*) GMAC_Handler, /* 44 EMAC */ -#else - (void*) Dummy_Handler, -#endif - (void*) UART1_Handler /* 45 UART */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - -#if __FPU_USED - fpu_enable(); -#endif - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/system_sam4e.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/system_sam4e.c deleted file mode 100644 index 906ed98c2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/system_sam4e.c +++ /dev/null @@ -1,231 +0,0 @@ -/** - * \file - * - * \brief Provides the low-level initialization functions that called - * on chip startup. - * - * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "sam4e.h" - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/* @endcond */ - -/* Clock Settings (120MHz) */ -#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U)) -#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \ - | CKGR_PLLAR_MULA(0x13U) \ - | CKGR_PLLAR_PLLACOUNT(0x3fU) \ - | CKGR_PLLAR_DIVA(0x1U)) -#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) - -#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */ - -uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; - -/** - * \brief Setup the microcontroller system. - * Initialize the System and update the SystemFrequency variable. - */ -void SystemInit( void ) -{ - /* Set FWS according to SYS_BOARD_MCKR configuration */ - EFC->EEFC_FMR = EEFC_FMR_FWS(5); - - /* Initialize main oscillator */ - if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) { - PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | - CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - - while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) { - } - } - - /* Switch to 3-20MHz Xtal oscillator */ - PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | - CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | - CKGR_MOR_MOSCSEL; - - while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) { - } - - PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | - PMC_MCKR_CSS_MAIN_CLK; - - while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { - } - - /* Initialize PLLA */ - PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; - while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) { - } - - /* Switch to main clock */ - PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | - PMC_MCKR_CSS_MAIN_CLK; - while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { - } - - /* Switch to PLLA */ - PMC->PMC_MCKR = SYS_BOARD_MCKR; - while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { - } - - SystemCoreClock = CHIP_FREQ_CPU_MAX; -} - -void SystemCoreClockUpdate( void ) -{ - /* Determine clock frequency according to clock register values */ - switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) { - case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ - if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL ) { - SystemCoreClock = CHIP_FREQ_XTAL_32K; - } else { - SystemCoreClock = CHIP_FREQ_SLCK_RC; - } - break; - - case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ - if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) { - SystemCoreClock = CHIP_FREQ_XTAL_12M; - } else { - SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; - - switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) { - case CKGR_MOR_MOSCRCF_4_MHz: - break; - - case CKGR_MOR_MOSCRCF_8_MHz: - SystemCoreClock *= 2U; - break; - - case CKGR_MOR_MOSCRCF_12_MHz: - SystemCoreClock *= 3U; - break; - - default: - break; - } - } - break; - - case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ - if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) { - SystemCoreClock = CHIP_FREQ_XTAL_12M ; - } else { - SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; - - switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) { - case CKGR_MOR_MOSCRCF_4_MHz: - break; - - case CKGR_MOR_MOSCRCF_8_MHz: - SystemCoreClock *= 2U; - break; - - case CKGR_MOR_MOSCRCF_12_MHz: - SystemCoreClock *= 3U; - break; - - default: - break; - } - } - - if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) - { - SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U); - SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos)); - } - break; - - default: - break; - } - - if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) { - SystemCoreClock /= 3U; - } else { - SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> - PMC_MCKR_PRES_Pos); - } -} - -/** - * Initialize flash. - */ -void system_init_flash( uint32_t ul_clk ) -{ - /* Set FWS for embedded Flash access according to operating frequency */ - if ( ul_clk < CHIP_FREQ_FWS_0 ) { - EFC->EEFC_FMR = EEFC_FMR_FWS(0); - } else { - if (ul_clk < CHIP_FREQ_FWS_1) { - EFC->EEFC_FMR = EEFC_FMR_FWS(1); - } else { - if (ul_clk < CHIP_FREQ_FWS_2) { - EFC->EEFC_FMR = EEFC_FMR_FWS(2); - } else { - if ( ul_clk < CHIP_FREQ_FWS_3 ) { - EFC->EEFC_FMR = EEFC_FMR_FWS(3); - } else { - if ( ul_clk < CHIP_FREQ_FWS_4 ) { - EFC->EEFC_FMR = EEFC_FMR_FWS(4); - } else { - EFC->EEFC_FMR = EEFC_FMR_FWS(5); - } - } - } - } - } -} - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/* @endcond */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/system_sam4e.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/system_sam4e.h deleted file mode 100644 index d1238d602..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/cmsis/sam4e/source/templates/system_sam4e.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * \file - * - * \brief Provides the low-level initialization functions that called - * on chip startup. - * - * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef SYSTEM_SAM4E_H_INCLUDED -#define SYSTEM_SAM4E_H_INCLUDED - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/* @endcond */ - -#include - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/** - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void); - -/** - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void); - -/** - * Initialize flash. - */ -void system_init_flash(uint32_t dw_clk); - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/* @endcond */ - -#endif /* SYSTEM_SAM4E_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h deleted file mode 100644 index 943eed1d5..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h +++ /dev/null @@ -1,1163 +0,0 @@ -/** - * \file - * - * \brief Commonly used includes, types and macros. - * - * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef UTILS_COMPILER_H -#define UTILS_COMPILER_H - -/** - * \defgroup group_sam_utils Compiler abstraction layer and code utilities - * - * Compiler abstraction layer and code utilities for AT91SAM. - * This module provides various abstraction layers and utilities to make code compatible between different compilers. - * - * \{ - */ -#include - -#if (defined __ICCARM__) -# include -#endif - -#include -#include "preprocessor.h" - -#include - -//_____ D E C L A R A T I O N S ____________________________________________ - -#ifndef __ASSEMBLY__ // Not defined for assembling. - -#include -#include -#include -#include - -#ifdef __ICCARM__ -/*! \name Compiler Keywords - * - * Port of some keywords from GCC to IAR Embedded Workbench. - */ -//! @{ -#define __asm__ asm -#define __inline__ inline -#define __volatile__ -//! @} - -#endif - -#define FUNC_PTR void * -/** - * \def UNUSED - * \brief Marking \a v as a unused parameter or value. - */ -#define UNUSED(v) (void)(v) - -/** - * \def unused - * \brief Marking \a v as a unused parameter or value. - */ -#define unused(v) do { (void)(v); } while(0) - -/** - * \def barrier - * \brief Memory barrier - */ -#define barrier() __DMB() - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union - * definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union - * definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - - -/** - * \brief Set aligned boundary. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif (defined __ICCARM__) -# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#endif - -/** - * \brief Set word-aligned boundary. - */ -#if (defined __GNUC__) || defined(__CC_ARM) -#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) -#elif (defined __ICCARM__) -#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) -#endif - -/** - * \def __always_inline - * \brief The function should always be inlined. - * - * This annotation instructs the compiler to ignore its inlining - * heuristics and inline the function no matter how big it thinks it - * becomes. - */ -#ifndef __always_inline - #if defined(__CC_ARM) - # define __always_inline __forceinline - #elif (defined __GNUC__) - # define __always_inline inline __attribute__((__always_inline__)) - #elif (defined __ICCARM__) - # define __always_inline _Pragma("inline=forced") - #endif -#endif - -/*! \brief This macro is used to test fatal errors. - * - * The macro tests if the expression is false. If it is, a fatal error is - * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO - * is defined, a unit test version of the macro is used, to allow execution - * of further tests after a false expression. - * - * \param expr Expression to evaluate and supposed to be nonzero. - */ -#if defined(_ASSERT_ENABLE_) -# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO) - // Assert() is defined in unit_test/suite.h -# include "unit_test/suite.h" -# else -#undef TEST_SUITE_DEFINE_ASSERT_MACRO -# define Assert(expr) \ - {\ - if (!(expr)) while (true);\ - } -# endif -#else -# define Assert(expr) ((void) 0) -#endif - -/* Define WEAK attribute */ -#if defined ( __CC_ARM ) /* Keil µVision 4 */ -# define WEAK __attribute__ ((weak)) -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define WEAK __weak -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define WEAK __attribute__ ((weak)) -#endif - -/* Define NO_INIT attribute */ -#if defined ( __CC_ARM ) -# define NO_INIT __attribute__((zero_init)) -#elif defined ( __ICCARM__ ) -# define NO_INIT __no_init -#elif defined ( __GNUC__ ) -# define NO_INIT __attribute__((section(".no_init"))) -#endif - -/* Define RAMFUNC attribute */ -#if defined ( __CC_ARM ) /* Keil µVision 4 */ -# define RAMFUNC __attribute__ ((section(".ramfunc"))) -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define RAMFUNC __ramfunc -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define RAMFUNC __attribute__ ((section(".ramfunc"))) -#endif - -/* Define OPTIMIZE_HIGH attribute */ -#if defined ( __CC_ARM ) /* Keil µVision 4 */ -# define OPTIMIZE_HIGH _Pragma("O3") -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define OPTIMIZE_HIGH _Pragma("optimize=high") -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define OPTIMIZE_HIGH __attribute__((optimize(s))) -#endif - -#include "interrupt.h" - -/*! \name Usual Types - */ -//! @{ -typedef unsigned char Bool; //!< Boolean. -#ifndef __cplusplus -#if !defined(__bool_true_false_are_defined) -typedef unsigned char bool; //!< Boolean. -#endif -#endif -typedef int8_t S8 ; //!< 8-bit signed integer. -typedef uint8_t U8 ; //!< 8-bit unsigned integer. -typedef int16_t S16; //!< 16-bit signed integer. -typedef uint16_t U16; //!< 16-bit unsigned integer. -typedef uint16_t le16_t; -typedef uint16_t be16_t; -typedef int32_t S32; //!< 32-bit signed integer. -typedef uint32_t U32; //!< 32-bit unsigned integer. -typedef uint32_t le32_t; -typedef uint32_t be32_t; -typedef int64_t S64; //!< 64-bit signed integer. -typedef uint64_t U64; //!< 64-bit unsigned integer. -typedef float F32; //!< 32-bit floating-point number. -typedef double F64; //!< 64-bit floating-point number. -typedef uint32_t iram_size_t; -//! @} - - -/*! \name Status Types - */ -//! @{ -typedef bool Status_bool_t; //!< Boolean status. -typedef U8 Status_t; //!< 8-bit-coded status. -//! @} - - -/*! \name Aliasing Aggregate Types - */ -//! @{ - -//! 16-bit union. -typedef union -{ - S16 s16 ; - U16 u16 ; - S8 s8 [2]; - U8 u8 [2]; -} Union16; - -//! 32-bit union. -typedef union -{ - S32 s32 ; - U32 u32 ; - S16 s16[2]; - U16 u16[2]; - S8 s8 [4]; - U8 u8 [4]; -} Union32; - -//! 64-bit union. -typedef union -{ - S64 s64 ; - U64 u64 ; - S32 s32[2]; - U32 u32[2]; - S16 s16[4]; - U16 u16[4]; - S8 s8 [8]; - U8 u8 [8]; -} Union64; - -//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. -typedef union -{ - S64 *s64ptr; - U64 *u64ptr; - S32 *s32ptr; - U32 *u32ptr; - S16 *s16ptr; - U16 *u16ptr; - S8 *s8ptr ; - U8 *u8ptr ; -} UnionPtr; - -//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. -typedef union -{ - volatile S64 *s64ptr; - volatile U64 *u64ptr; - volatile S32 *s32ptr; - volatile U32 *u32ptr; - volatile S16 *s16ptr; - volatile U16 *u16ptr; - volatile S8 *s8ptr ; - volatile U8 *u8ptr ; -} UnionVPtr; - -//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. -typedef union -{ - const S64 *s64ptr; - const U64 *u64ptr; - const S32 *s32ptr; - const U32 *u32ptr; - const S16 *s16ptr; - const U16 *u16ptr; - const S8 *s8ptr ; - const U8 *u8ptr ; -} UnionCPtr; - -//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. -typedef union -{ - const volatile S64 *s64ptr; - const volatile U64 *u64ptr; - const volatile S32 *s32ptr; - const volatile U32 *u32ptr; - const volatile S16 *s16ptr; - const volatile U16 *u16ptr; - const volatile S8 *s8ptr ; - const volatile U8 *u8ptr ; -} UnionCVPtr; - -//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. -typedef struct -{ - S64 *s64ptr; - U64 *u64ptr; - S32 *s32ptr; - U32 *u32ptr; - S16 *s16ptr; - U16 *u16ptr; - S8 *s8ptr ; - U8 *u8ptr ; -} StructPtr; - -//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. -typedef struct -{ - volatile S64 *s64ptr; - volatile U64 *u64ptr; - volatile S32 *s32ptr; - volatile U32 *u32ptr; - volatile S16 *s16ptr; - volatile U16 *u16ptr; - volatile S8 *s8ptr ; - volatile U8 *u8ptr ; -} StructVPtr; - -//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. -typedef struct -{ - const S64 *s64ptr; - const U64 *u64ptr; - const S32 *s32ptr; - const U32 *u32ptr; - const S16 *s16ptr; - const U16 *u16ptr; - const S8 *s8ptr ; - const U8 *u8ptr ; -} StructCPtr; - -//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. -typedef struct -{ - const volatile S64 *s64ptr; - const volatile U64 *u64ptr; - const volatile S32 *s32ptr; - const volatile U32 *u32ptr; - const volatile S16 *s16ptr; - const volatile U16 *u16ptr; - const volatile S8 *s8ptr ; - const volatile U8 *u8ptr ; -} StructCVPtr; - -//! @} - -#endif // #ifndef __ASSEMBLY__ - -/*! \name Usual Constants - */ -//! @{ -#define DISABLE 0 -#define ENABLE 1 -#ifndef __cplusplus -#if !defined(__bool_true_false_are_defined) -#define false 0 -#define true 1 -#endif -#endif -#define PASS 0 -#define FAIL 1 -#define LOW 0 -#define HIGH 1 -//! @} - - -#ifndef __ASSEMBLY__ // not for assembling. - -//! \name Optimization Control -//@{ - -/** - * \def likely(exp) - * \brief The expression \a exp is likely to be true - */ -#ifndef likely -# define likely(exp) (exp) -#endif - -/** - * \def unlikely(exp) - * \brief The expression \a exp is unlikely to be true - */ -#ifndef unlikely -# define unlikely(exp) (exp) -#endif - -/** - * \def is_constant(exp) - * \brief Determine if an expression evaluates to a constant value. - * - * \param exp Any expression - * - * \return true if \a exp is constant, false otherwise. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define is_constant(exp) __builtin_constant_p(exp) -#else -# define is_constant(exp) (0) -#endif - -//! @} - -/*! \name Bit-Field Handling - */ -//! @{ - -/*! \brief Reads the bits of a value specified by a given bit-mask. - * - * \param value Value to read bits from. - * \param mask Bit-mask indicating bits to read. - * - * \return Read bits. - */ -#define Rd_bits( value, mask) ((value) & (mask)) - -/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue to write bits to. - * \param mask Bit-mask indicating bits to write. - * \param bits Bits to write. - * - * \return Resulting value with written bits. - */ -#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ - ((bits ) & (mask))) - -/*! \brief Tests the bits of a value specified by a given bit-mask. - * - * \param value Value of which to test bits. - * \param mask Bit-mask indicating bits to test. - * - * \return \c 1 if at least one of the tested bits is set, else \c 0. - */ -#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) - -/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue of which to clear bits. - * \param mask Bit-mask indicating bits to clear. - * - * \return Resulting value with cleared bits. - */ -#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) - -/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue of which to set bits. - * \param mask Bit-mask indicating bits to set. - * - * \return Resulting value with set bits. - */ -#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) - -/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue of which to toggle bits. - * \param mask Bit-mask indicating bits to toggle. - * - * \return Resulting value with toggled bits. - */ -#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) - -/*! \brief Reads the bit-field of a value specified by a given bit-mask. - * - * \param value Value to read a bit-field from. - * \param mask Bit-mask indicating the bit-field to read. - * - * \return Read bit-field. - */ -#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) - -/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. - * - * \param lvalue C lvalue to write a bit-field to. - * \param mask Bit-mask indicating the bit-field to write. - * \param bitfield Bit-field to write. - * - * \return Resulting value with written bit-field. - */ -#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) - -//! @} - - -/*! \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - */ -//! @{ - -/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define clz(u) __builtin_clz(u) -#elif (defined __ICCARM__) -# define clz(u) __CLZ(u) -#else -# define clz(u) (((u) == 0) ? 32 : \ - ((u) & (1ul << 31)) ? 0 : \ - ((u) & (1ul << 30)) ? 1 : \ - ((u) & (1ul << 29)) ? 2 : \ - ((u) & (1ul << 28)) ? 3 : \ - ((u) & (1ul << 27)) ? 4 : \ - ((u) & (1ul << 26)) ? 5 : \ - ((u) & (1ul << 25)) ? 6 : \ - ((u) & (1ul << 24)) ? 7 : \ - ((u) & (1ul << 23)) ? 8 : \ - ((u) & (1ul << 22)) ? 9 : \ - ((u) & (1ul << 21)) ? 10 : \ - ((u) & (1ul << 20)) ? 11 : \ - ((u) & (1ul << 19)) ? 12 : \ - ((u) & (1ul << 18)) ? 13 : \ - ((u) & (1ul << 17)) ? 14 : \ - ((u) & (1ul << 16)) ? 15 : \ - ((u) & (1ul << 15)) ? 16 : \ - ((u) & (1ul << 14)) ? 17 : \ - ((u) & (1ul << 13)) ? 18 : \ - ((u) & (1ul << 12)) ? 19 : \ - ((u) & (1ul << 11)) ? 20 : \ - ((u) & (1ul << 10)) ? 21 : \ - ((u) & (1ul << 9)) ? 22 : \ - ((u) & (1ul << 8)) ? 23 : \ - ((u) & (1ul << 7)) ? 24 : \ - ((u) & (1ul << 6)) ? 25 : \ - ((u) & (1ul << 5)) ? 26 : \ - ((u) & (1ul << 4)) ? 27 : \ - ((u) & (1ul << 3)) ? 28 : \ - ((u) & (1ul << 2)) ? 29 : \ - ((u) & (1ul << 1)) ? 30 : \ - 31) -#endif - -/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define ctz(u) __builtin_ctz(u) -#else -# define ctz(u) ((u) & (1ul << 0) ? 0 : \ - (u) & (1ul << 1) ? 1 : \ - (u) & (1ul << 2) ? 2 : \ - (u) & (1ul << 3) ? 3 : \ - (u) & (1ul << 4) ? 4 : \ - (u) & (1ul << 5) ? 5 : \ - (u) & (1ul << 6) ? 6 : \ - (u) & (1ul << 7) ? 7 : \ - (u) & (1ul << 8) ? 8 : \ - (u) & (1ul << 9) ? 9 : \ - (u) & (1ul << 10) ? 10 : \ - (u) & (1ul << 11) ? 11 : \ - (u) & (1ul << 12) ? 12 : \ - (u) & (1ul << 13) ? 13 : \ - (u) & (1ul << 14) ? 14 : \ - (u) & (1ul << 15) ? 15 : \ - (u) & (1ul << 16) ? 16 : \ - (u) & (1ul << 17) ? 17 : \ - (u) & (1ul << 18) ? 18 : \ - (u) & (1ul << 19) ? 19 : \ - (u) & (1ul << 20) ? 20 : \ - (u) & (1ul << 21) ? 21 : \ - (u) & (1ul << 22) ? 22 : \ - (u) & (1ul << 23) ? 23 : \ - (u) & (1ul << 24) ? 24 : \ - (u) & (1ul << 25) ? 25 : \ - (u) & (1ul << 26) ? 26 : \ - (u) & (1ul << 27) ? 27 : \ - (u) & (1ul << 28) ? 28 : \ - (u) & (1ul << 29) ? 29 : \ - (u) & (1ul << 30) ? 30 : \ - (u) & (1ul << 31) ? 31 : \ - 32) -#endif - -//! @} - - -/*! \name Bit Reversing - */ -//! @{ - -/*! \brief Reverses the bits of \a u8. - * - * \param u8 U8 of which to reverse the bits. - * - * \return Value resulting from \a u8 with reversed bits. - */ -#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) - -/*! \brief Reverses the bits of \a u16. - * - * \param u16 U16 of which to reverse the bits. - * - * \return Value resulting from \a u16 with reversed bits. - */ -#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) - -/*! \brief Reverses the bits of \a u32. - * - * \param u32 U32 of which to reverse the bits. - * - * \return Value resulting from \a u32 with reversed bits. - */ -#define bit_reverse32(u32) __RBIT(u32) - -/*! \brief Reverses the bits of \a u64. - * - * \param u64 U64 of which to reverse the bits. - * - * \return Value resulting from \a u64 with reversed bits. - */ -#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\ - ((U64)bit_reverse32((U64)(u64)) << 32))) - -//! @} - - -/*! \name Alignment - */ -//! @{ - -/*! \brief Tests alignment of the number \a val with the \a n boundary. - * - * \param val Input value. - * \param n Boundary. - * - * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. - */ -#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) - -/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. - * - * \param val Input value. - * \param n Boundary. - * - * \return Alignment of the number \a val with respect to the \a n boundary. - */ -#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) - -/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. - * - * \param lval Input/output lvalue. - * \param n Boundary. - * \param alg Alignment. - * - * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. - */ -#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) - -/*! \brief Aligns the number \a val with the upper \a n boundary. - * - * \param val Input value. - * \param n Boundary. - * - * \return Value resulting from the number \a val aligned with the upper \a n boundary. - */ -#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) - -/*! \brief Aligns the number \a val with the lower \a n boundary. - * - * \param val Input value. - * \param n Boundary. - * - * \return Value resulting from the number \a val aligned with the lower \a n boundary. - */ -#define Align_down(val, n ) ( (val) & ~((n) - 1)) - -//! @} - - -/*! \name Mathematics - * - * The same considerations as for clz and ctz apply here but GCC does not - * provide built-in functions to access the assembly instructions abs, min and - * max and it does not produce them by itself in most cases, so two sets of - * macros are defined here: - * - Abs, Min and Max to apply to constant expressions (values known at - * compile time); - * - abs, min and max to apply to non-constant expressions (values unknown at - * compile time), abs is found in stdlib.h. - */ -//! @{ - -/*! \brief Takes the absolute value of \a a. - * - * \param a Input value. - * - * \return Absolute value of \a a. - * - * \note More optimized if only used with values known at compile time. - */ -#define Abs(a) (((a) < 0 ) ? -(a) : (a)) - -/*! \brief Takes the minimal value of \a a and \a b. - * - * \param a Input value. - * \param b Input value. - * - * \return Minimal value of \a a and \a b. - * - * \note More optimized if only used with values known at compile time. - */ -#define Min(a, b) (((a) < (b)) ? (a) : (b)) - -/*! \brief Takes the maximal value of \a a and \a b. - * - * \param a Input value. - * \param b Input value. - * - * \return Maximal value of \a a and \a b. - * - * \note More optimized if only used with values known at compile time. - */ -#define Max(a, b) (((a) > (b)) ? (a) : (b)) - -// abs() is already defined by stdlib.h - -/*! \brief Takes the minimal value of \a a and \a b. - * - * \param a Input value. - * \param b Input value. - * - * \return Minimal value of \a a and \a b. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define min(a, b) Min(a, b) - -/*! \brief Takes the maximal value of \a a and \a b. - * - * \param a Input value. - * \param b Input value. - * - * \return Maximal value of \a a and \a b. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define max(a, b) Max(a, b) - -//! @} - - -/*! \brief Calls the routine at address \a addr. - * - * It generates a long call opcode. - * - * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if - * it is invoked from the CPU supervisor mode. - * - * \param addr Address of the routine to call. - * - * \note It may be used as a long jump opcode in some special cases. - */ -#define Long_call(addr) ((*(void (*)(void))(addr))()) - - -/*! \name MCU Endianism Handling - * ARM is MCU little endianism. - */ -//! @{ -#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. -#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. - -#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. -#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. -#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32. -#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32. -#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32. -#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32. -#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. -#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. -#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. -#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. - -#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. -#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. -#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64. -#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64. -#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64. -#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64. -#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. -#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. -#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. -#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. -#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64. -#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64. -#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64. -#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64. -#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64. -#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64. -#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64. -#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64. -#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. -#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. -#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. -#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. -#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. -#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. -#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. -#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. - -#define BE16(x) Swap16(x) -#define LE16(x) (x) - -#define le16_to_cpu(x) (x) -#define cpu_to_le16(x) (x) -#define LE16_TO_CPU(x) (x) -#define CPU_TO_LE16(x) (x) - -#define be16_to_cpu(x) Swap16(x) -#define cpu_to_be16(x) Swap16(x) -#define BE16_TO_CPU(x) Swap16(x) -#define CPU_TO_BE16(x) Swap16(x) - -#define le32_to_cpu(x) (x) -#define cpu_to_le32(x) (x) -#define LE32_TO_CPU(x) (x) -#define CPU_TO_LE32(x) (x) - -#define be32_to_cpu(x) swap32(x) -#define cpu_to_be32(x) swap32(x) -#define BE32_TO_CPU(x) swap32(x) -#define CPU_TO_BE32(x) swap32(x) -//! @} - - -/*! \name Endianism Conversion - * - * The same considerations as for clz and ctz apply here but GCC's - * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when - * applied to constant expressions, so two sets of macros are defined here: - * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known - * at compile time); - * - swap16, swap32 and swap64 to apply to non-constant expressions (values - * unknown at compile time). - */ -//! @{ - -/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ - ((U16)(u16) << 8))) - -/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ - ((U32)Swap16((U32)(u32)) << 16))) - -/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). - * - * \param u64 U64 of which to toggle the endianism. - * - * \return Value resulting from \a u64 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ - ((U64)Swap32((U64)(u64)) << 32))) - -/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define swap16(u16) Swap16(u16) - -/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#if (defined __GNUC__) -# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32))) -#else -# define swap32(u32) Swap32(u32) -#endif - -/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). - * - * \param u64 U64 of which to toggle the endianism. - * - * \return Value resulting from \a u64 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#if (defined __GNUC__) -# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64))) -#else -# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ - ((U64)swap32((U64)(u64)) << 32))) -#endif - -//! @} - - -/*! \name Target Abstraction - */ -//! @{ - -#define _GLOBEXT_ extern //!< extern storage-class specifier. -#define _CONST_TYPE_ const //!< const type qualifier. -#define _MEM_TYPE_SLOW_ //!< Slow memory type. -#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. -#define _MEM_TYPE_FAST_ //!< Fast memory type. - -typedef U8 Byte; //!< 8-bit unsigned integer. - -#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. -#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. -#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. -#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. - -#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. -#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. -#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. -#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. -#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. -#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. -#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. -#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. - -//! @} - -/** - * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using - * integer arithmetic. - * - * \param a An integer - * \param b Another integer - * - * \return (\a a / \a b) rounded up to the nearest integer. - */ -#define div_ceil(a, b) (((a) + (b) - 1) / (b)) - -#endif // #ifndef __ASSEMBLY__ - - -#if defined(__ICCARM__) -#define SHORTENUM __packed -#elif defined(__GNUC__) -#define SHORTENUM __attribute__((packed)) -#endif - -/* No operation */ -#if defined(__ICCARM__) -#define nop() __no_operation() -#elif defined(__GNUC__) -#define nop() (__NOP()) -#endif - -#define FLASH_DECLARE(x) const x -#define FLASH_EXTERN(x) extern const x -#define PGM_READ_BYTE(x) *(x) -#define PGM_READ_WORD(x) *(x) -#define MEMCPY_ENDIAN memcpy -#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len)) - -/*Defines the Flash Storage for the request and response of MAC*/ -#define CMD_ID_OCTET (0) - -/* Converting of values from CPU endian to little endian. */ -#define CPU_ENDIAN_TO_LE16(x) (x) -#define CPU_ENDIAN_TO_LE32(x) (x) -#define CPU_ENDIAN_TO_LE64(x) (x) - -/* Converting of values from little endian to CPU endian. */ -#define LE16_TO_CPU_ENDIAN(x) (x) -#define LE32_TO_CPU_ENDIAN(x) (x) -#define LE64_TO_CPU_ENDIAN(x) (x) - -/* Converting of constants from little endian to CPU endian. */ -#define CLE16_TO_CPU_ENDIAN(x) (x) -#define CLE32_TO_CPU_ENDIAN(x) (x) -#define CLE64_TO_CPU_ENDIAN(x) (x) - -/* Converting of constants from CPU endian to little endian. */ -#define CCPU_ENDIAN_TO_LE16(x) (x) -#define CCPU_ENDIAN_TO_LE32(x) (x) -#define CCPU_ENDIAN_TO_LE64(x) (x) - -#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src)) -#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src)) - -/** - * @brief Converts a 64-Bit value into a 8 Byte array - * - * @param[in] value 64-Bit value - * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value - * @ingroup apiPalApi - */ -static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) -{ - uint8_t val_index = 0; - - while (val_index < 8) - { - data[val_index++] = value & 0xFF; - value = value >> 8; - } -} - -/** - * @brief Converts a 16-Bit value into a 2 Byte array - * - * @param[in] value 16-Bit value - * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value - * @ingroup apiPalApi - */ -static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* Converts a 16-Bit value into a 2 Byte array */ -static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* Converts a 16-Bit value into a 2 Byte array */ -static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* - * @brief Converts a 2 Byte array into a 16-Bit value - * - * @param data Specifies the pointer to the 2 Byte array - * - * @return 16-Bit value - * @ingroup apiPalApi - */ -static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) -{ - return (data[0] | ((uint16_t)data[1] << 8)); -} - -/** - * @brief Converts a 8 Byte array into a 64-Bit value - * - * @param data Specifies the pointer to the 8 Byte array - * - * @return 64-Bit value - * @ingroup apiPalApi - */ -static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) -{ - union - { - uint64_t u64; - uint8_t u8[8]; - } long_addr; - - uint8_t val_index; - - for (val_index = 0; val_index < 8; val_index++) - { - long_addr.u8[val_index] = *data++; - } - - return long_addr.u64; -} -/** - * \} - */ - -#endif /* UTILS_COMPILER_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/fpu/fpu.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/fpu/fpu.h deleted file mode 100644 index c28c39a9b..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/fpu/fpu.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * \file - * - * \brief FPU support for SAM. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _FPU_H_INCLUDED_ -#define _FPU_H_INCLUDED_ - -#include - -/** Address for ARM CPACR */ -#define ADDR_CPACR 0xE000ED88 - -/** CPACR Register */ -#define REG_CPACR (*((volatile uint32_t *)ADDR_CPACR)) - -/** - * Enable FPU - */ -__always_inline static void fpu_enable(void) -{ - irqflags_t flags; - flags = cpu_irq_save(); - REG_CPACR |= (0xFu << 20); - __DSB(); - __ISB(); - cpu_irq_restore(flags); -} - -/** - * Disable FPU - */ -__always_inline static void fpu_disable(void) -{ - irqflags_t flags; - flags = cpu_irq_save(); - REG_CPACR &= ~(0xFu << 20); - __DSB(); - __ISB(); - cpu_irq_restore(flags); -} - -/** - * Check if FPU is enabled - */ -__always_inline static bool fpu_is_enabled(void) -{ - return (REG_CPACR & (0xFu << 20)); -} - -#endif /* _FPU_H_INCLUDED_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/header_files/io.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/header_files/io.h deleted file mode 100644 index b0fbd29ca..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/header_files/io.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * \brief Arch file for SAM. - * - * This file defines common SAM series. - * - * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAM_IO_ -#define _SAM_IO_ - -/* SAM3 family */ - -/* SAM3S series */ -#if (SAM3S) -# if (SAM3S8 || SAM3SD8) -# include "sam3s8.h" -# else -# include "sam3s.h" -# endif -#endif - -/* SAM3U series */ -#if (SAM3U) -# include "sam3u.h" -#endif - -/* SAM3N series */ -#if (SAM3N) -# include "sam3n.h" -#endif - -/* SAM3XA series */ -#if (SAM3XA) -# include "sam3xa.h" -#endif - -/* SAM4S series */ -#if (SAM4S) -# include "sam4s.h" -#endif - -/* SAM4L series */ -#if (SAM4L) -# include "sam4l.h" -#endif - -/* SAM4E series */ -#if (SAM4E) -# include "sam4e.h" -#endif - -/* SAM4N series */ -#if (SAM4N) -# include "sam4n.h" -#endif - -#endif /* _SAM_IO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/linker_scripts/sam4e/sam4e16e/gcc/flash.ld b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/linker_scripts/sam4e/sam4e16e/gcc/flash.ld deleted file mode 100644 index d01ef3ef3..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/linker_scripts/sam4e/sam4e16e/gcc/flash.ld +++ /dev/null @@ -1,153 +0,0 @@ -/** - * \file - * - * \brief Flash Linker script for SAM. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/make/Makefile.sam.in b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/make/Makefile.sam.in deleted file mode 100644 index 2dd582d6c..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/make/Makefile.sam.in +++ /dev/null @@ -1,482 +0,0 @@ -# List of available make goals: -# -# all Default target, builds the project -# clean Clean up the project -# rebuild Rebuild the project -# debug_flash Builds the project and debug in flash -# debug_sram Builds the project and debug in sram -# -# doc Build the documentation -# cleandoc Clean up the documentation -# rebuilddoc Rebuild the documentation -# -# \file -# -# Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. -# -# \asf_license_start -# -# \page License -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# 3. The name of Atmel may not be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# 4. This software may only be redistributed and used in connection with an -# Atmel microcontroller product. -# -# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -# \asf_license_stop -# - -# Include the config.mk file from the current working path, e.g., where the -# user called make. -include config.mk - -# Tool to use to generate documentation from the source code -DOCGEN ?= doxygen - -# Look for source files relative to the top-level source directory -VPATH := $(PRJ_PATH) - -# Output target file -project_type := $(PROJECT_TYPE) - -# Output target file -ifeq ($(project_type),flash) -target := $(TARGET_FLASH) -linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH) -debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH) -else -target := $(TARGET_SRAM) -linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM) -debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM) -endif - -# Output project name (target name minus suffix) -project := $(basename $(target)) - -# Output target file (typically ELF or static library) -ifeq ($(suffix $(target)),.a) -target_type := lib -else -ifeq ($(suffix $(target)),.elf) -target_type := elf -else -$(error "Target type $(target_type) is not supported") -endif -endif - -# Allow override of operating system detection. The user can add OS=Linux or -# OS=Windows on the command line to explicit set the host OS. -# -# This allows to work around broken uname utility on certain systems. -ifdef OS - ifeq ($(strip $(OS)), Linux) - os_type := Linux - endif - ifeq ($(strip $(OS)), Windows) - os_type := windows32_64 - endif -endif - -os_type ?= $(strip $(shell uname)) - -ifeq ($(os_type),windows32) -os := Windows -else -ifeq ($(os_type),windows64) -os := Windows -else -ifeq ($(os_type),windows32_64) -os ?= Windows -else -ifeq ($(os_type),) -os := Windows -else -# Default to Linux style operating system. Both Cygwin and mingw are fully -# compatible (for this Makefile) with Linux. -os := Linux -endif -endif -endif -endif - -# Output documentation directory and configuration file. -docdir := ../doxygen/html -doccfg := ../doxygen/doxyfile.doxygen - -CROSS ?= arm-none-eabi- -AR := $(CROSS)ar -AS := $(CROSS)as -CC := $(CROSS)gcc -CPP := $(CROSS)gcc -E -CXX := $(CROSS)g++ -LD := $(CROSS)g++ -NM := $(CROSS)nm -OBJCOPY := $(CROSS)objcopy -OBJDUMP := $(CROSS)objdump -SIZE := $(CROSS)size -GDB := $(CROSS)gdb - -RM := rm -ifeq ($(os),Windows) -RMDIR := rmdir /S /Q -else -RMDIR := rmdir -p --ignore-fail-on-non-empty -endif - -# On Windows, we need to override the shell to force the use of cmd.exe -ifeq ($(os),Windows) -SHELL := cmd -endif - -# Strings for beautifying output -MSG_CLEAN_FILES = "RM *.o *.d" -MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))" -MSG_CLEAN_DOC = "RMDIR $(docdir)" -MSG_MKDIR = "MKDIR $(dir $@)" - -MSG_INFO = "INFO " - -MSG_ARCHIVING = "AR $@" -MSG_ASSEMBLING = "AS $@" -MSG_BINARY_IMAGE = "OBJCOPY $@" -MSG_COMPILING = "CC $@" -MSG_COMPILING_CXX = "CXX $@" -MSG_EXTENDED_LISTING = "OBJDUMP $@" -MSG_IHEX_IMAGE = "OBJCOPY $@" -MSG_LINKING = "LN $@" -MSG_PREPROCESSING = "CPP $@" -MSG_SIZE = "SIZE $@" -MSG_SYMBOL_TABLE = "NM $@" - -MSG_GENERATING_DOC = "DOXYGEN $(docdir)" - -# Don't use make's built-in rules and variables -MAKEFLAGS += -rR - -# Don't print 'Entering directory ...' -MAKEFLAGS += --no-print-directory - -# Function for reversing the order of a list -reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1)) - -# Hide command output by default, but allow the user to override this -# by adding V=1 on the command line. -# -# This is inspired by the Kbuild system used by the Linux kernel. -ifdef V - ifeq ("$(origin V)", "command line") - VERBOSE = $(V) - endif -endif -ifndef VERBOSE - VERBOSE = 0 -endif - -ifeq ($(VERBOSE), 1) - Q = -else - Q = @ -endif - -arflags-gnu-y := $(ARFLAGS) -asflags-gnu-y := $(ASFLAGS) -cflags-gnu-y := $(CFLAGS) -cxxflags-gnu-y := $(CXXFLAGS) -cppflags-gnu-y := $(CPPFLAGS) -cpuflags-gnu-y := -dbgflags-gnu-y := $(DBGFLAGS) -libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB)) -ldflags-gnu-y := $(LDFLAGS) -flashflags-gnu-y := -clean-files := -clean-dirs := - -clean-files += $(wildcard $(target) $(project).map) -clean-files += $(wildcard $(project).hex $(project).bin) -clean-files += $(wildcard $(project).lss $(project).sym) -clean-files += $(wildcard $(build)) - -# Use pipes instead of temporary files for communication between processes -cflags-gnu-y += -pipe -asflags-gnu-y += -pipe -ldflags-gnu-y += -pipe - -# Archiver flags. -arflags-gnu-y += rcs - -# Always enable warnings. And be very careful about implicit -# declarations. -cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes -cflags-gnu-y += -Werror-implicit-function-declaration -cxxflags-gnu-y += -Wall -# IAR doesn't allow arithmetic on void pointers, so warn about that. -cflags-gnu-y += -Wpointer-arith -cxxflags-gnu-y += -Wpointer-arith - -# Preprocessor flags. -cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC)) -asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)') - -# CPU specific flags. -cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__ - -# Dependency file flags. -depflags = -MD -MP -MQ $@ - -# Debug specific flags. -ifdef BUILD_DEBUG_LEVEL -dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL) -else -dbgflags-gnu-y += -g3 -endif - -# Optimization specific flags. -ifdef BUILD_OPTIMIZATION -optflags-gnu-y = -O$(BUILD_OPTIMIZATION) -else -optflags-gnu-y = $(OPTIMIZATION) -endif - -# Always preprocess assembler files. -asflags-gnu-y += -x assembler-with-cpp -# Compile C files using the GNU99 standard. -cflags-gnu-y += -std=gnu99 -# Compile C++ files using the GNU++98 standard. -cxxflags-gnu-y += -std=gnu++98 - -# Don't use strict aliasing (very common in embedded applications). -cflags-gnu-y += -fno-strict-aliasing -cxxflags-gnu-y += -fno-strict-aliasing - -# Separate each function and data into its own separate section to allow -# garbage collection of unused sections. -cflags-gnu-y += -ffunction-sections -fdata-sections -cxxflags-gnu-y += -ffunction-sections -fdata-sections - -# Various cflags. -cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -cflags-gnu-y += -Wmain -Wparentheses -cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings -cflags-gnu-y += -Wsign-compare -Waggregate-return -cflags-gnu-y += -Wmissing-declarations -cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long -cflags-gnu-y += -Wunreachable-code -cflags-gnu-y += -Wcast-align -cflags-gnu-y += --param max-inline-insns-single=500 - -# Garbage collect unreferred sections when linking. -ldflags-gnu-y += -Wl,--gc-sections - -# Use the linker script if provided by the project. -ifneq ($(strip $(linker_script)),) -ldflags-gnu-y += -Wl,-T $(linker_script) -endif - -# Output a link map file and a cross reference table -ldflags-gnu-y += -Wl,-Map=$(project).map,--cref - -# Add library search paths relative to the top level directory. -ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH)) - -a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__ -c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y) -cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y) -l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y) -ar_flags = $(arflags-gnu-y) - -# Source files list and part informations must already be included before -# running this makefile - -# If a custom build directory is specified, use it -- force trailing / in directory name. -ifdef BUILD_DIR - build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/) -else - build-dir = -endif - -# Create object files list from source files list. -obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS)))) -# Create dependency files list from source files list. -dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d)) - -clean-files += $(wildcard $(obj-y)) -clean-files += $(dep-files) - -clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y))))) - -# Default target. -.PHONY: all -ifeq ($(project_type),all) -all: - $(MAKE) all PROJECT_TYPE=flash - $(MAKE) all PROJECT_TYPE=sram -else -ifeq ($(target_type),lib) -all: $(target) $(project).lss $(project).sym -else -ifeq ($(target_type),elf) -all: $(target) $(project).lss $(project).sym $(project).hex $(project).bin -endif -endif -endif - -# Clean up the project. -.PHONY: clean -clean: - @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES)) - $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),) - @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS)) -# Remove created directories, and make sure we only remove existing -# directories, since recursive rmdir might help us a bit on the way. -ifeq ($(os),Windows) - $(Q)$(if $(strip $(clean-dirs)), \ - $(RMDIR) $(strip $(subst /,\,$(clean-dirs)))) -else - $(Q)$(if $(strip $(clean-dirs)), \ - for directory in $(strip $(clean-dirs)); do \ - if [ -d "$$directory" ]; then \ - $(RMDIR) $$directory; \ - fi \ - done \ - ) -endif - -# Rebuild the project. -.PHONY: rebuild -rebuild: clean all - -# Debug the project in flash. -.PHONY: debug_flash -debug_flash: all - $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH) - -# Debug the project in sram. -.PHONY: debug_sram -debug_sram: all - $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM) - -.PHONY: objfiles -objfiles: $(obj-y) - -# Create object files from C source files. -$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk - $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) -ifeq ($(os),Windows) - $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) -else - $(Q)test -d $(dir $@) || mkdir -p $(dir $@) -endif - @echo $(MSG_COMPILING) - $(Q)$(CC) $(c_flags) -c $< -o $@ - -# Create object files from C++ source files. -$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk - $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) -ifeq ($(os),Windows) - $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) -else - $(Q)test -d $(dir $@) || mkdir -p $(dir $@) -endif - @echo $(MSG_COMPILING_CXX) - $(Q)$(CXX) $(cxx_flags) -c $< -o $@ - -# Preprocess and assemble: create object files from assembler source files. -$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk - $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) -ifeq ($(os),Windows) - $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) -else - $(Q)test -d $(dir $@) || mkdir -p $(dir $@) -endif - @echo $(MSG_ASSEMBLING) - $(Q)$(CC) $(a_flags) -c $< -o $@ - -# Include all dependency files to add depedency to all header files in use. -include $(dep-files) - -ifeq ($(target_type),lib) -# Archive object files into an archive -$(target): $(MAKEFILE_PATH) config.mk $(obj-y) - @echo $(MSG_ARCHIVING) - $(Q)$(AR) $(ar_flags) $@ $(obj-y) - @echo $(MSG_SIZE) - $(Q)$(SIZE) -Bxt $@ -else -ifeq ($(target_type),elf) -# Link the object files into an ELF file. Also make sure the target is rebuilt -# if the common Makefile.sam.in or project config.mk is changed. -$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y) - @echo $(MSG_LINKING) - $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@ - @echo $(MSG_SIZE) - $(Q)$(SIZE) -Ax $@ - $(Q)$(SIZE) -Bx $@ -endif -endif - -# Create extended function listing from target output file. -%.lss: $(target) - @echo $(MSG_EXTENDED_LISTING) - $(Q)$(OBJDUMP) -h -S $< > $@ - -# Create symbol table from target output file. -%.sym: $(target) - @echo $(MSG_SYMBOL_TABLE) - $(Q)$(NM) -n $< > $@ - -# Create Intel HEX image from ELF output file. -%.hex: $(target) - @echo $(MSG_IHEX_IMAGE) - $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@ - -# Create binary image from ELF output file. -%.bin: $(target) - @echo $(MSG_BINARY_IMAGE) - $(Q)$(OBJCOPY) -O binary $< $@ - -# Provide information about the detected host operating system. -.SECONDARY: info-os -info-os: - @echo $(MSG_INFO)$(os) build host detected - -# Build Doxygen generated documentation. -.PHONY: doc -doc: - @echo $(MSG_GENERATING_DOC) - $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg)) - -# Clean Doxygen generated documentation. -.PHONY: cleandoc -cleandoc: - @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC)) - $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir)) - -# Rebuild the Doxygen generated documentation. -.PHONY: rebuilddoc -rebuilddoc: cleandoc doc diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/mrepeat.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/mrepeat.h deleted file mode 100644 index 954dd5f02..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/mrepeat.h +++ /dev/null @@ -1,336 +0,0 @@ -/** - * \file - * - * \brief Preprocessor macro repeating utils. - * - * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _MREPEAT_H_ -#define _MREPEAT_H_ - -/** - * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat - * - * \ingroup group_sam_utils - * - * \{ - */ - -#include "preprocessor.h" - - -//! Maximal number of repetitions supported by MREPEAT. -#define MREPEAT_LIMIT 256 - -/*! \brief Macro repeat. - * - * This macro represents a horizontal repetition construct. - * - * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. - * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with - * the current repetition number and the auxiliary data argument. - * \param data Auxiliary data passed to macro. - * - * \return macro(0, data) macro(1, data) ... macro(count - 1, data) - */ -#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) - -#define MREPEAT0( macro, data) -#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) -#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) -#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) -#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) -#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) -#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) -#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) -#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) -#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) -#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) -#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) -#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) -#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) -#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) -#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) -#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) -#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) -#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) -#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) -#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) -#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) -#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) -#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) -#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) -#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) -#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) -#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) -#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) -#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) -#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) -#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) -#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) -#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) -#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) -#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) -#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) -#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) -#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) -#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) -#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) -#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) -#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) -#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) -#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) -#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) -#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) -#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) -#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) -#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) -#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) -#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) -#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) -#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) -#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) -#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) -#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) -#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) -#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) -#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) -#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) -#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) -#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) -#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) -#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) -#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) -#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) -#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) -#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) -#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) -#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) -#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) -#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) -#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) -#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) -#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) -#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) -#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) -#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) -#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) -#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) -#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) -#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) -#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) -#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) -#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) -#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) -#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) -#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) -#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) -#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) -#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) -#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) -#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) -#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) -#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) -#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) -#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) -#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) -#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) -#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) -#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) -#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) -#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) -#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) -#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) -#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) -#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) -#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) -#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) -#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) -#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) -#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) -#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) -#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) -#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) -#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) -#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) -#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) -#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) -#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) -#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) -#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) -#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) -#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) -#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) -#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) -#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) -#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) -#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) -#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) -#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) -#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) -#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) -#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) -#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) -#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) -#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) -#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) -#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) -#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) -#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) -#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) -#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) -#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) -#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) -#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) -#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) -#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) -#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) -#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) -#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) -#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) -#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) -#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) -#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) -#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) -#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) -#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) -#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) -#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) -#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) -#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) -#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) -#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) -#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) -#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) -#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) -#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) -#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) -#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) -#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) -#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) -#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) -#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) -#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) -#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) -#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) -#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) -#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) -#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) -#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) -#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) -#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) -#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) -#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) -#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) -#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) -#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) -#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) -#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) -#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) -#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) -#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) -#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) -#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) -#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) -#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) -#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) -#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) -#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) -#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) -#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) -#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) -#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) -#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) -#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) -#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) -#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) -#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) -#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) -#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) -#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) -#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) -#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) -#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) -#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) -#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) -#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) -#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) -#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) -#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) -#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) -#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) -#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) -#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) -#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) -#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) -#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) -#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) -#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) -#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) -#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) -#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) -#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) -#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) -#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) -#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) -#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) -#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) -#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) -#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) -#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) -#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) -#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) -#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) -#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) -#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) -#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) -#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) -#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) -#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) -#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) -#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) -#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) -#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) -#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) - -/** - * \} - */ - -#endif // _MREPEAT_H_ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/preprocessor.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/preprocessor.h deleted file mode 100644 index fd544e3e6..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/preprocessor.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Preprocessor utils. - * - * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _PREPROCESSOR_H_ -#define _PREPROCESSOR_H_ - -#include "tpaste.h" -#include "stringz.h" -#include "mrepeat.h" - - -#endif // _PREPROCESSOR_H_ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/stringz.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/stringz.h deleted file mode 100644 index 063b94447..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/stringz.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * \file - * - * \brief Preprocessor stringizing utils. - * - * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _STRINGZ_H_ -#define _STRINGZ_H_ - -/** - * \defgroup group_sam_utils_stringz Preprocessor - Stringize - * - * \ingroup group_sam_utils - * - * \{ - */ - -/*! \brief Stringize. - * - * Stringize a preprocessing token, this token being allowed to be \#defined. - * - * May be used only within macros with the token passed as an argument if the token is \#defined. - * - * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) - * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to - * writing "A0". - */ -#define STRINGZ(x) #x - -/*! \brief Absolute stringize. - * - * Stringize a preprocessing token, this token being allowed to be \#defined. - * - * No restriction of use if the token is \#defined. - * - * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is - * equivalent to writing "A0". - */ -#define ASTRINGZ(x) STRINGZ(x) - -/** - * \} - */ - -#endif // _STRINGZ_H_ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/tpaste.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/tpaste.h deleted file mode 100644 index 8894ba659..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/preprocessor/tpaste.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * \file - * - * \brief Preprocessor token pasting utils. - * - * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _TPASTE_H_ -#define _TPASTE_H_ - -/** - * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste - * - * \ingroup group_sam_utils - * - * \{ - */ - -/*! \name Token Paste - * - * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. - * - * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. - * - * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by - * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is - * equivalent to writing U32. - */ -//! @{ -#define TPASTE2( a, b) a##b -#define TPASTE3( a, b, c) a##b##c -#define TPASTE4( a, b, c, d) a##b##c##d -#define TPASTE5( a, b, c, d, e) a##b##c##d##e -#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f -#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g -#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h -#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i -#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j -//! @} - -/*! \name Absolute Token Paste - * - * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. - * - * No restriction of use if the tokens are \#defined. - * - * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined - * as 32 is equivalent to writing U32. - */ -//! @{ -#define ATPASTE2( a, b) TPASTE2( a, b) -#define ATPASTE3( a, b, c) TPASTE3( a, b, c) -#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) -#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) -#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) -#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) -#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) -#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) -#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) -//! @} - -/** - * \} - */ - -#endif // _TPASTE_H_ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/status_codes.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/status_codes.h deleted file mode 100644 index 3b99dfcad..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/status_codes.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * \file - * - * \brief Status code definitions. - * - * This file defines various status codes returned by functions, - * indicating success or failure as well as what kind of failure. - * - * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef STATUS_CODES_H_INCLUDED -#define STATUS_CODES_H_INCLUDED - -/* Note: this is a local workaround to avoid a pre-processor clash due to the - * lwIP macro ERR_TIMEOUT. */ -#if defined(__LWIP_ERR_H__) && defined(ERR_TIMEOUT) -#if (ERR_TIMEOUT != -3) - -/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT - * macro is set to the correct value. Note that it is highly improbable that - * this value ever changes in lwIP. */ -#error ASF developers: check lwip err.h new value for ERR_TIMEOUT -#endif -#undef ERR_TIMEOUT -#endif - -/** - * Status code that may be returned by shell commands and protocol - * implementations. - * - * \note Any change to these status codes and the corresponding - * message strings is strictly forbidden. New codes can be added, - * however, but make sure that any message string tables are updated - * at the same time. - */ -enum status_code { - STATUS_OK = 0, //!< Success - STATUS_ERR_BUSY = 0x19, - STATUS_ERR_DENIED = 0x1C, - STATUS_ERR_TIMEOUT = 0x12, - ERR_IO_ERROR = -1, //!< I/O error - ERR_FLUSHED = -2, //!< Request flushed from queue - ERR_TIMEOUT = -3, //!< Operation timed out - ERR_BAD_DATA = -4, //!< Data integrity check failed - ERR_PROTOCOL = -5, //!< Protocol error - ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device - ERR_NO_MEMORY = -7, //!< Insufficient memory - ERR_INVALID_ARG = -8, //!< Invalid argument - ERR_BAD_ADDRESS = -9, //!< Bad address - ERR_BUSY = -10, //!< Resource is busy - ERR_BAD_FORMAT = -11, //!< Data format not recognized - ERR_NO_TIMER = -12, //!< No timer available - ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running - ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running - - /** - * \brief Operation in progress - * - * This status code is for driver-internal use when an operation - * is currently being performed. - * - * \note Drivers should never return this status code to any - * callers. It is strictly for internal use. - */ - OPERATION_IN_PROGRESS = -128, -}; - -typedef enum status_code status_code_t; - -#if defined(__LWIP_ERR_H__) -#define ERR_TIMEOUT -3 -#endif - -#endif /* STATUS_CODES_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/syscalls/gcc/syscalls.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/syscalls/gcc/syscalls.c deleted file mode 100644 index b23b999a0..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/syscalls/gcc/syscalls.c +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief Syscalls for SAM (GCC). - * - * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -#undef errno -extern int errno; -extern int _end; - -extern caddr_t _sbrk(int incr); -extern int link(char *old, char *new); -extern int _close(int file); -extern int _fstat(int file, struct stat *st); -extern int _isatty(int file); -extern int _lseek(int file, int ptr, int dir); -extern void _exit(int status); -extern void _kill(int pid, int sig); -extern int _getpid(void); - -extern caddr_t _sbrk(int incr) -{ - static unsigned char *heap = NULL; - unsigned char *prev_heap; - - if (heap == NULL) { - heap = (unsigned char *)&_end; - } - prev_heap = heap; - - heap += incr; - - return (caddr_t) prev_heap; -} - -extern int link(char *old, char *new) -{ - ( void ) old; - ( void ) new; - return -1; -} - -extern int _close(int file) -{ - ( void ) file; - return -1; -} - -extern int _fstat(int file, struct stat *st) -{ - ( void ) file; - ( void ) st; - st->st_mode = S_IFCHR; - - return 0; -} - -extern int _isatty(int file) -{ - ( void ) file; - return 1; -} - -extern int _lseek(int file, int ptr, int dir) -{ - ( void ) file; - ( void ) ptr; - ( void ) dir; - return 0; -} - -extern void _exit(int status) -{ - printf("Exiting with status %d.\n", status); - - for (;;); -} - -extern void _kill(int pid, int sig) -{ - ( void ) pid; - ( void ) sig; - return; -} - -extern int _getpid(void) -{ - return -1; -} - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/arm_math.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/arm_math.h deleted file mode 100644 index b01681c63..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7057 +0,0 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * $Date: 15. July 2011 - * $Revision: V1.0.10 - * - * Project: CMSIS DSP Library - * Title: arm_math.h - * - * Description: Public header file for CMSIS DSP Library - * - * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 - * - * Version 1.0.10 2011/7/15 - * Big Endian support added and Merged M0 and M3/M4 Source code. - * - * Version 1.0.3 2010/11/29 - * Re-organized the CMSIS folders and updated documentation. - * - * Version 1.0.2 2010/11/11 - * Documentation updated. - * - * Version 1.0.1 2010/10/05 - * Production release and review comments incorporated. - * - * Version 1.0.0 2010/09/20 - * Production release and review comments incorporated. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of modules each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Processor Support - * - * The library is completely written in C and is fully CMSIS compliant. - * High performance is achieved through maximum use of Cortex-M4 intrinsics. - * - * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, - * with the DSP intrinsics being emulated through software. - * - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.21. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * Each library project have differant pre-processor macros. - * - * ARM_MATH_CMx: - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target. - * - * ARM_MATH_BIG_ENDIAN: - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * ARM_MATH_MATRIX_CHECK: - * Define macro for checking on the input and output sizes of matrices - * - * ARM_MATH_ROUNDING: - * Define macro for rounding on support functions - * - * __FPU_PRESENT: - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. - * - * Copyright Notice - * - * Copyright (C) 2010 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" - #include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#define PI 3.14159265358979f - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#define __SIMD32(addr) (*(int32_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0) && defined ( __TASKING__ ) -/* No need to redefine __CLZ */ -#endif - -#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) ) - - __STATIC_INLINE uint32_t __CLZ(q31_t data); - - - __STATIC_INLINE uint32_t __CLZ(q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return(count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. - */ - - __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. - */ - __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0) - - __STATIC_INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0 */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - __STATIC_INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - __STATIC_INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - __STATIC_INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - __STATIC_INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - - -#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t *pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t *pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t *pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - #ifdef ARM_MATH_CM0 - q15_t A1; - q15_t A2; - #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ - #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - - /** - * @brief Processing function for the Q15 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Initialization function for the Q15 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Initialization function for the Q31 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point CFFT/CIFFT. - * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Initialization function for the floating-point CFFT/CIFFT. - * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - - - /*---------------------------------------------------------------------- - * Internal functions prototypes FFT function - ----------------------------------------------------------------------*/ - - /** - * @brief Core function for the floating-point CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to the twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the floating-point CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen value of 1/fftLen. - * @return none. - */ - - void arm_radix4_butterfly_inverse_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier, - float32_t onebyfftLen); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftSize length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. - * @param[in] *pBitRevTab points to the bit reversal table. - * @return none. - */ - - void arm_bitreversal_f32( - float32_t *pSrc, - uint16_t fftSize, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q31( - q31_t *pSrc, - uint32_t fftLen, - q31_t *pCoef, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q31 CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q31( - q31_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q15 CFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q15 CIFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q15( - q15_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - /** - * @brief Processing function for the Q15 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Initialization function for the Q15 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Initialization function for the Q31 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Initialization function for the floating-point RFFT/RIFFT. - * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point RFFT/RIFFT. - * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t *pkCoeffs, - float32_t *pvCoeffs, - float32_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t *pkCoeffs, - q31_t *pvCoeffs, - q31_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t *pkCoeffs, - q15_t *pvCoeffs, - q15_t *pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t *pCoeffs, - q31_t *pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t *pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t *pSinVal, - float32_t *pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t *pSinVal, - q31_t *pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - - /* Implementation of PID controller */ - - #ifdef ARM_MATH_CM0 - - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0 )* in ; - - #else - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - #endif - - #ifdef ARM_MATH_CM0 - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0] ; - acc += (q31_t) S->A2 * S->state[1] ; - - #else - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); - - #endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (x - S->x1) / xSpacing; - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if(i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues-1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i +1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - __STATIC_INLINE q31_t arm_linear_interp_q31(q31_t *pYData, - q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - __STATIC_INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - __STATIC_INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, float32_t *pOut) - { - if(in > 0) - { - -// #if __FPU_USED - #if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); - #elif (__FPU_USED == 1) && defined ( __TMS_740 ) - *pOut = __builtin_sqrtf(in); - #else - *pOut = sqrtf(in); - #endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, q31_t *pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, q15_t *pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - __STATIC_INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - __STATIC_INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - __STATIC_INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - __STATIC_INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - __STATIC_INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - __STATIC_INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) - { - return(0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex-1) * S->numCols ; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex-1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cm4.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cm4.h deleted file mode 100644 index ef818e4d1..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1689 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.00 - * @date 03. February 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks to define __FPU_USED */ - #define __FPU_USED 0 -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cm4_simd.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cm4_simd.h deleted file mode 100644 index 34b395a04..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cm4_simd.h +++ /dev/null @@ -1,649 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.00 - * @date 19. January 2012 - * - * @note - * Copyright (C) 2010-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 1991ae3d9..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.00 - * @date 19. January 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index 7981634e7..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,618 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.00 - * @date 07. February 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/README.txt b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/README.txt deleted file mode 100644 index efa2ad16e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/README.txt +++ /dev/null @@ -1,37 +0,0 @@ -* ------------------------------------------------------------------- -* Copyright (C) 2011 ARM Limited. All rights reserved. -* -* Date: 11 October 2011 -* Revision: V3.00 -* -* Project: Cortex Microcontroller Software Interface Standard (CMSIS) -* Title: Release Note for CMSIS -* -* ------------------------------------------------------------------- - - -NOTE - Open the index.html file to access CMSIS documentation - - -The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all -Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects -and reduces time-to-market for new embedded applications. - -CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf"). -Any user of the software package is bound to the terms and conditions of the end user license agreement. - - -You will find the following sub-directories: - -Documentation - Contains CMSIS documentation. - -DSP_Lib - MDK project files, Examples and source files etc.. to build the - CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. - -Include - CMSIS Core Support and CMSIS DSP Include Files. - -Lib - CMSIS DSP Libraries. - -RTOS - CMSIS RTOS API template header file. - -SVD - CMSIS SVD Schema files and Conversion Utility. diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/license.txt b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/license.txt deleted file mode 100644 index b220574a5..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/thirdparty/CMSIS/license.txt +++ /dev/null @@ -1,167 +0,0 @@ -END USER LICENCE AGREEMENT FOR THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE -STANDARD (CMSIS) SPECIFICATION AND SOFTWARE - -THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A -SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE -CMSIS SPECIFICATION, EXAMPLE CODE, DSP LIBRARY SPECIFICATION AND DSP LIBRARY -IMPLEMENTATION AS SUCH TERMS ARE DEFINED BELOW (COLLECTIVELY, THE "ARM -DELIVERABLES"). ARM IS ONLY WILLING TO LICENSE THE ARM DELIVERABLES TO YOU ON CONDITION -THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING -OR OTHERWISE USING OR COPYING THE ARM DELIVERABLES YOU INDICATE THAT YOU AGREE TO -BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS -LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE THE ARM DELIVERABLES AND YOU MAY NOT -INSTALL, USE OR COPY THE ARM DELIVERABLES. - -"CMSIS Specification" means any documentation and C programming language files defining the application -programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface -Standard (CMSIS) as well as the System View Description (SVD) documentation and associated XML schema -file. Notwithstanding the foregoing, "CMSIS Specification" shall not include (i) the implementation of other -published specifications referenced in the CMSIS Specification; (ii) any enabling technologies that may be -necessary to make or use any product or portion thereof that complies with the CMSIS Specification, but are not -themselves expressly set forth in the CMSIS Specification (e.g. compiler front ends, code generators, back ends, -libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; -applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii) -maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of -integrated circuit designs. - -"DSP Library Implementation" means any C programming language source code implementing the functionality -of the digital signal processor (DSP) algorithms and the application programming interface as defined in the DSP -Library Specification. The DSP Library Implementation makes use of CMSIS application programming interface -and therefore is targeted at Cortex-M class processors. - -"DSP Library Specification" means the DSP library documentation and C programming language file defining the -application programming interface of the DSP Library Implementation. Notwithstanding the foregoing, "DSP -Library Specification" shall not include (i) the implementation of other published specifications referenced in the -DSP Library Specification; (ii) any enabling technologies that may be necessary to make or use any product or -portion thereof that complies with the DSP Library Specification, but are not themselves expressly set forth in the -DSP Library Specification (e.g. compiler front ends, code generators, back ends, libraries or other compiler, -assembler or linker technologies; validation or debug software or hardware; applications, operating system or -driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of -integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs. - -"Example Code" means any files in C, C++ or ARM assembly programming languages, associated project and -configuration files that demonstrate the usage of the CMSIS Specification, the DSP Library Specification and the -DSP Library Implementation, for microprocessors or device specific software applications that are for use with -microprocessors. - -1. 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This Licence may not be assigned without the prior written consent of ARM. - -ARM contract reference LEC-PRE-00489 diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/IntQueueTimer.c deleted file mode 100644 index c216fe086..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/IntQueueTimer.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.0 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * Provides the two timers sources for the standard demo IntQueue test. Also - * includes a high frequency timer to maximise the interrupt nesting achieved. - */ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "IntQueueTimer.h" -#include "IntQueue.h" - -/* System includes. */ -#include "board.h" -#include "asf.h" - -/* The frequencies at which the first two timers expire are slightly offset to -ensure they don't remain synchronised. The frequency of the highest priority -interrupt is 20 times faster so really hammers the interrupt entry and exit -code. */ -#define tmrTIMER_0_FREQUENCY ( 2000UL ) -#define tmrTIMER_1_FREQUENCY ( 1003UL ) -#define tmrTIMER_2_FREQUENCY ( 20000UL ) - -/* Priorities used by the timer interrupts - these are set differently to make -nesting likely/common. The high frequency timer operates above the max -system call interrupt priority, but does not use the RTOS API. */ -#define tmrTIMER_0_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ) -#define tmrTIMER_1_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 ) -#define tmrTIMER_2_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 ) - -/* The channels used within the TC0 timer. */ -#define tmrTIMER_0_CHANNEL ( 0 ) -#define tmrTIMER_1_CHANNEL ( 1 ) -#define tmrTIMER_2_CHANNEL ( 2 ) - -/* TC register bit specifics. */ -#define tmrTRIGGER_ON_RC ( 1UL << 4UL ) -#define trmDIVIDER ( 128 ) - -/*-----------------------------------------------------------*/ - -/* Handers for the timer interrupts. */ -void TC0_Handler( void ); -void TC1_Handler( void ); -void TC2_Handler( void ); - -/*-----------------------------------------------------------*/ - -/* Incremented by the high frequency timer, which operates above the max -syscall interrupt priority. This is just for inspection. */ -volatile uint32_t ulHighFrequencyTimerInterrupts = 0; - -/*-----------------------------------------------------------*/ - -void vInitialiseTimerForIntQueueTest( void ) -{ -uint32_t ulInputFrequency; - - /* Calculate the frequency of the clock that feeds the TC. */ - ulInputFrequency = configCPU_CLOCK_HZ; - ulInputFrequency /= trmDIVIDER; - - /* Three channels are used - two that run at or under - configMAX_SYSCALL_INTERRUPT_PRIORITY, and one that runs over - configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - sysclk_enable_peripheral_clock( ID_TC0 ); - sysclk_enable_peripheral_clock( ID_TC1 ); - sysclk_enable_peripheral_clock( ID_TC2 ); - - /* Init TC channels to waveform mode - up mode clean on RC match. */ - tc_init( TC0, tmrTIMER_0_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG ); - tc_init( TC0, tmrTIMER_1_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG ); - tc_init( TC0, tmrTIMER_2_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG ); - - tc_enable_interrupt( TC0, tmrTIMER_0_CHANNEL, tmrTRIGGER_ON_RC ); - tc_enable_interrupt( TC0, tmrTIMER_1_CHANNEL, tmrTRIGGER_ON_RC ); - tc_enable_interrupt( TC0, tmrTIMER_2_CHANNEL, tmrTRIGGER_ON_RC ); - - tc_write_rc( TC0, tmrTIMER_0_CHANNEL, ( ulInputFrequency / tmrTIMER_0_FREQUENCY ) ); - tc_write_rc( TC0, tmrTIMER_1_CHANNEL, ( ulInputFrequency / tmrTIMER_1_FREQUENCY ) ); - tc_write_rc( TC0, tmrTIMER_2_CHANNEL, ( ulInputFrequency / tmrTIMER_2_FREQUENCY ) ); - - NVIC_SetPriority( TC0_IRQn, tmrTIMER_0_PRIORITY ); - NVIC_SetPriority( TC1_IRQn, tmrTIMER_1_PRIORITY ); - NVIC_SetPriority( TC2_IRQn, tmrTIMER_2_PRIORITY ); - - NVIC_EnableIRQ( TC0_IRQn ); - NVIC_EnableIRQ( TC1_IRQn ); - NVIC_EnableIRQ( TC2_IRQn ); - - tc_start( TC0, tmrTIMER_0_CHANNEL ); - tc_start( TC0, tmrTIMER_1_CHANNEL ); - tc_start( TC0, tmrTIMER_2_CHANNEL ); -} -/*-----------------------------------------------------------*/ - -void TC0_Handler( void ) -{ - /* Handler for the first timer in the IntQueue test. Was the interrupt - caused by a compare on RC? */ - if( ( tc_get_status( TC0, tmrTIMER_0_CHANNEL ) & ~TC_SR_CPCS ) != 0 ) - { - portYIELD_FROM_ISR( xFirstTimerHandler() ); - } -} -/*-----------------------------------------------------------*/ - -void TC1_Handler( void ) -{ - /* Handler for the second timer in the IntQueue test. Was the interrupt - caused by a compare on RC? */ - if( ( tc_get_status( TC0, tmrTIMER_1_CHANNEL ) & ~TC_SR_CPCS ) != 0 ) - { - portYIELD_FROM_ISR( xSecondTimerHandler() ); - } -} -/*-----------------------------------------------------------*/ - -void TC2_Handler( void ) -{ - /* Handler for the high frequency timer that does nothing but increment a - variable to give an indication that it is running. Was the interrupt caused - by a compare on RC? */ - if( ( tc_get_status( TC0, tmrTIMER_2_CHANNEL ) & ~TC_SR_CPCS ) != 0 ) - { - ulHighFrequencyTimerInterrupts++; - } -} diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/IntQueueTimer.h deleted file mode 100644 index 4594efdff..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/IntQueueTimer.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.0 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef INT_QUEUE_TIMER_H -#define INT_QUEUE_TIMER_H - -void vInitialiseTimerForIntQueueTest( void ); -BaseType_t xTimer0Handler( void ); -BaseType_t xTimer1Handler( void ); - -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/LCDUtils.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/LCDUtils.c deleted file mode 100644 index 3e11a5820..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/LCDUtils.c +++ /dev/null @@ -1,174 +0,0 @@ -/** - * gfx_draw_bmpfile() is provided by and copyright to Atmel Corporation with the - * following usage restrictions: - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* Standard includes. */ -#include - -/* Library includes. */ -#include - -/* Bitmap. */ -#include "logo_atmel.h" - -/* Chip select number to be set for LCD. */ -#define ILI93XX_LCD_CS 1 - -/* - * Initialise the LCD and output a bitmap. - */ -void vInitialiseLCD( void ); - -/* - * Output a bitmap to the LCD. - */ -static void gfx_draw_bmpfile( const uint8_t *bmpImage ); - -/*-----------------------------------------------------------*/ - -COMPILER_PACK_SET( 1 ) -struct bmpfile_header { - /** signature, must be 4D42 hex */ - uint16_t type; - /** size of BMP file in bytes (unreliable) */ - uint32_t file_size; - /** reserved, must be zero */ - uint16_t reserved1; - /** reserved, must be zero */ - uint16_t reserved2; - /** offset to start of image data in bytes */ - uint32_t offset; - /** size of BITMAPINFOHEADER structure, must be 40 */ - uint32_t header_size; - /** image width in pixels */ - uint32_t width; - /** image height in pixels */ - uint32_t height; - /** number of planes in the image, must be 1 */ - uint16_t planes; - /** number of bits per pixel (1, 4, 8, 16, 24, 32) */ - uint16_t bits; - /** compression type (0=none, 1=RLE-8, 2=RLE-4) */ - uint32_t compression; - /** size of image data in bytes (including padding) */ - uint32_t inage_size; - /** horizontal resolution in pixels per meter */ - uint32_t h_resolution; - /** vertical resolution in pixels per meter */ - uint32_t v_resolution; - /** number of colors in image, or zero */ - uint32_t colours; - /** number of important colors, or zero */ - uint32_t important_colors; -}; -COMPILER_PACK_RESET() - -void vInitialiseLCD( void ) -{ -struct ili93xx_opt_t g_ili93xx_display_opt; - - /* Configure SMC interface for Lcd */ - smc_set_setup_timing( SMC, ILI93XX_LCD_CS, SMC_SETUP_NWE_SETUP( 2 ) | SMC_SETUP_NCS_WR_SETUP( 2 ) | SMC_SETUP_NRD_SETUP( 2 ) | SMC_SETUP_NCS_RD_SETUP( 2 ) ); - smc_set_pulse_timing( SMC, ILI93XX_LCD_CS, SMC_PULSE_NWE_PULSE( 4 ) | SMC_PULSE_NCS_WR_PULSE( 4 ) | SMC_PULSE_NRD_PULSE( 10 )| SMC_PULSE_NCS_RD_PULSE( 10 ) ); - smc_set_cycle_timing( SMC, ILI93XX_LCD_CS, SMC_CYCLE_NWE_CYCLE( 10 )| SMC_CYCLE_NRD_CYCLE( 22 ) ); - smc_set_mode( SMC, ILI93XX_LCD_CS, SMC_MODE_READ_MODE | SMC_MODE_WRITE_MODE ); - - /* Initialise the LCD. */ - g_ili93xx_display_opt.ul_width = ILI93XX_LCD_WIDTH; - g_ili93xx_display_opt.ul_height = ILI93XX_LCD_HEIGHT; - g_ili93xx_display_opt.foreground_color = COLOR_BLACK; - g_ili93xx_display_opt.background_color = COLOR_WHITE; - ili93xx_init( &g_ili93xx_display_opt ); - - /* Set backlight level */ - aat31xx_set_backlight(AAT31XX_AVG_BACKLIGHT_LEVEL); - - /* Turn on LCD */ - ili93xx_display_on(); - - /* Clear. */ - ili93xx_set_foreground_color( COLOR_WHITE ); - ili93xx_draw_filled_rectangle( 0, 0, ILI93XX_LCD_WIDTH, ILI93XX_LCD_HEIGHT ); - - /* Draw logos. */ - ili93xx_set_cursor_position( 0,0 ); - gfx_draw_bmpfile( logo_atmel_bmp ); - - /* Set foreground colour ready to write text. */ - ili93xx_set_foreground_color( COLOR_BLACK ); -} -/*-----------------------------------------------------------*/ - -static void gfx_draw_bmpfile( const uint8_t *bmpImage ) -{ - struct bmpfile_header *bmp_header; - uint32_t length; - uint32_t i = 0; - uint32_t offset; - uint16_t j; - - bmp_header = (struct bmpfile_header*) bmpImage; - length = bmp_header->height * bmp_header->width * 3; - offset = sizeof(struct bmpfile_header); - - if (ili93xx_device_type() == DEVICE_TYPE_ILI9325) { - - ili93xx_set_cursor_position(0, 0); - - /** Prepare to write in GRAM */ - LCD_IR(0); - LCD_IR(ILI9325_GRAM_DATA_REG); - for (i = offset; i < length; i += 3) { - /** Invert red and blue. */ - LCD_WD(bmpImage[i + 2]); - LCD_WD(bmpImage[i + 1]); - LCD_WD(bmpImage[i]); - } - } else if (ili93xx_device_type() == DEVICE_TYPE_ILI9341) { - ili93xx_set_window(0, 0, bmp_header->width - 15, bmp_header->height); - /** memory write command (R2Ch)*/ - LCD_IR(ILI9341_CMD_MEMORY_WRITE); - LCD_IR(ILI9341_CMD_WRITE_MEMORY_CONTINUE); - - /** the original image is mirrored */ - for (i= bmp_header->height - 1; i * bmp_header->width * 3 > offset; - i -=1) { - for (j = 45; j < bmp_header->width * 3; j += 3) { - LCD_WD(bmpImage[i * bmp_header->width * 3 + j + 2]); - LCD_WD(bmpImage[i * bmp_header->width * 3 + j + 1]); - LCD_WD(bmpImage[i * bmp_header->width * 3 + j]); - } - } - } -} diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ParTest.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ParTest.c deleted file mode 100644 index f2f66f352..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ParTest.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.0 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/*----------------------------------------------------------- - * Simple IO routines to control the LEDs. - *-----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "partest.h" - -/* The number of LEDs available to the user on the evaluation kit. */ -#define partestNUM_LEDS ( 3UL ) - -/* The index of the pins to which the LEDs are connected. The ordering of the -LEDs in this array is intentional and matches the order they appear on the -hardware. */ -static const uint32_t ulLED[] = { LED0_GPIO, LED1_GPIO, LED2_GPIO }; - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* LEDs are initialised in the Atmel provided board initialisation - function. */ -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - if( uxLED < partestNUM_LEDS ) - { - /* Turn the LED off. */ - taskENTER_CRITICAL(); - { - ioport_set_pin_level( ulLED[ uxLED ], !xValue ); - } - taskEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - if( uxLED < partestNUM_LEDS ) - { - taskENTER_CRITICAL(); - { - ioport_toggle_pin_level( ulLED[ uxLED ] ); - } - taskEXIT_CRITICAL(); - } -} - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/RunTimeStatsTimer.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/RunTimeStatsTimer.c deleted file mode 100644 index 897d1ffc7..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/RunTimeStatsTimer.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.0 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" - -/* Utility functions to implement run time stats on Cortex-M CPUs. The collected -run time data can be viewed through the CLI interface. See the following URL for -more information on run time stats: -http://www.freertos.org/rtos-run-time-stats.html */ - -/* Addresses of registers in the Cortex-M debug hardware. */ -#define rtsDWT_CYCCNT ( *( ( unsigned long * ) 0xE0001004 ) ) -#define rtsDWT_CONTROL ( *( ( unsigned long * ) 0xE0001000 ) ) -#define rtsSCB_DEMCR ( *( ( unsigned long * ) 0xE000EDFC ) ) -#define rtsTRCENA_BIT ( 0x01000000UL ) -#define rtsCOUNTER_ENABLE_BIT ( 0x01UL ) - -/* Simple shift divide for scaling to avoid an overflow occurring too soon. The -number of bits to shift depends on the clock speed. */ -#define runtimeSLOWER_CLOCK_SPEEDS ( 70000000UL ) -#define runtimeSHIFT_13 13 -#define runtimeOVERFLOW_BIT_13 ( 1UL << ( 32UL - runtimeSHIFT_13 ) ) -#define runtimeSHIFT_14 14 -#define runtimeOVERFLOW_BIT_14 ( 1UL << ( 32UL - runtimeSHIFT_14 ) ) - -/*-----------------------------------------------------------*/ - -void vConfigureTimerForRunTimeStats( void ) -{ - /* Enable TRCENA. */ - rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT; - - /* Reset counter. */ - rtsDWT_CYCCNT = 0; - - /* Enable counter. */ - rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT; -} -/*-----------------------------------------------------------*/ - -uint32_t ulGetRunTimeCounterValue( void ) -{ -static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0; -unsigned long ulValueNow; - - ulValueNow = rtsDWT_CYCCNT; - - /* Has the value overflowed since it was last read. */ - if( ulValueNow < ulLastCounterValue ) - { - ulOverflows++; - } - ulLastCounterValue = ulValueNow; - - /* Cannot use configCPU_CLOCK_HZ directly as it may itself not be a constant - but instead map to a variable that holds the clock speed. */ - - /* There is no prescale on the counter, so simulate in software. */ - if( configCPU_CLOCK_HZ < runtimeSLOWER_CLOCK_SPEEDS ) - { - ulValueNow >>= runtimeSHIFT_13; - ulValueNow += ( runtimeOVERFLOW_BIT_13 * ulOverflows ); - } - else - { - ulValueNow >>= runtimeSHIFT_14; - ulValueNow += ( runtimeOVERFLOW_BIT_14 * ulOverflows ); - } - - return ulValueNow; -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/asf.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/asf.h deleted file mode 100644 index b5036d022..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/asf.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * \file - * - * \brief Autogenerated API include file for the Atmel Software Framework (ASF) - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ASF_H -#define ASF_H - -/* - * This file includes all API header files for the selected drivers from ASF. - * Note: There might be duplicate includes required by more than one driver. - * - * The file is automatically generated and will be re-written when - * running the ASF driver selector tool. Any changes will be discarded. - */ - -// From module: Common SAM compiler driver -#include -#include - -// From module: Display - AAT31XX Backlight Controller -#include - -// From module: Display - ILI93xx LCD Controller -#include -#include -#include - -// From module: Ethernet MAC (GMAC) -#include - -// From module: Ethernet Physical Transceiver (ksz8051mnl) -#include - -// From module: Generic board support -#include - -// From module: IOPORT - General purpose I/O service -#include - -// From module: Interrupt management - SAM implementation -#include - -// From module: PMC - Power Management Controller -#include -#include - -// From module: Part identification macros -#include - -// From module: SAM FPU driver -#include - -// From module: SAM4E EK LED support enabled -#include - -// From module: SAM4E startup code -#include - -// From module: SMC - Static Memory Controller -#include - -// From module: System Clock Control - SAM4E implementation -#include - -// From module: TC - Timer Counter -#include - -#endif // ASF_H diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/FreeRTOSConfig.h deleted file mode 100644 index 0ec140c59..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/FreeRTOSConfig.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.0 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/* Atmel library includes. */ -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html - *----------------------------------------------------------*/ - -extern uint32_t SystemCoreClock; - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#define configUSE_QUEUE_SETS 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( SystemCoreClock ) -#define configTICK_RATE_HZ ( 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 47 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 10 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 8 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_COUNTING_SEMAPHORES 1 - -/* The full demo always has tasks to run so the tick will never be turned off. -The blinky demo will use the default tickless idle implementation to turn the -tick off. */ -#define configUSE_TICKLESS_IDLE 1 - -/* Run time stats gathering definitions. */ -void vConfigureTimerForRunTimeStats( void ); -uint32_t ulGetRunTimeCounterValue( void ); -#define configGENERATE_RUN_TIME_STATS 1 -#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() -#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( 2 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xTimerPendFunctionCall 1 - -/* Cortex-M specific definitions. */ -#ifdef __NVIC_PRIO_BITS - /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ - #define configPRIO_BITS __NVIC_PRIO_BITS -#else - #define configPRIO_BITS 4 /* 15 priority levels */ -#endif - -/* The lowest interrupt priority that can be used in a call to a "set priority" -function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf - -/* The highest interrupt priority that can be used by any interrupt service -routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL -INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER -PRIORITY THAN THIS! (higher priorities are lower numeric values. */ -#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 - -/* Interrupt priorities used by the kernel port layer itself. These are generic -to all Cortex-M ports, and do not rely on any particular library functions. */ -#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) -/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! -See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - -/* Normal assert() semantics without relying on the provision of an assert.h -header file. */ -extern void vAssertCalled( uint32_t ulLine, const char *pcFile ); -#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ ) - -/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS -standard names. */ -#define xPortPendSVHandler PendSV_Handler -#define vPortSVCHandler SVC_Handler -#define xPortSysTickHandler SysTick_Handler - -/* MAC address configuration. In a deployed production system this would -probably be read from an EEPROM. In the demo it is just hard coded. Make sure -each node on the network has a unique MAC address. */ -#define configMAC_ADDR0 0x00 -#define configMAC_ADDR1 0x11 -#define configMAC_ADDR2 0x22 -#define configMAC_ADDR3 0x33 -#define configMAC_ADDR4 0x44 -#define configMAC_ADDR5 0x45 - -/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or -ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configIP_ADDR0 172 -#define configIP_ADDR1 25 -#define configIP_ADDR2 218 -#define configIP_ADDR3 200 - -/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to -0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configGATEWAY_ADDR0 172 -#define configGATEWAY_ADDR1 25 -#define configGATEWAY_ADDR2 218 -#define configGATEWAY_ADDR3 2 - -/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and -208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set -to 1 but a DNS server cannot be contacted.*/ -#define configDNS_SERVER_ADDR0 208 -#define configDNS_SERVER_ADDR1 67 -#define configDNS_SERVER_ADDR2 222 -#define configDNS_SERVER_ADDR3 222 - -/* Default netmask configuration. Used in ipconfigUSE_DNS is set to 0, or -ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configNET_MASK0 255 -#define configNET_MASK1 255 -#define configNET_MASK2 255 -#define configNET_MASK3 0 - -/* The address of the echo server. Used when the demo is build to include the -UDP echo tasks (when mainINCLUDE_ECHO_CLIENT_TASKS is set to 1 in -FreeRTOSConfig.h. -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */ -#define configECHO_SERVER_ADDR0 172 -#define configECHO_SERVER_ADDR1 25 -#define configECHO_SERVER_ADDR2 218 -#define configECHO_SERVER_ADDR3 100 - - -/* The priority used by the Ethernet MAC driver interrupt. */ -#define configMAC_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ) - -/* Dimensions a buffer that can be used by the FreeRTOS+CLI command -interpreter. See the FreeRTOS+CLI documentation for more information: -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */ -#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1024 - -/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace -macros are defined to gather some UDP stack statistics that can then be viewed -through the CLI interface. */ -#define configINCLUDE_DEMO_DEBUG_STATS 1 - -#endif /* FREERTOS_CONFIG_H */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/FreeRTOSIPConfig.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/FreeRTOSIPConfig.h deleted file mode 100644 index 2f06ba469..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/FreeRTOSIPConfig.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * FreeRTOS+UDP V1.0.4 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/***************************************************************************** - * - * See the following URL for configuration information. - * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Configuration.shtml - * - *****************************************************************************/ - -#ifndef FREERTOS_IP_CONFIG_H -#define FREERTOS_IP_CONFIG_H - -/* The IP stack executes it its own task (although any application task can make -use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY -sets the priority of the task that executes the IP stack. The priority is a -standard FreeRTOS task priority so can take any value from 0 (the lowest -priority) to (configMAX_PRIORITIES - 1) (the highest priority). -configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in -FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to -the priority assigned to the task executing the IP stack relative to the -priority assigned to tasks that use the IP stack. - -Note: If the application is started without the network cable plugged in then -this should be set to the lowest priority - otherwise the Atmel ASF GMAC driver -will poll the GMAC interface waiting for a connection to be established. The -driver uses a very long timeout and no lower priority tasks will be able to -execute during this time. This demo starts with the IP task running at the idle -priority - then raises the priority of the IP task in the network event hook -when a connection has been established. */ -#define ipconfigUDP_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+UDP -task. This setting is less important when the FreeRTOS Win32 simulator is used -as the Win32 simulator only stores a fixed amount of information on the task -stack. FreeRTOS includes optional stack overflow detection, see: -http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigUDP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 2 ) - -/* ipconfigRAND32() is called by the IP stack to generate a random number that -is then used as a DHCP transaction number. Random number generation is performed -via this macro to allow applications to use their own random number generation -method. For example, it might be possible to generate a random number by -sampling noise on an analogue input. */ -#define ipconfigRAND32() 1 - -/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+UDP will call the -network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK -is not set to 1 then the network event hook will never be called. See -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml -*/ -#define ipconfigUSE_NETWORK_EVENT_HOOK 1 - -/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but -a network buffer cannot be obtained then the calling task is held in the Blocked -state (so other tasks can continue to executed) until either a network buffer -becomes available or the send block time expires. If the send block time expires -then the send operation is aborted. The maximum allowable send block time is -capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the -maximum allowable send block time prevents prevents a deadlock occurring when -all the network buffers are in use and the tasks that process (and subsequently -free) the network buffers are themselves blocked waiting for a network buffer. -ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in -milliseconds can be converted to a time in ticks by dividing the time in -milliseconds by portTICK_PERIOD_MS. */ -#define ipconfigMAX_SEND_BLOCK_TIME_TICKS ( 20 / portTICK_PERIOD_MS ) - -/* If ipconfigUSE_DHCP is 1 then FreeRTOS+UDP will attempt to retrieve an IP -address, netmask, DNS server address and gateway address from a DHCP server. If -ipconfigUSE_DHCP is 0 then FreeRTOS+UDP will use a static IP address. The -stack will revert to using the static IP address even when ipconfigUSE_DHCP is -set to 1 if a valid configuration cannot be obtained from a DHCP server for any -reason. The static configuration used is that passed into the stack by the -FreeRTOS_IPInit() function call. */ -#define ipconfigUSE_DHCP 1 - -/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at -increasing time intervals until either a reply is received from a DHCP server -and accepted, or the interval between transmissions reaches -ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the -static IP address passed as a parameter to FreeRTOS_IPInit() if the -re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without -a DHCP reply being received. */ -#define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 999 / portTICK_PERIOD_MS ) - -/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP -stack can only send a UDP message to a remove IP address if it knowns the MAC -address associated with the IP address, or the MAC address of the router used to -contact the remote IP address. When a UDP message is received from a remote IP -address the MAC address and IP address are added to the ARP cache. When a UDP -message is sent to a remote IP address that does not already appear in the ARP -cache then the UDP message is replaced by a ARP message that solicits the -required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum -number of entries that can exist in the ARP table at any one time. */ -#define ipconfigARP_CACHE_ENTRIES 6 - -/* ARP requests that do not result in an ARP response will be re-transmitted a -maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is -aborted. */ -#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 ) - -/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP -table being created or refreshed and the entry being removed because it is stale. -New ARP requests are sent for ARP cache entries that are nearing their maximum -age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is -equal to 1500 seconds (or 25 minutes). */ -#define ipconfigMAX_ARP_AGE 150 - -/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling -routines, which are relatively large. To save code space the full -FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster -alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr() -takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter. -FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets -(for example, 192, 168, 0, 1) as its parameters. If -ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and -FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is -not set to 1 then only FreeRTOS_indet_addr_quick() is available. */ -#define ipconfigINCLUDE_FULL_INET_ADDR 1 - -/* ipconfigNUM_NETWORK_BUFFERS defines the total number of network buffer that -are available to the IP stack. The total number of network buffers is limited -to ensure the total amount of RAM that can be consumed by the IP stack is capped -to a pre-determinable value. */ -#define ipconfigNUM_NETWORK_BUFFERS 10 - -/* A FreeRTOS queue is used to send events from application tasks to the IP -stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can -be queued for processing at any one time. The event queue must be a minimum of -5 greater than the total number of network buffers. */ -#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFERS + 5 ) - -/* The address of a socket is the combination of its IP address and its port -number. FreeRTOS_bind() is used to manually allocate a port number to a socket -(to 'bind' the socket to a port), but manual binding is not normally necessary -for client sockets (those sockets that initiate outgoing connections rather than -wait for incoming connections on a known port number). If -ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling -FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP -stack automatically binding the socket to a port number from the range -socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If -ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto() -on a socket that has not yet been bound will result in the send operation being -aborted. */ -#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1 - -/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */ -#define updconfigIP_TIME_TO_LIVE 128 - -/* If ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 1 then UDP packets that -contain more data than will fit in a single network frame will be fragmented -across multiple IP packets. Also see the ipconfigNETWORK_MTU setting. If -ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must -be divisible by 8. Setting ipconfigCAN_FRAGMENT_OUTGOING_PACKETS to 1 will -increase both the code size and execution time. */ -#define ipconfigCAN_FRAGMENT_OUTGOING_PACKETS 0 - -/* The MTU is the maximum number of bytes the payload of a network frame can -contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a -lower value can save RAM, depending on the buffer management scheme used. If -ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must -be divisible by 8. */ -#define ipconfigNETWORK_MTU 1500 /* Leave at 1500 for SAM4E. */ - -/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used -through the FreeRTOS_gethostbyname() API function. */ -#define ipconfigUSE_DNS 1 - -/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will -generate replies to incoming ICMP echo (ping) requests. */ -#define ipconfigREPLY_TO_INCOMING_PINGS 1 - -/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the -FreeRTOS_SendPingRequest() API function is available. */ -#define ipconfigSUPPORT_OUTGOING_PINGS 1 - -/* If ipconfigSUPPORT_SELECT_FUNCTION is set to 1 then the FreeRTOS_select() -(and associated) API function is available. */ -#define ipconfigSUPPORT_SELECT_FUNCTION 1 - -/* Used for stack testing only, and must be implemented in the network -interface. */ -#define updconfigLOOPBACK_ETHERNET_PACKETS 0 - -/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames -that are not in Ethernet II format will be dropped. This option is included for -potential future IP stack developments. */ -#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1 - -/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the -responsibility of the Ethernet interface to filter out packets that are of no -interest. If the Ethernet interface does not implement this functionality, then -set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack -perform the filtering instead (it is much less efficient for the stack to do it -because the packet will already have been passed into the stack). If the -Ethernet driver does all the necessary filtering in hardware then software -filtering can be removed by using a value other than 1 or 0. */ -#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 0 - -/* If ipconfigETHERNET_DRIVER_ADDS_UDP_CHECKSUM is set to 1 then a UDP checksum -will not be calculated and added to a packet before the packet is sent to the -hardware for transmission. */ -#define ipconfigETHERNET_DRIVER_ADDS_UDP_CHECKSUM 0 - -/* If ipconfigETHERNET_DRIVER_ADDS_IP_CHECKSUM is set to 1 then an IP checksum -will not be calculated and added to a packet before the packet is sent to the -hardware for transmission. */ -#define ipconfigETHERNET_DRIVER_ADDS_IP_CHECKSUM 0 - -/* If ipconfigETHERNET_DRIVER_CHECKS_IP_CHECKSUM is set to 1 then the IP -checksum will be ignored on incoming packets on the assumption IP packets with -an invalid checksum are not passed to the stack. */ -#define ipconfigETHERNET_DRIVER_CHECKS_IP_CHECKSUM 0 - -/* If ipconfigETHERNET_DRIVER_CHECKS_UDP_CHECKSUM is set to 1 then the UDP -checksum will be ignored on incoming packets on the assumption the UDP packets -with an invalid checksum are not passed to the stack. */ -#define ipconfigETHERNET_DRIVER_CHECKS_UDP_CHECKSUM 0 - -/* Set ipconfigFREERTOS_PLUS_NABTO to 1 to support the Nabto protocol, or 0 to -exclude support for the Nabto protocol. If ipconfigFREERTOS_PLUS_NABTO is set -to one then the project must build the Nabto source code (or reference a -pre-build Nabto library. */ -#define ipconfigFREERTOS_PLUS_NABTO 0 - -/* Sets the size of the stack used by the Nabto service task. The Nabto event -handler executes in the context of the Nabto service task. If the event handler -uses a lot of stack then it is possible the value set here will need to be -increased. It is recommended to have FreeRTOS stack overflow checking turned -on during development (see the configCHECK_FOR_STACK_OVERFLOW in -FreeRTOSConfig.h and in the documentation. */ -#define ipconfigNABTO_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) - -/* Sets the priority of the Nabto service task. This is a standard FreeRTOS -task priority so can take values between 0 (the lowest priority) and -configMAX_PRIORITIES - 1 (the highest priority). Also see the definition of -ipconfigUDP_TASK_PRIORITY. This would normally be set to be either one higher -or one lower than ipconfigUDP_TASK_PRIORITY, depending on the application. */ -#define ipconfigNABTO_TASK_PRIORITY ( ipconfigUDP_TASK_PRIORITY + 1 ) - -/* The windows simulator cannot really simulate MAC interrupts, and needs to -block occasionally to allow other tasks to run. */ -#ifdef _WINDOWS_ - #define configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ( 3 / portTICK_PERIOD_MS ) -#endif - -/* The example IP trace macros are included here so the definitions are -available in all the FreeRTOS+UDP source files. */ -#include "DemoIPTrace.h" - -#endif /* FREERTOS_IP_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_aat31xx.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_aat31xx.h deleted file mode 100644 index 0d757c52f..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_aat31xx.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * \brief AAT31XX configuration. - * - * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -//! Configuration of the AAT31XX Backlight driver - -#ifndef CONF_AAT31XX_H_INCLUDED -#define CONF_AAT31XX_H_INCLUDED - -#include "board.h" - -#if !defined(BOARD_AAT31XX_SET_GPIO) - - #warning The AAT31XX PIN configuration does not exist in the board definition file. Using default settings. - - #define BOARD_AAT31XX_SET_GPIO PIO_PC13_IDX /* Should use the PIN index of which pin is connected with EN/SET of AAT31XX device */ - -#endif - -#endif /* CONF_AAT31XX_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_board.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_board.h deleted file mode 100644 index e616581ec..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_board.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * \file - * - * \brief SAM4E-EK board configuration. - * - * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CONF_BOARD_H_INCLUDED -#define CONF_BOARD_H_INCLUDED - -/* Configure UART pins */ -//#define CONF_BOARD_UART_CONSOLE - -/* Enable ETH PHY: KSZ8051MNL feature */ -#define CONF_BOARD_KSZ8051MNL - -/** Configure LCD EBI pins */ -#define CONF_BOARD_ILI93XX - -/** Configure Backlight control pin */ -#define CONF_BOARD_AAT3155 - -/* - * LED pins are not configured for PWM function here. - * Because those LED pins are enabled for PIO function by default. - * You can enable them according to application. - */ -/* Configure PWM LED0 pin */ -//#define CONF_BOARD_PWM_LED0 - -/* Configure PWM LED1 pin */ -//#define CONF_BOARD_PWM_LED1 - -/* Configure PWM LED2 pin */ -//#define CONF_BOARD_PWM_LED2 - -/* Configure PWM LED3 pin */ -//#define CONF_BOARD_PWM_LED3 - -/* - * USART pins are configured as basic serial port by default. - * You can enable other pins according application. - */ -/* Configure USART RXD pin */ -//#define CONF_BOARD_USART_RXD - -/* Configure USART TXD pin */ -//#define CONF_BOARD_USART_TXD - -/* Configure USART CTS pin */ -//#define CONF_BOARD_USART_CTS - -/* Configure USART RTS pin */ -//#define CONF_BOARD_USART_RTS - -/* Configure USART synchronous communication SCK pin */ -//#define CONF_BOARD_USART_SCK - -/* Configure ADM3312 enable pin */ -//#define CONF_BOARD_ADM3312_EN -//#define CONF_BOARD_ADM3312_EN_DISABLE_AT_INIT - -#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_clock.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_clock.h deleted file mode 100644 index 65f41e2cf..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_clock.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - * \file - * - * \brief SAM4E clock configuration. - * - * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CONF_CLOCK_H_INCLUDED -#define CONF_CLOCK_H_INCLUDED - -// ===== System Clock (MCK) Source Options -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS -#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK - -// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES)) -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 -#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 - -// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) -// Use mul and div effective values here. -#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL -#define CONFIG_PLL0_MUL 16 -#define CONFIG_PLL0_DIV 1 - - -// ===== USB Clock Source Options (Fusb = FpllX / USB_div) -// Use div effective value here. -#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 -#define CONFIG_USBCLK_DIV 2 - -// ===== Target frequency (System clock) -// - XTAL frequency: 12MHz -// - System clock source: PLLA -// - System clock prescaler: 2 (divided by 2) -// - PLLA source: XTAL -// - PLLA output: XTAL * 16 / 1 -// - System clock: 12 * 16 / 1 / 2 = 96MHz -// ===== Target frequency (USB Clock) -// - USB clock source: PLLA -// - USB clock divider: 2 (divided by 2) -// - PLLA output: XTAL * 16 / 2 -// - USB clock: 12 * 16 / 2 / 2 = 48MHz - - -#endif /* CONF_CLOCK_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_eth.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_eth.h deleted file mode 100644 index 842c2293b..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_eth.h +++ /dev/null @@ -1,77 +0,0 @@ - /** - * \file - * - * \brief GMAC (Ethernet MAC) driver for SAM. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CONF_EMAC_H_INCLUDED -#define CONF_EMAC_H_INCLUDED - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -#include "gmac.h" - -/** Number of buffer for RX */ -#define GMAC_RX_BUFFERS 64 - -/** Number of buffer for TX */ -#define GMAC_TX_BUFFERS 16 - -/** MAC PHY operation max retry count */ -#define MAC_PHY_RETRY_MAX 1000000 - -/** Ethernet MII/RMII mode */ -#define ETH_PHY_MODE GMAC_PHY_MII - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* CONF_EMAC_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_ili93xx.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_ili93xx.h deleted file mode 100644 index 53ee3cbec..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/conf_ili93xx.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * \brief ILI93XX configuration. - * - * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -//! Configuration of the ILI93XX (ILI9325 or ILI9341) LCD display driver - -#ifndef CONF_ILI93XX_H_INCLUDED -#define CONF_ILI93XX_H_INCLUDED - -#include "board.h" - -#if !defined(BOARD_ILI93XX_ADDR) || !defined(BOARD_ILI93XX_RS) - - #warning The ILI93XX EBI configuration does not exist in the board definition file. Using default settings. - - /** The base address, depends on which SMC chip select is used by ILI9325. */ - #define BOARD_ILI93XX_ADDR 0x61000000 - /** Register select (1 << 1) */ - #define BOARD_ILI93XX_RS 1 << 1 - -#endif - -#endif /* CONF_ILI93XX_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/config_fat_sl.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/config_fat_sl.h deleted file mode 100644 index 8647077ee..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/config_fat_sl.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * FreeRTOS+FAT SL V1.0.1 (C) 2014 HCC Embedded - * - * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers - * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of - * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS, - * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual - * license model, information on which is provided below: - * - * - Open source licensing - - * FreeRTOS+FAT SL is a free download and may be used, modified and distributed - * without charge provided the user adheres to version two of the GNU General - * Public license (GPL) and does not remove the copyright notice or this text. - * The GPL V2 text is available on the gnu.org web site, and on the following - * URL: http://www.FreeRTOS.org/gpl-2.0.txt - * - * - Commercial licensing - - * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into - * proprietary software for redistribution in any form must first obtain a - * commercial license - and in-so-doing support the maintenance, support and - * further development of the FreeRTOS+FAT SL product. Commercial licenses can - * be obtained from http://shop.freertos.org and do not require any source files - * to be changed. - * - * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You - * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as - * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the - * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A - * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all - * conditions and terms, be they implied, expressed, or statutory. - * - * http://www.FreeRTOS.org - * http://www.FreeRTOS.org/FreeRTOS-Plus - * - */ - -#ifndef _CONFIG_FAT_SL_H -#define _CONFIG_FAT_SL_H - -#include "../version/ver_fat_sl.h" -#if VER_FAT_SL_MAJOR != 5 || VER_FAT_SL_MINOR != 2 - #error Incompatible FAT_SL version number! -#endif - -#include "../api/api_mdriver.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/************************************************************************** -** -** FAT SL user settings -** -**************************************************************************/ -#define F_SECTOR_SIZE 512u /* Disk sector size. */ -#define F_FS_THREAD_AWARE 1 /* Set to one if the file system will be access from more than one task. */ -#define F_MAXPATH 64 /* Maximum length a file name (including its full path) can be. */ -#define F_MAX_LOCK_WAIT_TICKS 20 /* The maximum number of RTOS ticks to wait when attempting to obtain a lock on the file system when F_FS_THREAD_AWARE is set to 1. */ - -#ifdef __cplusplus -} -#endif - -#endif /* _CONFIG_FAT_SL_H */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/config_mdriver_ram.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/config_mdriver_ram.h deleted file mode 100644 index de630faf2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/config/config_mdriver_ram.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * FreeRTOS+FAT SL V1.0.1 (C) 2014 HCC Embedded - * - * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers - * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of - * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS, - * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual - * license model, information on which is provided below: - * - * - Open source licensing - - * FreeRTOS+FAT SL is a free download and may be used, modified and distributed - * without charge provided the user adheres to version two of the GNU General - * Public license (GPL) and does not remove the copyright notice or this text. - * The GPL V2 text is available on the gnu.org web site, and on the following - * URL: http://www.FreeRTOS.org/gpl-2.0.txt - * - * - Commercial licensing - - * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into - * proprietary software for redistribution in any form must first obtain a - * commercial license - and in-so-doing support the maintenance, support and - * further development of the FreeRTOS+FAT SL product. Commercial licenses can - * be obtained from http://shop.freertos.org and do not require any source files - * to be changed. - * - * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You - * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as - * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the - * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A - * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all - * conditions and terms, be they implied, expressed, or statutory. - * - * http://www.FreeRTOS.org - * http://www.FreeRTOS.org/FreeRTOS-Plus - * - */ - -#ifndef _CONFIG_MDRIVER_RAM_H_ -#define _CONFIG_MDRIVER_RAM_H_ - -#include "../version/ver_mdriver_ram.h" -#if VER_MDRIVER_RAM_MAJOR != 1 || VER_MDRIVER_RAM_MINOR != 2 - #error Incompatible MDRIVER_RAM version number! -#endif - -#define MDRIVER_RAM_SECTOR_SIZE 512 /* Sector size */ - -#define MDRIVER_RAM_VOLUME0_SIZE (28 * 1024) /* definition for size of ramdrive0 */ - -#define MDRIVER_MEM_LONG_ACCESS 1 /* set this value to 1 if 32bit access available */ - -#endif /* ifndef _CONFIG_MDRIVER_RAM_H_ */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/logo_atmel.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/logo_atmel.h deleted file mode 100644 index c2ce4b9f7..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/logo_atmel.h +++ /dev/null @@ -1,15412 +0,0 @@ -/** - * \file - * - * \brief Atmel logo for the FreeRTOS Web/DSP Demo. - * - * Copyright (c) 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef __ATMEL_LOGO_H__ -#define __ATMEL_LOGO_H__ -const uint8_t logo_atmel_bmp[230454]= -{ -0x42,0x4d,0x36,0x84,0x03,0x00,0x00,0x00,0x00,0x00,0x36,0x00,0x00,0x00,0x28, -0x00,0x00,0x00,0xf0,0x00,0x00,0x00,0x40,0x01,0x00,0x00,0x01,0x00,0x18,0x00, -0x00,0x00,0x00,0x00,0x00,0x84,0x03,0x00,0x13,0x0b,0x00,0x00,0x13,0x0b,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff,0xff,0xff, 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-0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc, -0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc, -0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc, -0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc, -0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc, -0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc, -0xfc,0xfe,0xfc,0xfc,0xfe,0xfc,0xfc,0xfe,0xfc -}; -#endif /* __ATMEL_LOGO_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main.c deleted file mode 100644 index d1e42e4f3..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.0 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/****************************************************************************** - * This project provides two demo applications. A simple blinky style project, - * and a more comprehensive application that includes FreeRTOS+CLI, FreeRTOS+UDP - * and FreeRTOS+FAT SL. The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined - * in this file) is used to select between the two. The simply blinky demo is - * implemented and described in main_blinky.c. The more comprehensive demo - * application is implemented and described in main_full.c and full user - * instructions are provided on the following URL: - * http://www.FreeRTOS.org/Atmel_SAM4E_RTOS_Demo.html - * - * This file implements the code that is not demo specific, including the - * hardware setup and FreeRTOS hook functions. - * - */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "partest.h" - -/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive demo application that includes add-on -components. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 - -/*-----------------------------------------------------------*/ - -/* - * Set up the hardware ready to run this demo. - */ -static void prvSetupHardware( void ); - -/* - * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. - */ -extern void main_blinky( void ); -extern void main_full( void ); - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - /* Full user instructions are provided on the following URL: - http://www.FreeRTOS.org/Atmel_SAM4E_RTOS_Demo.html */ - main_full(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ - - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Call the ASF initialisation functions. */ - board_init(); - sysclk_init(); - pmc_enable_periph_clk( ID_GMAC ); - pmc_enable_periph_clk( ID_SMC ); -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ -static volatile uint32_t ulCount = 0; - - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). - - Just count the number of malloc fails as some failures may occur simply - because the network load is very high, resulting in the consumption of a - lot of network buffers. */ - ulCount++; -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ - - /* The simple blinky demo does not use the idle hook - the full demo does. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 ) - { - extern void vFullDemoIdleHook( void ); - - /* Implemented in main_full.c. */ - vFullDemoIdleHook(); - } - #endif -} -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is - called if a stack overflow is detected. */ - vAssertCalled( __LINE__, __FILE__ ); -} -/*-----------------------------------------------------------*/ - -void vApplicationTickHook( void ) -{ - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ - - /* The simple blinky demo does not use the tick hook - the full demo does. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 ) - { - extern void vFullDemoTickHook( void ); - - /* Implemented in main_full.c. */ - vFullDemoTickHook(); - } - #endif -} -/*-----------------------------------------------------------*/ - -void vAssertCalled( uint32_t ulLine, const char *pcFile ) -{ -/* The following two variables are just to ensure the parameters are not -optimised away and therefore unavailable when viewed in the debugger. */ -volatile uint32_t ulLineNumber = ulLine, ulSetNonZeroInDebuggerToReturn = 0; -volatile const char * const pcFileName = pcFile; - - taskENTER_CRITICAL(); - while( ulSetNonZeroInDebuggerToReturn == 0 ) - { - /* If you want to set out of this function in the debugger to see the - assert() location then set ulSetNonZeroInDebuggerToReturn to a non-zero - value. */ - } - taskEXIT_CRITICAL(); - - ( void ) pcFileName; - ( void ) ulLineNumber; -} -/*-----------------------------------------------------------*/ - -/* Provided to keep the linker happy. */ -void _exit_( int status ) -{ - ( void ) status; - vAssertCalled( __LINE__, __FILE__ ); - for( ;; ); -} -/*-----------------------------------------------------------*/ - -/* Provided to keep the linker happy. */ -int _read( void ) -{ - return 0; -} -/*-----------------------------------------------------------*/ - -/* Provided to keep the linker happy. */ -int _write( int x ) -{ - ( void ) x; - return 0; -} -/*-----------------------------------------------------------*/ - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main_blinky.c deleted file mode 100644 index e7e31d048..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main_blinky.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.0 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive demo application that makes use of - * FreeRTOS_CLI, FreeRTOS+UDP and FreeRTOS+FAT SL. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the simply blinky style version. - * - * NOTE 2: This file only contains the source code that is specific to the - * basic demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - ****************************************************************************** - * - * main_blinky() creates one queue, two tasks and one software timer. It then - * starts the scheduler. - * - * The Queue Send Task: - * The queue send task is implemented by the prvQueueSendTask() function in - * this file. The task sits in a loop that sends a value to the queue every - * 200 milliseconds. - * - * The Queue Receive Task: - * The queue receive task is implemented by the prvQueueReceiveTask() function - * in this file. The task sits in a loop that blocks on the queue to wait for - * data to arrive (it does not use any CPU time while it is in the Blocked - * state), toggling an LED each time it receives the value sent by the queue - * send task. As the queue send task writes to the queue every 200 milliseconds - * the LED will toggle every 200 milliseconds. - */ - - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "timers.h" - -/* Demo application includes. */ -#include "partest.h" - -/* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) - -/* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) - -/* The period of the blinky software timer. The period is specified in ms and -converted to ticks using the portTICK_PERIOD_MS constant. */ -#define mainBLINKY_TIMER_PERIOD ( 50 / portTICK_PERIOD_MS ) - -/* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0 ) - -/* The LEDs toggled by the timer callback and queue receive task respectively. */ -#define mainTIMER_LED 0 -#define mainTASK_LED 1 - -/*-----------------------------------------------------------*/ - -/* - * The tasks as described in the comments at the top of this file. - */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); - -/* - * The callback function for the blinky software timer, as described at the top - * of this file. - */ -static void prvBlinkyTimerCallback( TimerHandle_t xTimer ); - -/* - * Called by main() to create the simply blinky style application if - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - */ -void main_blinky( void ); - -/*-----------------------------------------------------------*/ - -void main_blinky( void ) -{ -TimerHandle_t xTimer; -QueueHandle_t xQueue; - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) xQueue, /* Pass the queue into the task using the task parameter. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) xQueue, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the blinky software timer as described at the top of this - file. */ - xTimer = xTimerCreate( "Blinky", /* A text name, purely to help debugging. */ - ( mainBLINKY_TIMER_PERIOD ),/* The timer period. */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvBlinkyTimerCallback ); /* The callback function that inspects the status of all the other tasks. */ - - configASSERT( xTimer ); - - if( xTimer != NULL ) - { - xTimerStart( xTimer, mainDONT_BLOCK ); - } - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTask( void *pvParameters ) -{ -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; -QueueHandle_t xQueue; - - /* The handle of the queue is passed in using the task's parameter. */ - xQueue = ( QueueHandle_t ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK ); - } -} -/*-----------------------------------------------------------*/ - -static void prvQueueReceiveTask( void *pvParameters ) -{ -unsigned long ulReceivedValue; -QueueHandle_t xQueue; - - /* The queue is passed in as the task's parameter. */ - xQueue = ( QueueHandle_t ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - vParTestToggleLED( mainTASK_LED ); - ulReceivedValue = 0U; - } - } -} -/*-----------------------------------------------------------*/ - -static void prvBlinkyTimerCallback( TimerHandle_t xTimer ) -{ - /* Avoid compiler warnings. */ - ( void ) xTimer; - - /* This function is called when the blinky software time expires. All the - function does is toggle the LED. LED mainTIMER_LED should therefore toggle - with the period set by mainBLINKY_TIMER_PERIOD. */ - vParTestToggleLED( mainTIMER_LED ); -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main_full.c deleted file mode 100644 index 60cf15a5b..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/main_full.c +++ /dev/null @@ -1,934 +0,0 @@ -/* - * FreeRTOS Kernel V10.1.0 - * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application that makes use of - * the FreeRTOS+CLI, FreeRTOS+UDP and FreeRTOS+FAT SL components. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the comprehensive test and demo version, - * which is fully documented on the following URL: - * http://www.FreeRTOS.org/Atmel_SAM4E_RTOS_Demo.html - * - * NOTE 2: This file only contains the source code that is specific to the - * full demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - ****************************************************************************** - * - * Full user instructions are provided on the following URL: - * http://www.FreeRTOS.org/Atmel_SAM4E_RTOS_Demo.html - * - * main_full(): - * + Uses FreeRTOS+FAT SL to create a set of example files on a RAM disk. - * + Displays some bitmaps on the LCD. - * + Registers sample generic, file system related and UDP related commands - * with FreeRTOS+CLI. - * + Creates all the standard demo application tasks and software timers. - * + Starts the scheduler. - * - * A UDP command server and optionally two UDP echo client tasks are created - * from the network event hook after an IP address has been obtained. The IP - * address is displayed on the LCD. - * - * A "check software timer" is created to provide visual feedback of the system - * status. The timer's period is initially set to three seconds. The callback - * function associated with the timer checks all the standard demo tasks are not - * only still executed, but are executing without reporting any errors. If the - * timer discovers a task has either stalled, or reported an error, then it - * changes its own period from the initial three seconds, to just 200ms. The - * check software timer also toggles the LED marked D4 - so if the LED toggles - * every three seconds then no potential errors have been found, and if the LED - * toggles every 200ms then a potential error has been found in at least one - * task. - * - * Information on accessing the CLI and file system, and using the UDP echo - * tasks is provided on http://www.FreeRTOS.org/Atmel_SAM4E_RTOS_Demo.html - * - */ - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" - -/* FreeRTOS+UDP includes. */ -#include "FreeRTOS_UDP_IP.h" -#include "FreeRTOS_Sockets.h" - -/* UDP demo includes. */ -#include "UDPCommandInterpreter.h" -#include "TwoEchoClients.h" - -/* Standard demo includes. */ -#include "partest.h" -#include "blocktim.h" -#include "flash_timer.h" -#include "semtest.h" -#include "GenQTest.h" -#include "QPeek.h" -#include "IntQueue.h" -#include "countsem.h" -#include "dynamic.h" -#include "QueueOverwrite.h" -#include "QueueSet.h" -#include "recmutex.h" -#include "EventGroupsDemo.h" -#include "TaskNotify.h" -#include "IntSemTest.h" -#include "TimerDemo.h" -#include "IntQueue.h" - -/* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) - -/* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) - -/* The priorities of the various demo application tasks. */ -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainQUEUE_OVERWRITE_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* The LED controlled by the 'check' software timer. */ -#define mainCHECK_LED ( 2 ) - -/* The number of LEDs that should be controlled by the flash software timer -standard demo. In this case it is only 1 as the starter kit has three LEDs, one -of which is controlled by the check timer and one of which is controlled by the -ISR triggered task. */ -#define mainNUM_FLASH_TIMER_LEDS ( 1 ) - -/* Misc. */ -#define mainDONT_BLOCK ( 0 ) - -/* Note: If the application is started without the network cable plugged in -then ipconfigUDP_TASK_PRIORITY should be set to 0 in FreeRTOSIPConfig.h to -ensure the IP task is created at the idle priority. This is because the Atmel -ASF GMAC driver polls the GMAC looking for a connection, and doing so will -prevent any lower priority tasks from executing. In this demo the IP task is -started at the idle priority, then set to configMAX_PRIORITIES - 2 in the -network event hook only after a connection has been established (when the event -passed into the network event hook is eNetworkUp). -http://www.FreeRTOS.org/udp */ -#define mainCONNECTED_IP_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define mainDISCONNECTED_IP_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* UDP command server and echo task parameters. */ -#define mainUDP_CLI_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainUDP_CLI_PORT_NUMBER ( 5001UL ) -#define mainUDP_CLI_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 90 ) -#define mainECHO_CLIENT_STACK_SIZE ( configMINIMAL_STACK_SIZE + 30 ) - -/* Set to 1 to include the UDP echo client tasks in the build. The echo clients -require the IP address of the echo server to be defined using the -configECHO_SERVER_ADDR0 to configECHO_SERVER_ADDR3 constants in -FreeRTOSConfig.h. */ -#define mainINCLUDE_ECHO_CLIENT_TASKS 1 - -/* Used by the standard demo timer tasks. */ -#define mainTIMER_TEST_PERIOD ( 50 ) - -/*-----------------------------------------------------------*/ - -/* - * The check timer callback function, as described at the top of this file. - */ -static void prvCheckTimerCallback( TimerHandle_t xTimer ); - -/* - * Creates a set of sample files on a RAM disk. http://www.FreeRTOS.org/fat_sl - */ -extern void vCreateAndVerifySampleFiles( void ); - -/* - * Register sample generic commands that can be used with FreeRTOS+CLI. Type - * 'help' in the command line to see a list of registered commands. - * http://www.FreeRTOS.org/cli - */ -extern void vRegisterSampleCLICommands( void ); - -/* - * Register sample file system commands that can be used with FreeRTOS+CLI. - */ -extern void vRegisterFileSystemCLICommands( void ); - -/* - * Register sample UDP related commands that can be used with FreeRTOS+CLI. - */ -extern void vRegisterUDPCLICommands( void ); - -/* - * Initialise the LCD and output a bitmap. - */ -extern void vInitialiseLCD( void ); - -/* - * Register check tasks, and the tasks used to write over and check the contents - * of the FPU registers, as described at the top of this file. The nature of - * these files necessitates that they are written in an assembly file. - */ -static void prvRegTest1Task( void *pvParameters ) __attribute__((naked)); -static void prvRegTest2Task( void *pvParameters ) __attribute__((naked)); - -/*-----------------------------------------------------------*/ - -/* The default IP and MAC address used by the demo. The address configuration -defined here will be used if ipconfigUSE_DHCP is 0, or if ipconfigUSE_DHCP is -1 but a DHCP server could not be contacted. See the online documentation for -more information. */ -static const uint8_t ucIPAddress[ 4 ] = { configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 }; -static const uint8_t ucNetMask[ 4 ] = { configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 }; -static const uint8_t ucGatewayAddress[ 4 ] = { configGATEWAY_ADDR0, configGATEWAY_ADDR1, configGATEWAY_ADDR2, configGATEWAY_ADDR3 }; -static const uint8_t ucDNSServerAddress[ 4 ] = { configDNS_SERVER_ADDR0, configDNS_SERVER_ADDR1, configDNS_SERVER_ADDR2, configDNS_SERVER_ADDR3 }; - -/* The MAC address used by the demo. In production units the MAC address would -probably be read from flash memory or an EEPROM. Here it is just hard coded. -Note each node on a network must have a unique MAC address. */ -const uint8_t ucMACAddress[ 6 ] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 }; - -/* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ -volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; - -/*-----------------------------------------------------------*/ - -int main_full( void ) -{ - /* Usage instructions on http://www.FreeRTOS.org/Atmel_SAM4E_RTOS_Demo.html */ - - /* Initialise the LCD and output a bitmap. The IP address will also be - displayed on the LCD when it has been obtained. */ - vInitialiseLCD(); - - /* If the file system is only going to be accessed from one task then - F_FS_THREAD_AWARE can be set to 0 and the set of example files are created - before the RTOS scheduler is started. If the file system is going to be - access from more than one task then F_FS_THREAD_AWARE must be set to 1 and - the set of sample files are created from the idle task hook function - vApplicationIdleHook(). */ - #if( F_FS_THREAD_AWARE == 0 ) - { - /* Initialise the drive and file system, then create a few example - files. The files can be viewed and accessed via the CLI. View the - documentation page for this demo (link at the top of this file) for more - information. */ - vCreateAndVerifySampleFiles(); - } - #endif - - /* Register example generic, file system related and UDP related CLI - commands respectively. Type 'help' into the command console to view a list - of registered commands. */ - vRegisterSampleCLICommands(); - vRegisterFileSystemCLICommands(); - vRegisterUDPCLICommands(); - - /* Initialise the network interface. Tasks that use the network are - created in the network event hook when the network is connected and ready - for use. The address values passed in here are used if ipconfigUSE_DHCP is - set to 0, or if ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be - contacted. The IP address actually used is displayed on the LCD (after DHCP - has completed if DHCP is used). */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); - - /* Create all the other standard demo tasks. */ - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - vStartQueuePeekTasks(); - vStartCountingSemaphoreTasks(); - vStartDynamicPriorityTasks(); - vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_TASK_PRIORITY ); - vStartQueueSetTasks(); - vStartRecursiveMutexTasks(); - vStartEventGroupTasks(); - vStartTaskNotifyTask(); - vStartInterruptSemaphoreTasks(); - vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); - vStartInterruptQueueTasks(); - - /* Create the register check tasks, as described at the top of this - file */ - xTaskCreate( prvRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Start the scheduler itself. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvCheckTimerCallback( TimerHandle_t xTimer ) -{ -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorOccurred = pdFALSE; - - /* Avoid compiler warnings. */ - ( void ) xTimer; - - /* Have any of the standard demo tasks detected an error in their - operation? */ - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 3UL ); - } - else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 4UL ); - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 5UL ); - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 6UL ); - } - else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 8UL ); - } - else if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 9UL ); - } - else if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 10UL ); - } - else if( xAreQueueSetTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 11UL ); - } - else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 12UL ); - } - else if( xAreEventGroupTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 13UL ); - } - else if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 14UL ); - } - else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= ( 0x01UL << 15UL ); - } - else if( xAreTimerDemoTasksStillRunning( mainCHECK_TIMER_PERIOD_MS ) != pdTRUE ) - { - ulErrorOccurred |= 1UL << 16UL; - } - else if( xAreIntQueueTasksStillRunning() != pdTRUE ) - { - ulErrorOccurred |= 1UL << 17UL; - } - - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorOccurred |= 1UL << 18UL; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorOccurred |= 1UL << 19UL; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - if( ulErrorOccurred != pdFALSE ) - { - /* An error occurred. Increase the frequency at which the check timer - toggles its LED to give visual feedback of the potential error - condition. */ - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block as to do so could impact other software - timers. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } - - /* Toggle the LED to give visual feedback of the system status. The rate at - which the LED toggles will increase to mainERROR_CHECK_TIMER_PERIOD_MS if a - suspected error has been found in any of the standard demo tasks. */ - vParTestToggleLED( mainCHECK_LED ); -} -/*-----------------------------------------------------------*/ - -/* Called by FreeRTOS+UDP when the network connects. */ -void vApplicationIPNetworkEventHook( eIPCallbackEvent_t eNetworkEvent ) -{ -static long lTasksAlreadyCreated = pdFALSE; -const unsigned long ulXCoord = 3, ulYCoord = 3, ulIPAddressOffset = 45; -unsigned long ulIPAddress; -char cIPAddress[ 20 ]; - - /* Note: If the application is started without the network cable plugged in - then ipconfigUDP_TASK_PRIORITY should be set to 0 in FreeRTOSIPConfig.h to - ensure the IP task is created at the idle priority. This is because the Atmel - ASF GMAC driver polls the GMAC looking for a connection, and doing so will - prevent any lower priority tasks from executing. In this demo the IP task is - started at the idle priority, then set to configMAX_PRIORITIES - 2 in the - network event hook only after a connection has been established (when the event - passed into the network event hook is eNetworkUp). */ - if( eNetworkEvent == eNetworkUp ) - { - /* Ensure tasks are only created once. */ - if( lTasksAlreadyCreated == pdFALSE ) - { - /* Create the task that handles the CLI on a UDP port. The port - number is set using the configUDP_CLI_PORT_NUMBER setting in - FreeRTOSConfig.h. */ - vStartUDPCommandInterpreterTask( mainUDP_CLI_TASK_STACK_SIZE, mainUDP_CLI_PORT_NUMBER, mainUDP_CLI_TASK_PRIORITY ); - - #if( mainINCLUDE_ECHO_CLIENT_TASKS == 1 ) - { - /* Create the UDP echo tasks. The UDP echo tasks require the IP - address of the echo server to be defined using the - configECHO_SERVER_ADDR0 to configECHO_SERVER_ADDR3 constants in - FreeRTOSConfig.h. */ - vStartEchoClientTasks( mainECHO_CLIENT_STACK_SIZE, tskIDLE_PRIORITY ); - } - #endif - } - - /* Obtain the IP address, convert it to a string, then display it on the - LCD. */ - FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL ); - FreeRTOS_inet_ntoa( ulIPAddress, cIPAddress ); - ili93xx_draw_string( ulXCoord, ulYCoord, ( uint8_t * ) "IP: " ); - ili93xx_draw_string( ulXCoord + ulIPAddressOffset, ulYCoord, ( uint8_t * ) cIPAddress ); - - /* Set the priority of the IP task up to the desired priority now it has - connected. */ - vTaskPrioritySet( NULL, mainCONNECTED_IP_TASK_PRIORITY ); - } - - /* NOTE: At the time of writing the Ethernet driver does not report the - cable being unplugged - so the following if() condition will never be met. - It is included for possible future updates to the driver. */ - if( eNetworkEvent == eNetworkDown ) - { - /* Ensure the Atmel GMAC drivers don't hog all the CPU time as they look - for a new connection by lowering the priority of the IP task to that of - the Idle task. */ - vTaskPrioritySet( NULL, tskIDLE_PRIORITY ); - - /* Disconnected - so no IP address. */ - ili93xx_draw_string( ulXCoord, ulYCoord, ( uint8_t * ) "IP: " ); - } -} -/*-----------------------------------------------------------*/ - -void vFullDemoIdleHook( void ) -{ -static TimerHandle_t xCheckTimer = NULL; - - if( xCheckTimer == NULL ) - { - /* Create the software timer that performs the 'check' - functionality, in the full demo. This is not done before the - scheduler is started as to do so would prevent the standard demo - timer tasks from passing their tests (they expect the timer - command queue to be empty. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback ); /* The callback function that inspects the status of all the other tasks. */ - - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* Also start some timers that just flash LEDs. */ - vStartLEDFlashTimers( mainNUM_FLASH_TIMER_LEDS ); - } - - /* If the file system is only going to be accessed from one task then - F_FS_THREAD_AWARE can be set to 0 and the set of example files is created - before the RTOS scheduler is started. If the file system is going to be - access from more than one task then F_FS_THREAD_AWARE must be set to 1 and - the set of sample files are created from the idle task hook function. */ - #if( F_FS_THREAD_AWARE == 1 ) - { - static portBASE_TYPE xCreatedSampleFiles = pdFALSE; - - /* Initialise the drive and file system, then create a few example - files. The output from this function just goes to the stdout window, - allowing the output to be viewed when the UDP command console is not - connected. */ - if( xCreatedSampleFiles == pdFALSE ) - { - vCreateAndVerifySampleFiles(); - xCreatedSampleFiles = pdTRUE; - } - } - #endif -} -/*-----------------------------------------------------------*/ - -void vFullDemoTickHook( void ) -{ - /* Call the periodic queue overwrite from ISR test function. */ - vQueueOverwritePeriodicISRDemo(); - - /* Call the periodic queue set ISR test function. */ - vQueueSetAccessQueueSetFromISR(); - - /* Call the event group ISR tests. */ - vPeriodicEventGroupsProcessing(); - - /* Exercise task notifications from interrupts. */ - xNotifyTaskFromISR(); - - /* Use mutexes from interrupts. */ - vInterruptSemaphorePeriodicTest(); - - /* Use timers from an interrupt. */ - vTimerPeriodicISRTests(); -} -/*-----------------------------------------------------------*/ - -/* Called automatically when a reply to an outgoing ping is received. */ -void vApplicationPingReplyHook( ePingReplyStatus_t eStatus, uint16_t usIdentifier ) -{ - /* This demo has nowhere to output any information so does nothing, but the - IP address resolved for the pined URL is displayed in the CLI. */ - ( void ) usIdentifier; - ( void ) eStatus; -} -/*-----------------------------------------------------------*/ - -/* This is a naked function. */ -static void prvRegTest1Task( void *pvParameters ) -{ - __asm volatile - ( - " /* Fill the core registers with known values. */ \n" - " mov r0, #100 \n" - " mov r1, #101 \n" - " mov r2, #102 \n" - " mov r3, #103 \n" - " mov r4, #104 \n" - " mov r5, #105 \n" - " mov r6, #106 \n" - " mov r7, #107 \n" - " mov r8, #108 \n" - " mov r9, #109 \n" - " mov r10, #110 \n" - " mov r11, #111 \n" - " mov r12, #112 \n" - " \n" - " /* Fill the VFP registers with known values. */ \n" - " vmov d0, r0, r1 \n" - " vmov d1, r2, r3 \n" - " vmov d2, r4, r5 \n" - " vmov d3, r6, r7 \n" - " vmov d4, r8, r9 \n" - " vmov d5, r10, r11 \n" - " vmov d6, r0, r1 \n" - " vmov d7, r2, r3 \n" - " vmov d8, r4, r5 \n" - " vmov d9, r6, r7 \n" - " vmov d10, r8, r9 \n" - " vmov d11, r10, r11 \n" - " vmov d12, r0, r1 \n" - " vmov d13, r2, r3 \n" - " vmov d14, r4, r5 \n" - " vmov d15, r6, r7 \n" - " \n" - "reg1_loop: \n" - " /* Check all the VFP registers still contain the values set above.\n" - " First save registers that are clobbered by the test. */ \n" - " push { r0-r1 } \n" - " \n" - " vmov r0, r1, d0 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d1 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d2 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d3 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d4 \n" - " cmp r0, #108 \n" - " bne reg1_error_loopf \n" - " cmp r1, #109 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d5 \n" - " cmp r0, #110 \n" - " bne reg1_error_loopf \n" - " cmp r1, #111 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d6 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d7 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d8 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d9 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d10 \n" - " cmp r0, #108 \n" - " bne reg1_error_loopf \n" - " cmp r1, #109 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d11 \n" - " cmp r0, #110 \n" - " bne reg1_error_loopf \n" - " cmp r1, #111 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d12 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d13 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d14 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d15 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " \n" - " /* Restore the registers that were clobbered by the test. */\n" - " pop {r0-r1} \n" - " \n" - " /* VFP register test passed. Jump to the core register test. */\n" - " b reg1_loopf_pass \n" - " \n" - "reg1_error_loopf: \n" - " /* If this line is hit then a VFP register value was found to be\n" - " incorrect. */ \n" - " b reg1_error_loopf \n" - " \n" - "reg1_loopf_pass: \n" - " \n" - " cmp r0, #100 \n" - " bne reg1_error_loop \n" - " cmp r1, #101 \n" - " bne reg1_error_loop \n" - " cmp r2, #102 \n" - " bne reg1_error_loop \n" - " cmp r3, #103 \n" - " bne reg1_error_loop \n" - " cmp r4, #104 \n" - " bne reg1_error_loop \n" - " cmp r5, #105 \n" - " bne reg1_error_loop \n" - " cmp r6, #106 \n" - " bne reg1_error_loop \n" - " cmp r7, #107 \n" - " bne reg1_error_loop \n" - " cmp r8, #108 \n" - " bne reg1_error_loop \n" - " cmp r9, #109 \n" - " bne reg1_error_loop \n" - " cmp r10, #110 \n" - " bne reg1_error_loop \n" - " cmp r11, #111 \n" - " bne reg1_error_loop \n" - " cmp r12, #112 \n" - " bne reg1_error_loop \n" - " \n" - " /* Everything passed, increment the loop counter. */ \n" - " push { r0-r1 } \n" - " ldr r0, =ulRegTest1LoopCounter \n" - " ldr r1, [r0] \n" - " adds r1, r1, #1 \n" - " str r1, [r0] \n" - " pop { r0-r1 } \n" - " \n" - " /* Start again. */ \n" - " b reg1_loop \n" - " \n" - "reg1_error_loop: \n" - " /* If this line is hit then there was an error in a core register value.\n" - " The loop ensures the loop counter stops incrementing. */\n" - " b reg1_error_loop \n" - " nop " - ); - - /* Remove compiler warnings about unused parameters. */ - ( void ) pvParameters; -} -/*-----------------------------------------------------------*/ - -/* This is a naked function. */ -static void prvRegTest2Task( void *pvParameters ) -{ - __asm volatile - ( - " /* Set all the core registers to known values. */ \n" - " mov r0, #-1 \n" - " mov r1, #1 \n" - " mov r2, #2 \n" - " mov r3, #3 \n" - " mov r4, #4 \n" - " mov r5, #5 \n" - " mov r6, #6 \n" - " mov r7, #7 \n" - " mov r8, #8 \n" - " mov r9, #9 \n" - " mov r10, #10 \n" - " mov r11, #11 \n" - " mov r12, #12 \n" - " \n" - " /* Set all the VFP to known values. */ \n" - " vmov d0, r0, r1 \n" - " vmov d1, r2, r3 \n" - " vmov d2, r4, r5 \n" - " vmov d3, r6, r7 \n" - " vmov d4, r8, r9 \n" - " vmov d5, r10, r11 \n" - " vmov d6, r0, r1 \n" - " vmov d7, r2, r3 \n" - " vmov d8, r4, r5 \n" - " vmov d9, r6, r7 \n" - " vmov d10, r8, r9 \n" - " vmov d11, r10, r11 \n" - " vmov d12, r0, r1 \n" - " vmov d13, r2, r3 \n" - " vmov d14, r4, r5 \n" - " vmov d15, r6, r7 \n" - " \n" - "reg2_loop: \n" - " \n" - " /* Check all the VFP registers still contain the values set above.\n" - " First save registers that are clobbered by the test. */ \n" - " push { r0-r1 } \n" - " \n" - " vmov r0, r1, d0 \n" - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d1 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d2 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d3 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d4 \n" - " cmp r0, #8 \n" - " bne reg2_error_loopf \n" - " cmp r1, #9 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d5 \n" - " cmp r0, #10 \n" - " bne reg2_error_loopf \n" - " cmp r1, #11 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d6 \n" - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d7 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d8 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d9 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d10 \n" - " cmp r0, #8 \n" - " bne reg2_error_loopf \n" - " cmp r1, #9 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d11 \n" - " cmp r0, #10 \n" - " bne reg2_error_loopf \n" - " cmp r1, #11 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d12 \n" - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d13 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d14 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d15 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " \n" - " /* Restore the registers that were clobbered by the test. */\n" - " pop {r0-r1} \n" - " \n" - " /* VFP register test passed. Jump to the core register test. */\n" - " b reg2_loopf_pass \n" - " \n" - "reg2_error_loopf: \n" - " /* If this line is hit then a VFP register value was found to be\n" - " incorrect. */ \n" - " b reg2_error_loopf \n" - " \n" - "reg2_loopf_pass: \n" - " \n" - " cmp r0, #-1 \n" - " bne reg2_error_loop \n" - " cmp r1, #1 \n" - " bne reg2_error_loop \n" - " cmp r2, #2 \n" - " bne reg2_error_loop \n" - " cmp r3, #3 \n" - " bne reg2_error_loop \n" - " cmp r4, #4 \n" - " bne reg2_error_loop \n" - " cmp r5, #5 \n" - " bne reg2_error_loop \n" - " cmp r6, #6 \n" - " bne reg2_error_loop \n" - " cmp r7, #7 \n" - " bne reg2_error_loop \n" - " cmp r8, #8 \n" - " bne reg2_error_loop \n" - " cmp r9, #9 \n" - " bne reg2_error_loop \n" - " cmp r10, #10 \n" - " bne reg2_error_loop \n" - " cmp r11, #11 \n" - " bne reg2_error_loop \n" - " cmp r12, #12 \n" - " bne reg2_error_loop \n" - " \n" - " /* Increment the loop counter to indicate this test is still functioning\n" - " correctly. */ \n" - " push { r0-r1 } \n" - " ldr r0, =ulRegTest2LoopCounter \n" - " ldr r1, [r0] \n" - " adds r1, r1, #1 \n" - " str r1, [r0] \n" - " \n" - " /* Yield to increase test coverage. */ \n" - " movs r0, #0x01 \n" - " ldr r1, =0xe000ed04 \n" /* NVIC_INT_CTRL */ - " lsl r0, #28 \n" /* Shift to PendSV bit */ - " str r0, [r1] \n" - " dsb \n" - " pop { r0-r1 } \n" - " \n" - " /* Start again. */ \n" - " b reg2_loop \n" - " \n" - "reg2_error_loop: \n" - " /* If this line is hit then there was an error in a core register value.\n" - " This loop ensures the loop counter variable stops incrementing. */\n" - " b reg2_error_loop \n" - " nop \n" - ); - - /* Remove compiler warnings about unused parameters. */ - ( void ) pvParameters; -} diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/printf-stdarg.c b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/printf-stdarg.c deleted file mode 100644 index 7062a04e4..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/printf-stdarg.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - Copyright 2001, 2002 Georges Menie (www.menie.org) - stdarg version contributed by Christian Ettinger - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU Lesser General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -/* - putchar is the only external dependency for this file, - if you have a working putchar, leave it commented out. - If not, uncomment the define below and - replace outbyte(c) by your own function call. - -#define putchar(c) outbyte(c) -*/ - -#include - -static void printchar(char **str, int c) -{ - extern int putchar(int c); - - if (str) { - **str = c; - ++(*str); - } - else (void)putchar(c); -} - -#define PAD_RIGHT 1 -#define PAD_ZERO 2 - -static int prints(char **out, const char *string, int width, int pad) -{ - register int pc = 0, padchar = ' '; - - if (width > 0) { - register int len = 0; - register const char *ptr; - for (ptr = string; *ptr; ++ptr) ++len; - if (len >= width) width = 0; - else width -= len; - if (pad & PAD_ZERO) padchar = '0'; - } - if (!(pad & PAD_RIGHT)) { - for ( ; width > 0; --width) { - printchar (out, padchar); - ++pc; - } - } - for ( ; *string ; ++string) { - printchar (out, *string); - ++pc; - } - for ( ; width > 0; --width) { - printchar (out, padchar); - ++pc; - } - - return pc; -} - -/* the following should be enough for 32 bit int */ -#define PRINT_BUF_LEN 12 - -static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase) -{ - char print_buf[PRINT_BUF_LEN]; - register char *s; - register int t, neg = 0, pc = 0; - register unsigned int u = i; - - if (i == 0) { - print_buf[0] = '0'; - print_buf[1] = '\0'; - return prints (out, print_buf, width, pad); - } - - if (sg && b == 10 && i < 0) { - neg = 1; - u = -i; - } - - s = print_buf + PRINT_BUF_LEN-1; - *s = '\0'; - - while (u) { - t = u % b; - if( t >= 10 ) - t += letbase - '0' - 10; - *--s = t + '0'; - u /= b; - } - - if (neg) { - if( width && (pad & PAD_ZERO) ) { - printchar (out, '-'); - ++pc; - --width; - } - else { - *--s = '-'; - } - } - - return pc + prints (out, s, width, pad); -} - -static int print( char **out, const char *format, va_list args ) -{ - register int width, pad; - register int pc = 0; - char scr[2]; - - for (; *format != 0; ++format) { - if (*format == '%') { - ++format; - width = pad = 0; - if (*format == '\0') break; - if (*format == '%') goto out; - if (*format == '-') { - ++format; - pad = PAD_RIGHT; - } - while (*format == '0') { - ++format; - pad |= PAD_ZERO; - } - for ( ; *format >= '0' && *format <= '9'; ++format) { - width *= 10; - width += *format - '0'; - } - if( *format == 's' ) { - register char *s = (char *)va_arg( args, int ); - pc += prints (out, s?s:"(null)", width, pad); - continue; - } - if( *format == 'd' ) { - pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a'); - continue; - } - if( *format == 'x' ) { - pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a'); - continue; - } - if( *format == 'X' ) { - pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A'); - continue; - } - if( *format == 'u' ) { - pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a'); - continue; - } - if( *format == 'c' ) { - /* char are converted to int then pushed on the stack */ - scr[0] = (char)va_arg( args, int ); - scr[1] = '\0'; - pc += prints (out, scr, width, pad); - continue; - } - } - else { - out: - printchar (out, *format); - ++pc; - } - } - if (out) **out = '\0'; - va_end( args ); - return pc; -} - -int printf(const char *format, ...) -{ - va_list args; - - va_start( args, format ); - return print( 0, format, args ); -} - -int sprintf(char *out, const char *format, ...) -{ - va_list args; - - va_start( args, format ); - return print( &out, format, args ); -} - - -int snprintf( char *buf, unsigned int count, const char *format, ... ) -{ - va_list args; - - ( void ) count; - - va_start( args, format ); - return print( &buf, format, args ); -} - - -#ifdef TEST_PRINTF -int main(void) -{ - char *ptr = "Hello world!"; - char *np = 0; - int i = 5; - unsigned int bs = sizeof(int)*8; - int mi; - char buf[80]; - - mi = (1 << (bs-1)) + 1; - printf("%s\n", ptr); - printf("printf test\n"); - printf("%s is null pointer\n", np); - printf("%d = 5\n", i); - printf("%d = - max int\n", mi); - printf("char %c = 'a'\n", 'a'); - printf("hex %x = ff\n", 0xff); - printf("hex %02x = 00\n", 0); - printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3); - printf("%d %s(s)%", 0, "message"); - printf("\n"); - printf("%d %s(s) with %%\n", 0, "message"); - sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf); - sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf); - sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf); - sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf); - sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf); - sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf); - sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf); - sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf); - - return 0; -} - -/* - * if you compile this file with - * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c - * you will get a normal warning: - * printf.c:214: warning: spurious trailing `%' in format - * this line is testing an invalid % at the end of the format string. - * - * this should display (on 32bit int machine) : - * - * Hello world! - * printf test - * (null) is null pointer - * 5 = 5 - * -2147483647 = - max int - * char a = 'a' - * hex ff = ff - * hex 00 = 00 - * signed -3 = unsigned 4294967293 = hex fffffffd - * 0 message(s) - * 0 message(s) with % - * justif: "left " - * justif: " right" - * 3: 0003 zero padded - * 3: 3 left justif. - * 3: 3 right justif. - * -3: -003 zero padded - * -3: -3 left justif. - * -3: -3 right justif. - */ - -#endif - -