From: Peng Fan <peng.fan@nxp.com>
Date: Mon, 12 Jun 2017 09:50:53 +0000 (+0800)
Subject: mmc: fsl_esdhc: introduce vs18_enable for 1.8V fix I/O
X-Git-Tag: v2017.09-rc1~190^2~14
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=32a9179f3adf6b36d85601ff6eba251dc6d207f9;p=u-boot

mmc: fsl_esdhc: introduce vs18_enable for 1.8V fix I/O

When using eMMC with 1.8V I/O, the VSELECT bit need to be set in
the USDHC controller when init.

This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg
structure and priv data, so each controller can have different
settings.

We could not use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT, it has problem
that it will apply to all USDHC controllers and it only set the 1.8V
at init phase. So if user does not select to the eMMC device,
the voltage on the I/O pins are not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 73748c5658..74a0017842 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -92,6 +92,7 @@ struct fsl_esdhc {
  * @dev: pointer for the device
  * @non_removable: 0: removable; 1: non-removable
  * @wp_enable: 1: enable checking wp; 0: no check
+ * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
  * @cd_gpio: gpio for card detection
  * @wp_gpio: gpio for write protection
  */
@@ -104,6 +105,7 @@ struct fsl_esdhc_priv {
 	struct udevice *dev;
 	int non_removable;
 	int wp_enable;
+	int vs18_enable;
 #ifdef CONFIG_DM_GPIO
 	struct gpio_desc cd_gpio;
 	struct gpio_desc wp_gpio;
@@ -674,6 +676,9 @@ static int esdhc_init(struct mmc *mmc)
 	esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 #endif
 
+	if (priv->vs18_enable)
+		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
 	return 0;
 }
 
@@ -746,6 +751,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
 			VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
 #endif
 
+	if (priv->vs18_enable)
+		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
 	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 	memset(&priv->cfg, 0, sizeof(priv->cfg));
 
@@ -831,6 +839,7 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
 	priv->bus_width = cfg->max_bus_width;
 	priv->sdhc_clk = cfg->sdhc_clk;
 	priv->wp_enable  = cfg->wp_enable;
+	priv->vs18_enable  = cfg->vs18_enable;
 
 	return 0;
 };
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 5550e00eab..02b362d5e3 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -178,6 +178,7 @@ struct fsl_esdhc_cfg {
 	u32	sdhc_clk;
 	u8	max_bus_width;
 	int	wp_enable;
+	int	vs18_enable; /* Use 1.8V if set to 1 */
 	struct mmc_config cfg;
 };