From: Mark Jonas Date: Mon, 10 Mar 2008 10:37:10 +0000 (+0100) Subject: sh: Added support for SH7720 based board MPR2. X-Git-Tag: v1.3.3-rc1~116^2~9 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3313e0e26224fc9a0c445124f3455058c696df84;p=u-boot sh: Added support for SH7720 based board MPR2. Signed-off-by: Mark Jonas Signed-off-by: Nobuhiro Iwamatsu --- diff --git a/CREDITS b/CREDITS index 1627dc7f0a..26d5f51b99 100644 --- a/CREDITS +++ b/CREDITS @@ -236,6 +236,10 @@ E: mark.jonas@freescale.com D: Support for Freescale Total5200 platform W: http://www.mobilegt.com/ +N: Mark Jonas +E: mark.jonas@de.bosch.com +D: Support for MPR2 board + N: Sam Song E: samsongshu@yahoo.com.cn D: Port to the RPXlite_DW board diff --git a/MAINTAINERS b/MAINTAINERS index 6fc1e60b4e..5471c1d1a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -699,6 +699,10 @@ Nobuhiro Iwmaatsu MS7750SE SH7750 MS7722SE SH7722 +Mark Jonas + + mpr2 SH7720 + Yoshihiro Shimoda MS7720SE SH7720 diff --git a/MAKEALL b/MAKEALL index f65351abad..ea02a8aa52 100755 --- a/MAKEALL +++ b/MAKEALL @@ -704,6 +704,7 @@ LIST_sh4=" \ " LIST_sh3=" \ + mpr2 \ ms7720se \ " diff --git a/Makefile b/Makefile index 948108b4c2..f9850455e4 100644 --- a/Makefile +++ b/Makefile @@ -2837,6 +2837,11 @@ atngw100_config : unconfig ######################################################################### ## sh3 (Renesas SuperH) ######################################################################### +mpr2_config: unconfig + @ >include/config.h + @echo "#define CONFIG_MPR2 1" >> include/config.h + @$(MKCONFIG) -a $(@:_config=) sh sh3 mpr2 + ms7720se_config: unconfig @echo "#define CONFIG_MS7720SE 1" > include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile new file mode 100644 index 0000000000..17ca17ec5b --- /dev/null +++ b/board/mpr2/Makefile @@ -0,0 +1,54 @@ +# +# Copyright (C) 2007 +# Yoshihiro Shimoda +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# (C) Copyright 2008 +# Mark Jonas +# +# board/mpr2/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := mpr2.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpr2/config.mk b/board/mpr2/config.mk new file mode 100644 index 0000000000..6d41d97cb7 --- /dev/null +++ b/board/mpr2/config.mk @@ -0,0 +1,37 @@ +# +# Copyright (C) 2007 +# Yoshihiro Shimoda +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# Copyright (C) 2008 +# Mark Jonas +# +# board/mpr2/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S new file mode 100644 index 0000000000..060957ad06 --- /dev/null +++ b/board/mpr2/lowlevel_init.S @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2008 + * Mark Jonas + * + * (C) Copyright 2007 + * Yoshihiro Shimoda + * + * board/mpr2/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + +/* + * Set frequency multipliers and dividers in FRQCR. + */ + mov.l WTCSR_A,r1 + mov.l WTCSR_D,r0 + mov.w r0,@r1 + + mov.l WTCNT_A,r1 + mov.l WTCNT_D,r0 + mov.w r0,@r1 + + mov.l FRQCR_A,r1 + mov.l FRQCR_D,r0 + mov.w r0,@r1 + +/* + * Setup CS0 (Flash). + */ + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 + mov.l r0, @r1 + + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 + +/* + * Setup CS3 (SDRAM). + */ + mov.l CS3BCR_A, r1 + mov.l CS3BCR_D, r0 + mov.l r0, @r1 + + mov.l CS3WCR_A, r1 + mov.l CS3WCR_D, r0 + mov.l r0, @r1 + + mov.l SDCR_A, r1 + mov.l SDCR_D1, r0 + mov.l r0, @r1 + + mov.l RTCSR_A, r1 + mov.l RTCSR_D, r0 + mov.l r0, @r1 + + mov.l RTCNT_A, r1 + mov.l RTCNT_D, r0 + mov.l r0, @r1 + + mov.l RTCOR_A, r1 + mov.l RTCOR_D, r0 + mov.l r0, @r1 + + mov.l SDCR_A, r1 + mov.l SDCR_D2, r0 + mov.l r0, @r1 + + mov.l SDMR3_A, r1 + mov.l SDMR3_D, r0 + add r0, r1 + mov #0, r0 + mov.w r0, @r1 + + rts + nop + + .align 4 + +/* + * Configuration for MPR2 A.3 through A.7 + */ + +/* + * PLL Settings + */ +FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .long 0x5A00 /* start counting at zero */ +WTCSR_D: .long 0xA507 /* divide by 4096 */ + +/* + * Spansion S29GL256N11 @ 48 MHz + */ +CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */ +CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ + +/* + * Samsung K4S511632B-UL75 @ 48 MHz + * Micron MT48LC32M16A2-75 @ 48 MHz + */ +CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ +CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ +SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */ +SDCR_D2: .long 0x00000812 /* refresh */ +RTCSR_D: .long 0xA55A0008 /* 1/4, once */ +RTCNT_D: .long 0xA55A005D /* count 93 */ +RTCOR_D: .long 0xa55a005d /* count 93 */ +SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */ + +/* + * Registers + */ + +FRQCR_A: .long 0xA415FF80 +WTCNT_A: .long 0xA415FF84 +WTCSR_A: .long 0xA415FF86 + +#define BSC_BASE 0xA4FD0000 +CS0BCR_A: .long BSC_BASE + 0x04 +CS3BCR_A: .long BSC_BASE + 0x0C +CS0WCR_A: .long BSC_BASE + 0x24 +CS3WCR_A: .long BSC_BASE + 0x2C +SDCR_A: .long BSC_BASE + 0x44 +RTCSR_A: .long BSC_BASE + 0x48 +RTCNT_A: .long BSC_BASE + 0x4C +RTCOR_A: .long BSC_BASE + 0x50 +SDMR3_A: .long BSC_BASE + 0x5000 diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c new file mode 100644 index 0000000000..2ddb0c10c1 --- /dev/null +++ b/board/mpr2/mpr2.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2008 + * Mark Jonas + * + * board/mpr2/mpr2.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int checkboard(void) +{ + puts("BOARD: MPR2\n"); + return 0; +} + +int board_init(void) +{ + /* + * For MPR2 A.3 through A.7 + */ + + /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */ + __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */ + __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */ + + /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */ + __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + + /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */ + __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + + /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */ + __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + + /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */ + __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ + + /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */ + __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */ + + /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */ + __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */ + + /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */ + __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */ + + /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */ + __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */ + + /* OTH: (00) Other fuction + * GPO: (01) General Purpose Output + * GPI: (11) General Purpose Input + * GPI+: (10) General Purpose Input with internal pull-up + *------------------------------------------------------- + * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); + * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */ + __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */ + + /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); + * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */ + __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */ + + /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); + * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */ + __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */ + + /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); + * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */ + __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */ + + /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; + * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */ + __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */ + + /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; + * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */ + __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */ + + /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2); + * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */ + __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */ + + /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); + * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */ + __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */ + + /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; + * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */ + __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */ + + /* K7 (x); K6 (x); K5 (x); K4 (x) + * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */ + __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */ + + /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; + * L3 TCK; L2 (x); L1 (x); L0 (x); */ + __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */ + + /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET); + * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */ + __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */ + __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */ + + /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup); + * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */ + __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */ + __raw_writeb(0x10, PPDR); /* no current flow through pullup */ + + /* R7 A25; R6 A24; R5 A23; R4 A22; + * R3 A21; R2 A20; R1 A19; R0 A0; */ + __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */ + + /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); + * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */ + __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */ + + /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; + * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */ + __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */ + + /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); + * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */ + __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */ + + /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); + * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */ + __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */ + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + diff --git a/board/mpr2/u-boot.lds b/board/mpr2/u-boot.lds new file mode 100644 index 0000000000..6fee7f2542 --- /dev/null +++ b/board/mpr2/u-boot.lds @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2007 + * Yoshihiro Shimoda + * + * Copyright (C) 2007 + * Nobuhiro Iwamatsu + * + * Copyright (C) 2008 + * Mark Jonas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x8C000000. + U-Boot resides in the last 256 kB of the 64 MB. + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh3/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/include/asm-sh/cpu_sh7720.h b/include/asm-sh/cpu_sh7720.h index bafb8deb19..1b393b88a6 100644 --- a/include/asm-sh/cpu_sh7720.h +++ b/include/asm-sh/cpu_sh7720.h @@ -1,5 +1,9 @@ /* - * (C) Copyright 2007 Yoshihiro Shimoda + * Copyright 2007 (C) + * Yoshihiro Shimoda + * + * Copyright 2008 (C) + * Mark Jonas * * SH7720 Internal I/O register * @@ -201,6 +205,25 @@ #define PSELD (PFC_BASE + 0x2A) /* I/O Port */ +#define PORT_BASE 0xA4050100 +#define PADR (PORT_BASE + 0x40) +#define PBDR (PORT_BASE + 0x42) +#define PCDR (PORT_BASE + 0x44) +#define PDDR (PORT_BASE + 0x46) +#define PEDR (PORT_BASE + 0x48) +#define PFDR (PORT_BASE + 0x4A) +#define PGDR (PORT_BASE + 0x4C) +#define PHDR (PORT_BASE + 0x4E) +#define PJDR (PORT_BASE + 0x50) +#define PKDR (PORT_BASE + 0x52) +#define PLDR (PORT_BASE + 0x54) +#define PMDR (PORT_BASE + 0x56) +#define PPDR (PORT_BASE + 0x58) +#define PRDR (PORT_BASE + 0x5A) +#define PSDR (PORT_BASE + 0x5C) +#define PTDR (PORT_BASE + 0x5E) +#define PUDR (PORT_BASE + 0x60) +#define PVDR (PORT_BASE + 0x62) /* H-UDI */ diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h new file mode 100644 index 0000000000..0fc0b970db --- /dev/null +++ b/include/configs/mpr2.h @@ -0,0 +1,92 @@ +/* + * Configuation settings for MPR2 + * + * Copyright (C) 2008 + * Mark Jonas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MPR2_H +#define __MPR2_H + +/* Supported commands */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_FLASH + +/* Default environment variables */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "console=ttySC0,115200" +#define CONFIG_BOOTFILE /boot/zImage +#define CONFIG_LOADADDR 0x8E000000 +#define CONFIG_VERSION_VARIABLE + +/* CPU and platform */ +#define CONFIG_SH 1 +#define CONFIG_SH3 1 +#define CONFIG_CPU_SH7720 1 +#define CONFIG_MPR2 1 + +/* U-Boot internals */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ +#define CFG_PBSIZE 256 /* Buffer size for Console output */ +#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ +#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ +#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_GBL_DATA_SIZE 256 + +/* Memory */ +#define CFG_SDRAM_BASE 0x8C000000 +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) + +/* Flash */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_BASE 0xA0000000 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE (128 * 1024) +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_WRITE_TOUT 500 + +/* Clocks */ +#define CONFIG_SYS_CLK_FREQ 24000000 +#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +/* UART */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF0 1 + +#endif /* __MPR2_H */