From: Stefan Roese <sr@denx.de>
Date: Fri, 31 Mar 2006 13:18:37 +0000 (+0200)
Subject: Reorder CHANGELOG
X-Git-Tag: LABEL_2006_04_18_1106~9^2
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=35118539435d1a6f40eab348a4ac2040f3bd882c;p=u-boot

Reorder CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index 16b50e96f9..c8d4e42067 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,24 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
+
+  405 SDRAM: - The SDRAM parameters can now be defined in the board
+               config file and the 405 SDRAM controller values will
+               be calculated upon bootup (see PPChameleonEVB).
+               When those settings are not defined in the board
+               config file, the register setup will be as it is now,
+               so this implementation should not break any current
+               design using this code.
+
+               Thanks to Andrea Marson from DAVE for this patch.
+
+  440 DDR:   - Added function sdram_tr1_set to auto calculate the
+               TR1 value for the DDR.
+             - Added ECC support (see p3p440).
+
+  Patch by Stefan Roese, 17 Mar 2006
+
 * Enable Quad UART om MCC200 board.
 
 * Cleanup MCC200 board configuration; omit non-existent stuff.
@@ -33,24 +51,6 @@ Changes since U-Boot 1.1.4:
 * Add support for Lite5200B board.
   Patch by  Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
 
-* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
-
-  405 SDRAM: - The SDRAM parameters can now be defined in the board
-               config file and the 405 SDRAM controller values will
-               be calculated upon bootup (see PPChameleonEVB).
-               When those settings are not defined in the board
-               config file, the register setup will be as it is now,
-               so this implementation should not break any current
-               design using this code.
-
-               Thanks to Andrea Marson from DAVE for this patch.
-
-  440 DDR:   - Added function sdram_tr1_set to auto calculate the
-               TR1 value for the DDR.
-             - Added ECC support (see p3p440).
-
-  Patch by Stefan Roese, 17 Mar 2006
-
 * Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
   timer and cpu_reset code from cpu/$(CPU) into the new
   cpu/$(CPU)/$(SOC) directories