From: Marek Vasut Date: Sun, 19 Jul 2015 05:03:15 +0000 (+0200) Subject: ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3 X-Git-Tag: v2015.10-rc2~255 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=37b7b13d4818ca3941dc5f8217ff0fa8d60ce501;p=u-boot ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3 Clean up odd multiline loop, no functional change. Signed-off-by: Marek Vasut --- diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 16d09c1264..3d975f99fb 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -1633,8 +1633,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp) } /* The dtap increment to find the failing edge is done here. */ - for (; d <= IO_DQS_EN_DELAY_MAX; - d++, work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) { + for (; d <= IO_DQS_EN_DELAY_MAX; d++) { debug_cond(DLEVEL == 2, "%s:%d end-2: dtap=%u\n", __func__, __LINE__, d); @@ -1645,6 +1644,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp) &bit_chk, 0)) { break; } + + work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP; } /* Go back to working dtap */