From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue, 24 Apr 2007 12:03:45 +0000 (+0200)
Subject: ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.
X-Git-Tag: v1.3.0-rc1~88^2~4^2
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=37ed6cdd4159195bfad68d8a237f6adda8f482cb;p=u-boot

ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index cf56581d84..be4e82405e 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -339,29 +339,41 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 {
 	unsigned long zmiifer=0x0;
+	unsigned long pfc1;
 
-	/*
-	 * Right now only 2*RGMII is supported. Please extend when needed.
-	 * sr - 2006-08-29
-	 */
-	switch (1) {
-	case 0:
+	mfsdr(sdr_pfc1, pfc1);
+	pfc1 &= SDR0_PFC1_SELECT_MASK;
+
+	switch (pfc1) { 
+	case SDR0_PFC1_SELECT_CONFIG_2:
 		/* 1 x GMII port */
 		out32 (ZMII_FER, 0x00);
 		out32 (RGMII_FER, 0x00000037);
 		bis->bi_phymode[0] = BI_PHYMODE_GMII;
 		bis->bi_phymode[1] = BI_PHYMODE_NONE;
 		break;
-	case 1:
+	case SDR0_PFC1_SELECT_CONFIG_4:
 		/* 2 x RGMII ports */
 		out32 (ZMII_FER, 0x00);
 		out32 (RGMII_FER, 0x00000055);
 		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
 		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
 		break;
-	case 2:
+	case SDR0_PFC1_SELECT_CONFIG_6:
 		/* 2 x SMII ports */
-
+		out32 (ZMII_FER, 
+		       ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
+		       ((ZMII_FER_SMII) << ZMII_FER_V(1)));
+		out32 (RGMII_FER, 0x00000000);
+		bis->bi_phymode[0] = BI_PHYMODE_SMII;
+		bis->bi_phymode[1] = BI_PHYMODE_SMII;
+		break;
+	case SDR0_PFC1_SELECT_CONFIG_1_2:
+		/* only 1 x MII supported */
+		out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+		out32 (RGMII_FER, 0x00000000);
+		bis->bi_phymode[0] = BI_PHYMODE_MII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
 		break;
 	default:
 		break;