From: Ying Zhang <b40530@freescale.com>
Date: Fri, 16 Aug 2013 07:16:14 +0000 (+0800)
Subject: powerpc : p1022ds : Enable p1022ds to start from eSPI with SPL
X-Git-Tag: v2013.10-rc2~9^2~13
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=382ce7e909c09ba28da5763e717efac7a2c4d156;p=u-boot

powerpc : p1022ds : Enable p1022ds to start from eSPI with SPL

Enable p1022ds to start from eSPI with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
---

diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 71a0f85aff..7e89de2b11 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -27,6 +27,7 @@
 #include <i2c.h>
 #include "../common/ngpixis.h"
 #include <fsl_esdhc.h>
+#include <spi_flash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -53,6 +54,11 @@ void board_init_f(ulong bootflag)
 	setbits_be32(&gur->pmuxcr,
 		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
 
+#ifdef CONFIG_SPL_SPI_BOOT
+	/* Enable the SPI */
+	clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+#endif
+
 	/* Read back the register to synchronize the write. */
 	in_be32(&gur->pmuxcr);
 
@@ -66,6 +72,8 @@ void board_init_f(ulong bootflag)
 		     bus_clk / 16 / CONFIG_BAUDRATE);
 #ifdef CONFIG_SPL_MMC_BOOT
 	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
 #endif
 
 	/* copy code to RAM and jump to it - this should not return */
@@ -106,5 +114,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
 #endif
 }
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 6db0c2700b..762b136cd0 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -45,11 +45,33 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x18000
+#define CONFIG_SPL_MAX_SIZE		(96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #define CONFIG_NAND_FSL_ELBC
@@ -315,7 +337,7 @@
  * Config the L2 Cache as L2 SRAM
 */
 #if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
@@ -559,7 +581,7 @@
 /*
  * Environment
  */
-#ifdef CONFIG_RAMBOOT_SPIFLASH
+#ifdef CONFIG_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0