From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 22 Aug 2006 22:55:45 +0000 (-0500)
Subject: Merge branch 'mpc86xx'
X-Git-Tag: U-Boot-1_1_6~20^2~3^2~33
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=38546f08c608b871a65bd538b9c460b3348b1261;p=u-boot

Merge branch 'mpc86xx'
---

38546f08c608b871a65bd538b9c460b3348b1261
diff --cc include/asm-ppc/mmu.h
index 11de3b0879,4f49789f63..5c38ce1e78
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@@ -478,50 -478,9 +478,50 @@@ extern int write_bat(ppc_bat_t bat, uns
  #define LAWAR_SIZE_512M		(LAWAR_SIZE_BASE+18)
  #define LAWAR_SIZE_1G		(LAWAR_SIZE_BASE+19)
  #define LAWAR_SIZE_2G		(LAWAR_SIZE_BASE+20)
- #define LAWAR_SIZE_4G          (LAWAR_SIZE_BASE+21)
- #define LAWAR_SIZE_8G          (LAWAR_SIZE_BASE+22)
- #define LAWAR_SIZE_16G         (LAWAR_SIZE_BASE+23)
- #define LAWAR_SIZE_32G         (LAWAR_SIZE_BASE+24)
+ #define LAWAR_SIZE_4G		(LAWAR_SIZE_BASE+21)
+ #define LAWAR_SIZE_8G		(LAWAR_SIZE_BASE+22)
+ #define LAWAR_SIZE_16G		(LAWAR_SIZE_BASE+23)
+ #define LAWAR_SIZE_32G		(LAWAR_SIZE_BASE+24)
  
 +#ifdef CONFIG_440SPE
 +/*----------------------------------------------------------------------------+
 +| Following instructions are not available in Book E mode of the GNU assembler.
 ++----------------------------------------------------------------------------*/
 +#define DCCCI(ra,rb)			.long 0x7c000000|\
 +					(ra<<16)|(rb<<11)|(454<<1)
 +
 +#define ICCCI(ra,rb)			.long 0x7c000000|\
 +					(ra<<16)|(rb<<11)|(966<<1)
 +
 +#define DCREAD(rt,ra,rb)		.long 0x7c000000|\
 +					(rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
 +
 +#define ICREAD(ra,rb)			.long 0x7c000000|\
 +					(ra<<16)|(rb<<11)|(998<<1)
 +
 +#define TLBSX(rt,ra,rb)			.long 0x7c000000|\
 +					(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
 +
 +#define TLBWE(rs,ra,ws)			.long 0x7c000000|\
 +					(rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
 +
 +#define TLBRE(rt,ra,ws)			.long 0x7c000000|\
 +					(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
 +
 +#define TLBSXDOT(rt,ra,rb)		.long 0x7c000001|\
 +					(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
 +
 +#define MSYNC				.long 0x7c000000|\
 +					(598<<1)
 +
 +#define MBAR_INST 				.long 0x7c000000|\
 +					(854<<1)
 +
 +/*----------------------------------------------------------------------------+
 +| Following instruction is not available in PPC405 mode of the GNU assembler.
 ++----------------------------------------------------------------------------*/
 +#define TLBRE(rt,ra,ws)			.long 0x7c000000|\
 +					(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
 +
 +#endif
  #endif /* _PPC_MMU_H_ */