From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 8 May 2013 13:37:28 +0000 (+0200)
Subject: zynq: slcr: Wait 100ms till clk is properly setup
X-Git-Tag: v2013.10-rc3~8^2~8^2~1
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=39523bef29f71967247ca00fe4b2c7e0831bb8a2;p=u-boot

zynq: slcr: Wait 100ms till clk is properly setup

If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index e5fe992982..717ec65aee 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -70,7 +70,7 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
 		/* Configure GEM_RCLK_CTRL */
 		writel(rclk, &slcr_base->gem0_rclk_ctrl);
 	}
-
+	udelay(100000);
 out:
 	zynq_slcr_lock();
 }