From: Kever Yang <kever.yang@rock-chips.com>
Date: Wed, 28 Dec 2016 03:32:35 +0000 (+0800)
Subject: mmc: rockchip_sdhci: add clock init for mmc
X-Git-Tag: v2017.03-rc1~136^2~15
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=39fbb56f845431686966a90456bd232f0b355dbd;p=u-boot

mmc: rockchip_sdhci: add clock init for mmc

Init the clock rate to max-frequency from dts with clock driver api.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
---

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index c56e1a3a1c..e33e35e4fa 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -12,7 +12,9 @@
 #include <libfdt.h>
 #include <malloc.h>
 #include <sdhci.h>
+#include <clk.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 /* 400KHz is max freq for card ID etc. Use that as min */
 #define EMMC_MIN_FREQ	400000
 
@@ -32,11 +34,24 @@ static int arasan_sdhci_probe(struct udevice *dev)
 	struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
 	struct rockchip_sdhc *prv = dev_get_priv(dev);
 	struct sdhci_host *host = &prv->host;
-	int ret;
+	int max_frequency, ret;
+	struct clk clk;
+
+
+	max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+			"max-frequency", 0);
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (!ret) {
+		ret = clk_set_rate(&clk, max_frequency);
+		if (IS_ERR_VALUE(ret))
+			printf("%s clk set rate fail!\n", __func__);
+	} else {
+		printf("%s fail to get clk\n", __func__);
+	}
 
 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
 
-	ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ,
+	ret = sdhci_setup_cfg(&plat->cfg, host, max_frequency,
 			EMMC_MIN_FREQ);
 
 	host->mmc = &plat->mmc;