From: Simon Glass <sjg@chromium.org>
Date: Sun, 13 Nov 2016 21:22:13 +0000 (-0700)
Subject: rockchip: clk: Support setting ACLK
X-Git-Tag: v2017.01-rc1~210^2~5
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3a8a42d9550cf6779495037ce19c5357eed5ff88;p=u-boot

rockchip: clk: Support setting ACLK

Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index ed97e87a95..d15504c3aa 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -691,6 +691,13 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 
 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 	switch (clk->id) {
+	case PLL_APLL:
+		/* We only support a fixed rate here */
+		if (rate != 1800000000)
+			return -EINVAL;
+		rk3288_clk_configure_cpu(priv->cru, priv->grf);
+		new_rate = rate;
+		break;
 	case CLK_DDR:
 		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
 		break;