From: Tom Rini <trini@konsulko.com>
Date: Fri, 11 May 2018 15:45:28 +0000 (-0400)
Subject: Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
X-Git-Tag: v2018.07-rc1~159
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3b52847a451a81001b578353e793d7d9739b69d6;p=u-boot

Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup
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3b52847a451a81001b578353e793d7d9739b69d6