From: Penda Naveen Kumar Date: Thu, 30 Jul 2009 18:36:36 +0000 (+0530) Subject: omap3: bug fix for NOR boot support X-Git-Tag: v2009.08-rc2~23 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3b9043a7c03290c9bdbef03848307263f5f3472c;p=u-boot omap3: bug fix for NOR boot support This patch provides bug fix, when omap3 uses nor boot. Signed-off-by: Penda Naveen Kumar Acked-by: Dirk Behme --- diff --git a/cpu/arm_cortexa8/omap3/lowlevel_init.S b/cpu/arm_cortexa8/omap3/lowlevel_init.S index cf1f927cff..73063ec8e6 100644 --- a/cpu/arm_cortexa8/omap3/lowlevel_init.S +++ b/cpu/arm_cortexa8/omap3/lowlevel_init.S @@ -135,19 +135,19 @@ _go_to_speed: .word go_to_speed /* these constants need to be close for PIC code */ /* The Nor has to be in the Flash Base CS0 for this condition to happen */ flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1) flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3) flash_cfg3_val: .word STNOR_GPMC_CONFIG3 flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4) flash_cfg4_val: .word STNOR_GPMC_CONFIG4 flash_cfg5_val: .word STNOR_GPMC_CONFIG5 flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5) pll_ctl_add: .word CM_CLKEN_PLL pll_div_add1: