From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Wed, 20 May 2009 16:30:41 +0000 (-0400)
Subject: 85xx: Add UEC6 and UEC8 at SGMII mode for MPC8569MDS
X-Git-Tag: v2009.08-rc1~153^2~6
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3bd8e532b5de20647aeaff94a1cbf33fb8b897b9;p=u-boot

85xx: Add UEC6 and UEC8 at SGMII mode for MPC8569MDS

On MPC8569MDS board, UCC6 and UCC8 can be configured to work at SGMII mode via
UEM on PB board. Since MPC8569 supports up to 4 Gigabit Ethernet ports, we
disable UEC6 and UEC8 by default.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index c97ea2fdcc..27044f7bb1 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -365,6 +365,31 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH4 */
+
+#undef CONFIG_UEC_ETH6         /* GETH6 */
+#define CONFIG_HAS_ETH5
+
+#ifdef CONFIG_UEC_ETH6
+#define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
+#define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC6_PHY_ADDR       4
+#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
+#endif /* CONFIG_UEC_ETH6 */
+
+#undef CONFIG_UEC_ETH8         /* GETH8 */
+#define CONFIG_HAS_ETH7
+
+#ifdef CONFIG_UEC_ETH8
+#define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
+#define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC8_PHY_ADDR       6
+#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
+#endif /* CONFIG_UEC_ETH8 */
+
 #endif /* CONFIG_QE */
 
 #if defined(CONFIG_PCI)