From: Kim Phillips Date: Fri, 5 Jun 2009 19:11:33 +0000 (-0500) Subject: mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI operation X-Git-Tag: v2009.06~9^2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3c9b1ee17e19bd6d80344678d41a85e52b0be713;p=u-boot mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI operation In GMII mode (which operates at 3.3V) both SICRH TSEC1/2 output buffer impedance bits should be clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0. SICRH[TSIOB1] was erroneously being set high. U-Boot always operated this PHY interface in GMII mode. It is assumed this was missed in the clean up by the original board porters, and copied along to the TQM and sbc boards. Signed-off-by: Kim Phillips Acked-by: Ira Snyder Reviewed-by: David Hawkins Tested-by: Paul Gortmaker CC: Dave Liu --- diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3c574039f3..2d2799e111 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -598,7 +598,7 @@ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ /* System IO Config */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 +#define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 5ca8720a32..551073025f 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -393,7 +393,7 @@ extern int tqm834x_num_flash_banks; #endif /* System IO Config */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 +#define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A /* i-cache and d-cache disabled */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index d0338f168b..edd928d81b 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -519,7 +519,7 @@ #endif /* System IO Config */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 +#define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000