From: York Sun Date: Thu, 26 Jun 2014 18:14:44 +0000 (-0700) Subject: driver/ddr: Fix DDR register timing_cfg_8 X-Git-Tag: v2014.10-rc1~40^2~5 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3d75ec95f57224995210db5c5dea8d458cf862fb;p=u-boot driver/ddr: Fix DDR register timing_cfg_8 The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun --- diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index dcf6287f66..04e4178b15 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); wrtord_bg = max(4, picos_to_mclk(7500)); + if (popts->otf_burst_chop_en) + wrtord_bg += 2; + pre_all_rec = 0; ddr->timing_cfg_8 = (0