From: Spencer Oliver <ntfreak@users.sourceforge.net>
Date: Wed, 22 Dec 2010 17:20:11 +0000 (+0000)
Subject: stm32: add stm32 xl family flash support
X-Git-Tag: v0.5.0-rc1~260
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3d834bdab782065ba736328d6f7f19ded8ba975a;p=openocd

stm32: add stm32 xl family flash support

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
---

diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index 8aae2036..6393aa40 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -905,6 +905,34 @@ static int stm32x_probe(struct flash_bank *bank)
 			num_pages = 128;
 		}
 	}
+	else if ((device_id & 0x7ff) == 0x430)
+	{
+		/* xl line density - we have 2k pages
+		 * 2 pages for a protection area */
+		page_size = 2048;
+		stm32x_info->ppage_size = 2;
+
+		/* check for early silicon */
+		if (num_pages == 0xffff)
+		{
+			/* number of sectors may be incorrrect on early silicon */
+			LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
+			num_pages = 1024;
+		}
+
+		/* split reported size into matching bank */
+		if (bank->base != 0x08080000)
+		{
+			/* bank 0 will be fixed 512k */
+			num_pages = 512;
+		}
+		else
+		{
+			num_pages -= 512;
+			/* bank1 also uses a register offset */
+			stm32x_info->register_offset = 0x40;
+		}
+	}
 	else
 	{
 		LOG_WARNING("Cannot identify target as a STM32 family.");
@@ -922,7 +950,6 @@ static int stm32x_probe(struct flash_bank *bank)
 		bank->sectors = NULL;
 	}
 
-	bank->base = 0x08000000;
 	bank->size = (num_pages * page_size);
 	bank->num_sectors = num_pages;
 	bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
@@ -1075,6 +1102,23 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
 				break;
 		}
 	}
+	else if ((device_id & 0x7ff) == 0x430)
+	{
+		printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
+		buf += printed;
+		buf_size -= printed;
+
+		switch (device_id >> 16)
+		{
+			case 0x1000:
+				snprintf(buf, buf_size, "A");
+				break;
+
+			default:
+				snprintf(buf, buf_size, "unknown");
+				break;
+		}
+	}
 	else
 	{
 		snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
diff --git a/tcl/target/stm32.cfg b/tcl/target/stm32.cfg
index 86e6ebb8..eef12699 100644
--- a/tcl/target/stm32.cfg
+++ b/tcl/target/stm32.cfg
@@ -52,18 +52,22 @@ if { [info exists BSTAPID ] } {
   set _BSTAPID4 0x06414041
   # Connectivity line devices, Rev A and Rev Z
   set _BSTAPID5 0x06418041
+  # XL line devices, Rev A
+  set _BSTAPID6 0x06430041
 }
 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
 	-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
-	-expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+	-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
+	-expected-id $_BSTAPID6
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
+# flash size will be probed
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32x 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
diff --git a/tcl/target/stm32xl.cfg b/tcl/target/stm32xl.cfg
new file mode 100644
index 00000000..cde07df2
--- /dev/null
+++ b/tcl/target/stm32xl.cfg
@@ -0,0 +1,6 @@
+# script for stm32xl family (dual flash bank)
+source [find target/stm32.cfg]
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32x 0x08080000 0 0 0 $_TARGETNAME