From: Tom Rini Date: Thu, 15 Mar 2018 12:27:27 +0000 (-0400) Subject: Merge git://git.denx.de/u-boot-spi X-Git-Tag: v2018.05-rc1~91 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=3fa9bc7969c130b373f41731db526a3511f40ea5;hp=706f077577cafaa21e6dcf93797d3a0e7dc82444;p=u-boot Merge git://git.denx.de/u-boot-spi --- diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 1fededd0a3..dc48eefdef 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -847,4 +847,12 @@ config SPL_STACK_R_ADDR default 0x2fe00000 if MACH_SUN9I default 0x4fe00000 if MACH_SUN50I +config SPL_SPI_SUNXI + bool "Support for SPI Flash on Allwinner SoCs in SPL" + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + help + Enable support for SPI Flash. This option allows SPL to read from + sunxi SPI Flash. It uses the same method as the boot ROM, so does + not need any extra configuration. + endif diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 2a3c379b72..6ddf682764 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o +obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c new file mode 100644 index 0000000000..fa22981316 --- /dev/null +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -0,0 +1,312 @@ +/* + * Copyright (C) 2016 Siarhei Siamashka + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_OS_BOOT +#error CONFIG_SPL_OS_BOOT is not supported yet +#endif + +/* + * This is a very simple U-Boot image loading implementation, trying to + * replicate what the boot ROM is doing when loading the SPL. Because we + * know the exact pins where the SPI Flash is connected and also know + * that the Read Data Bytes (03h) command is supported, the hardware + * configuration is very simple and we don't need the extra flexibility + * of the SPI framework. Moreover, we rely on the default settings of + * the SPI controler hardware registers and only adjust what needs to + * be changed. This is good for the code size and this implementation + * adds less than 400 bytes to the SPL. + * + * There are two variants of the SPI controller in Allwinner SoCs: + * A10/A13/A20 (sun4i variant) and everything else (sun6i variant). + * Both of them are supported. + * + * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are + * supported at the moment. + */ + +/*****************************************************************************/ +/* SUN4I variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C) +#define SUN4I_SPI0_CTL (0x01C05000 + 0x08) +#define SUN4I_SPI0_RX (0x01C05000 + 0x00) +#define SUN4I_SPI0_TX (0x01C05000 + 0x04) +#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28) +#define SUN4I_SPI0_BC (0x01C05000 + 0x20) +#define SUN4I_SPI0_TC (0x01C05000 + 0x24) + +#define SUN4I_CTL_ENABLE BIT(0) +#define SUN4I_CTL_MASTER BIT(1) +#define SUN4I_CTL_TF_RST BIT(8) +#define SUN4I_CTL_RF_RST BIT(9) +#define SUN4I_CTL_XCH BIT(10) + +/*****************************************************************************/ +/* SUN6I variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24) +#define SUN6I_SPI0_GCR (0x01C68000 + 0x04) +#define SUN6I_SPI0_TCR (0x01C68000 + 0x08) +#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C) +#define SUN6I_SPI0_MBC (0x01C68000 + 0x30) +#define SUN6I_SPI0_MTC (0x01C68000 + 0x34) +#define SUN6I_SPI0_BCC (0x01C68000 + 0x38) +#define SUN6I_SPI0_TXD (0x01C68000 + 0x200) +#define SUN6I_SPI0_RXD (0x01C68000 + 0x300) + +#define SUN6I_CTL_ENABLE BIT(0) +#define SUN6I_CTL_MASTER BIT(1) +#define SUN6I_CTL_SRST BIT(31) +#define SUN6I_TCR_XCH BIT(31) + +/*****************************************************************************/ + +#define CCM_AHB_GATING0 (0x01C20000 + 0x60) +#define CCM_SPI0_CLK (0x01C20000 + 0xA0) +#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) + +#define AHB_RESET_SPI0_SHIFT 20 +#define AHB_GATE_OFFSET_SPI0 20 + +#define SPI0_CLK_DIV_BY_2 0x1000 +#define SPI0_CLK_DIV_BY_4 0x1001 + +/*****************************************************************************/ + +/* + * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting + * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. + */ +static void spi0_pinmux_setup(unsigned int pin_function) +{ + unsigned int pin; + + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) + sunxi_gpio_set_cfgpin(pin, pin_function); + + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); + else + sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); +} + +/* + * Setup 6 MHz from OSC24M (because the BROM is doing the same). + */ +static void spi0_enable_clock(void) +{ + /* Deassert SPI0 reset on SUN6I */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + setbits_le32(SUN6I_BUS_SOFT_RST_REG0, + (1 << AHB_RESET_SPI0_SHIFT)); + + /* Open the SPI0 gate */ + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + + /* Divide by 4 */ + writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + /* 24MHz from OSC24M */ + writel((1 << 31), CCM_SPI0_CLK); + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + /* Enable SPI in the master mode and do a soft reset */ + setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE | + SUN6I_CTL_SRST); + /* Wait for completion */ + while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + ; + } else { + /* Enable SPI in the master mode and reset FIFO */ + setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + SUN4I_CTL_ENABLE | + SUN4I_CTL_TF_RST | + SUN4I_CTL_RF_RST); + } +} + +static void spi0_disable_clock(void) +{ + /* Disable the SPI0 controller */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE); + else + clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + SUN4I_CTL_ENABLE); + + /* Disable the SPI0 clock */ + writel(0, CCM_SPI0_CLK); + + /* Close the SPI0 gate */ + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + + /* Assert SPI0 reset on SUN6I */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, + (1 << AHB_RESET_SPI0_SHIFT)); +} + +static void spi0_init(void) +{ + unsigned int pin_function = SUNXI_GPC_SPI0; + + if (IS_ENABLED(CONFIG_MACH_SUN50I)) + pin_function = SUN50I_GPC_SPI0; + + spi0_pinmux_setup(pin_function); + spi0_enable_clock(); +} + +static void spi0_deinit(void) +{ + /* New SoCs can disable pins, older could only set them as input */ + unsigned int pin_function = SUNXI_GPIO_INPUT; + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + pin_function = SUNXI_GPIO_DISABLE; + + spi0_disable_clock(); + spi0_pinmux_setup(pin_function); +} + +/*****************************************************************************/ + +#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */ + +static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize, + ulong spi_ctl_reg, + ulong spi_ctl_xch_bitmask, + ulong spi_fifo_reg, + ulong spi_tx_reg, + ulong spi_rx_reg, + ulong spi_bc_reg, + ulong spi_tc_reg, + ulong spi_bcc_reg) +{ + writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */ + writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */ + if (spi_bcc_reg) + writel(4, spi_bcc_reg); /* SUN6I also needs this */ + + /* Send the Read Data Bytes (03h) command header */ + writeb(0x03, spi_tx_reg); + writeb((u8)(addr >> 16), spi_tx_reg); + writeb((u8)(addr >> 8), spi_tx_reg); + writeb((u8)(addr), spi_tx_reg); + + /* Start the data transfer */ + setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); + + /* Wait until everything is received in the RX FIFO */ + while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize) + ; + + /* Skip 4 bytes */ + readl(spi_rx_reg); + + /* Read the data */ + while (bufsize-- > 0) + *buf++ = readb(spi_rx_reg); + + /* tSHSL time is up to 100 ns in various SPI flash datasheets */ + udelay(1); +} + +static void spi0_read_data(void *buf, u32 addr, u32 len) +{ + u8 *buf8 = buf; + u32 chunk_len; + + while (len > 0) { + chunk_len = len; + if (chunk_len > SPI_READ_MAX_SIZE) + chunk_len = SPI_READ_MAX_SIZE; + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN6I_SPI0_TCR, + SUN6I_TCR_XCH, + SUN6I_SPI0_FIFO_STA, + SUN6I_SPI0_TXD, + SUN6I_SPI0_RXD, + SUN6I_SPI0_MBC, + SUN6I_SPI0_MTC, + SUN6I_SPI0_BCC); + } else { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN4I_SPI0_CTL, + SUN4I_CTL_XCH, + SUN4I_SPI0_FIFO_STA, + SUN4I_SPI0_TX, + SUN4I_SPI0_RX, + SUN4I_SPI0_BC, + SUN4I_SPI0_TC, + 0); + } + + len -= chunk_len; + buf8 += chunk_len; + addr += chunk_len; + } +} + +static ulong spi_load_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + spi0_read_data(buf, sector, count); + + return count; +} + +/*****************************************************************************/ + +static int spl_spi_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + int ret = 0; + struct image_header *header; + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); + + spi0_init(); + + spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT image\n"); + load.dev = NULL; + load.priv = NULL; + load.filename = NULL; + load.bl_len = 1; + load.read = spi_load_read; + ret = spl_load_simple_fit(spl_image, &load, + CONFIG_SYS_SPI_U_BOOT_OFFS, header); + } else { + ret = spl_parse_image_header(spl_image, header); + if (ret) + return ret; + + spi0_read_data((void *)spl_image->load_addr, + CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size); + } + + spi0_deinit(); + + return ret; +} +/* Use priorty 0 to override the default if it happens to be linked in */ +SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image); diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index c3e999e27b..519b2a0814 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -47,6 +47,7 @@ CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x08000000 CONFIG_SMC911X_32_BIT=y CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 6ba255d676..4484cf8195 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -135,17 +135,4 @@ config SPI_FLASH_MTD If unsure, say N -if SPL - -config SPL_SPI_SUNXI - bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I - select SPL_SPI_FLASH_SUPPORT - ---help--- - Enable support for SPI Flash. This option allows SPL to read from - sunxi SPI Flash. It uses the same method as the boot ROM, so does - not need any extra configuration. - -endif - endmenu # menu "SPI Flash Support" diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index fcda023412..4be6e9b15f 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -9,7 +9,6 @@ obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o -obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o endif obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c deleted file mode 100644 index fa22981316..0000000000 --- a/drivers/mtd/spi/sunxi_spi_spl.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright (C) 2016 Siarhei Siamashka - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SPL_OS_BOOT -#error CONFIG_SPL_OS_BOOT is not supported yet -#endif - -/* - * This is a very simple U-Boot image loading implementation, trying to - * replicate what the boot ROM is doing when loading the SPL. Because we - * know the exact pins where the SPI Flash is connected and also know - * that the Read Data Bytes (03h) command is supported, the hardware - * configuration is very simple and we don't need the extra flexibility - * of the SPI framework. Moreover, we rely on the default settings of - * the SPI controler hardware registers and only adjust what needs to - * be changed. This is good for the code size and this implementation - * adds less than 400 bytes to the SPL. - * - * There are two variants of the SPI controller in Allwinner SoCs: - * A10/A13/A20 (sun4i variant) and everything else (sun6i variant). - * Both of them are supported. - * - * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are - * supported at the moment. - */ - -/*****************************************************************************/ -/* SUN4I variant of the SPI controller */ -/*****************************************************************************/ - -#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C) -#define SUN4I_SPI0_CTL (0x01C05000 + 0x08) -#define SUN4I_SPI0_RX (0x01C05000 + 0x00) -#define SUN4I_SPI0_TX (0x01C05000 + 0x04) -#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28) -#define SUN4I_SPI0_BC (0x01C05000 + 0x20) -#define SUN4I_SPI0_TC (0x01C05000 + 0x24) - -#define SUN4I_CTL_ENABLE BIT(0) -#define SUN4I_CTL_MASTER BIT(1) -#define SUN4I_CTL_TF_RST BIT(8) -#define SUN4I_CTL_RF_RST BIT(9) -#define SUN4I_CTL_XCH BIT(10) - -/*****************************************************************************/ -/* SUN6I variant of the SPI controller */ -/*****************************************************************************/ - -#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24) -#define SUN6I_SPI0_GCR (0x01C68000 + 0x04) -#define SUN6I_SPI0_TCR (0x01C68000 + 0x08) -#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C) -#define SUN6I_SPI0_MBC (0x01C68000 + 0x30) -#define SUN6I_SPI0_MTC (0x01C68000 + 0x34) -#define SUN6I_SPI0_BCC (0x01C68000 + 0x38) -#define SUN6I_SPI0_TXD (0x01C68000 + 0x200) -#define SUN6I_SPI0_RXD (0x01C68000 + 0x300) - -#define SUN6I_CTL_ENABLE BIT(0) -#define SUN6I_CTL_MASTER BIT(1) -#define SUN6I_CTL_SRST BIT(31) -#define SUN6I_TCR_XCH BIT(31) - -/*****************************************************************************/ - -#define CCM_AHB_GATING0 (0x01C20000 + 0x60) -#define CCM_SPI0_CLK (0x01C20000 + 0xA0) -#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) - -#define AHB_RESET_SPI0_SHIFT 20 -#define AHB_GATE_OFFSET_SPI0 20 - -#define SPI0_CLK_DIV_BY_2 0x1000 -#define SPI0_CLK_DIV_BY_4 0x1001 - -/*****************************************************************************/ - -/* - * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. - */ -static void spi0_pinmux_setup(unsigned int pin_function) -{ - unsigned int pin; - - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) - sunxi_gpio_set_cfgpin(pin, pin_function); - - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); - else - sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); -} - -/* - * Setup 6 MHz from OSC24M (because the BROM is doing the same). - */ -static void spi0_enable_clock(void) -{ - /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - setbits_le32(SUN6I_BUS_SOFT_RST_REG0, - (1 << AHB_RESET_SPI0_SHIFT)); - - /* Open the SPI0 gate */ - setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); - - /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); - /* 24MHz from OSC24M */ - writel((1 << 31), CCM_SPI0_CLK); - - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { - /* Enable SPI in the master mode and do a soft reset */ - setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE | - SUN6I_CTL_SRST); - /* Wait for completion */ - while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) - ; - } else { - /* Enable SPI in the master mode and reset FIFO */ - setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | - SUN4I_CTL_ENABLE | - SUN4I_CTL_TF_RST | - SUN4I_CTL_RF_RST); - } -} - -static void spi0_disable_clock(void) -{ - /* Disable the SPI0 controller */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE); - else - clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | - SUN4I_CTL_ENABLE); - - /* Disable the SPI0 clock */ - writel(0, CCM_SPI0_CLK); - - /* Close the SPI0 gate */ - clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); - - /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, - (1 << AHB_RESET_SPI0_SHIFT)); -} - -static void spi0_init(void) -{ - unsigned int pin_function = SUNXI_GPC_SPI0; - - if (IS_ENABLED(CONFIG_MACH_SUN50I)) - pin_function = SUN50I_GPC_SPI0; - - spi0_pinmux_setup(pin_function); - spi0_enable_clock(); -} - -static void spi0_deinit(void) -{ - /* New SoCs can disable pins, older could only set them as input */ - unsigned int pin_function = SUNXI_GPIO_INPUT; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - pin_function = SUNXI_GPIO_DISABLE; - - spi0_disable_clock(); - spi0_pinmux_setup(pin_function); -} - -/*****************************************************************************/ - -#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */ - -static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize, - ulong spi_ctl_reg, - ulong spi_ctl_xch_bitmask, - ulong spi_fifo_reg, - ulong spi_tx_reg, - ulong spi_rx_reg, - ulong spi_bc_reg, - ulong spi_tc_reg, - ulong spi_bcc_reg) -{ - writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */ - writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */ - if (spi_bcc_reg) - writel(4, spi_bcc_reg); /* SUN6I also needs this */ - - /* Send the Read Data Bytes (03h) command header */ - writeb(0x03, spi_tx_reg); - writeb((u8)(addr >> 16), spi_tx_reg); - writeb((u8)(addr >> 8), spi_tx_reg); - writeb((u8)(addr), spi_tx_reg); - - /* Start the data transfer */ - setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); - - /* Wait until everything is received in the RX FIFO */ - while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize) - ; - - /* Skip 4 bytes */ - readl(spi_rx_reg); - - /* Read the data */ - while (bufsize-- > 0) - *buf++ = readb(spi_rx_reg); - - /* tSHSL time is up to 100 ns in various SPI flash datasheets */ - udelay(1); -} - -static void spi0_read_data(void *buf, u32 addr, u32 len) -{ - u8 *buf8 = buf; - u32 chunk_len; - - while (len > 0) { - chunk_len = len; - if (chunk_len > SPI_READ_MAX_SIZE) - chunk_len = SPI_READ_MAX_SIZE; - - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { - sunxi_spi0_read_data(buf8, addr, chunk_len, - SUN6I_SPI0_TCR, - SUN6I_TCR_XCH, - SUN6I_SPI0_FIFO_STA, - SUN6I_SPI0_TXD, - SUN6I_SPI0_RXD, - SUN6I_SPI0_MBC, - SUN6I_SPI0_MTC, - SUN6I_SPI0_BCC); - } else { - sunxi_spi0_read_data(buf8, addr, chunk_len, - SUN4I_SPI0_CTL, - SUN4I_CTL_XCH, - SUN4I_SPI0_FIFO_STA, - SUN4I_SPI0_TX, - SUN4I_SPI0_RX, - SUN4I_SPI0_BC, - SUN4I_SPI0_TC, - 0); - } - - len -= chunk_len; - buf8 += chunk_len; - addr += chunk_len; - } -} - -static ulong spi_load_read(struct spl_load_info *load, ulong sector, - ulong count, void *buf) -{ - spi0_read_data(buf, sector, count); - - return count; -} - -/*****************************************************************************/ - -static int spl_spi_load_image(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev) -{ - int ret = 0; - struct image_header *header; - header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); - - spi0_init(); - - spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT image\n"); - load.dev = NULL; - load.priv = NULL; - load.filename = NULL; - load.bl_len = 1; - load.read = spi_load_read; - ret = spl_load_simple_fit(spl_image, &load, - CONFIG_SYS_SPI_U_BOOT_OFFS, header); - } else { - ret = spl_parse_image_header(spl_image, header); - if (ret) - return ret; - - spi0_read_data((void *)spl_image->load_addr, - CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size); - } - - spi0_deinit(); - - return ret; -} -/* Use priorty 0 to override the default if it happens to be linked in */ -SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7d73..a3b4a0b2f0 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -23,6 +23,13 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATCSPI200_SPI + bool "Andestech ATCSPI200 SPI driver" + help + Enable the Andestech ATCSPI200 SPI driver. This driver can be + used to access the SPI flash on AE3XX and AE250 platforms embedding + this Andestech IP core. + config ATH79_SPI bool "Atheros SPI driver" depends on ARCH_ATH79 @@ -232,13 +239,6 @@ config FSL_QSPI used to access the SPI NOR flash on platforms embedding this Freescale IP core. -config ATCSPI200_SPI - bool "Andestech ATCSPI200 SPI driver" - help - Enable the Andestech ATCSPI200 SPI driver. This driver can be - used to access the SPI flash on AE3XX and AE250 platforms embedding - this Andestech IP core. - config DAVINCI_SPI bool "Davinci & Keystone SPI driver" depends on ARCH_DAVINCI || ARCH_KEYSTONE diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index 5b2e9d6264..bc08914b9e 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -75,9 +75,6 @@ struct atcspi200_spi_regs { }; struct nds_spi_slave { -#ifndef CONFIG_DM_SPI - struct spi_slave slave; -#endif volatile struct atcspi200_spi_regs *regs; int to; unsigned int freq; @@ -286,89 +283,6 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns, return ret; } -#ifndef CONFIG_DM_SPI -#define to_nds_spi_slave(s) container_of(s, struct nds_spi_slave, slave) -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct nds_spi_slave *ns; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ns = spi_alloc_slave(struct nds_spi_slave, bus, cs); - if (!ns) - return NULL; - - switch (bus) { - case SPI0_BUS: - ns->regs = (struct atcspi200_spi_regs *)SPI0_BASE; - break; - - case SPI1_BUS: - ns->regs = (struct atcspi200_spi_regs *)SPI1_BASE; - break; - - default: - return NULL; - } - - ns->freq= max_hz; - ns->mode = mode; - ns->to = SPI_TIMEOUT; - ns->max_transfer_length = MAX_TRANSFER_LEN; - ns->slave.max_write_size = MAX_TRANSFER_LEN; - - return &ns->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct nds_spi_slave *ns = to_nds_spi_slave(slave); - free(ns); -} - -void spi_init(void) -{ - /* do nothing */ -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct nds_spi_slave *ns = to_nds_spi_slave(slave); - return __atcspi200_spi_claim_bus(ns); -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct nds_spi_slave *ns = to_nds_spi_slave(slave); - __atcspi200_spi_release_bus(ns); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, - void *data_in, unsigned long flags) -{ - struct nds_spi_slave *ns = to_nds_spi_slave(slave); - return __atcspi200_spi_xfer(ns, bitlen, data_out, data_in, flags); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < NSPI_MAX_CS_NUM; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - struct nds_spi_slave *ns = to_nds_spi_slave(slave); - __atcspi200_spi_start(ns); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct nds_spi_slave *ns = to_nds_spi_slave(slave); - __atcspi200_spi_stop(ns); -} -#else static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz) { struct nds_spi_slave *ns = dev_get_priv(bus); @@ -496,4 +410,3 @@ U_BOOT_DRIVER(atcspi200_spi) = { .priv_auto_alloc_size = sizeof(struct nds_spi_slave), .probe = atcspi200_spi_probe, }; -#endif diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 1da4542af0..053a67bbe0 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -456,9 +456,6 @@ static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) conf |= OMAP3_MCSPI_MODULCTRL_SINGLE; writel(conf, &priv->regs->modulctrl); - - _omap3_spi_set_mode(priv); - _omap3_spi_set_speed(priv); } #ifndef CONFIG_DM_SPI @@ -594,8 +591,6 @@ static int omap3_spi_claim_bus(struct udevice *dev) struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); priv->cs = slave_plat->cs; - priv->mode = slave_plat->mode; - priv->freq = slave_plat->max_hz; _omap3_spi_claim_bus(priv); return 0; @@ -650,13 +645,29 @@ static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen, return _spi_xfer(priv, bitlen, dout, din, flags); } -static int omap3_spi_set_speed(struct udevice *bus, unsigned int speed) +static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed) { + struct udevice *bus = dev->parent; + struct omap3_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + priv->cs = slave_plat->cs; + priv->freq = slave_plat->max_hz; + _omap3_spi_set_speed(priv); + return 0; } -static int omap3_spi_set_mode(struct udevice *bus, uint mode) +static int omap3_spi_set_mode(struct udevice *dev, uint mode) { + struct udevice *bus = dev->parent; + struct omap3_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + priv->cs = slave_plat->cs; + priv->mode = slave_plat->mode; + _omap3_spi_set_mode(priv); + return 0; }