From: Paul Fertser <fercerpav@gmail.com>
Date: Fri, 6 Nov 2015 17:26:46 +0000 (+0300)
Subject: target: cortex_a: do not create new register cache every reset
X-Git-Tag: v0.10.0-rc1~382
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=408213f554be009a11023b987dd1158b966b06cb;p=openocd

target: cortex_a: do not create new register cache every reset

Commit 68101e67ac16bdead3bd6d48cbe0a2bfd63aac02 introduced a
regression which resulted for ever-growing registers list (as output
by "reg" command), its contents were doubled every reset (actually,
every examination).

Change-Id: Ie3409c795160a2fc840a5e8a892928df0bcc0c57
Reported-by: Daniele Emancipato <daniele12457@hotmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3100
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
---

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 39a79ddf..d0260dae 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2996,9 +2996,13 @@ static int cortex_a_examine_first(struct target *target)
 	LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR  0x%" PRIx32, target->coreid, dbg_osreg);
 
 	armv7a->arm.core_type = ARM_MODE_MON;
-	retval = cortex_a_dpm_setup(cortex_a, didr);
-	if (retval != ERROR_OK)
-		return retval;
+
+	/* Avoid recreating the registers cache */
+	if (!target_was_examined(target)) {
+		retval = cortex_a_dpm_setup(cortex_a, didr);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	/* Setup Breakpoint Register Pairs */
 	cortex_a->brp_num = ((didr >> 24) & 0x0F) + 1;