From: Masahiro Yamada Date: Mon, 19 Jan 2015 13:31:10 +0000 (+0900) Subject: ARM: UniPhier: fix IECTRL set code for PH1-Pro4 X-Git-Tag: v2015.04-rc1~62^2~5 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=448437496b7cb2b7a80d4b3ada9f225506379c5c;p=u-boot ARM: UniPhier: fix IECTRL set code for PH1-Pro4 For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only available bit in this register. There is no effect of the write access to the other bits. Signed-off-by: Masahiro Yamada --- diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c index 2cc5df608f..b7c4b10969 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c @@ -23,6 +23,6 @@ void sg_init(void) /* Input ports must be enabled before deasserting reset of cores */ tmp = readl(SG_IECTRL); - tmp |= 0x1; + tmp |= 1 << 6; writel(tmp, SG_IECTRL); }