From: Ken Ma <make@marvell.com>
Date: Mon, 26 Mar 2018 07:55:59 +0000 (+0800)
Subject: arm64: a37xx: pinctrl: Fix number of pin in south bridge
X-Git-Tag: v2018.05-rc1~2^2~13
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=44ac747bdfceeefdf3cd70caed05eddfe23affb8;p=u-boot

arm64: a37xx: pinctrl: Fix number of pin in south bridge

On the south bridge we have pin from 0 to 29, so it gives 30 pins (and
not 29).

Reviewed-on: http://vgitil04.il.marvell.com:8080/43285
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 2bf853eba1..d058fbace8 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -189,7 +189,7 @@ const struct armada_37xx_pin_data armada_37xx_pin_nb = {
 };
 
 const struct armada_37xx_pin_data armada_37xx_pin_sb = {
-	.nr_pins = 29,
+	.nr_pins = 30,
 	.name = "GPIO2",
 	.groups = armada_37xx_sb_groups,
 	.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),