From: rtel Date: Fri, 8 Mar 2019 17:30:49 +0000 (+0000) Subject: Correcting spelling mistakes in comments only. X-Git-Tag: V10.2.1~18 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=44d8c36b4178b2d1c6d8d8e64a5e9e2be2901e99;p=freertos Correcting spelling mistakes in comments only. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2645 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h index 51924f0be..7a47e1efb 100644 --- a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h +++ b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h @@ -75,7 +75,7 @@ /* Save additional registers found on the Pulpino. */ .macro portasmSAVE_ADDITIONAL_REGISTERS addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */ - csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */ + csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */ csrr t1, lpend0 csrr t2, lpcount0 csrr t3, lpstart1 @@ -91,7 +91,7 @@ /* Restore the additional registers found on the Pulpino. */ .macro portasmRESTORE_ADDITIONAL_REGISTERS - lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */ + lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ lw t1, 2 * portWORD_SIZE( sp ) lw t2, 3 * portWORD_SIZE( sp ) lw t3, 4 * portWORD_SIZE( sp )