From: Arun Mankuzhi Date: Fri, 30 Nov 2012 13:01:14 +0000 (+0000) Subject: arm: move flush_dcache_all() to just before disable cache X-Git-Tag: v2013.01~9^2~10 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=44df5e8d30a276985b40bb32a69584f5a7fac9a0;p=u-boot arm: move flush_dcache_all() to just before disable cache In Cortex-A15 architecture, when we run cache invalidate the cache clean operation executes automatically. So if there are any dirty cache lines before disabling the L2 cache these will be synchronized with the main memory when invalidate_dcache_all() runs in the last part of U-boot The two functions after flush_dcache_all is using the stack. So this data will be on the cache. After disable when invalidate is called the data will be flushed from cache to memory. This corrupts the stack in invalida_dcache_all. So this change is required to avoid the u-boot hang. So flush has to be done just before clearing CR_C bit Signed-off-by: Arun Mankuzhi Signed-off-by: Simon Glass --- diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6edf815d4d..1cab27c226 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -153,8 +153,11 @@ static void cache_disable(uint32_t cache_bit) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; - flush_dcache_all(); } + reg = get_cr(); + cp_delay(); + if (cache_bit == (CR_C | CR_M)) + flush_dcache_all(); set_cr(reg & ~cache_bit); } #endif