From: Marek Vasut <marex@denx.de>
Date: Wed, 8 Jul 2015 23:47:56 +0000 (+0200)
Subject: ddr: altera: Fix typo in mp_threshold1 programming
X-Git-Tag: v2015.10-rc2~382
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=452a81e0786825d0a86c26d320b22055a387c749;p=u-boot

ddr: altera: Fix typo in mp_threshold1 programming

It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
---

diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 45846debdf..90a4b2c687 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -539,7 +539,7 @@ static void set_sdr_mp_threshold(void)
 
 	clrsetbits_le32(&sdr_ctrl->mp_threshold1,
 			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
-			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK <<
+			CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
 
 	clrsetbits_le32(&sdr_ctrl->mp_threshold2,