From: richardbarry Date: Sun, 28 Aug 2011 16:41:01 +0000 (+0000) Subject: Remove platform studio project as it is about to be replaced. X-Git-Tag: V7.0.2~37 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=459a33bef971a7ac2ef5c91c5eb695858681bbee;p=freertos Remove platform studio project as it is about to be replaced. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1573 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit deleted file mode 100644 index 4fa2c85c3..000000000 Binary files a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit and /dev/null differ diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.xml deleted file mode 100644 index 3c2d81d0d..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.xml +++ /dev/null @@ -1,6936 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Interconnect - AXI4 Memory-Mapped Interconnect - - - - - - - Family - - - Base Family - - - Number of Slave Slots - - - Number of Master Slots - - - AXI ID Widgth - - - AXI Address Widgth - - - AXI Data Maximum Width - - - Slave AXI Data Width - - - Master AXI Data Width - - - Interconnect Crossbar Data Width - - - AXI Protocol - - - Master AXI Protocol - - - Master AXI Base Address - - - Master AXI High Address - - - Slave AXI Base ID - - - Slave AXI Thread ID Width - - - Slave AXI Is Interconnect - - - Slave AXI ACLK Ratio - - - Slvave AXI Is ACLK ASYNC - - - Master AXI ACLK Ratio - - - Master AXI Is ACLK ASYNC - - - Interconnect Crossbar ACLK Frequency Ratio - - - Slave AXI Supports Write - - - Slave AXI Supports Read - - - Master AXI Supports Write - - - Master AXI Supports Read - - - Propagate USER Signals - - - AWUSER Signal Width - - - ARUSER Signal Width - - - WUSER Signal Width - - - RUSER Signal Width - - - BUSER Signal Width - - - AXI Connectivity - - - Slave AXI Single Thread - - - Master AXI Supports Reordering - - - Master generates narrow bursts - - - Slave accepts narrow bursts - - - Slave AXI Write Acceptance - - - Slave AXI Read Acceptance - - - Master AXI Write Issuing - - - Master AXI Read Issuing - - - Slave AXI ARB Priority - - - Master AXI Secure - - - Master AXI Write FIFO Depth - - - Slave AXI Write FIFO Type - - - Slave AXI Write FIFO Delay - - - Slave AXI Read FIFO Depth - - - Slave AXI Read FIFO Type - - - Slave AXI Read FIFO Delay - - - Master AXI Write FIFO Depth - - - Master AXI Write FIFO Type - - - Master AXI Write FIFO Delay - - - Master AXI Read FIFO Depth - - - Master AXI Read FIFO Type - - - Master AXI Read FIFO Delay - - - Slave AXI AW Register - - - Slave AXI AR Register - - - Slave AXI W Register - - - Slave AXI R Register - - - Slave AXI B Register - - - Master AXI AW Register - - - Master AXI AR Register - - - Master AXI W Register - - - Master AXI R Register - - - Master AXI B Register - - - C_INTERCONNECT_R_REGISTER - - - Interconnect Architecture - - - Use Diagnostic Slave Port - - - Generate Interrupts - - - Check for transaction errors (DECERR) - - - Slave AXI CTRL Protocol - - - Slave AXI CTRL Address Width - - - Slave AXI CTRL Data Width - - - Diagnostic Slave Port Base Address - - - Diagnostic Slave Port High Address - - - Simulation debug - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Interconnect - AXI4 Memory-Mapped Interconnect - - - - - - - Family - - - Base Family - - - Number of Slave Slots - - - Number of Master Slots - - - AXI ID Widgth - - - AXI Address Widgth - - - AXI Data Maximum Width - - - Slave AXI Data Width - - - Master AXI Data Width - - - Interconnect Crossbar Data Width - - - AXI Protocol - - - Master AXI Protocol - - - Master AXI Base Address - - - Master AXI High Address - - - Slave AXI Base ID - - - Slave AXI Thread ID Width - - - Slave AXI Is Interconnect - - - Slave AXI ACLK Ratio - - - Slvave AXI Is ACLK ASYNC - - - Master AXI ACLK Ratio - - - Master AXI Is ACLK ASYNC - - - Interconnect Crossbar ACLK Frequency Ratio - - - Slave AXI Supports Write - - - Slave AXI Supports Read - - - Master AXI Supports Write - - - Master AXI Supports Read - - - Propagate USER Signals - - - AWUSER Signal Width - - - ARUSER Signal Width - - - WUSER Signal Width - - - RUSER Signal Width - - - BUSER Signal Width - - - AXI Connectivity - - - Slave AXI Single Thread - - - Master AXI Supports Reordering - - - Master generates narrow bursts - - - Slave accepts narrow bursts - - - Slave AXI Write Acceptance - - - Slave AXI Read Acceptance - - - Master AXI Write Issuing - - - Master AXI Read Issuing - - - Slave AXI ARB Priority - - - Master AXI Secure - - - Master AXI Write FIFO Depth - - - Slave AXI Write FIFO Type - - - Slave AXI Write FIFO Delay - - - Slave AXI Read FIFO Depth - - - Slave AXI Read FIFO Type - - - Slave AXI Read FIFO Delay - - - Master AXI Write FIFO Depth - - - Master AXI Write FIFO Type - - - Master AXI Write FIFO Delay - - - Master AXI Read FIFO Depth - - - Master AXI Read FIFO Type - - - Master AXI Read FIFO Delay - - - Slave AXI AW Register - - - Slave AXI AR Register - - - Slave AXI W Register - - - Slave AXI R Register - - - Slave AXI B Register - - - Master AXI AW Register - - - Master AXI AR Register - - - Master AXI W Register - - - Master AXI R Register - - - Master AXI B Register - - - C_INTERCONNECT_R_REGISTER - - - Interconnect Architecture - - - Use Diagnostic Slave Port - - - Generate Interrupts - - - Check for transaction errors (DECERR) - - - Slave AXI CTRL Protocol - - - Slave AXI CTRL Address Width - - - Slave AXI CTRL Data Width - - - Diagnostic Slave Port Base Address - - - Diagnostic Slave Port High Address - - - Simulation debug - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MicroBlaze - The MicroBlaze 32 bit soft processor - - - - - - - - - - - - - Enable Fault Tolerance Support - - - - - Select implementation to optimize area (with lower instruction throughput) - - - - Select Bus Interfaces - - - Select Stream Interfaces - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Enable Additional Machine Status Register Instructions - - - Enable Pattern Comparator - - - Enable Barrel Shifter - - - Enable Integer Divider - - - Enable Integer Multiplier - - - Enable Floating Point Unit - - - Enable Unaligned Data Exception - - - Enable Illegal Instruction Exception - - - Enable Instruction-side AXI Exception - - - Enable Data-side AXI Exception - - - Enable Instruction-side PLB Exception - - - Enable Data-side PLB Exception - - - Enable Integer Divide Exception - - - Enable Floating Point Unit Exceptions - - - Enable Stream Exception - - - <qt>Enable stack protection</qt> - - - Specifies Processor Version Register - - - Specify USER1 Bits in Processor Version Register - - - Specify USER2 Bits in Processor Version Registers - - - Enable MicroBlaze Debug Module Interface - - - Number of PC Breakpoints - - - Number of Read Address Watchpoints - - - Number of Write Address Watchpoints - - - Sense Interrupt on Edge vs. Level - - - Sense Interrupt on Rising vs. Falling Edge - - - Specify Reset Value for Select MSR Bits - - - <qt>Generate Illegal Instruction Exception for NULL Instruction</qt> - - - Number of Stream Links - - - - Enable Additional Stream Instructions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I-Cache Base Address - - - I-Cache High Address - - - Enable Instruction Cache - - - Enable I-Cache Writes - - - - Size of the I-Cache in Bytes - - - - Instruction Cache Line Length - - - Use Cache Links for All I-Cache Memory Accesses - - - - Number of I-Cache Victims - - - Number of I-Cache Streams - - - Use Distributed RAM for I-Cache Tags - - - - - - - - - - - - - - - - - - - - D-Cache Base Address - - - D-Cache High Address - - - Enable Data Cache - - - Enable D-Cache Writes - - - - Size of D-Cache in Bytes - - - - Data Cache Line Length - - - Use Cache Links for All D-Cache Memory Accesses - - - - Enable Write-back Storage Policy - - - Number of D-Cache Victims - - - Use Distributed RAM for D-Cache Tags - - - - - - - - - - - - - - - - - - - - - - Memory Management - - - Data Shadow Translation Look-Aside Buffer Size - - - Instruction Shadow Translation Look-Aside Buffer Size - - - Enable Access to Memory Management Special Registers - - - Number of Memory Protection Zones - - - Privileged Instructions - - - - - - Enable Branch Target Cache - - - Branch Target Cache Size - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Local Memory Bus (LMB) 1.0 - 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' - - - - - - - Number of Bus Slaves - - - LMB Address Bus Width - - - LMB Data Bus Width - - - Active High External Reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Local Memory Bus (LMB) 1.0 - 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' - - - - - - - Number of Bus Slaves - - - LMB Address Bus Width - - - LMB Data Bus Width - - - Active High External Reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMB BRAM Controller - Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus - - - - - - - LMB BRAM Base Address - - - LMB BRAM High Address - - - - LMB Address Decode Mask - - - LMB Address Bus Width - - - LMB Data Bus Width - - - Error Correction Code - - - Select Interconnect - - - Fault Inject Registers - - - Correctable Error First Failing Register - - - Uncorrectable Error First Failing Register - - - ECC Status and Control Register - - - ECC On/Off Register - - - ECC On/Off Reset Value - - - Correctable Error Counter Register Width - - - Write Access setting - - - Base Address for PLB Interface - - - High Address for PLB Interface - - - PLB Address Bus Width - - - PLB Data Bus Width - - - PLB Slave Uses P2P Topology - - - Master ID Bus Width of PLB - - - Number of PLB Masters - - - PLB Slave is Capable of Bursts - - - Native Data Bus Width of PLB Slave - - - Frequency of PLB Slave - - - S_AXI_CTRL Clock Frequency - - - S_AXI_CTRL Base Address - - - S_AXI_CTRL High Address - - - S_AXI_CTRL Address Width - - - S_AXI_CTRL Data Width - - - S_AXI_CTRL Protocol - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMB BRAM Controller - Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus - - - - - - - LMB BRAM Base Address - - - LMB BRAM High Address - - - - LMB Address Decode Mask - - - LMB Address Bus Width - - - LMB Data Bus Width - - - Error Correction Code - - - Select Interconnect - - - Fault Inject Registers - - - Correctable Error First Failing Register - - - Uncorrectable Error First Failing Register - - - ECC Status and Control Register - - - ECC On/Off Register - - - ECC On/Off Reset Value - - - Correctable Error Counter Register Width - - - Write Access setting - - - Base Address for PLB Interface - - - High Address for PLB Interface - - - PLB Address Bus Width - - - PLB Data Bus Width - - - PLB Slave Uses P2P Topology - - - Master ID Bus Width of PLB - - - Number of PLB Masters - - - PLB Slave is Capable of Bursts - - - Native Data Bus Width of PLB Slave - - - Frequency of PLB Slave - - - S_AXI_CTRL Clock Frequency - - - S_AXI_CTRL Base Address - - - S_AXI_CTRL High Address - - - S_AXI_CTRL Address Width - - - S_AXI_CTRL Data Width - - - S_AXI_CTRL Protocol - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Block RAM (BRAM) Block - The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. - - - - - - - Size of BRAM(s) in Bytes - - - Data Width of Port A and B - - - Address Width of Port A and B - - - Number of Byte Write Enables - - - Device Family - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Processor System Reset Module - Reset management module - - - - - - - Device Subfamily - - - Number of Clocks Before Input Change is Recognized On The External Reset Input - - - Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input - - - External Reset Active High - - - Auxiliary Reset Active High - - - Number of Bus Structure Reset Registered Outputs - - - Number of Peripheral Reset Registered Outputs - - - Number of Active Low Interconnect Reset Registered Outputs - - - Number of Active Low Peripheral Reset Registered Outputs - - - Device Family - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Clock Generator - Clock generator for processor system. - - - - - - - Family - - - Device - - - Package - - - Speed Grade - - - Input Clock Frequency (Hz) - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Varaible Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Varaible Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase - - - Required Frequency (Hz) - - - Clock Deskew - - - Required Frequency (Hz) - - - Required Phase - - - Required Group - - - Buffered - - - Variable Phase Shift - - - - Clock Primitive Feedback Buffer - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MicroBlaze Debug Module (MDM) - Debug module for MicroBlaze Soft Processor. - - - - - - - Device Family - - - Specifies the JTAG user-defined register used - - - Specifies the Bus Interface for the JTAG UART - - - Base Address - - - High Address - - - PLB Address Bus Width - - - PLB Data Bus Width - - - PLB Slave Uses P2P Topology - - - Master ID Bus Width of PLB - - - Number of PLB Masters - - - Native Data Bus Width of PLB Slave - - - PLB Slave is Capable of Bursts - - - Number of MicroBlaze debug ports - - - Enable JTAG UART - - - AXI Address Width - - - AXI Data Width - - - AXI4LITE protocal - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI UART (Lite) - Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI. - - - - - - - Device Family - - - AXI Clock Frequency - - - AXI Base Address - - - AXI High Address - - - AXI Address Width - - - AXI Data Width - - - UART Lite Baud Rate - Baud Rate - - - Number of Data Bits in a Serial Frame - Data Bits - - - Use Parity - - - Parity Type - - - AXI4LITE protocol - - - - - - - - - - Serial Data Out - - - Serial Data In - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI General Purpose IO - General Purpose Input/Output (GPIO) core for the AXI bus. - - - - - - - Device Family - - - AXI Base Address - - - AXI High Address - - - AXI Address Width - - - AXI Data Width - - - GPIO Data Channel Width - GPIO Data Width - - - GPIO2 Data Channel Width - - - Channel 1 is Input Only - - - Channel 2 is Input Only - - - GPIO Supports Interrupts - - - Channel 1 Data Out Default Value - - - Channel 1 Tri-state Default Value - - - Enable Channel 2 - - - Channel 2 Data Out Default Value - - - Channel 2 Tri-state Default Value - - - AXI4LITE protocol - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GPIO1 Data IO - - - GPIO2 Data IO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI General Purpose IO - General Purpose Input/Output (GPIO) core for the AXI bus. - - - - - - - Device Family - - - AXI Base Address - - - AXI High Address - - - AXI Address Width - - - AXI Data Width - - - GPIO Data Channel Width - GPIO Data Width - - - GPIO2 Data Channel Width - - - Channel 1 is Input Only - - - Channel 2 is Input Only - - - GPIO Supports Interrupts - - - Channel 1 Data Out Default Value - - - Channel 1 Tri-state Default Value - - - Enable Channel 2 - - - Channel 2 Data Out Default Value - - - Channel 2 Tri-state Default Value - - - AXI4LITE protocol - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GPIO1 Data IO - - - GPIO2 Data IO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI S6 Memory Controller(DDR/DDR2/DDR3) - Spartan-6 memory controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Ethernet - AXI Ethernet MAC - - - - - - - AXI Protocol - - - AXI Stream Bus Width - - - AXI Stream Bus Width - - - AXI Stream Bus Width - - - AXI Stream Bus Width - - - AXI Stream Protocol - - - AXI Stream Protocol - - - AXI Stream Protocol - - - AXI Stream Protocol - - - AXI Stream Protocol - - - AXI Stream Protocol - - - Device Family - - - AXI Clock Freq in HZ - - - Base Address - - - High Address - - - AXI Address Width - - - AXI Data Width - - - AXI ID Width - - - Spartan 6 Transceiver Side - - - PHY Address - - - Include IO and BUFG as Needed for the PHY Interface Selected - - - Type of TEMAC - - - Physical Interface Type - - - Enable Half Duplex mode - - - TX Memory Depth - - - RX Memory Depth - - - Enable TX Checksum Offload - - - Enable RX Checksum Offload - - - Transmit VLAN translation - - - Receive VLAN translation - - - Transmit VLAN tagging - - - Receive VLAN tagging - - - Transmit VLAN stripping - - - Receive VLAN stripping - - - Receive Extended Multicast Address Filtering - - - Statistics Counters - - - Audio Video Bridging (AVB) - license required - - - Simulation Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI DMA Engine - AXI MemoryMap to/from AXI Stream Direct Memory Access Engine - - - - - - - AXI Lite Address Width - - - AXI Lite Data Width - - - Delay Timer Counter Resolution - - - Primary clock Is Asynchronous - - - Include Scatter Gather Descriptor Queuing - - - Include AXI Status and Control Streams - - - Use Status Stream App Length - - - Buffer Length Field Width - - - AXI SG Address Width - - - AXI SG Data Width - - - AXI Control Stream Width - - - AXI Status Stream Width - - - Include MM2S Channel - - - Include MM2S Data Realignment Engine - - - Maximum Memory Map Burst Size for MM2S - - - MM2S Address Width - - - MM2S Memory Map Data Width - - - MM2S Stream Data Width - - - Include S2MM Channel - - - Include S2MM Data Realignment Engine - - - Maximum Memory Map Burst Size for S2MM (data beats) - - - S2MM Address Width - - - S2MM Memory Map Data Width - - - S2MM Stream Data Width - - - Device Family - - - Base Address - - - High Address - - - AXI Lite Clock Frequency - - - AXI Scatter Gather Clock Frequency - - - AXI MM2S Clock Frequency - - - AXI S2MM Clock Frequency - - - AXI Lite Protocol - - - AXI Lite Supports Read Access - - - AXI Lite Supports Write Access - - - AXI SG Protocol - - - AXI SG Support Threads - - - Base Address - - - AXI SG Supports Narrow Bursts - - - AXI SG Generates Read Accesses - - - AXI SG Generates Write Accesses - - - AXI MM2S Protocol - - - AXI MM2S Support Threads - - - AXI MM2S Thread ID Width - - - AXI MM2S Supports Narrow Bursts - - - AXI MM2S Generates Read Accesses - - - AXI MM2S Generates Write Accesses - - - AXI MM2S Interface Read Issuing - - - AXI MM2S Interface Read FIFO Depth - - - AXI S2MM Protocol - - - AXI S2MM Support Threads - - - AXI S2MM Thread ID Width - - - AXI S2MM Supports Narrow Bursts - - - AXI S2MM Generates Write Accesses - - - AXI S2MM Generates Read Accesses - - - AXI S2MM Interface Write Issuing - - - AXI S2MM Interface Write FIFO Depth - - - AXI MM2S Stream Interface Protocol - - - AXI S2MM Stream Interface Protocol - - - AXI MM2S Control Stream Interface Protocol - - - AXI S2MM Status Stream Interface Protocol - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Interrupt Controller - intc core attached to the AXI - - - - - - - Device Family - - - AXI Base Address - - - AXI High Address - - - AXI Address Width - - - AXI Data Width - - - Number of Interrupt Inputs - - - Type of Interrupt for Each Input - - - Type of Each Edge Senstive Interrupt - - - Type of Each Level Sensitive Interrupt - - - Support IPR - - - Support SIE - - - Support CIE - - - Support IVR - - - IRQ Output Use Level - - - The Sense of IRQ Output - - - AXI4LITE protocol - - - - - - - - - - Interrupt Request Output - - - - - - - - - - - - Interrupt Inputs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Timer/Counter - Timer counter with AXI interface - - - - - - - AXI4LITE protocol - - - Device Family - - - The Width of Counter in Timer - Count Width - - - Only One Timer is present - - - TRIG0 Active Level - - - TRIG1 Active Level - - - GEN0 Active Level - - - GEN1 Active Level - - - AXI Base Address - - - AXI High Address - - - AXI Address Width - - - AXI Data Width - - - - - - - Capture Trig 0 - - - Capture Trig 1 - - - Generate Out 0 - - - Generate Out 1 - - - Pulse Width Modulation 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm deleted file mode 100644 index 4ccd72ac6..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm +++ /dev/null @@ -1,32 +0,0 @@ -// BMM LOC annotation file. -// -// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010 -// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. - - -/////////////////////////////////////////////////////////////////////////////// -// -// Processor 'microblaze_0', ID 100, memory map. -// -/////////////////////////////////////////////////////////////////////////////// - -ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100 - - - /////////////////////////////////////////////////////////////////////////////// - // - // Processor 'microblaze_0' address space 'microblaze_0_bram_block_combined' 0x00000000:0x00001FFF (8 KBytes). - // - /////////////////////////////////////////////////////////////////////////////// - - ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF] - BUS_BLOCK - microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X3Y26; - microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X3Y28; - microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X2Y30; - microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X2Y28; - END_BUS_BLOCK; - END_ADDRESS_SPACE; - -END_ADDRESS_MAP; - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl deleted file mode 100644 index 31625c0c4..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl +++ /dev/null @@ -1,180 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_Colors.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_Colors.xsl deleted file mode 100644 index 1c97a4dee..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_Colors.xsl +++ /dev/null @@ -1,150 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_Globals.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_Globals.xsl deleted file mode 100644 index c066fad3a..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_Globals.xsl +++ /dev/null @@ -1,168 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl deleted file mode 100644 index 88282dee5..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl +++ /dev/null @@ -1,584 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - UNKNOWN Text style class - - - - - - - - - - \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl deleted file mode 100644 index 89b61569f..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl +++ /dev/null @@ -1,2758 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NONE - - - - - - - - NONE - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - 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- - - - - - 0 - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - -symbol_STACK_ - - - - -symbol_GROUP_ - - - -symbol_SPACE_WEST__EAST_ -symbol_STACK_ -symbol_STACK__SHAPE_ - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgBLKD_Processors.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgBLKD_Processors.xsl deleted file mode 100644 index 11ab1be08..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgBLKD_Processors.xsl +++ /dev/null @@ -1,465 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SLAVES OF - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - "_no_interrupt_cntlr_" - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl deleted file mode 100644 index 160f2d8be..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl +++ /dev/null @@ -1,271 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_input.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_input.txt deleted file mode 100644 index afb0f0de5..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_input.txt +++ /dev/null @@ -1,16 +0,0 @@ -SET_FLAG FLOW SOCKETABLE -SET_FLAG MODE BATCH -SET_FLAG DRCMODE ERROR -SET_FLAG COMPONENT_NAME MCB_DDR3 -SET_PREFERENCE projectname MCB_DDR3 -SET_PREFERENCE devicefamily spartan6 -SET_PREFERENCE devicesubfamily t -SET_PREFERENCE partname xc6slx45tfgg484-3 -SET_PREFERENCE device xc6slx45t -SET_PREFERENCE package fgg484 -SET_PREFERENCE speedgrade -3 -SET_PREFERENCE outputdirectory ./ -SET_PREFERENCE workingdirectory ./ -SET_PREFERENCE subworkingdirectory ./ -SET_PREFERENCE InputParamsFile param_input.xml -SET_PREFERENCE OutputParamsFile param_output.xml diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_output.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_output.txt deleted file mode 100644 index ed2bda49c..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_output.txt +++ /dev/null @@ -1,4 +0,0 @@ -SET_ERROR_CODE 0 -SET_XMDF_PATH ./MCB_DDR3_xmdf.tcl -SET_PARAMETER component_name MCB_DDR3 -SET_PARAMETER xml_input_file ./MCB_DDR3/user_design/mig.prj diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml deleted file mode 100644 index 5371f8626..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml +++ /dev/null @@ -1,953 +0,0 @@ - - - - - - - - - - - - - - - C_ARB_ALGORITHM - "0" - - - C_ARB_NUM_TIME_SLOTS - "12" - - - C_ARB_TIME_SLOT_0 - "0b000000000001010011" - - - C_ARB_TIME_SLOT_1 - "0b000000001010011000" - - - C_ARB_TIME_SLOT_2 - "0b000000010011000001" - - - C_ARB_TIME_SLOT_3 - "0b000000011000001010" - - - C_ARB_TIME_SLOT_4 - "0b000000000001010011" - - - C_ARB_TIME_SLOT_5 - "0b000000001010011000" - - - C_ARB_TIME_SLOT_6 - "0b000000010011000001" - - - C_ARB_TIME_SLOT_7 - "0b000000011000001010" - - - C_ARB_TIME_SLOT_8 - "0b000000000001010011" - - - C_ARB_TIME_SLOT_9 - "0b000000001010011000" - - - C_ARB_TIME_SLOT_10 - "0b000000010011000001" - - - C_ARB_TIME_SLOT_11 - "0b000000011000001010" - - - C_BYPASS_CORE_UCF - "0" - - - C_INTERCONNECT_S0_AXI_ACLK_RATIO - "100000000" - - - C_INTERCONNECT_S0_AXI_AR_REGISTER - "1" - - - C_INTERCONNECT_S0_AXI_AW_REGISTER - "1" - - - C_INTERCONNECT_S0_AXI_B_REGISTER - "1" - - - C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC - "0" - - - C_INTERCONNECT_S0_AXI_MASTERS - "microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM" - - - C_INTERCONNECT_S0_AXI_R_REGISTER - "1" - - - C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE - "4" - - - C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S0_AXI_SECURE - "0" - - - C_INTERCONNECT_S0_AXI_W_REGISTER - "1" - - - C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE - "4" - - - C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S1_AXI_ACLK_RATIO - "1" - - - C_INTERCONNECT_S1_AXI_AR_REGISTER - "0" - - - C_INTERCONNECT_S1_AXI_AW_REGISTER - "0" - - - C_INTERCONNECT_S1_AXI_B_REGISTER - "0" - - - C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC - "0" - - - C_INTERCONNECT_S1_AXI_MASTERS - "none" - - - C_INTERCONNECT_S1_AXI_R_REGISTER - "0" - - - C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE - "4" - - - C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S1_AXI_SECURE - "0" - - - C_INTERCONNECT_S1_AXI_W_REGISTER - "0" - - - C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE - "4" - - - C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S2_AXI_ACLK_RATIO - "1" - - - C_INTERCONNECT_S2_AXI_AR_REGISTER - "0" - - - C_INTERCONNECT_S2_AXI_AW_REGISTER - "0" - - - C_INTERCONNECT_S2_AXI_B_REGISTER - "0" - - - C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC - "0" - - - C_INTERCONNECT_S2_AXI_MASTERS - "none" - - - C_INTERCONNECT_S2_AXI_R_REGISTER - "0" - - - C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE - "4" - - - C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S2_AXI_SECURE - "0" - - - C_INTERCONNECT_S2_AXI_W_REGISTER - "0" - - - C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE - "4" - - - C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S3_AXI_ACLK_RATIO - "1" - - - C_INTERCONNECT_S3_AXI_AR_REGISTER - "0" - - - C_INTERCONNECT_S3_AXI_AW_REGISTER - "0" - - - C_INTERCONNECT_S3_AXI_B_REGISTER - "0" - - - C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC - "0" - - - C_INTERCONNECT_S3_AXI_MASTERS - "none" - - - C_INTERCONNECT_S3_AXI_R_REGISTER - "0" - - - C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE - "4" - - - C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S3_AXI_SECURE - "0" - - - C_INTERCONNECT_S3_AXI_W_REGISTER - "0" - - - C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE - "4" - - - C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S4_AXI_ACLK_RATIO - "1" - - - C_INTERCONNECT_S4_AXI_AR_REGISTER - "0" - - - C_INTERCONNECT_S4_AXI_AW_REGISTER - "0" - - - C_INTERCONNECT_S4_AXI_B_REGISTER - "0" - - - C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC - "0" - - - C_INTERCONNECT_S4_AXI_MASTERS - "none" - - - C_INTERCONNECT_S4_AXI_R_REGISTER - "0" - - - C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE - "4" - - - C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S4_AXI_SECURE - "0" - - - C_INTERCONNECT_S4_AXI_W_REGISTER - "0" - - - C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE - "4" - - - C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S5_AXI_ACLK_RATIO - "1" - - - C_INTERCONNECT_S5_AXI_AR_REGISTER - "0" - - - C_INTERCONNECT_S5_AXI_AW_REGISTER - "0" - - - C_INTERCONNECT_S5_AXI_B_REGISTER - "0" - - - C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC - "0" - - - C_INTERCONNECT_S5_AXI_MASTERS - "none" - - - C_INTERCONNECT_S5_AXI_R_REGISTER - "0" - - - C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE - "4" - - - C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH - "0" - - - C_INTERCONNECT_S5_AXI_SECURE - "0" - - - C_INTERCONNECT_S5_AXI_W_REGISTER - "0" - - - C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE - "4" - - - C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH - "0" - - - C_MCB_LOC - "MEMC3" - - - C_MCB_PERFORMANCE - "STANDARD" - - - C_MCB_RZQ_LOC - "K7" - - - C_MCB_USE_EXTERNAL_BUFPLL - "0" - - - C_MCB_ZIO_LOC - "R7" - - - C_MEM_ADDR_ORDER - "ROW_BANK_COLUMN" - - - C_MEM_ADDR_WIDTH - "13" - - - C_MEM_BANKADDR_WIDTH - "3" - - - C_MEM_BASEPARTNO - "" - - - C_MEM_CAS_LATENCY - "6" - - - C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS - "CLASS_II" - - - C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS - "CLASS_II" - - - C_MEM_DDR1_2_ODS - "FULL" - - - C_MEM_DDR2_3_HIGH_TEMP_SR - "NORMAL" - - - C_MEM_DDR2_3_PA_SR - "FULL" - - - C_MEM_DDR2_DIFF_DQS_EN - "YES" - - - C_MEM_DDR2_RTT - "150OHMS" - - - C_MEM_DDR3_AUTO_SR - "ENABLED" - - - C_MEM_DDR3_CAS_LATENCY - "6" - - - C_MEM_DDR3_CAS_WR_LATENCY - "5" - - - C_MEM_DDR3_ODS - "DIV6" - - - C_MEM_DDR3_RTT - "DIV4" - - - C_MEM_MDDR_ODS - "FULL" - - - C_MEM_MOBILE_PA_SR - "FULL" - - - C_MEM_NUM_COL_BITS - "10" - - - C_MEM_PARTNO - "MT41J64M16XX-187E" - - - C_MEM_TRAS - "-1" - - - C_MEM_TRCD - "-1" - - - C_MEM_TREFI - "-1" - - - C_MEM_TRFC - "-1" - - - C_MEM_TRP - "-1" - - - C_MEM_TRTP - "-1" - - - C_MEM_TWR - "-1" - - - C_MEM_TWTR - "-1" - - - C_MEM_TYPE - "DDR3" - - - C_MEM_TZQINIT_MAXCNT - "512" - - - C_MEMCLK_PERIOD - "0" - - - C_NUM_DQ_PINS - "16" - - - C_PORT_CONFIG - "B32_B32_B32_B32" - - - C_S0_AXI_ADDED_AXI_PARAMS - "TRUE" - - - C_S0_AXI_ADDR_WIDTH - "32" - - - C_S0_AXI_AXI_VER - "1.02.a" - - - C_S0_AXI_BASEADDR - "0x80000000" - - - C_S0_AXI_DATA_WIDTH - "32" - - - C_S0_AXI_ENABLE - "1" - - - C_S0_AXI_ENABLE_AP - "0" - - - C_S0_AXI_HIGHADDR - "0x807FFFFF" - - - C_S0_AXI_ID_WIDTH - "3" - - - C_S0_AXI_PROTOCOL - "AXI4" - - - C_S0_AXI_REG_EN0 - "0x00000" - - - C_S0_AXI_REG_EN1 - "0x01000" - - - C_S0_AXI_STRICT_COHERENCY - "0" - - - C_S0_AXI_SUPPORTS_NARROW_BURST - "Auto" - - - C_S0_AXI_SUPPORTS_READ - "1" - - - C_S0_AXI_SUPPORTS_WRITE - "1" - - - C_S1_AXI_ADDED_AXI_PARAMS - "TRUE" - - - C_S1_AXI_ADDR_WIDTH - "32" - - - C_S1_AXI_AXI_VER - "1.01.a" - - - C_S1_AXI_BASEADDR - "0xFFFFFFFF" - - - C_S1_AXI_DATA_WIDTH - "32" - - - C_S1_AXI_ENABLE - "0" - - - C_S1_AXI_ENABLE_AP - "0" - - - C_S1_AXI_HIGHADDR - "0x00000000" - - - C_S1_AXI_ID_WIDTH - "4" - - - C_S1_AXI_PROTOCOL - "AXI4" - - - C_S1_AXI_REG_EN0 - "0x00000" - - - C_S1_AXI_REG_EN1 - "0x01000" - - - C_S1_AXI_STRICT_COHERENCY - "1" - - - C_S1_AXI_SUPPORTS_NARROW_BURST - "Auto" - - - C_S1_AXI_SUPPORTS_READ - "1" - - - C_S1_AXI_SUPPORTS_WRITE - "1" - - - C_S2_AXI_ADDED_AXI_PARAMS - "TRUE" - - - C_S2_AXI_ADDR_WIDTH - "32" - - - C_S2_AXI_AXI_VER - "1.01.a" - - - C_S2_AXI_BASEADDR - "0xFFFFFFFF" - - - C_S2_AXI_DATA_WIDTH - "32" - - - C_S2_AXI_ENABLE - "0" - - - C_S2_AXI_ENABLE_AP - "0" - - - C_S2_AXI_HIGHADDR - "0x00000000" - - - C_S2_AXI_ID_WIDTH - "4" - - - C_S2_AXI_PROTOCOL - "AXI4" - - - C_S2_AXI_REG_EN0 - "0x00000" - - - C_S2_AXI_REG_EN1 - "0x01000" - - - C_S2_AXI_STRICT_COHERENCY - "1" - - - C_S2_AXI_SUPPORTS_NARROW_BURST - "Auto" - - - C_S2_AXI_SUPPORTS_READ - "1" - - - C_S2_AXI_SUPPORTS_WRITE - "1" - - - C_S3_AXI_ADDED_AXI_PARAMS - "TRUE" - - - C_S3_AXI_ADDR_WIDTH - "32" - - - C_S3_AXI_AXI_VER - "1.01.a" - - - C_S3_AXI_BASEADDR - "0xFFFFFFFF" - - - C_S3_AXI_DATA_WIDTH - "32" - - - C_S3_AXI_ENABLE - "0" - - - C_S3_AXI_ENABLE_AP - "0" - - - C_S3_AXI_HIGHADDR - "0x00000000" - - - C_S3_AXI_ID_WIDTH - "4" - - - C_S3_AXI_PROTOCOL - "AXI4" - - - C_S3_AXI_REG_EN0 - "0x00000" - - - C_S3_AXI_REG_EN1 - "0x01000" - - - C_S3_AXI_STRICT_COHERENCY - "1" - - - C_S3_AXI_SUPPORTS_NARROW_BURST - "Auto" - - - C_S3_AXI_SUPPORTS_READ - "1" - - - C_S3_AXI_SUPPORTS_WRITE - "1" - - - C_S4_AXI_ADDED_AXI_PARAMS - "TRUE" - - - C_S4_AXI_ADDR_WIDTH - "32" - - - C_S4_AXI_AXI_VER - "1.01.a" - - - C_S4_AXI_BASEADDR - "0xFFFFFFFF" - - - C_S4_AXI_DATA_WIDTH - "32" - - - C_S4_AXI_ENABLE - "0" - - - C_S4_AXI_ENABLE_AP - "0" - - - C_S4_AXI_HIGHADDR - "0x00000000" - - - C_S4_AXI_ID_WIDTH - "4" - - - C_S4_AXI_PROTOCOL - "AXI4" - - - C_S4_AXI_REG_EN0 - "0x00000" - - - C_S4_AXI_REG_EN1 - "0x01000" - - - C_S4_AXI_STRICT_COHERENCY - "1" - - - C_S4_AXI_SUPPORTS_NARROW_BURST - "Auto" - - - C_S4_AXI_SUPPORTS_READ - "1" - - - C_S4_AXI_SUPPORTS_WRITE - "1" - - - C_S5_AXI_ADDED_AXI_PARAMS - "TRUE" - - - C_S5_AXI_ADDR_WIDTH - "32" - - - C_S5_AXI_AXI_VER - "1.01.a" - - - C_S5_AXI_BASEADDR - "0xFFFFFFFF" - - - C_S5_AXI_DATA_WIDTH - "32" - - - C_S5_AXI_ENABLE - "0" - - - C_S5_AXI_ENABLE_AP - "0" - - - C_S5_AXI_HIGHADDR - "0x00000000" - - - C_S5_AXI_ID_WIDTH - "4" - - - C_S5_AXI_PROTOCOL - "AXI4" - - - C_S5_AXI_REG_EN0 - "0x00000" - - - C_S5_AXI_REG_EN1 - "0x01000" - - - C_S5_AXI_STRICT_COHERENCY - "1" - - - C_S5_AXI_SUPPORTS_NARROW_BURST - "Auto" - - - C_S5_AXI_SUPPORTS_READ - "1" - - - C_S5_AXI_SUPPORTS_WRITE - "1" - - - C_SIMULATION - "FALSE" - - - C_SKIP_IN_TERM_CAL - "0" - - - C_SKIP_IN_TERM_CAL_VALUE - "NONE" - - - C_SYS_RST_PRESENT - "1" - - - HW_VER - "1.02.a" - - - INSTANCE - "MCB_DDR3" - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/bitinit.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/bitinit.opt deleted file mode 100644 index 7d88d37d7..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/bitinit.opt +++ /dev/null @@ -1 +0,0 @@ - -p xc6slx45tfgg484-3 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_globals.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_globals.xsl deleted file mode 100644 index 9249c08a9..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_globals.xsl +++ /dev/null @@ -1,263 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> - - - - - - - - - - - document($P_SYSTEM_XML) - / - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - document($P_GROUPS_XML) - / - - - - - - - - - - - - - - - - - - - FOCUSED MASTERS SPECIFIED - - - - - FOCUSED MASTER BIF . = - - - - - - - - - - FOCUSED PERIPHERAL BRIDGE - - - - - - FOCUSED PERIPHERAL BRIDGE - - - - - - - - - - - FOCUSED PERIPHERAL has memory ranges - - - - FOCUSED PERIPHERAL BUS - - - - - - - - - - FOCUSED BUSSES SPECIFIED - - - - - - FOCUSED BUS - - - - - - - - TRUE - FALSE - - - - - - - - Bus - Debug - Memory - Memory Controller - Interrupt Controller - Peripheral - Processor - Bus Bridge - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRUE - FALSE - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view.xsl deleted file mode 100644 index b0fee7aa9..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view.xsl +++ /dev/null @@ -1,245 +0,0 @@ - - - - - - - - - - - - -]> - - - - - - - - - - - - - - - - - - - - - - - - - - - SAV VIEW - SAV MODE - SAV SCOPE - - - - - EDW2SAV XTELLER ERROR: UNDEFINED VIEW - - - - EDW2SAV XTELLER ERROR: UNDEFINED MODE - - - - EDW2SAV XTELLER ERROR: UNDEFINED SCOPE - - - - EDW2SAV XTELLER ERROR: SYSTEM XML UNDEFINED - - - - EDW2SAV XTELLER ERROR: EDKSYSTEM MISSING in SYSTEM XML - - - - EDW2SAV XTELLER ERROR: GROUP XML UNDEFINED for FOCUS - - - - EDW2SAV XTELLER ERROR: GROUP XML UNDEFINED for SCOPE - - - - - - SYSTEM XML - GROUPS XML - - - - - TREE - - - - - - - - - PROJECT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ERROR during SAV XTeller generation with panel and display mode - - - - - - - - - - - - - - - - TRUE - FALSE - - - - - - - - TREE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ERROR during SAV XTeller generation with panel and display mode - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_addr.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_addr.xsl deleted file mode 100644 index 5e8d06cb4..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_addr.xsl +++ /dev/null @@ -1,894 +0,0 @@ - - - - - - - - - - - - -]> - - - - - - - - - - - - - - - - - 's Address Map - - - - - - - MODULE - - - - - - INSTANCE - - Instance - STATIC - - - - - - : - - - - - - - - .: - - - : - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Connected - - - - - - TRUE - FALSE - - - - - STATIC - TEXTBOX - - - - - - - - - - - - - - - - - - - - - - - - - - - DROPDOWN - STATIC - DROPDOWN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : - - - - - - - : - - - - - - - - - - - - Not Applicable - Not Connected - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : - : - - - - - - - - - - - - - - - TRUE - FALSE - - - - - STATIC - TEXTBOX - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DROPDOWN - STATIC - DROPDOWN - - - - - - - - - - - - - - - : - - - - - - - - - - : - - - - - - - - - Not Connected - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 's Address Map - - - - - - - - - - - : - - - - - ADDRESS ID - - - - - .: - - - : - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Connected - - - - - - TRUE - FALSE - - - - - STATIC - TEXTBOX - - - - - - - - - - - - - - - - - - - - - - - - - - - - DROPDOWN - STATIC - DROPDOWN - - - - - - - - - - - - - - - - - - : - - - - - - - - - - : - - - - - - - - - - - - - - Not Applicable - Not Connected - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : - : - - - - - - - - - - - - - - - TRUE - FALSE - - - - - STATIC - TEXTBOX - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DROPDOWN - STATIC - DROPDOWN - - - - - - - - - - - - - - - : - - - - - - - - - - : - - - - - - - - - Not Connected - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_busif.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_busif.xsl deleted file mode 100644 index 97adb0df8..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_busif.xsl +++ /dev/null @@ -1,631 +0,0 @@ - - - - - - - - - - - - -]> - - - - - - - - - - - - - - - - MODULE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BUSINTERFACE - - - - - TRUE - - - TRUE - - - - - - - - STATIC - Bus Standard - BUSSTD - - - - - - - - - - - - USER - - - - - - - - TEXTBOX - Bus Name - BUSNAME - - - _ - - - - - - - - - - - - - - - - - - - - - - BUTTON - - - DROPDOWN - - - Bus Name - BUSNAME - No Connection - - - - - - - - - - - - - - - - DROPDOWN - Bus Name - BUSNAME - - - - - - - - - - - - - - - BUTTON - - - DROPDOWN - - - BUSNAME - Bus Name - - - & - - - - - - - - - - - - - - - - - - - DROPDOWN - Bus Name - BUSNAME - - - - - - - - - - - - - - - - - - - - - - - - - - - $moduleRef_/BUSINTERFACES - $moduleRef_ - - - - - - - - - - - - - - - - - - - - - - - - - BUSINTERFACE - - - - - TRUE - - - TRUE - - - - - - - - - - - - - - - - - - - - - - STATIC - Bus Standard - BUSSTD - - - - - - - - - USER - - - - - - - - TEXTBOX - Bus Name - BUSNAME - - - _ - - - - - - - - - - - - - - - - - - - - - - BUTTON - - - DROPDOWN - - - Bus Name - BUSNAME - No Connection - - - - - - - - - - - - - - - - - DROPDOWN - Bus Name - BUSNAME - - - - - - - - - - - - - - - BUTTON - - - DROPDOWN - - - BUSNAME - Bus Name - - - & - - - - - - - - - - - - - - - - - - - DROPDOWN - Bus Name - BUSNAME - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_groups.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_groups.xsl deleted file mode 100644 index e302f3a23..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_groups.xsl +++ /dev/null @@ -1,1447 +0,0 @@ - - - - - - - - - - - - - -]> - - - - - - - - - - - - - - - - - - - - - - -Focusing on busses - - - - - - MODULES WITH POTENTIAL CONNECTIONS TO FOCUSED BUS - SEPARATOR - - Name - STATIC - Name - POTENTIAL MODULES BELOW HERE - - - IP Type - STATIC - MODTYPE - - - - IP Version - STATIC - HWVERSION - - - - IP Classification - STATIC - IPCLASS - - - - Bus Name - - BUSNAME - - - - Type - STATIC - TYPE - - - - Bus Standard - STATIC - BUSSTD - - - - - - - - - - - - - - - - - MODULES WITH POTENTIAL CONNECTIONS TO THIS SUBSYSTEM - SEPARATOR - - Name - STATIC - Name - POTENTIAL MODULES BELOW HERE - - - IP Type - STATIC - MODTYPE - - - - IP Version - STATIC - HWVERSION - - - - IP Classification - STATIC - IPCLASS - - - - Bus Name - - BUSNAME - - - - Type - STATIC - TYPE - - - - Bus Standard - - STATIC - BUSSTD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLACING BUS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CONNECTED MASTER GROUP - - - - - - - POTENTIAL MASTER GROUP - - - - - - - - - SHARED GROUP - - - - - - - - - - - - - - - - - - - - - MEMORY GROUP - - - - - - - - - - PERIPHERAL GROUP - - - - - - - - SLAVE GROUP - - - - - - - - IP GROUP - - - - - - - FLOATING GROUP - - - - - - - IGNORING - - - - - - - - - - - - - - - - PLACING BUS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PERI PROCESSOR - - - - - - - PLACING MEMORY - - - - - - - - - - PLACING POTENTIAL GROUP OF PERIPHERALS - - - - - - - - PLACING POTENTIAL GROUP OF SLAVES - - - - - - - IGNORING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLACING MODULE ON BUS - - - - - - - MODULE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - __NONE__ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - EXAMINING CONNECTED MODULE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CONNECTED BIFS - POTENTIAL BIFS - IS PERIPHERAL - - PLACING MODULE - - - - - - MODULE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - EXAMINING POTENTIAL MODULE - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BUS has bifs - - - - - - - - - - - - - - - - - - - - - connected BIFS - potential bifs - unfocused bifs - is a peripheral - - - PLACING POTENTIAL MODULE - - - - - - MODULE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - EXAMINING CONNECTED INTERFACE . - - - - - - - - - - - - - - - . - PROC CONNECTIONS - MAST CONNECTIONS - PERI CONNECTIONS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CONNECTED SCOPE - POTENTIAL SCOPE - - - - TRUE - TRUE - TRUE - FALSE - - - - - PLACING CONNECTED INTERFACE . - - - - - __NONE__ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - EXAMINING POTENTIAL INTERFACE . - - - - - - - - - - - - - - - PROC CONNECTIONS - MAST CONNECTIONS - PERI CONNECTIONS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRUE - TRUE - TRUE - FALSE - - - - - - - __NONE__ - - - - - PLACING POTENTIAL INTERFACE . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PROJECT - BUSINTERFACE - TREE - - - - - - - - - - PLACING BUS - - - - - - - - - - - - MODULE - - Name - TEXTBOX - INSTANCE - - - - IP Type - STATIC - MODTYPE - - - - IP Version - STATIC - HWVERSION - - - - IP Classification - STATIC - IPCLASS - BUS - - - - - - - - - - - - - - - - - - MODULE - - - Name - TEXTBOX - INSTANCE - - - - IP Type - STATIC - MODTYPE - - - - IP Version - STATIC - HWVERSION - - - - IP Classification - STATIC - IPCLASS - - - - - - - - - - PLACING BIF - TYPE - BUS - - - - TEXTBOX - BUTTON - BUTTON - BUTTON - DROPDOWN - - - - - - & - - - - - - - VIEWTYPE - BUSNAME - - - BUSINTERFACE - - NAME - STATIC - NAME - - - - Bus Name - - BUSNAME - - - - Type - STATIC - TYPE - - - - Bus Standard - STATIC - BUSSTD - - - - - - - - - - PROCESSOR GROUP - - - - - GROUP - - NAME - STATIC - INSTANCE - Subsystem of - - - - - - - - - - MASTER GROUP - - - - - GROUP - - NAME - STATIC - INSTANCE - Subsystem of - - - - - - - - - - - PLACING SHARED PERIPHERALS - - - GROUP - - NAME - STATIC - INSTANCE - Peripherals shared by - - - - - - - - - PLACING MEMORY - - - - GROUP - - NAME - STATIC - INSTANCE - (Memory) - - - - - - - - - PLACING PERIPHERAL - - - - - - - PLACING SLAVES - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_port.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_port.xsl deleted file mode 100644 index 5cfc3be61..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view_port.xsl +++ /dev/null @@ -1,771 +0,0 @@ - - - - - - - - - - - - -]> - - - - - - - - - - - - - WRITING PORT in MODE : - - - - - - - - - - - - - - - - - - - - - - - - ExternalPorts - MODULE - - - - - Name - External Ports - Name - STATIC - - - - - - - - - PORT - - - - - - - - - - - - - - - - [:] - - - - [:] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRUE - TRUE - FALSE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - __NONE__ - - - - - - - - __NONE__ - - - - - - - __NONE__ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - __NONE__ - - - - - - - - __NONE__ - - - - - - - __NONE__ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Connected to BUS - Connected to External Ports - Not connected to BUS or External Ports - - - - - - - - BUSINTERFACE.PORTS - - - TRUE - - - - - - - - - - - - - - - - - - - __NONE__ - - - - - - - - __NONE__ - - - - - - - __NONE__ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Connected to External Ports - Not connected to External Ports - - - - - - - IOINTERFACE.PORTS - - - TRUE - - - - - - - - - - - - - - - - - - - - - __NONE__ - - - - - - - - __NONE__ - - - - - - - __NONE__ - - - - - - - - - - - - - - - - - - - - - - - - - WRITING PORT MODE - - - - - - - - - - - - - - - - - - - - - - - - - - - TRUE - FALSE - - - - - - - - - - [:] - - - - [:] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRUE - TRUE - FALSE - - - - - - - - - - has valid ports - - - - - - - - - - - - FALSE - TRUE - TRUE - FALSE - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRUE - FALSE - - - - - TRUE - TRUE - TRUE - FALSE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRUE - FALSE - - - - - TRUE - TRUE - TRUE - FALSE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/gensav_cmd.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/gensav_cmd.xml deleted file mode 100644 index 42f1efa6c..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/gensav_cmd.xml +++ /dev/null @@ -1,2 +0,0 @@ - - \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport deleted file mode 100644 index 222336916..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport +++ /dev/null @@ -1,218 +0,0 @@ - - -
- 2011-08-27T15:17:50 - system - 2011-08-27T15:17:49 - C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport - filter.filter - C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise - 2011-08-26T19:44:45 - false -
- - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/xmsgprops.lst b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/xmsgprops.lst deleted file mode 100644 index 10c9bb7ac..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/xmsgprops.lst +++ /dev/null @@ -1,3 +0,0 @@ -MessageCaptureEnabled: TRUE -MessageFilteringEnabled: FALSE -IncrementalMessagingEnabled: TRUE diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/platgen.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/platgen.opt deleted file mode 100644 index 14ffabbc8..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/platgen.opt +++ /dev/null @@ -1,2 +0,0 @@ - -p xc6slx45tfgg484-3 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst -ethernet Hardware_Evaluation diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/simgen.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/simgen.opt deleted file mode 100644 index 9fbb0051c..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/simgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p spartan6 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst -s isim diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml deleted file mode 100644 index 86498813d..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml +++ /dev/null @@ -1,5757 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Interconnect - AXI4 Memory-Mapped Interconnect - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Interconnect - AXI4 Memory-Mapped Interconnect - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MicroBlaze - The MicroBlaze 32 bit soft processor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Local Memory Bus (LMB) 1.0 - 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Local Memory Bus (LMB) 1.0 - 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMB BRAM Controller - Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMB BRAM Controller - Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Block RAM (BRAM) Block - The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Processor System Reset Module - Reset management module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Clock Generator - Clock generator for processor system. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MicroBlaze Debug Module (MDM) - Debug module for MicroBlaze Soft Processor. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI UART (Lite) - Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI. - - - - - - - - - - - - - - - - - - - - - - - - - Serial Data Out - - - Serial Data In - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI General Purpose IO - General Purpose Input/Output (GPIO) core for the AXI bus. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GPIO1 Data IO - - - GPIO2 Data IO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI General Purpose IO - General Purpose Input/Output (GPIO) core for the AXI bus. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GPIO1 Data IO - - - GPIO2 Data IO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI S6 Memory Controller(DDR/DDR2/DDR3) - Spartan-6 memory controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Ethernet - AXI Ethernet MAC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI DMA Engine - AXI MemoryMap to/from AXI Stream Direct Memory Access Engine - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Interrupt Controller - intc core attached to the AXI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Interrupt Request Output - - - - - - - - - - - - Interrupt Inputs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AXI Timer/Counter - Timer counter with AXI interface - - - - - - - - - - - - - - - - - - - - - - - Capture Trig 0 - - - Capture Trig 1 - - - Generate Out 0 - - - Generate Out 1 - - - Pulse Width Modulation 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/xplorer.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/xplorer.opt deleted file mode 100644 index 1ba7dad07..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/xplorer.opt +++ /dev/null @@ -1 +0,0 @@ - -device xc6slx45tfgg484-3 data/system.ucf 7 0 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/xpsxflow.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/xpsxflow.opt deleted file mode 100644 index 51c612843..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/xpsxflow.opt +++ /dev/null @@ -1 +0,0 @@ - -device xc6slx45tfgg484-3 data/system.ucf 0 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/data/system.ucf b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/data/system.ucf deleted file mode 100644 index 345fc68c1..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/data/system.ucf +++ /dev/null @@ -1,356 +0,0 @@ -# -# pin constraints -# -NET CLK_N LOC = "K22" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; -NET CLK_P LOC = "K21" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; -NET ETHERNET_MDC LOC = "R19" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_MDIO LOC = "V20" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_MII_TX_CLK LOC = "L20" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_PHY_RST_N LOC = "J22" | IOSTANDARD = "LVCMOS25" | TIG; -NET ETHERNET_RXD[0] LOC = "P19" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[1] LOC = "Y22" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[2] LOC = "Y21" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[3] LOC = "W22" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[4] LOC = "W20" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[5] LOC = "V22" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[6] LOC = "V21" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[7] LOC = "U22" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RX_CLK LOC = "P20" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RX_DV LOC = "T22" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RX_ER LOC = "U20" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[0] LOC = "U10" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[1] LOC = "T10" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[2] LOC = "AB8" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[3] LOC = "AA8" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[4] LOC = "AB9" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[5] LOC = "Y9" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[6] LOC = "Y12" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[7] LOC = "W12" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TX_CLK LOC = "AB7" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TX_EN LOC = "T8" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TX_ER LOC = "U8" | IOSTANDARD = "LVCMOS25"; -NET LEDs_4Bits_TRI_O[0] LOC = "D17" | IOSTANDARD = "LVCMOS25"; -NET LEDs_4Bits_TRI_O[1] LOC = "AB4" | IOSTANDARD = "LVCMOS25"; -NET LEDs_4Bits_TRI_O[2] LOC = "D21" | IOSTANDARD = "LVCMOS25"; -NET LEDs_4Bits_TRI_O[3] LOC = "W15" | IOSTANDARD = "LVCMOS25"; -NET Push_Buttons_4Bits_TRI_I[0] LOC = "F3" | IOSTANDARD = "LVCMOS25"; -NET Push_Buttons_4Bits_TRI_I[1] LOC = "G6" | IOSTANDARD = "LVCMOS25"; -NET Push_Buttons_4Bits_TRI_I[2] LOC = "F5" | IOSTANDARD = "LVCMOS25"; -NET Push_Buttons_4Bits_TRI_I[3] LOC = "C1" | IOSTANDARD = "LVCMOS25"; -NET RESET LOC = "H8" | IOSTANDARD = "LVCMOS15" | TIG; -NET RS232_Uart_1_sin LOC = "H17" | IOSTANDARD = "LVCMOS25"; -NET RS232_Uart_1_sout LOC = "B21" | IOSTANDARD = "LVCMOS25"; -# -# additional constraints -# - -NET "CLK" TNM_NET = sys_clk_pin; -TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; -###### Soft ETHERNET -# This is a GMII system -# AXI_STR_*_ACLK is not the same as S_AXI_ACLK from clock generator -# Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods -# Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency -# allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB, -# the constraints are over constrained. Relaxing them for your system may reduce build time. - -NET "*ETHERNET*/S_AXI_ACLK" TNM_NET = "axi4lite_clk"; -NET "*ETHERNET*/AXI_STR_TXD_ACLK" TNM_NET = "axistream_clk"; -NET "*ETHERNET*/AXI_STR_TXC_ACLK" TNM_NET = "axistream_clk"; -NET "*ETHERNET*/AXI_STR_RXD_ACLK" TNM_NET = "axistream_clk"; -NET "*ETHERNET*/AXI_STR_RXS_ACLK" TNM_NET = "axistream_clk"; - -############################################################ -# Clock Period Constraints # -############################################################ - -############################################################ -# RX Clock period Constraints # -############################################################ -# Ethernet GMII PHY-side receive clock -# __________ -# | | -# --- GMII_RX_CLK-----| BUFR |---Rx_Client_Clk -# |__________| -# -# Receiver clock period constraints: please do not relax -# Changed NET name -# Changed TNM_NET name from CoreGen name to be consistent in -# EDK constraints -# NET "*/rx_gmii_clk_int" TNM_NET = "clk_rx"; -NET "*/GMII_RX_CLK" TNM_NET = "phy_clk_rx"; -# Added TIMEGRP for later DATAPATHONLY constraint -TIMEGRP "rx_clock" = "phy_clk_rx"; -TIMESPEC "TS_rx_clk" = PERIOD "rx_clock" 8000 ps HIGH 50 %; - -############################################################ -# TX Clock period Constraints # -############################################################ -############################################################ -# TIG for BUFGMUX SPEED CLK: please do not edit # -############################################################ -# Want to TIG any timing paths to the select of the TX clock BUFGMUXs -# at this point and subsequent constraints can override. MII_TX_CLK -# will remained TIG so that path is not used in any setup/hold timing -# analysis. -# Changed net name in synthesis of axi_ethernet -# PIN "*clock_inst*BUFGMUX*.I?" TNM="clk_bufgmux"; -PIN "*I_CLOCK_INST*/*BUFGMUX_SPEED_CLK.I?" TNM="clk_bufgmux"; -TIMESPEC "TS_bufgmux" = FROM "async_config" TO "clk_bufgmux" TIG; - -############################################################################### -# The following two TimeSpecs are from CoreGen Ethernet Core Example Design UCF -# file. In systems GTX_CLK is driven by clock generator core, then the derived -# period constraint will override these TimeSpecs. -############################################################################### -# Ethernet GTX_CLK high quality 125 MHz reference clock -# __________ -# -GTX_CLK------------| | -# | BUFGMUX |---Tx_Client_Clk -# -MII_TX_CLK---------|__________| -# -# Depending on system configuration, the analysis tool may use either gtx_clk -# or tx_client_clk so both nets are used in defining PERIOD constraint and -# TNM_NETS for subsequent constraints. -# The PERIOD constraints may not be analyzed if inferred clock generator -# constraints are generated for the system. - -# Transmitter clock period constraints: please do not relax -# Changed NET name -# NET "gtx_clk*" TNM_NET = "clk_gtx"; -NET "*/GTX_CLK" TNM_NET = "clk_gtx"; -# Added TIMEGRP for later DATAPATHONLY constraint -TIMEGRP "gtx_clock" = "clk_gtx"; -TIMESPEC "TS_gtx_clk" = PERIOD "gtx_clock" 8000 ps HIGH 50 %; - -# Changed NET name -# Changed TNM_NET name from CoreGen name to be consistent in -# EDK constraints -# NET "*tx_gmii_clk" TNM_NET = "clk_tx_gmii"; -NET "*/GMII.tx_gmii_clk_int" TNM_NET = "phy_clk_tx"; -TIMEGRP "tx_clock_gmii" = "phy_clk_tx"; -TIMESPEC "TS_tx_clk_gmii" = PERIOD "tx_clock_gmii" 8000 ps HIGH 50 %; - -############################################################ -# Host Clock period Constraint # -############################################################ -# Management Clock period constraints: relax as required -# Changed NET name -# NET "host_clk" TNM_NET = "host"; -NET "*/S_AXI_ACLK" TNM_NET = "host_clk"; -TIMEGRP "host" = "host_clk" EXCEPT "mdio_logic"; -TIMESPEC "TS_host_clk" = PERIOD "host" 10000 ps HIGH 50 % PRIORITY 10; - -############################################################ -# External GMII Constraints # -############################################################ -# GMII Transmitter Constraints: place flip-flops in IOB -# Changed 'true' to 'force' -# Shortened INST names to remove internal hierarchy -# INST "*trimac_block*gmii_interface*gmii_txd*" IOB = true; -# INST "*trimac_block*gmii_interface*gmii_tx_en" IOB = true; -# INST "*trimac_block*gmii_interface*gmii_tx_er" IOB = true; -INST "*gmii_txd*" IOB = force; -INST "*gmii_tx_en" IOB = force; -INST "*gmii_tx_er" IOB = force; - -# GMII Receiver Constraints: place flip-flops in IOB -# Changed 'true' to 'force' -# Shortened INST names to remove internal hierarchy -# INST "*trimac_block*gmii_interface*rxd_to_mac*" IOB = true; -# INST "*trimac_block*gmii_interface*rx_dv_to_mac" IOB = true; -# INST "*trimac_block*gmii_interface*rx_er_to_mac" IOB = true; -INST "*rxd_to_mac*" IOB = force; -INST "*rx_dv_to_mac" IOB = force; -INST "*rx_er_to_mac" IOB = force; - -############################################################ -# The following are required to maximize setup/hold # -############################################################ -# Changed to add Drive strength and INST Name -# INST "gmii_txd" SLEW = FAST; -# INST "gmii_tx_en" SLEW = FAST; -# INST "gmii_tx_er" SLEW = FAST; -# INST "gmii_tx_clk" SLEW = FAST; -INST "ETHERNET_TXD_?_OBUF" SLEW = FAST; -INST "ETHERNET_TX_EN_OBUF" SLEW = FAST; -INST "ETHERNET_TX_ER_OBUF" SLEW = FAST; -INST "ETHERNET_TX_CLK_OBUF" SLEW = FAST; - -############################################################ -# GMII: IODELAY Constraints # -############################################################ -# Please modify the value of the IDELAY_VALUE -# according to your design. -# For more information on IDELAYCTRL and IODELAY, please -# refer to the Spartan-6 User Guide. -# -INST "*delay_gmii_rx_dv" IDELAY_VALUE = 6; -INST "*delay_gmii_rx_er" IDELAY_VALUE = 6; -INST "*data_bus[0].delay_gmii_rxd" IDELAY_VALUE = 6; -INST "*data_bus[1].delay_gmii_rxd" IDELAY_VALUE = 6; -INST "*data_bus[2].delay_gmii_rxd" IDELAY_VALUE = 6; -INST "*data_bus[3].delay_gmii_rxd" IDELAY_VALUE = 6; -INST "*data_bus[4].delay_gmii_rxd" IDELAY_VALUE = 6; -INST "*data_bus[5].delay_gmii_rxd" IDELAY_VALUE = 6; -INST "*data_bus[6].delay_gmii_rxd" IDELAY_VALUE = 6; -INST "*data_bus[7].delay_gmii_rxd" IDELAY_VALUE = 6; - -# Group IODELAY and IDELAYCTRL components to aid placement -# INST "*delay_gmii_rx_clk" IODELAY_GROUP = "grp1"; -INST "*delay_gmii_rx_dv" IODELAY_GROUP = "grp1"; -INST "*delay_gmii_rx_er" IODELAY_GROUP = "grp1"; -INST "*delay_gmii_rxd" IODELAY_GROUP = "grp1"; -# INST "*dlyctrl" IODELAY_GROUP = "grp1"; - -# Changed to let the tools pick the LOC -# INST *trimac_block*clock_inst*BUFGMUX_SPEED_CLK LOC = BUFGMUX_X3Y13; - -############################################################ -# For Setup and Hold time analysis on GMII inputs # -############################################################ -# Identify GMII Rx Pads only. -# This prevents setup/hold analysis being performed on false inputs, -# eg, the configuration_vector inputs. -# Changed to remove TNM and changed INST Names -# INST "gmii_rxd" TNM = IN_GMII; -# INST "gmii_rx_er" TNM = IN_GMII; -# INST "gmii_rx_dv" TNM = IN_GMII; - -# Define data valid window with respect to the clock. -# The spec states that, worst case, the data is valid 2 ns before the clock edge. -# The worst case it to provide zero hold time (a 2ns window in total) -# Changed to remove TIMEGRP -# TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "gmii_rx_clk"; -# Set to allow for 100ps setup/hold trace delay difference in relation to clock -OFFSET = IN 2.4 ns VALID 2.8 ns BEFORE "ETHERNET_RX_CLK"; - -############################################################ -# Crossing of Clock Domain Constraints: please do not edit # -############################################################ -# Flow Control logic reclocking - control signal is synchronised -# Changed net name in synthesis of axi_ethernet -# INST "*trimac_core*FLOW?RX_PAUSE?PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx"; -# INST "*trimac_core*FLOW?RX_PAUSE?PAUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx"; -INST "*/I_FLOW/I_RX_PAUSE/PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx"; -INST "*/I_FLOW/I_RX_PAUSE/PAUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx"; -TIMESPEC "TS_flow_rx_to_tx" = FROM "flow_rx_to_tx" TO phy_clk_tx 8000 ps DATAPATHONLY; - -# Generate a group of all flops NOT in the host clock domain -TIMEGRP "all_ffs" = FFS; -TIMEGRP "ffs_except_host" = "all_ffs" EXCEPT "host"; - -# Configuration Register reclocking -# Changed net name in synthesis of axi_ethernet -# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?RX0_OUT*" TNM="async_config"; -# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?RX1_OUT*" TNM="async_config"; -# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?FC_OUT_29" TNM="async_config"; -INST "*/MANIFGEN.I_MANAGEN/I_CONF/RX0_OUT*" TNM="async_config"; -INST "*/MANIFGEN.I_MANAGEN/I_CONF/RX1_OUT*" TNM="async_config"; -INST "*/MANIFGEN.I_MANAGEN/I_CONF/FC_OUT_29" TNM="async_config"; - -# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?TX_OUT*" TNM="async_config"; -# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?FC_OUT_30" TNM="async_config"; -INST "*/MANIFGEN.I_MANAGEN/I_CONF/TX_OUT*" TNM="async_config"; -INST "*/MANIFGEN.I_MANAGEN/I_CONF/FC_OUT_30" TNM="async_config"; - -# Speed change config -# Changed net name in synthesis of axi_ethernet -# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?CNFG_SPEED*" TNM="async_config"; -# INST "*trimac_core*SPEED_IS*" TNM="async_config"; -INST "*/MANIFGEN.I_MANAGEN/I_CONF/CNFG_SPEED*" TNM="async_config"; -INST "*/I_?XGEN/*SPEED*" TNM="async_config"; - -# Changed to comment out. -# In BSB systems the Host_clk = S_AXI_ACLK. Since the CORE Gen TIG'd constraints below -# are affecting axi_ethernet DATAPATHONLY constraints above (at start of Soft_Ethernet_MAC constraints) -# these paths are commented out in favor of using the DATAPATHONLY constraints. The constraints are: -# "TS_axi4lite_clk_clk_2_TX_CLIENT_CLK" and "TS_TX_CLIENT_CLK_2_axi4lite_clk_clk" -# TIMESPEC "TS_host_clk_to_rx_clk" = FROM "host" TO "rx_clock" TIG; -# TIMESPEC "TS_host_clk_to_tx_clk" = FROM "host" TO "tx_clock_gmii" TIG; - -TIMESPEC "TS_config_to_all" = FROM "async_config" TO "ffs_except_host" TIG; - -# Address filter specific cross clocking -# Changed net name in synthesis of axi_ethernet -# INST "*trimac_core*addr_filter_top/dynamic_af_gen.dynamic_config/unicast_addr_*" TNM="addr_config_to_rx"; -INST "*/I_ADDR_FILTER_TOP/dynamic_af_gen.I_DYNAMIC_CONFIG/unicast_addr_*" TNM="addr_config_to_rx"; -TIMESPEC "TS_addr_config_to_rx" = FROM "addr_config_to_rx" TO "ffs_except_host" TIG; - -############################################################ -# Ignore paths to resync flops # -############################################################ -# Changed to replace TIG with DATAPATHONLY constraints -# INST "*data_sync" TNM = "resync_reg"; -# TIMESPEC "ts_resync_flops" = TO "resync_reg" TIG; - -###################################################################### -# MDIO Constraints: please do not edit unless TS_host_clk is relaxed # -# in which case the multiplier needs to be adjusted to give the # -# required 400ns (or faster) # -###################################################################### - -# Place the MDIO logic in it's own timing groups -# Changed net name in synthesis of axi_ethernet -# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?ENABLE_REG" TNM = "mdio_logic"; -# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?READY_INT" TNM = "mdio_logic"; -# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?STATE_COUNT*" TNM = FFS "mdio_logic"; -# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?MDIO_TRISTATE" TNM = "mdio_logic"; -# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?MDIO_OUT" TNM = "mdio_logic"; -INST "*/I_RXGEN/ENABLE_REG" TNM = "mdio_logic"; -INST "*/MANIFGEN.I_MANAGEN/MIIM_READY_INT" TNM = "mdio_logic"; -INST "*/MANIFGEN.I_MANAGEN/I_PHY/STATE_COUNT*" TNM = FFS "mdio_logic"; -INST "*/MANIFGEN.I_MANAGEN/I_PHY/MDIO_TRISTATE" TNM = "mdio_logic"; -INST "*/MANIFGEN.I_MANAGEN/I_PHY/MDIO_OUT" TNM = "mdio_logic"; - -# The MDIO logic is constrained to a 400ns period. this is generated by relating the required -# period to that specified for host_clk. This ensures the two clocks are related timed -# correctly. -TIMESPEC "TS_mdio" = PERIOD "mdio_logic" "TS_host_clk" * 40 PRIORITY 0; - -############################################################ -# Crossing of Clock Domain Constraints: please do not edit # -# In addition to CoreGen constraints # -############################################################ - -# The following TimeSpecs are required only when AXILite clock differs from AXI-Stream clock -# Data path timing depends on the destination clock period -TIMESPEC "TS_axistreamclks_2_axi4liteclks" = FROM axistream_clk TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz -TIMESPEC "TS_axi4liteclks_2_axistreamclks" = FROM axi4lite_clk TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz - -# TNM_NET phy_clk_rx is rx_client_clk -# TIMESPECs for AXI streaming clock crossing to/from rx_client_clk -TIMESPEC "TS_axistreamclks_2_RX_CLIENT_CLK" = FROM axistream_clk TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz -TIMESPEC "TS_RX_CLIENT_CLK_2_axistreamclks" = FROM phy_clk_rx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz -# TIMESPECs for AXI-Lite clock crossing to/from tx_client_clk -TIMESPEC "TS_axi4liteclks_2_RX_CLIENT_CLK" = FROM axi4lite_clk TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz -TIMESPEC "TS_RX_CLIENT_CLK_2_axi4liteclks" = FROM phy_clk_rx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz - -# Depending on system configuration, the analysis tool may use either TNM_NET clk_gtx -# or TNM_NET phy_clk_tx so only one set will be analyzed -# TNM_NET phy_clk_tx is tx_client_clk -# TIMESPECs for AXI streaming clock crossing to/from tx_client_clk -TIMESPEC "TS_axistreamclks_2_TX_CLIENT_CLK" = FROM axistream_clk TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz -TIMESPEC "TS_TX_CLIENT_CLK_2_axistreamclks" = FROM phy_clk_tx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz -# TIMESPECs for AXI-Lite clock crossing to/from tx_client_clk -TIMESPEC "TS_axi4liteclks_2_TX_CLIENT_CLK" = FROM axi4lite_clk TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz -TIMESPEC "TS_TX_CLIENT_CLK_2_axi4liteclks" = FROM phy_clk_tx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz - -# TNM_NET clk_gtx is */GTX_CLK -# TIMESPECs for AXI Streaming clock crossing to/from */GTX_CLK -TIMESPEC "TS_axistreamclks_2_GTX_CLK" = FROM axistream_clk TO clk_gtx 8000 ps DATAPATHONLY; #assumes clk_gtx <= 125 MHz -TIMESPEC "TS_GTX_CLK_2_axistreamclks" = FROM clk_gtx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz -# TIMESPECs for AXI-Lite clock crossing to/from */GTX_CLK -TIMESPEC "TS_axi4lite_clk_2_GTX_CLK" = FROM axi4lite_clk TO clk_gtx 8000 ps DATAPATHONLY; #assumes clk_gtx <= 125 MHz -TIMESPEC "TS_GTX_CLK_2_axi4lite_clk" = FROM clk_gtx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz - -# Depending on system configuration, the analysis tool may use either TNM_NET clk_gtx -# or TNM_NET phy_clk_tx so only one set will be analyzed -# Rx Clock crossings - Some paths are analyzed by the TS_flow_rx_to_tx constraint also -# Needed since ts_resync_flops is commented out -TIMESPEC "TS_RX_CLIENT_CLK_2_TX_CLIENT_CLK" = FROM phy_clk_rx TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz -TIMESPEC "TS_TX_CLIENT_CLK_2_RX_CLIENT_CLK" = FROM phy_clk_tx TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz -TIMESPEC "TS_RX_CLIENT_CLK_2_GTX_CLK" = FROM phy_clk_rx TO clk_gtx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz -TIMESPEC "TS_GTX_CLK_2_RX_CLIENT_CLK" = FROM clk_gtx TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/bitgen.ut b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/bitgen.ut deleted file mode 100644 index bca21c81b..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/bitgen.ut +++ /dev/null @@ -1,3 +0,0 @@ --g TdoPin:PULLNONE --g StartUpClk:JTAGCLK -#add other options here. diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/download.cmd b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/download.cmd deleted file mode 100644 index da4d7717e..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/download.cmd +++ /dev/null @@ -1,6 +0,0 @@ -setMode -bscan -setCable -p auto -identify -assignfile -p 2 -file implementation/download.bit -program -p 2 -quit diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/fast_runtime.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/fast_runtime.opt deleted file mode 100644 index 994a6d2f8..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/fast_runtime.opt +++ /dev/null @@ -1,84 +0,0 @@ -FLOWTYPE = FPGA; -############################################################### -## Filename: fast_runtime.opt -## -## Option File For Xilinx FPGA Implementation Flow for Fast -## Runtime. -## -## Version: 4.1.1 -############################################################### -# -# Options for Translator -# -# Type "ngdbuild -h" for a detailed list of ngdbuild command line options -# -Program ngdbuild --p ; # Partname to use - picked from xflow commandline --nt timestamp; # NGO File generation. Regenerate only when - # source netlist is newer than existing - # NGO file (default) --bm .bmm # Block RAM memory map file -; # User design - pick from xflow command line --uc .ucf; # ucf constraints -.ngd; # Name of NGD file. Filebase same as design filebase -End Program ngdbuild - -# -# Options for Mapper -# -# Type "map -h " for a detailed list of map command line options -# -Program map --o _map.ncd; # Output Mapped ncd file --w; # Overwrite output files. --pr b; # Pack internal FF/latches into IOBs -#-fp .mfp; # Floorplan file --ol high; --timing; --detail; -.ngd; # Input NGD file -.pcf; # Physical constraints file -END Program map - -# -# Options for Post Map Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_map_trce --e 3; # Produce error report limited to 3 items per constraint -#-o _map.twr; # Output trace report file --xml _map.twx; # Output XML version of the timing report -#-tsi _map.tsi; # Produce Timing Specification Interaction report -_map.ncd; # Input mapped ncd -.pcf; # Physical constraints file -END Program post_map_trce - -# -# Options for Place and Route -# -# Type "par -h" for a detailed list of par command line options -# -Program par --w; # Overwrite existing placed and routed ncd --ol high; # Overall effort level -_map.ncd; # Input mapped NCD file -.ncd; # Output placed and routed NCD -.pcf; # Input physical constraints file -END Program par - -# -# Options for Post Par Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_par_trce --e 3; # Produce error report limited to 3 items per constraint -#-o .twr; # Output trace report file --xml .twx; # Output XML version of the timing report -#-tsi .tsi; # Produce Timing Specification Interaction report -.ncd; # Input placed and routed ncd -.pcf; # Physical constraints file -END Program post_par_trce - - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters deleted file mode 100644 index ec65f7de2..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters +++ /dev/null @@ -1,158 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui deleted file mode 100644 index b5e00b4d7..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui +++ /dev/null @@ -1,227 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.bsb b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.bsb deleted file mode 100644 index 85c9d7994..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.bsb +++ /dev/null @@ -1 +0,0 @@ -„æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Dbb\b\`bDv*„æÄ®Òôtt¦Êè„ÞÂäÈ@DðÒØÒÜð\ÆÞÚD@Dæàl`jD@D†Dv.„æÄ®ÒôttªàÈÂèʄÞÂäÈ@D‚¤†’¨Š†¨ª¤ŠD@DæàÂäèÂÜlDv.„æÄ®ÒôttªàÈÂèʄÞÂäÈ@DˆŠ¬’†Š¾¦’´ŠD@DðÆlæØðhjèDv'„æÄ®ÒôttªàÈÂèʄÞÂäÈ@D ‚†–‚ŽŠD@DÌÎÎhphDv'„æÄ®ÒôttªàÈÂèʄÞÂäÈ@D¤¦¨¾ ž˜‚¤’¨²D@DbDv&„æÄ®ÒôttªàÈÂèʄÞÂäÈ@D¦ ŠŠˆŽ¤‚ˆŠD@DZfDv%„æÄ®Òôtt¦Êè¦òæèÊÚ@DÚľÂðÒ¾bêàD@Db\`Dv;„æÄ®ÒôttªàÈÂèʦòæèÊÚ@D†ØÖ¾ŒäÊâD@Dd````````D@DÚÒÆäÞÄØÂôʾ`Dv@„æÄ®Òôtt‚ÈÈ äÞÆÊææÞä@DÚÒÆäÞÄØÂôʾ`D@DÚÒÆäÞÄØÂôÊD@DÚÒÆäÞÄØÂôʾ`DvH„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÈÂè¾ÆÂÆÐʾÚÊÚ¾ØÒæèD@Dš†„¾ˆˆ¤fDv@„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÈÂè¾ÆÂÆÐʾæÒôÊD@DpbrdDvI„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÒÜæèä¾ÆÂÆÐʾÚÊÚ¾ØÒæèD@Dš†„¾ˆˆ¤fDvA„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÒÜæèä¾ÆÂÆÐʾæÒôÊD@DpbrdDvH„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÚľÆØÞÆÖ¾ÌäÊâêÊÜÆòD@Db````````Dv>„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÚľÌàê¾ÊÜÂÄØÊD@D¨¤ªŠDvF„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôʾ`D@DÚľØÞÆÂؾÚÊÚÞäò¾æÒôÊD@DljjflDv?„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@DŠ¨Š¤œŠ¨D@DÂðÒ¾ÊèÐÊäÜÊèD@DÚÒÆäÞÄØÂôʾ`Dv;„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DŠ¨Š¤œŠ¨D@DÊèÐÊäÜÊè¾ÈÚ¾`D@D¨¤ªŠDv=„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DŠ¨Š¤œŠ¨D@DêæʾÒÜèÊääêàè¾ÒÈD@D¨¤ªŠDv=„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾h„ÒèæD@DÂðÒ¾ÎàÒÞD@DÚÒÆäÞÄØÂôʾ`Dv@„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾h„ÒèæD@DêæʾÒÜèÊääêàè¾ÒÈD@DŒ‚˜¦ŠDv>„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@Dš†„¾ˆˆ¤fD@DÂðÒ¾æl¾ÈÈäðD@DÚÒÆäÞÄØÂôʾ`DvE„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D êæо„êèèÞÜæ¾h„ÒèæD@DÂðÒ¾ÎàÒÞD@DÚÒÆäÞÄØÂôʾ`DvH„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D êæо„êèèÞÜæ¾h„ÒèæD@DêæʾÒÜèÊääêàè¾ÒÈD@DŒ‚˜¦ŠDvC„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäè¾bD@DÂðÒ¾êÂäèØÒèÊD@DÚÒÆäÞÄØÂôʾ`DvA„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DêÂäè¾`¾ÄÂêȾäÂèÊD@Drl``Dv>„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DêÂäè¾`¾ÈÂèÂîÒÈèÐD@DpDv>„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DêÂäè¾`¾àÂäÒèòD@DÜÞÜÊDvB„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DêæʾÒÜèÊääêàè¾ÒÈD@DŒ‚˜¦ŠDv \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.make b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.make deleted file mode 100644 index 87c158c23..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.make +++ /dev/null @@ -1,216 +0,0 @@ -################################################################# -# Makefile generated by Xilinx Platform Studio -# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetFull\PlatformStudioProject\system.xmp -# -# WARNING : This file will be re-generated every time a command -# to run a make target is invoked. So, any changes made to this -# file manually, will be lost when make is invoked next. -################################################################# - -# Name of the Microprocessor system -# The hardware specification of the system is in file : -# C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetFull\PlatformStudioProject\system.mhs - -include system_incl.make - -################################################################# -# PHONY TARGETS -################################################################# -.PHONY: dummy -.PHONY: netlistclean -.PHONY: bitsclean -.PHONY: simclean -.PHONY: exporttosdk - -################################################################# -# EXTERNAL TARGETS -################################################################# -all: - @echo "Makefile to build a Microprocessor system :" - @echo "Run make with any of the following targets" - @echo " " - @echo " netlist : Generates the netlist for the given MHS " - @echo " bits : Runs Implementation tools to generate the bitstream" - @echo " exporttosdk: Export files to SDK" - @echo " " - @echo " init_bram: Initializes bitstream with BRAM data" - @echo " ace : Generate ace file from bitstream and elf" - @echo " download : Downloads the bitstream onto the board" - @echo " " - @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" - @echo " simmodel : Generates HDL simulation models for chosen simulation mode" - @echo " " - @echo " netlistclean: Deletes netlist" - @echo " bitsclean: Deletes bit, ncd, bmm files" - @echo " hwclean : Deletes implementation dir" - @echo " simclean : Deletes simulation dir" - @echo " clean : Deletes all generated files/directories" - @echo " " - -bits: $(SYSTEM_BIT) - -ace: $(SYSTEM_ACE) - -exporttosdk: $(SYSTEM_HW_HANDOFF_DEP) - -netlist: $(POSTSYN_NETLIST) - -download: $(DOWNLOAD_BIT) dummy - @echo "*********************************************" - @echo "Downloading Bitstream onto the target board" - @echo "*********************************************" - impact -batch etc/download.cmd - -init_bram: $(DOWNLOAD_BIT) - -sim: $(DEFAULT_SIM_SCRIPT) - cd simulation/behavioral & \ - system_fuse.cmd - cd simulation/behavioral & \ - start /B $(SIM_CMD) -gui -tclbatch system_setup.tcl - -simmodel: $(DEFAULT_SIM_SCRIPT) - -behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) - -structural_model: $(STRUCTURAL_SIM_SCRIPT) - -clean: hwclean simclean - rm -f _impact.cmd - -hwclean: netlistclean bitsclean - rm -rf implementation synthesis xst hdl - rm -rf xst.srp $(SYSTEM).srp - rm -f __xps/ise/_xmsgs/bitinit.xmsgs - -netlistclean: - rm -f $(POSTSYN_NETLIST) - rm -f platgen.log - rm -f __xps/ise/_xmsgs/platgen.xmsgs - rm -f $(BMM_FILE) - -bitsclean: - rm -f $(SYSTEM_BIT) - rm -f implementation/$(SYSTEM).ncd - rm -f implementation/$(SYSTEM)_bd.bmm - rm -f implementation/$(SYSTEM)_map.ncd - rm -f implementation/download.bit - rm -f __xps/$(SYSTEM)_routed - -simclean: - rm -rf simulation/behavioral - rm -f simgen.log - rm -f __xps/ise/_xmsgs/simgen.xmsgs - -################################################################# -# BOOTLOOP ELF FILES -################################################################# - - -$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP_LE) - IF NOT EXIST "$(BOOTLOOP_DIR)" @mkdir "$(BOOTLOOP_DIR)" - cp -f $(MICROBLAZE_BOOTLOOP_LE) $(MICROBLAZE_0_BOOTLOOP) - -################################################################# -# HARDWARE IMPLEMENTATION FLOW -################################################################# - - -$(BMM_FILE) \ -$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ - $(CORE_STATE_DEVELOPMENT_FILES) - @echo "****************************************************" - @echo "Creating system netlist for hardware specification.." - @echo "****************************************************" - platgen $(PLATGEN_OPTIONS) $(MHSFILE) - -$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) - @echo "Running synthesis..." - cd synthesis & synthesis.cmd - -__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) - @echo "*********************************************" - @echo "Running Xilinx Implementation tools.." - @echo "*********************************************" - @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf - @cp -f etc/fast_runtime.opt implementation/xflow.opt - xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc - touch __xps/$(SYSTEM)_routed - -$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE) - xilperl $(XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par - @echo "*********************************************" - @echo "Running Bitgen.." - @echo "*********************************************" - @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut - cd implementation & bitgen -w -f bitgen.ut $(SYSTEM) & cd .. - -$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_IMP_FILES) __xps/bitinit.opt - @cp -f implementation/$(SYSTEM)_bd.bmm . - @echo "*********************************************" - @echo "Initializing BRAM contents of the bitstream" - @echo "*********************************************" - bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_IMP_FILE_ARGS) \ - -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) - @rm -f $(SYSTEM)_bd.bmm - -$(SYSTEM_ACE): - @echo "In order to generate ace file, you must have:-" - @echo "- exactly one processor." - @echo "- opb_mdm, if using microblaze." - -################################################################# -# EXPORT_TO_SDK FLOW -################################################################# - -$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt - IF NOT EXIST "$(SDK_EXPORT_DIR)" @mkdir "$(SDK_EXPORT_DIR)" - psf2Edward -inp $(SYSTEM).xmp -exit_on_error -edwver 1.2 -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT) - xdsgen -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(GLOBAL_SEARCHPATHOPT) -make_docs_local - -$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT) - @rm -rf $(SYSTEM_HW_HANDOFF_BIT) - @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR) - -$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm - @rm -rf $(SYSTEM_HW_HANDOFF_BMM) - @cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR) - -################################################################# -# SIMULATION FLOW -################################################################# - - -################## BEHAVIORAL SIMULATION ################## - -$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ - $(BRAMINIT_ELF_SIM_FILES) - @echo "*********************************************" - @echo "Creating behavioral simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) - -################## STRUCTURAL SIMULATION ################## - -$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ - $(BRAMINIT_ELF_SIM_FILES) - @echo "*********************************************" - @echo "Creating structural simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) - - -################## TIMING SIMULATION ################## - -implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed - -$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \ - $(BRAMINIT_ELF_SIM_FILES) - @echo "*********************************************" - @echo "Creating timing simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) - -dummy: - @echo "" - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs deleted file mode 100644 index 864094491..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs +++ /dev/null @@ -1,458 +0,0 @@ - -# ############################################################################## -# Created by Base System Builder Wizard for Xilinx EDK 13.1 Build EDK_O.40d -# Fri Aug 26 19:44:08 2011 -# Target Board: xilinx.com sp605 Rev C -# Family: spartan6 -# Device: xc6slx45t -# Package: fgg484 -# Speed Grade: -3 -# ############################################################################## - PARAMETER VERSION = 2.1.0 - - - PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 - PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000 - PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000 - PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O - PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I - PORT LEDs_4Bits_TRI_O = LEDs_4Bits_TRI_O, DIR = O, VEC = [3:0] - PORT Push_Buttons_4Bits_TRI_I = Push_Buttons_4Bits_TRI_I, DIR = I, VEC = [3:0] - PORT mcbx_dram_clk = mcbx_dram_clk, DIR = O - PORT mcbx_dram_clk_n = mcbx_dram_clk_n, DIR = O - PORT mcbx_dram_cke = mcbx_dram_cke, DIR = O - PORT mcbx_dram_odt = mcbx_dram_odt, DIR = O - PORT mcbx_dram_ras_n = mcbx_dram_ras_n, DIR = O - PORT mcbx_dram_cas_n = mcbx_dram_cas_n, DIR = O - PORT mcbx_dram_we_n = mcbx_dram_we_n, DIR = O - PORT mcbx_dram_udm = mcbx_dram_udm, DIR = O - PORT mcbx_dram_ldm = mcbx_dram_ldm, DIR = O - PORT mcbx_dram_ba = mcbx_dram_ba, DIR = O, VEC = [2:0] - PORT mcbx_dram_addr = mcbx_dram_addr, DIR = O, VEC = [12:0] - PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst, DIR = O - PORT mcbx_dram_dq = mcbx_dram_dq, DIR = IO, VEC = [15:0] - PORT mcbx_dram_dqs = mcbx_dram_dqs, DIR = IO - PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n, DIR = IO - PORT mcbx_dram_udqs = mcbx_dram_udqs, DIR = IO - PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n, DIR = IO - PORT rzq = rzq, DIR = IO - PORT zio = zio, DIR = IO - PORT ETHERNET_MDIO = ETHERNET_MDIO, DIR = IO - PORT ETHERNET_MDC = ETHERNET_MDC, DIR = O - PORT ETHERNET_TX_ER = ETHERNET_TX_ER, DIR = O - PORT ETHERNET_TXD = ETHERNET_TXD, DIR = O, VEC = [7:0] - PORT ETHERNET_TX_EN = ETHERNET_TX_EN, DIR = O - PORT ETHERNET_MII_TX_CLK = ETHERNET_MII_TX_CLK, DIR = I - PORT ETHERNET_TX_CLK = ETHERNET_TX_CLK, DIR = O - PORT ETHERNET_RXD = ETHERNET_RXD, DIR = I, VEC = [7:0] - PORT ETHERNET_RX_ER = ETHERNET_RX_ER, DIR = I - PORT ETHERNET_RX_CLK = ETHERNET_RX_CLK, DIR = I - PORT ETHERNET_RX_DV = ETHERNET_RX_DV, DIR = I - PORT ETHERNET_PHY_RST_N = ETHERNET_PHY_RST_N, DIR = O - - -BEGIN axi_interconnect - PARAMETER INSTANCE = axi4_0 - PARAMETER HW_VER = 1.02.a - PORT interconnect_aclk = clk_100_0000MHzPLL0 - PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn -END - -BEGIN axi_interconnect - PARAMETER INSTANCE = axi4lite_0 - PARAMETER HW_VER = 1.02.a - PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 - PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn - PORT INTERCONNECT_ACLK = clk_50_0000MHzPLL0 -END - -BEGIN microblaze - PARAMETER INSTANCE = microblaze_0 - PARAMETER HW_VER = 8.10.a - PARAMETER C_INTERCONNECT = 2 - PARAMETER C_USE_BARREL = 1 - PARAMETER C_USE_FPU = 0 - PARAMETER C_DEBUG_ENABLED = 1 - PARAMETER C_ICACHE_BASEADDR = 0xc0000000 - PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff - PARAMETER C_USE_ICACHE = 1 - PARAMETER C_ICACHE_ALWAYS_USED = 1 - PARAMETER C_DCACHE_BASEADDR = 0xc0000000 - PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff - PARAMETER C_USE_DCACHE = 1 - PARAMETER C_DCACHE_ALWAYS_USED = 1 - PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1 - PARAMETER C_NUMBER_OF_PC_BRK = 7 - PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2 - PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2 - PARAMETER C_CACHE_BYTE_SIZE = 16384 - PARAMETER C_DCACHE_BYTE_SIZE = 16384 - BUS_INTERFACE M_AXI_DP = axi4lite_0 - BUS_INTERFACE DEBUG = microblaze_0_debug - BUS_INTERFACE DLMB = microblaze_0_dlmb - BUS_INTERFACE ILMB = microblaze_0_ilmb - BUS_INTERFACE M_AXI_DC = axi4_0 - BUS_INTERFACE M_AXI_IC = axi4_0 - PORT MB_RESET = proc_sys_reset_0_MB_Reset - PORT CLK = clk_100_0000MHzPLL0 - PORT INTERRUPT = microblaze_0_interrupt -END - -BEGIN lmb_v10 - PARAMETER INSTANCE = microblaze_0_ilmb - PARAMETER HW_VER = 2.00.a - PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET - PORT LMB_CLK = clk_100_0000MHzPLL0 -END - -BEGIN lmb_v10 - PARAMETER INSTANCE = microblaze_0_dlmb - PARAMETER HW_VER = 2.00.a - PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET - PORT LMB_CLK = clk_100_0000MHzPLL0 -END - -BEGIN lmb_bram_if_cntlr - PARAMETER INSTANCE = microblaze_0_i_bram_ctrl - PARAMETER HW_VER = 3.00.a - PARAMETER C_BASEADDR = 0x00000000 - PARAMETER C_HIGHADDR = 0x00001FFF - BUS_INTERFACE SLMB = microblaze_0_ilmb - BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block -END - -BEGIN lmb_bram_if_cntlr - PARAMETER INSTANCE = microblaze_0_d_bram_ctrl - PARAMETER HW_VER = 3.00.a - PARAMETER C_BASEADDR = 0x00000000 - PARAMETER C_HIGHADDR = 0x00001FFF - BUS_INTERFACE SLMB = microblaze_0_dlmb - BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block -END - -BEGIN bram_block - PARAMETER INSTANCE = microblaze_0_bram_block - PARAMETER HW_VER = 1.00.a - BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block - BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block -END - -BEGIN proc_sys_reset - PARAMETER INSTANCE = proc_sys_reset_0 - PARAMETER HW_VER = 3.00.a - PARAMETER C_EXT_RESET_HIGH = 1 - PORT Ext_Reset_In = RESET - PORT MB_Reset = proc_sys_reset_0_MB_Reset - PORT Slowest_sync_clk = clk_50_0000MHzPLL0 - PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn - PORT Dcm_locked = proc_sys_reset_0_Dcm_locked - PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst - PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET -END - -BEGIN clock_generator - PARAMETER INSTANCE = clock_generator_0 - PARAMETER HW_VER = 4.01.a - PARAMETER C_CLKIN_FREQ = 200000000 - PARAMETER C_CLKOUT0_FREQ = 600000000 - PARAMETER C_CLKOUT0_GROUP = PLL0 - PARAMETER C_CLKOUT0_BUF = FALSE - PARAMETER C_CLKOUT1_FREQ = 600000000 - PARAMETER C_CLKOUT1_PHASE = 180 - PARAMETER C_CLKOUT1_GROUP = PLL0 - PARAMETER C_CLKOUT1_BUF = FALSE - PARAMETER C_CLKOUT2_FREQ = 100000000 - PARAMETER C_CLKOUT2_GROUP = PLL0 - PARAMETER C_CLKOUT3_FREQ = 125000000 - PARAMETER C_CLKOUT3_GROUP = NONE - PARAMETER C_CLKOUT4_FREQ = 200000000 - PARAMETER C_CLKOUT4_GROUP = PLL0 - PARAMETER C_CLKOUT5_FREQ = 50000000 - PARAMETER C_CLKOUT5_GROUP = PLL0 - PORT RST = RESET - PORT CLKIN = CLK - PORT CLKOUT2 = clk_100_0000MHzPLL0 - PORT CLKOUT5 = clk_50_0000MHzPLL0 - PORT CLKOUT3 = clk_125_0000MHz - PORT CLKOUT4 = clk_200_0000MHzPLL0 - PORT CLKOUT0 = clk_600_0000MHzPLL0_nobuf - PORT CLKOUT1 = clk_600_0000MHz180PLL0_nobuf - PORT LOCKED = proc_sys_reset_0_Dcm_locked -END - -BEGIN mdm - PARAMETER INSTANCE = debug_module - PARAMETER HW_VER = 2.00.b - PARAMETER C_INTERCONNECT = 2 - PARAMETER C_USE_UART = 1 - PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 - PARAMETER C_BASEADDR = 0x74800000 - PARAMETER C_HIGHADDR = 0x7480FFFF - BUS_INTERFACE S_AXI = axi4lite_0 - BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug - PORT S_AXI_ACLK = clk_50_0000MHzPLL0 - PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst -END - -BEGIN axi_uartlite - PARAMETER INSTANCE = RS232_Uart_1 - PARAMETER HW_VER = 1.01.a - PARAMETER C_BAUDRATE = 115200 - PARAMETER C_DATA_BITS = 8 - PARAMETER C_USE_PARITY = 0 - PARAMETER C_ODD_PARITY = 1 - PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 - PARAMETER C_BASEADDR = 0x40600000 - PARAMETER C_HIGHADDR = 0x4060ffff - BUS_INTERFACE S_AXI = axi4lite_0 - PORT TX = RS232_Uart_1_sout - PORT RX = RS232_Uart_1_sin - PORT S_AXI_ACLK = clk_50_0000MHzPLL0 - PORT Interrupt = RS232_Uart_1_Interrupt -END - -BEGIN axi_gpio - PARAMETER INSTANCE = LEDs_4Bits - PARAMETER HW_VER = 1.01.a - PARAMETER C_GPIO_WIDTH = 4 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_INTERRUPT_PRESENT = 0 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 - PARAMETER C_BASEADDR = 0x40020000 - PARAMETER C_HIGHADDR = 0x4002ffff - BUS_INTERFACE S_AXI = axi4lite_0 - PORT GPIO_IO_O = LEDs_4Bits_TRI_O - PORT S_AXI_ACLK = clk_50_0000MHzPLL0 -END - -BEGIN axi_gpio - PARAMETER INSTANCE = Push_Buttons_4Bits - PARAMETER HW_VER = 1.01.a - PARAMETER C_GPIO_WIDTH = 4 - PARAMETER C_ALL_INPUTS = 1 - PARAMETER C_INTERRUPT_PRESENT = 1 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 - PARAMETER C_BASEADDR = 0x40000000 - PARAMETER C_HIGHADDR = 0x4000ffff - BUS_INTERFACE S_AXI = axi4lite_0 - PORT GPIO_IO_I = Push_Buttons_4Bits_TRI_I - PORT S_AXI_ACLK = clk_50_0000MHzPLL0 - PORT IP2INTC_Irpt = Push_Buttons_4Bits_IP2INTC_Irpt -END - -BEGIN axi_s6_ddrx - PARAMETER INSTANCE = MCB_DDR3 - PARAMETER HW_VER = 1.02.a - PARAMETER C_MCB_RZQ_LOC = K7 - PARAMETER C_MCB_ZIO_LOC = R7 - PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E - PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM - PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1 - PARAMETER C_S0_AXI_BASEADDR = 0x80000000 - PARAMETER C_S0_AXI_HIGHADDR = 0x807FFFFF - PARAMETER C_S0_AXI_STRICT_COHERENCY = 0 - BUS_INTERFACE S0_AXI = axi4_0 - PORT mcbx_dram_clk = mcbx_dram_clk - PORT mcbx_dram_clk_n = mcbx_dram_clk_n - PORT mcbx_dram_cke = mcbx_dram_cke - PORT mcbx_dram_odt = mcbx_dram_odt - PORT mcbx_dram_ras_n = mcbx_dram_ras_n - PORT mcbx_dram_cas_n = mcbx_dram_cas_n - PORT mcbx_dram_we_n = mcbx_dram_we_n - PORT mcbx_dram_udm = mcbx_dram_udm - PORT mcbx_dram_ldm = mcbx_dram_ldm - PORT mcbx_dram_ba = mcbx_dram_ba - PORT mcbx_dram_addr = mcbx_dram_addr - PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst - PORT mcbx_dram_dq = mcbx_dram_dq - PORT mcbx_dram_dqs = mcbx_dram_dqs - PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n - PORT mcbx_dram_udqs = mcbx_dram_udqs - PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n - PORT rzq = rzq - PORT zio = zio - PORT s0_axi_aclk = clk_100_0000MHzPLL0 - PORT ui_clk = clk_100_0000MHzPLL0 - PORT sysclk_2x = clk_600_0000MHzPLL0_nobuf - PORT sysclk_2x_180 = clk_600_0000MHz180PLL0_nobuf - PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET - PORT PLL_LOCK = proc_sys_reset_0_Dcm_locked -END - -BEGIN axi_ethernet - PARAMETER INSTANCE = ETHERNET - PARAMETER HW_VER = 2.01.a - PARAMETER C_PHYADDR = 0B00001 - PARAMETER C_INCLUDE_IO = 1 - PARAMETER C_TYPE = 1 - PARAMETER C_PHY_TYPE = 1 - PARAMETER C_HALFDUP = 0 - PARAMETER C_TXMEM = 4096 - PARAMETER C_RXMEM = 4096 - PARAMETER C_TXCSUM = 0 - PARAMETER C_RXCSUM = 0 - PARAMETER C_TXVLAN_TRAN = 0 - PARAMETER C_RXVLAN_TRAN = 0 - PARAMETER C_TXVLAN_TAG = 0 - PARAMETER C_RXVLAN_TAG = 0 - PARAMETER C_TXVLAN_STRP = 0 - PARAMETER C_RXVLAN_STRP = 0 - PARAMETER C_MCAST_EXTEND = 0 - PARAMETER C_STATS = 0 - PARAMETER C_AVB = 0 - PARAMETER C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC = 0 - PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 - PARAMETER C_BASEADDR = 0x41240000 - PARAMETER C_HIGHADDR = 0x4127ffff - BUS_INTERFACE S_AXI = axi4lite_0 - BUS_INTERFACE AXI_STR_TXD = ETHERNET_dma_txd - BUS_INTERFACE AXI_STR_TXC = ETHERNET_dma_txc - BUS_INTERFACE AXI_STR_RXS = ETHERNET_dma_rxs - BUS_INTERFACE AXI_STR_RXD = ETHERNET_dma_rxd - PORT MDIO = ETHERNET_MDIO - PORT MDC = ETHERNET_MDC - PORT GMII_TX_ER = ETHERNET_TX_ER - PORT GMII_TXD = ETHERNET_TXD - PORT GMII_TX_EN = ETHERNET_TX_EN - PORT MII_TX_CLK = ETHERNET_MII_TX_CLK - PORT GMII_TX_CLK = ETHERNET_TX_CLK - PORT GMII_RXD = ETHERNET_RXD - PORT GMII_RX_ER = ETHERNET_RX_ER - PORT GMII_RX_CLK = ETHERNET_RX_CLK - PORT GMII_RX_DV = ETHERNET_RX_DV - PORT PHY_RST_N = ETHERNET_PHY_RST_N - PORT S_AXI_ACLK = clk_50_0000MHzPLL0 - PORT GTX_CLK = clk_125_0000MHz - PORT REF_CLK = clk_200_0000MHzPLL0 - PORT AXI_STR_TXD_ACLK = clk_100_0000MHzPLL0 - PORT AXI_STR_TXC_ACLK = clk_100_0000MHzPLL0 - PORT AXI_STR_RXD_ACLK = clk_100_0000MHzPLL0 - PORT AXI_STR_RXS_ACLK = clk_100_0000MHzPLL0 - PORT AXI_STR_TXD_ARESETN = AXI_STR_TXD_ARESETN - PORT AXI_STR_TXC_ARESETN = AXI_STR_TXC_ARESETN - PORT AXI_STR_RXD_ARESETN = AXI_STR_RXD_ARESETN - PORT AXI_STR_RXS_ARESETN = AXI_STR_RXS_ARESETN - PORT INTERRUPT = ETHERNET_INTERRUPT -END - -BEGIN axi_dma - PARAMETER INSTANCE = ETHERNET_dma - PARAMETER HW_VER = 3.00.a - PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1 - PARAMETER C_SG_USE_STSAPP_LENGTH = 1 - PARAMETER C_INCLUDE_MM2S_DRE = 1 - PARAMETER C_INCLUDE_S2MM_DRE = 1 - PARAMETER C_DLYTMR_RESOLUTION = 1250 - PARAMETER C_PRMRY_IS_ACLK_ASYNC = 0 - PARAMETER C_SG_INCLUDE_STSCNTRL_STRM = 1 - PARAMETER C_SG_LENGTH_WIDTH = 16 - PARAMETER C_INCLUDE_MM2S = 1 - PARAMETER C_INCLUDE_S2MM = 1 - PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 1 - PARAMETER C_BASEADDR = 0x41e00000 - PARAMETER C_HIGHADDR = 0x41e0ffff - BUS_INTERFACE S_AXI_LITE = axi4lite_0 - BUS_INTERFACE M_AXI_SG = axi4_0 - BUS_INTERFACE M_AXI_MM2S = axi4_0 - BUS_INTERFACE M_AXI_S2MM = axi4_0 - BUS_INTERFACE M_AXIS_MM2S = ETHERNET_dma_txd - BUS_INTERFACE M_AXIS_CNTRL = ETHERNET_dma_txc - BUS_INTERFACE S_AXIS_STS = ETHERNET_dma_rxs - BUS_INTERFACE S_AXIS_S2MM = ETHERNET_dma_rxd - PORT s_axi_lite_aclk = clk_100_0000MHzPLL0 - PORT m_axi_sg_aclk = clk_100_0000MHzPLL0 - PORT m_axi_mm2s_aclk = clk_100_0000MHzPLL0 - PORT m_axi_s2mm_aclk = clk_100_0000MHzPLL0 - PORT mm2s_prmry_reset_out_n = AXI_STR_TXD_ARESETN - PORT mm2s_cntrl_reset_out_n = AXI_STR_TXC_ARESETN - PORT s2mm_prmry_reset_out_n = AXI_STR_RXD_ARESETN - PORT s2mm_sts_reset_out_n = AXI_STR_RXS_ARESETN - PORT mm2s_introut = ETHERNET_dma_mm2s_introut - PORT s2mm_introut = ETHERNET_dma_s2mm_introut -END - -BEGIN axi_intc - PARAMETER INSTANCE = microblaze_0_intc - PARAMETER HW_VER = 1.01.a - PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 - PARAMETER C_BASEADDR = 0x41200000 - PARAMETER C_HIGHADDR = 0x4120ffff - BUS_INTERFACE S_AXI = axi4lite_0 - PORT IRQ = microblaze_0_interrupt - PORT S_AXI_ACLK = clk_50_0000MHzPLL0 - PORT INTR = ETHERNET_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut & Push_Buttons_4Bits_IP2INTC_Irpt & RS232_Uart_1_Interrupt & axi_timer_0_Interrupt -END - -BEGIN axi_timer - PARAMETER INSTANCE = axi_timer_0 - PARAMETER HW_VER = 1.01.a - PARAMETER C_BASEADDR = 0x41c00000 - PARAMETER C_HIGHADDR = 0x41c0ffff - BUS_INTERFACE S_AXI = axi4lite_0 - PORT S_AXI_ACLK = clk_50_0000MHzPLL0 - PORT Interrupt = axi_timer_0_Interrupt -END - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp deleted file mode 100644 index 3862cd3d6..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp +++ /dev/null @@ -1,38 +0,0 @@ -#Please do not modify this file by hand -XmpVersion: 13.1 -VerMgmt: 13.1 -IntStyle: default -MHS File: system.mhs -Architecture: spartan6 -Device: xc6slx45t -Package: fgg484 -SpeedGrade: -3 -UserCmd1: -UserCmd1Type: 0 -UserCmd2: -UserCmd2Type: 0 -GenSimTB: 0 -SdkExportBmmBit: 1 -SdkExportDir: SDK/SDK_Export -InsertNoPads: 0 -WarnForEAArch: 1 -HdlLang: VHDL -SimModel: BEHAVIORAL -UcfFile: data/system.ucf -EnableParTimingError: 1 -ShowLicenseDialog: 1 -ICacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR -ICacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR -ICacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR -ICacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR -ICacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR -ICacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR -DCacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR -DCacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR -DCacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR -DCacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR -DCacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR -DCacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR -Processor: microblaze_0 -ElfImp: -ElfSim: diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system_incl.make b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system_incl.make deleted file mode 100644 index b73b933aa..000000000 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system_incl.make +++ /dev/null @@ -1,111 +0,0 @@ -################################################################# -# Makefile generated by Xilinx Platform Studio -# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetFull\PlatformStudioProject\system.xmp -# -# WARNING : This file will be re-generated every time a command -# to run a make target is invoked. So, any changes made to this -# file manually, will be lost when make is invoked next. -################################################################# - -SHELL = CMD - -XILINX_EDK_DIR = C:/devtools/Xilinx/13.1/ISE_DS/EDK - -SYSTEM = system - -MHSFILE = system.mhs - -FPGA_ARCH = spartan6 - -DEVICE = xc6slx45tfgg484-3 - -LANGUAGE = vhdl -GLOBAL_SEARCHPATHOPT = -PROJECT_SEARCHPATHOPT = - -SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) - -SUBMODULE_OPT = - -PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst - -OBSERVE_PAR_OPTIONS = -error yes - -MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf -MICROBLAZE_BOOTLOOP_LE = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop_le.elf -PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf -PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf -BOOTLOOP_DIR = bootloops - -MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf - -BRAMINIT_ELF_IMP_FILES = $(MICROBLAZE_0_BOOTLOOP) -BRAMINIT_ELF_IMP_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP) - -BRAMINIT_ELF_SIM_FILES = $(MICROBLAZE_0_BOOTLOOP) -BRAMINIT_ELF_SIM_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP) - -SIM_CMD = isim_system - -BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.tcl - -STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.tcl - -TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.tcl - -DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) - -MIX_LANG_SIM_OPT = -mixed yes - -SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_SIM_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s isim - - -CORE_STATE_DEVELOPMENT_FILES = - -WRAPPER_NGC_FILES = implementation/axi4_0_wrapper.ngc \ -implementation/axi4lite_0_wrapper.ngc \ -implementation/microblaze_0_wrapper.ngc \ -implementation/microblaze_0_ilmb_wrapper.ngc \ -implementation/microblaze_0_dlmb_wrapper.ngc \ -implementation/microblaze_0_i_bram_ctrl_wrapper.ngc \ -implementation/microblaze_0_d_bram_ctrl_wrapper.ngc \ -implementation/microblaze_0_bram_block_wrapper.ngc \ -implementation/proc_sys_reset_0_wrapper.ngc \ -implementation/clock_generator_0_wrapper.ngc \ -implementation/debug_module_wrapper.ngc \ -implementation/rs232_uart_1_wrapper.ngc \ -implementation/leds_4bits_wrapper.ngc \ -implementation/push_buttons_4bits_wrapper.ngc \ -implementation/mcb_ddr3_wrapper.ngc \ -implementation/ethernet_wrapper.ngc \ -implementation/ethernet_dma_wrapper.ngc \ -implementation/microblaze_0_intc_wrapper.ngc \ -implementation/axi_timer_0_wrapper.ngc - -POSTSYN_NETLIST = implementation/$(SYSTEM).ngc - -SYSTEM_BIT = implementation/$(SYSTEM).bit - -DOWNLOAD_BIT = implementation/download.bit - -SYSTEM_ACE = implementation/$(SYSTEM).ace - -UCF_FILE = data/system.ucf - -BMM_FILE = implementation/$(SYSTEM).bmm - -BITGEN_UT_FILE = etc/bitgen.ut - -XFLOW_OPT_FILE = etc/fast_runtime.opt -XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE) - -XPLORER_DEPENDENCY = __xps/xplorer.opt -XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7 - -FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY) - -SDK_EXPORT_DIR = SDK\SDK_Export\hw -SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml -SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit -SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm -SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM)