From: Stefan Mavrodiev Date: Tue, 27 Mar 2018 13:57:23 +0000 (+0300) Subject: sunxi: mmc: Fix phase delays X-Git-Tag: v2018.05-rc3~2^2~1 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=4744d81cc0dbe238bd4d8cd88c1c71022bffa621;p=u-boot sunxi: mmc: Fix phase delays U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where PLL5 is used, with clock rates respectively 600MHz and 768MHz. Thus there are different phase degree steps - 24 for the kernel and 30 for u-boot. In the kernel driver the phase is set 90 deg for output and 120 for sample. Dividing by 30 will result values 3 and 4. Those are the values set in the u-boot driver. However, the condition defining delays is wrong. MMC core driver requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but phase is set 30 deg for output and 120 deg for sample. Apparently this works for most cards. On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains about it. Maybe there is other boards with similar problem? So the fix is to match delays for both u-boot and kernel. Signed-off-by: Stefan Mavrodiev Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index df6f32850e..f4c245c5eb 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -147,19 +147,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) oclk_dly = 0; sclk_dly = 5; #ifdef CONFIG_MACH_SUN9I - } else if (hz <= 50000000) { + } else if (hz <= 52000000) { oclk_dly = 5; sclk_dly = 4; } else { - /* hz > 50000000 */ + /* hz > 52000000 */ oclk_dly = 2; sclk_dly = 4; #else - } else if (hz <= 50000000) { + } else if (hz <= 52000000) { oclk_dly = 3; sclk_dly = 4; } else { - /* hz > 50000000 */ + /* hz > 52000000 */ oclk_dly = 1; sclk_dly = 4; #endif