From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Mon, 30 Sep 2013 16:16:52 +0000 (-0300)
Subject: ARM: mx5: Enable L2 cache
X-Git-Tag: v2014.01-rc1~77^2^2~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=4867b634b7c0e5ede258b4998fa4b2710e7daacf;p=u-boot

ARM: mx5: Enable L2 cache

Enable L2 cache for improving the system performance.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 25fadf6487..97077fd367 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -45,6 +45,12 @@
 #endif
 
 	mcr 15, 1, r0, c9, c0, 2
+
+	/* enable L2 cache */
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #2
+	mcr 15, 0, r0, c1, c0, 1
+
 .endm /* init_l2cc */
 
 /* AIPS setup - Only setup MPROTx registers.