From: Michal Simek Date: Mon, 7 May 2007 15:11:09 +0000 (+0200) Subject: new: add writing to msr register X-Git-Tag: v1.3.0-rc1~76^2~4^2~11 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=48fbd3a4cdabbebc1debd7eed73c00c2caf914f6;p=u-boot new: add writing to msr register --- diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h old mode 100644 new mode 100755 index f63ffed3dc..2b0c045b9f --- a/board/xilinx/ml401/xparameters.h +++ b/board/xilinx/ml401/xparameters.h @@ -21,50 +21,54 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * - * * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 6.3 EDK_Gmm.12.3 + * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 */ /* System Clock Frequency */ #define XILINX_CLOCK_FREQ 100000000 /* Microblaze is microblaze_0 */ -#define XILINX_FSL_NUMBER 2 +#define XILINX_FSL_NUMBER 3 -/* Interrupt controller is intc_0 */ +/* Interrupt controller is opb_intc_0 */ #define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 4 +#define XILINX_INTC_NUM_INTR_INPUTS 5 -/* Timer pheriphery is opb_timer_0 */ +/* Timer pheriphery is opb_timer_1 */ #define XILINX_TIMER_BASEADDR 0x41c00000 #define XILINX_TIMER_IRQ 0 -/* Uart pheriphery is console_uart */ +/* Uart pheriphery is RS232_Uart */ #define XILINX_UART_BASEADDR 0x40600000 #define XILINX_UART_BAUDRATE 115200 -/* GPIO is opb_gpio_0*/ -#define XILINX_GPIO_BASEADDR 0x90000000 +/* IIC pheriphery is IIC_EEPROM */ +#define XILINX_IIC_0_BASEADDR 0x40800000 +#define XILINX_IIC_0_FREQ 100000 +#define XILINX_IIC_0_BIT 0 + +/* GPIO is LEDs_4Bit*/ +#define XILINX_GPIO_BASEADDR 0x40000000 -/* Flash Memory is opb_emc_0 */ +/* Flash Memory is FLASH_2Mx32 */ #define XILINX_FLASH_START 0x2c000000 #define XILINX_FLASH_SIZE 0x00800000 -/* Main Memory is plb_ddr_0 */ +/* Main Memory is DDR_SDRAM_64Mx32 */ #define XILINX_RAM_START 0x28000000 #define XILINX_RAM_SIZE 0x04000000 -/* Sysace Controller is opb_sysace_0 */ +/* Sysace Controller is SysACE_CompactFlash */ #define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180FFFF +#define XILINX_SYSACE_HIGHADDR 0x4180ffff #define XILINX_SYSACE_MEM_WIDTH 16 -/* Ethernet controller is opb_ethernet_0 */ +/* Ethernet controller is Ethernet_MAC */ #define XPAR_XEMAC_NUM_INSTANCES 1 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 #define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0fFFF +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1 diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c index 827b75e6ce..ca8a8897d5 100644 --- a/common/cmd_mfsl.c +++ b/common/cmd_mfsl.c @@ -238,13 +238,19 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - int val = 0; + unsigned int val = 0; + val = (unsigned int)simple_strtoul (argv[1], NULL, 16); if (argc < 1) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } - RMSR (val); + if (argc > 1) { + MTS (val); + MFS (val); + } else { + MFS (val); + } printf ("rmsr: 0x%08lx\n", val); return 0; } @@ -259,7 +265,7 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr, "fwr - write data to FSL\n", "- [fslnum data [0|x]], (0 - non blocking|x - blocking).\n"); -U_BOOT_CMD (rmsr, 1, 1, do_rmsr, +U_BOOT_CMD (rmsr, 3, 1, do_rmsr, "rmsr - read MSR register\n", "- read MSR register.\n"); -#endif /* CONFIG_MICROBLAZE & CFG_CMD_MFSL */ +#endif /* CONFIG_MICROBLAZE & CFG_CMD_MFSL */ diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h index 67475725e2..fcda31f4a8 100644 --- a/include/asm-microblaze/asm.h +++ b/include/asm-microblaze/asm.h @@ -31,7 +31,13 @@ __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val)); #define PUT(val, fslnum) \ __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val)); - + /* CPU dependent */ -#define RMSR(val) \ - __asm__ __volatile__ ("mfs %0,rmsr":"=r" (val)); +#define MFS(val) \ + __asm__ __volatile__ ("mfs %0, rmsr":"=r" (val)); + +#define MTS(val) \ + __asm__ __volatile__ ("mts rmsr, %0"::"r" (val)); + +#define R14(val) \ + __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));