From: Sandeep Paulraj <s-paulraj@ti.com>
Date: Sat, 9 May 2009 16:35:20 +0000 (-0400)
Subject: NAND DaVinci: Update to ALE/CLE Mask values
X-Git-Tag: v2009.08-rc1~114^2~10
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=496863b2440dd7cd69a1ad2443a9badd5f8968d1;p=u-boot

NAND DaVinci: Update to ALE/CLE Mask values

All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8
except the DM646x. This was decided by the design team driving the design.
This patch updates the CLE and ALE values for DM646x.
Updated patches for DM646x will be sent shortly.
This applies to u-boot-nand-flash git

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---

diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h
index ba75cd66c5..f2020728d6 100644
--- a/include/asm-arm/arch-davinci/nand_defs.h
+++ b/include/asm-arm/arch-davinci/nand_defs.h
@@ -28,8 +28,13 @@
 
 #include <asm/arch/hardware.h>
 
+#ifdef CONFIG_SOC_DM646x
+#define	MASK_CLE	0x80000
+#define	MASK_ALE	0x40000
+#else
 #define	MASK_CLE	0x10
 #define	MASK_ALE	0x08
+#endif
 
 #define NAND_READ_START		0x00
 #define NAND_READ_END		0x30