From: Tien Fong Chee Date: Tue, 5 Dec 2017 07:57:58 +0000 (+0800) Subject: arm: socfpga: Fix with the correct polling on bit is set X-Git-Tag: v2018.05-rc3~36^2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=4ae87a83a64dbd71a14894114481dd92ffed4fdb;hp=d2a1f120cf638fd8a149bc8a46aec961c2fb9406;p=u-boot arm: socfpga: Fix with the correct polling on bit is set Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10") Polling on wrong cleared bit. Fix with correct polling on bit is set. Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10") Signed-off-by: Tien Fong Chee --- diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index d5763965dd..685e8e271a 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -111,12 +111,12 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void) unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK | ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK; - /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted, - * timeout at 1000ms + /* + * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until + * de-asserted, timeout at 1000ms */ - return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, - mask, - false, FPGA_TIMEOUT_MSEC, false); + return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask, + true, FPGA_TIMEOUT_MSEC, false); } static int wait_for_f2s_nstatus_pin(unsigned long value)