From: Tom Rini <trini@ti.com>
Date: Wed, 8 Aug 2012 21:29:51 +0000 (-0700)
Subject: am33xx: Add support, update omap3 McSPI driver
X-Git-Tag: v2012.10-rc1~254
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=4c0620bf42172325ea0c6afa0fdd362bb264e31b;p=u-boot

am33xx: Add support, update omap3 McSPI driver

Signed-off-by: Tom Rini <trini@ti.com>
---

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 1071f925cc..2b19506a34 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -148,6 +148,11 @@ static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
 	while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
 		;
+
+	/* spi0 */
+	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
+	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
+		;
 }
 
 static void mpu_pll_config(void)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 9346c0b5b4..47f9e56f42 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -86,15 +86,21 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	case 0:
 		ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
 		break;
+#ifdef OMAP3_MCSPI2_BASE
 	case 1:
 		ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
 		break;
+#endif
+#ifdef OMAP3_MCSPI3_BASE 
 	case 2:
 		ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
 		break;
+#endif
+#ifdef OMAP3_MCSPI4_BASE
 	case 3:
 		ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
 		break;
+#endif
 	default:
 		printf("SPI error: unsupported bus %i. \
 			Supported busses 0 - 3\n", bus);
diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index 0ac801cb25..bffa43cb6c 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -30,10 +30,15 @@
 #ifndef _OMAP3_SPI_H_
 #define _OMAP3_SPI_H_
 
+#ifdef CONFIG_AM33XX
+#define OMAP3_MCSPI1_BASE	0x48030100
+#define OMAP3_MCSPI2_BASE	0x481A0100
+#else
 #define OMAP3_MCSPI1_BASE	0x48098000
 #define OMAP3_MCSPI2_BASE	0x4809A000
 #define OMAP3_MCSPI3_BASE	0x480B8000
 #define OMAP3_MCSPI4_BASE	0x480BA000
+#endif
 
 #define OMAP3_MCSPI_MAX_FREQ	48000000