From: richardbarry Date: Sat, 31 Aug 2013 16:03:11 +0000 (+0000) Subject: Rename CORTEX_M)_Infineion_Boot_Kits_IAR_Keil to CORTEX_M0_Infineon_XMC1000_IAR_Keil_... X-Git-Tag: V7.5.3~53 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=4c34372ea5728330f8ecf0abe7be4e1d4b836902;p=freertos Rename CORTEX_M)_Infineion_Boot_Kits_IAR_Keil to CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC as it now contains projects for all three compilers. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2013 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.cproject b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.cproject deleted file mode 100644 index 7aefb8212..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.cproject +++ /dev/null @@ -1,135 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.project b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.project deleted file mode 100644 index 7a0005113..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.project +++ /dev/null @@ -1,104 +0,0 @@ - - - RTOSDemo - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - Common_Demo_Source - 2 - virtual:/virtual - - - FreeRTOS_Source - 2 - virtual:/virtual - - - Common_Demo_Source/blocktim.c - 1 - FREERTOS_BASE/Demo/Common/Minimal/blocktim.c - - - Common_Demo_Source/countsem.c - 1 - FREERTOS_BASE/Demo/Common/Minimal/countsem.c - - - Common_Demo_Source/dynamic.c - 1 - FREERTOS_BASE/Demo/Common/Minimal/dynamic.c - - - Common_Demo_Source/include - 2 - FREERTOS_BASE/Demo/Common/include - - - Common_Demo_Source/recmutex.c - 1 - FREERTOS_BASE/Demo/Common/Minimal/recmutex.c - - - FreeRTOS_Source/ARM_CM0 - 2 - FREERTOS_BASE/Source/portable/GCC/ARM_CM0 - - - FreeRTOS_Source/heap_4.c - 1 - FREERTOS_BASE/Source/portable/MemMang/heap_4.c - - - FreeRTOS_Source/include - 2 - FREERTOS_BASE/Source/include - - - FreeRTOS_Source/list.c - 1 - FREERTOS_BASE/Source/list.c - - - FreeRTOS_Source/queue.c - 1 - FREERTOS_BASE/Source/queue.c - - - FreeRTOS_Source/tasks.c - 1 - FREERTOS_BASE/Source/tasks.c - - - FreeRTOS_Source/timers.c - 1 - FREERTOS_BASE/Source/timers.c - - - - - FREERTOS_BASE - $%7BPARENT-2-PROJECT_LOC%7D - - - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/com.atollic.truestudio.debug.hardware_device.prefs deleted file mode 100644 index 669e09ab0..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/com.atollic.truestudio.debug.hardware_device.prefs +++ /dev/null @@ -1,11 +0,0 @@ -BOARD=XMC1200_Boot_Kit -CODE_LOCATION=FLASH -ENDIAN=Little-endian -MCU=XMC1200-T038F0200 -MCU_VENDOR=Infineon -MODEL=Pro -PROBE=SEGGER J-LINK -PROJECT_FORMAT_VERSION=2 -TARGET=ARM\u00AE -VERSION=4.1.0 -eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/org.eclipse.cdt.managedbuilder.core.prefs deleted file mode 100644 index 96ff207bb..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/org.eclipse.cdt.managedbuilder.core.prefs +++ /dev/null @@ -1,11 +0,0 @@ -eclipse.preferences.version=1 -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/delimiter=; -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/operation=remove -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/delimiter=; -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/operation=remove -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/append=true -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/delimiter=; -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/operation=remove -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/append=true -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/RegTest.c deleted file mode 100644 index 472cba864..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/RegTest.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -void vRegTest1Task( void ) __attribute__((naked)); -void vRegTest2Task( void ) __attribute__((naked)); - -void vRegTest1Task( void ) -{ - __asm volatile - ( - ".extern ulRegTest1LoopCounter \n" - " \n" - " /* Fill the core registers with known values. */ \n" - " movs r1, #101 \n" - " movs r2, #102 \n" - " movs r3, #103 \n" - " movs r4, #104 \n" - " movs r5, #105 \n" - " movs r6, #106 \n" - " movs r7, #107 \n" - " movs r0, #108 \n" - " mov r8, r0 \n" - " movs r0, #109 \n" - " mov r9, r0 \n" - " movs r0, #110 \n" - " mov r10, r0 \n" - " movs r0, #111 \n" - " mov r11, r0 \n" - " movs r0, #112 \n" - " mov r12, r0 \n" - " movs r0, #100 \n" - " \n" - "reg1_loop: \n" - " \n" - " cmp r0, #100 \n" - " bne reg1_error_loop \n" - " cmp r1, #101 \n" - " bne reg1_error_loop \n" - " cmp r2, #102 \n" - " bne reg1_error_loop \n" - " cmp r3, #103 \n" - " bne reg1_error_loop \n" - " cmp r4, #104 \n" - " bne reg1_error_loop \n" - " cmp r5, #105 \n" - " bne reg1_error_loop \n" - " cmp r6, #106 \n" - " bne reg1_error_loop \n" - " cmp r7, #107 \n" - " bne reg1_error_loop \n" - " movs r0, #108 \n" - " cmp r8, r0 \n" - " bne reg1_error_loop \n" - " movs r0, #109 \n" - " cmp r9, r0 \n" - " bne reg1_error_loop \n" - " movs r0, #110 \n" - " cmp r10, r0 \n" - " bne reg1_error_loop \n" - " movs r0, #111 \n" - " cmp r11, r0 \n" - " bne reg1_error_loop \n" - " movs r0, #112 \n" - " cmp r12, r0 \n" - " bne reg1_error_loop \n" - " \n" - " /* Everything passed, increment the loop counter. */ \n" - " push { r1 } \n" - " ldr r0, =ulRegTest1LoopCounter \n" - " ldr r1, [r0] \n" - " add r1, r1, #1 \n" - " str r1, [r0] \n" - " pop { r1 } \n" - " \n" - " /* Start again. */ \n" - " movs r0, #100 \n" - " b reg1_loop \n" - " \n" - "reg1_error_loop: \n" - " /* If this line is hit then there was an error in a core register value. \n" - " The loop ensures the loop counter stops incrementing. */ \n" - " b reg1_error_loop \n" - " nop \n" - ); -} -/*-----------------------------------------------------------*/ - -void vRegTest2Task( void ) -{ - __asm volatile - ( - ".extern ulRegTest2LoopCounter \n" - " \n" - " /* Fill the core registers with known values. */ \n" - " movs r1, #1 \n" - " movs r2, #2 \n" - " movs r3, #3 \n" - " movs r4, #4 \n" - " movs r5, #5 \n" - " movs r6, #6 \n" - " movs r7, #7 \n" - " movs r0, #8 \n" - " movs r8, r0 \n" - " movs r0, #9 \n" - " mov r9, r0 \n" - " movs r0, #10 \n" - " mov r10, r0 \n" - " movs r0, #11 \n" - " mov r11, r0 \n" - " movs r0, #12 \n" - " mov r12, r0 \n" - " movs r0, #10 \n" - " \n" - "reg2_loop: \n" - " \n" - " cmp r0, #10 \n" - " bne reg2_error_loop \n" - " cmp r1, #1 \n" - " bne reg2_error_loop \n" - " cmp r2, #2 \n" - " bne reg2_error_loop \n" - " cmp r3, #3 \n" - " bne reg2_error_loop \n" - " cmp r4, #4 \n" - " bne reg2_error_loop \n" - " cmp r5, #5 \n" - " bne reg2_error_loop \n" - " cmp r6, #6 \n" - " bne reg2_error_loop \n" - " cmp r7, #7 \n" - " bne reg2_error_loop \n" - " movs r0, #8 \n" - " cmp r8, r0 \n" - " bne reg2_error_loop \n" - " movs r0, #9 \n" - " cmp r9, r0 \n" - " bne reg2_error_loop \n" - " movs r0, #10 \n" - " cmp r10, r0 \n" - " bne reg2_error_loop \n" - " movs r0, #11 \n" - " cmp r11, r0 \n" - " bne reg2_error_loop \n" - " movs r0, #12 \n" - " cmp r12, r0 \n" - " bne reg2_error_loop \n" - " \n" - " /* Everything passed, increment the loop counter. */ \n" - " push { r1 } \n" - " ldr r0, =ulRegTest2LoopCounter \n" - " ldr r1, [r0] \n" - " add r1, r1, #1 \n" - " str r1, [r0] \n" - " pop { r1 } \n" - " \n" - " /* Start again. */ \n" - " movs r0, #10 \n" - " b reg2_loop \n" - " \n" - "reg2_error_loop: \n" - " /* If this line is hit then there was an error in a core register value. \n" - " The loop ensures the loop counter stops incrementing. */ \n" - " b reg2_error_loop \n" - " nop \n" - ); -} -/*-----------------------------------------------------------*/ - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/startup_XMC1200.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/startup_XMC1200.s deleted file mode 100644 index 914907047..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/startup_XMC1200.s +++ /dev/null @@ -1,608 +0,0 @@ -/** -***************************************************************************** -** -** File : startup_XMC1200.s -** -** Abstract : This assembler file contains interrupt vector and -** startup code for ARM. -** -** Functions : Reset_Handler -** Default_Handler -** XMCVeneer code -** -** Target : Infineon $(DEVICE) Device -** -** Environment : Atollic TrueSTUDIO(R) -** -** Distribution: The file is distributed “as is,” without any warranty -** of any kind. -** -** (c)Copyright Atollic AB. -** You may use this file as-is or modify it according to the needs of your -** project. This file may only be built (assembled or compiled and linked) -** using the Atollic TrueSTUDIO(R) product. The use of this file together -** with other tools than Atollic TrueSTUDIO(R) is not permitted. -** -***************************************************************************** -*/ - -#ifdef DAVE_CE -#include -#else -#define CLKVAL1_SSW 0x80000000 -#define CLKVAL2_SSW 0x80000000 -#endif - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global Reset_Handler -.global InterruptVector -.global Default_Handler - -/* Linker script definitions */ -/* start address for the initialization values of the .data section */ -.word _sidata -/* start address for the .data section */ -.word _sdata -/* end address for the .data section */ -.word _edata -/* start address for the .bss section */ -.word _sbss -/* end address for the .bss section */ -.word _ebss - -.word VeneerLoadAddr -.word VeneerStart -.word VeneerSize - - -/** -**=========================================================================== -** Program - Reset_Handler -** Abstract: This code gets called after reset. -**=========================================================================== -*/ - .section .text.Reset_Handler,"ax", %progbits - .type Reset_Handler, %function -Reset_Handler: - /* Set stack pointer */ - ldr r0, =_estack - mov sp, r0 - - /* Branch to SystemInit function */ - bl SystemInit - - /* Copy data initialization values */ - ldr r1,=_sidata - ldr r2,=_sdata - ldr r3,=_edata - b cmpdata -CopyLoop: - ldr r0, [r1] - str r0, [r2] - adds r1, r1, #4 - adds r2, r2, #4 -cmpdata: - cmp r2, r3 - blt CopyLoop - - /* Clear BSS section */ - movs r0, #0 - ldr r2,=_sbss - ldr r3,=_ebss - b cmpbss -ClearLoop: - str r0, [r2] - adds r2, r2, #4 -cmpbss: - cmp r2, r3 - blt ClearLoop - - /* VENEER COPY */ - /* R0 = Start address, R1 = Destination address, R2 = Size */ - ldr r0, =VeneerLoadAddr - ldr r1, =VeneerStart - ldr r2, =VeneerSize - -STARTVENEERCOPY: - /* R2 contains byte count. Change it to word count. It is ensured in the - linker script that the length is always word aligned. - */ - lsrs r2,r2,#2 /* Divide by 4 to obtain word count */ - beq SKIPVENEERCOPY - - /* The proverbial loop from the schooldays */ -VENEERCOPYLOOP: - ldr r3,[R0] - str r3,[R1] - subs r2,#1 - beq SKIPVENEERCOPY - adds r0,#4 - adds r1,#4 - b VENEERCOPYLOOP - -SKIPVENEERCOPY: - /* Update System Clock */ - ldr r0,=SystemCoreClockUpdate - blx r0 - - /* Call static constructors */ - bl __libc_init_array - - /* Branch to main */ - bl main - - /* If main returns, branch to Default_Handler. */ - b Default_Handler - - .size Reset_Handler, .-Reset_Handler - -/** -**=========================================================================== -** Program - Default_Handler -** Abstract: This code gets called when the processor receives an -** unexpected interrupt. -**=========================================================================== -*/ - .section .text.Default_Handler,"ax", %progbits -Default_Handler: - b Default_Handler - - .size Default_Handler, .-Default_Handler - -/** -**=========================================================================== -** Interrupt vector table -**=========================================================================== -*/ - .section .isr_vector,"a", %progbits - .globl InterruptVector - .type InterruptVector, %object - -InterruptVector: - .word _estack /* 0 - Stack pointer */ - .word Reset_Handler /* 1 - Reset */ - .word NMI_Handler /* 2 - NMI */ - .word HardFault_Handler /* 3 - Hard fault */ - .word CLKVAL1_SSW /* Clock configuration value */ - .word CLKVAL2_SSW /* Clock gating configuration */ - - .size InterruptVector, . - InterruptVector - -/** -**=========================================================================== -** Weak interrupt handlers redirected to Default_Handler. These can be -** overridden in user code. -**=========================================================================== -*/ - .weak NMI_Handler - .thumb_set NMI_Handler, Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler, Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler, Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler, Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler, Default_Handler - -/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ - -/* IRQ Handlers */ - .weak SCU_0_IRQHandler - .type SCU_0_IRQHandler, %function -SCU_0_IRQHandler: - B . - .size SCU_0_IRQHandler, . - SCU_0_IRQHandler -/* ======================================================================== */ - .weak SCU_1_IRQHandler - .type SCU_1_IRQHandler, %function -SCU_1_IRQHandler: - B . - .size SCU_1_IRQHandler, . - SCU_1_IRQHandler -/* ======================================================================== */ - .weak SCU_2_IRQHandler - .type SCU_2_IRQHandler, %function -SCU_2_IRQHandler: - B . - .size SCU_2_IRQHandler, . - SCU_2_IRQHandler -/* ======================================================================== */ - .weak ERU0_0_IRQHandler - .type ERU0_0_IRQHandler, %function -ERU0_0_IRQHandler: - B . - .size ERU0_0_IRQHandler, . - ERU0_0_IRQHandler -/* ======================================================================== */ - .weak ERU0_1_IRQHandler - .type ERU0_1_IRQHandler, %function -ERU0_1_IRQHandler: - B . - .size ERU0_1_IRQHandler, . - ERU0_1_IRQHandler -/* ======================================================================== */ - .weak ERU0_2_IRQHandler - .type ERU0_2_IRQHandler, %function -ERU0_2_IRQHandler: - B . - .size ERU0_2_IRQHandler, . - ERU0_2_IRQHandler -/* ======================================================================== */ - .weak ERU0_3_IRQHandler - .type ERU0_3_IRQHandler, %function -ERU0_3_IRQHandler: - B . - .size ERU0_3_IRQHandler, . - ERU0_3_IRQHandler -/* ======================================================================== */ - .weak MATH0_0_IRQHandler - .type MATH0_0_IRQHandler, %function -MATH0_0_IRQHandler: - B . - .size MATH0_0_IRQHandler, . - MATH0_0_IRQHandler -/* ======================================================================== */ - .weak VADC0_C0_0_IRQHandler - .type VADC0_C0_0_IRQHandler , %function -VADC0_C0_0_IRQHandler: - B . - .size VADC0_C0_0_IRQHandler , . - VADC0_C0_0_IRQHandler -/* ======================================================================== */ - .weak VADC0_C0_1_IRQHandler - .type VADC0_C0_1_IRQHandler , %function -VADC0_C0_1_IRQHandler: - B . - .size VADC0_C0_1_IRQHandler , . - VADC0_C0_1_IRQHandler -/* ======================================================================== */ - .weak VADC0_G0_0_IRQHandler - .type VADC0_G0_0_IRQHandler, %function -VADC0_G0_0_IRQHandler: - B . - .size VADC0_G0_0_IRQHandler, . - VADC0_G0_0_IRQHandler -/* ======================================================================== */ - .weak VADC0_G0_1_IRQHandler - .type VADC0_G0_1_IRQHandler, %function -VADC0_G0_1_IRQHandler: - B . - .size VADC0_G0_1_IRQHandler, . - VADC0_G0_1_IRQHandler -/* ======================================================================== */ - .weak VADC0_G1_0_IRQHandler - .type VADC0_G1_0_IRQHandler, %function -VADC0_G1_0_IRQHandler: - B . - .size VADC0_G1_0_IRQHandler, . - VADC0_G1_0_IRQHandler -/* ======================================================================== */ - .weak VADC0_G1_1_IRQHandler - .type VADC0_G1_1_IRQHandler, %function -VADC0_G1_1_IRQHandler: - B . - .size VADC0_G1_1_IRQHandler, . - VADC0_G1_1_IRQHandler -/* ======================================================================== */ - .weak CCU40_0_IRQHandler - .type CCU40_0_IRQHandler, %function -CCU40_0_IRQHandler: - B . - .size CCU40_0_IRQHandler, . - CCU40_0_IRQHandler -/* ======================================================================== */ - .weak CCU40_1_IRQHandler - .type CCU40_1_IRQHandler, %function - -CCU40_1_IRQHandler: - B . - .size CCU40_1_IRQHandler, . - CCU40_1_IRQHandler -/* ======================================================================== */ - .weak CCU40_2_IRQHandler - .type CCU40_2_IRQHandler, %function -CCU40_2_IRQHandler: - B . - .size CCU40_2_IRQHandler, . - CCU40_2_IRQHandler -/* ======================================================================== */ - .weak CCU40_3_IRQHandler - .type CCU40_3_IRQHandler, %function -CCU40_3_IRQHandler: - B . - .size CCU40_3_IRQHandler, . - CCU40_3_IRQHandler -/* ======================================================================== */ - .weak CCU80_0_IRQHandler - .type CCU80_0_IRQHandler, %function -CCU80_0_IRQHandler: - B . - .size CCU80_0_IRQHandler, . - CCU80_0_IRQHandler -/* ======================================================================== */ - .weak CCU80_1_IRQHandler - .type CCU80_1_IRQHandler, %function -CCU80_1_IRQHandler: - B . - .size CCU80_1_IRQHandler, . - CCU80_1_IRQHandler -/* ======================================================================== */ - .weak POSIF0_0_IRQHandler - .type POSIF0_0_IRQHandler, %function - -POSIF0_0_IRQHandler: - B . - .size POSIF0_0_IRQHandler, . - POSIF0_0_IRQHandler -/* ======================================================================== */ - .weak POSIF0_1_IRQHandler - .type POSIF0_1_IRQHandler, %function -POSIF0_1_IRQHandler: - B . - .size POSIF0_1_IRQHandler, . - POSIF0_1_IRQHandler -/* ======================================================================== */ - .weak USIC0_0_IRQHandler - .type USIC0_0_IRQHandler, %function -USIC0_0_IRQHandler: - B . - .size USIC0_0_IRQHandler, . - USIC0_0_IRQHandler -/* ======================================================================== */ - .weak USIC0_1_IRQHandler - .type USIC0_1_IRQHandler, %function -USIC0_1_IRQHandler: - B . - .size USIC0_1_IRQHandler, . - USIC0_1_IRQHandler -/* ======================================================================== */ - .weak USIC0_2_IRQHandler - .type USIC0_2_IRQHandler, %function -USIC0_2_IRQHandler: - B . - .size USIC0_2_IRQHandler, . - USIC0_2_IRQHandler -/* ======================================================================== */ - .weak USIC0_3_IRQHandler - .type USIC0_3_IRQHandler, %function -USIC0_3_IRQHandler: - B . - .size USIC0_3_IRQHandler, . - USIC0_3_IRQHandler -/* ======================================================================== */ - .weak USIC0_4_IRQHandler - .type USIC0_4_IRQHandler, %function -USIC0_4_IRQHandler: - B . - .size USIC0_4_IRQHandler, . - USIC0_4_IRQHandler -/* ======================================================================== */ - .weak USIC0_5_IRQHandler - .type USIC0_5_IRQHandler, %function -USIC0_5_IRQHandler: - B . - .size USIC0_5_IRQHandler, . - USIC0_5_IRQHandler -/* ======================================================================== */ - .weak LEDTS0_0_IRQHandler - .type LEDTS0_0_IRQHandler, %function -LEDTS0_0_IRQHandler: - B . - .size LEDTS0_0_IRQHandler, . - LEDTS0_0_IRQHandler -/* ======================================================================== */ - .weak LEDTS1_0_IRQHandler - .type LEDTS1_0_IRQHandler, %function -LEDTS1_0_IRQHandler: - B . - .size LEDTS1_0_IRQHandler, . - LEDTS1_0_IRQHandler -/* ======================================================================== */ - .weak BCCU0_0_IRQHandler - .type BCCU0_0_IRQHandler, %function -BCCU0_0_IRQHandler: - B . - .size BCCU0_0_IRQHandler, . - BCCU0_0_IRQHandler -/* ======================================================================== */ -/* ======================================================================== */ - -/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */ - .section ".XmcVeneerCode","ax",%progbits -.globl HardFault_Veneer -HardFault_Veneer: - LDR R0, =HardFault_Handler - MOV PC,R0 - .long 0 - .long 0 - .long 0 - .long 0 - .long 0 - .long 0 - .long 0 - -/* ======================================================================== */ -.globl SVC_Veneer -SVC_Veneer: - LDR R0, =SVC_Handler - MOV PC,R0 - .long 0 - .long 0 -/* ======================================================================== */ -.globl PendSV_Veneer -PendSV_Veneer: - LDR R0, =PendSV_Handler - MOV PC,R0 -/* ======================================================================== */ -.globl SysTick_Veneer -SysTick_Veneer: - LDR R0, =SysTick_Handler - MOV PC,R0 -/* ======================================================================== */ -.globl SCU_0_Veneer -SCU_0_Veneer: - LDR R0, =SCU_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl SCU_1_Veneer -SCU_1_Veneer: - LDR R0, =SCU_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl SCU_2_Veneer -SCU_2_Veneer: - LDR R0, =SCU_2_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl SCU_3_Veneer -SCU_3_Veneer: - LDR R0, =ERU0_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl SCU_4_Veneer -SCU_4_Veneer: - LDR R0, =ERU0_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl SCU_5_Veneer -SCU_5_Veneer: - LDR R0, =ERU0_2_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl SCU_6_Veneer -SCU_6_Veneer: - LDR R0, =ERU0_3_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl SCU_7_Veneer -SCU_7_Veneer: - LDR R0, =MATH0_0_IRQHandler - MOV PC,R0 - .long 0 -/* ======================================================================== */ -.globl VADC0_C0_0_Veneer -VADC0_C0_0_Veneer: - LDR R0, =VADC0_C0_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl VADC0_C0_1_Veneer -VADC0_C0_1_Veneer: - LDR R0, =VADC0_C0_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl VADC0_G0_0_Veneer -VADC0_G0_0_Veneer: - LDR R0, =VADC0_G0_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl VADC0_G0_1_Veneer -VADC0_G0_1_Veneer: - LDR R0, =VADC0_G0_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl VADC0_G1_0_Veneer -VADC0_G1_0_Veneer: - LDR R0, =VADC0_G1_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl VADC0_G1_1_Veneer -VADC0_G1_1_Veneer: - LDR R0, =VADC0_G1_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl CCU40_0_Veneer -CCU40_0_Veneer: - LDR R0, =CCU40_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl CCU40_1_Veneer -CCU40_1_Veneer: - LDR R0, =CCU40_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl CCU40_2_Veneer -CCU40_2_Veneer: - LDR R0, =CCU40_2_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl CCU40_3_Veneer -CCU40_3_Veneer: - LDR R0, =CCU40_3_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl CCU80_0_Veneer -CCU80_0_Veneer: - LDR R0, =CCU80_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl CCU80_1_Veneer -CCU80_1_Veneer: - LDR R0, =CCU80_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl POSIF0_0_Veneer -POSIF0_0_Veneer: - LDR R0, =POSIF0_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl POSIF0_1_Veneer -POSIF0_1_Veneer: - LDR R0, =POSIF0_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl USIC0_0_Veneer -USIC0_0_Veneer: - LDR R0, =USIC0_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl USIC0_1_Veneer -USIC0_1_Veneer: - LDR R0, =USIC0_1_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl USIC0_2_Veneer -USIC0_2_Veneer: - LDR R0, =USIC0_2_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl USIC0_3_Veneer -USIC0_3_Veneer: - LDR R0, =USIC0_3_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl USIC0_4_Veneer -USIC0_4_Veneer: - LDR R0, =USIC0_4_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl USIC0_5_Veneer -USIC0_5_Veneer: - LDR R0, =USIC0_5_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl LEDTS0_0_Veneer -LEDTS0_0_Veneer: - LDR R0, =LEDTS0_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ -.globl LEDTS1_0_Veneer -LEDTS1_0_Veneer: - LDR R0, =LEDTS1_0_IRQHandler - MOV PC,R0 -/* ======================================================================== */ - .globl BCCU0_0_Veneer -BCCU0_0_Veneer: - LDR R0, =BCCU0_0_IRQHandler - MOV PC,R0 - -/* ======================================================================== */ - -/* ===== Decision function queried by CMSIS startup for Clock tree setup === */ -/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock - tree setup. - - This decision routine defined here will always return TRUE. - - When overridden by a definition defined in DAVE code engine, this routine - returns FALSE indicating that the code engine has performed the clock setup -*/ - .section ".XmcStartup" - .weak AllowClkInitByStartup - .type AllowClkInitByStartup, %function -AllowClkInitByStartup: - MOVS R0,#1 - BX LR - .size AllowClkInitByStartup, . - AllowClkInitByStartup - -/* ====== Definition of the default weak SystemInit_DAVE3 function ========= -If DAVE3 requires an extended SystemInit it will create its own version of -SystemInit_DAVE3 which overrides this weak definition. Example includes -setting up of external memory interfaces. -*/ - .weak SystemInit_DAVE3 - .type SystemInit_DAVE3, %function -SystemInit_DAVE3: - NOP - BX LR - .size SystemInit_DAVE3, . - SystemInit_DAVE3 - - .end diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/xmc1000_flash.ld b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/xmc1000_flash.ld deleted file mode 100644 index 4c3bb4c35..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/xmc1000_flash.ld +++ /dev/null @@ -1,190 +0,0 @@ -/* -***************************************************************************** -** -** File : xmc1000_flash.ld -** -** Abstract : Linker script for XMC1200-T038F0200 Device with -** 200KByte FLASH, 16KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Target : Infineon XMC1000 Microcontrollers -** -** Environment : Atollic TrueSTUDIO(R) -** -** Distribution: The file is distributed “as is,” without any warranty -** of any kind. -** -** (c)Copyright Atollic AB. -** You may use this file as-is or modify it according to the needs of your -** project. This file may only be built (assembled or compiled and linked) -** using the Atollic TrueSTUDIO(R) product. The use of this file together -** with other tools than Atollic TrueSTUDIO(R) is not permitted. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20004000; /* end of 16K RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0; /* required amount of heap */ -_Min_Stack_Size = 0x80; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x10001000, LENGTH = 200K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K - MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.XmcStartup); - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - . = ALIGN(4); - eROData = . ; - - /* Initialize XMC Veneer interrupt code */ - VeneerLoadAddr = ABSOLUTE(eROData); - .VENEER_Code ABSOLUTE(0x2000000C) : - { - VeneerStart = .; - KEEP(*(.XmcVeneerCode)) /* Keep the VeneerCode */ - *(.XmcVeneerCode); - . = ALIGN(4); - VeneerEnd = .; - - } >RAM AT> FLASH - - VeneerSize = ABSOLUTE(VeneerEnd) - ABSOLUTE(VeneerStart); - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - /* MEMORY_bank1 section, code must be located here explicitly */ - /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ - .memory_b1_text : - { - *(.mb1text) /* .mb1text sections (code) */ - *(.mb1text*) /* .mb1text* sections (code) */ - *(.mb1rodata) /* read-only data (constants) */ - *(.mb1rodata*) - } >MEMORY_B1 - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cm0.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cm0.h deleted file mode 100644 index 1b6b54ef4..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cm0.h +++ /dev/null @@ -1,682 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmFunc.h deleted file mode 100644 index 139bc3c5e..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,636 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmInstr.h deleted file mode 100644 index 8946c2c49..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,688 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/FreeRTOSConfig.h deleted file mode 100644 index 7bcce204c..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/FreeRTOSConfig.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -/* Prevent C code being included by the IAR assembler. */ -#ifndef __IASMARM__ - #include - extern uint32_t SystemCoreClock; -#endif - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( SystemCoreClock ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6000 ) ) -#define configMAX_TASK_NAME_LEN ( 5 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 8 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configGENERATE_RUN_TIME_STATS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( 2 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH ( 80 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - -/* Normal assert() semantics without relying on the provision of an assert.h -header file. */ -#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } - -/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS -standard names - or at least those used in the unmodified vector table. */ -#define vPortSVCHandler SVC_Handler -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler - -#endif /* FREERTOS_CONFIG_H */ - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/RegTest_IAR.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/RegTest_IAR.s deleted file mode 100644 index 8e65a5cda..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/RegTest_IAR.s +++ /dev/null @@ -1,228 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - RSEG CODE:CODE(2) - thumb - - - EXTERN ulRegTest1LoopCounter - EXTERN ulRegTest2LoopCounter - - PUBLIC vRegTest1Task - PUBLIC vRegTest2Task - -/*-----------------------------------------------------------*/ -vRegTest1Task - - /* Fill the core registers with known values. This is only done once. */ - movs r1, #101 - movs r2, #102 - movs r3, #103 - movs r4, #104 - movs r5, #105 - movs r6, #106 - movs r7, #107 - movs r0, #108 - mov r8, r0 - movs r0, #109 - mov r9, r0 - movs r0, #110 - mov r10, r0 - movs r0, #111 - mov r11, r0 - movs r0, #112 - mov r12, r0 - movs r0, #100 - -reg1_loop - /* Repeatedly check that each register still contains the value written to - it when the task started. */ - cmp r0, #100 - bne reg1_error_loop - cmp r1, #101 - bne reg1_error_loop - cmp r2, #102 - bne reg1_error_loop - cmp r3, #103 - bne reg1_error_loop - cmp r4, #104 - bne reg1_error_loop - cmp r5, #105 - bne reg1_error_loop - cmp r6, #106 - bne reg1_error_loop - cmp r7, #107 - bne reg1_error_loop - movs r0, #108 - cmp r8, r0 - bne reg1_error_loop - movs r0, #109 - cmp r9, r0 - bne reg1_error_loop - movs r0, #110 - cmp r10, r0 - bne reg1_error_loop - movs r0, #111 - cmp r11, r0 - bne reg1_error_loop - movs r0, #112 - cmp r12, r0 - bne reg1_error_loop - - /* Everything passed, increment the loop counter. */ - push { r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r1 } - - /* Start again. */ - movs r0, #100 - b reg1_loop - -reg1_error_loop - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop - - - -vRegTest2Task - - /* Fill the core registers with known values. This is only done once. */ - movs r1, #1 - movs r2, #2 - movs r3, #3 - movs r4, #4 - movs r5, #5 - movs r6, #6 - movs r7, #7 - movs r0, #8 - mov r8, r0 - movs r0, #9 - mov r9, r0 - movs r0, #10 - mov r10, r0 - movs r0, #11 - mov r11, r0 - movs r0, #12 - mov r12, r0 - movs r0, #10 - -reg2_loop - /* Repeatedly check that each register still contains the value written to - it when the task started. */ - cmp r0, #10 - bne reg2_error_loop - cmp r1, #1 - bne reg2_error_loop - cmp r2, #2 - bne reg2_error_loop - cmp r3, #3 - bne reg2_error_loop - cmp r4, #4 - bne reg2_error_loop - cmp r5, #5 - bne reg2_error_loop - cmp r6, #6 - bne reg2_error_loop - cmp r7, #7 - bne reg2_error_loop - movs r0, #8 - cmp r8, r0 - bne reg2_error_loop - movs r0, #9 - cmp r9, r0 - bne reg2_error_loop - movs r0, #10 - cmp r10, r0 - bne reg2_error_loop - movs r0, #11 - cmp r11, r0 - bne reg2_error_loop - movs r0, #12 - cmp r12, r0 - bne reg2_error_loop - - /* Everything passed, increment the loop counter. */ - push { r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r1 } - - /* Start again. */ - movs r0, #10 - b reg2_loop - -reg2_error_loop - ;/* If this line is hit then there was an error in a core register value. - ;The loop ensures the loop counter stops incrementing. */ - b reg2_error_loop - nop - - END diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/startup_XMC1200.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/startup_XMC1200.s deleted file mode 100644 index 2de915c52..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/startup_XMC1200.s +++ /dev/null @@ -1,371 +0,0 @@ -;************************************************ -;* -;* Part one of the system initialization code, contains low-level -;* initialization, plain thumb variant. -;* -;* Copyright 2013 IAR Systems. All rights reserved. -;* -;* $Revision: 64600 $ -;* -;******************* Version History ********************************************** -; -; V6, May, 16,2013 TYS:a) Add XMC1200_SCU.inc -; -;********************************************************************************** -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; Cortex-M version -; - - MODULE ?cstartup -#ifdef DAVE_CE -#include "XMC1200_SCU.inc" -#include "Device_Data.h" -#else -#define CLKVAL1_SSW 0x00000100 -#define CLKVAL2_SSW 0x00000000 -#endif - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD 0 ; 0x8 - DCD 0 ; 0xC - DCD CLKVAL1_SSW ; 0x10 CLK_VAL1 - (CLKCR default) - DCD CLKVAL2_SSW ; 0x14 CLK_VAL2 - (CGATCLR0 default) - - SECTION .vect_table:CODE:ROOT(2) - THUMB - LDR R0,=HardFault_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=SVC_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=Undef_Handler - BX R0 - LDR R0,=PendSV_Handler - BX R0 - LDR R0,=SysTick_Handler - BX R0 - - ; External Interrupts - LDR R0,=SCU_0_IRQHandler ; Handler name for SR SCU_0 - BX R0 - LDR R0,=SCU_1_IRQHandler ; Handler name for SR SCU_1 - BX R0 - LDR R0,=SCU_2_IRQHandler ; Handler name for SR SCU_2 - BX R0 - LDR R0,=ERU0_0_IRQHandler ; Handler name for SR ERU0_0 - BX R0 - LDR R0,=ERU0_1_IRQHandler ; Handler name for SR ERU0_1 - BX R0 - LDR R0,=ERU0_2_IRQHandler ; Handler name for SR ERU0_2 - BX R0 - LDR R0,=ERU0_3_IRQHandler ; Handler name for SR ERU0_3 - BX R0 - LDR R0,=Undef_Handler ; Not Available - BX R0 - LDR R0,=Undef_Handler ; Not Available - BX R0 - LDR R0,=USIC0_0_IRQHandler ; Handler name for SR USIC0_0 - BX R0 - LDR R0,=USIC0_1_IRQHandler ; Handler name for SR USIC0_1 - BX R0 - LDR R0,=USIC0_2_IRQHandler ; Handler name for SR USIC0_2 - BX R0 - LDR R0,=USIC0_3_IRQHandler ; Handler name for SR USIC0_3 - BX R0 - LDR R0,=USIC0_4_IRQHandler ; Handler name for SR USIC0_4 - BX R0 - LDR R0,=USIC0_5_IRQHandler ; Handler name for SR USIC0_5 - BX R0 - LDR R0,=VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0 - BX R0 - LDR R0,=VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1 - BX R0 - LDR R0,=VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0 - BX R0 - LDR R0,=VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1 - BX R0 - LDR R0,=VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0 - BX R0 - LDR R0,=VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1 - BX R0 - LDR R0,=CCU40_0_IRQHandler ; Handler name for SR CCU40_0 - BX R0 - LDR R0,=CCU40_1_IRQHandler ; Handler name for SR CCU40_1 - BX R0 - LDR R0,=CCU40_2_IRQHandler ; Handler name for SR CCU40_2 - BX R0 - LDR R0,=CCU40_3_IRQHandler ; Handler name for SR CCU40_3 - BX R0 - LDR R0,=Undef_Handler ; Not Available - BX R0 - LDR R0,=Undef_Handler ; Not Available - BX R0 - LDR R0,=Undef_Handler ; Not Available - BX R0 - LDR R0,=Undef_Handler ; Not Available - BX R0 - LDR R0,=LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0 - BX R0 - LDR R0,=LEDTS1_0_IRQHandler ; Handler name for SR LEDTS1_0 - BX R0 - LDR R0,=BCCU0_0_IRQHandler ; Handler name for SR BCCU0_0 - BX R0 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - EXTERN SystemInit - SECTION .text:CODE:NOROOT(2) - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =SystemInit_DAVE3 - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK Undef_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -Undef_Handler - B Undef_Handler - - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK SCU_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SCU_0_IRQHandler - B SCU_0_IRQHandler - - PUBWEAK SCU_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SCU_1_IRQHandler - B SCU_1_IRQHandler - - - PUBWEAK SCU_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SCU_2_IRQHandler - B SCU_2_IRQHandler - - - PUBWEAK ERU0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ERU0_0_IRQHandler - B ERU0_0_IRQHandler - - - PUBWEAK ERU0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ERU0_1_IRQHandler - B ERU0_1_IRQHandler - - - PUBWEAK ERU0_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ERU0_2_IRQHandler - B ERU0_2_IRQHandler - - - PUBWEAK ERU0_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ERU0_3_IRQHandler - B ERU0_3_IRQHandler - - - PUBWEAK USIC0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USIC0_0_IRQHandler - B USIC0_0_IRQHandler - - - PUBWEAK USIC0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USIC0_1_IRQHandler - B USIC0_1_IRQHandler - - - PUBWEAK USIC0_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USIC0_2_IRQHandler - B USIC0_2_IRQHandler - - - PUBWEAK USIC0_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USIC0_3_IRQHandler - B USIC0_3_IRQHandler - - - PUBWEAK USIC0_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USIC0_4_IRQHandler - B USIC0_4_IRQHandler - - - PUBWEAK USIC0_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USIC0_5_IRQHandler - B USIC0_5_IRQHandler - - - PUBWEAK VADC0_C0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VADC0_C0_0_IRQHandler - B VADC0_C0_0_IRQHandler - - - PUBWEAK VADC0_C0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VADC0_C0_1_IRQHandler - B VADC0_C0_1_IRQHandler - - - PUBWEAK VADC0_G0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VADC0_G0_0_IRQHandler - B VADC0_G0_0_IRQHandler - - - PUBWEAK VADC0_G0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VADC0_G0_1_IRQHandler - B VADC0_G0_1_IRQHandler - - - PUBWEAK VADC0_G1_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VADC0_G1_0_IRQHandler - B VADC0_G1_0_IRQHandler - - - PUBWEAK VADC0_G1_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VADC0_G1_1_IRQHandler - B VADC0_G1_1_IRQHandler - - - PUBWEAK CCU40_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCU40_0_IRQHandler - B CCU40_0_IRQHandler - - - PUBWEAK CCU40_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCU40_1_IRQHandler - B CCU40_1_IRQHandler - - - PUBWEAK CCU40_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCU40_2_IRQHandler - B CCU40_2_IRQHandler - - - PUBWEAK CCU40_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCU40_3_IRQHandler - B CCU40_3_IRQHandler - - - PUBWEAK LEDTS0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEDTS0_0_IRQHandler - B LEDTS0_0_IRQHandler - - - PUBWEAK LEDTS1_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEDTS1_0_IRQHandler - B LEDTS1_0_IRQHandler - - - PUBWEAK BCCU0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BCCU0_0_IRQHandler - B BCCU0_0_IRQHandler - -; Definition of the default weak SystemInit_DAVE3 function -;If DAVE3 requires an extended SystemInit it will create its own version of -;SystemInit_DAVE3 which overrides this weak definition. Example includes -;setting up of external memory interfaces. - - PUBWEAK SystemInit_DAVE3 - SECTION .text:CODE:REORDER:NOROOT(2) -SystemInit_DAVE3 - NOP - BX LR - -;Decision function queried by CMSIS startup for Clock tree setup ======== */ -;In the absence of DAVE code engine, CMSIS SystemInit() must perform clock tree setup. -;This decision routine defined here will always return TRUE. -;When overridden by a definition defined in DAVE code engine, this routine -;returns FALSE indicating that the code engine has performed the clock setup - - PUBWEAK AllowClkInitByStartup - SECTION .text:CODE:REORDER:NOROOT(2) -AllowClkInitByStartup - MOVS R0,#1 - BX LR - - END diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/JLinkSettings.ini deleted file mode 100644 index de1b137f3..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/JLinkSettings.ini +++ /dev/null @@ -1,34 +0,0 @@ -[BREAKPOINTS] -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="UNSPECIFIED" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/RegTest_Keil.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/RegTest_Keil.s deleted file mode 100644 index c7158f533..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/RegTest_Keil.s +++ /dev/null @@ -1,239 +0,0 @@ -;/* -; FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. -; -; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. -; -; *************************************************************************** -; * * -; * FreeRTOS provides completely free yet professionally developed, * -; * robust, strictly quality controlled, supported, and cross * -; * platform software that has become a de facto standard. * -; * * -; * Help yourself get started quickly and support the FreeRTOS * -; * project by purchasing a FreeRTOS tutorial book, reference * -; * manual, or both from: http://www.FreeRTOS.org/Documentation * -; * * -; * Thank you! * -; * * -; *************************************************************************** -; -; This file is part of the FreeRTOS distribution. -; -; FreeRTOS is free software; you can redistribute it and/or modify it under -; the terms of the GNU General Public License (version 2) as published by the -; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. -; -; >>! NOTE: The modification to the GPL is included to allow you to distribute -; >>! a combined work that includes FreeRTOS without being obliged to provide -; >>! the source code for proprietary components outside of the FreeRTOS -; >>! kernel. -; -; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY -; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS -; FOR A PARTICULAR PURPOSE. Full license text is available from the following -; link: http://www.freertos.org/a00114.html -; -; 1 tab == 4 spaces! -; -; *************************************************************************** -; * * -; * Having a problem? Start by reading the FAQ "My application does * -; * not run, what could be wrong?" * -; * * -; * http://www.FreeRTOS.org/FAQHelp.html * -; * * -; *************************************************************************** -; -; http://www.FreeRTOS.org - Documentation, books, training, latest versions, -; license and Real Time Engineers Ltd. contact details. -; -; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, -; including FreeRTOS+Trace - an indispensable productivity tool, a DOS -; compatible FAT file system, and our tiny thread aware UDP/IP stack. -; -; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High -; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS -; licenses offer ticketed support, indemnification and middleware. -; -; http://www.SafeRTOS.com - High Integrity Systems also provide a safety -; engineered and independently SIL3 certified version for use in safety and -; mission critical applications that require provable dependability. -; -; 1 tab == 4 spaces! -;*/ - - PRESERVE8 - THUMB - - - IMPORT ulRegTest1LoopCounter - IMPORT ulRegTest2LoopCounter - - EXTERN vPortYield ;//////////////////////////////////////////////////////////////////////////////////////// - - EXPORT vRegTest1Task - EXPORT vRegTest2Task - - AREA |.text|, CODE, READONLY - -;/*-----------------------------------------------------------*/ -vRegTest1Task PROC - - ;/* Fill the core registers with known values. This is only done once. */ - movs r1, #101 - movs r2, #102 - movs r3, #103 - movs r4, #104 - movs r5, #105 - movs r6, #106 - movs r7, #107 - movs r0, #108 - mov r8, r0 - movs r0, #109 - mov r9, r0 - movs r0, #110 - mov r10, r0 - movs r0, #111 - mov r11, r0 - movs r0, #112 - mov r12, r0 - movs r0, #100 - -reg1_loop - ;/* Repeatedly check that each register still contains the value written to - ;it when the task started. */ - cmp r0, #100 - bne reg1_error_loop - cmp r1, #101 - bne reg1_error_loop - cmp r2, #102 - bne reg1_error_loop - cmp r3, #103 - bne reg1_error_loop - cmp r4, #104 - bne reg1_error_loop - cmp r5, #105 - bne reg1_error_loop - cmp r6, #106 - bne reg1_error_loop - cmp r7, #107 - bne reg1_error_loop - movs r0, #108 - cmp r8, r0 - bne reg1_error_loop - movs r0, #109 - cmp r9, r0 - bne reg1_error_loop - movs r0, #110 - cmp r10, r0 - bne reg1_error_loop - movs r0, #111 - cmp r11, r0 - bne reg1_error_loop - movs r0, #112 - cmp r12, r0 - bne reg1_error_loop - - ;/* Everything passed, increment the loop counter. */ - push { r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r1 } - - ;/* Start again. */ - movs r0, #100 - - push {r0-r1} - bl vPortYield ;;/////////////////////////////////////////////////////////////////////////////////////////////////// - pop {r0-r1} - - b reg1_loop - -reg1_error_loop - ;/* If this line is hit then there was an error in a core register value. - ;The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop - ENDP - - - -vRegTest2Task PROC - - ;/* Fill the core registers with known values. This is only done once. */ - movs r1, #1 - movs r2, #2 - movs r3, #3 - movs r4, #4 - movs r5, #5 - movs r6, #6 - movs r7, #7 - movs r0, #8 - mov r8, r0 - movs r0, #9 - mov r9, r0 - movs r0, #10 - mov r10, r0 - movs r0, #11 - mov r11, r0 - movs r0, #12 - mov r12, r0 - movs r0, #10 - -reg2_loop - ;/* Repeatedly check that each register still contains the value written to - ;it when the task started. */ - cmp r0, #10 - bne reg2_error_loop - cmp r1, #1 - bne reg2_error_loop - cmp r2, #2 - bne reg2_error_loop - cmp r3, #3 - bne reg2_error_loop - cmp r4, #4 - bne reg2_error_loop - cmp r5, #5 - bne reg2_error_loop - cmp r6, #6 - bne reg2_error_loop - cmp r7, #7 - bne reg2_error_loop - movs r0, #8 - cmp r8, r0 - bne reg2_error_loop - movs r0, #9 - cmp r9, r0 - bne reg2_error_loop - movs r0, #10 - cmp r10, r0 - bne reg2_error_loop - movs r0, #11 - cmp r11, r0 - bne reg2_error_loop - movs r0, #12 - cmp r12, r0 - bne reg2_error_loop - - ;/* Everything passed, increment the loop counter. */ - push { r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r1 } - - ;/* Start again. */ - movs r0, #10 - b reg2_loop - -reg2_error_loop - ;/* If this line is hit then there was an error in a core register value. - ;The loop ensures the loop counter stops incrementing. */ - b reg2_error_loop - nop - ENDP - - END diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/startup_XMC1300.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/startup_XMC1300.s deleted file mode 100644 index 65d38149e..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/startup_XMC1300.s +++ /dev/null @@ -1,397 +0,0 @@ -;*****************************************************************************/ -; * @file startup_XMC1300.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Infineon XMC1300 Device Series -; * @version V1.00 -; * @date 21. Jan. 2013 -; * -; * @note -; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -;* <<< Use Configuration Wizard in Context Menu >>> - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - -; Clock system handling by SSW -; CLK_VAL1 Configuration -; FDIV Fractional Divider Selection -; IDIV Divider Selection -; <0=> Divider is bypassed -; <1=> MCLK = 32 MHz -; <2=> MCLK = 16 MHz -; <3=> MCLK = 10.67 MHz -; <4=> MCLK = 8 MHz -; <254=> MCLK = 126 kHz -; <255=> MCLK = 125.5 kHz -; PCLKSEL PCLK Clock Select -; <0=> PCLK = MCLK -; <1=> PCLK = 2 x MCLK -; RTCCLKSEL RTC Clock Select -; <0=> 32.768kHz standby clock -; <1=> 32.768kHz external clock from ERU0.IOUT0 -; <2=> 32.768kHz external clock from ACMP0.OUT -; <3=> 32.768kHz external clock from ACMP1.OUT -; <4=> 32.768kHz external clock from ACMP2.OUT -; <5=> Reserved -; <6=> Reserved -; <7=> Reserved -; do not move CLK_VAL1 to SCU_CLKCR[0..19] -; -CLK_VAL1_Val EQU 0x00000100 ; 0xF0000000 - -; CLK_VAL2 Configuration -; disable VADC and SHS Gating -; disable CCU80 Gating -; disable CCU40 Gating -; disable USIC0 Gating -; disable BCCU0 Gating -; disable LEDTS0 Gating -; disable LEDTS1 Gating -; disable POSIF0 Gating -; disable MATH Gating -; disable WDT Gating -; disable RTC Gating -; do not move CLK_VAL2 to SCU_CGATCLR0[0..10] -; -CLK_VAL2_Val EQU 0x00000000 ; 0xF0000000 -; - - PRESERVE8 - THUMB - -;* ================== START OF VECTOR TABLE DEFINITION ====================== */ -;* Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - - - -__Vectors - DCD __initial_sp ;* Top of Stack - DCD Reset_Handler ;* Reset Handler - DCD 0 ;* Not used - DCD 0 ;* Not Used - DCD CLK_VAL1_Val ;* CLK_VAL1 - DCD CLK_VAL2_Val ;* CLK_VAL2 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -;* ================== END OF VECTOR TABLE DEFINITION ======================== */ - - -;* ================== START OF VECTOR ROUTINES ============================== */ - AREA |.text|, CODE, READONLY - -;* Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - ;* C routines are likely to be called. Setup the stack now - LDR R0, =__initial_sp - MOV SP, R0 - - ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself" - ; The real veneers will be copied later from the scatter loader before reaching main. - ; This init code should handle an exception before the real veneers are copied. -SRAM_BASE EQU 0x20000000 -VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B . - - LDR R1, =SRAM_BASE - LDR R2, =VENEER_INIT_CODE - MOVS R0, #48 ; Veneer 0..47 -Init_Veneers - STR R2, [R1] - ADDS R1, #4 - SUBS R0, R0, #1 - BNE Init_Veneers - - - LDR R0, =SystemInit - BLX R0 - - - ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is - ; weakly defined here though for a potential override. - - LDR R0, = SystemInit_DAVE3 - BLX R0 - - - LDR R0, =__main - BX R0 - - - ALIGN - ENDP - -;* ========================================================================== */ - - - -;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */ -;* Default exception Handlers - Users may override this default functionality - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ - - -;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ -;* IRQ Handlers - -Default_Handler PROC - EXPORT SCU_0_IRQHandler [WEAK] - EXPORT SCU_1_IRQHandler [WEAK] - EXPORT SCU_2_IRQHandler [WEAK] - EXPORT ERU0_0_IRQHandler [WEAK] - EXPORT ERU0_1_IRQHandler [WEAK] - EXPORT ERU0_2_IRQHandler [WEAK] - EXPORT ERU0_3_IRQHandler [WEAK] - EXPORT MATH0_0_IRQHandler [WEAK] - EXPORT USIC0_0_IRQHandler [WEAK] - EXPORT USIC0_1_IRQHandler [WEAK] - EXPORT USIC0_2_IRQHandler [WEAK] - EXPORT USIC0_3_IRQHandler [WEAK] - EXPORT USIC0_4_IRQHandler [WEAK] - EXPORT USIC0_5_IRQHandler [WEAK] - EXPORT VADC0_C0_0_IRQHandler [WEAK] - EXPORT VADC0_C0_1_IRQHandler [WEAK] - EXPORT VADC0_G0_0_IRQHandler [WEAK] - EXPORT VADC0_G0_1_IRQHandler [WEAK] - EXPORT VADC0_G1_0_IRQHandler [WEAK] - EXPORT VADC0_G1_1_IRQHandler [WEAK] - EXPORT CCU40_0_IRQHandler [WEAK] - EXPORT CCU40_1_IRQHandler [WEAK] - EXPORT CCU40_2_IRQHandler [WEAK] - EXPORT CCU40_3_IRQHandler [WEAK] - EXPORT CCU80_0_IRQHandler [WEAK] - EXPORT CCU80_1_IRQHandler [WEAK] - EXPORT POSIF0_0_IRQHandler [WEAK] - EXPORT POSIF0_1_IRQHandler [WEAK] - EXPORT LEDTS0_0_IRQHandler [WEAK] - EXPORT LEDTS1_0_IRQHandler [WEAK] - EXPORT BCCU0_0_IRQHandler [WEAK] - -SCU_0_IRQHandler -SCU_1_IRQHandler -SCU_2_IRQHandler -ERU0_0_IRQHandler -ERU0_1_IRQHandler -ERU0_2_IRQHandler -ERU0_3_IRQHandler -MATH0_0_IRQHandler -USIC0_0_IRQHandler -USIC0_1_IRQHandler -USIC0_2_IRQHandler -USIC0_3_IRQHandler -USIC0_4_IRQHandler -USIC0_5_IRQHandler -VADC0_C0_0_IRQHandler -VADC0_C0_1_IRQHandler -VADC0_G0_0_IRQHandler -VADC0_G0_1_IRQHandler -VADC0_G1_0_IRQHandler -VADC0_G1_1_IRQHandler -CCU40_0_IRQHandler -CCU40_1_IRQHandler -CCU40_2_IRQHandler -CCU40_3_IRQHandler -CCU80_0_IRQHandler -CCU80_1_IRQHandler -POSIF0_0_IRQHandler -POSIF0_1_IRQHandler -LEDTS0_0_IRQHandler -LEDTS1_0_IRQHandler -BCCU0_0_IRQHandler - - B . - - ENDP - - ALIGN - -;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ - -;* Definition of the default weak SystemInit_DAVE3 function. -;* This function will be called by the CMSIS SystemInit function. -;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 -;* which will overule this weak definition -SystemInit_DAVE3 PROC - EXPORT SystemInit_DAVE3 [WEAK] - NOP - BX LR - ENDP - -;* Definition of the default weak DAVE3 function for clock App usage. -;* AllowClkInitByStartup Handler */ -AllowClkInitByStartup PROC - EXPORT AllowClkInitByStartup [WEAK] - MOVS R0,#1 - BX LR - ENDP - - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - -;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */ -; Veneers are located to fix SRAM Address 0x2000'0000 - AREA |.ARM.__at_0x20000000|, CODE, READWRITE - -; Each Veneer has exactly a lengs of 4 Byte - - MACRO - STAYHERE $IrqNumber - LDR R0, =$IrqNumber - B . - MEND - - MACRO - JUMPTO $Handler - LDR R0, =$Handler - BX R0 - MEND - - STAYHERE 0x0 ;* Reserved - STAYHERE 0x1 ;* Reserved - STAYHERE 0x2 ;* Reserved - JUMPTO HardFault_Handler ;* HardFault Veneer - STAYHERE 0x4 ;* Reserved - STAYHERE 0x5 ;* Reserved - STAYHERE 0x6 ;* Reserved - STAYHERE 0x7 ;* Reserved - STAYHERE 0x8 ;* Reserved - STAYHERE 0x9 ;* Reserved - STAYHERE 0xA ;* Reserved - JUMPTO SVC_Handler ;* SVC Veneer - STAYHERE 0xC ;* Reserved - STAYHERE 0xD ;* Reserved - JUMPTO PendSV_Handler ;* PendSV Veneer - JUMPTO SysTick_Handler ;* SysTick Veneer - JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer - JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer - JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer - JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer - JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer - JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer - JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer - JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer - STAYHERE 0x18 ;* Reserved - JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer - JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer - JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer - JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer - JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer - JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer - JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer - JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer - JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer - JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer - JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer - JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer - JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer - JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer - JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer - JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer - JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer - JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer - JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer - JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer - JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer - JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer - JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer - - ALIGN - -;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */ - - END diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1100.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1100.c deleted file mode 100644 index 99884b3e9..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1100.c +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** - * @file system_XMC1100.c - * @brief Device specific initialization for the XMC1100-Series according - * to CMSIS - * @version V1.2 - * @date 13 Dec 2012 - * - * @note - * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon’s microcontrollers. - * - * This file can be freely distributed within development tools that are - * supporting such microcontrollers. - * - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -/* - * *************************** Change history ******************************** - * V1.2, 13 Dec 2012, PKB : Created change history table - */ - -#include "system_XMC1100.h" -#include - -/*--------------------------------------------------------------------------- - Extern definitions - *--------------------------------------------------------------------------*/ -extern uint32_t AllowClkInitByStartup(void); - -/*---------------------------------------------------------------------------- - Clock Global defines - *----------------------------------------------------------------------------*/ -#define DCO_DCLK 64000000UL - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* - * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE - * Clock app. - */ - if(AllowClkInitByStartup()){ - /* Do not change default values of IDIV,FDIV and RTCCLKSEL */ - /* ====== Default configuration ======= */ - /* - * MCLK = DCO_DCLK - * PCLK = MCLK - * RTC CLK = Standby clock - */ - } -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t IDIV, CLKCR; - - CLKCR = SCU_CLOCK -> CLKCR; - - IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; - - if(IDIV) - { - SystemCoreClock = DCO_DCLK / (2 * IDIV ); - } - else - { - /* Divider bypassed */ - SystemCoreClock = DCO_DCLK; - } -} - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1200.c deleted file mode 100644 index 5b06bc4c1..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1200.c +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** - * @file system_XMC1200.c - * @brief Device specific initialization for the XMC1200-Series according - * to CMSIS - * @version V1.2 - * @date 13 Dec 2012 - * - * @note - * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon’s microcontrollers. - * - * This file can be freely distributed within development tools that are - * supporting such microcontrollers. - * - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -/* - * *************************** Change history ******************************** - * V1.2, 13 Dec 2012, PKB : Created change history table - */ - -#include "System_XMC1200.h" -#include - -/*--------------------------------------------------------------------------- - Extern definitions - *--------------------------------------------------------------------------*/ -extern uint32_t AllowClkInitByStartup(void); - -/*---------------------------------------------------------------------------- - Clock Global defines - *----------------------------------------------------------------------------*/ -#define DCO_DCLK 64000000UL - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* - * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE - * Clock app. - */ - if(AllowClkInitByStartup()){ - /* Do not change default values of IDIV,FDIV and RTCCLKSEL */ - /* ====== Default configuration ======= */ - /* - * MCLK = DCO_DCLK - * PCLK = MCLK - * RTC CLK = Standby clock - */ - } -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t IDIV, CLKCR; - - CLKCR = SCU_CLOCK -> CLKCR; - - IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; - - if(IDIV) - { - SystemCoreClock = DCO_DCLK / (2 * IDIV ); - } - else - { - /* Divider bypassed */ - SystemCoreClock = DCO_DCLK; - } -} - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1300.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1300.c deleted file mode 100644 index c83e3fec6..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1300.c +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** - * @file system_XMC1300.c - * @brief Device specific initialization for the XMC1300-Series according - * to CMSIS - * @version V1.2 - * @date 13 Dec 2012 - * - * @note - * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon’s microcontrollers. - * - * This file can be freely distributed within development tools that are - * supporting such microcontrollers. - * - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -/* - * ************************** Change history ********************************* - * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_ - */ - -#include "system_XMC1300.h" -#include - -/*--------------------------------------------------------------------------- - Extern definitions - *--------------------------------------------------------------------------*/ -extern uint32_t AllowClkInitByStartup(void); - -/*---------------------------------------------------------------------------- - Clock Global defines - *----------------------------------------------------------------------------*/ -#define DCO_DCLK 64000000UL - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* - * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE - * Clock app. - */ - if(AllowClkInitByStartup()){ - /* Do not change default values of IDIV,FDIV and RTCCLKSEL */ - /* ====== Default configuration ======= */ - /* - * MCLK = DCO_DCLK - * PCLK = MCLK - * RTC CLK = Standby clock - */ - } -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t IDIV, CLKCR; - - CLKCR = SCU_CLOCK -> CLKCR; - - IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; - - if(IDIV) - { - SystemCoreClock = DCO_DCLK / (2 * IDIV ); - } - else - { - /* Divider bypassed */ - SystemCoreClock = DCO_DCLK; - } -} - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest_XMC1200.c deleted file mode 100644 index 23c64c2b1..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest_XMC1200.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/*----------------------------------------------------------- - * Simple GPIO (parallel port) IO routines. - *-----------------------------------------------------------*/ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Hardware includes. */ -#include - -/* Standard demo include. */ -#include "partest.h" - -/* The port bits on which LEDs are connected. */ -static const unsigned long ulLEDBits[] = -{ - 1UL << 0, /* P0.0 */ - 1UL << 2, /* P0.2 */ - 1UL << 5, /* P0.5 */ - 1UL << 6, /* P0.6 */ - 1UL << 7 /* P0.7 */ -}; - -#define partstNUM_LEDS ( sizeof( ulLEDBits ) / sizeof( unsigned long ) ) - -/* Shift the LED bit into the correct position within the POW register to -perform the desired operation. */ -#define partstON_SHIFT ( 16UL ) -#define partstOFF_SHIFT ( 0UL ) - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* Configure relevant port P0 to push pull output to drive LEDs. */ - - /* P0.0 */ - PORT0->IOCR0 &= ~( ( 0xFFUL << 0 ) ); - PORT0->IOCR0 |= ( 0x80UL << 0 ); - vParTestSetLED( 0, pdFALSE ); - - /* P0.2 */ - PORT0->IOCR0 &= ~( ( 0xFFUL << 16 ) ); - PORT0->IOCR0 |= ( 0x80UL << 16 ); - vParTestSetLED( 1, pdFALSE ); - - /* P0.5 */ - PORT0->IOCR4 &= ~( ( 0xFFUL << 8 ) ); - PORT0->IOCR4 |= ( 0x80UL << 8 ); - vParTestSetLED( 2, pdFALSE ); - - /* P0.6 */ - PORT0->IOCR4 &= ~( ( 0xFFUL << 16 ) ); - PORT0->IOCR4 |= ( 0x80UL << 16 ); - vParTestSetLED( 3, pdFALSE ); - - /* P0.7 */ - PORT0->IOCR4 &= ~( ( 0xFFUL << 24 ) ); - PORT0->IOCR4 |= ( 0x80UL << 24 ); - vParTestSetLED( 4, pdFALSE ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue ) -{ - if( ulLED < partstNUM_LEDS ) - { - if( xValue == pdTRUE ) - { - /* Turn the LED on. */ - PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ); - } - else - { - /* Turn the LED off. */ - PORT0->OMR = ( ulLEDBits[ ulLED ] << partstOFF_SHIFT ); - } - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned long ulLED ) -{ - if( ulLED < partstNUM_LEDS ) - { - /* Setting both the ON and OFF bits simultaneously results in the bit - being toggled. */ - PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ) | ( ulLEDBits[ ulLED ] << partstOFF_SHIFT ); - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewd deleted file mode 100644 index d1f08e34e..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewd +++ /dev/null @@ -1,1304 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - C-SPY - 2 - - 25 - 1 - 1 - - - - - - - - - - - - - - - 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- - - - - - - - - - $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewp deleted file mode 100644 index 29cfce81e..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewp +++ /dev/null @@ -1,1009 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 29 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Common Demo Source - - $PROJ_DIR$\..\Common\Minimal\blocktim.c - - - $PROJ_DIR$\..\Common\Minimal\countsem.c - - - $PROJ_DIR$\..\Common\Minimal\dynamic.c - - - $PROJ_DIR$\..\Common\Minimal\recmutex.c - - - - FreeRTOS Source - - portable - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM0\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM0\portasm.s - - - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - $PROJ_DIR$\..\..\Source\timers.c - - - - System - - $PROJ_DIR$\IAR_Specific\startup_XMC1200.s - - - $PROJ_DIR$\system_XMC1200.c - - - - $PROJ_DIR$\main-blinky.c - - - $PROJ_DIR$\main-full.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\ParTest_XMC1200.c - - - $PROJ_DIR$\IAR_Specific\RegTest_IAR.s - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.eww deleted file mode 100644 index 1ebe70f55..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.eww +++ /dev/null @@ -1,18 +0,0 @@ - - - - - $WS_DIR$\RTOSDemo.ewp - - - - All - - RTOSDemo - Debug - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.plg b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.plg deleted file mode 100644 index f059c3bab..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.plg +++ /dev/null @@ -1,48 +0,0 @@ - - -
-
µVision Build Log

-
Project:

-C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil\RTOSDemo.uvproj
-Project File Date:  08/24/2013
-
-
Output:

-Build target 'XMC1300'
-assembling startup_XMC1300.s...
-compiling timers.c...
-compiling list.c...
-compiling queue.c...
-compiling tasks.c...
-compiling port.c...
-..\..\Source\portable\RVDS\ARM_CM0\port.c(101): warning:  #1207-D: attribute "naked" ignored
-..\..\Source\portable\RVDS\ARM_CM0\port.c(103): warning:  #1207-D: attribute "naked" ignored
-..\..\Source\portable\RVDS\ARM_CM0\port.c(108): warning:  #1207-D: attribute "naked" ignored
-..\..\Source\portable\RVDS\ARM_CM0\port.c(155): warning:  #1267-D: Implicit physical register R3 should be defined as a variable
-..\..\Source\portable\RVDS\ARM_CM0\port.c(155): error:  #1086: Operand is wrong type
-..\..\Source\portable\RVDS\ARM_CM0\port.c(155): error:  #114: label "pxCurrentTCBConst2" was referenced but not defined
-..\..\Source\portable\RVDS\ARM_CM0\port.c(168): warning:  #1267-D: Implicit physical register R0 should be defined as a variable
-..\..\Source\portable\RVDS\ARM_CM0\port.c(278): warning:  #1267-D: Implicit physical register R0 should be defined as a variable
-..\..\Source\portable\RVDS\ARM_CM0\port.c(278): warning:  #1267-D: Implicit physical register R3 should be defined as a variable
-..\..\Source\portable\RVDS\ARM_CM0\port.c(278): error:  #1086: Operand is wrong type
-..\..\Source\portable\RVDS\ARM_CM0\port.c(278): error:  #114: label "pxCurrentTCBConst" was referenced but not defined
-..\..\Source\portable\RVDS\ARM_CM0\port.c(306): error:  #20: identifier "SystemCoreClock" is undefined
-compiling ParTest.c...
-compiling main.c...
-compiling main-blinky.c...
-".\RTOSDemo.axf" - 5 Errors, 7 Warning(s).
-Target not created
-Clean started: Project: 'RTOSDemo'
-   deleting intermediate output files for target 'XMC1300'
-Build target 'XMC1300'
-assembling startup_XMC1300.s...
-compiling timers.c...
-compiling list.c...
-compiling queue.c...
-compiling tasks.c...
-compiling port.c...
-..\..\Source\portable\RVDS\ARM_CM0\port.c(305): error:  #20: identifier "SystemCoreClock" is undefined
-compiling ParTest.c...
-compiling main.c...
-compiling main-blinky.c...
-".\Output\RTOSDemo.axf" - 1 Errors, 0 Warning(s).
-Target not created
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvopt
deleted file mode 100644
index 4ea6bea3b..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvopt
+++ /dev/null
@@ -1,745 +0,0 @@
-
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-  1.0
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diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvproj b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvproj
deleted file mode 100644
index 0cccd2f04..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvproj
+++ /dev/null
@@ -1,1081 +0,0 @@
-
-
-
-  1.1
-
-  
### uVision Project, (C) Keil Software

-
-  
-    
-      XMC1300
-      0x4
-      ARM-ADS
-      
-        
-          XMC1302-200
-          Infineon
-          IRAM(0x20000000-0x20003FFF) IROM(0x10001000-0x10032FFF) CLOCK(12000000) CPUTYPE("Cortex-M0")
-          
-          "STARTUP\Infineon\XMC1300\startup_XMC1300.s" ("Infineon XMC1300 Startup Code")
-          UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1300_200 -FS010001000 -FL032000)
-          6778
-          XMC1300.h
-          
-          
-          
-          
-          
-          
-          
-          
-          
-          SFD\Infineon\XMC1300\xmc1300.SFR
-          0
-          
-          
-          
-          Infineon\XMC1300\
-          Infineon\XMC1300\
-          
-            0
-            0
-            0
-            0
-            1
-          
-          .\Output\
-          RTOSDemo
-          1
-          0
-          0
-          1
-          1
-          .\
-          1
-          0
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-          0
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-          0
-          0
-          0
-          0
-          3
-          
-          
-        
-        
-          SARMCM3.DLL
-          
-          DARMCM1.DLL
-          -pCM0
-          SARMCM3.DLL
-          
-          TARMCM1.DLL
-          -pCM0
-        
-        
-          
-            1
-            0
-            0
-            0
-            16
-          
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-            1
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-            
-            
-            
-            
-          
-          
-            
-            
-            
-            
-            
-            BIN\UL2CM3.DLL
-          
-        
-        
-          
-            1
-            0
-            0
-            1
-            1
-            4096
-          
-          1
-          BIN\UL2CM3.DLL
-          "" ()
-          
-        
-        
-          
-            0
-            1
-            1
-            1
-            1
-            1
-            1
-            1
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-            1
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-            0
-            1
-            1
-            1
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-            0x10001000
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-        
-      
-      
-        
-          System
-          
-            
-              system_XMC1200.c
-              1
-              .\system_XMC1200.c
-            
-            
-              startup_XMC1300.s
-              2
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-        
-        
-          FreeRTOS source
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-              timers.c
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-            
-            
-              heap_4.c
-              1
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-            
-          
-        
-        
-          Demo App Source
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-            
-              main.c
-              1
-              .\main.c
-            
-            
-              main-blinky.c
-              1
-              .\main-blinky.c
-            
-            
-              FreeRTOSConfig.h
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-              .\FreeRTOSConfig.h
-            
-            
-              main-full.c
-              1
-              .\main-full.c
-            
-            
-              ParTest_XMC1200.c
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-                    
-                      
-                      
-                      
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-            
-            
-              RegTest_Keil.s
-              2
-              .\Keil_Specific\RegTest_Keil.s
-            
-          
-        
-        
-          Common Demo Tasks
-          
-            
-              dynamic.c
-              1
-              ..\Common\Minimal\dynamic.c
-            
-            
-              recmutex.c
-              1
-              ..\Common\Minimal\recmutex.c
-            
-            
-              blocktim.c
-              1
-              ..\Common\Minimal\blocktim.c
-            
-            
-              countsem.c
-              1
-              ..\Common\Minimal\countsem.c
-            
-          
-        
-      
-    
-    
-      XMC1200
-      0x4
-      ARM-ADS
-      
-        
-          XMC1200-200
-          Infineon
-          IRAM(0x20000000-0x20003FFF) IROM(0x10001000-0x10032FFF) CLOCK(12000000) CPUTYPE("Cortex-M0")
-          
-          "STARTUP\Infineon\XMC1200\startup_XMC1200.s" ("Infineon XMC1200 Startup Code")
-          UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000)
-          6777
-          XMC1200.h
-          
-          
-          
-          
-          
-          
-          
-          
-          
-          SFD\Infineon\XMC1200\xmc1200.SFR
-          0
-          
-          
-          
-          Infineon\XMC1200\
-          Infineon\XMC1200\
-          
-            0
-            0
-            0
-            0
-            1
-          
-          .\Output\
-          RTOSDemo
-          1
-          0
-          0
-          1
-          1
-          .\
-          1
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-            0
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-        
-          SARMCM3.DLL
-          
-          DARMCM1.DLL
-          -pCM0
-          SARMCM3.DLL
-          
-          TARMCM1.DLL
-          -pCM0
-        
-        
-          
-            1
-            0
-            0
-            0
-            16
-          
-          
-            0
-            1
-            0
-            1
-            1
-            1
-            1
-            1
-            0
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-            1
-            1
-            1
-            1
-            1
-            1
-            0
-            1
-            1
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-          0
-          7
-          
-            
-            
-            
-            
-            
-          
-          
-            
-            
-            
-            
-            
-            Segger\JL2CM3.dll
-          
-        
-        
-          
-            1
-            0
-            0
-            1
-            1
-            4100
-          
-          0
-          Segger\JL2CM3.dll
-          "" ()
-          
-        
-        
-          
-            0
-            1
-            1
-            1
-            1
-            1
-            1
-            1
-            0
-            1
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-            0
-            1
-            1
-            1
-            1
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-            1
-            1
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-            1
-            0
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-            "Cortex-M0"
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-            8
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-              --c99
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-              
-              .;..\Common\include;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;.\CMSIS
-            
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-            1
-            0
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-        
-      
-      
-        
-          System
-          
-            
-              system_XMC1200.c
-              1
-              .\system_XMC1200.c
-            
-            
-              startup_XMC1300.s
-              2
-              .\Keil_Specific\startup_XMC1300.s
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-        
-        
-          FreeRTOS source
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-            
-              timers.c
-              1
-              ..\..\Source\timers.c
-            
-            
-              list.c
-              1
-              ..\..\Source\list.c
-            
-            
-              queue.c
-              1
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-            
-            
-              tasks.c
-              1
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-            
-              port.c
-              1
-              ..\..\Source\portable\RVDS\ARM_CM0\port.c
-            
-            
-              heap_4.c
-              1
-              ..\..\Source\portable\MemMang\heap_4.c
-            
-          
-        
-        
-          Demo App Source
-          
-            
-              main.c
-              1
-              .\main.c
-            
-            
-              main-blinky.c
-              1
-              .\main-blinky.c
-            
-            
-              FreeRTOSConfig.h
-              5
-              .\FreeRTOSConfig.h
-            
-            
-              main-full.c
-              1
-              .\main-full.c
-            
-            
-              ParTest_XMC1200.c
-              1
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-                  2
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-                    2
-                    2
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-                      
-                      
-                      
-                      
-                    
-                  
-                
-              
-            
-            
-              RegTest_Keil.s
-              2
-              .\Keil_Specific\RegTest_Keil.s
-            
-          
-        
-        
-          Common Demo Tasks
-          
-            
-              dynamic.c
-              1
-              ..\Common\Minimal\dynamic.c
-            
-            
-              recmutex.c
-              1
-              ..\Common\Minimal\recmutex.c
-            
-            
-              blocktim.c
-              1
-              ..\Common\Minimal\blocktim.c
-            
-            
-              countsem.c
-              1
-              ..\Common\Minimal\countsem.c
-            
-          
-        
-      
-    
-  
-
-
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/XMC1200.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/XMC1200.h
deleted file mode 100644
index 9077f62b1..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/XMC1200.h
+++ /dev/null
@@ -1,5838 +0,0 @@
-
-/****************************************************************************************************//**
- * @file     XMC1200.h
- *
- * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for
- *           XMC1200 from Infineon.
- *
- * @version  V1.0.6 (Reference Manual v1.0)
- * @date     26. March 2013
- *
- * @note     Generated with SVDConv V2.78b 
- *           from CMSIS SVD File 'XMC1200_Processed_SVD.xml' Version 1.0.6 (Reference Manual v1.0),
- *******************************************************************************************************/
-
-
-
-/** @addtogroup Infineon
-  * @{
-  */
-
-/** @addtogroup XMC1200
-  * @{
-  */
-
-#ifndef XMC1200_H
-#define XMC1200_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* -------------------------  Interrupt Number Definition  ------------------------ */
-
-typedef enum {
-/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
-  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
-  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
-  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
-  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
-  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
-  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
-  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
-/* ---------------------  XMC1200 Specific Interrupt Numbers  --------------------- */
-  SCU_0_IRQn          =   0,   /*!< SCU SR0 Interrupt                        */
-  SCU_1_IRQn          =   1,   /*!< SCU SR1 Interrupt                        */
-  SCU_2_IRQn          =   2,   /*!< SCU SR2 Interrupt                        */
-  ERU0_0_IRQn         =   3,   /*!< ERU0 SR0 Interrupt                       */
-  ERU0_1_IRQn         =   4,   /*!< ERU0 SR1 Interrupt                       */
-  ERU0_2_IRQn         =   5,   /*!< ERU0 SR2 Interrupt                       */
-  ERU0_3_IRQn         =   6,   /*!< ERU0 SR3 Interrupt                       */
-  
-  USIC0_0_IRQn        =   9,   /*!< USIC SR0 Interrupt                       */
-  USIC0_1_IRQn        =  10,   /*!< USIC SR1 Interrupt                       */
-  USIC0_2_IRQn        =  11,   /*!< USIC SR2 Interrupt                       */
-  USIC0_3_IRQn        =  12,   /*!< USIC SR3 Interrupt                       */
-  USIC0_4_IRQn        =  13,   /*!< USIC SR4 Interrupt                       */
-  USIC0_5_IRQn        =  14,   /*!< USIC SR5 Interrupt                       */
-  
-  VADC0_C0_0_IRQn     =  15,   /*!< VADC SR0 Interrupt                       */
-  VADC0_C0_1_IRQn     =  16,   /*!< VADC SR1 Interrupt                       */
-  VADC0_G0_0_IRQn     =  17,   /*!< VADC SR2 Interrupt                       */
-  VADC0_G0_1_IRQn     =  18,   /*!< VADC SR3 Interrupt                       */
-  VADC0_G1_0_IRQn     =  19,   /*!< VADC SR4 Interrupt                       */
-  VADC0_G1_1_IRQn     =  20,   /*!< VADC SR5 Interrupt                       */
-  
-  CCU40_0_IRQn        =  21,   /*!< CCU40 SR0 Interrupt                      */
-  CCU40_1_IRQn        =  22,   /*!< CCU40 SR1 Interrupt                      */
-  CCU40_2_IRQn        =  23,   /*!< CCU40 SR2 Interrupt                      */
-  CCU40_3_IRQn        =  24,   /*!< CCU40 SR3 Interrupt                      */
-  
-  LEDTS0_0_IRQn       =  29,   /*!< LEDTS0 SR0 Interrupt                     */
-  LEDTS1_0_IRQn       =  30,   /*!< LEDTS1 SR0 Interrupt                     */
-  
-  BCCU0_0_IRQn        =  31,   /*!< BCCU0 SR0 Interrupt                      */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-
-/* ================================================================================ */
-/* ================      Processor and Core Peripheral Section     ================ */
-/* ================================================================================ */
-
-/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
-#define __CM0_REV                 0x0000            /*!< Cortex-M0 Core Revision                                               */
-#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
-#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
-#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include                                /*!< Cortex-M0 processor and core peripherals                              */
-#include "system_XMC1200.h"                         /*!< XMC1200 System                                                        */
-
-
-/* ================================================================================ */
-/* ================       Device Specific Peripheral Section       ================ */
-/* ================================================================================ */
-/* Macro to modify desired bitfields of a register */
-#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \
-		                                         ((uint32_t)mask)) | \
-                                          (reg & ((uint32_t)~((uint32_t)mask)))
-
-/* Macro to modify desired bitfields of a register */
-#define WR_REG_SIZE(reg, mask, pos, val, size) {  \
-uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \
-uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \
-uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \
-uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \
-reg = (uint##size##_t) (VAL2 | VAL4);\
-}
-
-/** Macro to read bitfields from a register */
-#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)
-
-/** Macro to read bitfields from a register */
-#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \
-                                                      (uint32_t)mask) >> pos) )
-
-/** Macro to set a bit in register */
-#define SET_BIT(reg, pos)     (reg |= ((uint32_t)1<>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-    >>! NOTE: The modification to the GPL is included to allow you to distribute
-    >>! a combined work that includes FreeRTOS without being obliged to provide
-    >>! the source code for proprietary components outside of the FreeRTOS
-    >>! kernel.
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
-    link: http://www.freertos.org/a00114.html
-
-    1 tab == 4 spaces!
-
-    ***************************************************************************
-     *                                                                       *
-     *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?"                                     *
-     *                                                                       *
-     *    http://www.FreeRTOS.org/FAQHelp.html                               *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
-    license and Real Time Engineers Ltd. contact details.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
-    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-/******************************************************************************
- * NOTE 1:  This project provides two demo applications.  A simple blinky style
- * project, and a more comprehensive test and demo application.  The
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
- * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
- * in main.c.  This file implements the simply blinky style version.
- *
- * NOTE 2:  This file only contains the source code that is specific to the
- * basic demo.  Generic functions, such FreeRTOS hook functions, and functions
- * required to configure the hardware, are defined in main.c.
- ******************************************************************************
- *
- * main_blinky() creates one queue, and two tasks.  It then starts the
- * scheduler.
- *
- * The Queue Send Task:
- * The queue send task is implemented by the prvQueueSendTask() function in
- * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly
- * block for 200 milliseconds, before sending the value 100 to the queue that
- * was created within main_blinky().  Once the value is sent, the task loops
- * back around to block for another 200 milliseconds.
- *
- * The Queue Receive Task:
- * The queue receive task is implemented by the prvQueueReceiveTask() function
- * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly
- * blocks on attempts to read data from the queue that was created within
- * main_blinky().  When data is received, the task checks the value of the
- * data, and if the value equals the expected 100, toggles LED 1.  The 'block
- * time' parameter passed to the queue receive function specifies that the
- * task should be held in the Blocked state indefinitely to wait for data to
- * be available on the queue.  The queue receive task will only leave the
- * Blocked state when the queue send task writes to the queue.  As the queue
- * send task writes to the queue every 200 milliseconds, the queue receive
- * task leaves the Blocked state every 200 milliseconds, and therefore toggles
- * the LED every 200 milliseconds.
- */
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-/* Demo includes. */
-#include "ParTest.h"
-
-/* Priorities at which the tasks are created. */
-#define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
-#define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
-
-/* The rate at which data is sent to the queue.  The 200ms value is converted
-to ticks using the portTICK_RATE_MS constant. */
-#define mainQUEUE_SEND_FREQUENCY_MS			( 200 / portTICK_RATE_MS )
-
-/* The number of items the queue can hold.  This is 1 as the receive task
-will remove items as they are added, meaning the send task should always find
-the queue empty. */
-#define mainQUEUE_LENGTH					( 1 )
-
-/* Values passed to the two tasks just to check the task parameter
-functionality. */
-#define mainQUEUE_SEND_PARAMETER			( 0x1111UL )
-#define mainQUEUE_RECEIVE_PARAMETER			( 0x22UL )
-
-/* The number of the LED that is toggled. */
-#define mainLED_TO_TOGGLE					( 0 )
-/*-----------------------------------------------------------*/
-
-/*
- * The tasks as described in the comments at the top of this file.
- */
-static void prvQueueReceiveTask( void *pvParameters );
-static void prvQueueSendTask( void *pvParameters );
-
-/*
- * Called by main() to create the simply blinky style application if
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
- */
-void main_blinky( void );
-
-/*
- * The hardware only has a single LED.  Simply toggle it.
- */
-extern void vMainToggleLED( void );
-
-/*-----------------------------------------------------------*/
-
-/* The queue used by both tasks. */
-static xQueueHandle xQueue = NULL;
-
-/*-----------------------------------------------------------*/
-
-void main_blinky( void )
-{
-	/* Create the queue. */
-	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
-
-	if( xQueue != NULL )
-	{
-		/* Start the two tasks as described in the comments at the top of this
-		file. */
-		xTaskCreate( prvQueueReceiveTask,					/* The function that implements the task. */
-					( signed char * ) "Rx", 				/* The text name assigned to the task - for debug only as it is not used by the kernel. */
-					configMINIMAL_STACK_SIZE, 				/* The size of the stack to allocate to the task. */
-					( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
-					mainQUEUE_RECEIVE_TASK_PRIORITY, 		/* The priority assigned to the task. */
-					NULL );									/* The task handle is not required, so NULL is passed. */
-
-		xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
-
-		/* Start the tasks and timer running. */
-		vTaskStartScheduler();
-	}
-
-	/* If all is well, the scheduler will now be running, and the following
-	line will never be reached.  If the following line does execute, then
-	there was insufficient FreeRTOS heap memory available for the idle and/or
-	timer tasks	to be created.  See the memory management section on the
-	FreeRTOS web site for more details. */
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-static void prvQueueSendTask( void *pvParameters )
-{
-portTickType xNextWakeTime;
-const unsigned long ulValueToSend = 100UL;
-
-	/* Check the task parameter is as expected. */
-	configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
-
-	/* Initialise xNextWakeTime - this only needs to be done once. */
-	xNextWakeTime = xTaskGetTickCount();
-
-	for( ;; )
-	{
-		/* Place this task in the blocked state until it is time to run again.
-		The block time is specified in ticks, the constant used converts ticks
-		to ms.  While in the Blocked state this task will not consume any CPU
-		time. */
-		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
-
-		/* Send to the queue - causing the queue receive task to unblock and
-		toggle the LED.  0 is used as the block time so the sending operation
-		will not block - it shouldn't need to block as the queue should always
-		be empty at this point in the code. */
-		xQueueSend( xQueue, &ulValueToSend, 0U );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvQueueReceiveTask( void *pvParameters )
-{
-unsigned long ulReceivedValue;
-
-	/* Check the task parameter is as expected. */
-	configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
-
-	for( ;; )
-	{
-		/* Wait until something arrives in the queue - this task will block
-		indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
-		FreeRTOSConfig.h. */
-		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
-
-		/*  To get here something must have been received from the queue, but
-		is it the expected value?  If it is, toggle the LED. */
-		if( ulReceivedValue == 100UL )
-		{
-			vParTestToggleLED( mainLED_TO_TOGGLE );
-			ulReceivedValue = 0U;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-full.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-full.c
deleted file mode 100644
index 8d23357c3..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-full.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
-    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that has become a de facto standard.             *
-     *                                                                       *
-     *    Help yourself get started quickly and support the FreeRTOS         *
-     *    project by purchasing a FreeRTOS tutorial book, reference          *
-     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
-     *                                                                       *
-     *    Thank you!                                                         *
-     *                                                                       *
-    ***************************************************************************
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-    >>! NOTE: The modification to the GPL is included to allow you to distribute
-    >>! a combined work that includes FreeRTOS without being obliged to provide
-    >>! the source code for proprietary components outside of the FreeRTOS
-    >>! kernel.
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
-    link: http://www.freertos.org/a00114.html
-
-    1 tab == 4 spaces!
-
-    ***************************************************************************
-     *                                                                       *
-     *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?"                                     *
-     *                                                                       *
-     *    http://www.FreeRTOS.org/FAQHelp.html                               *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
-    license and Real Time Engineers Ltd. contact details.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
-    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-/******************************************************************************
- * NOTE 1:  This project provides two demo applications.  A simple blinky style
- * project, and a more comprehensive test and demo application.  The
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
- * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
- * in main.c.  This file implements the comprehensive test and demo version.
- *
- * NOTE 2:  This file only contains the source code that is specific to the
- * full demo.  Generic functions, such FreeRTOS hook functions, and functions
- * required to configure the hardware, are defined in main.c.
- ******************************************************************************
- *
- * main_full() creates a set of standard demo tasks, some application specific
- * tasks, and four timers.  It then starts the scheduler.  The web documentation
- * provides more details of the standard demo application tasks, which provide
- * no particular functionality, but do provide a good example of how to use the
- * FreeRTOS API.
- *
- * In addition to the standard demo tasks, the following tasks and timer are
- * defined and/or created within this file:
- *
- * "Reg test" tasks - These fill the registers with known values, then check
- * that each register maintains its expected value for the lifetime of the
- * task.  Each task uses a different set of values.  The reg test tasks execute
- * with a very low priority, so get preempted very frequently.  A register
- * containing an unexpected value is indicative of an error in the context
- * switching mechanism.
- *
- * "Flash timers" - A software timer callback function is defined that does
- * nothing but toggle an LED.  Three software timers are created that each
- * use the same callback function, but each toggles a different LED at a
- * different frequency.  One software timer uses LED1, another LED2 and the
- * third LED3.
- *
- * "Check" software timer - The check timer period is initially set to three
- * seconds.  Its callback function checks that all the standard demo tasks, and
- * the register check tasks, are not only still executing, but are executing
- * without reporting any errors.  If the check timer callback discovers that a
- * task has either stalled, or reported an error, then it changes the period of
- * the check timer from the initial three seconds, to just 200ms.  The callback
- * function also toggles LED 4 each time it is called.  This provides a visual
- * indication of the system status:  If the LED toggles every three seconds,
- * then no issues have been discovered.  If the LED toggles every 200ms, then
- * an issue has been discovered with at least one task.
- */
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "timers.h"
-
-/* Common demo includes. */
-#include "blocktim.h"
-#include "countsem.h"
-#include "recmutex.h"
-#include "ParTest.h"
-#include "dynamic.h"
-
-/* The period after which the check timer will expire provided no errors have
-been reported by any of the standard demo tasks.  ms are converted to the
-equivalent in ticks using the portTICK_RATE_MS constant. */
-#define mainCHECK_TIMER_PERIOD_MS			( 3000UL / portTICK_RATE_MS )
-
-/* The period at which the check timer will expire if an error has been
-reported in one of the standard demo tasks.  ms are converted to the equivalent
-in ticks using the portTICK_RATE_MS constant. */
-#define mainERROR_CHECK_TIMER_PERIOD_MS 	( 200UL / portTICK_RATE_MS )
-
-/* A block time of zero simply means "don't block". */
-#define mainDONT_BLOCK						( 0UL )
-
-/* The base toggle rate used by the flash timers.  Each toggle rate is a
-multiple of this. */
-#define mainFLASH_TIMER_BASE_RATE			( 200UL / portTICK_RATE_MS )
-
-/* The LED toggle by the check timer. */
-#define mainCHECK_LED						( 4 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Register check tasks, as described at the top of this file.  The nature of
- * these files necessitates that they are written in an assembly.
- */
-extern void vRegTest1Task( void *pvParameters );
-extern void vRegTest2Task( void *pvParameters );
-
-/*
- * The hardware only has a single LED.  Simply toggle it.
- */
-extern void vMainToggleLED( void );
-
-/*
- * The check timer callback function, as described at the top of this file.
- */
-static void prvCheckTimerCallback( xTimerHandle xTimer );
-
-/*
- * The flash timer callback function, as described at the top of this file.
- * This callback function is assigned to three separate software timers.
- */
-static void prvFlashTimerCallback( xTimerHandle xTimer );
-
-/*
- * Called by main() to create the comprehensive test/demo application if
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not set to 1.
- */
-void main_full( void );
-
-/*-----------------------------------------------------------*/
-
-/* The following two variables are used to communicate the status of the
-register check tasks to the check software timer.  If the variables keep
-incrementing, then the register check tasks has not discovered any errors.  If
-a variable stops incrementing, then an error has been found. */
-volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
-
-/*-----------------------------------------------------------*/
-
-void main_full( void )
-{
-xTimerHandle xTimer = NULL;
-unsigned long ulTimer;
-const unsigned long ulTimersToCreate = 3L;
-/* The register test tasks are asm functions that don't use a stack.  The
-stack allocated just has to be large enough to hold the task context, and
-for the additional required for the stack overflow checking to work (if
-configured). */
-const size_t xRegTestStackSize = 25U;
-
-	/* Create the standard demo tasks */
-	vCreateBlockTimeTasks();
-	vStartCountingSemaphoreTasks();
-	vStartRecursiveMutexTasks();
-	vStartDynamicPriorityTasks();
-
-	/* Create the register test tasks as described at the top of this file.
-	These are naked functions that don't use any stack.  A stack still has
-	to be allocated to hold the task context. */
-	xTaskCreate( 	vRegTest1Task,			/* Function that implements the task. */
-					( signed char * ) "Reg1", /* Text name of the task. */
-					xRegTestStackSize,		/* Stack allocated to the task. */
-					NULL, 					/* The task parameter is not used. */
-					tskIDLE_PRIORITY, 		/* The priority to assign to the task. */
-					NULL );					/* Don't receive a handle back, it is not needed. */
-
-	xTaskCreate( 	vRegTest2Task,			/* Function that implements the task. */
-					( signed char * ) "Reg2", /* Text name of the task. */
-					xRegTestStackSize,		/* Stack allocated to the task. */
-					NULL, 					/* The task parameter is not used. */
-					tskIDLE_PRIORITY, 		/* The priority to assign to the task. */
-					NULL );					/* Don't receive a handle back, it is not needed. */
-
-	/* Create the three flash timers. */
-	for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ )
-	{
-		xTimer = xTimerCreate( 	( const signed char * ) "FlashTimer",	/* A text name, purely to help debugging. */
-								( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ),	/* The timer period, in this case 3000ms (3s). */
-								pdTRUE,									/* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
-								( void * ) ulTimer,						/* The ID is used to hold the number of the LED that will be flashed. */
-								prvFlashTimerCallback					/* The callback function that inspects the status of all the other tasks. */
-							);
-
-		if( xTimer != NULL )
-		{
-			xTimerStart( xTimer, mainDONT_BLOCK );
-		}
-	}
-
-	/* Create the software timer that performs the 'check' functionality,
-	as described at the top of this file. */
-	xTimer = xTimerCreate( 	( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
-							( mainCHECK_TIMER_PERIOD_MS ),		/* The timer period, in this case 3000ms (3s). */
-							pdTRUE,								/* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
-							( void * ) 0,						/* The ID is not used, so can be set to anything. */
-							prvCheckTimerCallback				/* The callback function that inspects the status of all the other tasks. */
-					  	);
-
-	/* If the software timer was created successfully, start it.  It won't
-	actually start running until the scheduler starts.  A block time of
-	zero is used in this call, although any value could be used as the block
-	time will be ignored because the scheduler has not started yet. */
-	if( xTimer != NULL )
-	{
-		xTimerStart( xTimer, mainDONT_BLOCK );
-	}
-
-	/* Start the kernel.  From here on, only tasks and interrupts will run. */
-	vTaskStartScheduler();
-
-	/* If all is well, the scheduler will now be running, and the following
-	line will never be reached.  If the following line does execute, then there
-	was	insufficient FreeRTOS heap memory available for the idle and/or timer
-	tasks to be created.  See the memory management section on the FreeRTOS web
-	site, or the FreeRTOS tutorial books for more details. */
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/* See the description at the top of this file. */
-static void prvCheckTimerCallback( xTimerHandle xTimer )
-{
-static long lChangedTimerPeriodAlready = pdFALSE;
-static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
-unsigned long ulErrorFound = pdFALSE;
-
-	/* Check all the demo and test tasks to ensure that they are all still
-	running, and that none have detected an error. */
-	if( xAreDynamicPriorityTasksStillRunning() != pdPASS )
-	{
-		ulErrorFound |= ( 0x01UL << 0UL );
-	}
-
-	if( xAreBlockTimeTestTasksStillRunning() != pdPASS )
-	{
-		ulErrorFound |= ( 0x01UL << 1UL );
-	}
-
-	if( xAreCountingSemaphoreTasksStillRunning() != pdPASS )
-	{
-		ulErrorFound |= ( 0x01UL << 2UL );
-	}
-
-	if( xAreRecursiveMutexTasksStillRunning() != pdPASS )
-	{
-		ulErrorFound |= ( 0x01UL << 3UL );
-	}
-
-	/* Check that the register test 1 task is still running. */
-	if( ulLastRegTest1Value == ulRegTest1LoopCounter )
-	{
-		ulErrorFound |= ( 0x01UL << 4UL );
-	}
-	ulLastRegTest1Value = ulRegTest1LoopCounter;
-
-	/* Check that the register test 2 task is still running. */
-	if( ulLastRegTest2Value == ulRegTest2LoopCounter )
-	{
-		ulErrorFound |= ( 0x01UL << 5UL );
-	}
-	ulLastRegTest2Value = ulRegTest2LoopCounter;
-
-	/* Toggle the check LED to give an indication of the system status.  If
-	the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
-	everything is ok.  A faster toggle indicates an error. */
-	vParTestToggleLED( mainCHECK_LED );
-
-	/* Have any errors been latched in ulErrorFound?  If so, shorten the
-	period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
-	This will result in an increase in the rate at which mainCHECK_LED
-	toggles. */
-	if( ulErrorFound != pdFALSE )
-	{
-		if( lChangedTimerPeriodAlready == pdFALSE )
-		{
-			lChangedTimerPeriodAlready = pdTRUE;
-
-			/* This call to xTimerChangePeriod() uses a zero block time.
-			Functions called from inside of a timer callback function must
-			*never* attempt	to block. */
-			xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvFlashTimerCallback( xTimerHandle xTimer )
-{
-unsigned long ulLED;
-
-	/* This callback function is assigned to three separate software timers.
-	Each timer toggles a different LED.  Obtain the number of the LED that
-	this timer is toggling. */
-	ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer );
-
-	/* Toggle the LED. */
-	vParTestToggleLED( ulLED );
-}
-
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main.c
deleted file mode 100644
index 6707792fe..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
-    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that has become a de facto standard.             *
-     *                                                                       *
-     *    Help yourself get started quickly and support the FreeRTOS         *
-     *    project by purchasing a FreeRTOS tutorial book, reference          *
-     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
-     *                                                                       *
-     *    Thank you!                                                         *
-     *                                                                       *
-    ***************************************************************************
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-    >>! NOTE: The modification to the GPL is included to allow you to distribute
-    >>! a combined work that includes FreeRTOS without being obliged to provide
-    >>! the source code for proprietary components outside of the FreeRTOS
-    >>! kernel.
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
-    link: http://www.freertos.org/a00114.html
-
-    1 tab == 4 spaces!
-
-    ***************************************************************************
-     *                                                                       *
-     *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?"                                     *
-     *                                                                       *
-     *    http://www.FreeRTOS.org/FAQHelp.html                               *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
-    license and Real Time Engineers Ltd. contact details.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
-    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-/******************************************************************************
- * This project provides two demo applications.  A simple blinky style project,
- * and a more comprehensive test and demo application.  The
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
- * select between the two.  The simply blinky demo is implemented and described
- * in main_blinky.c.  The more comprehensive test and demo application is
- * implemented and described in main_full.c.
- *
- * This file implements the code that is not demo specific, including the
- * hardware setup and FreeRTOS hook functions.  It also contains a dummy
- * interrupt service routine called Dummy_IRQHandler() that is provided as an
- * example of how to use interrupt safe FreeRTOS API functions (those that end
- * in "FromISR").
- *
- *****************************************************************************/
-
-
-/* Standard includes. */
-#include "string.h"
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Demo application include. */
-#include "ParTest.h"
-
-/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
-or 0 to run the more comprehensive test and demo application. */
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY	0
-
-
-/*-----------------------------------------------------------*/
-
-/*
- * Perform any application specific hardware configuration.  The clocks,
- * memory, etc. are configured before main() is called.
- */
-static void prvSetupHardware( void );
-
-/*
- * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
- * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
- */
-extern void main_blinky( void );
-extern void main_full( void );
-
-/*
- * CMSIS clock configuration function.
- */
-extern void SystemCoreClockUpdate( void );
-
-/*-----------------------------------------------------------*/
-
-int main( void )
-{
-	/* Prepare the hardware to run this demo. */
-	prvSetupHardware();
-
-	/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
-	of this file. */
-	#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
-	{
-		main_blinky();
-	}
-	#else
-	{
-		main_full();
-	}
-	#endif
-
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupHardware( void )
-{
-	SystemCoreClockUpdate();
-	vParTestInitialise();
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationMallocFailedHook( void )
-{
-	/* vApplicationMallocFailedHook() will only be called if
-	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
-	function that will get called if a call to pvPortMalloc() fails.
-	pvPortMalloc() is called internally by the kernel whenever a task, queue,
-	timer or semaphore is created.  It is also called by various parts of the
-	demo application.  If heap_1.c or heap_2.c are used, then the size of the
-	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
-	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
-	to query the size of free heap space that remains (although it does not
-	provide information on how the remaining heap might be fragmented). */
-	taskDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationIdleHook( void )
-{
-	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
-	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
-	task.  It is essential that code added to this hook function never attempts
-	to block in any way (for example, call xQueueReceive() with a block time
-	specified, or call vTaskDelay()).  If the application makes use of the
-	vTaskDelete() API function (as this demo application does) then it is also
-	important that vApplicationIdleHook() is permitted to return to its calling
-	function, because it is the responsibility of the idle task to clean up
-	memory allocated by the kernel to any task that has since been deleted. */
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
-{
-	( void ) pcTaskName;
-	( void ) pxTask;
-
-	/* Run time stack overflow checking is performed if
-	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
-	function is called if a stack overflow is detected. */
-	taskDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationTickHook( void )
-{
-	/* This function will be called by each tick interrupt if
-	configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h.  User code can be
-	added here, but the tick hook is called from an interrupt context, so
-	code must not attempt to block, and only the interrupt safe FreeRTOS API
-	functions can be used (those that end in FromISR()). */
-}
-/*-----------------------------------------------------------*/
-
-#ifdef JUST_AN_EXAMPLE_ISR
-
-void Dummy_IRQHandler(void)
-{
-long lHigherPriorityTaskWoken = pdFALSE;
-
-	/* Clear the interrupt if necessary. */
-	Dummy_ClearITPendingBit();
-
-	/* This interrupt does nothing more than demonstrate how to synchronise a
-	task with an interrupt.  A semaphore is used for this purpose.  Note
-	lHigherPriorityTaskWoken is initialised to zero. Only FreeRTOS API functions
-	that end in "FromISR" can be called from an ISR. */
-	xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
-
-	/* If there was a task that was blocked on the semaphore, and giving the
-	semaphore caused the task to unblock, and the unblocked task has a priority
-	higher than the current Running state task (the task that this interrupt
-	interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE
-	internally within xSemaphoreGiveFromISR().  Passing pdTRUE into the
-	portEND_SWITCHING_ISR() macro will result in a context switch being pended to
-	ensure this interrupt returns directly to the unblocked, higher priority,
-	task.  Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */
-	portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
-}
-
-#endif /* JUST_AN_EXAMPLE_ISR */
-
-
-
-
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.cspy.bat b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.cspy.bat
deleted file mode 100644
index 24de1fdcf..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.cspy.bat
+++ /dev/null
@@ -1,24 +0,0 @@
-@REM This batch file has been generated by the IAR Embedded Workbench
-@REM C-SPY Debugger, as an aid to preparing a command line for running
-@REM the cspybat command line utility using the appropriate settings.
-@REM
-@REM Note that this file is generated every time a new debug session
-@REM is initialized, so you may want to move or rename the file before
-@REM making changes.
-@REM
-@REM You can launch cspybat by typing the name of this batch file followed
-@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
-@REM
-@REM Read about available command line parameters in the C-SPY Debugging
-@REM Guide. Hints about additional command line parameters that may be
-@REM useful in specific cases:
-@REM   --download_only   Downloads a code image without starting a debug
-@REM                     session afterwards.
-@REM   --silent          Omits the sign-on message.
-@REM   --timeout         Limits the maximum allowed execution time.
-@REM 
-
-
-"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armjlink.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\Infineon\FlashXMC1200.board" --backend -B "--endian=little" "--cpu=Cortex-M0" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Infineon\xmc1200.ddf" "--drv_verify_download" "--semihosting" "--device=xmc1200" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=72000000,0,2000000" 
-
-
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.dni
deleted file mode 100644
index 076f53409..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.dni
+++ /dev/null
@@ -1,113 +0,0 @@
-[DebugChecksum]
-Checksum=-2111807952
-[Stack]
-FillEnabled=0
-OverflowWarningsEnabled=1
-WarningThreshold=90
-SpWarningsEnabled=1
-WarnLogOnly=1
-UseTrigger=1
-TriggerName=main
-LimitSize=0
-ByteLimit=50
-[Exceptions]
-StopOnUncaught=_ 0
-StopOnThrow=_ 0
-[CallStack]
-ShowArgs=0
-[Disassembly]
-MixedMode=1
-[JLinkDriver]
-CStepIntDis=_ 0
-[SWOTraceHWSettings]
-OverrideDefaultClocks=0
-CpuClock=72000000
-ClockAutoDetect=0
-ClockWanted=1000000
-JtagSpeed=1000000
-Prescaler=72
-TimeStampPrescIndex=0
-TimeStampPrescData=0
-PcSampCYCTAP=1
-PcSampPOSTCNT=15
-PcSampIndex=0
-DataLogMode=0
-ITMportsEnable=0
-ITMportsTermIO=0
-ITMportsLogFile=0
-ITMlogFile=$PROJ_DIR$\ITM.log
-[PowerLog]
-LogEnabled=0
-GraphEnabled=0
-ShowTimeLog=1
-ShowTimeSum=0
-Title0=I0
-Symbol0=0 4 1
-LiveEnabled=0
-LiveFile=PowerLogLive.log
-[DataLog]
-LogEnabled=0
-SumEnabled=0
-GraphEnabled=0
-ShowTimeLog=1
-ShowTimeSum=1
-[EventLog]
-LogEnabled=0
-SumEnabled=0
-GraphEnabled=0
-ShowTimeLog=1
-ShowTimeSum=1
-Title0=Ch0
-Symbol0=0 4 1
-Title1=Ch1
-Symbol1=0 4 1
-Title2=Ch2
-Symbol2=0 4 1
-Title3=Ch3
-Symbol3=0 4 1
-SumSortOrder=0
-[InterruptLog]
-LogEnabled=0
-SumEnabled=0
-GraphEnabled=0
-ShowTimeLog=1
-ShowTimeSum=1
-SumSortOrder=0
-[Log file]
-LoggingEnabled=_ 0
-LogFile=_ ""
-Category=_ 0
-[TermIOLog]
-LoggingEnabled=_ 0
-LogFile=_ ""
-[Trace2]
-Enabled=0
-ShowSource=0
-[SWOTraceWindow]
-PcSampling=0
-InterruptLogs=0
-ForcedTimeStamps=0
-EventCPI=0
-EventEXC=0
-EventFOLD=0
-EventLSU=0
-EventSLEEP=0
-[PowerProbe]
-Frequency=10000
-Probe0=I0
-ProbeSetup0=2 1 1 2 0 0
-[CallStackLog]
-Enabled=0
-[DriverProfiling]
-Enabled=0
-Mode=3
-Graph=0
-Symbiont=0
-Exclusions=
-[Disassemble mode]
-mode=0
-[Breakpoints2]
-Count=0
-[Aliases]
-Count=0
-SuppressDialog=0
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.wsdt
deleted file mode 100644
index 4df60d42c..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo.wsdt
+++ /dev/null
@@ -1,67 +0,0 @@
-
-
-
-  
-    
-  RTOSDemo/Debug
-  
-    
-      
-        
-          
-          
-          
-          
-        236272727
-      
-      
-        
-        
-        
-        
-      20121632481
-      
-    
-    
-      
-      
-    
-        
-          
-            TabID-23707-15152
-            Workspace
-            Workspace
-            
-              
-            RTOSDemoRTOSDemo/System
-          
-        
-        
-      0
-        
-          
-            TabID-19002-15240
-            Build
-            Build
-            
-          
-        
-        
-      0
-    
-      
-      
-      
-      
-    TextEditor$WS_DIR$\main.c000009955095509TextEditor$WS_DIR$\main-full.c000001117445744510100000010000001
-    
-      
-      
-      
-      
-      
-    iaridepm.enu1-2-2740310-2-2200200119048203666185714755601-2-21981682-2-216842001002381203666119048203666
-  
-
-
-
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo_Debug.jlink b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo_Debug.jlink
deleted file mode 100644
index de1b137f3..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/settings/RTOSDemo_Debug.jlink
+++ /dev/null
@@ -1,34 +0,0 @@
-[BREAKPOINTS]
-ShowInfoWin = 1
-EnableFlashBP = 2
-BPDuringExecution = 0
-[CFI]
-CFISize = 0x00
-CFIAddr = 0x00
-[CPU]
-OverrideMemMap = 0
-AllowSimulation = 1
-ScriptFile=""
-[FLASH]
-CacheExcludeSize = 0x00
-CacheExcludeAddr = 0x00
-MinNumBytesFlashDL = 0
-SkipProgOnCRCMatch = 1
-VerifyDownload = 1
-AllowCaching = 1
-EnableFlashDL = 2
-Override = 0
-Device="UNSPECIFIED"
-[GENERAL]
-WorkRAMSize = 0x00
-WorkRAMAddr = 0x00
-RAMUsageLimit = 0x00
-[SWO]
-SWOLogFile=""
-[MEM]
-RdOverrideOrMask = 0x00
-RdOverrideAndMask = 0xFFFFFFFF
-RdOverrideAddr = 0xFFFFFFFF
-WrOverrideOrMask = 0x00
-WrOverrideAndMask = 0xFFFFFFFF
-WrOverrideAddr = 0xFFFFFFFF
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1200.c
deleted file mode 100644
index 05934bb6f..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1200.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/******************************************************************************
- * @file     system_XMC1200.c
- * @brief    Device specific initialization for the XMC1200-Series according
- * to CMSIS
- * @version  V1.4
- * @date     01 Feb 2013
- *
- * @note
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
-
- *
- * @par
- * Infineon Technologies AG (Infineon) is supplying this software for use with
- * Infineon’s microcontrollers.
- *
- * This file can be freely distributed within development tools that are
- * supporting such microcontrollers.
- *
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-/*
- * *************************** Change history ********************************
- * V1.2, 13 Dec 2012, PKB : Created change history table
- * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation
- * V1.4, 01 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK
- */
-
-#include "system_XMC1200.h"
-#include 
-
-/*---------------------------------------------------------------------------
- Extern definitions
- *--------------------------------------------------------------------------*/
-extern uint32_t AllowClkInitByStartup(void);
-
-/*----------------------------------------------------------------------------
-  Clock Global defines
- *----------------------------------------------------------------------------*/
-#define DCO_DCLK                  64000000UL
-#define DCO_DCLK_MULTIPLIER       16384000UL
-#define DCO_DCLK_DIVIDER          9UL
-#define MCLK_MHZ                  32000000UL
-#define KHZ_MULTIPLIER            1000UL
-#define FRACBITS                  8UL
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */
-uint32_t SystemCoreClock;
-
-/*----------------------------------------------------------------------------
-  Fixed point math definitions
- *----------------------------------------------------------------------------*/
-typedef int32_t Q_24_8;
-typedef int32_t Q_15_0;
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-
-  /*
-   * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE
-   * Clock app.
-   */
-  if(AllowClkInitByStartup()){
-  /* Do not change default values of IDIV,FDIV and RTCCLKSEL */
-  /* ====== Default configuration ======= */
-  /*
-   * MCLK    = DCO_DCLK
-   * PCLK    = MCLK
-   * RTC CLK = Standby clock
-   */
-  }
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  * @note   -
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t IDIV, FDIV, CLKCR, Clock;
-
-  CLKCR = SCU_CLK -> CLKCR;
-  IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
-  FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;
-
-  if(IDIV)
-  {
-    /* Divider is enabled and used */
-    if(0 == FDIV)
-     {
-       /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */
-       Clock = MCLK_MHZ / IDIV;
-     }
-    else
-     {
-       /* Both integer and fractional divider must be considered */
-       /* 1. IDIV + FDIV/256 */
-       Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV;
-
-       /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */
-       Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum;
-       Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER;
-       Clock = Clock >> DCO_DCLK_DIVIDER;
-     }
-  }
-  else
-  {
-    /* Divider bypassed. Simply divide DCO_DCLK by 2 */
-    Clock = MCLK_MHZ;
-  }
-
-  /* Finally with the math class over, update SystemCoreClock */
-  SystemCoreClock = Clock;
-}
-
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1200.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1200.h
deleted file mode 100644
index 476fcfe87..000000000
--- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1200.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/******************************************************************************
- * @file     system_XMC1200.h
- * @brief    Device specific initialization for the XMC1200-Series according 
- * to CMSIS
- * @version  V1.1
- * @date     13 Dec 2012
- *
- * @note
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
-
- *
- * @par
- * Infineon Technologies AG (Infineon) is supplying this software for use with 
- * Infineon’s microcontrollers.
- *   
- * This file can be freely distributed within development tools that are 
- * supporting such microcontrollers.
- *  
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-/* 
- * **************************** Change history *******************************
- * V1.1, 13 Dec 2012, PKB : Created this table, added extern and stdint
- */
-
-#include 
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-extern uint32_t SystemCoreClock;
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void);
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  * @note   -  
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void);
-
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.cproject b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.cproject
new file mode 100644
index 000000000..7aefb8212
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.cproject
@@ -0,0 +1,135 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+							
+								
+									
+								
+							
+							
+								
+								
+								
+							
+							
+								
+								
+								
+							
+								
+							
+								
+								
+								
+							
+								
+							
+						
+					
+					
+						
+					
+					
+						
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+			
+		
+	
+	
+		
+		
+			
+		
+	
+	
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.project b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.project
new file mode 100644
index 000000000..7a0005113
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.project
@@ -0,0 +1,104 @@
+
+
+	RTOSDemo
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			Common_Demo_Source
+			2
+			virtual:/virtual
+		
+		
+			FreeRTOS_Source
+			2
+			virtual:/virtual
+		
+		
+			Common_Demo_Source/blocktim.c
+			1
+			FREERTOS_BASE/Demo/Common/Minimal/blocktim.c
+		
+		
+			Common_Demo_Source/countsem.c
+			1
+			FREERTOS_BASE/Demo/Common/Minimal/countsem.c
+		
+		
+			Common_Demo_Source/dynamic.c
+			1
+			FREERTOS_BASE/Demo/Common/Minimal/dynamic.c
+		
+		
+			Common_Demo_Source/include
+			2
+			FREERTOS_BASE/Demo/Common/include
+		
+		
+			Common_Demo_Source/recmutex.c
+			1
+			FREERTOS_BASE/Demo/Common/Minimal/recmutex.c
+		
+		
+			FreeRTOS_Source/ARM_CM0
+			2
+			FREERTOS_BASE/Source/portable/GCC/ARM_CM0
+		
+		
+			FreeRTOS_Source/heap_4.c
+			1
+			FREERTOS_BASE/Source/portable/MemMang/heap_4.c
+		
+		
+			FreeRTOS_Source/include
+			2
+			FREERTOS_BASE/Source/include
+		
+		
+			FreeRTOS_Source/list.c
+			1
+			FREERTOS_BASE/Source/list.c
+		
+		
+			FreeRTOS_Source/queue.c
+			1
+			FREERTOS_BASE/Source/queue.c
+		
+		
+			FreeRTOS_Source/tasks.c
+			1
+			FREERTOS_BASE/Source/tasks.c
+		
+		
+			FreeRTOS_Source/timers.c
+			1
+			FREERTOS_BASE/Source/timers.c
+		
+	
+	
+		
+			FREERTOS_BASE
+			$%7BPARENT-2-PROJECT_LOC%7D
+		
+	
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 000000000..669e09ab0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,11 @@
+BOARD=XMC1200_Boot_Kit
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=XMC1200-T038F0200
+MCU_VENDOR=Infineon
+MODEL=Pro
+PROBE=SEGGER J-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=4.1.0
+eclipse.preferences.version=1
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 000000000..96ff207bb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/append=true
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/append=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/RegTest.c
new file mode 100644
index 000000000..472cba864
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/RegTest.c
@@ -0,0 +1,232 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+void vRegTest1Task( void ) __attribute__((naked));
+void vRegTest2Task( void ) __attribute__((naked));
+
+void vRegTest1Task( void )
+{
+	__asm volatile
+	(
+		".extern ulRegTest1LoopCounter		\n"
+		"									\n"
+		"	/* Fill the core registers with known values. */ \n"
+		"	movs r1, #101					\n"
+		"	movs r2, #102					\n"
+		"	movs r3, #103					\n"
+		"	movs r4, #104					\n"
+		"	movs r5, #105					\n"
+		"	movs r6, #106					\n"
+		"	movs r7, #107					\n"
+		"	movs r0, #108					\n"
+		"	mov	 r8, r0						\n"
+		"	movs r0, #109					\n"
+		"	mov  r9, r0						\n"
+		"	movs r0, #110					\n"
+		"	mov	 r10, r0					\n"
+		"	movs r0, #111					\n"
+		"	mov	 r11, r0					\n"
+		"	movs r0, #112					\n"
+		"	mov  r12, r0					\n"
+		"	movs r0, #100					\n"
+		"									\n"
+		"reg1_loop:							\n"
+		"									\n"
+		"	cmp	r0, #100					\n"
+		"	bne	reg1_error_loop				\n"
+		"	cmp	r1, #101					\n"
+		"	bne	reg1_error_loop				\n"
+		"	cmp	r2, #102					\n"
+		"	bne	reg1_error_loop				\n"
+		"	cmp r3, #103					\n"
+		"	bne	reg1_error_loop				\n"
+		"	cmp	r4, #104					\n"
+		"	bne	reg1_error_loop				\n"
+		"	cmp	r5, #105					\n"
+		"	bne	reg1_error_loop				\n"
+		"	cmp	r6, #106					\n"
+		"	bne	reg1_error_loop				\n"
+		"	cmp	r7, #107					\n"
+		"	bne	reg1_error_loop				\n"
+		"	movs r0, #108					\n"
+		"	cmp	r8, r0						\n"
+		"	bne	reg1_error_loop				\n"
+		"	movs r0, #109					\n"
+		"	cmp	r9, r0						\n"
+		"	bne	reg1_error_loop				\n"
+		"	movs r0, #110					\n"
+		"	cmp	r10, r0						\n"
+		"	bne	reg1_error_loop				\n"
+		"	movs r0, #111					\n"
+		"	cmp	r11, r0						\n"
+		"	bne	reg1_error_loop				\n"
+		"	movs r0, #112					\n"
+		"	cmp	r12, r0						\n"
+		"	bne	reg1_error_loop				\n"
+		"									\n"
+		"	/* Everything passed, increment the loop counter. */ \n"
+		"	push { r1 }						\n"
+		"	ldr	r0, =ulRegTest1LoopCounter	\n"
+		"	ldr r1, [r0]					\n"
+		"	add r1, r1, #1					\n"
+		"	str r1, [r0]					\n"
+		"	pop { r1 }						\n"
+		"									\n"
+		"	/* Start again. */				\n"
+		"	movs r0, #100					\n"
+		"	b reg1_loop						\n"
+		"									\n"
+		"reg1_error_loop:					\n"
+		"	/* If this line is hit then there was an error in a core register value. 	\n"
+		"	The loop ensures the loop counter stops incrementing. */					\n"
+		"	b reg1_error_loop				\n"
+		"	nop								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRegTest2Task( void )
+{
+	__asm volatile
+	(
+		".extern ulRegTest2LoopCounter		\n"
+		"									\n"
+		"	/* Fill the core registers with known values. */ \n"
+		"	movs r1, #1						\n"
+		"	movs r2, #2						\n"
+		"	movs r3, #3						\n"
+		"	movs r4, #4						\n"
+		"	movs r5, #5						\n"
+		"	movs r6, #6						\n"
+		"	movs r7, #7						\n"
+		"	movs r0, #8						\n"
+		"	movs r8, r0						\n"
+		"	movs r0, #9						\n"
+		"	mov  r9, r0						\n"
+		"	movs r0, #10					\n"
+		"	mov	 r10, r0					\n"
+		"	movs r0, #11					\n"
+		"	mov	 r11, r0					\n"
+		"	movs r0, #12					\n"
+		"	mov  r12, r0					\n"
+		"	movs r0, #10					\n"
+		"									\n"
+		"reg2_loop:							\n"
+		"									\n"
+		"	cmp	r0, #10						\n"
+		"	bne	reg2_error_loop				\n"
+		"	cmp	r1, #1						\n"
+		"	bne	reg2_error_loop				\n"
+		"	cmp	r2, #2						\n"
+		"	bne	reg2_error_loop				\n"
+		"	cmp r3, #3						\n"
+		"	bne	reg2_error_loop				\n"
+		"	cmp	r4, #4						\n"
+		"	bne	reg2_error_loop				\n"
+		"	cmp	r5, #5						\n"
+		"	bne	reg2_error_loop				\n"
+		"	cmp	r6, #6						\n"
+		"	bne	reg2_error_loop				\n"
+		"	cmp	r7, #7						\n"
+		"	bne	reg2_error_loop				\n"
+		"	movs r0, #8						\n"
+		"	cmp	r8, r0						\n"
+		"	bne	reg2_error_loop				\n"
+		"	movs r0, #9						\n"
+		"	cmp	r9, r0						\n"
+		"	bne	reg2_error_loop				\n"
+		"	movs r0, #10					\n"
+		"	cmp	r10, r0						\n"
+		"	bne	reg2_error_loop				\n"
+		"	movs r0, #11					\n"
+		"	cmp	r11, r0						\n"
+		"	bne	reg2_error_loop				\n"
+		"	movs r0, #12					\n"
+		"	cmp	r12, r0						\n"
+		"	bne	reg2_error_loop				\n"
+		"									\n"
+		"	/* Everything passed, increment the loop counter. */ \n"
+		"	push { r1 }						\n"
+		"	ldr	r0, =ulRegTest2LoopCounter	\n"
+		"	ldr r1, [r0]					\n"
+		"	add r1, r1, #1					\n"
+		"	str r1, [r0]					\n"
+		"	pop { r1 }						\n"
+		"									\n"
+		"	/* Start again. */				\n"
+		"	movs r0, #10					\n"
+		"	b reg2_loop						\n"
+		"									\n"
+		"reg2_error_loop:					\n"
+		"	/* If this line is hit then there was an error in a core register value. 	\n"
+		"	The loop ensures the loop counter stops incrementing. */					\n"
+		"	b reg2_error_loop				\n"
+		"	nop								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/startup_XMC1200.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/startup_XMC1200.s
new file mode 100644
index 000000000..914907047
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/startup_XMC1200.s
@@ -0,0 +1,608 @@
+/**
+*****************************************************************************
+**
+**  File        : startup_XMC1200.s
+**
+**  Abstract    : This assembler file contains interrupt vector and
+**                startup code for ARM.
+**
+**  Functions   : Reset_Handler
+**                Default_Handler
+**                XMCVeneer code
+**
+**  Target      : Infineon $(DEVICE) Device 
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. This file may only be built (assembled or compiled and linked)
+**  using the Atollic TrueSTUDIO(R) product. The use of this file together
+**  with other tools than Atollic TrueSTUDIO(R) is not permitted.
+**
+*****************************************************************************
+*/
+
+#ifdef DAVE_CE
+#include 
+#else
+#define CLKVAL1_SSW 0x80000000
+#define CLKVAL2_SSW 0x80000000
+#endif
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.global Reset_Handler
+.global InterruptVector
+.global Default_Handler
+
+/* Linker script definitions */
+/* start address for the initialization values of the .data section */
+.word _sidata
+/* start address for the .data section */
+.word _sdata
+/* end address for the .data section */
+.word _edata
+/* start address for the .bss section */
+.word _sbss
+/* end address for the .bss section */
+.word _ebss
+
+.word VeneerLoadAddr
+.word VeneerStart
+.word VeneerSize
+
+
+/**
+**===========================================================================
+**  Program - Reset_Handler
+**  Abstract: This code gets called after reset.
+**===========================================================================
+*/
+  .section  .text.Reset_Handler,"ax", %progbits
+  .type Reset_Handler, %function
+Reset_Handler:
+  /* Set stack pointer */
+  ldr   r0, =_estack
+  mov   sp, r0
+
+  /* Branch to SystemInit function */
+  bl SystemInit
+
+  /* Copy data initialization values */
+  ldr r1,=_sidata
+  ldr r2,=_sdata
+  ldr r3,=_edata
+  b cmpdata
+CopyLoop:
+  ldr r0, [r1]
+  str r0, [r2]
+  adds r1, r1, #4
+  adds r2, r2, #4
+cmpdata:
+  cmp r2, r3
+  blt CopyLoop
+
+  /* Clear BSS section */
+  movs r0, #0
+  ldr r2,=_sbss
+  ldr r3,=_ebss
+  b cmpbss
+ClearLoop:
+  str r0, [r2]
+  adds r2, r2, #4
+cmpbss:
+  cmp r2, r3
+  blt ClearLoop
+
+  /* VENEER COPY */
+  /* R0 = Start address, R1 = Destination address, R2 = Size */
+  ldr r0, =VeneerLoadAddr
+  ldr r1, =VeneerStart
+  ldr r2, =VeneerSize
+
+STARTVENEERCOPY:
+  /* R2 contains byte count. Change it to word count. It is ensured in the
+     linker script that the length is always word aligned.
+  */
+  lsrs r2,r2,#2 /* Divide by 4 to obtain word count */
+  beq SKIPVENEERCOPY
+
+  /* The proverbial loop from the schooldays */
+VENEERCOPYLOOP:
+  ldr r3,[R0]
+  str r3,[R1]
+  subs r2,#1
+  beq SKIPVENEERCOPY
+  adds r0,#4
+  adds r1,#4
+  b VENEERCOPYLOOP
+
+SKIPVENEERCOPY:
+  /* Update System Clock */
+  ldr r0,=SystemCoreClockUpdate
+  blx r0
+
+  /* Call static constructors */
+  bl __libc_init_array
+
+  /* Branch to main */
+  bl main
+
+  /* If main returns, branch to Default_Handler. */
+  b Default_Handler
+
+  .size  Reset_Handler, .-Reset_Handler
+
+/**
+**===========================================================================
+**  Program - Default_Handler
+**  Abstract: This code gets called when the processor receives an
+**    unexpected interrupt.
+**===========================================================================
+*/
+  .section  .text.Default_Handler,"ax", %progbits
+Default_Handler:
+  b  Default_Handler
+
+  .size  Default_Handler, .-Default_Handler
+
+/**
+**===========================================================================
+**  Interrupt vector table
+**===========================================================================
+*/
+  .section .isr_vector,"a", %progbits
+  .globl  InterruptVector
+  .type   InterruptVector, %object
+
+InterruptVector:
+  .word _estack                   /* 0 - Stack pointer */
+  .word Reset_Handler             /* 1 - Reset */
+  .word NMI_Handler               /* 2 - NMI  */
+  .word HardFault_Handler         /* 3 - Hard fault */
+  .word CLKVAL1_SSW               /* Clock configuration value  */
+  .word CLKVAL2_SSW               /* Clock gating configuration */
+
+  .size  InterruptVector, . - InterruptVector
+
+/**
+**===========================================================================
+**  Weak interrupt handlers redirected to Default_Handler. These can be
+**  overridden in user code.
+**===========================================================================
+*/
+  .weak NMI_Handler
+  .thumb_set NMI_Handler, Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler, Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler, Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler, Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler, Default_Handler
+
+/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+/* IRQ Handlers */
+    .weak   SCU_0_IRQHandler
+    .type   SCU_0_IRQHandler, %function
+SCU_0_IRQHandler:
+    B       .
+    .size   SCU_0_IRQHandler, . - SCU_0_IRQHandler
+/* ======================================================================== */
+    .weak   SCU_1_IRQHandler
+    .type   SCU_1_IRQHandler, %function
+SCU_1_IRQHandler:
+    B       .
+    .size   SCU_1_IRQHandler, . - SCU_1_IRQHandler
+/* ======================================================================== */
+    .weak   SCU_2_IRQHandler
+    .type   SCU_2_IRQHandler, %function
+SCU_2_IRQHandler:
+    B       .
+    .size   SCU_2_IRQHandler, . - SCU_2_IRQHandler
+/* ======================================================================== */
+    .weak   ERU0_0_IRQHandler
+    .type   ERU0_0_IRQHandler, %function
+ERU0_0_IRQHandler:
+    B       .
+    .size   ERU0_0_IRQHandler, . - ERU0_0_IRQHandler
+/* ======================================================================== */
+    .weak   ERU0_1_IRQHandler
+    .type   ERU0_1_IRQHandler, %function
+ERU0_1_IRQHandler:
+    B       .
+    .size   ERU0_1_IRQHandler, . - ERU0_1_IRQHandler
+/* ======================================================================== */
+    .weak   ERU0_2_IRQHandler
+    .type   ERU0_2_IRQHandler, %function
+ERU0_2_IRQHandler:
+    B       .
+    .size   ERU0_2_IRQHandler, . - ERU0_2_IRQHandler
+/* ======================================================================== */
+    .weak   ERU0_3_IRQHandler
+    .type   ERU0_3_IRQHandler, %function
+ERU0_3_IRQHandler:
+    B       .
+    .size   ERU0_3_IRQHandler, . - ERU0_3_IRQHandler
+/* ======================================================================== */
+    .weak   MATH0_0_IRQHandler
+    .type   MATH0_0_IRQHandler, %function
+MATH0_0_IRQHandler:
+    B       .
+    .size   MATH0_0_IRQHandler, . - MATH0_0_IRQHandler
+/* ======================================================================== */
+    .weak   VADC0_C0_0_IRQHandler
+    .type   VADC0_C0_0_IRQHandler , %function
+VADC0_C0_0_IRQHandler:
+    B       .
+    .size   VADC0_C0_0_IRQHandler , . - VADC0_C0_0_IRQHandler
+/* ======================================================================== */
+    .weak   VADC0_C0_1_IRQHandler
+    .type   VADC0_C0_1_IRQHandler , %function
+VADC0_C0_1_IRQHandler:
+    B       .
+    .size   VADC0_C0_1_IRQHandler , . - VADC0_C0_1_IRQHandler
+/* ======================================================================== */
+    .weak   VADC0_G0_0_IRQHandler
+    .type   VADC0_G0_0_IRQHandler, %function
+VADC0_G0_0_IRQHandler:
+    B       .
+    .size   VADC0_G0_0_IRQHandler, . - VADC0_G0_0_IRQHandler
+/* ======================================================================== */
+    .weak   VADC0_G0_1_IRQHandler
+    .type   VADC0_G0_1_IRQHandler, %function
+VADC0_G0_1_IRQHandler:
+    B       .
+    .size   VADC0_G0_1_IRQHandler, . - VADC0_G0_1_IRQHandler
+/* ======================================================================== */
+    .weak   VADC0_G1_0_IRQHandler
+    .type   VADC0_G1_0_IRQHandler, %function
+VADC0_G1_0_IRQHandler:
+    B       .
+    .size   VADC0_G1_0_IRQHandler, . - VADC0_G1_0_IRQHandler
+/* ======================================================================== */
+    .weak   VADC0_G1_1_IRQHandler
+    .type   VADC0_G1_1_IRQHandler, %function
+VADC0_G1_1_IRQHandler:
+    B       .
+    .size   VADC0_G1_1_IRQHandler, . - VADC0_G1_1_IRQHandler
+/* ======================================================================== */
+    .weak   CCU40_0_IRQHandler
+    .type   CCU40_0_IRQHandler, %function
+CCU40_0_IRQHandler:
+    B       .
+    .size   CCU40_0_IRQHandler, . - CCU40_0_IRQHandler
+/* ======================================================================== */
+    .weak   CCU40_1_IRQHandler
+    .type   CCU40_1_IRQHandler, %function
+
+CCU40_1_IRQHandler:
+    B       .
+    .size   CCU40_1_IRQHandler, . - CCU40_1_IRQHandler
+/* ======================================================================== */
+    .weak   CCU40_2_IRQHandler
+    .type   CCU40_2_IRQHandler, %function
+CCU40_2_IRQHandler:
+    B       .
+    .size   CCU40_2_IRQHandler, . - CCU40_2_IRQHandler
+/* ======================================================================== */
+    .weak   CCU40_3_IRQHandler
+    .type   CCU40_3_IRQHandler, %function
+CCU40_3_IRQHandler:
+    B       .
+    .size   CCU40_3_IRQHandler, . - CCU40_3_IRQHandler
+/* ======================================================================== */
+    .weak   CCU80_0_IRQHandler
+    .type   CCU80_0_IRQHandler, %function
+CCU80_0_IRQHandler:
+    B       .
+    .size   CCU80_0_IRQHandler, . - CCU80_0_IRQHandler
+/* ======================================================================== */
+    .weak   CCU80_1_IRQHandler
+    .type   CCU80_1_IRQHandler, %function
+CCU80_1_IRQHandler:
+    B       .
+    .size   CCU80_1_IRQHandler, . - CCU80_1_IRQHandler
+/* ======================================================================== */
+    .weak   POSIF0_0_IRQHandler
+    .type   POSIF0_0_IRQHandler, %function
+
+POSIF0_0_IRQHandler:
+    B       .
+    .size   POSIF0_0_IRQHandler, . - POSIF0_0_IRQHandler
+/* ======================================================================== */
+    .weak   POSIF0_1_IRQHandler
+    .type   POSIF0_1_IRQHandler, %function
+POSIF0_1_IRQHandler:
+    B       .
+    .size   POSIF0_1_IRQHandler, . - POSIF0_1_IRQHandler
+/* ======================================================================== */
+    .weak   USIC0_0_IRQHandler
+    .type   USIC0_0_IRQHandler, %function
+USIC0_0_IRQHandler:
+    B       .
+    .size   USIC0_0_IRQHandler, . - USIC0_0_IRQHandler
+/* ======================================================================== */
+    .weak   USIC0_1_IRQHandler
+    .type   USIC0_1_IRQHandler, %function
+USIC0_1_IRQHandler:
+    B       .
+    .size   USIC0_1_IRQHandler, . - USIC0_1_IRQHandler
+/* ======================================================================== */
+    .weak   USIC0_2_IRQHandler
+    .type   USIC0_2_IRQHandler, %function
+USIC0_2_IRQHandler:
+    B       .
+    .size   USIC0_2_IRQHandler, . - USIC0_2_IRQHandler
+/* ======================================================================== */
+    .weak   USIC0_3_IRQHandler
+    .type   USIC0_3_IRQHandler, %function
+USIC0_3_IRQHandler:
+    B       .
+    .size   USIC0_3_IRQHandler, . - USIC0_3_IRQHandler
+/* ======================================================================== */
+    .weak   USIC0_4_IRQHandler
+    .type   USIC0_4_IRQHandler, %function
+USIC0_4_IRQHandler:
+    B       .
+    .size   USIC0_4_IRQHandler, . - USIC0_4_IRQHandler
+/* ======================================================================== */
+    .weak   USIC0_5_IRQHandler
+    .type   USIC0_5_IRQHandler, %function
+USIC0_5_IRQHandler:
+    B       .
+    .size   USIC0_5_IRQHandler, . - USIC0_5_IRQHandler
+/* ======================================================================== */
+    .weak   LEDTS0_0_IRQHandler
+    .type   LEDTS0_0_IRQHandler, %function
+LEDTS0_0_IRQHandler:
+    B       .
+    .size   LEDTS0_0_IRQHandler, . - LEDTS0_0_IRQHandler
+/* ======================================================================== */
+    .weak   LEDTS1_0_IRQHandler
+    .type   LEDTS1_0_IRQHandler, %function
+LEDTS1_0_IRQHandler:
+    B       .
+    .size   LEDTS1_0_IRQHandler, . - LEDTS1_0_IRQHandler
+/* ======================================================================== */
+    .weak   BCCU0_0_IRQHandler
+    .type   BCCU0_0_IRQHandler, %function
+BCCU0_0_IRQHandler:
+    B       .
+    .size   BCCU0_0_IRQHandler, . - BCCU0_0_IRQHandler
+/* ======================================================================== */
+/* ======================================================================== */
+
+/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */
+    .section ".XmcVeneerCode","ax",%progbits
+.globl HardFault_Veneer
+HardFault_Veneer:
+    LDR R0, =HardFault_Handler
+    MOV PC,R0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+
+/* ======================================================================== */
+.globl SVC_Veneer
+SVC_Veneer:
+    LDR R0, =SVC_Handler
+    MOV PC,R0
+    .long 0
+    .long 0
+/* ======================================================================== */
+.globl PendSV_Veneer
+PendSV_Veneer:
+    LDR R0, =PendSV_Handler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SysTick_Veneer
+SysTick_Veneer:
+    LDR R0, =SysTick_Handler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SCU_0_Veneer
+SCU_0_Veneer:
+    LDR R0, =SCU_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SCU_1_Veneer
+SCU_1_Veneer:
+    LDR R0, =SCU_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SCU_2_Veneer
+SCU_2_Veneer:
+    LDR R0, =SCU_2_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SCU_3_Veneer
+SCU_3_Veneer:
+    LDR R0, =ERU0_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SCU_4_Veneer
+SCU_4_Veneer:
+    LDR R0, =ERU0_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SCU_5_Veneer
+SCU_5_Veneer:
+    LDR R0, =ERU0_2_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SCU_6_Veneer
+SCU_6_Veneer:
+    LDR R0, =ERU0_3_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl SCU_7_Veneer
+SCU_7_Veneer:
+    LDR R0, =MATH0_0_IRQHandler
+    MOV PC,R0
+    .long 0
+/* ======================================================================== */
+.globl VADC0_C0_0_Veneer
+VADC0_C0_0_Veneer:
+    LDR R0, =VADC0_C0_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_C0_1_Veneer
+VADC0_C0_1_Veneer:
+    LDR R0, =VADC0_C0_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G0_0_Veneer
+VADC0_G0_0_Veneer:
+    LDR R0, =VADC0_G0_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G0_1_Veneer
+VADC0_G0_1_Veneer:
+    LDR R0, =VADC0_G0_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G1_0_Veneer
+VADC0_G1_0_Veneer:
+    LDR R0, =VADC0_G1_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G1_1_Veneer
+VADC0_G1_1_Veneer:
+    LDR R0, =VADC0_G1_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_0_Veneer
+CCU40_0_Veneer:
+    LDR R0, =CCU40_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_1_Veneer
+CCU40_1_Veneer:
+    LDR R0, =CCU40_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_2_Veneer
+CCU40_2_Veneer:
+    LDR R0, =CCU40_2_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_3_Veneer
+CCU40_3_Veneer:
+    LDR R0, =CCU40_3_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl CCU80_0_Veneer
+CCU80_0_Veneer:
+    LDR R0, =CCU80_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl CCU80_1_Veneer
+CCU80_1_Veneer:
+    LDR R0, =CCU80_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl POSIF0_0_Veneer
+POSIF0_0_Veneer:
+    LDR R0, =POSIF0_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl POSIF0_1_Veneer
+POSIF0_1_Veneer:
+    LDR R0, =POSIF0_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_0_Veneer
+USIC0_0_Veneer:
+    LDR R0, =USIC0_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_1_Veneer
+USIC0_1_Veneer:
+    LDR R0, =USIC0_1_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_2_Veneer
+USIC0_2_Veneer:
+    LDR R0, =USIC0_2_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_3_Veneer
+USIC0_3_Veneer:
+    LDR R0, =USIC0_3_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_4_Veneer
+USIC0_4_Veneer:
+    LDR R0, =USIC0_4_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_5_Veneer
+USIC0_5_Veneer:
+    LDR R0, =USIC0_5_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl LEDTS0_0_Veneer
+LEDTS0_0_Veneer:
+    LDR R0, =LEDTS0_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+.globl LEDTS1_0_Veneer
+LEDTS1_0_Veneer:
+    LDR R0, =LEDTS1_0_IRQHandler
+    MOV PC,R0
+/* ======================================================================== */
+    .globl BCCU0_0_Veneer
+BCCU0_0_Veneer:
+    LDR R0, =BCCU0_0_IRQHandler
+    MOV PC,R0
+
+/* ======================================================================== */
+
+/* ===== Decision function queried by CMSIS startup for Clock tree setup === */
+/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
+   tree setup.
+
+   This decision routine defined here will always return TRUE.
+
+   When overridden by a definition defined in DAVE code engine, this routine
+   returns FALSE indicating that the code engine has performed the clock setup
+*/
+     .section ".XmcStartup"
+    .weak   AllowClkInitByStartup
+    .type   AllowClkInitByStartup, %function
+AllowClkInitByStartup:
+    MOVS R0,#1
+    BX LR
+    .size   AllowClkInitByStartup, . - AllowClkInitByStartup
+
+/* ======  Definition of the default weak SystemInit_DAVE3 function =========
+If DAVE3 requires an extended SystemInit it will create its own version of
+SystemInit_DAVE3 which overrides this weak definition. Example includes
+setting up of external memory interfaces.
+*/
+     .weak SystemInit_DAVE3
+     .type SystemInit_DAVE3, %function
+SystemInit_DAVE3:
+     NOP
+     BX LR
+     .size SystemInit_DAVE3, . - SystemInit_DAVE3
+
+  .end
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/xmc1000_flash.ld b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/xmc1000_flash.ld
new file mode 100644
index 000000000..4c3bb4c35
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/xmc1000_flash.ld
@@ -0,0 +1,190 @@
+/*
+*****************************************************************************
+**
+**  File        : xmc1000_flash.ld
+**
+**  Abstract    : Linker script for XMC1200-T038F0200 Device with
+**                200KByte FLASH, 16KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**  Target      : Infineon XMC1000 Microcontrollers
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. This file may only be built (assembled or compiled and linked)
+**  using the Atollic TrueSTUDIO(R) product. The use of this file together
+**  with other tools than Atollic TrueSTUDIO(R) is not permitted.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000;    /* end of 16K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x80; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)     : ORIGIN = 0x10001000, LENGTH = 200K
+  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 16K
+  MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.XmcStartup);
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+  
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  . = ALIGN(4);
+  eROData = . ;
+
+  /* Initialize XMC Veneer interrupt code */ 
+  VeneerLoadAddr = ABSOLUTE(eROData);
+  .VENEER_Code ABSOLUTE(0x2000000C) : 
+  {
+    VeneerStart = .;
+    KEEP(*(.XmcVeneerCode)) /* Keep the VeneerCode */
+    *(.XmcVeneerCode);
+    . = ALIGN(4);
+    VeneerEnd = .;
+    
+  } >RAM AT> FLASH
+
+  VeneerSize = ABSOLUTE(VeneerEnd) - ABSOLUTE(VeneerStart);
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cm0.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cm0.h
new file mode 100644
index 000000000..1b6b54ef4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cm0.h
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include                       /* standard types definitions                      */
+#include                 /* Core Instruction Access                         */
+#include                  /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
+    function SysTick_Config is not included. In this case, the file device.h
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cmFunc.h
new file mode 100644
index 000000000..139bc3c5e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include 
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cmInstr.h
new file mode 100644
index 000000000..8946c2c49
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/CMSIS/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include 
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/FreeRTOSConfig.h
new file mode 100644
index 000000000..7bcce204c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/FreeRTOSConfig.h
@@ -0,0 +1,139 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* Prevent C code being included by the IAR assembler. */
+#ifndef __IASMARM__
+	#include 
+	extern uint32_t SystemCoreClock;
+#endif
+
+#define configUSE_PREEMPTION			1
+#define configUSE_IDLE_HOOK				0
+#define configUSE_TICK_HOOK				0
+#define configCPU_CLOCK_HZ				( SystemCoreClock )
+#define configTICK_RATE_HZ				( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES			( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE		( ( unsigned short ) 60 )
+#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 6000 ) )
+#define configMAX_TASK_NAME_LEN			( 5 )
+#define configUSE_TRACE_FACILITY		1
+#define configUSE_16_BIT_TICKS			0
+#define configIDLE_SHOULD_YIELD			1
+#define configUSE_MUTEXES				1
+#define configQUEUE_REGISTRY_SIZE		8
+#define configCHECK_FOR_STACK_OVERFLOW	2
+#define configUSE_RECURSIVE_MUTEXES		1
+#define configUSE_MALLOC_FAILED_HOOK	1
+#define configUSE_APPLICATION_TASK_TAG	0
+#define configUSE_COUNTING_SEMAPHORES	1
+#define configGENERATE_RUN_TIME_STATS	0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 			0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY		( 2 )
+#define configTIMER_QUEUE_LENGTH		5
+#define configTIMER_TASK_STACK_DEPTH	( 80 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	1
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names - or at least those used in the unmodified vector table. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/RegTest_IAR.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/RegTest_IAR.s
new file mode 100644
index 000000000..8e65a5cda
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/RegTest_IAR.s
@@ -0,0 +1,228 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+
+	EXTERN ulRegTest1LoopCounter
+	EXTERN ulRegTest2LoopCounter
+
+	PUBLIC vRegTest1Task
+	PUBLIC vRegTest2Task
+
+/*-----------------------------------------------------------*/
+vRegTest1Task
+
+	/* Fill the core registers with known values.  This is only done once. */
+	movs r1, #101
+	movs r2, #102
+	movs r3, #103
+	movs r4, #104
+	movs r5, #105
+	movs r6, #106
+	movs r7, #107
+	movs r0, #108
+	mov	 r8, r0
+	movs r0, #109
+	mov  r9, r0
+	movs r0, #110
+	mov	 r10, r0
+	movs r0, #111
+	mov	 r11, r0
+	movs r0, #112
+	mov  r12, r0
+	movs r0, #100
+
+reg1_loop
+	/* Repeatedly check that each register still contains the value written to
+	it when the task started. */
+	cmp	r0, #100
+	bne	reg1_error_loop
+	cmp	r1, #101
+	bne	reg1_error_loop
+	cmp	r2, #102
+	bne	reg1_error_loop
+	cmp r3, #103
+	bne	reg1_error_loop
+	cmp	r4, #104
+	bne	reg1_error_loop
+	cmp	r5, #105
+	bne	reg1_error_loop
+	cmp	r6, #106
+	bne	reg1_error_loop
+	cmp	r7, #107
+	bne	reg1_error_loop
+	movs r0, #108
+	cmp	r8, r0
+	bne	reg1_error_loop
+	movs r0, #109
+	cmp	r9, r0
+	bne	reg1_error_loop
+	movs r0, #110
+	cmp	r10, r0
+	bne	reg1_error_loop
+	movs r0, #111
+	cmp	r11, r0
+	bne	reg1_error_loop
+	movs r0, #112
+	cmp	r12, r0
+	bne	reg1_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	push { r1 }
+	ldr	r0, =ulRegTest1LoopCounter
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+	pop { r1 }
+
+	/* Start again. */
+	movs r0, #100
+	b reg1_loop
+
+reg1_error_loop
+	/* If this line is hit then there was an error in a core register value.
+	The loop ensures the loop counter stops incrementing. */
+	b reg1_error_loop
+	nop
+
+
+
+vRegTest2Task
+
+	/* Fill the core registers with known values.  This is only done once. */
+	movs r1, #1
+	movs r2, #2
+	movs r3, #3
+	movs r4, #4
+	movs r5, #5
+	movs r6, #6
+	movs r7, #7
+	movs r0, #8
+	mov	r8, r0
+	movs r0, #9
+	mov r9, r0
+	movs r0, #10
+	mov	r10, r0
+	movs r0, #11
+	mov	r11, r0
+	movs r0, #12
+	mov r12, r0
+	movs r0, #10
+
+reg2_loop
+	/* Repeatedly check that each register still contains the value written to
+	it when the task started. */
+	cmp	r0, #10
+	bne	reg2_error_loop
+	cmp	r1, #1
+	bne	reg2_error_loop
+	cmp	r2, #2
+	bne	reg2_error_loop
+	cmp r3, #3
+	bne	reg2_error_loop
+	cmp	r4, #4
+	bne	reg2_error_loop
+	cmp	r5, #5
+	bne	reg2_error_loop
+	cmp	r6, #6
+	bne	reg2_error_loop
+	cmp	r7, #7
+	bne	reg2_error_loop
+	movs r0, #8
+	cmp	r8, r0
+	bne	reg2_error_loop
+	movs r0, #9
+	cmp	r9, r0
+	bne	reg2_error_loop
+	movs r0, #10
+	cmp	r10, r0
+	bne	reg2_error_loop
+	movs r0, #11
+	cmp	r11, r0
+	bne	reg2_error_loop
+	movs r0, #12
+	cmp	r12, r0
+	bne	reg2_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	push { r1 }
+	ldr	r0, =ulRegTest2LoopCounter
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+	pop { r1 }
+
+	/* Start again. */
+	movs r0, #10
+	b reg2_loop
+
+reg2_error_loop
+	;/* If this line is hit then there was an error in a core register value.
+	;The loop ensures the loop counter stops incrementing. */
+	b reg2_error_loop
+	nop
+
+	END
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/startup_XMC1200.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/startup_XMC1200.s
new file mode 100644
index 000000000..2de915c52
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/IAR_Specific/startup_XMC1200.s
@@ -0,0 +1,371 @@
+;************************************************
+;*
+;* Part one of the system initialization code, contains low-level
+;* initialization, plain thumb variant.
+;*
+;* Copyright 2013 IAR Systems. All rights reserved.
+;*
+;* $Revision: 64600 $
+;*
+;******************* Version History **********************************************
+;
+;  V6, May, 16,2013 TYS:a) Add XMC1200_SCU.inc
+;
+;**********************************************************************************
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+#ifdef DAVE_CE
+#include "XMC1200_SCU.inc"
+#include "Device_Data.h"
+#else
+#define CLKVAL1_SSW 0x00000100
+#define CLKVAL2_SSW 0x00000000
+#endif
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     0                         ; 0x8
+        DCD     0                         ; 0xC
+        DCD     CLKVAL1_SSW               ; 0x10 CLK_VAL1 - (CLKCR default)
+        DCD     CLKVAL2_SSW               ; 0x14 CLK_VAL2 - (CGATCLR0 default)
+
+        SECTION .vect_table:CODE:ROOT(2)
+        THUMB
+        LDR     R0,=HardFault_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=SVC_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=Undef_Handler
+        BX      R0
+        LDR     R0,=PendSV_Handler
+        BX      R0
+        LDR     R0,=SysTick_Handler
+        BX      R0
+
+        ; External Interrupts
+        LDR     R0,=SCU_0_IRQHandler      ; Handler name for SR SCU_0
+        BX      R0
+        LDR     R0,=SCU_1_IRQHandler      ; Handler name for SR SCU_1
+        BX      R0
+        LDR     R0,=SCU_2_IRQHandler      ; Handler name for SR SCU_2
+        BX      R0
+        LDR     R0,=ERU0_0_IRQHandler     ; Handler name for SR ERU0_0
+        BX      R0
+        LDR     R0,=ERU0_1_IRQHandler     ; Handler name for SR ERU0_1
+        BX      R0
+        LDR     R0,=ERU0_2_IRQHandler     ; Handler name for SR ERU0_2
+        BX      R0
+        LDR     R0,=ERU0_3_IRQHandler     ; Handler name for SR ERU0_3
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=USIC0_0_IRQHandler    ; Handler name for SR USIC0_0
+        BX      R0
+        LDR     R0,=USIC0_1_IRQHandler    ; Handler name for SR USIC0_1
+        BX      R0
+        LDR     R0,=USIC0_2_IRQHandler    ; Handler name for SR USIC0_2
+        BX      R0
+        LDR     R0,=USIC0_3_IRQHandler    ; Handler name for SR USIC0_3
+        BX      R0
+        LDR     R0,=USIC0_4_IRQHandler    ; Handler name for SR USIC0_4
+        BX      R0
+        LDR     R0,=USIC0_5_IRQHandler    ; Handler name for SR USIC0_5
+        BX      R0
+        LDR     R0,=VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
+        BX      R0
+        LDR     R0,=VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
+        BX      R0
+        LDR     R0,=VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
+        BX      R0
+        LDR     R0,=VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
+        BX      R0
+        LDR     R0,=VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
+        BX      R0
+        LDR     R0,=VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
+        BX      R0
+        LDR     R0,=CCU40_0_IRQHandler    ; Handler name for SR CCU40_0
+        BX      R0
+        LDR     R0,=CCU40_1_IRQHandler    ; Handler name for SR CCU40_1
+        BX      R0
+        LDR     R0,=CCU40_2_IRQHandler    ; Handler name for SR CCU40_2
+        BX      R0
+        LDR     R0,=CCU40_3_IRQHandler    ; Handler name for SR CCU40_3
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=Undef_Handler         ; Not Available
+        BX      R0
+        LDR     R0,=LEDTS0_0_IRQHandler   ; Handler name for SR LEDTS0_0
+        BX      R0
+        LDR     R0,=LEDTS1_0_IRQHandler   ; Handler name for SR LEDTS1_0
+        BX      R0
+        LDR     R0,=BCCU0_0_IRQHandler    ; Handler name for SR BCCU0_0
+        BX      R0
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        EXTERN  SystemInit
+        SECTION .text:CODE:NOROOT(2)
+
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =SystemInit_DAVE3
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK Undef_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Undef_Handler
+        B Undef_Handler
+
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+
+        PUBWEAK SCU_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_0_IRQHandler
+        B SCU_0_IRQHandler
+
+        PUBWEAK SCU_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_1_IRQHandler
+        B SCU_1_IRQHandler
+
+
+        PUBWEAK SCU_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SCU_2_IRQHandler
+        B SCU_2_IRQHandler
+
+
+        PUBWEAK ERU0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_0_IRQHandler
+        B ERU0_0_IRQHandler
+
+
+        PUBWEAK ERU0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_1_IRQHandler
+        B ERU0_1_IRQHandler
+
+
+        PUBWEAK ERU0_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_2_IRQHandler
+        B ERU0_2_IRQHandler
+
+
+        PUBWEAK ERU0_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ERU0_3_IRQHandler
+        B ERU0_3_IRQHandler
+
+
+        PUBWEAK USIC0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_0_IRQHandler
+        B USIC0_0_IRQHandler
+
+
+        PUBWEAK USIC0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_1_IRQHandler
+        B USIC0_1_IRQHandler
+
+
+        PUBWEAK USIC0_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_2_IRQHandler
+        B USIC0_2_IRQHandler
+
+
+        PUBWEAK USIC0_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_3_IRQHandler
+        B USIC0_3_IRQHandler
+
+
+        PUBWEAK USIC0_4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_4_IRQHandler
+        B USIC0_4_IRQHandler
+
+
+        PUBWEAK USIC0_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USIC0_5_IRQHandler
+        B USIC0_5_IRQHandler
+
+
+        PUBWEAK VADC0_C0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_C0_0_IRQHandler
+        B VADC0_C0_0_IRQHandler
+
+
+        PUBWEAK VADC0_C0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_C0_1_IRQHandler
+        B VADC0_C0_1_IRQHandler
+
+
+        PUBWEAK VADC0_G0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_G0_0_IRQHandler
+        B VADC0_G0_0_IRQHandler
+
+
+        PUBWEAK VADC0_G0_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_G0_1_IRQHandler
+        B VADC0_G0_1_IRQHandler
+
+
+        PUBWEAK VADC0_G1_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_G1_0_IRQHandler
+        B VADC0_G1_0_IRQHandler
+
+
+        PUBWEAK VADC0_G1_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+VADC0_G1_1_IRQHandler
+        B VADC0_G1_1_IRQHandler
+
+
+        PUBWEAK CCU40_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_0_IRQHandler
+        B CCU40_0_IRQHandler
+
+
+        PUBWEAK CCU40_1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_1_IRQHandler
+        B CCU40_1_IRQHandler
+
+
+        PUBWEAK CCU40_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_2_IRQHandler
+        B CCU40_2_IRQHandler
+
+
+        PUBWEAK CCU40_3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCU40_3_IRQHandler
+        B CCU40_3_IRQHandler
+
+
+        PUBWEAK LEDTS0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LEDTS0_0_IRQHandler
+        B LEDTS0_0_IRQHandler
+
+
+        PUBWEAK LEDTS1_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LEDTS1_0_IRQHandler
+        B LEDTS1_0_IRQHandler
+
+
+        PUBWEAK BCCU0_0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BCCU0_0_IRQHandler
+        B BCCU0_0_IRQHandler
+
+; Definition of the default weak SystemInit_DAVE3 function
+;If DAVE3 requires an extended SystemInit it will create its own version of
+;SystemInit_DAVE3 which overrides this weak definition. Example includes
+;setting up of external memory interfaces.
+
+        PUBWEAK SystemInit_DAVE3
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SystemInit_DAVE3
+        NOP
+        BX LR
+
+;Decision function queried by CMSIS startup for Clock tree setup ======== */
+;In the absence of DAVE code engine, CMSIS SystemInit() must perform clock tree setup.
+;This decision routine defined here will always return TRUE.
+;When overridden by a definition defined in DAVE code engine, this routine
+;returns FALSE indicating that the code engine has performed the clock setup
+
+        PUBWEAK AllowClkInitByStartup
+        SECTION .text:CODE:REORDER:NOROOT(2)
+AllowClkInitByStartup
+        MOVS  R0,#1
+        BX    LR
+
+        END
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/JLinkSettings.ini
new file mode 100644
index 000000000..de1b137f3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/JLinkSettings.ini
@@ -0,0 +1,34 @@
+[BREAKPOINTS]
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 0
+Device="UNSPECIFIED"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/RegTest_Keil.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/RegTest_Keil.s
new file mode 100644
index 000000000..c7158f533
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/RegTest_Keil.s
@@ -0,0 +1,239 @@
+;/*
+;    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+;
+;    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+;
+;    ***************************************************************************
+;     *                                                                       *
+;     *    FreeRTOS provides completely free yet professionally developed,    *
+;     *    robust, strictly quality controlled, supported, and cross          *
+;     *    platform software that has become a de facto standard.             *
+;     *                                                                       *
+;     *    Help yourself get started quickly and support the FreeRTOS         *
+;     *    project by purchasing a FreeRTOS tutorial book, reference          *
+;     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+;     *                                                                       *
+;     *    Thank you!                                                         *
+;     *                                                                       *
+;    ***************************************************************************
+;
+;    This file is part of the FreeRTOS distribution.
+;
+;    FreeRTOS is free software; you can redistribute it and/or modify it under
+;    the terms of the GNU General Public License (version 2) as published by the
+;    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+;
+;    >>! NOTE: The modification to the GPL is included to allow you to distribute
+;    >>! a combined work that includes FreeRTOS without being obliged to provide
+;    >>! the source code for proprietary components outside of the FreeRTOS
+;    >>! kernel.
+;
+;    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+;    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+;    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+;    link: http://www.freertos.org/a00114.html
+;
+;    1 tab == 4 spaces!
+;
+;    ***************************************************************************
+;     *                                                                       *
+;     *    Having a problem?  Start by reading the FAQ "My application does   *
+;     *    not run, what could be wrong?"                                     *
+;     *                                                                       *
+;     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+;     *                                                                       *
+;    ***************************************************************************
+;
+;    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+;    license and Real Time Engineers Ltd. contact details.
+;
+;    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+;    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+;    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+;
+;    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+;    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+;    licenses offer ticketed support, indemnification and middleware.
+;
+;    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+;    engineered and independently SIL3 certified version for use in safety and
+;    mission critical applications that require provable dependability.
+;
+;    1 tab == 4 spaces!
+;*/
+
+	PRESERVE8
+	THUMB
+	
+
+	IMPORT ulRegTest1LoopCounter
+	IMPORT ulRegTest2LoopCounter
+
+	EXTERN vPortYield ;////////////////////////////////////////////////////////////////////////////////////////
+
+	EXPORT vRegTest1Task
+	EXPORT vRegTest2Task
+	
+	AREA    |.text|, CODE, READONLY
+
+;/*-----------------------------------------------------------*/
+vRegTest1Task PROC
+
+	;/* Fill the core registers with known values.  This is only done once. */
+	movs r1, #101
+	movs r2, #102
+	movs r3, #103
+	movs r4, #104
+	movs r5, #105
+	movs r6, #106
+	movs r7, #107
+	movs r0, #108
+	mov	 r8, r0
+	movs r0, #109
+	mov  r9, r0
+	movs r0, #110
+	mov	 r10, r0
+	movs r0, #111
+	mov	 r11, r0
+	movs r0, #112
+	mov  r12, r0
+	movs r0, #100
+
+reg1_loop
+	;/* Repeatedly check that each register still contains the value written to
+	;it when the task started. */
+	cmp	r0, #100
+	bne	reg1_error_loop
+	cmp	r1, #101
+	bne	reg1_error_loop
+	cmp	r2, #102
+	bne	reg1_error_loop
+	cmp r3, #103
+	bne	reg1_error_loop
+	cmp	r4, #104
+	bne	reg1_error_loop
+	cmp	r5, #105
+	bne	reg1_error_loop
+	cmp	r6, #106
+	bne	reg1_error_loop
+	cmp	r7, #107
+	bne	reg1_error_loop
+	movs r0, #108
+	cmp	r8, r0
+	bne	reg1_error_loop
+	movs r0, #109
+	cmp	r9, r0
+	bne	reg1_error_loop
+	movs r0, #110
+	cmp	r10, r0
+	bne	reg1_error_loop
+	movs r0, #111
+	cmp	r11, r0
+	bne	reg1_error_loop
+	movs r0, #112
+	cmp	r12, r0
+	bne	reg1_error_loop
+
+	;/* Everything passed, increment the loop counter. */
+	push { r1 }
+	ldr	r0, =ulRegTest1LoopCounter
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+	pop { r1 }
+
+	;/* Start again. */
+	movs r0, #100
+	
+	push {r0-r1}
+	bl vPortYield	;;///////////////////////////////////////////////////////////////////////////////////////////////////
+	pop {r0-r1}
+	
+	b reg1_loop
+
+reg1_error_loop
+	;/* If this line is hit then there was an error in a core register value.
+	;The loop ensures the loop counter stops incrementing. */
+	b reg1_error_loop
+	nop
+	ENDP
+
+
+
+vRegTest2Task PROC
+
+	;/* Fill the core registers with known values.  This is only done once. */
+	movs r1, #1
+	movs r2, #2
+	movs r3, #3
+	movs r4, #4
+	movs r5, #5
+	movs r6, #6
+	movs r7, #7
+	movs r0, #8
+	mov	r8, r0
+	movs r0, #9
+	mov r9, r0
+	movs r0, #10
+	mov	r10, r0
+	movs r0, #11
+	mov	r11, r0
+	movs r0, #12
+	mov r12, r0
+	movs r0, #10
+
+reg2_loop
+	;/* Repeatedly check that each register still contains the value written to
+	;it when the task started. */
+	cmp	r0, #10
+	bne	reg2_error_loop
+	cmp	r1, #1
+	bne	reg2_error_loop
+	cmp	r2, #2
+	bne	reg2_error_loop
+	cmp r3, #3
+	bne	reg2_error_loop
+	cmp	r4, #4
+	bne	reg2_error_loop
+	cmp	r5, #5
+	bne	reg2_error_loop
+	cmp	r6, #6
+	bne	reg2_error_loop
+	cmp	r7, #7
+	bne	reg2_error_loop
+	movs r0, #8
+	cmp	r8, r0
+	bne	reg2_error_loop
+	movs r0, #9
+	cmp	r9, r0
+	bne	reg2_error_loop
+	movs r0, #10
+	cmp	r10, r0
+	bne	reg2_error_loop
+	movs r0, #11
+	cmp	r11, r0
+	bne	reg2_error_loop
+	movs r0, #12
+	cmp	r12, r0
+	bne	reg2_error_loop
+
+	;/* Everything passed, increment the loop counter. */
+	push { r1 }
+	ldr	r0, =ulRegTest2LoopCounter
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+	pop { r1 }
+
+	;/* Start again. */
+	movs r0, #10
+	b reg2_loop
+
+reg2_error_loop
+	;/* If this line is hit then there was an error in a core register value.
+	;The loop ensures the loop counter stops incrementing. */
+	b reg2_error_loop
+	nop
+	ENDP
+
+	END
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/startup_XMC1300.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/startup_XMC1300.s
new file mode 100644
index 000000000..65d38149e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/startup_XMC1300.s
@@ -0,0 +1,397 @@
+;*****************************************************************************/
+; * @file     startup_XMC1300.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File for
+; *           Infineon XMC1300 Device Series
+; * @version  V1.00
+; * @date     21. Jan. 2013
+; *
+; * @note
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;*  <<< Use Configuration Wizard in Context Menu >>>
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+;  Clock system handling by SSW
+;    CLK_VAL1 Configuration
+;         FDIV Fractional Divider Selection
+;        IDIV Divider Selection
+;                     <0=> Divider is bypassed
+;                     <1=> MCLK = 32 MHz
+;                     <2=> MCLK = 16 MHz
+;                     <3=> MCLK = 10.67 MHz
+;                     <4=> MCLK = 8 MHz
+;                     <254=> MCLK = 126 kHz
+;                     <255=> MCLK = 125.5 kHz
+;           PCLKSEL PCLK Clock Select
+;                     <0=> PCLK = MCLK
+;                     <1=> PCLK = 2 x MCLK
+;       RTCCLKSEL RTC Clock Select
+;                     <0=> 32.768kHz standby clock
+;                     <1=> 32.768kHz external clock from ERU0.IOUT0
+;                     <2=> 32.768kHz external clock from ACMP0.OUT
+;                     <3=> 32.768kHz external clock from ACMP1.OUT
+;                     <4=> 32.768kHz external clock from ACMP2.OUT
+;                     <5=> Reserved
+;                     <6=> Reserved
+;                     <7=> Reserved
+;           do not move CLK_VAL1 to SCU_CLKCR[0..19]
+;   
+CLK_VAL1_Val    EQU     0x00000100      ; 0xF0000000
+
+;    CLK_VAL2 Configuration
+;         disable VADC and SHS Gating
+;         disable CCU80 Gating
+;         disable CCU40 Gating
+;         disable USIC0 Gating
+;         disable BCCU0 Gating
+;         disable LEDTS0 Gating
+;         disable LEDTS1 Gating
+;         disable POSIF0 Gating
+;         disable MATH Gating
+;         disable WDT Gating
+;        disable RTC Gating
+;        do not move CLK_VAL2 to SCU_CGATCLR0[0..10]
+;   
+CLK_VAL2_Val    EQU     0x00000000      ; 0xF0000000
+; 
+
+                PRESERVE8
+                THUMB
+
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */
+;* Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+
+
+__Vectors
+    DCD   __initial_sp                ;* Top of Stack
+    DCD   Reset_Handler               ;* Reset Handler
+    DCD   0                           ;* Not used
+    DCD   0                           ;* Not Used
+    DCD   CLK_VAL1_Val                ;* CLK_VAL1
+    DCD   CLK_VAL2_Val                ;* CLK_VAL2
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+;* ================== END OF VECTOR TABLE DEFINITION ======================== */
+
+
+;* ================== START OF VECTOR ROUTINES ============================== */
+                AREA    |.text|, CODE, READONLY
+
+;* Reset Handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit
+
+        ;* C routines are likely to be called. Setup the stack now
+        LDR     R0, =__initial_sp
+        MOV     SP, R0
+
+       ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"
+       ; The real veneers will be copied later from the scatter loader before reaching main.
+       ; This init code should handle an exception before the real veneers are copied.
+SRAM_BASE            EQU     0x20000000
+VENEER_INIT_CODE     EQU     0xE7FEBF00             ; NOP, B .
+
+        LDR     R1, =SRAM_BASE
+        LDR     R2, =VENEER_INIT_CODE                
+        MOVS    R0, #48                     ; Veneer 0..47
+Init_Veneers
+        STR     R2, [R1]
+        ADDS    R1, #4
+        SUBS    R0, R0, #1
+        BNE     Init_Veneers
+
+
+        LDR     R0, =SystemInit
+        BLX     R0
+
+
+        ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
+        ; weakly defined here though for a potential override.
+
+        LDR     R0, = SystemInit_DAVE3
+        BLX     R0
+
+
+        LDR     R0, =__main
+        BX      R0
+
+
+        ALIGN
+        ENDP
+
+;* ========================================================================== */
+
+
+
+;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */
+;* Default exception Handlers - Users may override this default functionality
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                   [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler                   [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler                [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler               [WEAK]
+                B       .
+                ENDP
+
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
+
+
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+;* IRQ Handlers
+
+Default_Handler PROC
+               EXPORT     SCU_0_IRQHandler            [WEAK]
+               EXPORT     SCU_1_IRQHandler            [WEAK]
+               EXPORT     SCU_2_IRQHandler            [WEAK]
+               EXPORT     ERU0_0_IRQHandler           [WEAK]
+               EXPORT     ERU0_1_IRQHandler           [WEAK]
+               EXPORT     ERU0_2_IRQHandler           [WEAK]
+               EXPORT     ERU0_3_IRQHandler           [WEAK]
+               EXPORT     MATH0_0_IRQHandler          [WEAK]
+               EXPORT     USIC0_0_IRQHandler          [WEAK]
+               EXPORT     USIC0_1_IRQHandler          [WEAK]
+               EXPORT     USIC0_2_IRQHandler          [WEAK]
+               EXPORT     USIC0_3_IRQHandler          [WEAK]
+               EXPORT     USIC0_4_IRQHandler          [WEAK]
+               EXPORT     USIC0_5_IRQHandler          [WEAK]
+               EXPORT     VADC0_C0_0_IRQHandler       [WEAK]
+               EXPORT     VADC0_C0_1_IRQHandler       [WEAK]
+               EXPORT     VADC0_G0_0_IRQHandler       [WEAK]
+               EXPORT     VADC0_G0_1_IRQHandler       [WEAK]
+               EXPORT     VADC0_G1_0_IRQHandler       [WEAK]
+               EXPORT     VADC0_G1_1_IRQHandler       [WEAK]
+               EXPORT     CCU40_0_IRQHandler          [WEAK]
+               EXPORT     CCU40_1_IRQHandler          [WEAK]
+               EXPORT     CCU40_2_IRQHandler          [WEAK]
+               EXPORT     CCU40_3_IRQHandler          [WEAK]
+               EXPORT     CCU80_0_IRQHandler          [WEAK]
+               EXPORT     CCU80_1_IRQHandler          [WEAK]
+               EXPORT     POSIF0_0_IRQHandler         [WEAK]
+               EXPORT     POSIF0_1_IRQHandler         [WEAK]
+               EXPORT     LEDTS0_0_IRQHandler         [WEAK]
+               EXPORT     LEDTS1_0_IRQHandler         [WEAK]
+               EXPORT     BCCU0_0_IRQHandler          [WEAK]
+
+SCU_0_IRQHandler
+SCU_1_IRQHandler
+SCU_2_IRQHandler
+ERU0_0_IRQHandler
+ERU0_1_IRQHandler
+ERU0_2_IRQHandler
+ERU0_3_IRQHandler
+MATH0_0_IRQHandler
+USIC0_0_IRQHandler
+USIC0_1_IRQHandler
+USIC0_2_IRQHandler
+USIC0_3_IRQHandler
+USIC0_4_IRQHandler
+USIC0_5_IRQHandler
+VADC0_C0_0_IRQHandler
+VADC0_C0_1_IRQHandler
+VADC0_G0_0_IRQHandler
+VADC0_G0_1_IRQHandler
+VADC0_G1_0_IRQHandler
+VADC0_G1_1_IRQHandler
+CCU40_0_IRQHandler
+CCU40_1_IRQHandler
+CCU40_2_IRQHandler
+CCU40_3_IRQHandler
+CCU80_0_IRQHandler
+CCU80_1_IRQHandler
+POSIF0_0_IRQHandler
+POSIF0_1_IRQHandler
+LEDTS0_0_IRQHandler
+LEDTS1_0_IRQHandler
+BCCU0_0_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
+
+;*  Definition of the default weak SystemInit_DAVE3 function.
+;*  This function will be called by the CMSIS SystemInit function.
+;*  If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
+;*  which will overule this weak definition
+SystemInit_DAVE3    PROC
+                  EXPORT  SystemInit_DAVE3             [WEAK]
+                  NOP
+                  BX LR
+        ENDP
+
+;*  Definition of the default weak DAVE3 function for clock App usage.
+;*  AllowClkInitByStartup Handler */
+AllowClkInitByStartup    PROC
+                  EXPORT  AllowClkInitByStartup        [WEAK]
+                  MOVS R0,#1
+                  BX LR
+        ENDP
+
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+
+;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */
+; Veneers are located to fix SRAM Address 0x2000'0000
+                AREA    |.ARM.__at_0x20000000|, CODE, READWRITE
+
+; Each Veneer has exactly a lengs of 4 Byte
+
+                MACRO
+                STAYHERE $IrqNumber
+                LDR  R0, =$IrqNumber
+                B    .
+                MEND
+
+                MACRO
+                JUMPTO $Handler
+                LDR  R0, =$Handler
+                BX   R0
+                MEND
+
+                STAYHERE 0x0                          ;* Reserved
+                STAYHERE 0x1                          ;* Reserved 
+                STAYHERE 0x2                          ;* Reserved 
+                JUMPTO   HardFault_Handler            ;* HardFault Veneer  
+                STAYHERE 0x4                          ;* Reserved 
+                STAYHERE 0x5                          ;* Reserved 
+                STAYHERE 0x6                          ;* Reserved 
+                STAYHERE 0x7                          ;* Reserved 
+                STAYHERE 0x8                          ;* Reserved 
+                STAYHERE 0x9                          ;* Reserved 
+                STAYHERE 0xA                          ;* Reserved
+                JUMPTO   SVC_Handler                  ;* SVC Veneer        
+                STAYHERE 0xC                          ;* Reserved
+                STAYHERE 0xD                          ;* Reserved
+                JUMPTO   PendSV_Handler               ;* PendSV Veneer     
+                JUMPTO   SysTick_Handler              ;* SysTick Veneer    
+                JUMPTO   SCU_0_IRQHandler             ;* SCU_0 Veneer      
+                JUMPTO   SCU_1_IRQHandler             ;* SCU_1 Veneer      
+                JUMPTO   SCU_2_IRQHandler             ;* SCU_2 Veneer      
+                JUMPTO   ERU0_0_IRQHandler            ;* SCU_3 Veneer      
+                JUMPTO   ERU0_1_IRQHandler            ;* SCU_4 Veneer      
+                JUMPTO   ERU0_2_IRQHandler            ;* SCU_5 Veneer      
+                JUMPTO   ERU0_3_IRQHandler            ;* SCU_6 Veneer      
+                JUMPTO   MATH0_0_IRQHandler           ;* SCU_7 Veneer      
+                STAYHERE 0x18                         ;* Reserved
+                JUMPTO   USIC0_0_IRQHandler           ;* USIC0_0 Veneer    
+                JUMPTO   USIC0_1_IRQHandler           ;* USIC0_1 Veneer    
+                JUMPTO   USIC0_2_IRQHandler           ;* USIC0_2 Veneer    
+                JUMPTO   USIC0_3_IRQHandler           ;* USIC0_3 Veneer    
+                JUMPTO   USIC0_4_IRQHandler           ;* USIC0_4 Veneer    
+                JUMPTO   LEDTS0_0_IRQHandler          ;* USIC0_5 Veneer    
+                JUMPTO   VADC0_C0_0_IRQHandler        ;* VADC0_C0_0 Veneer 
+                JUMPTO   VADC0_C0_1_IRQHandler        ;* VADC0_C0_1 Veneer 
+                JUMPTO   VADC0_G0_0_IRQHandler        ;* VADC0_G0_0 Veneer 
+                JUMPTO   VADC0_G0_1_IRQHandler        ;* VADC0_G0_1 Veneer 
+                JUMPTO   VADC0_G1_0_IRQHandler        ;* VADC0_G1_0 Veneer 
+                JUMPTO   VADC0_G1_1_IRQHandler        ;* VADC0_G1_1 Veneer 
+                JUMPTO   CCU40_0_IRQHandler           ;* CCU40_0 Veneer    
+                JUMPTO   CCU40_1_IRQHandler           ;* CCU40_1 Veneer    
+                JUMPTO   CCU40_2_IRQHandler           ;* CCU40_2 Veneer    
+                JUMPTO   CCU40_3_IRQHandler           ;* CCU40_3 Veneer    
+                JUMPTO   CCU80_0_IRQHandler           ;* CCU80_0 Veneer    
+                JUMPTO   CCU80_1_IRQHandler           ;* CCU80_1 Veneer    
+                JUMPTO   POSIF0_0_IRQHandler          ;* POSIF0_0 Veneer   
+                JUMPTO   POSIF0_1_IRQHandler          ;* POSIF0_1 Veneer   
+                JUMPTO   LEDTS0_0_IRQHandler          ;* LEDTS0_0 Veneer   
+                JUMPTO   LEDTS1_0_IRQHandler          ;* LEDTS1_0 Veneer   
+                JUMPTO   BCCU0_0_IRQHandler           ;* BCCU0_0 Veneer    
+
+                ALIGN
+
+;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */
+
+                END
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1100.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1100.c
new file mode 100644
index 000000000..99884b3e9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1100.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+ * @file     system_XMC1100.c
+ * @brief    Device specific initialization for the XMC1100-Series according 
+ * to CMSIS
+ * @version  V1.2
+ * @date     13 Dec 2012
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
+ * Infineon’s microcontrollers.
+ *   
+ * This file can be freely distributed within development tools that are 
+ * supporting such microcontrollers.
+ *  
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+ * *************************** Change history ********************************
+ * V1.2, 13 Dec 2012, PKB : Created change history table
+ */
+
+#include "system_XMC1100.h"
+#include 
+
+/*---------------------------------------------------------------------------
+ Extern definitions 
+ *--------------------------------------------------------------------------*/
+extern uint32_t AllowClkInitByStartup(void);
+
+/*----------------------------------------------------------------------------
+  Clock Global defines
+ *----------------------------------------------------------------------------*/
+#define DCO_DCLK       64000000UL
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{    
+  /*
+   * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE
+   * Clock app.
+   */ 
+  if(AllowClkInitByStartup()){ 
+  /* Do not change default values of IDIV,FDIV and RTCCLKSEL */
+  /* ====== Default configuration ======= */
+  /*
+   * MCLK    = DCO_DCLK
+   * PCLK    = MCLK
+   * RTC CLK = Standby clock
+   */
+  }
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t IDIV, CLKCR;
+
+  CLKCR = SCU_CLOCK -> CLKCR;
+  
+  IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;
+  
+  if(IDIV)
+  {
+    SystemCoreClock = DCO_DCLK / (2 * IDIV );
+  }
+  else
+  {
+    /* Divider bypassed */
+    SystemCoreClock = DCO_DCLK;
+  }
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1200.c
new file mode 100644
index 000000000..5b06bc4c1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1200.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+ * @file     system_XMC1200.c
+ * @brief    Device specific initialization for the XMC1200-Series according 
+ * to CMSIS
+ * @version  V1.2
+ * @date     13 Dec 2012
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
+ * Infineon’s microcontrollers.
+ *   
+ * This file can be freely distributed within development tools that are 
+ * supporting such microcontrollers.
+ *  
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+ * *************************** Change history ********************************
+ * V1.2, 13 Dec 2012, PKB : Created change history table
+ */
+
+#include "System_XMC1200.h"
+#include 
+
+/*---------------------------------------------------------------------------
+ Extern definitions 
+ *--------------------------------------------------------------------------*/
+extern uint32_t AllowClkInitByStartup(void);
+
+/*----------------------------------------------------------------------------
+  Clock Global defines
+ *----------------------------------------------------------------------------*/
+#define DCO_DCLK       64000000UL
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{    
+  /*
+   * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE
+   * Clock app.
+   */ 
+  if(AllowClkInitByStartup()){ 
+  /* Do not change default values of IDIV,FDIV and RTCCLKSEL */
+  /* ====== Default configuration ======= */
+  /*
+   * MCLK    = DCO_DCLK
+   * PCLK    = MCLK
+   * RTC CLK = Standby clock
+   */
+  }
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t IDIV, CLKCR;
+
+  CLKCR = SCU_CLOCK -> CLKCR;
+  
+  IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;
+  
+  if(IDIV)
+  {
+    SystemCoreClock = DCO_DCLK / (2 * IDIV );
+  }
+  else
+  {
+    /* Divider bypassed */
+    SystemCoreClock = DCO_DCLK;
+  }
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1300.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1300.c
new file mode 100644
index 000000000..c83e3fec6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/system_XMC1300.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+ * @file     system_XMC1300.c
+ * @brief    Device specific initialization for the XMC1300-Series according 
+ * to CMSIS
+ * @version  V1.2
+ * @date     13 Dec 2012
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
+ * Infineon’s microcontrollers.
+ *   
+ * This file can be freely distributed within development tools that are 
+ * supporting such microcontrollers.
+ *  
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+ * ************************** Change history *********************************
+ * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_
+ */
+
+#include "system_XMC1300.h"
+#include 
+
+/*---------------------------------------------------------------------------
+ Extern definitions 
+ *--------------------------------------------------------------------------*/
+extern uint32_t AllowClkInitByStartup(void);
+
+/*----------------------------------------------------------------------------
+  Clock Global defines
+ *----------------------------------------------------------------------------*/
+#define DCO_DCLK       64000000UL
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{    
+  /*
+   * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE
+   * Clock app.
+   */ 
+  if(AllowClkInitByStartup()){ 
+  /* Do not change default values of IDIV,FDIV and RTCCLKSEL */
+  /* ====== Default configuration ======= */
+  /*
+   * MCLK    = DCO_DCLK
+   * PCLK    = MCLK
+   * RTC CLK = Standby clock
+   */
+  }
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t IDIV, CLKCR;
+
+  CLKCR = SCU_CLOCK -> CLKCR;
+  
+  IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;
+  
+  if(IDIV)
+  {
+    SystemCoreClock = DCO_DCLK / (2 * IDIV );
+  }
+  else
+  {
+    /* Divider bypassed */
+    SystemCoreClock = DCO_DCLK;
+  }
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1200.c
new file mode 100644
index 000000000..23c64c2b1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1200.c
@@ -0,0 +1,157 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*-----------------------------------------------------------
+ * Simple GPIO (parallel port) IO routines.
+ *-----------------------------------------------------------*/
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include 
+
+/* Standard demo include. */
+#include "partest.h"
+
+/* The port bits on which LEDs are connected. */
+static const unsigned long ulLEDBits[] = 
+{ 
+	1UL << 0, /* P0.0 */
+	1UL << 2, /* P0.2 */
+	1UL << 5, /* P0.5 */
+	1UL << 6, /* P0.6 */
+	1UL << 7  /* P0.7 */
+};
+
+#define partstNUM_LEDS	( sizeof( ulLEDBits ) / sizeof( unsigned long ) )
+
+/* Shift the LED bit into the correct position within the POW register to
+perform the desired operation. */
+#define partstON_SHIFT	( 16UL )
+#define partstOFF_SHIFT	( 0UL )
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	/* Configure relevant port P0 to push pull output to drive LEDs. */
+	
+	/* P0.0 */
+	PORT0->IOCR0 &= ~( ( 0xFFUL <<  0 ) );
+	PORT0->IOCR0 |= ( 0x80UL <<  0 );
+	vParTestSetLED( 0, pdFALSE );
+
+	/* P0.2 */
+	PORT0->IOCR0 &= ~( ( 0xFFUL << 16 ) );
+	PORT0->IOCR0 |= ( 0x80UL << 16 );
+	vParTestSetLED( 1, pdFALSE );
+
+	/* P0.5 */
+	PORT0->IOCR4 &= ~( ( 0xFFUL << 8 ) );
+	PORT0->IOCR4 |= ( 0x80UL << 8 );
+	vParTestSetLED( 2, pdFALSE );
+
+	/* P0.6 */
+	PORT0->IOCR4 &= ~( ( 0xFFUL << 16 ) );
+	PORT0->IOCR4 |= ( 0x80UL << 16 );
+	vParTestSetLED( 3, pdFALSE );
+
+	/* P0.7 */
+	PORT0->IOCR4 &= ~( ( 0xFFUL << 24 ) );
+	PORT0->IOCR4 |= ( 0x80UL << 24 );
+	vParTestSetLED( 4, pdFALSE );
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue )
+{
+	if( ulLED < partstNUM_LEDS )
+	{
+		if( xValue == pdTRUE )
+		{
+			/* Turn the LED on. */			
+			PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT );
+		}
+		else
+		{
+			/* Turn the LED off. */			
+			PORT0->OMR = ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned long ulLED )
+{
+	if( ulLED < partstNUM_LEDS )
+	{
+		/* Setting both the ON and OFF bits simultaneously results in the bit
+		being toggled. */
+		PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ) | ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );
+	}
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.ewd
new file mode 100644
index 000000000..d1f08e34e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.ewd
@@ -0,0 +1,1304 @@
+
+
+
+  2
+  
+    Debug
+    
+      ARM
+    
+    1
+    
+      C-SPY
+      2
+      
+        25
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
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+        
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+        
+      
+    
+    
+      ARMSIM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      ANGEL_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      CMSISDAP_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
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+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARROM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      IJET_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
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+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      JLINK_ID
+      2
+      
+        15
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
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diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.ewp
new file mode 100644
index 000000000..29cfce81e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.ewp
@@ -0,0 +1,1009 @@
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+      $PROJ_DIR$\..\Common\Minimal\blocktim.c
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+    
+    
+      $PROJ_DIR$\..\Common\Minimal\dynamic.c
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+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.eww
new file mode 100644
index 000000000..1ebe70f55
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.eww
@@ -0,0 +1,18 @@
+
+
+
+  
+    $WS_DIR$\RTOSDemo.ewp
+  
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+        RTOSDemo
+        Debug
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+  
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.plg b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.plg
new file mode 100644
index 000000000..f059c3bab
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.plg
@@ -0,0 +1,48 @@
+
+
+
+
µVision Build Log

+
Project:

+C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil\RTOSDemo.uvproj
+Project File Date:  08/24/2013
+
+
Output:

+Build target 'XMC1300'
+assembling startup_XMC1300.s...
+compiling timers.c...
+compiling list.c...
+compiling queue.c...
+compiling tasks.c...
+compiling port.c...
+..\..\Source\portable\RVDS\ARM_CM0\port.c(101): warning:  #1207-D: attribute "naked" ignored
+..\..\Source\portable\RVDS\ARM_CM0\port.c(103): warning:  #1207-D: attribute "naked" ignored
+..\..\Source\portable\RVDS\ARM_CM0\port.c(108): warning:  #1207-D: attribute "naked" ignored
+..\..\Source\portable\RVDS\ARM_CM0\port.c(155): warning:  #1267-D: Implicit physical register R3 should be defined as a variable
+..\..\Source\portable\RVDS\ARM_CM0\port.c(155): error:  #1086: Operand is wrong type
+..\..\Source\portable\RVDS\ARM_CM0\port.c(155): error:  #114: label "pxCurrentTCBConst2" was referenced but not defined
+..\..\Source\portable\RVDS\ARM_CM0\port.c(168): warning:  #1267-D: Implicit physical register R0 should be defined as a variable
+..\..\Source\portable\RVDS\ARM_CM0\port.c(278): warning:  #1267-D: Implicit physical register R0 should be defined as a variable
+..\..\Source\portable\RVDS\ARM_CM0\port.c(278): warning:  #1267-D: Implicit physical register R3 should be defined as a variable
+..\..\Source\portable\RVDS\ARM_CM0\port.c(278): error:  #1086: Operand is wrong type
+..\..\Source\portable\RVDS\ARM_CM0\port.c(278): error:  #114: label "pxCurrentTCBConst" was referenced but not defined
+..\..\Source\portable\RVDS\ARM_CM0\port.c(306): error:  #20: identifier "SystemCoreClock" is undefined
+compiling ParTest.c...
+compiling main.c...
+compiling main-blinky.c...
+".\RTOSDemo.axf" - 5 Errors, 7 Warning(s).
+Target not created
+Clean started: Project: 'RTOSDemo'
+   deleting intermediate output files for target 'XMC1300'
+Build target 'XMC1300'
+assembling startup_XMC1300.s...
+compiling timers.c...
+compiling list.c...
+compiling queue.c...
+compiling tasks.c...
+compiling port.c...
+..\..\Source\portable\RVDS\ARM_CM0\port.c(305): error:  #20: identifier "SystemCoreClock" is undefined
+compiling ParTest.c...
+compiling main.c...
+compiling main-blinky.c...
+".\Output\RTOSDemo.axf" - 1 Errors, 0 Warning(s).
+Target not created
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvopt
new file mode 100644
index 000000000..4ea6bea3b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvopt
@@ -0,0 +1,745 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
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+        
+        
+          1
+          User Manual
+          DATASHTS\Infineon\XMC1300\xmc1300_ds.pdf
+        
+        
+          2
+          Technical Reference Manual
+          datashts\arm\cortex_m0\r0p0\DDI0432C_CORTEX_M0_R0P0_TRM.PDF
+        
+        
+          3
+          Generic User Guide
+          datashts\arm\cortex_m0\r0p0\DUI0497A_CORTEX_M0_R0P0_GENERIC_UG.PDF
+        
+      
+      
+        SARMCM3.DLL
+        
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+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
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+        
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+          0
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+          UL2CM3(-O207 -S0 -C0 -FO7  -FN1 -FC800 -FD20000000 -FF0XMC1300_200 -FL032000 -FS010001000
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+        
+        
+          2
+          Technical Reference Manual
+          datashts\arm\cortex_m0\r0p0\DDI0432C_CORTEX_M0_R0P0_TRM.PDF
+        
+        
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+      ..\..\Source\portable\MemMang\heap_4.c
+      heap_4.c
+      0
+      0
+    
+  
+
+  
+    Demo App Source
+    1
+    0
+    0
+    0
+    
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+      9
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+      0
+      0
+      0
+      134
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+      main-blinky.c
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+      FreeRTOSConfig.h
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+      main-full.c
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+      ParTest_XMC1200.c
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+      0
+      .\Keil_Specific\RegTest_Keil.s
+      RegTest_Keil.s
+      0
+      0
+    
+  
+
+  
+    Common Demo Tasks
+    1
+    0
+    0
+    0
+    
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+      15
+      1
+      0
+      0
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+      0
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+      dynamic.c
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+      recmutex.c
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+    
+      4
+      17
+      1
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+      0
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+      ..\Common\Minimal\blocktim.c
+      blocktim.c
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+    
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+      1
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+      0
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+      ..\Common\Minimal\countsem.c
+      countsem.c
+      0
+      0
+    
+  
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvproj b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvproj
new file mode 100644
index 000000000..0cccd2f04
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/RTOSDemo.uvproj
@@ -0,0 +1,1081 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      XMC1300
+      0x4
+      ARM-ADS
+      
+        
+          XMC1302-200
+          Infineon
+          IRAM(0x20000000-0x20003FFF) IROM(0x10001000-0x10032FFF) CLOCK(12000000) CPUTYPE("Cortex-M0")
+          
+          "STARTUP\Infineon\XMC1300\startup_XMC1300.s" ("Infineon XMC1300 Startup Code")
+          UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1300_200 -FS010001000 -FL032000)
+          6778
+          XMC1300.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          SFD\Infineon\XMC1300\xmc1300.SFR
+          0
+          
+          
+          
+          Infineon\XMC1300\
+          Infineon\XMC1300\
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Output\
+          RTOSDemo
+          1
+          0
+          0
+          1
+          1
+          .\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
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+            0
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+          
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+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DARMCM1.DLL
+          -pCM0
+          SARMCM3.DLL
+          
+          TARMCM1.DLL
+          -pCM0
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            0
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            0
+            1
+            1
+          
+          0
+          0
+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            
+            BIN\UL2CM3.DLL
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4096
+          
+          1
+          BIN\UL2CM3.DLL
+          "" ()
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
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+            1
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+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M0"
+            
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+            0
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+                0x32000
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+            
+              
+              
+              
+              ..\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;..\Common\include
+            
+          
+          
+            1
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+            0x10001000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          System
+          
+            
+              system_XMC1200.c
+              1
+              .\system_XMC1200.c
+            
+            
+              startup_XMC1300.s
+              2
+              .\Keil_Specific\startup_XMC1300.s
+            
+          
+        
+        
+          FreeRTOS source
+          
+            
+              timers.c
+              1
+              ..\..\Source\timers.c
+            
+            
+              list.c
+              1
+              ..\..\Source\list.c
+            
+            
+              queue.c
+              1
+              ..\..\Source\queue.c
+            
+            
+              tasks.c
+              1
+              ..\..\Source\tasks.c
+            
+            
+              port.c
+              1
+              ..\..\Source\portable\RVDS\ARM_CM0\port.c
+            
+            
+              heap_4.c
+              1
+              ..\..\Source\portable\MemMang\heap_4.c
+            
+          
+        
+        
+          Demo App Source
+          
+            
+              main.c
+              1
+              .\main.c
+            
+            
+              main-blinky.c
+              1
+              .\main-blinky.c
+            
+            
+              FreeRTOSConfig.h
+              5
+              .\FreeRTOSConfig.h
+            
+            
+              main-full.c
+              1
+              .\main-full.c
+            
+            
+              ParTest_XMC1200.c
+              1
+              .\ParTest_XMC1200.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  0
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+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              RegTest_Keil.s
+              2
+              .\Keil_Specific\RegTest_Keil.s
+            
+          
+        
+        
+          Common Demo Tasks
+          
+            
+              dynamic.c
+              1
+              ..\Common\Minimal\dynamic.c
+            
+            
+              recmutex.c
+              1
+              ..\Common\Minimal\recmutex.c
+            
+            
+              blocktim.c
+              1
+              ..\Common\Minimal\blocktim.c
+            
+            
+              countsem.c
+              1
+              ..\Common\Minimal\countsem.c
+            
+          
+        
+      
+    
+    
+      XMC1200
+      0x4
+      ARM-ADS
+      
+        
+          XMC1200-200
+          Infineon
+          IRAM(0x20000000-0x20003FFF) IROM(0x10001000-0x10032FFF) CLOCK(12000000) CPUTYPE("Cortex-M0")
+          
+          "STARTUP\Infineon\XMC1200\startup_XMC1200.s" ("Infineon XMC1200 Startup Code")
+          UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000)
+          6777
+          XMC1200.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          SFD\Infineon\XMC1200\xmc1200.SFR
+          0
+          
+          
+          
+          Infineon\XMC1200\
+          Infineon\XMC1200\
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Output\
+          RTOSDemo
+          1
+          0
+          0
+          1
+          1
+          .\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
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+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DARMCM1.DLL
+          -pCM0
+          SARMCM3.DLL
+          
+          TARMCM1.DLL
+          -pCM0
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+          
+          0
+          7
+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            
+            Segger\JL2CM3.dll
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4100
+          
+          0
+          Segger\JL2CM3.dll
+          "" ()
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
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+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M0"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            8
+            1
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+            0
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+            0
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+            0
+            0
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+            1
+            0
+            
+              
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+                0x0
+                0x0
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+              
+                0
+                0x0
+                0x0
+              
+              
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+              
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+                0x0
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+              
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+              
+                0
+                0x20000000
+                0x4000
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+                1
+                0x10001000
+                0x32000
+              
+              
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+                0x0
+              
+              
+                1
+                0x0
+                0x0
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+              
+                1
+                0x0
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+                0x0
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+              
+                1
+                0x10001000
+                0x32000
+              
+              
+                1
+                0x0
+                0x0
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+              
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+                0x0
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+              
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+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              --c99
+              
+              
+              .;..\Common\include;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;.\CMSIS
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
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+          
+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0x10001000
+            0x20000000
+            .\Output\RTOSDemo.sct
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          System
+          
+            
+              system_XMC1200.c
+              1
+              .\system_XMC1200.c
+            
+            
+              startup_XMC1300.s
+              2
+              .\Keil_Specific\startup_XMC1300.s
+            
+          
+        
+        
+          FreeRTOS source
+          
+            
+              timers.c
+              1
+              ..\..\Source\timers.c
+            
+            
+              list.c
+              1
+              ..\..\Source\list.c
+            
+            
+              queue.c
+              1
+              ..\..\Source\queue.c
+            
+            
+              tasks.c
+              1
+              ..\..\Source\tasks.c
+            
+            
+              port.c
+              1
+              ..\..\Source\portable\RVDS\ARM_CM0\port.c
+            
+            
+              heap_4.c
+              1
+              ..\..\Source\portable\MemMang\heap_4.c
+            
+          
+        
+        
+          Demo App Source
+          
+            
+              main.c
+              1
+              .\main.c
+            
+            
+              main-blinky.c
+              1
+              .\main-blinky.c
+            
+            
+              FreeRTOSConfig.h
+              5
+              .\FreeRTOSConfig.h
+            
+            
+              main-full.c
+              1
+              .\main-full.c
+            
+            
+              ParTest_XMC1200.c
+              1
+              .\ParTest_XMC1200.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
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+                
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+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              RegTest_Keil.s
+              2
+              .\Keil_Specific\RegTest_Keil.s
+            
+          
+        
+        
+          Common Demo Tasks
+          
+            
+              dynamic.c
+              1
+              ..\Common\Minimal\dynamic.c
+            
+            
+              recmutex.c
+              1
+              ..\Common\Minimal\recmutex.c
+            
+            
+              blocktim.c
+              1
+              ..\Common\Minimal\blocktim.c
+            
+            
+              countsem.c
+              1
+              ..\Common\Minimal\countsem.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/XMC1200.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/XMC1200.h
new file mode 100644
index 000000000..9077f62b1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/XMC1200.h
@@ -0,0 +1,5838 @@
+
+/****************************************************************************************************//**
+ * @file     XMC1200.h
+ *
+ * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for
+ *           XMC1200 from Infineon.
+ *
+ * @version  V1.0.6 (Reference Manual v1.0)
+ * @date     26. March 2013
+ *
+ * @note     Generated with SVDConv V2.78b 
+ *           from CMSIS SVD File 'XMC1200_Processed_SVD.xml' Version 1.0.6 (Reference Manual v1.0),
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Infineon
+  * @{
+  */
+
+/** @addtogroup XMC1200
+  * @{
+  */
+
+#ifndef XMC1200_H
+#define XMC1200_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ---------------------  XMC1200 Specific Interrupt Numbers  --------------------- */
+  SCU_0_IRQn          =   0,   /*!< SCU SR0 Interrupt                        */
+  SCU_1_IRQn          =   1,   /*!< SCU SR1 Interrupt                        */
+  SCU_2_IRQn          =   2,   /*!< SCU SR2 Interrupt                        */
+  ERU0_0_IRQn         =   3,   /*!< ERU0 SR0 Interrupt                       */
+  ERU0_1_IRQn         =   4,   /*!< ERU0 SR1 Interrupt                       */
+  ERU0_2_IRQn         =   5,   /*!< ERU0 SR2 Interrupt                       */
+  ERU0_3_IRQn         =   6,   /*!< ERU0 SR3 Interrupt                       */
+  
+  USIC0_0_IRQn        =   9,   /*!< USIC SR0 Interrupt                       */
+  USIC0_1_IRQn        =  10,   /*!< USIC SR1 Interrupt                       */
+  USIC0_2_IRQn        =  11,   /*!< USIC SR2 Interrupt                       */
+  USIC0_3_IRQn        =  12,   /*!< USIC SR3 Interrupt                       */
+  USIC0_4_IRQn        =  13,   /*!< USIC SR4 Interrupt                       */
+  USIC0_5_IRQn        =  14,   /*!< USIC SR5 Interrupt                       */
+  
+  VADC0_C0_0_IRQn     =  15,   /*!< VADC SR0 Interrupt                       */
+  VADC0_C0_1_IRQn     =  16,   /*!< VADC SR1 Interrupt                       */
+  VADC0_G0_0_IRQn     =  17,   /*!< VADC SR2 Interrupt                       */
+  VADC0_G0_1_IRQn     =  18,   /*!< VADC SR3 Interrupt                       */
+  VADC0_G1_0_IRQn     =  19,   /*!< VADC SR4 Interrupt                       */
+  VADC0_G1_1_IRQn     =  20,   /*!< VADC SR5 Interrupt                       */
+  
+  CCU40_0_IRQn        =  21,   /*!< CCU40 SR0 Interrupt                      */
+  CCU40_1_IRQn        =  22,   /*!< CCU40 SR1 Interrupt                      */
+  CCU40_2_IRQn        =  23,   /*!< CCU40 SR2 Interrupt                      */
+  CCU40_3_IRQn        =  24,   /*!< CCU40 SR3 Interrupt                      */
+  
+  LEDTS0_0_IRQn       =  29,   /*!< LEDTS0 SR0 Interrupt                     */
+  LEDTS1_0_IRQn       =  30,   /*!< LEDTS1 SR0 Interrupt                     */
+  
+  BCCU0_0_IRQn        =  31,   /*!< BCCU0 SR0 Interrupt                      */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
+#define __CM0_REV                 0x0000            /*!< Cortex-M0 Core Revision                                               */
+#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include                                /*!< Cortex-M0 processor and core peripherals                              */
+#include "system_XMC1200.h"                         /*!< XMC1200 System                                                        */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+/* Macro to modify desired bitfields of a register */
+#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \
+		                                         ((uint32_t)mask)) | \
+                                          (reg & ((uint32_t)~((uint32_t)mask)))
+
+/* Macro to modify desired bitfields of a register */
+#define WR_REG_SIZE(reg, mask, pos, val, size) {  \
+uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \
+uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \
+uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \
+uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \
+reg = (uint##size##_t) (VAL2 | VAL4);\
+}
+
+/** Macro to read bitfields from a register */
+#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)
+
+/** Macro to read bitfields from a register */
+#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \
+                                                      (uint32_t)mask) >> pos) )
+
+/** Macro to set a bit in register */
+#define SET_BIT(reg, pos)     (reg |= ((uint32_t)1<>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style
+ * project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the simply blinky style version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * basic demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks.  It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 200 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky().  Once the value is sent, the task loops
+ * back around to block for another 200 milliseconds.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky().  When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, toggles LED 1.  The 'block
+ * time' parameter passed to the queue receive function specifies that the
+ * task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue.  The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue.  As the queue
+ * send task writes to the queue every 200 milliseconds, the queue receive
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo includes. */
+#include "ParTest.h"
+
+/* Priorities at which the tasks are created. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue.  The 200ms value is converted
+to ticks using the portTICK_RATE_MS constant. */
+#define mainQUEUE_SEND_FREQUENCY_MS			( 200 / portTICK_RATE_MS )
+
+/* The number of items the queue can hold.  This is 1 as the receive task
+will remove items as they are added, meaning the send task should always find
+the queue empty. */
+#define mainQUEUE_LENGTH					( 1 )
+
+/* Values passed to the two tasks just to check the task parameter
+functionality. */
+#define mainQUEUE_SEND_PARAMETER			( 0x1111UL )
+#define mainQUEUE_RECEIVE_PARAMETER			( 0x22UL )
+
+/* The number of the LED that is toggled. */
+#define mainLED_TO_TOGGLE					( 0 )
+/*-----------------------------------------------------------*/
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*
+ * Called by main() to create the simply blinky style application if
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ */
+void main_blinky( void );
+
+/*
+ * The hardware only has a single LED.  Simply toggle it.
+ */
+extern void vMainToggleLED( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static xQueueHandle xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+	/* Create the queue. */
+	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
+
+	if( xQueue != NULL )
+	{
+		/* Start the two tasks as described in the comments at the top of this
+		file. */
+		xTaskCreate( prvQueueReceiveTask,					/* The function that implements the task. */
+					( signed char * ) "Rx", 				/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+					configMINIMAL_STACK_SIZE, 				/* The size of the stack to allocate to the task. */
+					( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
+					mainQUEUE_RECEIVE_TASK_PRIORITY, 		/* The priority assigned to the task. */
+					NULL );									/* The task handle is not required, so NULL is passed. */
+
+		xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+		/* Start the tasks and timer running. */
+		vTaskStartScheduler();
+	}
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the idle and/or
+	timer tasks	to be created.  See the memory management section on the
+	FreeRTOS web site for more details. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+portTickType xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+
+	/* Check the task parameter is as expected. */
+	configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
+
+	/* Initialise xNextWakeTime - this only needs to be done once. */
+	xNextWakeTime = xTaskGetTickCount();
+
+	for( ;; )
+	{
+		/* Place this task in the blocked state until it is time to run again.
+		The block time is specified in ticks, the constant used converts ticks
+		to ms.  While in the Blocked state this task will not consume any CPU
+		time. */
+		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+		/* Send to the queue - causing the queue receive task to unblock and
+		toggle the LED.  0 is used as the block time so the sending operation
+		will not block - it shouldn't need to block as the queue should always
+		be empty at this point in the code. */
+		xQueueSend( xQueue, &ulValueToSend, 0U );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+
+	/* Check the task parameter is as expected. */
+	configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
+
+	for( ;; )
+	{
+		/* Wait until something arrives in the queue - this task will block
+		indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+		FreeRTOSConfig.h. */
+		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+		/*  To get here something must have been received from the queue, but
+		is it the expected value?  If it is, toggle the LED. */
+		if( ulReceivedValue == 100UL )
+		{
+			vParTestToggleLED( mainLED_TO_TOGGLE );
+			ulReceivedValue = 0U;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-full.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-full.c
new file mode 100644
index 000000000..8d23357c3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-full.c
@@ -0,0 +1,344 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style
+ * project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the comprehensive test and demo version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * full demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ ******************************************************************************
+ *
+ * main_full() creates a set of standard demo tasks, some application specific
+ * tasks, and four timers.  It then starts the scheduler.  The web documentation
+ * provides more details of the standard demo application tasks, which provide
+ * no particular functionality, but do provide a good example of how to use the
+ * FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and timer are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill the registers with known values, then check
+ * that each register maintains its expected value for the lifetime of the
+ * task.  Each task uses a different set of values.  The reg test tasks execute
+ * with a very low priority, so get preempted very frequently.  A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ *
+ * "Flash timers" - A software timer callback function is defined that does
+ * nothing but toggle an LED.  Three software timers are created that each
+ * use the same callback function, but each toggles a different LED at a
+ * different frequency.  One software timer uses LED1, another LED2 and the
+ * third LED3.
+ *
+ * "Check" software timer - The check timer period is initially set to three
+ * seconds.  Its callback function checks that all the standard demo tasks, and
+ * the register check tasks, are not only still executing, but are executing
+ * without reporting any errors.  If the check timer callback discovers that a
+ * task has either stalled, or reported an error, then it changes the period of
+ * the check timer from the initial three seconds, to just 200ms.  The callback
+ * function also toggles LED 4 each time it is called.  This provides a visual
+ * indication of the system status:  If the LED toggles every three seconds,
+ * then no issues have been discovered.  If the LED toggles every 200ms, then
+ * an issue has been discovered with at least one task.
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+/* Common demo includes. */
+#include "blocktim.h"
+#include "countsem.h"
+#include "recmutex.h"
+#include "ParTest.h"
+#include "dynamic.h"
+
+/* The period after which the check timer will expire provided no errors have
+been reported by any of the standard demo tasks.  ms are converted to the
+equivalent in ticks using the portTICK_RATE_MS constant. */
+#define mainCHECK_TIMER_PERIOD_MS			( 3000UL / portTICK_RATE_MS )
+
+/* The period at which the check timer will expire if an error has been
+reported in one of the standard demo tasks.  ms are converted to the equivalent
+in ticks using the portTICK_RATE_MS constant. */
+#define mainERROR_CHECK_TIMER_PERIOD_MS 	( 200UL / portTICK_RATE_MS )
+
+/* A block time of zero simply means "don't block". */
+#define mainDONT_BLOCK						( 0UL )
+
+/* The base toggle rate used by the flash timers.  Each toggle rate is a
+multiple of this. */
+#define mainFLASH_TIMER_BASE_RATE			( 200UL / portTICK_RATE_MS )
+
+/* The LED toggle by the check timer. */
+#define mainCHECK_LED						( 4 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Register check tasks, as described at the top of this file.  The nature of
+ * these files necessitates that they are written in an assembly.
+ */
+extern void vRegTest1Task( void *pvParameters );
+extern void vRegTest2Task( void *pvParameters );
+
+/*
+ * The hardware only has a single LED.  Simply toggle it.
+ */
+extern void vMainToggleLED( void );
+
+/*
+ * The check timer callback function, as described at the top of this file.
+ */
+static void prvCheckTimerCallback( xTimerHandle xTimer );
+
+/*
+ * The flash timer callback function, as described at the top of this file.
+ * This callback function is assigned to three separate software timers.
+ */
+static void prvFlashTimerCallback( xTimerHandle xTimer );
+
+/*
+ * Called by main() to create the comprehensive test/demo application if
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not set to 1.
+ */
+void main_full( void );
+
+/*-----------------------------------------------------------*/
+
+/* The following two variables are used to communicate the status of the
+register check tasks to the check software timer.  If the variables keep
+incrementing, then the register check tasks has not discovered any errors.  If
+a variable stops incrementing, then an error has been found. */
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+xTimerHandle xTimer = NULL;
+unsigned long ulTimer;
+const unsigned long ulTimersToCreate = 3L;
+/* The register test tasks are asm functions that don't use a stack.  The
+stack allocated just has to be large enough to hold the task context, and
+for the additional required for the stack overflow checking to work (if
+configured). */
+const size_t xRegTestStackSize = 25U;
+
+	/* Create the standard demo tasks */
+	vCreateBlockTimeTasks();
+	vStartCountingSemaphoreTasks();
+	vStartRecursiveMutexTasks();
+	vStartDynamicPriorityTasks();
+
+	/* Create the register test tasks as described at the top of this file.
+	These are naked functions that don't use any stack.  A stack still has
+	to be allocated to hold the task context. */
+	xTaskCreate( 	vRegTest1Task,			/* Function that implements the task. */
+					( signed char * ) "Reg1", /* Text name of the task. */
+					xRegTestStackSize,		/* Stack allocated to the task. */
+					NULL, 					/* The task parameter is not used. */
+					tskIDLE_PRIORITY, 		/* The priority to assign to the task. */
+					NULL );					/* Don't receive a handle back, it is not needed. */
+
+	xTaskCreate( 	vRegTest2Task,			/* Function that implements the task. */
+					( signed char * ) "Reg2", /* Text name of the task. */
+					xRegTestStackSize,		/* Stack allocated to the task. */
+					NULL, 					/* The task parameter is not used. */
+					tskIDLE_PRIORITY, 		/* The priority to assign to the task. */
+					NULL );					/* Don't receive a handle back, it is not needed. */
+
+	/* Create the three flash timers. */
+	for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ )
+	{
+		xTimer = xTimerCreate( 	( const signed char * ) "FlashTimer",	/* A text name, purely to help debugging. */
+								( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ),	/* The timer period, in this case 3000ms (3s). */
+								pdTRUE,									/* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+								( void * ) ulTimer,						/* The ID is used to hold the number of the LED that will be flashed. */
+								prvFlashTimerCallback					/* The callback function that inspects the status of all the other tasks. */
+							);
+
+		if( xTimer != NULL )
+		{
+			xTimerStart( xTimer, mainDONT_BLOCK );
+		}
+	}
+
+	/* Create the software timer that performs the 'check' functionality,
+	as described at the top of this file. */
+	xTimer = xTimerCreate( 	( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
+							( mainCHECK_TIMER_PERIOD_MS ),		/* The timer period, in this case 3000ms (3s). */
+							pdTRUE,								/* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+							( void * ) 0,						/* The ID is not used, so can be set to anything. */
+							prvCheckTimerCallback				/* The callback function that inspects the status of all the other tasks. */
+					  	);
+
+	/* If the software timer was created successfully, start it.  It won't
+	actually start running until the scheduler starts.  A block time of
+	zero is used in this call, although any value could be used as the block
+	time will be ignored because the scheduler has not started yet. */
+	if( xTimer != NULL )
+	{
+		xTimerStart( xTimer, mainDONT_BLOCK );
+	}
+
+	/* Start the kernel.  From here on, only tasks and interrupts will run. */
+	vTaskStartScheduler();
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then there
+	was	insufficient FreeRTOS heap memory available for the idle and/or timer
+	tasks to be created.  See the memory management section on the FreeRTOS web
+	site, or the FreeRTOS tutorial books for more details. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/* See the description at the top of this file. */
+static void prvCheckTimerCallback( xTimerHandle xTimer )
+{
+static long lChangedTimerPeriodAlready = pdFALSE;
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+unsigned long ulErrorFound = pdFALSE;
+
+	/* Check all the demo and test tasks to ensure that they are all still
+	running, and that none have detected an error. */
+	if( xAreDynamicPriorityTasksStillRunning() != pdPASS )
+	{
+		ulErrorFound |= ( 0x01UL << 0UL );
+	}
+
+	if( xAreBlockTimeTestTasksStillRunning() != pdPASS )
+	{
+		ulErrorFound |= ( 0x01UL << 1UL );
+	}
+
+	if( xAreCountingSemaphoreTasksStillRunning() != pdPASS )
+	{
+		ulErrorFound |= ( 0x01UL << 2UL );
+	}
+
+	if( xAreRecursiveMutexTasksStillRunning() != pdPASS )
+	{
+		ulErrorFound |= ( 0x01UL << 3UL );
+	}
+
+	/* Check that the register test 1 task is still running. */
+	if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+	{
+		ulErrorFound |= ( 0x01UL << 4UL );
+	}
+	ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+	/* Check that the register test 2 task is still running. */
+	if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+	{
+		ulErrorFound |= ( 0x01UL << 5UL );
+	}
+	ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+	/* Toggle the check LED to give an indication of the system status.  If
+	the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
+	everything is ok.  A faster toggle indicates an error. */
+	vParTestToggleLED( mainCHECK_LED );
+
+	/* Have any errors been latched in ulErrorFound?  If so, shorten the
+	period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
+	This will result in an increase in the rate at which mainCHECK_LED
+	toggles. */
+	if( ulErrorFound != pdFALSE )
+	{
+		if( lChangedTimerPeriodAlready == pdFALSE )
+		{
+			lChangedTimerPeriodAlready = pdTRUE;
+
+			/* This call to xTimerChangePeriod() uses a zero block time.
+			Functions called from inside of a timer callback function must
+			*never* attempt	to block. */
+			xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvFlashTimerCallback( xTimerHandle xTimer )
+{
+unsigned long ulLED;
+
+	/* This callback function is assigned to three separate software timers.
+	Each timer toggles a different LED.  Obtain the number of the LED that
+	this timer is toggling. */
+	ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer );
+
+	/* Toggle the LED. */
+	vParTestToggleLED( ulLED );
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c
new file mode 100644
index 000000000..6707792fe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c
@@ -0,0 +1,231 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/******************************************************************************
+ * This project provides two demo applications.  A simple blinky style project,
+ * and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
+ * select between the two.  The simply blinky demo is implemented and described
+ * in main_blinky.c.  The more comprehensive test and demo application is
+ * implemented and described in main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and FreeRTOS hook functions.  It also contains a dummy
+ * interrupt service routine called Dummy_IRQHandler() that is provided as an
+ * example of how to use interrupt safe FreeRTOS API functions (those that end
+ * in "FromISR").
+ *
+ *****************************************************************************/
+
+
+/* Standard includes. */
+#include "string.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application include. */
+#include "ParTest.h"
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY	0
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform any application specific hardware configuration.  The clocks,
+ * memory, etc. are configured before main() is called.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+extern void main_blinky( void );
+extern void main_full( void );
+
+/*
+ * CMSIS clock configuration function.
+ */
+extern void SystemCoreClockUpdate( void );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+	/* Prepare the hardware to run this demo. */
+	prvSetupHardware();
+
+	/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+	of this file. */
+	#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+	{
+		main_blinky();
+	}
+	#else
+	{
+		main_full();
+	}
+	#endif
+
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	SystemCoreClockUpdate();
+	vParTestInitialise();
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+	/* This function will be called by each tick interrupt if
+	configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h.  User code can be
+	added here, but the tick hook is called from an interrupt context, so
+	code must not attempt to block, and only the interrupt safe FreeRTOS API
+	functions can be used (those that end in FromISR()). */
+}
+/*-----------------------------------------------------------*/
+
+#ifdef JUST_AN_EXAMPLE_ISR
+
+void Dummy_IRQHandler(void)
+{
+long lHigherPriorityTaskWoken = pdFALSE;
+
+	/* Clear the interrupt if necessary. */
+	Dummy_ClearITPendingBit();
+
+	/* This interrupt does nothing more than demonstrate how to synchronise a
+	task with an interrupt.  A semaphore is used for this purpose.  Note
+	lHigherPriorityTaskWoken is initialised to zero. Only FreeRTOS API functions
+	that end in "FromISR" can be called from an ISR. */
+	xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
+
+	/* If there was a task that was blocked on the semaphore, and giving the
+	semaphore caused the task to unblock, and the unblocked task has a priority
+	higher than the current Running state task (the task that this interrupt
+	interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE
+	internally within xSemaphoreGiveFromISR().  Passing pdTRUE into the
+	portEND_SWITCHING_ISR() macro will result in a context switch being pended to
+	ensure this interrupt returns directly to the unblocked, higher priority,
+	task.  Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */
+	portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
+}
+
+#endif /* JUST_AN_EXAMPLE_ISR */
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.cspy.bat b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.cspy.bat
new file mode 100644
index 000000000..24de1fdcf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.cspy.bat
@@ -0,0 +1,24 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armjlink.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\Infineon\FlashXMC1200.board" --backend -B "--endian=little" "--cpu=Cortex-M0" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Infineon\xmc1200.ddf" "--drv_verify_download" "--semihosting" "--device=xmc1200" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=72000000,0,2000000" 
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.dni
new file mode 100644
index 000000000..076f53409
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.dni
@@ -0,0 +1,113 @@
+[DebugChecksum]
+Checksum=-2111807952
+[Stack]
+FillEnabled=0
+OverflowWarningsEnabled=1
+WarningThreshold=90
+SpWarningsEnabled=1
+WarnLogOnly=1
+UseTrigger=1
+TriggerName=main
+LimitSize=0
+ByteLimit=50
+[Exceptions]
+StopOnUncaught=_ 0
+StopOnThrow=_ 0
+[CallStack]
+ShowArgs=0
+[Disassembly]
+MixedMode=1
+[JLinkDriver]
+CStepIntDis=_ 0
+[SWOTraceHWSettings]
+OverrideDefaultClocks=0
+CpuClock=72000000
+ClockAutoDetect=0
+ClockWanted=1000000
+JtagSpeed=1000000
+Prescaler=72
+TimeStampPrescIndex=0
+TimeStampPrescData=0
+PcSampCYCTAP=1
+PcSampPOSTCNT=15
+PcSampIndex=0
+DataLogMode=0
+ITMportsEnable=0
+ITMportsTermIO=0
+ITMportsLogFile=0
+ITMlogFile=$PROJ_DIR$\ITM.log
+[PowerLog]
+LogEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=0
+Title0=I0
+Symbol0=0 4 1
+LiveEnabled=0
+LiveFile=PowerLogLive.log
+[DataLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+[EventLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+Title0=Ch0
+Symbol0=0 4 1
+Title1=Ch1
+Symbol1=0 4 1
+Title2=Ch2
+Symbol2=0 4 1
+Title3=Ch3
+Symbol3=0 4 1
+SumSortOrder=0
+[InterruptLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+SumSortOrder=0
+[Log file]
+LoggingEnabled=_ 0
+LogFile=_ ""
+Category=_ 0
+[TermIOLog]
+LoggingEnabled=_ 0
+LogFile=_ ""
+[Trace2]
+Enabled=0
+ShowSource=0
+[SWOTraceWindow]
+PcSampling=0
+InterruptLogs=0
+ForcedTimeStamps=0
+EventCPI=0
+EventEXC=0
+EventFOLD=0
+EventLSU=0
+EventSLEEP=0
+[PowerProbe]
+Frequency=10000
+Probe0=I0
+ProbeSetup0=2 1 1 2 0 0
+[CallStackLog]
+Enabled=0
+[DriverProfiling]
+Enabled=0
+Mode=3
+Graph=0
+Symbiont=0
+Exclusions=
+[Disassemble mode]
+mode=0
+[Breakpoints2]
+Count=0
+[Aliases]
+Count=0
+SuppressDialog=0
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.wsdt
new file mode 100644
index 000000000..4df60d42c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo.wsdt
@@ -0,0 +1,67 @@
+
+
+
+  
+    
+  RTOSDemo/Debug
+  
+    
+      
+        
+          
+          
+          
+          
+        236272727
+      
+      
+        
+        
+        
+        
+      20121632481
+      
+    
+    
+      
+      
+    
+        
+          
+            TabID-23707-15152
+            Workspace
+            Workspace
+            
+              
+            RTOSDemoRTOSDemo/System
+          
+        
+        
+      0
+        
+          
+            TabID-19002-15240
+            Build
+            Build
+            
+          
+        
+        
+      0
+    
+      
+      
+      
+      
+    TextEditor$WS_DIR$\main.c000009955095509TextEditor$WS_DIR$\main-full.c000001117445744510100000010000001
+    
+      
+      
+      
+      
+      
+    iaridepm.enu1-2-2740310-2-2200200119048203666185714755601-2-21981682-2-216842001002381203666119048203666
+  
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo_Debug.jlink b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo_Debug.jlink
new file mode 100644
index 000000000..de1b137f3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/settings/RTOSDemo_Debug.jlink
@@ -0,0 +1,34 @@
+[BREAKPOINTS]
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 0
+Device="UNSPECIFIED"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/system_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/system_XMC1200.c
new file mode 100644
index 000000000..05934bb6f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/system_XMC1200.c
@@ -0,0 +1,130 @@
+/******************************************************************************
+ * @file     system_XMC1200.c
+ * @brief    Device specific initialization for the XMC1200-Series according
+ * to CMSIS
+ * @version  V1.4
+ * @date     01 Feb 2013
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with
+ * Infineon’s microcontrollers.
+ *
+ * This file can be freely distributed within development tools that are
+ * supporting such microcontrollers.
+ *
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+ * *************************** Change history ********************************
+ * V1.2, 13 Dec 2012, PKB : Created change history table
+ * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation
+ * V1.4, 01 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK
+ */
+
+#include "system_XMC1200.h"
+#include 
+
+/*---------------------------------------------------------------------------
+ Extern definitions
+ *--------------------------------------------------------------------------*/
+extern uint32_t AllowClkInitByStartup(void);
+
+/*----------------------------------------------------------------------------
+  Clock Global defines
+ *----------------------------------------------------------------------------*/
+#define DCO_DCLK                  64000000UL
+#define DCO_DCLK_MULTIPLIER       16384000UL
+#define DCO_DCLK_DIVIDER          9UL
+#define MCLK_MHZ                  32000000UL
+#define KHZ_MULTIPLIER            1000UL
+#define FRACBITS                  8UL
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */
+uint32_t SystemCoreClock;
+
+/*----------------------------------------------------------------------------
+  Fixed point math definitions
+ *----------------------------------------------------------------------------*/
+typedef int32_t Q_24_8;
+typedef int32_t Q_15_0;
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+
+  /*
+   * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE
+   * Clock app.
+   */
+  if(AllowClkInitByStartup()){
+  /* Do not change default values of IDIV,FDIV and RTCCLKSEL */
+  /* ====== Default configuration ======= */
+  /*
+   * MCLK    = DCO_DCLK
+   * PCLK    = MCLK
+   * RTC CLK = Standby clock
+   */
+  }
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t IDIV, FDIV, CLKCR, Clock;
+
+  CLKCR = SCU_CLK -> CLKCR;
+  IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
+  FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;
+
+  if(IDIV)
+  {
+    /* Divider is enabled and used */
+    if(0 == FDIV)
+     {
+       /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */
+       Clock = MCLK_MHZ / IDIV;
+     }
+    else
+     {
+       /* Both integer and fractional divider must be considered */
+       /* 1. IDIV + FDIV/256 */
+       Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV;
+
+       /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */
+       Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum;
+       Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER;
+       Clock = Clock >> DCO_DCLK_DIVIDER;
+     }
+  }
+  else
+  {
+    /* Divider bypassed. Simply divide DCO_DCLK by 2 */
+    Clock = MCLK_MHZ;
+  }
+
+  /* Finally with the math class over, update SystemCoreClock */
+  SystemCoreClock = Clock;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/system_XMC1200.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/system_XMC1200.h
new file mode 100644
index 000000000..476fcfe87
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/system_XMC1200.h
@@ -0,0 +1,55 @@
+/******************************************************************************
+ * @file     system_XMC1200.h
+ * @brief    Device specific initialization for the XMC1200-Series according 
+ * to CMSIS
+ * @version  V1.1
+ * @date     13 Dec 2012
+ *
+ * @note
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with 
+ * Infineon’s microcontrollers.
+ *   
+ * This file can be freely distributed within development tools that are 
+ * supporting such microcontrollers.
+ *  
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/* 
+ * **************************** Change history *******************************
+ * V1.1, 13 Dec 2012, PKB : Created this table, added extern and stdint
+ */
+
+#include 
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+extern uint32_t SystemCoreClock;
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void);
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  * @note   -  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void);
+
diff --git a/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/FreeRTOSConfig.h
index 917c3d486..bedf9458d 100644
--- a/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/FreeRTOSConfig.h
@@ -115,20 +115,6 @@ We use --gc-sections when linking, so there is no harm is setting all of these t
 #define BLOCKQ_1						1
 
 
-
-
-/* A task is created to test the behaviour of the interrupt controller during
-context switches.  This macro is just used to set a variable to true each time
-the test task is switched out - the task itself needs to know when this happens
-in order to complete its tests.  This macro will slow down the context switch
-and can normally be removed (just delete the whole macro, although doing so will
-cause the test task to indicate an error). */
-extern void *xICTestTask;
-extern volatile unsigned long ulTaskSwitchedOut;
-#define traceTASK_SWITCHED_OUT() if( pxCurrentTCB == xICTestTask ) ulTaskSwitchedOut = pdTRUE
-
-
-
 #endif /* FREERTOS_CONFIG_H */
 
 
diff --git a/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/RegTest.c b/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/RegTest.c
index 5deee05d3..7c08850a1 100644
--- a/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/RegTest.c
+++ b/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/RegTest.c
@@ -77,33 +77,15 @@
 static void vRegTest1( void *pvParameters );
 static void vRegTest2( void *pvParameters );
 
-/*
- * A task that tests the management of the Interrupt Controller (IC) during a
- * context switch.  The state of the IC current mask level must be maintained
- * across context switches.  Also, yields must be able to be performed when the
- * interrupt controller mask is not zero.  This task tests both these
- * requirements.
- */
-static void prvICCheck1Task( void *pvParameters );
-
 /* Counters used to ensure the tasks are still running. */
-static volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL, ulICTestCounter = 0UL;
+static volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;
 
-/* Handle to the task that checks the interrupt controller behaviour.  This is
-used by the traceTASK_SWITCHED_OUT() macro, which is defined in
-FreeRTOSConfig.h and can be removed - it is just for the purpose of this test. */
-xTaskHandle xICTestTask = NULL;
-
-/* Variable that gets set to pdTRUE by traceTASK_SWITCHED_OUT each time
-is switched out. */
-volatile unsigned long ulTaskSwitchedOut;
 /*-----------------------------------------------------------*/
 
 void vStartRegTestTasks( void )
 {
 	xTaskCreate( vRegTest1, ( signed char * ) "RTest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
 	xTaskCreate( vRegTest2, ( signed char * ) "RTest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-	xTaskCreate( prvICCheck1Task, ( signed char * ) "ICCheck", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xICTestTask );
 }
 /*-----------------------------------------------------------*/
 
@@ -232,61 +214,9 @@ static void vRegTest2( void *pvParameters )
 }
 /*-----------------------------------------------------------*/
 
-static void prvICCheck1Task( void *pvParameters )
-{
-long lICCheckStatus = pdPASS;
-
-	for( ;; )
-	{
-		/* At this point the interrupt mask should be zero. */
-		if( ic->cpl != 0 )
-		{
-			lICCheckStatus = pdFAIL;
-		}
-
-		/* If we yield here, it should still be 0 when the task next runs.
-		ulTaskSwitchedOut is just used to check that a switch does actually
-		happen. */
-		ulTaskSwitchedOut = pdFALSE;
-		taskYIELD();
-		if( ( ulTaskSwitchedOut != pdTRUE ) || ( ic->cpl != 0 ) )
-		{
-			lICCheckStatus = pdFAIL;
-		}
-
-		/* Set the interrupt mask to portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1,
-		before checking it is as expected. */
-		taskENTER_CRITICAL();
-		if( ic->cpl != ( portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1 ) )
-		{
-			lICCheckStatus = pdFAIL;
-		}
-
-		/* If we yield here, it should still be
-		portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 10 when the task next runs.  */
-		ulTaskSwitchedOut = pdFALSE;
-		taskYIELD();
-		if( ( ulTaskSwitchedOut != pdTRUE ) || ( ic->cpl != ( portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1 ) ) )
-		{
-			lICCheckStatus = pdFAIL;
-		}
-
-		/* Return the interrupt mask to its default state. */
-		taskEXIT_CRITICAL();
-
-		/* Just increment a loop counter so the check task knows if this task
-		is still running or not. */
-		if( lICCheckStatus == pdPASS )
-		{
-			ulICTestCounter++;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
 portBASE_TYPE xAreRegTestTasksStillRunning( void )
 {
-static unsigned long ulLastCounter1 = 0UL, ulLastCounter2 = 0UL, ulLastICTestCounter = 0UL;
+static unsigned long ulLastCounter1 = 0UL, ulLastCounter2 = 0UL;
 long lReturn;
 
 	/* Check that both loop counters are still incrementing, indicating that
@@ -299,10 +229,6 @@ long lReturn;
 	{
 		lReturn = pdFAIL;
 	}
-	else if( ulLastICTestCounter == ulICTestCounter )
-	{
-		lReturn = pdFAIL;
-	}
 	else
 	{
 		lReturn = pdPASS;
@@ -310,21 +236,6 @@ long lReturn;
 
 	ulLastCounter1 = ulRegTest1Counter;
 	ulLastCounter2 = ulRegTest2Counter;
-	ulLastICTestCounter = ulICTestCounter;
 
 	return lReturn;
 }
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/serial.c b/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/serial.c
index 88b469397..a29f99578 100644
--- a/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/serial.c
+++ b/FreeRTOS/Demo/CORTUS_APS3_GCC/Demo/serial.c
@@ -96,7 +96,6 @@ static void prvRxHandler( void ) __attribute__((noinline));
 transmitted. */
 static xQueueHandle xRxedChars;
 static xQueueHandle xCharsForTx;
-extern unsigned portBASE_TYPE *pxVectorTable;
 /*-----------------------------------------------------------*/
 
 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
@@ -112,9 +111,7 @@ xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned port
 		uart1->tx_mask = 0;
 		uart1->rx_mask = 1;
 		irq[IRQ_UART1_TX].ien = 1;
-		irq[IRQ_UART1_TX].ipl = portSYSTEM_INTERRUPT_PRIORITY_LEVEL;
 		irq[IRQ_UART1_RX].ien = 1;
-		irq[IRQ_UART1_RX].ipl = portSYSTEM_INTERRUPT_PRIORITY_LEVEL;
 	}
 
 	return ( xComPortHandle ) 0;