From: wdenk Date: Fri, 23 May 2003 12:36:20 +0000 (+0000) Subject: Patch by Kyle Harris, 20 May 2003: X-Git-Tag: LABEL_2006_03_12_0025~867 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=4c3b21a5f915988e3d9681cf9cb566bb7bd56859;p=u-boot Patch by Kyle Harris, 20 May 2003: In preparation for an ixp port, rename cpu/xscale and arch-xscale into cpu/pxa and arch-pxa. --- diff --git a/CHANGELOG b/CHANGELOG index a155344994..733a1d3ea1 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,10 @@ Changes since U-Boot 0.3.1: ====================================================================== +* Patch by Kyle Harris, 20 May 2003: + In preparation for an ixp port, rename cpu/xscale and arch-xscale + into cpu/pxa and arch-pxa. + * Patch by Stefan Roese, 23 May 2003: - IBM PPC405EP port added. - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not diff --git a/MAKEALL b/MAKEALL index 9d08b50b54..d577aaec56 100644 --- a/MAKEALL +++ b/MAKEALL @@ -114,10 +114,10 @@ LIST_ARM9="at91rm9200dk smdk2400 smdk2410 trab VCMA9" ## Xscale Systems ######################################################################### -LIST_xscale="cradle csb226 innokom lubbock wepep250" +LIST_pxa="cradle csb226 innokom lubbock wepep250" -LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_xscale}" +LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa}" ######################################################################### ## MIPS 4Kc Systems @@ -150,7 +150,7 @@ build_target() { for arg in $@ do case "$arg" in - 5xx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|xscale|mips) + 5xx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips) for target in `eval echo '$LIST_'${arg}` do build_target ${target} diff --git a/Makefile b/Makefile index 3e66bf0b2a..539d4998e5 100644 --- a/Makefile +++ b/Makefile @@ -706,19 +706,19 @@ ep7312_config : unconfig ######################################################################### cradle_config : unconfig - @./mkconfig $(@:_config=) arm xscale cradle + @./mkconfig $(@:_config=) arm pxa cradle csb226_config : unconfig - @./mkconfig $(@:_config=) arm xscale csb226 + @./mkconfig $(@:_config=) arm pxa csb226 innokom_config : unconfig - @./mkconfig $(@:_config=) arm xscale innokom + @./mkconfig $(@:_config=) arm pxa innokom lubbock_config : unconfig - @./mkconfig $(@:_config=) arm xscale lubbock + @./mkconfig $(@:_config=) arm pxa lubbock wepep250_config : unconfig - @./mkconfig $(@:_config=) arm xscale wepep250 + @./mkconfig $(@:_config=) arm pxa wepep250 #======================================================================== # i386 diff --git a/board/cradle/u-boot.lds b/board/cradle/u-boot.lds index 280fc48ace..46beb152c7 100644 --- a/board/cradle/u-boot.lds +++ b/board/cradle/u-boot.lds @@ -31,7 +31,7 @@ SECTIONS . = ALIGN(4); .text : { - cpu/xscale/start.o (.text) + cpu/pxa/start.o (.text) *(.text) } diff --git a/board/csb226/u-boot.lds b/board/csb226/u-boot.lds index 280fc48ace..46beb152c7 100644 --- a/board/csb226/u-boot.lds +++ b/board/csb226/u-boot.lds @@ -31,7 +31,7 @@ SECTIONS . = ALIGN(4); .text : { - cpu/xscale/start.o (.text) + cpu/pxa/start.o (.text) *(.text) } diff --git a/board/innokom/u-boot.lds b/board/innokom/u-boot.lds index 280fc48ace..46beb152c7 100644 --- a/board/innokom/u-boot.lds +++ b/board/innokom/u-boot.lds @@ -31,7 +31,7 @@ SECTIONS . = ALIGN(4); .text : { - cpu/xscale/start.o (.text) + cpu/pxa/start.o (.text) *(.text) } diff --git a/board/lubbock/u-boot.lds b/board/lubbock/u-boot.lds index 280fc48ace..46beb152c7 100644 --- a/board/lubbock/u-boot.lds +++ b/board/lubbock/u-boot.lds @@ -31,7 +31,7 @@ SECTIONS . = ALIGN(4); .text : { - cpu/xscale/start.o (.text) + cpu/pxa/start.o (.text) *(.text) } diff --git a/board/wepep250/u-boot.lds b/board/wepep250/u-boot.lds index 280fc48ace..46beb152c7 100644 --- a/board/wepep250/u-boot.lds +++ b/board/wepep250/u-boot.lds @@ -31,7 +31,7 @@ SECTIONS . = ALIGN(4); .text : { - cpu/xscale/start.o (.text) + cpu/pxa/start.o (.text) *(.text) } diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile new file mode 100644 index 0000000000..778a6646f8 --- /dev/null +++ b/cpu/pxa/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = serial.o interrupts.o cpu.o i2c.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk new file mode 100644 index 0000000000..c40dcf8614 --- /dev/null +++ b/cpu/pxa/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -mshort-load-bytes -msoft-float + +PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c new file mode 100644 index 0000000000..6a3c24deda --- /dev/null +++ b/cpu/pxa/cpu.c @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include + +int cpu_init (void) +{ + /* + * setup up stack if necessary + */ +/* + + FIXME: the stack is _below_ the uboot code!! + +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_end + + CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4; + FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; + _armboot_real_end = FIQ_STACK_START + 4; +#else + _armboot_real_end = _armboot_end + CONFIG_STACKSIZE; +#endif +*/ + return (0); +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * just disable everything that can disturb booting linux + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~0x1000; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern void reset_cpu (ulong addr); + + printf ("reseting ...\n"); + + udelay (50000); /* wait 50 ms */ + disable_interrupts (); + reset_cpu (0); + + /*NOTREACHED*/ + return (0); +} + +/* taken from blob */ +void icache_enable (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* set i-cache */ + i |= 0x1000; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void icache_disable (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* clear i-cache */ + i &= ~0x1000; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush i-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); +} + +int icache_status (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* return bit */ + return (i & 0x1000); +} + +/* we will never enable dcache, because we have to setup MMU first */ +void dcache_enable (void) +{ + return; +} + +void dcache_disable (void) +{ + return; +} + +int dcache_status (void) +{ + return 0; /* always off */ +} diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c new file mode 100644 index 0000000000..406f825cd5 --- /dev/null +++ b/cpu/pxa/i2c.c @@ -0,0 +1,460 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2003 Pengutronix e.K. + * Robert Schwebel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. + */ + +/* FIXME: this file is PXA255 specific! What about other XScales? */ + +#include + +#ifdef CONFIG_HARD_I2C + +/* + * - CFG_I2C_SPEED + * - I2C_PXA_SLAVE_ADDR + */ + +#include +#include +#include + +//#define DEBUG_I2C 1 /* activate local debugging output */ +#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) +#define I2C_ISR_INIT 0x7FF + +#ifdef DEBUG_I2C +#define PRINTD(x) printf x +#else +#define PRINTD(x) +#endif + + +/* Shall the current transfer have a start/stop condition? */ +#define I2C_COND_NORMAL 0 +#define I2C_COND_START 1 +#define I2C_COND_STOP 2 + +/* Shall the current transfer be ack/nacked or being waited for it? */ +#define I2C_ACKNAK_WAITACK 1 +#define I2C_ACKNAK_SENDACK 2 +#define I2C_ACKNAK_SENDNAK 4 + +/* Specify who shall transfer the data (master or slave) */ +#define I2C_READ 0 +#define I2C_WRITE 1 + +/* All transfers are described by this data structure */ +struct i2c_msg { + u8 condition; + u8 acknack; + u8 direction; + u8 data; +}; + + +/** + * i2c_pxa_reset: - reset the host controller + * + */ + +static void i2c_reset( void ) +{ + ICR &= ~ICR_IUE; /* disable unit */ + ICR |= ICR_UR; /* reset the unit */ + udelay(100); + ICR &= ~ICR_IUE; /* disable unit */ + CKEN |= CKEN14_I2C; /* set the global I2C clock on */ + ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ + ICR = I2C_ICR_INIT; /* set control register values */ + ISR = I2C_ISR_INIT; /* set clear interrupt bits */ + ICR |= ICR_IUE; /* enable unit */ + udelay(100); +} + + +/** + * i2c_isr_set_cleared: - wait until certain bits of the I2C status register + * are set and cleared + * + * @return: 0 in case of success, 1 means timeout (no match within 10 ms). + */ + +static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) +{ + int timeout = 10000; + + while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){ + udelay( 10 ); + if( timeout-- < 0 ) return 0; + } + + return 1; +} + + +/** + * i2c_transfer: - Transfer one byte over the i2c bus + * + * This function can tranfer a byte over the i2c bus in both directions. + * It is used by the public API functions. + * + * @return: 0: transfer successful + * -1: message is empty + * -2: transmit timeout + * -3: ACK missing + * -4: receive timeout + * -5: illegal parameters + * -6: bus is busy and couldn't be aquired + */ +int i2c_transfer(struct i2c_msg *msg) +{ + int ret; + + if (!msg) + goto transfer_error_msg_empty; + + switch(msg->direction) { + + case I2C_WRITE: + + /* check if bus is not busy */ + if (!i2c_isr_set_cleared(0,ISR_IBB)) + goto transfer_error_bus_busy; + + /* start transmission */ + ICR &= ~ICR_START; + ICR &= ~ICR_STOP; + IDBR = msg->data; + if (msg->condition == I2C_COND_START) ICR |= ICR_START; + if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; + if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; + if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; + ICR &= ~ICR_ALDIE; + ICR |= ICR_TB; + + /* transmit register empty? */ + if (!i2c_isr_set_cleared(ISR_ITE,0)) + goto transfer_error_transmit_timeout; + + /* clear 'transmit empty' state */ + ISR |= ISR_ITE; + + /* wait for ACK from slave */ + if (msg->acknack == I2C_ACKNAK_WAITACK) + if (!i2c_isr_set_cleared(0,ISR_ACKNAK)) + goto transfer_error_ack_missing; + break; + + case I2C_READ: + + /* check if bus is not busy */ + if (!i2c_isr_set_cleared(0,ISR_IBB)) + goto transfer_error_bus_busy; + + /* start receive */ + ICR &= ~ICR_START; + ICR &= ~ICR_STOP; + if (msg->condition == I2C_COND_START) ICR |= ICR_START; + if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; + if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; + if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; + ICR &= ~ICR_ALDIE; + ICR |= ICR_TB; + + /* receive register full? */ + if (!i2c_isr_set_cleared(ISR_IRF,0)) + goto transfer_error_receive_timeout; + + msg->data = IDBR; + + /* clear 'receive empty' state */ + ISR |= ISR_IRF; + + break; + + default: + + goto transfer_error_illegal_param; + + } + + return 0; + +transfer_error_msg_empty: + PRINTD(("i2c_transfer: error: 'msg' is empty\n")); + ret = -1; goto i2c_transfer_finish; + +transfer_error_transmit_timeout: + PRINTD(("i2c_transfer: error: transmit timeout\n")); + ret = -2; goto i2c_transfer_finish; + +transfer_error_ack_missing: + PRINTD(("i2c_transfer: error: ACK missing\n")); + ret = -3; goto i2c_transfer_finish; + +transfer_error_receive_timeout: + PRINTD(("i2c_transfer: error: receive timeout\n")); + ret = -4; goto i2c_transfer_finish; + +transfer_error_illegal_param: + PRINTD(("i2c_transfer: error: illegal parameters\n")); + ret = -5; goto i2c_transfer_finish; + +transfer_error_bus_busy: + PRINTD(("i2c_transfer: error: bus is busy\n")); + ret = -6; goto i2c_transfer_finish; + +i2c_transfer_finish: + PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR)); + i2c_reset(); + return ret; + +} + +/* ------------------------------------------------------------------------ */ +/* API Functions */ +/* ------------------------------------------------------------------------ */ + +void i2c_init(int speed, int slaveaddr) +{ +#ifdef CFG_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif +} + + +/** + * i2c_probe: - Test if a chip answers for a given i2c address + * + * @chip: address of the chip which is searched for + * @return: 0 if a chip was found, -1 otherwhise + */ + +int i2c_probe(uchar chip) +{ + struct i2c_msg msg; + + i2c_reset(); + + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1) + 1; + if (i2c_transfer(&msg)) return -1; + + msg.condition = I2C_COND_STOP; + msg.acknack = I2C_ACKNAK_SENDNAK; + msg.direction = I2C_READ; + msg.data = 0x00; + if (i2c_transfer(&msg)) return -1; + + return 0; +} + + +/** + * i2c_read: - Read multiple bytes from an i2c device + * + * The higher level routines take into account that this function is only + * called with len < page length of the device (see configuration file) + * + * @chip: address of the chip which is to be read + * @addr: i2c data address within the chip + * @alen: length of the i2c data address (1..2 bytes) + * @buffer: where to write the data + * @len: how much byte do we want to read + * @return: 0 in case of success + */ + +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + struct i2c_msg msg; + u8 addr_bytes[3]; /* lowest...highest byte of data address */ + int ret; + + PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); + + i2c_reset(); + + /* dummy chip address write */ + PRINTD(("i2c_read: dummy chip address write\n")); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data &= 0xFE; + if ((ret=i2c_transfer(&msg))) return -1; + + /* + * send memory address bytes; + * alen defines how much bytes we have to send. + */ + //addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); + addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); + addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); + addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); + + while (--alen >= 0) { + + PRINTD(("i2c_read: send memory word address byte %1d\n",alen)); + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = addr_bytes[alen]; + if ((ret=i2c_transfer(&msg))) return -1; + } + + + /* start read sequence */ + PRINTD(("i2c_read: start read sequence\n")); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data |= 0x01; + if ((ret=i2c_transfer(&msg))) return -1; + + /* read bytes; send NACK at last byte */ + while (len--) { + + if (len==0) { + msg.condition = I2C_COND_STOP; + msg.acknack = I2C_ACKNAK_SENDNAK; + } else { + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_SENDACK; + } + + msg.direction = I2C_READ; + msg.data = 0x00; + if ((ret=i2c_transfer(&msg))) return -1; + + *(buffer++) = msg.data; + + PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); + + } + + i2c_reset(); + + return 0; +} + + +/** + * i2c_write: - Write multiple bytes to an i2c device + * + * The higher level routines take into account that this function is only + * called with len < page length of the device (see configuration file) + * + * @chip: address of the chip which is to be written + * @addr: i2c data address within the chip + * @alen: length of the i2c data address (1..2 bytes) + * @buffer: where to find the data to be written + * @len: how much byte do we want to read + * @return: 0 in case of success + */ + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + struct i2c_msg msg; + u8 addr_bytes[3]; /* lowest...highest byte of data address */ + + PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); + + i2c_reset(); + + /* chip address write */ + PRINTD(("i2c_write: chip address write\n")); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data &= 0xFE; + if (i2c_transfer(&msg)) return -1; + + /* + * send memory address bytes; + * alen defines how much bytes we have to send. + */ + addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); + addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); + addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); + + while (--alen >= 0) { + + PRINTD(("i2c_write: send memory word address\n")); + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = addr_bytes[alen]; + if (i2c_transfer(&msg)) return -1; + } + + /* write bytes; send NACK at last byte */ + while (len--) { + + PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); + + if (len==0) + msg.condition = I2C_COND_STOP; + else + msg.condition = I2C_COND_NORMAL; + + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = *(buffer++); + + if (i2c_transfer(&msg)) return -1; + + } + + i2c_reset(); + + return 0; + +} + +uchar i2c_reg_read (uchar chip, uchar reg) +{ + PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); + return 0; +} + +void i2c_reg_write(uchar chip, uchar reg, uchar val) +{ + PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val)); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c new file mode 100644 index 0000000000..af7d63414e --- /dev/null +++ b/cpu/pxa/interrupts.c @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +extern void reset_cpu (ulong addr); + +#ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ +#error: interrupts not implemented yet +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ +#error: interrupts not implemented yet +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + + +int interrupt_init (void) +{ + /* nothing happens here - we don't setup any IRQs */ + return (0); +} + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked (); +} + +void set_timer (ulong t) +{ + /* nop */ +} + +void udelay (unsigned long usec) +{ + udelay_masked (usec); +} + + +void reset_timer_masked (void) +{ + OSCR = 0; +} + +ulong get_timer_masked (void) +{ + return OSCR; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + + reset_timer_masked (); + + while (tmo >= get_timer_masked ()) + /*NOP*/; +} diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c new file mode 100644 index 0000000000..c9d5f70bc4 --- /dev/null +++ b/cpu/pxa/serial.c @@ -0,0 +1,166 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned int quot = 0; + + if (gd->baudrate == 1200) + quot = 192; + else if (gd->baudrate == 9600) + quot = 96; + else if (gd->baudrate == 19200) + quot = 48; + else if (gd->baudrate == 38400) + quot = 24; + else if (gd->baudrate == 57600) + quot = 16; + else if (gd->baudrate == 115200) + quot = 8; + else + hang (); + +#ifdef CONFIG_FFUART + + CKEN |= CKEN6_FFUART; + + FFIER = 0; /* Disable for now */ + FFFCR = 0; /* No fifos enabled */ + + /* set baud rate */ + FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; + FFDLL = quot & 0xff; + FFDLH = quot >> 8; + FFLCR = LCR_WLS0 | LCR_WLS1; + + FFIER = IER_UUE; /* Enable FFUART */ + +#elif defined(CONFIG_BTUART) + CKEN |= CKEN7_BTUART; + + BTIER = 0; + BTFCR = 0; + + /* set baud rate */ + BTLCR = LCR_DLAB; + BTDLL = quot & 0xff; + BTDLH = quot >> 8; + BTLCR = LCR_WLS0 | LCR_WLS1; + + BTIER = IER_UUE; /* Enable BFUART */ + +#elif defined(CONFIG_STUART) +#error "Bad: not implemented yet!" +#else +#error "Bad: you didn't configured serial ..." +#endif +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ +#ifdef CONFIG_FFUART + /* wait for room in the tx FIFO on FFUART */ + while ((FFLSR & LSR_TEMT) == 0); + + FFTHR = c; +#elif defined(CONFIG_BTUART) + while ((BTLSR & LSR_TEMT ) == 0 ); + BTTHR = c; +#elif defined(CONFIG_STUART) +#endif + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_tstc (void) +{ +#ifdef CONFIG_FFUART + return FFLSR & LSR_DR; +#elif defined(CONFIG_BTUART) + return BTLSR & LSR_DR; +#elif defined(CONFIG_STUART) +#endif +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ +#ifdef CONFIG_FFUART + while (!(FFLSR & LSR_DR)); + + return (char) FFRBR & 0xff; +#elif defined(CONFIG_BTUART) + while (!(BTLSR & LSR_DR)); + + return (char) BTRBR & 0xff; +#elif defined(CONFIG_STUART) +#endif +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S new file mode 100644 index 0000000000..95b30e44e9 --- /dev/null +++ b/cpu/pxa/start.S @@ -0,0 +1,474 @@ +/* + * armboot - Startup Code for XScale + * + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000 Wolfgang Denk + * Copyright (C) 2001 Alex Züpke + * Copyright (C) 2002 Kyle Harris + * Copyright (C) 2003 Robert Schwebel + * Copyright (C) 2003 Kai-Uwe Bloehm + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * - relocate armboot to ram + * - setup stack + * - jump to second stage + */ + +/* + * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h) + */ +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * Note: _armboot_end_data and _armboot_end are defined + * by the (board-dependent) linker script. + * _armboot_end_data is the first usable FLASH address after armboot + */ +.globl _armboot_end_data +_armboot_end_data: + .word armboot_end_data +.globl _armboot_end +_armboot_end: + .word armboot_end + +/* + * This is defined in the board specific linker script + */ +.globl _bss_start +_bss_start: + .word bss_start + +.globl _bss_end +_bss_end: + .word bss_end + +/* + * _armboot_real_end is the first usable RAM address behind armboot + * and the various stacks + */ +.globl _armboot_real_end +_armboot_real_end: + .word 0x0badc0de + +/* + * We relocate uboot to this address (end of RAM - 128 KiB) + */ +.globl _uboot_reloc +_uboot_reloc: + .word TEXT_BASE + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/****************************************************************************/ +/* */ +/* the actual reset code */ +/* */ +/****************************************************************************/ + +reset: + mrs r0,cpsr /* set the cpu to SVC32 mode */ + bic r0,r0,#0x1f /* (superviser mode, M=10011) */ + orr r0,r0,#0x13 + msr cpsr,r0 + + bl cpu_init_crit /* we do sys-critical inits */ + +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _armboot_end + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + /* Set up the stack */ + +stack_setup: + + ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + /* FIXME: bdinfo should be here */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + + ldr r0, _bss_start /* find start of bss segment */ + add r0, r0, #4 /* start at first byte of bss */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/****************************************************************************/ +/* */ +/* CPU_init_critical registers */ +/* */ +/* - setup important registers */ +/* - setup memory timing */ +/* */ +/****************************************************************************/ + +/* Interrupt-Controller base address */ +IC_BASE: .word 0x40d00000 +#define ICMR 0x04 + +/* Reset-Controller */ +RST_BASE: .word 0x40f00030 +#define RCSR 0x00 + +/* Operating System Timer */ +OSTIMER_BASE: .word 0x40a00000 +#define OSMR3 0x0C +#define OSCR 0x10 +#define OWER 0x18 +#define OIER 0x1C + +/* Clock Manager Registers */ +CC_BASE: .word 0x41300000 +#define CCCR 0x00 +cpuspeed: .word CFG_CPUSPEED + + + /* RS: ??? */ + .macro CPWAIT + mrc p15,0,r0,c2,c0,0 + mov r0,r0 + sub pc,pc,#4 + .endm + + +cpu_init_crit: + + /* mask all IRQs */ + ldr r0, IC_BASE + mov r1, #0x00 + str r1, [r0, #ICMR] + +#if defined(CFG_CPUSPEED) + + /* set clock speed */ + ldr r0, CC_BASE + ldr r1, cpuspeed + str r1, [r0, #CCCR] + mov r0, #2 + mcr p14, 0, r0, c6, c0, 0 + +setspeed_done: +#endif + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a memsetup.S in your board directory. + */ + mov ip, lr + bl memsetup + mov lr, ip + + /* Memory interfaces are working. Disable MMU and enable I-cache. */ + + ldr r0, =0x2001 /* enable access to all coproc. */ + mcr p15, 0, r0, c15, c1, 0 + CPWAIT + + mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ + CPWAIT + + mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ + CPWAIT + + mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ + CPWAIT + + /* Enable the Icache */ +/* + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x1800 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT +*/ + mov pc, lr + + +/****************************************************************************/ +/* */ +/* Interrupt handling */ +/* */ +/****************************************************************************/ + +/* IRQ stack frame */ + +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 + + /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC + + ldr r2, _armboot_end + add r2, r2, #CONFIG_STACKSIZE + sub r2, r2, #8 + ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ + add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ + mov r0, sp + .endm + + + /* use irq_save_user_regs / irq_restore_user_regs for */ + /* IRQ/FIQ handling */ + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ /* Calling SP, LR */ + str lr, [r8, #0] /* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] /* Save CPSR */ + str r0, [r8, #8] /* Save OLD_R0 */ + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_end @ setup our mode stack + add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack + sub r13, r13, #8 + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + msr spsr_c, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + + +/****************************************************************************/ +/* */ +/* exception handlers */ +/* */ +/****************************************************************************/ + + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + irq_save_user_regs /* someone ought to write a more */ + bl do_fiq /* effiction fiq_save_user_regs */ + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + +/****************************************************************************/ +/* */ +/* Reset function: the PXA250 doesn't have a reset function, so we have to */ +/* perform a watchdog timeout for a soft reset. */ +/* */ +/****************************************************************************/ + + .align 5 +.globl reset_cpu + + /* FIXME: this code is PXA250 specific. How is this handled on */ + /* other XScale processors? */ + +reset_cpu: + + /* We set OWE:WME (watchdog enable) and wait until timeout happens */ + + ldr r0, OSTIMER_BASE + ldr r1, [r0, #OWER] + orr r1, r1, #0x0001 /* bit0: WME */ + str r1, [r0, #OWER] + + /* OS timer does only wrap every 1165 seconds, so we have to set */ + /* the match register as well. */ + + ldr r1, [r0, #OSCR] /* read OS timer */ + add r1, r1, #0x800 /* let OSMR3 match after */ + add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ + str r1, [r0, #OSMR3] + +reset_endless: + + b reset_endless + diff --git a/cpu/xscale/Makefile b/cpu/xscale/Makefile deleted file mode 100644 index 778a6646f8..0000000000 --- a/cpu/xscale/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = serial.o interrupts.o cpu.o i2c.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/xscale/config.mk b/cpu/xscale/config.mk deleted file mode 100644 index c40dcf8614..0000000000 --- a/cpu/xscale/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -mshort-load-bytes -msoft-float - -PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 diff --git a/cpu/xscale/cpu.c b/cpu/xscale/cpu.c deleted file mode 100644 index 6a3c24deda..0000000000 --- a/cpu/xscale/cpu.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include - -int cpu_init (void) -{ - /* - * setup up stack if necessary - */ -/* - - FIXME: the stack is _below_ the uboot code!! - -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_end + - CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4; - FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; - _armboot_real_end = FIQ_STACK_START + 4; -#else - _armboot_real_end = _armboot_end + CONFIG_STACKSIZE; -#endif -*/ - return (0); -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - extern void reset_cpu (ulong addr); - - printf ("reseting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void icache_disable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* clear i-cache */ - i &= ~0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} diff --git a/cpu/xscale/i2c.c b/cpu/xscale/i2c.c deleted file mode 100644 index 406f825cd5..0000000000 --- a/cpu/xscale/i2c.c +++ /dev/null @@ -1,460 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2003 Pengutronix e.K. - * Robert Schwebel - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Back ported to the 8xx platform (from the 8260 platform) by - * Murray.Jensen@cmst.csiro.au, 27-Jan-01. - */ - -/* FIXME: this file is PXA255 specific! What about other XScales? */ - -#include - -#ifdef CONFIG_HARD_I2C - -/* - * - CFG_I2C_SPEED - * - I2C_PXA_SLAVE_ADDR - */ - -#include -#include -#include - -//#define DEBUG_I2C 1 /* activate local debugging output */ -#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ -#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) -#define I2C_ISR_INIT 0x7FF - -#ifdef DEBUG_I2C -#define PRINTD(x) printf x -#else -#define PRINTD(x) -#endif - - -/* Shall the current transfer have a start/stop condition? */ -#define I2C_COND_NORMAL 0 -#define I2C_COND_START 1 -#define I2C_COND_STOP 2 - -/* Shall the current transfer be ack/nacked or being waited for it? */ -#define I2C_ACKNAK_WAITACK 1 -#define I2C_ACKNAK_SENDACK 2 -#define I2C_ACKNAK_SENDNAK 4 - -/* Specify who shall transfer the data (master or slave) */ -#define I2C_READ 0 -#define I2C_WRITE 1 - -/* All transfers are described by this data structure */ -struct i2c_msg { - u8 condition; - u8 acknack; - u8 direction; - u8 data; -}; - - -/** - * i2c_pxa_reset: - reset the host controller - * - */ - -static void i2c_reset( void ) -{ - ICR &= ~ICR_IUE; /* disable unit */ - ICR |= ICR_UR; /* reset the unit */ - udelay(100); - ICR &= ~ICR_IUE; /* disable unit */ - CKEN |= CKEN14_I2C; /* set the global I2C clock on */ - ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ - ICR = I2C_ICR_INIT; /* set control register values */ - ISR = I2C_ISR_INIT; /* set clear interrupt bits */ - ICR |= ICR_IUE; /* enable unit */ - udelay(100); -} - - -/** - * i2c_isr_set_cleared: - wait until certain bits of the I2C status register - * are set and cleared - * - * @return: 0 in case of success, 1 means timeout (no match within 10 ms). - */ - -static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) -{ - int timeout = 10000; - - while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){ - udelay( 10 ); - if( timeout-- < 0 ) return 0; - } - - return 1; -} - - -/** - * i2c_transfer: - Transfer one byte over the i2c bus - * - * This function can tranfer a byte over the i2c bus in both directions. - * It is used by the public API functions. - * - * @return: 0: transfer successful - * -1: message is empty - * -2: transmit timeout - * -3: ACK missing - * -4: receive timeout - * -5: illegal parameters - * -6: bus is busy and couldn't be aquired - */ -int i2c_transfer(struct i2c_msg *msg) -{ - int ret; - - if (!msg) - goto transfer_error_msg_empty; - - switch(msg->direction) { - - case I2C_WRITE: - - /* check if bus is not busy */ - if (!i2c_isr_set_cleared(0,ISR_IBB)) - goto transfer_error_bus_busy; - - /* start transmission */ - ICR &= ~ICR_START; - ICR &= ~ICR_STOP; - IDBR = msg->data; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; - if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; - if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; - ICR &= ~ICR_ALDIE; - ICR |= ICR_TB; - - /* transmit register empty? */ - if (!i2c_isr_set_cleared(ISR_ITE,0)) - goto transfer_error_transmit_timeout; - - /* clear 'transmit empty' state */ - ISR |= ISR_ITE; - - /* wait for ACK from slave */ - if (msg->acknack == I2C_ACKNAK_WAITACK) - if (!i2c_isr_set_cleared(0,ISR_ACKNAK)) - goto transfer_error_ack_missing; - break; - - case I2C_READ: - - /* check if bus is not busy */ - if (!i2c_isr_set_cleared(0,ISR_IBB)) - goto transfer_error_bus_busy; - - /* start receive */ - ICR &= ~ICR_START; - ICR &= ~ICR_STOP; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; - if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; - if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; - ICR &= ~ICR_ALDIE; - ICR |= ICR_TB; - - /* receive register full? */ - if (!i2c_isr_set_cleared(ISR_IRF,0)) - goto transfer_error_receive_timeout; - - msg->data = IDBR; - - /* clear 'receive empty' state */ - ISR |= ISR_IRF; - - break; - - default: - - goto transfer_error_illegal_param; - - } - - return 0; - -transfer_error_msg_empty: - PRINTD(("i2c_transfer: error: 'msg' is empty\n")); - ret = -1; goto i2c_transfer_finish; - -transfer_error_transmit_timeout: - PRINTD(("i2c_transfer: error: transmit timeout\n")); - ret = -2; goto i2c_transfer_finish; - -transfer_error_ack_missing: - PRINTD(("i2c_transfer: error: ACK missing\n")); - ret = -3; goto i2c_transfer_finish; - -transfer_error_receive_timeout: - PRINTD(("i2c_transfer: error: receive timeout\n")); - ret = -4; goto i2c_transfer_finish; - -transfer_error_illegal_param: - PRINTD(("i2c_transfer: error: illegal parameters\n")); - ret = -5; goto i2c_transfer_finish; - -transfer_error_bus_busy: - PRINTD(("i2c_transfer: error: bus is busy\n")); - ret = -6; goto i2c_transfer_finish; - -i2c_transfer_finish: - PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR)); - i2c_reset(); - return ret; - -} - -/* ------------------------------------------------------------------------ */ -/* API Functions */ -/* ------------------------------------------------------------------------ */ - -void i2c_init(int speed, int slaveaddr) -{ -#ifdef CFG_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#endif -} - - -/** - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ - -int i2c_probe(uchar chip) -{ - struct i2c_msg msg; - - i2c_reset(); - - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1) + 1; - if (i2c_transfer(&msg)) return -1; - - msg.condition = I2C_COND_STOP; - msg.acknack = I2C_ACKNAK_SENDNAK; - msg.direction = I2C_READ; - msg.data = 0x00; - if (i2c_transfer(&msg)) return -1; - - return 0; -} - - -/** - * i2c_read: - Read multiple bytes from an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be read - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to write the data - * @len: how much byte do we want to read - * @return: 0 in case of success - */ - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - int ret; - - PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); - - i2c_reset(); - - /* dummy chip address write */ - PRINTD(("i2c_read: dummy chip address write\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data &= 0xFE; - if ((ret=i2c_transfer(&msg))) return -1; - - /* - * send memory address bytes; - * alen defines how much bytes we have to send. - */ - //addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); - addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); - - while (--alen >= 0) { - - PRINTD(("i2c_read: send memory word address byte %1d\n",alen)); - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = addr_bytes[alen]; - if ((ret=i2c_transfer(&msg))) return -1; - } - - - /* start read sequence */ - PRINTD(("i2c_read: start read sequence\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data |= 0x01; - if ((ret=i2c_transfer(&msg))) return -1; - - /* read bytes; send NACK at last byte */ - while (len--) { - - if (len==0) { - msg.condition = I2C_COND_STOP; - msg.acknack = I2C_ACKNAK_SENDNAK; - } else { - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_SENDACK; - } - - msg.direction = I2C_READ; - msg.data = 0x00; - if ((ret=i2c_transfer(&msg))) return -1; - - *(buffer++) = msg.data; - - PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); - - } - - i2c_reset(); - - return 0; -} - - -/** - * i2c_write: - Write multiple bytes to an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be written - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to find the data to be written - * @len: how much byte do we want to read - * @return: 0 in case of success - */ - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - - PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); - - i2c_reset(); - - /* chip address write */ - PRINTD(("i2c_write: chip address write\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data &= 0xFE; - if (i2c_transfer(&msg)) return -1; - - /* - * send memory address bytes; - * alen defines how much bytes we have to send. - */ - addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); - - while (--alen >= 0) { - - PRINTD(("i2c_write: send memory word address\n")); - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = addr_bytes[alen]; - if (i2c_transfer(&msg)) return -1; - } - - /* write bytes; send NACK at last byte */ - while (len--) { - - PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); - - if (len==0) - msg.condition = I2C_COND_STOP; - else - msg.condition = I2C_COND_NORMAL; - - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = *(buffer++); - - if (i2c_transfer(&msg)) return -1; - - } - - i2c_reset(); - - return 0; - -} - -uchar i2c_reg_read (uchar chip, uchar reg) -{ - PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); - return 0; -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val)); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/xscale/interrupts.c b/cpu/xscale/interrupts.c deleted file mode 100644 index af7d63414e..0000000000 --- a/cpu/xscale/interrupts.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -extern void reset_cpu (ulong addr); - -#ifdef CONFIG_USE_IRQ -/* enable IRQ/FIQ interrupts */ -void enable_interrupts (void) -{ -#error: interrupts not implemented yet -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ -#error: interrupts not implemented yet -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32" - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - - -int interrupt_init (void) -{ - /* nothing happens here - we don't setup any IRQs */ - return (0); -} - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked (); -} - -void set_timer (ulong t) -{ - /* nop */ -} - -void udelay (unsigned long usec) -{ - udelay_masked (usec); -} - - -void reset_timer_masked (void) -{ - OSCR = 0; -} - -ulong get_timer_masked (void) -{ - return OSCR; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 1000; - - reset_timer_masked (); - - while (tmo >= get_timer_masked ()) - /*NOP*/; -} diff --git a/cpu/xscale/serial.c b/cpu/xscale/serial.c deleted file mode 100644 index c9d5f70bc4..0000000000 --- a/cpu/xscale/serial.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned int quot = 0; - - if (gd->baudrate == 1200) - quot = 192; - else if (gd->baudrate == 9600) - quot = 96; - else if (gd->baudrate == 19200) - quot = 48; - else if (gd->baudrate == 38400) - quot = 24; - else if (gd->baudrate == 57600) - quot = 16; - else if (gd->baudrate == 115200) - quot = 8; - else - hang (); - -#ifdef CONFIG_FFUART - - CKEN |= CKEN6_FFUART; - - FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ - - /* set baud rate */ - FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - FFDLL = quot & 0xff; - FFDLH = quot >> 8; - FFLCR = LCR_WLS0 | LCR_WLS1; - - FFIER = IER_UUE; /* Enable FFUART */ - -#elif defined(CONFIG_BTUART) - CKEN |= CKEN7_BTUART; - - BTIER = 0; - BTFCR = 0; - - /* set baud rate */ - BTLCR = LCR_DLAB; - BTDLL = quot & 0xff; - BTDLH = quot >> 8; - BTLCR = LCR_WLS0 | LCR_WLS1; - - BTIER = IER_UUE; /* Enable BFUART */ - -#elif defined(CONFIG_STUART) -#error "Bad: not implemented yet!" -#else -#error "Bad: you didn't configured serial ..." -#endif -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ -#ifdef CONFIG_FFUART - /* wait for room in the tx FIFO on FFUART */ - while ((FFLSR & LSR_TEMT) == 0); - - FFTHR = c; -#elif defined(CONFIG_BTUART) - while ((BTLSR & LSR_TEMT ) == 0 ); - BTTHR = c; -#elif defined(CONFIG_STUART) -#endif - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ -#ifdef CONFIG_FFUART - return FFLSR & LSR_DR; -#elif defined(CONFIG_BTUART) - return BTLSR & LSR_DR; -#elif defined(CONFIG_STUART) -#endif -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ -#ifdef CONFIG_FFUART - while (!(FFLSR & LSR_DR)); - - return (char) FFRBR & 0xff; -#elif defined(CONFIG_BTUART) - while (!(BTLSR & LSR_DR)); - - return (char) BTRBR & 0xff; -#elif defined(CONFIG_STUART) -#endif -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/xscale/start.S b/cpu/xscale/start.S deleted file mode 100644 index 95b30e44e9..0000000000 --- a/cpu/xscale/start.S +++ /dev/null @@ -1,474 +0,0 @@ -/* - * armboot - Startup Code for XScale - * - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 Wolfgang Denk - * Copyright (C) 2001 Alex Züpke - * Copyright (C) 2002 Kyle Harris - * Copyright (C) 2003 Robert Schwebel - * Copyright (C) 2003 Kai-Uwe Bloehm - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * - relocate armboot to ram - * - setup stack - * - jump to second stage - */ - -/* - * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h) - */ -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * Note: _armboot_end_data and _armboot_end are defined - * by the (board-dependent) linker script. - * _armboot_end_data is the first usable FLASH address after armboot - */ -.globl _armboot_end_data -_armboot_end_data: - .word armboot_end_data -.globl _armboot_end -_armboot_end: - .word armboot_end - -/* - * This is defined in the board specific linker script - */ -.globl _bss_start -_bss_start: - .word bss_start - -.globl _bss_end -_bss_end: - .word bss_end - -/* - * _armboot_real_end is the first usable RAM address behind armboot - * and the various stacks - */ -.globl _armboot_real_end -_armboot_real_end: - .word 0x0badc0de - -/* - * We relocate uboot to this address (end of RAM - 128 KiB) - */ -.globl _uboot_reloc -_uboot_reloc: - .word TEXT_BASE - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/****************************************************************************/ -/* */ -/* the actual reset code */ -/* */ -/****************************************************************************/ - -reset: - mrs r0,cpsr /* set the cpu to SVC32 mode */ - bic r0,r0,#0x1f /* (superviser mode, M=10011) */ - orr r0,r0,#0x13 - msr cpsr,r0 - - bl cpu_init_crit /* we do sys-critical inits */ - -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _armboot_end - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop - - /* Set up the stack */ - -stack_setup: - - ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - /* FIXME: bdinfo should be here */ - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - - ldr r0, _bss_start /* find start of bss segment */ - add r0, r0, #4 /* start at first byte of bss */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - bne clbss_l - - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/****************************************************************************/ -/* */ -/* CPU_init_critical registers */ -/* */ -/* - setup important registers */ -/* - setup memory timing */ -/* */ -/****************************************************************************/ - -/* Interrupt-Controller base address */ -IC_BASE: .word 0x40d00000 -#define ICMR 0x04 - -/* Reset-Controller */ -RST_BASE: .word 0x40f00030 -#define RCSR 0x00 - -/* Operating System Timer */ -OSTIMER_BASE: .word 0x40a00000 -#define OSMR3 0x0C -#define OSCR 0x10 -#define OWER 0x18 -#define OIER 0x1C - -/* Clock Manager Registers */ -CC_BASE: .word 0x41300000 -#define CCCR 0x00 -cpuspeed: .word CFG_CPUSPEED - - - /* RS: ??? */ - .macro CPWAIT - mrc p15,0,r0,c2,c0,0 - mov r0,r0 - sub pc,pc,#4 - .endm - - -cpu_init_crit: - - /* mask all IRQs */ - ldr r0, IC_BASE - mov r1, #0x00 - str r1, [r0, #ICMR] - -#if defined(CFG_CPUSPEED) - - /* set clock speed */ - ldr r0, CC_BASE - ldr r1, cpuspeed - str r1, [r0, #CCCR] - mov r0, #2 - mcr p14, 0, r0, c6, c0, 0 - -setspeed_done: -#endif - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a memsetup.S in your board directory. - */ - mov ip, lr - bl memsetup - mov lr, ip - - /* Memory interfaces are working. Disable MMU and enable I-cache. */ - - ldr r0, =0x2001 /* enable access to all coproc. */ - mcr p15, 0, r0, c15, c1, 0 - CPWAIT - - mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ - CPWAIT - - mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ - CPWAIT - - mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ - CPWAIT - - /* Enable the Icache */ -/* - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0x1800 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT -*/ - mov pc, lr - - -/****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ -/****************************************************************************/ - -/* IRQ stack frame */ - -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 - - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - - ldr r2, _armboot_end - add r2, r2, #CONFIG_STACKSIZE - sub r2, r2, #8 - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ - mov r0, sp - .endm - - - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_end @ setup our mode stack - add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack - sub r13, r13, #8 - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - - -/****************************************************************************/ -/* */ -/* exception handlers */ -/* */ -/****************************************************************************/ - - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -/****************************************************************************/ -/* */ -/* Reset function: the PXA250 doesn't have a reset function, so we have to */ -/* perform a watchdog timeout for a soft reset. */ -/* */ -/****************************************************************************/ - - .align 5 -.globl reset_cpu - - /* FIXME: this code is PXA250 specific. How is this handled on */ - /* other XScale processors? */ - -reset_cpu: - - /* We set OWE:WME (watchdog enable) and wait until timeout happens */ - - ldr r0, OSTIMER_BASE - ldr r1, [r0, #OWER] - orr r1, r1, #0x0001 /* bit0: WME */ - str r1, [r0, #OWER] - - /* OS timer does only wrap every 1165 seconds, so we have to set */ - /* the match register as well. */ - - ldr r1, [r0, #OSCR] /* read OS timer */ - add r1, r1, #0x800 /* let OSMR3 match after */ - add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ - str r1, [r0, #OSMR3] - -reset_endless: - - b reset_endless - diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h new file mode 100644 index 0000000000..f1f0e3387d --- /dev/null +++ b/include/asm-arm/arch-pxa/bitfield.h @@ -0,0 +1,113 @@ +/* + * FILE bitfield.h + * + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) + * Language C or ARM Assembly + * Purpose Definition of macros to operate on bit fields. + */ + + + +#ifndef __BITFIELD_H +#define __BITFIELD_H + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long) (Data)) +#else +#define UData(Data) (Data) +#endif + + +/* + * MACRO: Fld + * + * Purpose + * The macro "Fld" encodes a bit field, given its size and its shift value + * with respect to bit 0. + * + * Note + * A more intuitive way to encode bit fields would have been to use their + * mask. However, extracting size and shift value information from a bit + * field's mask is cumbersome and might break the assembler (255-character + * line-size limit). + * + * Input + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. + * + * Output + * Fld Encoded bit field. + */ + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + + +/* + * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit + * + * Purpose + * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return + * the size, shift value, mask, aligned mask, and first bit of a + * bit field. + * + * Input + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. + */ + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) +#define F1stBit(Field) (UData (1) << FShft (Field)) + + +/* + * MACRO: FInsrt + * + * Purpose + * The macro "FInsrt" inserts a value into a bit field by shifting the + * former appropriately. + * + * Input + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FInsrt Bit-field value positioned appropriately. + */ + +#define FInsrt(Value, Field) \ + (UData (Value) << FShft (Field)) + + +/* + * MACRO: FExtr + * + * Purpose + * The macro "FExtr" extracts the value of a bit field by masking and + * shifting it appropriately. + * + * Input + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FExtr Bit-field value. + */ + +#define FExtr(Data, Field) \ + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + + +#endif /* __BITFIELD_H */ diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h new file mode 100644 index 0000000000..b84ea48df1 --- /dev/null +++ b/include/asm-arm/arch-pxa/hardware.h @@ -0,0 +1,153 @@ +/* + * linux/include/asm-arm/arch-pxa/hardware.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: This file was taken from linux-2.4.19-rmk4-pxa1 + * + * - 2003/01/20 implementation specifics activated + * Robert Schwebel + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include +#include + + +/* + * These are statically mapped PCMCIA IO space for designs using it as a + * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. + * The actual PCMCIA code is mapping required IO region at run time. + */ +#define PCMCIA_IO_0_BASE 0xf6000000 +#define PCMCIA_IO_1_BASE 0xf7000000 + + +/* + * We requires absolute addresses. + */ +#define PCIO_BASE 0 + +/* + * Workarounds for at least 2 errata so far require this. + * The mapping is set in mach-pxa/generic.c. + */ +#define UNCACHED_PHYS_0 0xff000000 +#define UNCACHED_ADDR UNCACHED_PHYS_0 + +/* + * Intel PXA internal I/O mappings: + * + * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff + * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff + * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff + */ + +/* FIXME: Only this does work for u-boot... find out why... [RS] */ +#define UBOOT_REG_FIX 1 + +#ifndef UBOOT_REG_FIX +#ifndef __ASSEMBLY__ + +#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) +#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) + +/* + * This __REG() version gives the same results as the one above, except + * that we are fooling gcc somehow so it generates far better and smaller + * assembly code for access to contigous registers. It's a shame that gcc + * doesn't guess this by itself. + */ +#include +typedef struct { volatile u32 offset[4096]; } __regbase; +# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] +# define __REG(x) __REGP(io_p2v(x)) +#endif + +/* Let's kick gcc's ass again... */ +# define __REG2(x,y) \ + ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ + : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) + +# define __PREG(x) (io_v2p((u32)&(x))) + +#else + +# define __REG(x) io_p2v(x) +# define __PREG(x) io_v2p(x) + +#endif +#endif /* UBOOT_REG_FIX */ + +#ifdef UBOOT_REG_FIX +# undef io_p2v +# undef __REG +# ifndef __ASSEMBLY__ +# define io_p2v(PhAdd) (PhAdd) +# define __REG(x) (*((volatile u32 *)io_p2v(x))) +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +# else +# define __REG(x) (x) +#endif /* UBOOT_REG_FIX */ + +#include "pxa-regs.h" + +#ifndef __ASSEMBLY__ + +/* + * GPIO edge detection for IRQs: + * IRQs are generated on Falling-Edge, Rising-Edge, or both. + * This must be called *before* the corresponding IRQ is registered. + * Use this instead of directly setting GRER/GFER. + */ +#define GPIO_FALLING_EDGE 1 +#define GPIO_RISING_EDGE 2 +#define GPIO_BOTH_EDGES 3 +extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask ); + +/* + * Handy routine to set GPIO alternate functions + */ +extern void set_GPIO_mode( int gpio_mode ); + +/* + * return current lclk frequency in units of 10kHz + */ +extern unsigned int get_lclk_frequency_10khz(void); + +#endif + + +/* + * Implementation specifics + */ + +#ifdef CONFIG_ARCH_LUBBOCK +#include "lubbock.h" +#endif + +#ifdef CONFIG_ARCH_PXA_IDP +#include "idp.h" +#endif + +#ifdef CONFIG_ARCH_PXA_CERF +#include "cerf.h" +#endif + +#ifdef CONFIG_ARCH_CSB226 +#include "csb226.h" +#endif + +#ifdef CONFIG_ARCH_INNOKOM +#include "innokom.h" +#endif + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index dda246530e..208c110104 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -8,10 +8,16 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. + * + * - 2003/01/20: Robert Schwebel > 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/include/asm-arm/arch-xscale/hardware.h b/include/asm-arm/arch-xscale/hardware.h deleted file mode 100644 index b84ea48df1..0000000000 --- a/include/asm-arm/arch-xscale/hardware.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/hardware.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: This file was taken from linux-2.4.19-rmk4-pxa1 - * - * - 2003/01/20 implementation specifics activated - * Robert Schwebel - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include -#include - - -/* - * These are statically mapped PCMCIA IO space for designs using it as a - * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. - * The actual PCMCIA code is mapping required IO region at run time. - */ -#define PCMCIA_IO_0_BASE 0xf6000000 -#define PCMCIA_IO_1_BASE 0xf7000000 - - -/* - * We requires absolute addresses. - */ -#define PCIO_BASE 0 - -/* - * Workarounds for at least 2 errata so far require this. - * The mapping is set in mach-pxa/generic.c. - */ -#define UNCACHED_PHYS_0 0xff000000 -#define UNCACHED_ADDR UNCACHED_PHYS_0 - -/* - * Intel PXA internal I/O mappings: - * - * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff - * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff - * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff - */ - -/* FIXME: Only this does work for u-boot... find out why... [RS] */ -#define UBOOT_REG_FIX 1 - -#ifndef UBOOT_REG_FIX -#ifndef __ASSEMBLY__ - -#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) -#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) - -/* - * This __REG() version gives the same results as the one above, except - * that we are fooling gcc somehow so it generates far better and smaller - * assembly code for access to contigous registers. It's a shame that gcc - * doesn't guess this by itself. - */ -#include -typedef struct { volatile u32 offset[4096]; } __regbase; -# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] -# define __REG(x) __REGP(io_p2v(x)) -#endif - -/* Let's kick gcc's ass again... */ -# define __REG2(x,y) \ - ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ - : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) - -# define __PREG(x) (io_v2p((u32)&(x))) - -#else - -# define __REG(x) io_p2v(x) -# define __PREG(x) io_v2p(x) - -#endif -#endif /* UBOOT_REG_FIX */ - -#ifdef UBOOT_REG_FIX -# undef io_p2v -# undef __REG -# ifndef __ASSEMBLY__ -# define io_p2v(PhAdd) (PhAdd) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -#endif /* UBOOT_REG_FIX */ - -#include "pxa-regs.h" - -#ifndef __ASSEMBLY__ - -/* - * GPIO edge detection for IRQs: - * IRQs are generated on Falling-Edge, Rising-Edge, or both. - * This must be called *before* the corresponding IRQ is registered. - * Use this instead of directly setting GRER/GFER. - */ -#define GPIO_FALLING_EDGE 1 -#define GPIO_RISING_EDGE 2 -#define GPIO_BOTH_EDGES 3 -extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask ); - -/* - * Handy routine to set GPIO alternate functions - */ -extern void set_GPIO_mode( int gpio_mode ); - -/* - * return current lclk frequency in units of 10kHz - */ -extern unsigned int get_lclk_frequency_10khz(void); - -#endif - - -/* - * Implementation specifics - */ - -#ifdef CONFIG_ARCH_LUBBOCK -#include "lubbock.h" -#endif - -#ifdef CONFIG_ARCH_PXA_IDP -#include "idp.h" -#endif - -#ifdef CONFIG_ARCH_PXA_CERF -#include "cerf.h" -#endif - -#ifdef CONFIG_ARCH_CSB226 -#include "csb226.h" -#endif - -#ifdef CONFIG_ARCH_INNOKOM -#include "innokom.h" -#endif - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-xscale/pxa-regs.h b/include/asm-arm/arch-xscale/pxa-regs.h deleted file mode 100644 index 449ec9fd95..0000000000 --- a/include/asm-arm/arch-xscale/pxa-regs.h +++ /dev/null @@ -1,1374 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/pxa-regs.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - 2003/01/20: Robert Schwebel */ -#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ -#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ - -#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ -#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ -#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ - -#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ -#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ -#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ - -#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ -#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ - -#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ -#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ -#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ - -#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ -#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ - -#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ -#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ -#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ - -#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ -#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ -#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ -#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ -#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ -#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */ - -/* More handy macros. The argument is a literal GPIO number. */ - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) -#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -/* GPIO alternate function assignments */ - -#define GPIO1_RST 1 /* reset */ -#define GPIO6_MMCCLK 6 /* MMC Clock */ -#define GPIO8_48MHz 7 /* 48 MHz clock output */ -#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ -#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ -#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ -#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ -#define GPIO12_32KHz 12 /* 32 kHz out */ -#define GPIO13_MBGNT 13 /* memory controller grant */ -#define GPIO14_MBREQ 14 /* alternate bus master request */ -#define GPIO15_nCS_1 15 /* chip select 1 */ -#define GPIO16_PWM0 16 /* PWM0 output */ -#define GPIO17_PWM1 17 /* PWM1 output */ -#define GPIO18_RDY 18 /* Ext. Bus Ready */ -#define GPIO19_DREQ1 19 /* External DMA Request */ -#define GPIO20_DREQ0 20 /* External DMA Request */ -#define GPIO23_SCLK 23 /* SSP clock */ -#define GPIO24_SFRM 24 /* SSP Frame */ -#define GPIO25_STXD 25 /* SSP transmit */ -#define GPIO26_SRXD 26 /* SSP receive */ -#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ -#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ -#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ -#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ -#define GPIO31_SYNC 31 /* AC97/I2S sync */ -#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ -#define GPIO33_nCS_5 33 /* chip select 5 */ -#define GPIO34_FFRXD 34 /* FFUART receive */ -#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ -#define GPIO35_FFCTS 35 /* FFUART Clear to send */ -#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ -#define GPIO37_FFDSR 37 /* FFUART data set ready */ -#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ -#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ -#define GPIO39_FFTXD 39 /* FFUART transmit data */ -#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ -#define GPIO41_FFRTS 41 /* FFUART request to send */ -#define GPIO42_BTRXD 42 /* BTUART receive data */ -#define GPIO43_BTTXD 43 /* BTUART transmit data */ -#define GPIO44_BTCTS 44 /* BTUART clear to send */ -#define GPIO45_BTRTS 45 /* BTUART request to send */ -#define GPIO46_ICPRXD 46 /* ICP receive data */ -#define GPIO46_STRXD 46 /* STD_UART receive data */ -#define GPIO47_ICPTXD 47 /* ICP transmit data */ -#define GPIO47_STTXD 47 /* STD_UART transmit data */ -#define GPIO48_nPOE 48 /* Output Enable for Card Space */ -#define GPIO49_nPWE 49 /* Write Enable for Card Space */ -#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ -#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ -#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ -#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ -#define GPIO53_MMCCLK 53 /* MMC Clock */ -#define GPIO54_MMCCLK 54 /* MMC Clock */ -#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ -#define GPIO55_nPREG 55 /* Card Address bit 26 */ -#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ -#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ -#define GPIO58_LDD_0 58 /* LCD data pin 0 */ -#define GPIO59_LDD_1 59 /* LCD data pin 1 */ -#define GPIO60_LDD_2 60 /* LCD data pin 2 */ -#define GPIO61_LDD_3 61 /* LCD data pin 3 */ -#define GPIO62_LDD_4 62 /* LCD data pin 4 */ -#define GPIO63_LDD_5 63 /* LCD data pin 5 */ -#define GPIO64_LDD_6 64 /* LCD data pin 6 */ -#define GPIO65_LDD_7 65 /* LCD data pin 7 */ -#define GPIO66_LDD_8 66 /* LCD data pin 8 */ -#define GPIO66_MBREQ 66 /* alternate bus master req */ -#define GPIO67_LDD_9 67 /* LCD data pin 9 */ -#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ -#define GPIO68_LDD_10 68 /* LCD data pin 10 */ -#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ -#define GPIO69_LDD_11 69 /* LCD data pin 11 */ -#define GPIO69_MMCCLK 69 /* MMC_CLK */ -#define GPIO70_LDD_12 70 /* LCD data pin 12 */ -#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ -#define GPIO71_LDD_13 71 /* LCD data pin 13 */ -#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ -#define GPIO72_LDD_14 72 /* LCD data pin 14 */ -#define GPIO72_32kHz 72 /* 32 kHz clock */ -#define GPIO73_LDD_15 73 /* LCD data pin 15 */ -#define GPIO73_MBGNT 73 /* Memory controller grant */ -#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ -#define GPIO75_LCD_LCLK 75 /* LCD line clock */ -#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ -#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ -#define GPIO78_nCS_2 78 /* chip select 2 */ -#define GPIO79_nCS_3 79 /* chip select 3 */ -#define GPIO80_nCS_4 80 /* chip select 4 */ - -/* GPIO alternate function mode & direction */ - -#define GPIO_IN 0x000 -#define GPIO_OUT 0x080 -#define GPIO_ALT_FN_1_IN 0x100 -#define GPIO_ALT_FN_1_OUT 0x180 -#define GPIO_ALT_FN_2_IN 0x200 -#define GPIO_ALT_FN_2_OUT 0x280 -#define GPIO_ALT_FN_3_IN 0x300 -#define GPIO_ALT_FN_3_OUT 0x380 -#define GPIO_MD_MASK_NR 0x07f -#define GPIO_MD_MASK_DIR 0x080 -#define GPIO_MD_MASK_FN 0x300 - -#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) -#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) -#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) -#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) -#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) -#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) -#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) -#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) -#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) -#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) -#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) -#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) -#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) -#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) -#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) -#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) -#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) -#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) -#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) -#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) -#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) -#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) -#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) -#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) -#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) -#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) -#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) -#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) -#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) -#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) -#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) -#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) -#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) -#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) -#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) -#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) -#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) -#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) -#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) -#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) -#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) -#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) -#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) -#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) -#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) -#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) -#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) -#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) -#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) -#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) -#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) -#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) -#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) -#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) -#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) -#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) -#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) -#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) -#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) -#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) -#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) -#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) -#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) -#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) -#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) -#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) -#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) -#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) -#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) -#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) -#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) -#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) -#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) -#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) -#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) -#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) -#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) -#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) -#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) -#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) -#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) -#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) - - -/* - * Power Manager - */ - -#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ -#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ -#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ -#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ -#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ -#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ - -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ - -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ - -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ - - -/* - * SSP Serial Port Registers - */ - -#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */ -#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */ -#define SSSR __REG(0x41000008) /* SSP Status Register */ -#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */ -#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ - - -/* - * MultiMediaCard (MMC) controller - */ - -#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ -#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ -#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ -#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ -#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ -#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ -#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ -#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ -#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ -#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ -#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ -#define MMC_CMD __REG(0x41100030) /* Index of current command */ -#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ -#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ -#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ -#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ -#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ - - -/* - * Core Clock - */ - -#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ -#define CKEN __REG(0x41300004) /* Clock Enable Register */ -#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ - -#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - -#define CCCR_L09 (0x1F) -#define CCCR_L27 (0x1) -#define CCCR_L32 (0x2) -#define CCCR_L36 (0x3) -#define CCCR_L40 (0x4) -#define CCCR_L45 (0x5) - -#define CCCR_M1 (0x1 << 5) -#define CCCR_M2 (0x2 << 5) -#define CCCR_M4 (0x3 << 5) - -#define CCCR_N10 (0x2 << 7) -#define CCCR_N15 (0x3 << 7) -#define CCCR_N20 (0x4 << 7) -#define CCCR_N25 (0x5 << 7) -#define CCCR_N30 (0x6 << 7) - -/* - * LCD - */ - -#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */ -#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ -#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ -#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ -#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ -#define LCSR __REG(0x44000038) /* LCD Controller Status Register */ -#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ -#define TMEDCR __REG(0x44000044) /* TMED Control Register */ - -#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */ -#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */ - -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ -#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ -#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ -#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ -#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ -#define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ - -#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ - (((Pixel) - 1) << FShft (LCCR1_PPL)) - -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [1..64 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_HSW)) - -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) - -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) - -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) - -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) - -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#if 0 -#define LCCR3_PCD (0xff) /* Pixel clock divisor */ -#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ -#define LCCR3_ACB_S 8 -#endif - -#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ -#define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ -#define LCCR3_OEP (1 << 23) /* output enable polarity */ -#if 0 -#define LCCR3_BPP (7 << 24) /* bits per pixel */ -#define LCCR3_BPP_S 24 -#endif -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ - - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ - (((Div) << FShft (LCCR3_PCD))) - - -#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ -#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ - (((Bpp) << FShft (LCCR3_BPP))) - -#define LCCR3_ACB Fld (8, 8) /* AC Bias */ -#define LCCR3_Acb(Acb) /* BAC Bias */ \ - (((Acb) << FShft (LCCR3_ACB))) - -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ - -#define LCSR_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR_SOF (1 << 1) /* Start of frame */ -#define LCSR_BER (1 << 2) /* Bus error */ -#define LCSR_ABC (1 << 3) /* AC Bias count */ -#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR_OU (1 << 6) /* output FIFO underrun */ -#define LCSR_QD (1 << 7) /* quick disable */ -#define LCSR_EOF (1 << 8) /* end of frame */ -#define LCSR_BS (1 << 9) /* branch status */ -#define LCSR_SINT (1 << 10) /* subsequent interrupt */ - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ - -#define LCSR_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR_SOF (1 << 1) /* Start of frame */ -#define LCSR_BER (1 << 2) /* Bus error */ -#define LCSR_ABC (1 << 3) /* AC Bias count */ -#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR_OU (1 << 6) /* output FIFO underrun */ -#define LCSR_QD (1 << 7) /* quick disable */ -#define LCSR_EOF (1 << 8) /* end of frame */ -#define LCSR_BS (1 << 9) /* branch status */ -#define LCSR_SINT (1 << 10) /* subsequent interrupt */ - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ - -/* - * Memory controller - */ - -#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */ -#define MDCNFG_OFFSET 0x0 -#define MDREFR_OFFSET 0x4 -#define MSC0_OFFSET 0x8 -#define MSC1_OFFSET 0xC -#define MSC2_OFFSET 0x10 -#define MECR_OFFSET 0x14 -#define SXLCR_OFFSET 0x18 -#define SXCNFG_OFFSET 0x1C -#define FLYCNFG_OFFSET 0x20 -#define SXMRS_OFFSET 0x24 -#define MCMEM0_OFFSET 0x28 -#define MCMEM1_OFFSET 0x2C -#define MCATT0_OFFSET 0x30 -#define MCATT1_OFFSET 0x34 -#define MCIO0_OFFSET 0x38 -#define MCIO1_OFFSET 0x3C -#define MDMRS_OFFSET 0x40 - -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ -#define MDCNFG_DE0 0x00000001 -#define MDCNFG_DE1 0x00000002 -#define MDCNFG_DE2 0x00010000 -#define MDCNFG_DE3 0x00020000 -#define MDCNFG_DWID0 0x00000004 - -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - - -#endif