From: Alamy Liu Date: Thu, 6 Aug 2015 21:05:24 +0000 (-0700) Subject: adi_v5: Rename AP_REG_* to MEM_AP_REG_* and add LA support X-Git-Tag: v0.10.0-rc1~323 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=4dc012865f3856c38c6399df0f85abd59642308a;p=openocd adi_v5: Rename AP_REG_* to MEM_AP_REG_* and add LA support This is a TODO in the src/target/arm_adi_v5.h for MEM-AP registers. Some new registers are introduced in ADIv5.2 specification. MEM_AP_REG_MGT (0x20) // Memory Barrier Transfer register MEM_AP_REG_TAR64 (0x08) // Bits[63:32] of Transfer Address MEM_AP_REG_BASE64 (0xF0) // Bits[63:32] of Debug Base Address Refer to 7.5 MEM-AP register summary in IHI0031C: ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 Change-Id: I3bc4296a04c35f5c64f851e5865d3099922613fa Signed-off-by: Alamy Liu Reviewed-on: http://openocd.zylin.com/2904 Tested-by: jenkins Reviewed-by: Matthias Welwarsky Reviewed-by: Andreas Fritiofson --- diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c index c1e12866..c4ed98a7 100644 --- a/src/target/adi_v5_jtag.c +++ b/src/target/adi_v5_jtag.c @@ -115,8 +115,8 @@ static int adi_jtag_dp_scan(struct adiv5_dap *dap, * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec. */ if ((instr == JTAG_DP_APACC) - && ((reg_addr == AP_REG_DRW) - || ((reg_addr & 0xF0) == AP_REG_BD0)) + && ((reg_addr == MEM_AP_REG_DRW) + || ((reg_addr & 0xF0) == MEM_AP_REG_BD0)) && (dap->memaccess_tck != 0)) jtag_add_runtest(dap->memaccess_tck, TAP_IDLE); @@ -314,12 +314,12 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat); retval = dap_queue_ap_read(dap, - AP_REG_CSW, &mem_ap_csw); + MEM_AP_REG_CSW, &mem_ap_csw); if (retval != ERROR_OK) return retval; retval = dap_queue_ap_read(dap, - AP_REG_TAR, &mem_ap_tar); + MEM_AP_REG_TAR, &mem_ap_tar); if (retval != ERROR_OK) return retval; diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index c2929ef7..fd91281b 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -125,7 +125,7 @@ static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw) if (csw != dap->ap_csw_value) { /* LOG_DEBUG("DAP: Set CSW %x",csw); */ - int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw); + int retval = dap_queue_ap_write(dap, MEM_AP_REG_CSW, csw); if (retval != ERROR_OK) return retval; dap->ap_csw_value = csw; @@ -137,7 +137,7 @@ static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar) { if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) { /* LOG_DEBUG("DAP: Set TAR %x",tar); */ - int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar); + int retval = dap_queue_ap_write(dap, MEM_AP_REG_TAR, tar); if (retval != ERROR_OK) return retval; dap->ap_tar_value = tar; @@ -149,7 +149,7 @@ static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar) * Queue transactions setting up transfer parameters for the * currently selected MEM-AP. * - * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2 + * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2 * initiate data reads or writes using memory or peripheral addresses. * If the CSW is configured for it, the TAR may be automatically * incremented after each transfer. @@ -200,7 +200,7 @@ int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address, if (retval != ERROR_OK) return retval; - return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value); + return dap_queue_ap_read(dap, MEM_AP_REG_BD0 | (address & 0xC), value); } /** @@ -251,7 +251,7 @@ int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address, if (retval != ERROR_OK) return retval; - return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC), + return dap_queue_ap_write(dap, MEM_AP_REG_BD0 | (address & 0xC), value); } @@ -379,7 +379,7 @@ int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, ui nbytes -= this_size; - retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue); + retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue); if (retval != ERROR_OK) break; @@ -397,7 +397,7 @@ int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, ui if (retval != ERROR_OK) { uint32_t tar; - if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK + if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK && dap_run(dap) == ERROR_OK) LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar); else @@ -480,7 +480,7 @@ int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t if (retval != ERROR_OK) break; - retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++); + retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++); if (retval != ERROR_OK) break; @@ -507,7 +507,7 @@ int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t * at least give the caller what we have. */ if (retval != ERROR_OK) { uint32_t tar; - if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK + if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK && dap_run(dap) == ERROR_OK) { LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar); if (nbytes > tar - address) @@ -718,11 +718,11 @@ int ahbap_debugport_init(struct adiv5_dap *dap) if (retval != ERROR_OK) continue; - retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw); + retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw); if (retval != ERROR_OK) continue; - retval = dap_queue_ap_read(dap, AP_REG_CFG, &cfg); + retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg); if (retval != ERROR_OK) continue; @@ -847,7 +847,7 @@ int dap_get_debugbase(struct adiv5_dap *dap, int ap, ap_old = dap_ap_get_select(dap); dap_ap_select(dap, ap); - retval = dap_queue_ap_read(dap, AP_REG_BASE, dbgbase); + retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase); if (retval != ERROR_OK) return retval; retval = dap_queue_ap_read(dap, AP_REG_IDR, apid); @@ -1499,7 +1499,7 @@ COMMAND_HANDLER(dap_baseaddr_command) * though they're not common for now. This should * use the ID register to verify it's a MEM-AP. */ - retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr); + retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr); if (retval != ERROR_OK) return retval; retval = dap_run(dap); diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 7f61ff04..7140c8dc 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -90,19 +90,20 @@ #define CSYSPWRUPACK (1UL << 31) /* MEM-AP register addresses */ -/* TODO: rename as MEM_AP_REG_* */ -#define AP_REG_CSW 0x00 -#define AP_REG_TAR 0x04 -#define AP_REG_DRW 0x0C -#define AP_REG_BD0 0x10 -#define AP_REG_BD1 0x14 -#define AP_REG_BD2 0x18 -#define AP_REG_BD3 0x1C -#define AP_REG_CFG 0xF4 /* big endian? */ -#define AP_REG_BASE 0xF8 - +#define MEM_AP_REG_CSW 0x00 +#define MEM_AP_REG_TAR 0x04 +#define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */ +#define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */ +#define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */ +#define MEM_AP_REG_BD1 0x14 +#define MEM_AP_REG_BD2 0x18 +#define MEM_AP_REG_BD3 0x1C +#define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */ +#define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */ +#define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */ +#define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */ /* Generic AP register address */ -#define AP_REG_IDR 0xFC +#define AP_REG_IDR 0xFC /* RO: Identification Register */ /* Fields of the MEM-AP's CSW register */ #define CSW_8BIT 0