From: Philipp Tomsich Date: Fri, 1 Dec 2017 23:19:14 +0000 (+0100) Subject: rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK X-Git-Tag: v2018.01-rc1~25^2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=4fc495e9e2e497afee383294a6ee9212e9a8bd73;p=u-boot rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15. Fix this to remove an "integer-overflow on shifted constant" warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich --- diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h index 3d8317ed91..90012c7fce 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h @@ -187,7 +187,7 @@ enum { DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, DCLK_VOP_PLL_SEL_CPLL = 0, DCLK_VOP_DIV_CON_SHIFT = 8, - DCLK_VOP_DIV_CON_MASK = 0xfff << DCLK_VOP_DIV_CON_SHIFT, + DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, /* CRU_CLKSEL31_CON */ VIO0_PLL_SHIFT = 5,