From: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Sun, 3 Aug 2014 18:37:58 +0000 (+0000)
Subject: Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:
X-Git-Tag: V8.1.0~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5027d0ca9128b01a9e95507f8dfc7319459ed558;p=freertos

Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2284 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
index 965d304f5..81e16b4cd 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -139,10 +139,6 @@ uint32_t ulPortInterruptNesting = 0UL;
 
 /*-----------------------------------------------------------*/
 
-#warning What about branch distance in asm file.
-#warning Does not support flop use in ISRs.
-#warning Level interrupts must be cleared in their handling function.
-
 /*
  * See header file for description.
  */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
index fe6c74579..8aa8a12cd 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -99,9 +99,6 @@ portSAVE_CONTEXT macro
 
 portRESTORE_CONTEXT macro
 
-	; Switch to system mode
-	CPS		#SYS_MODE
-
 	; Set the SP to point to the stack of the task being restored.
 	LDR		R0, =pxCurrentTCB
 	LDR		R1, [R0]
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
index c66146964..1bfca7fc2 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
@@ -73,7 +73,7 @@ IRQ_MODE			EQU		0x12
 	INCLUDE portASM.h
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; SVC handler is used to start the scheduler and yield a task.
+; SVC handler is used to yield a task.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 FreeRTOS_SWI_Handler
 
@@ -83,11 +83,16 @@ FreeRTOS_SWI_Handler
 	portSAVE_CONTEXT
 	LDR R0, =vTaskSwitchContext
 	BLX	R0
+	portRESTORE_CONTEXT
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; vPortRestoreTaskContext is used to start the scheduler.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 vPortRestoreTaskContext
+	; Switch to system mode
+	CPS		#SYS_MODE
 	portRESTORE_CONTEXT
 
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ; IRQ interrupt handler used when individual priorities cannot be masked
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -121,11 +126,14 @@ FreeRTOS_IRQ_Handler
 	AND		r2, r2, #4
 	SUB		sp, sp, r2
 
-	; Call the interrupt handler
+	; Obtain the address of the interrupt handler, then call it.
 	PUSH	{r0-r3, lr}
 	LDR		r1, =configINTERRUPT_VECTOR_ADDRESS
 	LDR		r0, [r1]
-	STR		r1, [r1] ; Write to IVR in case protect mode is being used.
+	STR		r1, [r1] ; [SAMA5] Write to IVR in case protect mode is being used.
+	DSB
+	ISB
+	CPSIE	i
 	BLX		r0
 	POP		{r0-r3, lr}
 	ADD		sp, sp, r2
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
index ce6b83c09..8db2506ca 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
@@ -124,7 +124,7 @@
 	}
 
 	#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-	#define portYIELD() __asm( "SWI 0" );
+	#define portYIELD() __asm( "SWI 0" ); __ISB()
 
 
 	/*-----------------------------------------------------------
@@ -138,9 +138,9 @@
 
 	#define portENTER_CRITICAL()		vPortEnterCritical();
 	#define portEXIT_CRITICAL()			vPortExitCritical();
-	#define portDISABLE_INTERRUPTS()	__disable_irq() /* No priority mask register so global disable is used. */
+	#define portDISABLE_INTERRUPTS()	__disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */
 	#define portENABLE_INTERRUPTS()		__enable_irq()
-	#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_interrupt_state()
+	#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */
 	#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_interrupt_state(x)
 
 	/*-----------------------------------------------------------*/