From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Fri, 4 Sep 2009 05:20:45 +0000 (+0000)
Subject: Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR register
X-Git-Tag: v0.3.0-rc0~285
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=51be978b4329008ece5a501563ffcc4059baef8f;p=openocd

Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR register



git-svn-id: svn://svn.berlios.de/openocd/trunk@2666 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 829bf3dc..a806669d 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -166,7 +166,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
 		retvalue = mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
 	}
-	while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
 
@@ -175,7 +175,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
 		retvalue = mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
 	}
-	while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	return retvalue;
 }
@@ -291,7 +291,7 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
 		retval = mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
 	}
-	while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
 
 	retval = mem_ap_read_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
@@ -436,7 +436,7 @@ int cortex_a8_halt(target_t *target)
 	do {
 		mem_ap_read_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-	} while ((dscr & (1 << 0)) == 0);
+	} while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
 
 	target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -535,7 +535,7 @@ int cortex_a8_resume(struct target_s *target, int current,
 	do {
 		mem_ap_read_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-	} while ((dscr & (1 << 1)) == 0);
+	} while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
 	target->state = TARGET_RUNNING;
@@ -582,7 +582,7 @@ int cortex_a8_debug_entry(target_t *target)
 	/* Enable the ITR execution once we are in debug mode */
 	mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-	dscr |= (1 << 13);
+	dscr |= (1 << DSCR_EXT_INT_EN);
 	retval = mem_ap_write_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
 
diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h
index bb57b13e..a1efe667 100644
--- a/src/target/cortex_a8.h
+++ b/src/target/cortex_a8.h
@@ -67,6 +67,15 @@ extern char* cortex_a8_state_strings[];
 #define BRP_NORMAL 0
 #define BRP_CONTEXT 1
 
+/* DSCR Bit offset */
+#define DSCR_CORE_HALTED		0
+#define DSCR_CORE_RESTARTED 	1
+#define DSCR_EXT_INT_EN 		13
+#define DSCR_HALT_DBG_MODE		14
+#define DSCR_MON_DBG_MODE 		15
+#define DSCR_INSTR_COMP 		24
+#define DSCR_DTR_TX_FULL 		29
+
 typedef struct  cortex_a8_brp_s
 {
 	int used;