From: Axel Lin Date: Thu, 26 Feb 2015 02:45:22 +0000 (+0800) Subject: spi: designware_spi: revisit FIFO size detection again X-Git-Tag: v2015.04-rc5~4 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=52091ad146d766cdc5ccd65430b2a4e5cb7aec32;p=u-boot spi: designware_spi: revisit FIFO size detection again By specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth) Signed-off-by: Andy Shevchenko Signed-off-by: Axel Lin Acked-by: Pavel Machek Reviewed-by: Jagannadha Sutradharudu Teki --- diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 2624844d52..8f5c0fc802 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -164,13 +164,13 @@ static void spi_hw_init(struct dw_spi_priv *priv) if (!priv->fifo_len) { u32 fifo; - for (fifo = 2; fifo <= 256; fifo++) { + for (fifo = 1; fifo < 256; fifo++) { dw_writew(priv, DW_SPI_TXFLTR, fifo); if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) break; } - priv->fifo_len = (fifo == 2) ? 0 : fifo - 1; + priv->fifo_len = (fifo == 1) ? 0 : fifo; dw_writew(priv, DW_SPI_TXFLTR, 0); } debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);