From: Patrice Chotard <patrice.chotard@st.com>
Date: Tue, 18 Jul 2017 07:29:09 +0000 (+0200)
Subject: spi: stm32_qspi: add clk_get_rate() support
X-Git-Tag: v2017.09-rc1~104
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=541cd6e54eb80159d9212e2dda8fdea8c246eea7;p=u-boot

spi: stm32_qspi: add clk_get_rate() support

Replace proprietary clock_get() by clk_get_rate()
The stm32_qspi is now "generic" and can be used
by other STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
---

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index f0434a4413..ef2b64ec5f 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -165,6 +165,7 @@ struct stm32_qspi_platdata {
 
 struct stm32_qspi_priv {
 	struct stm32_qspi_regs *regs;
+	ulong clock_rate;
 	u32 max_hz;
 	u32 mode;
 
@@ -471,6 +472,13 @@ static int stm32_qspi_probe(struct udevice *bus)
 		dev_err(bus, "failed to enable clock\n");
 		return ret;
 	}
+
+	priv->clock_rate = clk_get_rate(&clk);
+	if (priv->clock_rate < 0) {
+		clk_disable(&clk);
+		return priv->clock_rate;
+	}
+
 #endif
 
 	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
@@ -536,7 +544,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 	if (speed > plat->max_hz)
 		speed = plat->max_hz;
 
-	u32 qspi_clk = clock_get(CLOCK_AHB);
+	u32 qspi_clk = priv->clock_rate;
 	u32 prescaler = 255;
 	if (speed > 0) {
 		prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;