From: Thierry Reding Date: Thu, 20 Aug 2015 09:52:13 +0000 (+0200) Subject: armv8/mmu: Clean up TCR programming X-Git-Tag: v2015.10~25^2~2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=55aa0bed9803b8a5bd3e462fd712741c2e1cff1b;p=u-boot armv8/mmu: Clean up TCR programming Use the inner shareable attribute for memory, which makes more sense considering that this code is called when caches are being enabled. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding --- diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0c928d40e7..a1c3c06539 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -103,9 +103,9 @@ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ -/* PTWs cacheable, inner/outer WBWA and non-shareable */ +/* PTWs cacheable, inner/outer WBWA and inner shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ + TCR_SHARED_INNER | \ TCR_ORGN_WBWA | \ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS))