From: York Sun <yorksun@freescale.com>
Date: Thu, 23 Jul 2015 21:04:48 +0000 (-0700)
Subject: drivers/ddr/fsl: Adjust bstopre value
X-Git-Tag: v2015.10-rc2~424^2~4
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=56848428a88f89420ae7acc04bb5805e70c430a3;p=u-boot

drivers/ddr/fsl: Adjust bstopre value

By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.

Signed-off-by: York Sun <yorksun@freescale.com>
---

diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 14ecf1219c..72ec1be65d 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -535,7 +535,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 			 * which is currently STEP_ASSIGN_ADDRESSES.
 			 */
 			populate_memctl_options(
-					timing_params[i].all_dimms_registered,
+					&timing_params[i],
 					&pinfo->memctl_opts[i],
 					pinfo->dimm_params[i], i);
 			/*
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 3b30fa284c..3c09c643fe 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -499,7 +499,7 @@ static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
 	return 0;
 }
 
-unsigned int populate_memctl_options(int all_dimms_registered,
+unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
 			memctl_options_t *popts,
 			dimm_params_t *pdimm,
 			unsigned int ctrl_num)
@@ -640,7 +640,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
 	popts->ba_intlv_ctl = 0;
 
 	/* Memory Organization Parameters */
-	popts->registered_dimm_en = all_dimms_registered;
+	popts->registered_dimm_en = common_dimm->all_dimms_registered;
 
 	/* Operational Mode Paramters */
 
@@ -778,9 +778,11 @@ unsigned int populate_memctl_options(int all_dimms_registered,
 	 * Set this to 0 for global auto precharge
 	 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
 	 * It is not wrong. Any value should be OK. The performance depends on
-	 * applications. There is no one good value for all.
+	 * applications. There is no one good value for all. One way to set
+	 * is to use 1/4 of refint value.
 	 */
-	popts->bstopre = 0x100;
+	popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
+			 >> 2;
 
 	/*
 	 * Window for four activates -- tFAW
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 728503b62c..1ac092bb92 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -103,7 +103,7 @@ unsigned int compute_lowest_common_dimm_parameters(
 				const dimm_params_t *dimm_params,
 				common_timing_params_t *outpdimm,
 				unsigned int number_of_dimms);
-unsigned int populate_memctl_options(int all_dimms_registered,
+unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
 				memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num);