From: Stefan Roese <sr@denx.de>
Date: Thu, 4 Dec 2014 12:04:06 +0000 (+0100)
Subject: arm: mx6: gw_ventana: Change clock init to enable NAND related clocks
X-Git-Tag: v2015.01~91^2~15
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=576cd6b3faf76f9a4248a80c7b9c737402c33be7;p=u-boot

arm: mx6: gw_ventana: Change clock init to enable NAND related clocks

Otherwise NAND booting is likely to fail. Since this disables the NAND related
clocks and SPL can't load the main U-Boot from NAND.

This problem was introduced with this patch:

e25fbe3f (gw_ventana: Move the DCD settings to spl code)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
---

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index d6a584745b..97128127fb 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -401,7 +401,7 @@ static void ccgr_init(void)
 	writel(0x0030FC03, &ccm->CCGR1);
 	writel(0x0FFFC000, &ccm->CCGR2);
 	writel(0x3FF00000, &ccm->CCGR3);
-	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0xFFFFF300, &ccm->CCGR4);	/* enable NAND/GPMI/BCH clks */
 	writel(0x0F0000C3, &ccm->CCGR5);
 	writel(0x000003FF, &ccm->CCGR6);
 }