From: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Date: Sat, 16 Jul 2011 12:30:20 +0000 (+0200)
Subject: rlink: fix reply counter to enable sending full buffers
X-Git-Tag: v0.6.0-rc1~627
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5812ef2b73db2f513f9c42d6cf4b695268d04d69;p=openocd

rlink: fix reply counter to enable sending full buffers

dtc_queue.reply_index was wrongly being increased during out scans, causing
the queue to be sent before the out buffer was full. This patch increases
raw upload speed by 50% or so.

Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
---

diff --git a/src/jtag/drivers/rlink.c b/src/jtag/drivers/rlink.c
index ae3431be..d0b18b1b 100644
--- a/src/jtag/drivers/rlink.c
+++ b/src/jtag/drivers/rlink.c
@@ -678,6 +678,10 @@ dtc_queue_run(void) {
 	uint8_t			dtc_mask, tdo_mask;
 	uint8_t			reply_buffer[USB_EP2IN_SIZE];
 
+	assert((dtc_queue.rq_head != 0) == (dtc_queue.reply_index > 0));
+	assert(dtc_queue.cmd_index < USB_EP2BANK_SIZE);
+	assert(dtc_queue.reply_index <= USB_EP2IN_SIZE);
+
 	retval = ERROR_OK;
 
 	if (dtc_queue.cmd_index < 1) return(retval);
@@ -807,8 +811,6 @@ dtc_queue_run(void) {
 	return(retval);
 }
 
-
-
 static
 int
 tap_state_queue_init(void) {
@@ -1232,6 +1234,7 @@ rlink_scan(
 				LOG_ERROR("enqueuing DTC reply entry: %s", strerror(errno));
 				exit(1);
 			}
+			dtc_queue.reply_index += (chunk_bits + 7) / 8;
 
 			tdi_bit_offset += chunk_bits;
 		}
@@ -1264,7 +1267,6 @@ rlink_scan(
 				dtc_mask >>= 1;
 				if (dtc_mask == 0) {
 					dtc_queue.cmd_buffer[dtc_queue.cmd_index++] = x;
-					dtc_queue.reply_index++;
 					x = 0;
 					dtc_mask = 1 << (8 - 1);
 				}
@@ -1298,6 +1300,8 @@ rlink_scan(
 			exit(1);
 		}
 
+		dtc_queue.reply_index++;
+
 		tdi_bit_offset += extra_bits;
 
 		if (type == SCAN_IN) {
@@ -1327,8 +1331,6 @@ rlink_scan(
 
 			dtc_queue.cmd_buffer[dtc_queue.cmd_index++] = x;
 		}
-
-		dtc_queue.reply_index++;
 	}
 
 	/* Schedule the last bit into the DTC command buffer */
@@ -1355,10 +1357,10 @@ rlink_scan(
 			exit(1);
 		}
 
+		dtc_queue.reply_index++;
+
 		dtc_queue.cmd_buffer[dtc_queue.cmd_index++] =
 				DTC_CMD_SHIFT_TMS_TDI_BIT_PAIR(1, (*tdi_p & tdi_mask), 1);
-
-		dtc_queue.reply_index++;
 	}
 
 	/* Move to pause state */