From: Mike Frysinger Date: Sun, 19 Sep 2010 20:28:40 +0000 (-0400) Subject: Blackfin: bf527-sdp: new board port X-Git-Tag: v2010.12-rc1~169^2~13 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=581e97df38dd23bf0b0e3840bbebd0cd730ddfc5;p=u-boot Blackfin: bf527-sdp: new board port Support for the Blackfin System Development Platform (SDP) base module. Signed-off-by: Mike Frysinger --- diff --git a/MAINTAINERS b/MAINTAINERS index 2cf29dd1d7..b0cc8254e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -993,6 +993,7 @@ Blackfin Team BF526-EZBRD BF526 BF527-EZKIT BF527 BF527-EZKIT-V2 BF527 + BF527-SDP BF527 BF533-EZKIT BF533 BF533-STAMP BF533 BF537-PNAV BF537 diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile new file mode 100644 index 0000000000..f2bd2c247d --- /dev/null +++ b/board/bf527-sdp/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c new file mode 100644 index 0000000000..504869d72a --- /dev/null +++ b/board/bf527-sdp/bf527-sdp.c @@ -0,0 +1,32 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include + +int checkboard(void) +{ + printf("Board: ADI BF527 SDP board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + + /* Enable access to parallel flash */ + gpio_request(GPIO_PG0, "parallel-flash"); + gpio_direction_output(GPIO_PG0, 0); + + return 0; +} + +int misc_init_r(void) +{ + /* CLKIN Buffer Output Enable */ + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); + + return 0; +} diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk new file mode 100644 index 0000000000..744e7a5d0d --- /dev/null +++ b/board/bf527-sdp/config.mk @@ -0,0 +1,36 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CONFIG_BFIN_CPU = bf527-0.2 + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/boards.cfg b/boards.cfg index 02eb15328f..8689ba4cd0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -283,6 +283,7 @@ bf518f-ezbrd blackfin blackfin bf526-ezbrd blackfin blackfin bf527-ad7160-eval blackfin blackfin bf527-ezkit blackfin blackfin +bf527-sdp blackfin blackfin bf533-ezkit blackfin blackfin bf533-stamp blackfin blackfin bf537-minotaur blackfin blackfin diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h new file mode 100644 index 0000000000..358284619c --- /dev/null +++ b/include/configs/bf527-sdp.h @@ -0,0 +1,121 @@ +/* + * U-boot - Configuration file for BF527 SDP board + */ + +#ifndef __CONFIG_BF527_SDP_H__ +#define __CONFIG_BF527_SDP_H__ + +#include + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 24000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 25 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + +#define CONFIG_PLL_LOCKCNT_VAL 0x0200 +#define CONFIG_PLL_CTL_VAL 0x2a00 +#define CONFIG_VR_CTL_VAL 0x7090 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x00FE +#define CONFIG_EBIU_SDGCTL_VAL 0x8011998d + +#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (640 * 1024) + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ALL + + +/* + * Env Storage Settings + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 + + +/* + * Misc Settings + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include + +#endif