From: richardbarry Date: Fri, 7 Oct 2011 08:30:23 +0000 (+0000) Subject: Create RX630/Renesas project. X-Git-Tag: V7.1.0~43 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5934a96667e2f10ae3145c71d36fe67edd9de059;p=freertos Create RX630/Renesas project. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1617 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.Hbp b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.Hbp new file mode 100644 index 000000000..0d3910dbc --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.Hbp @@ -0,0 +1,4 @@ +[Setting] +ToolChain=0 +[Section] +WindowSize=726,544 diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.hws b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.hws new file mode 100644 index 000000000..27dddfbf5 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.hws @@ -0,0 +1,45 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"11.0" +[WORKSPACE_DETAILS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo.hws" "RX" "Renesas RX Standard" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\RTOSDemo.hwp" 0 +[INFORMATION] +"No workspace information available" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[HELP_FILES] +"c:\devtools\renesas\hew\tools\renesas\rx\1_0_0\hew\stdlib.chm" "C/C++ Standard Library Help" 0 +"c:\devtools\renesas\hew\tools\renesas\rx\1_0_1\hew\stdlib.chm" "C/C++ Standard Library Help" 0 +"c:\devtools\renesas\hew\tools\renesas\rx\1_0_2\hew\stdlib.chm" "C/C++ Standard Library Help" 0 +"c:\devtools\renesas\hewforrx210-w1\tools\renesas\rx\1_1_0\hew\stdlib.chm" "C/C++ Standard Library Help" 1 +"c:\program files\renesas\hew\tools\renesas\rx\1_1_0\hew\stdlib.chm" "C/C++ Standard Library Help" 0 +[GENERAL_DATA_PROJECT] +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(PROJECTNAME)_$(CONFIGNAME).mak" "" "$(WORKSPDIR)\make" 0 0 0 +[VD_CONFIGURATION_OPTIONS] +"ACTIVE_DESKTOP" "0" +[VD_CONFIGURATIONS] +"0" "Default1" "1" +"1" "Default2" "1" +"2" "Default3" "1" +"3" "Default4" "1" +[OPTIONS_DEBUG_TAB] +0 0 0 0 0 +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[MAKEFILE_ENV_STRINGS] +[MAKEFILE_ENV_FLAGS] +1 0 0 +[MAKEFILE_CLEAN_INFO] +"" +[END] diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.tws b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.tws new file mode 100644 index 000000000..017ae1c06 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo.tws @@ -0,0 +1,21 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.2" +[CURRENT_PROJECT] +"RTOSDemo" +[GENERAL_DATA] +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\main-full.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" +[WORKSPACE_FILE_STATES] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" 66 66 1104 430 0 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" 0 0 1144 335 0 0 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\main-full.c" -4 -23 1310 655 1 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" 22 22 1104 430 0 1 +[LOADED_PROJECTS] +"RTOSDemo" +[END] diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/DefaultSession.hsf b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/DefaultSession.hsf new file mode 100644 index 000000000..4a7c75e6d --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/DefaultSession.hsf @@ -0,0 +1,106 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "1" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlWindowProperties" "17" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineWndInstanceKey0" "{WK_00000001_CmdLine}" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" +"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}ElfDwarf2Objects" "1" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}LoadModule0OBJ_ELFDWARF2_ARRAY_EXPAND_LIMIT" "-1" +"{CBEBB610-1516-11D4-8F2D-00409545B67B}LoadModule0OBJ_ELFDWARF2_STATIC_MEM_EXPAND" "1" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"Help" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 289 560 340 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 206 560 340 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000025_HELPSYSTEMTOOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N_Renesas\RTOSDemo\RTOSDemo.c" +[TARGET_NAME] +"" "" 1229201492 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"0.000000" 0 0 "" 0 "" 0 0 "" 1 1 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..1c8994ec8 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,167 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Board specifics. */ +#include "rskrx630def.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ICLK_FREQUENCY ) /* Set in rskrx630def.h. */ +#define configPERIPHERAL_CLOCK_HZ ( PCLKB_FREQUENCY ) /* Set in rskrx630def.h. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 3 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 + +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +extern volatile unsigned long ulHighFrequencyTickCount; +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() nop() /* Run time stats use the same timer as the high frequency timer test. */ +#define portGET_RUN_TIME_COUNTER_VALUE() ulHighFrequencyTickCount + + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 ) + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c new file mode 100644 index 000000000..8481782cc --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c @@ -0,0 +1,170 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * High frequency timer test as described in main.c. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( 20000UL ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( ( unsigned short ) ( ( configPERIPHERAL_CLOCK_HZ / 8UL ) / timerINTERRUPT_FREQUENCY ) ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 15 ) + +/* Misc defines. */ +#define timerTIMER_3_COUNT_VALUE ( *( ( unsigned short * ) 0x8801a ) ) /*( CMT3.CMCNT )*/ + +/*-----------------------------------------------------------*/ + +/* Interrupt handler in which the jitter is measured. */ +static void prvTimer2IntHandler( void ); + +/* Stores the value of the maximum recorded jitter between interrupts. This is +displayed on one of the served web pages. */ +volatile unsigned short usMaxJitter = 0; + +/* Counts the number of high frequency interrupts - used to generate the run +time stats. */ +volatile unsigned long ulHighFrequencyTickCount = 0UL; + +/*-----------------------------------------------------------*/ + +void vSetupHighFrequencyTimer( void ) +{ + /* Timer CMT2 is used to generate the interrupts, and CMT3 is used + to measure the jitter. */ + + /* Enable compare match timer 2 and 3. */ + MSTP( CMT2 ) = 0; + MSTP( CMT3 ) = 0; + + /* Interrupt on compare match. */ + CMT2.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT2.CMCR.BIT.CKS = 0; + CMT3.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT2_CMI2 ) = 1; + + /* ...and set its priority to the maximum possible, this is above the priority + set by configMAX_SYSCALL_INTERRUPT_PRIORITY so will nest. */ + _IPR( _CMT2_CMI2 ) = timerHIGHEST_PRIORITY; + + /* Start the timers. */ + CMT.CMSTR1.BIT.STR2 = 1; + CMT.CMSTR1.BIT.STR3 = 1; +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( prvTimer2IntHandler( vect = _VECT( _CMT2_CMI2 ), enable ) ) +static void prvTimer2IntHandler( void ) +{ +volatile unsigned short usCurrentCount; +static unsigned short usMaxCount = 0; +static unsigned long ulErrorCount = 0UL; + + /* We use the timer 1 counter value to measure the clock cycles between + the timer 0 interrupts. First stop the clock. */ + CMT.CMSTR1.BIT.STR3 = 0; + nop(); + nop(); + usCurrentCount = timerTIMER_3_COUNT_VALUE; + + /* Is this the largest count we have measured yet? */ + if( usCurrentCount > usMaxCount ) + { + if( usCurrentCount > timerEXPECTED_DIFFERENCE_VALUE ) + { + usMaxJitter = usCurrentCount - timerEXPECTED_DIFFERENCE_VALUE; + } + else + { + /* This should not happen! */ + ulErrorCount++; + } + + usMaxCount = usCurrentCount; + } + + /* Used to generate the run time stats. */ + ulHighFrequencyTickCount++; + + /* Clear the timer. */ + timerTIMER_3_COUNT_VALUE = 0; + + /* Then start the clock again. */ + CMT.CMSTR1.BIT.STR3 = 1; +} + + + + + + + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/IntQueueTimer.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/IntQueueTimer.c new file mode 100644 index 000000000..384fa540e --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/IntQueueTimer.c @@ -0,0 +1,143 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2001UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + IEN( TMR0, CMIA0 ) = 1; + IEN( TMR2, CMIA2 ) = 1; + + /* Set the timer interrupts to be above the kernel. The interrupts are + assigned different priorities so they nest with each other. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 ); + } + portEXIT_CRITICAL(); + + /* Ensure the interrupts are clear as they are edge detected. */ + IR( TMR0, CMIA0 ) = 0; + IR( TMR2, CMIA2 ) = 0; +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) ) +void vT0_1InterruptHandler( void ) +{ + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) ) +void vT2_3InterruptHandler( void ) +{ + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + + + + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/ParTest.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/ParTest.c new file mode 100644 index 000000000..2a9c63bd3 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/ParTest.c @@ -0,0 +1,183 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/*----------------------------------------------------------- + * Simple IO routines to control the LEDs. + *-----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define partestNUM_LEDS ( 4 ) + +long lParTestGetLEDState( unsigned long ulLED ); + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Port pin configuration is done by the low level set up prior to this + function being called. */ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned long ulLED, signed long xValue ) +{ + if( ulLED < partestNUM_LEDS ) + { + if( xValue != 0 ) + { + /* Turn the LED on. */ + taskENTER_CRITICAL(); + { + switch( ulLED ) + { + case 0: LED0 = LED_ON; + break; + case 1: LED1 = LED_ON; + break; + case 2: LED2 = LED_ON; + break; + case 3: LED3 = LED_ON; + break; + } + } + taskEXIT_CRITICAL(); + } + else + { + /* Turn the LED off. */ + taskENTER_CRITICAL(); + { + switch( ulLED ) + { + case 0: LED0 = LED_OFF; + break; + case 1: LED1 = LED_OFF; + break; + case 2: LED2 = LED_OFF; + break; + case 3: LED3 = LED_OFF; + break; + } + + } + taskEXIT_CRITICAL(); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned long ulLED ) +{ + if( ulLED < partestNUM_LEDS ) + { + taskENTER_CRITICAL(); + { + if( lParTestGetLEDState( ulLED ) != 0x00 ) + { + vParTestSetLED( ulLED, 0 ); + } + else + { + vParTestSetLED( ulLED, 1 ); + } + } + taskEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +long lParTestGetLEDState( unsigned long ulLED ) +{ +long lReturn = pdTRUE; + + if( ulLED < partestNUM_LEDS ) + { + switch( ulLED ) + { + case 0 : if( LED0 != 0 ) + { + lReturn = pdFALSE; + } + break; + case 1 : if( LED1 != 0 ) + { + lReturn = pdFALSE; + } + break; + case 2 : if( LED2 != 0 ) + { + lReturn = pdFALSE; + } + break; + case 3 : if( LED3 != 0 ) + { + lReturn = pdFALSE; + } + break; + } + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + + \ No newline at end of file diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/RTOSDemo.hwp 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b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/RTOSDemo.tps @@ -0,0 +1,69 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.1" +[SESSIONS_] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[CONFIGURATIONS] +"Blinky" +"Debug" +"Debug_RX600_E1_E20_SYSTEM" +"Debug_with_optimisation" +"SimDebug_RX600" +[CURRENT_CONFIGURATION] +"Debug" +[CURRENT_SESSION] +"SessionRX600_E1_E20_SYSTEM" +[GENERAL_DATA_PROJECT] +"FDT_UserBootAreaFiles" "" +[GENERAL_DATA_CONFIGURATION_Blinky] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Blinky] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Debug] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_CONFIGURATION_Debug_RX600_E1_E20_SYSTEM] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Debug_RX600_E1_E20_SYSTEM] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_CONFIGURATION_Debug_with_optimisation] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Debug_with_optimisation] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_CONFIGURATION_SimDebug_RX600] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_SimDebug_RX600] +"DefaultSession" +"SessionRX600_E1_E20_SYSTEM" +"SimSessionRX600" +[GENERAL_DATA_SESSION_SimSessionRX600] +[GENERAL_DATA_SESSION_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM] +[GENERAL_DATA_SESSION_SessionRX600_E1_E20_SYSTEM] +[END] diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc.c new file mode 100644 index 000000000..2ef0f8cb4 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc.c @@ -0,0 +1,139 @@ + + +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +*******************************************************************************/ + + +/* + * cgc.c + * + * Created on: 01 Oct 2011 + * Author: RJW + * Reneses Electronics Europe Ltd + */ + + +/****************************************************************************** + System Includes +******************************************************************************/ + + +/****************************************************************************** + User Includes +******************************************************************************/ +#include "iodefine.h" +#include "cgc.h" + + +/*****************************************************************************/ +/* */ +/* Configure the CGC (Clock Generation Circuit) of the RX630 using the */ +/* using the 7 STEPS specified in cgc.h */ +/* */ +/*****************************************************************************/ + + +/****************************************************************************** + Function : InitCGC + Description : Initialises the CGC registers based upon the settings + made in file cgc.h + Argument : none + Return value : none +******************************************************************************/ +void InitCGC(void) +{ + unsigned long i; + +#if (ENABLE_SUB) + SYSTEM.SOSCCR.BYTE = 0x00; /* Sub-clock oscillator ON */ +#else + SYSTEM.SOSCCR.BYTE = 0x01; /* Sub-clock oscillator OFF */ +#endif + +#if (ENABLE_HOCO) + SYSTEM.HOCOPCR.BYTE = 0x00; /* HOCO PSU ON */ + SYSTEM.HOCOCR.BYTE = 0x00; /* HOCO ON */ +#else + SYSTEM.HOCOPCR.BYTE = 0x01; /* HOCO PSU OFF */ + SYSTEM.HOCOCR.BYTE = 0x01; /* HOCO OFF */ +#endif + + + +#if (ENABLE_MAIN) + SYSTEM.MOSCWTCR.BYTE = 0x0e; /* Main Clock Oscillator Wait Control Register */ + /* 262144 states */ + SYSTEM.MOSCCR.BYTE = 0x00; /* EXTAL ON */ +#else + SYSTEM.MOSCCR.BYTE = 0x01; /* EXTAL OFF */ +#endif + + +#if (ENABLE_PLL) + SYSTEM.MOSCWTCR.BYTE = 0x0e; /* Main Clock Oscillator Wait Control Register */ + /* 262144 states */ + SYSTEM.MOSCCR.BYTE = 0x00; /* EXTAL ON */ + + SYSTEM.PLLWTCR.BYTE = 0x0e; /* PLL Wait Control Register */ + /* 2097152 states */ + + SYSTEM.PLLCR2.BYTE = 0x01; /* PLL OFF */ + + #if (PLL_INPUT_FREQ_DIV == 1) + SYSTEM.PLLCR.BIT.PLIDIV = 0; + #elif (PLL_INPUT_FREQ_DIV == 2) + SYSTEM.PLLCR.BIT.PLIDIV = 1; + #elif (PLL_INPUT_FREQ_DIV == 4) + SYSTEM.PLLCR.BIT.PLIDIV = 2; + #else + SYSTEM.PLLCR.BIT.PLIDIV = 0; + #endif + SYSTEM.PLLCR.BIT.STC = (PLL_MUL - 1); + + /* External oscillation input selection */ + SYSTEM.PLLCR2.BYTE = 0x00; /* PLL ON */ +#else + SYSTEM.PLLCR2.BYTE = 0x01; /* PLL OFF */ +#endif + + for(i = 0; i<2500; i++) /* Wait for stabilisation of */ + { /* HOCO, LOCO, PLL and main clock */ + } /* = 20ms */ + /* (2500 x 1/125kHz = 20ms) */ + + + SYSTEM.SCKCR.LONG = FCLK_SCKCR | + ICLK_SCKCR | + PSTOP1_SCKCR | + BCLK_SCKCR | + PCLK1215_SCKCR | + PCLKB_SCKCR | + PCLK47_SCKCR | + PCLK03_SCKCR ; + + + SYSTEM.SCKCR2.WORD = UCK_SCKCR2 | + IEBCK_SCKCR2 ; + + + SYSTEM.SCKCR3.WORD = CLK_SOURCE; +} \ No newline at end of file diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc.h new file mode 100644 index 000000000..31c426d82 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc.h @@ -0,0 +1,205 @@ + + +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +*******************************************************************************/ + + +/* + * cgc.h + * + * Created on: 01 Oct 2011 + * Author: RJW + * Reneses Electronics Europe Ltd + */ + + +#ifndef CGC_H_ +#define CGC_H_ + +/****************************************************************************** + Function Prototypes +******************************************************************************/ +void InitCGC(void); + + +/*****************************************************************************/ +/* */ +/* Set the CGC (Clock Generation Circuit of the RX630 using the */ +/* following 7 STEPS */ +/* */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* */ +/* STEP 1: System Clock Options */ +/* */ +/* Enter one of the CLK_SOURCE_ options into the */ +/* */ +/* #define CLK_SOURCE ( xxx ) */ +/* below. */ +/* This will be the clock source that the device will switch to as part of */ +/* HardwareSetup() */ +/* Extra clocks can be enabled in STEP 3. */ +/* */ +/* For example */ +/* #define CLK_SOURCE (CLK_SOURCE_MAIN) */ +/* */ +/*****************************************************************************/ +#define CLK_SOURCE_LOCO 0x0000 +#define CLK_SOURCE_HOCO 0x0100 +#define CLK_SOURCE_MAIN 0x0200 +#define CLK_SOURCE_SUB 0x0300 +#define CLK_SOURCE_PLL 0x0400 + +#define CLK_SOURCE (CLK_SOURCE_PLL) + + +/*****************************************************************************/ +/* */ +/* STEP 2: External XTAL values */ +/* */ +/* If using the CLK_SOURCE_MAIN, CLK_SOURCE_SUB, CLK_SOURCE_PLL */ +/* enter the MAIN XTAL and SUB XTAL values here. */ +/* */ +/* If using the PLL, enter the PLL multiplier and PLL frequency divder */ +/* Use the divider so that the input frequency into the PLL is in */ +/* the range of 4 MHz to 16 MHz. */ +/* */ +/* Use the multiplier so that the output frequency of the PLL is in */ +/* the range of 104MHz to 200Mhz */ +/* */ +/* The PLL frequency divider values are: */ +/* /1, /2, /4 */ +/* The PLL muliplier values are: */ +/* x8, x10, x12, x16, x20, x24, x25, x50 */ +/* */ +/* Example: */ +/* XTAL = 12MHz */ +/* PLL Divider = 1 */ +/* */ +/* Therefore, input into PLL = 12M / 1 */ +/* = 12M */ +/* PLL Multipler = 16 */ +/* */ +/* Therefore, ouput of PLL = 12M x 16 */ +/* = 192M */ +/* */ +/* NOTE: The maximum XTAL is 20MHz */ +/*****************************************************************************/ +#define XTAL_FREQUENCY (12000000L) +#define PLL_MUL (16) +#define PLL_INPUT_FREQ_DIV (1) + +#define SUB_FREQUENCY (32768L) + + +/*****************************************************************************/ +/* */ +/* STEP 3: Enable the chosen clock source and any extra clock sources */ +/* Remeber to enable the clock source chosen in STEP 1. */ +/* Foe example, if CLK_SOURCE_PLL has been chosen, set */ +/* #define ENABLE_PLL (1) */ +/* */ +/*****************************************************************************/ +#define ENABLE_HOCO (1) +#define ENABLE_SUB (0) +#define ENABLE_MAIN (0) +#define ENABLE_PLL (1) + + + +/*****************************************************************************/ +/* */ +/* STEP 4: */ +/* Enter the Clock Divders for */ +/* - FCLK_DIV, ICLK_DIV, BCLK_DIV, PCLKA_DIV, PCLKB_DIV */ +/* Valid values are 1, 2, 4, 8, 16, 32 and 64 */ +/* */ +/* The Clock Value being divided is: */ +/* If LOCO, 125kHz */ +/* If HOCO, 50MHz */ +/* If SUB, the value of SUB specified in STEP 2 */ +/* If MAIN, the value of XTAL specified in STEP 2 */ +/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */ +/*****************************************************************************/ +#define FCLK_DIV (4) +#define ICLK_DIV (2) +#define BCLK_DIV (4) +#define PCLK1215_DIV (2) /* Do not change this */ +#define PCLKB_DIV (4) +#define PCLK47_DIV (2) /* Do not change this */ +#define PCLK03_DIV (2) /* Do not change this */ + + +/*****************************************************************************/ +/* */ +/* STEP 5: */ +/* Enter the Clock Divder for */ +/* - IEBCK_DIV */ +/* Valid values are 2, 4, 6, 8, 16, 32 and 64 */ +/* */ +/* The Clock Value being divided is: */ +/* If LOCO, 125kHz */ +/* If HOCO, 50MHz */ +/* If SUB, the value of SUB specified in STEP 2 */ +/* If MAIN, the value of XTAL specified in STEP 2 */ +/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */ +/*****************************************************************************/ +#define IEBCK_DIV (2) + + +/*****************************************************************************/ +/* */ +/* STEP 6: */ +/* Enter the Clock Divder for */ +/* - UCK_DIV */ +/* Valid values are 3, 4 */ +/* */ +/* The Clock Value being divided is: */ +/* If LOCO, 125kHz */ +/* If HOCO, 50MHz */ +/* If SUB, the value of SUB specified in STEP 2 */ +/* If MAIN, the value of XTAL specified in STEP 2 */ +/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */ +/*****************************************************************************/ +#define UCK_DIV (3) + + +/*****************************************************************************/ +/* */ +/* STEP 7: */ +/* Specify the use of BCLK pin */ +/* To ENABLE, set to (0) */ +/* To DISABLE, set to (1) */ +/* */ +/*****************************************************************************/ +#define BCLK_PIN (1) + + +/*****************************************************************************/ +/* Clock configuration is now complete. */ +/*****************************************************************************/ +#include "cgc_set.h" +#include "cgc_error.h" + +#endif \ No newline at end of file diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_error.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_error.h new file mode 100644 index 000000000..f5355427d --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_error.h @@ -0,0 +1,47 @@ +#ifndef CGC_ERROR_H_ +#define CGC_ERROR_H_ + +/* Error checking macros for the clock selction and clock enable defines */ + +#if ( (CLK_SOURCE != CLK_SOURCE_LOCO) && \ + (CLK_SOURCE != CLK_SOURCE_HOCO) && \ + (CLK_SOURCE != CLK_SOURCE_MAIN) && \ + (CLK_SOURCE != CLK_SOURCE_SUB) && \ + (CLK_SOURCE != CLK_SOURCE_PLL) ) + #error "No CLK_SOURCE specified. Please specify a valid CLK_SOURCE"; +#endif + + +#if (CLK_SOURCE == CLK_SOURCE_HOCO) && (ENABLE_HOCO == 0) + #error "HOCO has been specified as the CLK_SOURCE but ENABLE_HOCO is (0). Please set to (1) in file cgc.h" +#endif + +#if (CLK_SOURCE == CLK_SOURCE_MAIN) && (ENABLE_MAIN == 0) + #error "HOCO has been specified as the CLK_SOURCE but ENABLE_HOCO is (0). Please set to (1) in file cgc.h" +#endif + +#if (CLK_SOURCE == CLK_SOURCE_SUB) && (ENABLE_SUB == 0) + #error "HOCO has been specified as the CLK_SOURCE but ENABLE_HOCO is (0). Please set to (1) in file cgc.h" +#endif + +#if (CLK_SOURCE == CLK_SOURCE_PLL) && (ENABLE_PLL == 0) + #error "PLL has been specified as the CLK_SOURCE but ENABLE_PLL is (0). Please set to (1) in file cgc.h" +#endif + +#if ( FCLK_FREQUENCY > 50000000L ) + #error "FCLK_FREQUENCY Error: Please enter a valid divider value" +#endif + +#if ( ICLK_FREQUENCY > 100000000L ) + #error "ICLK_FREQUENCY Error: Please enter a valid divider value" +#endif + +#if ( BCLK_FREQUENCY > 100000000L ) + #error "BCLK_FREQUENCY Error: Please enter a valid divider value" +#endif + +#if ( PCLKB_FREQUENCY > 50000000L ) + #error "PCLKB_FREQUENCY Error: Please enter a valid divider value" +#endif + +#endif \ No newline at end of file diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_set.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_set.h new file mode 100644 index 000000000..b155b1149 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_set.h @@ -0,0 +1,233 @@ +#ifndef CGC_SET_VALUES_H_ +#define CGC_SET_VALUES_H_ + +/* Do not modify these macros. These values are used to initialise + the SCKCR and SCKCR2 registers based upon the above values. */ +#if (FCLK_DIV == 64) + #define FCLK_SCKCR 0x60000000L +#elif (FCLK_DIV == 32) + #define FCLK_SCKCR 0x50000000L +#elif (FCLK_DIV == 16) + #define FCLK_SCKCR 0x40000000L +#elif (FCLK_DIV == 8) + #define FCLK_SCKCR 0x30000000L +#elif (FCLK_DIV == 4) + #define FCLK_SCKCR 0x20000000L +#elif (FCLK_DIV == 2) + #define FCLK_SCKCR 0x10000000L +#elif(FCLK_DIV == 1) + #define FCLK_SCKCR 0x00000000L +#else + #define FCLK_SCKCR 0x10000000L +#endif + + +#if (ICLK_DIV == 64) + #define ICLK_SCKCR 0x06000000L +#elif (ICLK_DIV == 32) + #define ICLK_SCKCR 0x05000000L +#elif (ICLK_DIV == 16) + #define ICLK_SCKCR 0x04000000L +#elif (ICLK_DIV == 8) + #define ICLK_SCKCR 0x03000000L +#elif (ICLK_DIV == 4) + #define ICLK_SCKCR 0x02000000L +#elif (ICLK_DIV == 2) + #define ICLK_SCKCR 0x01000000L +#elif (ICLK_DIV == 1) + #define ICLK_SCKCR 0x00000000L +#else + #define ICLK_SCKCR 0x01000000L +#endif + + +#if (BCLK_PIN == 1) + #define PSTOP1_SCKCR 0x00800000L +#elif + #define PSTOP1_SCKCR 0x00000000L +#endif + + +#if (BCLK_DIV == 64) + #define BCLK_SCKCR 0x00060000L +#elif (BCLK_DIV == 32) + #define BCLK_SCKCR 0x00050000L +#elif (BCLK_DIV == 16) + #define BCLK_SCKCR 0x00040000L +#elif (BCLK_DIV == 8) + #define BCLK_SCKCR 0x00030000L +#elif (BCLK_DIV == 4) + #define BCLK_SCKCR 0x00020000L +#elif (BCLK_DIV == 2) + #define BCLK_SCKCR 0x00010000L +#elif (BCLK_DIV == 1) + #define BCLK_SCKCR 0x00000000L +#else + #define BCLK_SCKCR 0x00010000L +#endif + + +#if (PCLK1215_DIV == 64) + #define PCLK1215_SCKCR 0x00006000L +#elif (PCLK1215_DIV == 32) + #define PCLK1215_SCKCR 0x00005000L +#elif (PCLK1215_DIV == 16) + #define PCLK1215_SCKCR 0x00004000L +#elif (PCLK1215_DIV == 8) + #define PCLK1215_SCKCR 0x00003000L +#elif (PCLK1215_DIV == 4) + #define PCLK1215_SCKCR 0x00002000L +#elif (PCLK1215_DIV == 2) + #define PCLK1215_SCKCR 0x00001000L +#elif (PCLK1215_DIV == 1) + #define PCLK1215_SCKCR 0x00000000L +#else + #define PCLK1215_SCKCR 0x00001000L +#endif + + +#if (PCLKB_DIV == 64) + #define PCLKB_SCKCR 0x00000600L +#elif (PCLKB_DIV == 32) + #define PCLKB_SCKCR 0x00000500L +#elif (PCLKB_DIV == 16) + #define PCLKB_SCKCR 0x00000400L +#elif (PCLKB_DIV == 8) + #define PCLKB_SCKCR 0x00000300L +#elif (PCLKB_DIV == 4) + #define PCLKB_SCKCR 0x00000200L +#elif (PCLKB_DIV == 2) + #define PCLKB_SCKCR 0x00000100L +#elif (PCLKB_DIV == 1) + #define PCLKB_SCKCR 0x00000000L +#else + #define PCLKB_SCKCR 0x00000100L +#endif + + +#if (PCLK47_DIV == 64) + #define PCLK47_SCKCR 0x00000060L +#elif (PCLK47_DIV == 32) + #define PCLK47_SCKCR 0x00000050L +#elif (PCLK47_DIV == 16) + #define PCLK47_SCKCR 0x00000040L +#elif (PCLK47_DIV == 8) + #define PCLK47_SCKCR 0x00000030L +#elif (PCLK47_DIV == 4) + #define PCLK47_SCKCR 0x00000020L +#elif (PCLK47_DIV == 2) + #define PCLK47_SCKCR 0x00000010L +#elif (PCLK47_DIV == 1) + #define PCLK47_SCKCR 0x00000000L +#else + #define PCLK47_SCKCR 0x00000010L +#endif + + +#if (PCLK03_DIV == 64) + #define PCLK03_SCKCR 0x00000006L +#elif (PCLK03_DIV == 32) + #define PCLK03_SCKCR 0x00000005L +#elif (PCLK03_DIV == 16) + #define PCLK03_SCKCR 0x00000004L +#elif (PCLK03_DIV == 8) + #define PCLK03_SCKCR 0x00000003L +#elif (PCLK03_DIV == 4) + #define PCLK03_SCKCR 0x00000002L +#elif (PCLK03_DIV == 2) + #define PCLK03_SCKCR 0x00000001L +#elif (PCLK03_DIV == 1) + #define PCLK03_SCKCR 0x00000000L +#else + #define PCLK03_SCKCR 0x00000001L +#endif + + +#if (UCK_DIV == 6) + #define UCK_SCKCR2 0x00C0L +#elif (UCK_DIV == 64) + #define UCK_SCKCR2 0x0060L +#elif (UCK_DIV == 32) + #define UCK_SCKCR2 0x0050L +#elif (UCK_DIV == 16) + #define UCK_SCKCR2 0x0040L +#elif (UCK_DIV == 8) + #define UCK_SCKCR2 0x0030L +#elif (UCK_DIV == 4) + #define UCK_SCKCR2 0x0020L +#elif (UCK_DIV == 2) + #define UCK_SCKCR2 0x0010L +#else + #define UCK_SCKCR2 0x0010L +#endif + + +#if (IEBCK_DIV == 3) + #define IEBCK_SCKCR2 0x00000020L +#elif (IEBCK_DIV == 4) + #define IEBCK_SCKCR2 0x00000030L +#else + #define IEBCK_SCKCR2 0x00000030L +#endif + + +#if (CLK_SOURCE == CLK_SOURCE_LOCO) +/* Internal LOCO circuit - 125kHz*/ +#define CLK_FREQUENCY (125000L) +#define FCLK_FREQUENCY (CLK_FREQUENCY / FCLK_DIV) +#define ICLK_FREQUENCY (CLK_FREQUENCY / ICLK_DIV) +#define BCLK_FREQUENCY (CLK_FREQUENCY / BCLK_DIV) +#define PCLKA_FREQUENCY (CLK_FREQUENCY / PCLK1215_DIV) +#define PCLKB_FREQUENCY (CLK_FREQUENCY / PCLKB_DIV) +#define PCLK47_FREQUENCY (CLK_FREQUENCY / PCLK47_DIV) +#define PCLK03_FREQUENCY (CLK_FREQUENCY / PCLK03_DIV) + + +#elif (CLK_SOURCE == CLK_SOURCE_HOCO) +/* Internal high speed on-chip oscillator (HOCO) */ +#define CLK_FREQUENCY (50000000L) +#define FCLK_FREQUENCY (CLK_FREQUENCY / FCLK_DIV) +#define ICLK_FREQUENCY (CLK_FREQUENCY / ICLK_DIV) +#define BCLK_FREQUENCY (CLK_FREQUENCY / BCLK_DIV) +#define PCLKA_FREQUENCY (CLK_FREQUENCY / PCLK1215_DIV) +#define PCLKB_FREQUENCY (CLK_FREQUENCY / PCLKB_DIV) +#define PCLK47_FREQUENCY (CLK_FREQUENCY / PCLK47_DIV) +#define PCLK03_FREQUENCY (CLK_FREQUENCY / PCLK03_DIV) + + +#elif (CLK_SOURCE == CLK_SOURCE_MAIN) +/* External XTAL, but not via the PLL circuit */ +#define FCLK_FREQUENCY (XTAL_FREQUENCY / FCLK_DIV) +#define ICLK_FREQUENCY (XTAL_FREQUENCY / ICLK_DIV) +#define BCLK_FREQUENCY (XTAL_FREQUENCY / BCLK_DIV) +#define PCLKA_FREQUENCY (XTAL_FREQUENCY / PCLK1215_DIV) +#define PCLKB_FREQUENCY (XTAL_FREQUENCY / PCLKB_DIV) +#define PCLK47_FREQUENCY (XTAL_FREQUENCY / PCLK47_DIV) +#define PCLK03_FREQUENCY (XTAL_FREQUENCY / PCLK03_DIV) + + +#elif (CLK_SOURCE == CLK_SOURCE_SUB) +/* External 32khZ XTAL */ +#define FCLK_FREQUENCY (SUB_FREQUENCY / FCLK_DIV) +#define ICLK_FREQUENCY (SUB_FREQUENCY / ICLK_DIV) +#define BCLK_FREQUENCY (SUB_FREQUENCY / BCLK_DIV) +#define PCLKA_FREQUENCY (SUB_FREQUENCY / PCLK1215_DIV) +#define PCLKB_FREQUENCY (SUB_FREQUENCY / PCLKB_DIV) +#define PCLK47_FREQUENCY (SUB_FREQUENCY / PCLK47_DIV) +#define PCLK03_FREQUENCY (SUB_FREQUENCY / PCLK03_DIV) + + +#elif (CLK_SOURCE == CLK_SOURCE_PLL) +/* External XTAL, but using the PLL circuit */ +#define PLL_FREQUENCY (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV)) +#define FCLK_FREQUENCY (PLL_FREQUENCY / FCLK_DIV) +#define ICLK_FREQUENCY (PLL_FREQUENCY / ICLK_DIV) +#define BCLK_FREQUENCY (PLL_FREQUENCY / BCLK_DIV) +#define PCLKA_FREQUENCY (PLL_FREQUENCY / PCLK1215_DIV) +#define PCLKB_FREQUENCY (PLL_FREQUENCY / PCLKB_DIV) +#define PCLK47_FREQUENCY (PLL_FREQUENCY / PCLK47_DIV) +#define PCLK03_FREQUENCY (PLL_FREQUENCY / PCLK03_DIV) + +#endif + +#endif \ No newline at end of file diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/dbsct.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/dbsct.c new file mode 100644 index 000000000..156f0b8f3 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/dbsct.c @@ -0,0 +1,66 @@ +/***********************************************************************/ +/* */ +/* FILE :dbsct.c */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Setting of B,R Section */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + +/********************************************************************* +* +* Device : RX +* +* File Name : dbsct.c +* +* Abstract : Setting of B,R Section. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include "typedefine.h" + +#pragma unpack + +#pragma section C C$DSEC +extern const struct { + _UBYTE *rom_s; /* Start address of the initialized data section in ROM */ + _UBYTE *rom_e; /* End address of the initialized data section in ROM */ + _UBYTE *ram_s; /* Start address of the initialized data section in RAM */ +} _DTBL[] = { + { __sectop("D"), __secend("D"), __sectop("R") }, + { __sectop("D_2"), __secend("D_2"), __sectop("R_2") }, + { __sectop("D_1"), __secend("D_1"), __sectop("R_1") } +}; +#pragma section C C$BSEC +extern const struct { + _UBYTE *b_s; /* Start address of non-initialized data section */ + _UBYTE *b_e; /* End address of non-initialized data section */ +} _BTBL[] = { + { __sectop("B"), __secend("B") }, + { __sectop("B_2"), __secend("B_2") }, + { __sectop("B_1"), __secend("B_1") } +}; + +#pragma section + +/* +** CTBL prevents excessive output of L1100 messages when linking. +** Even if CTBL is deleted, the operation of the program does not change. +*/ +_UBYTE * const _CTBL[] = { + __sectop("C_1"), __sectop("C_2"), __sectop("C"), + __sectop("W_1"), __sectop("W_2"), __sectop("W") +}; + +#pragma packoption diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/hwsetup.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/hwsetup.c new file mode 100644 index 000000000..e6fc56aea --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/hwsetup.c @@ -0,0 +1,154 @@ +/****************************************************************************** +* DISCLAIMER + +* This software is supplied by Renesas Technology Corp. and is only +* intended for use with Renesas products. No other uses are authorized. + +* This software is owned by Renesas Technology Corp. and is protected under +* all applicable laws, including copyright laws. + +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES +* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, +* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY +* DISCLAIMED. + +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES +* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS +* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +* Renesas reserves the right, without notice, to make changes to this +* software and to discontinue the availability of this software. +* By using this software, you agree to the additional terms and +* conditions found by accessing the following link: +* http://www.renesas.com/disclaimer +****************************************************************************** +* Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : hwsetup.c +* Version : 1.00 +* Description : Power up hardware initializations +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.02.2010 1.00 First Release +******************************************************************************/ + + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include "iodefine.h" +#include "cgc.h" +#include "rskrx630def.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ +void io_set_cpg(void); +void ConfigurePortPins(void); +void EnablePeripheralModules(void); + +/****************************************************************************** +* Function Name: HardwareSetup +* Description : This function does initial setting for CPG port pins used in +* : the Demo including the MII pins of the Ethernet PHY connection. +* Arguments : none +* Return Value : none +******************************************************************************/ +void HardwareSetup(void) +{ + /* Gain access to the System control registers */ + /* Refer to section 13 of the Hardware User Manual for further details */ + SYSTEM.PRCR.WORD = 0xA503; + + /* Gain access to the Port Function Select Registers */ + /* Refer to section 21 of the Hardware User Manual for further details */ + MPC.PWPR.BIT.B0WI = 0; + MPC.PWPR.BIT.PFSWE = 1; + + /* CPG setting */ + /* User defined values for XTAL, Clock Divders etc are set in cgc.h */ + InitCGC(); + + /* Setup the port pins */ + ConfigurePortPins(); + + /* Enables peripherals */ + EnablePeripheralModules(); + +#if INCLUDE_LCD == 1 + /* Initialize display */ + InitialiseDisplay(); +#endif +} + +/****************************************************************************** +* Function Name: EnablePeripheralModules +* Description : Enables Peripheral Modules before use +* Arguments : none +* Return Value : none +******************************************************************************/ +void EnablePeripheralModules(void) +{ + /* Module standby clear */ + SYSTEM.MSTPCRA.BIT.MSTPA15 = 0; /* CMT0 */ +} + +/****************************************************************************** +* Function Name: ConfigurePortPins +* Description : Configures port pins. +* Arguments : none +* Return Value : none +******************************************************************************/ +void ConfigurePortPins(void) +{ +/* Port pins default to inputs. To ensure safe initialisation set the pin states +before changing the data direction registers. This will avoid any unintentional +state changes on the external ports. +Many peripheral modules will override the setting of the port registers. Ensure +that the state is safe for external devices if the internal peripheral module is +disabled or powered down. */ + + /* Set initial LED pin state to off */ + LED0 = 1; + LED1 = 1; + LED2 = 1; + LED3 = 1; + /* Configure LED 0-3 pin settings */ + LED0_PDR = 1; + LED1_PDR = 1; + LED2_PDR = 1; + LED3_PDR = 1; + + /* Configure SW 1-3 pin settings */ + /* No need to configure inputs as they are inputs by default */ + +#if INCLUDE_LCD == 1 + /* Set LCD pins as outputs */ + /* LCD-RS */ + LCD_RS_PDR = 1; + /* LCD-EN */ + LCD_EN = 1; + /*LCD-data */ + LCD_DATA_PDR = 0xF0; +#endif +} diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/intprg.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/intprg.c new file mode 100644 index 000000000..b5ef3862f --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/intprg.c @@ -0,0 +1,53 @@ +/***********************************************************************/ +/* */ +/* FILE :intprg.c */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Interrupt Program */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX/RX600 +* +* File Name : intprg.c +* +* Abstract : Interrupt Program. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include +#include "vect.h" +#pragma section IntPRG + +// Exception(Supervisor Instruction) +void Excep_SuperVisorInst(void){/* brk(); */} + +// Exception(Undefined Instruction) +void Excep_UndefinedInst(void){/* brk(); */} + +// Exception(Floating Point) +void Excep_FloatingPoint(void){/* brk(); */} + +// NMI +void NonMaskableInterrupt(void){/* brk(); */} + +// Dummy +void Dummy(void){/* brk(); */} + +// BRK +void Excep_BRK(void){ wait(); } + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/lowlvl.src b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/lowlvl.src new file mode 100644 index 000000000..70330dadd --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/lowlvl.src @@ -0,0 +1,120 @@ + +; Comment out the orginal code + .IF 0 + +;------------------------------------------------------------------------ +; | +; FILE :lowlvl.src | +; DATE :Wed, Jun 16, 2010 | +; DESCRIPTION :Program of Low level | +; CPU TYPE :Other | +; | +; This file is generated by Renesas Project Generator (Ver.4.50). | +; NOTE:THIS IS A TYPICAL EXAMPLE. | +; | +;------------------------------------------------------------------------ + + + .GLB _charput + .GLB _charget + +SIM_IO .EQU 0h + + .SECTION P,CODE +;----------------------------------------------------------------------- +; _charput: +;----------------------------------------------------------------------- +_charput: + MOV.L #IO_BUF,R2 + MOV.B R1,[R2] + MOV.L #1220000h,R1 + MOV.L #PARM,R3 + MOV.L R2,[R3] + MOV.L R3,R2 + MOV.L #SIM_IO,R3 + JSR R3 + RTS + +;----------------------------------------------------------------------- +; _charget: +;----------------------------------------------------------------------- +_charget: + MOV.L #1210000h,R1 + MOV.L #IO_BUF,R2 + MOV.L #PARM,R3 + MOV.L R2,[R3] + MOV.L R3,R2 + MOV.L #SIM_IO,R3 + JSR R3 + MOV.L #IO_BUF,R2 + MOVU.B [R2],R1 + RTS + +;----------------------------------------------------------------------- +; I/O Buffer +;----------------------------------------------------------------------- + .SECTION B,DATA,ALIGN=4 +PARM: .BLKL 1 + .SECTION B_1,DATA +IO_BUF: .BLKB 1 +; .END ; Commented out for conditional assembly + +; Code below is for debug console + .ELSE + +;----------------------------------------------------------------------- +; +; FILE :lowlvl.src +; DATE :Wed, Jul 01, 2009 +; DESCRIPTION :Program of Low level +; CPU TYPE :RX +; +;----------------------------------------------------------------------- + .GLB _charput + .GLB _charget + +FC2E0 .EQU 00084080h +FE2C0 .EQU 00084090h +DBGSTAT .EQU 000840C0h +RXFL0EN .EQU 00001000h +TXFL0EN .EQU 00000100h + + .SECTION P,CODE + +;----------------------------------------------------------------------- +; _charput: +;----------------------------------------------------------------------- +_charput: + .STACK _charput = 00000000h +__C2ESTART: MOV.L #TXFL0EN,R3 + MOV.L #DBGSTAT,R4 +__TXLOOP: MOV.L [R4],R5 + AND R3,R5 + BNZ __TXLOOP +__WRITEFC2E0: MOV.L #FC2E0,R2 + MOV.L R1,[R2] +__CHARPUTEXIT: RTS + +;----------------------------------------------------------------------- +; _charget: +;----------------------------------------------------------------------- +_charget: + .STACK _charget = 00000000h +__E2CSTART: MOV.L #RXFL0EN,R3 + MOV.L #DBGSTAT,R4 +__RXLOOP: MOV.L [R4],R5 + AND R3,R5 + BZ __RXLOOP +__READFE2C0: MOV.L #FE2C0,R2 + MOV.L [R2],R1 +__CHARGETEXIT: RTS + +;----------------------------------------------------------------------- + +; End of conditional code + .ENDIF + + .END + + + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/lowsrc.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/lowsrc.c new file mode 100644 index 000000000..2d02ccad9 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/lowsrc.c @@ -0,0 +1,329 @@ +/***********************************************************************/ +/* */ +/* FILE :lowsrc.c */ +/* DATE :Wed, Jun 16, 2010 */ +/* DESCRIPTION :Program of I/O Stream */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX +* +* File Name : lowsrc.c +* +* Abstract : Program of I/O Stream. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include +#include +#include +#include "lowsrc.h" + +/* file number */ +#define STDIN 0 /* Standard input (console) */ +#define STDOUT 1 /* Standard output (console) */ +#define STDERR 2 /* Standard error output (console) */ + +#define FLMIN 0 /* Minimum file number */ +#define _MOPENR 0x1 +#define _MOPENW 0x2 +#define _MOPENA 0x4 +#define _MTRUNC 0x8 +#define _MCREAT 0x10 +#define _MBIN 0x20 +#define _MEXCL 0x40 +#define _MALBUF 0x40 +#define _MALFIL 0x80 +#define _MEOF 0x100 +#define _MERR 0x200 +#define _MLBF 0x400 +#define _MNBF 0x800 +#define _MREAD 0x1000 +#define _MWRITE 0x2000 +#define _MBYTE 0x4000 +#define _MWIDE 0x8000 +/* File Flags */ +#define O_RDONLY 0x0001 /* Read only */ +#define O_WRONLY 0x0002 /* Write only */ +#define O_RDWR 0x0004 /* Both read and Write */ +#define O_CREAT 0x0008 /* A file is created if it is not existed */ +#define O_TRUNC 0x0010 /* The file size is changed to 0 if it is existed. */ +#define O_APPEND 0x0020 /* The position is set for next reading/writing */ + /* 0: Top of the file 1: End of file */ + +/* Special character code */ +#define CR 0x0d /* Carriage return */ +#define LF 0x0a /* Line feed */ + +#if defined( __RX ) +const long _nfiles = IOSTREAM; /* The number of files for input/output files */ +#else +const int _nfiles = IOSTREAM; /* The number of files for input/output files */ +#endif +char flmod[IOSTREAM]; /* The location for the mode of opened file. */ + +unsigned char sml_buf[IOSTREAM]; + +#define FPATH_STDIN "C:\\stdin" +#define FPATH_STDOUT "C:\\stdout" +#define FPATH_STDERR "C:\\stderr" + +/* H8 Normal mode ,SH and RX */ +#if defined( __2000N__ ) || defined( __2600N__ ) || defined( __300HN__ ) || defined( _SH ) +/* Output one character to standard output */ +extern void charput(char); +/* Input one character from standard input */ +extern char charget(void); +/* Output one character to the file */ +extern char fcharput(char, unsigned char); +/* Input one character from the file */ +extern char fcharget(char*, unsigned char); +/* Open the file */ +extern char fileopen(char*, unsigned char, unsigned char*); +/* Close the file */ +extern char fileclose(unsigned char); +/* Move the file offset */ +extern char fpseek(unsigned char, long, unsigned char); +/* Get the file offset */ +extern char fptell(unsigned char, long*); + +/* RX */ +#elif defined( __RX ) +/* Output one character to standard output */ +extern void charput(unsigned char); +/* Input one character from standard input */ +extern unsigned char charget(void); + +/* H8 Advanced mode */ +#elif defined( __2000A__ ) || defined( __2600A__ ) || defined( __300HA__ ) || defined( __H8SXN__ ) || defined( __H8SXA__ ) || defined( __H8SXM__ ) || defined( __H8SXX__ ) +/* Output one character to standard output */ +extern void charput(char); +/* Input one character from standard input */ +extern char charget(void); +/* Output one character to the file */ +extern char fcharput(char, unsigned char); +/* Input one character from the file */ +extern char fcharget(char*, unsigned char); +/* Open the file */ +/* Specified as the number of register which stored paramter is 3 */ +extern char __regparam3 fileopen(char*, unsigned char, unsigned char*); +/* Close the file */ +extern char fileclose(unsigned char); +/* Move the file offset */ +extern char fpseek(unsigned char, long, unsigned char); +/* Get the file offset */ +extern char fptell(unsigned char, long*); + +/* H8300 and H8300L */ +#elif defined( __300__ ) || defined( __300L__ ) +/* Output one character to standard output */ +extern void charput(char); +/* Input one character from standard input */ +extern char charget(void); +/* Output one character to the file */ +extern char fcharput(char, unsigned char); +/* Input one character from the file */ +extern char fcharget(char*, unsigned char); +/* Open the file */ +/* Specified as the number of register which stored paramter is 3 */ +extern char __regparam3 fileopen(char*, unsigned char, unsigned char*); +/* Close the file */ +extern char fileclose(unsigned char); +/* Move the file offset */ +/* Move the file offset */ +extern char __regparam3 fpseek(unsigned char, long, unsigned char); +/* Get the file offset */ +extern char fptell(unsigned char, long*); +#endif + +#include +FILE *_Files[IOSTREAM]; // structure for FILE +char *env_list[] = { // Array for environment variables(**environ) + "ENV1=temp01", + "ENV2=temp02", + "ENV9=end", + '\0' // Terminal for environment variables +}; + +char **environ = env_list; + +/****************************************************************************/ +/* _INIT_IOLIB */ +/* Initialize C library Functions, if necessary. */ +/* Define USES_SIMIO on Assembler Option. */ +/****************************************************************************/ +void _INIT_IOLIB( void ) +{ + /* A file for standard input/output is opened or created. Each FILE */ + /* structure members are initialized by the library. Each _Buf member */ + /* in it is re-set the end of buffer pointer. */ + + /* Standard Input File */ + if( freopen( FPATH_STDIN, "r", stdin ) == NULL ) + stdin->_Mode = 0xffff; /* Not allow the access if it fails to open */ + stdin->_Mode = _MOPENR; /* Read only attribute */ + stdin->_Mode |= _MNBF; /* Non-buffering for data */ + stdin->_Bend = stdin->_Buf + 1; /* Re-set pointer to the end of buffer */ + + /* Standard Output File */ + if( freopen( FPATH_STDOUT, "w", stdout ) == NULL ) + stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */ + stdout->_Mode |= _MNBF; /* Non-buffering for data */ + stdout->_Bend = stdout->_Buf + 1;/* Re-set pointer to the end of buffer */ + + /* Standard Error File */ + if( freopen( FPATH_STDERR, "w", stderr ) == NULL ) + stderr->_Mode = 0xffff; /* Not allow the access if it fails to open */ + stderr->_Mode |= _MNBF; /* Non-buffering for data */ + stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */ +} + +/****************************************************************************/ +/* _CLOSEALL */ +/****************************************************************************/ +void _CLOSEALL( void ) +{ + long i; + + for( i=0; i < _nfiles; i++ ) + { + /* Checks if the file is opened or not */ + if( _Files[i]->_Mode & (_MOPENR | _MOPENW | _MOPENA ) ) + fclose( _Files[i] ); /* Closes the file */ + } +} + +/**************************************************************************/ +/* open:file open */ +/* Return value:File number (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +#if defined( __RX ) +long open(const char *name, /* File name */ + long mode, /* Open mode */ + long flg) /* Open flag */ +#else +int open(char *name, /* File name */ + int mode, /* Open mode */ + int flg) /* Open flag */ +#endif +{ + + + if( strcmp( name, FPATH_STDIN ) == 0 ) /* Standard Input file? */ + { + if( ( mode & O_RDONLY ) == 0 ) return -1; + flmod[STDIN] = mode; + return STDIN; + } + else if( strcmp( name, FPATH_STDOUT ) == 0 )/* Standard Output file? */ + { + if( ( mode & O_WRONLY ) == 0 ) return -1; + flmod[STDOUT] = mode; + return STDOUT; + } + else if(strcmp(name, FPATH_STDERR ) == 0 ) /* Standard Error file? */ + { + if( ( mode & O_WRONLY ) == 0 ) return -1; + flmod[STDERR] = mode; + return STDERR; + } + else return -1; /*Others */ +} + +#if defined( __RX ) +long close( long fileno ) +#else +int close( int fileno ) +#endif +{ + return 1; +} + +/**************************************************************************/ +/* write:Data write */ +/* Return value:Number of write characters (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +#if defined( __RX ) +long write(long fileno, /* File number */ + const unsigned char *buf, /* The address of destination buffer */ + long count) /* The number of chacter to write */ +#else +int write(int fileno, /* File number */ + char *buf, /* The address of destination buffer */ + int count) /* The number of chacter to write */ +#endif +{ + long i; /* A variable for counter */ + unsigned char c; /* An output character */ + + /* Checking the mode of file , output each character */ + /* Checking the attribute for Write-Only, Read-Only or Read-Write */ + if(flmod[fileno]&O_WRONLY || flmod[fileno]&O_RDWR) + { + if( fileno == STDIN ) return -1; /* Standard Input */ + else if( (fileno == STDOUT) || (fileno == STDERR) ) + /* Standard Error/output */ + { + for( i = count; i > 0; --i ) + { + c = *buf++; + charput(c); + } + return count; /*Return the number of written characters */ + } + else return -1; /* Incorrect file number */ + } + else return -1; /* An error */ +} + +#if defined( __RX ) +long read( long fileno, unsigned char *buf, long count ) +#else +int read( int fileno, char *buf, unsigned int count ) +#endif +{ + long i; + + /* Checking the file mode with the file number, each character is input and stored the buffer */ + + if((flmod[fileno]&_MOPENR) || (flmod[fileno]&O_RDWR)){ + for(i = count; i > 0; i--){ + *buf = charget(); + if(*buf==CR){ /* Replace the new line character */ + *buf = LF; + } + buf++; + } + return count; + } + else { + return -1; + } +} + +#if defined( __RX ) +long lseek( long fileno, long offset, long base ) +#else +long lseek( int fileno, long offset, int base ) +#endif +{ + return -1L; +} + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/resetprg.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/resetprg.c new file mode 100644 index 000000000..0404ac406 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/resetprg.c @@ -0,0 +1,129 @@ +/***********************************************************************/ +/* */ +/* FILE :resetprg.c */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Reset Program */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX/RX600 +* +* File Name : resetprg.c +* +* Abstract : Reset Program. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include +#include <_h_c_lib.h> +//#include // Remove the comment when you use errno +//#include // Remove the comment when you use rand() +#include "typedefine.h" +#include "stacksct.h" + +#pragma inline_asm Change_PSW_PM_to_UserMode +static void Change_PSW_PM_to_UserMode(void); + +#ifdef __cplusplus +extern "C" { +#endif +void PowerON_Reset_PC(void); +void main(void); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus // Use SIM I/O +extern "C" { +#endif +extern void _INIT_IOLIB(void); +extern void _CLOSEALL(void); +#ifdef __cplusplus +} +#endif + +#define PSW_init 0x00010000 +#define FPSW_init 0x00000100 + +//extern void srand(_UINT); // Remove the comment when you use rand() +//extern _SBYTE *_s1ptr; // Remove the comment when you use strtok() + +//#ifdef __cplusplus // Use Hardware Setup +//extern "C" { +//#endif +//extern void HardwareSetup(void); +//#ifdef __cplusplus +//} +//#endif + +//#ifdef __cplusplus // Remove the comment when you use global class object +//extern "C" { // Sections C$INIT and C$END will be generated +//#endif +//extern void _CALL_INIT(void); +//extern void _CALL_END(void); +//#ifdef __cplusplus +//} +//#endif + +#pragma section ResetPRG + +#pragma entry PowerON_Reset_PC + +void PowerON_Reset_PC(void) +{ + set_intb((unsigned long)__sectop("C$VECT")); + set_fpsw(FPSW_init); + + _INITSCT(); + +// _INIT_IOLIB(); // Remove the comment when you use SIM I/O + +// errno=0; // Remove the comment when you use errno +// srand((_UINT)1); // Remove the comment when you use rand() +// _s1ptr=NULL; // Remove the comment when you use strtok() + +// HardwareSetup(); // Use Hardware Setup + nop(); + +// _CALL_INIT(); // Remove the comment when you use global class object + + set_psw(PSW_init); // Set Ubit & Ibit for PSW +// Change_PSW_PM_to_UserMode(); // DO NOT CHANGE TO USER MODE IF USING FREERTOS! + ( void ) Change_PSW_PM_to_UserMode; // Just to avoid compiler warnings. + + main(); + +// _CLOSEALL(); // Use SIM I/O + +// _CALL_END(); // Remove the comment when you use global class object + + brk(); +} + +static void Change_PSW_PM_to_UserMode(void) +{ + MVFC PSW,R1 + OR #00100000h,R1 + PUSH.L R1 + MVFC PC,R1 + ADD #10,R1 + PUSH.L R1 + RTE + NOP + NOP +} diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/sbrk.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/sbrk.c new file mode 100644 index 000000000..98e5bcbeb --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/sbrk.c @@ -0,0 +1,28 @@ +#include +#include +#define HEAPSIZE 0x400 +signed char *sbrk( size_t size ); +union HEAP_TYPE +{ + signed long dummy; + signed char heap[HEAPSIZE]; +}; +static union HEAP_TYPE heap_area; + +/* End address allocated by sbrk */ +static signed char *brk = ( signed char * ) &heap_area; +signed char *sbrk( size_t size ) +{ + signed char *p; + if( brk + size > heap_area.heap + HEAPSIZE ) + { + p = ( signed char * ) - 1; + } + else + { + p = brk; + brk += size; + } + + return p; +} diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/vecttbl.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/vecttbl.c new file mode 100644 index 000000000..d2dec0b3b --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/vecttbl.c @@ -0,0 +1,64 @@ +/***********************************************************************/ +/* */ +/* FILE :vecttbl.c */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Initialize of Vector Table */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX/RX600 +* +* File Name : vecttbl.c +* +* Abstract : Initialize of Vector Table. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +#include "vect.h" + +#pragma section C FIXEDVECT + +void* const Fixed_Vectors[] = { +//;0xffffffd0 Exception(Supervisor Instruction) + (void*) Excep_SuperVisorInst, +//;0xffffffd4 Reserved + Dummy, +//;0xffffffd8 Reserved + Dummy, +//;0xffffffdc Exception(Undefined Instruction) + (void*) Excep_UndefinedInst, +//;0xffffffe0 Reserved + Dummy, +//;0xffffffe4 Exception(Floating Point) + (void*) Excep_FloatingPoint, +//;0xffffffe8 Reserved + Dummy, +//;0xffffffec Reserved + Dummy, +//;0xfffffff0 Reserved + Dummy, +//;0xfffffff4 Reserved + Dummy, +//;0xfffffff8 NMI + (void*) NonMaskableInterrupt, +//;0xfffffffc RESET +//;<> +//;Power On Reset PC +PowerON_Reset_PC +//;<> +}; diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf new file mode 100644 index 000000000..c831db086 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf @@ -0,0 +1,568 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"FIRST_CONNECTION_TAG" "NO" +"MRULABELS_DATAMANAGER_KEY" "108a|FFFFFFFF|00000000|1054|fff8cd9e|1050|fff8c484|88218|000870B4|000870AE|88204|88208|18b8" +"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_TRUE_STORE_TAG" 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"{00000000-0000-0000-C000-000000000046}" "" +[END] diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Upgrade.txt b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Upgrade.txt new file mode 100644 index 000000000..d4ab49942 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Upgrade.txt @@ -0,0 +1,5 @@ +Project name : RTOSDemo + +Renesas RX Standard Toolchain 1.0.2.0 was upgraded to + Renesas RX Standard Toolchain 1.1.0.0. + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h new file mode 100644 index 000000000..5a49989e1 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h @@ -0,0 +1,62 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/iodefine.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/iodefine.h new file mode 100644 index 000000000..b2ff2a8e4 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/iodefine.h @@ -0,0 +1,10881 @@ + + + + + + + + + + + +/************************************************************************ +* +* Device : RX/RX600/RX630 +* +* File Name : ioedfine.h +* +* Abstract : Definition of I/O Register. +* +* History : 0.50 (2011-03-28) [Hardware Manual Revision : 0.50] +* : 0.10 (2010-10-06) [Hardware Manual Revision : 0.11] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2010(2011) Renesas Electronics Corporation +* and Renesas Solutions Corp. +* +************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX630 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(TPU0,TGI0A) = 0; expands to : */ +/* ICU.IR[126].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(TPU0,TGI0A) = 2; expands to : */ +/* IPR(TPU0,TGI ) = 2; // TGI0A,TGI0B,TGI0C,TGI0D share IPR level. */ +/* ICU.IPR[126].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,RXI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[214].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=142) */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=VECT(TPU0,TGI0A)) expands to : */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=126) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU0,TPU1,TPU2,TPU3,TPU4,TPU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX630IODEFINE_HEADER__ +#define __RX630IODEFINE_HEADER__ +#pragma bit_order left +#pragma unpack +struct st_ad { + unsigned short ADDRA; + unsigned short ADDRB; + unsigned short ADDRC; + unsigned short ADDRD; + unsigned short ADDRE; + unsigned short ADDRF; + unsigned short ADDRG; + unsigned short ADDRH; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ADIE:1; + unsigned char ADST:1; + unsigned char :2; + unsigned char CH:3; + } BIT; + } ADCSR; + union { + unsigned char BYTE; + struct { + unsigned char TRGS:3; + unsigned char :1; + unsigned char CKS:2; + unsigned char MODE:2; + } BIT; + } ADCR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char EXOEN:1; + unsigned char EXSEL:2; + } BIT; + } ADCR2; + unsigned char ADSSTR; + char wk0[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DIAG:2; + } BIT; + } ADDIAGR; +}; + +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short BPEB:2; + unsigned short BPFB:2; + unsigned short :2; + unsigned short BPGB:2; + unsigned short BPIB:2; + unsigned short BPRO:2; + unsigned short BPRA:2; + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS3WCR2; + char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS4WCR2; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS5WCR2; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS6WCR2; + char wk11[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS7WCR2; + char wk12[1926]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS0CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS0REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS1CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS1REC; + char wk16[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS2CR; + char wk17[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS2REC; + char wk18[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS3CR; + char wk19[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS3REC; + char wk20[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS4CR; + char wk21[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS4REC; + char wk22[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS5CR; + char wk23[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS5REC; + char wk24[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS6CR; + char wk25[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS6REC; + char wk26[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS7CR; + char wk27[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS7REC; + char wk28[4]; + union { + unsigned short WORD; + struct { + unsigned short RCVENM7:1; + unsigned short RCVENM6:1; + unsigned short RCVENM5:1; + unsigned short RCVENM4:1; + unsigned short RCVENM3:1; + unsigned short RCVENM2:1; + unsigned short RCVENM1:1; + unsigned short RCVENM0:1; + unsigned short RCVEN7:1; + unsigned short RCVEN6:1; + unsigned short RCVEN5:1; + unsigned short RCVEN4:1; + unsigned short RCVEN3:1; + unsigned short RCVEN2:1; + unsigned short RCVEN1:1; + unsigned short RCVEN0:1; + } BIT; + } CSRECEN; + char wk29[974]; + unsigned char SDSR; +}; + +struct st_can { + struct { + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } ID; + unsigned short DLC; + unsigned char DATA[8]; + unsigned short TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long :3; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR1; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned char MB31:1; + unsigned char MB30:1; + unsigned char MB29:1; + unsigned char MB28:1; + unsigned char MB27:1; + unsigned char MB26:1; + unsigned char MB25:1; + unsigned char MB24:1; + unsigned char MB23:1; + unsigned char MB22:1; + unsigned char MB21:1; + unsigned char MB20:1; + unsigned char MB19:1; + unsigned char MB18:1; + unsigned char MB17:1; + unsigned char MB16:1; + unsigned char MB15:1; + unsigned char MB14:1; + unsigned char MB13:1; + unsigned char MB12:1; + unsigned char MB11:1; + unsigned char MB10:1; + unsigned char MB9:1; + unsigned char MB8:1; + unsigned char MB7:1; + unsigned char MB6:1; + unsigned char MB5:1; + unsigned char MB4:1; + unsigned char MB3:1; + unsigned char MB2:1; + unsigned char MB1:1; + unsigned char MB0:1; + } BIT; + } MKIVLR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned char MB31:1; + unsigned char MB30:1; + unsigned char MB29:1; + unsigned char MB28:1; + unsigned char MB27:1; + unsigned char MB26:1; + unsigned char MB25:1; + unsigned char MB24:1; + unsigned char MB23:1; + unsigned char MB22:1; + unsigned char MB21:1; + unsigned char MB20:1; + unsigned char MB19:1; + unsigned char MB18:1; + unsigned char MB17:1; + unsigned char MB16:1; + unsigned char MB15:1; + unsigned char MB14:1; + unsigned char MB13:1; + unsigned char MB12:1; + unsigned char MB11:1; + unsigned char MB10:1; + unsigned char MB9:1; + unsigned char MB8:1; + unsigned char MB7:1; + unsigned char MB6:1; + unsigned char MB5:1; + unsigned char MB4:1; + unsigned char MB3:1; + unsigned char MB2:1; + unsigned char MB1:1; + unsigned char MB0:1; + } BIT; + } MIER; + char wk0[1008]; + union { + unsigned char BYTE; + union { + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char TRMABT:1; + unsigned char TRMACTIVE:1; + unsigned char SENTDATA:1; + } TX; + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char MSGLOST:1; + unsigned char INVALDATA:1; + unsigned char NEWDATA:1; + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :2; + unsigned char RBOC:1; + unsigned char BOM:2; + unsigned char SLPM:1; + unsigned char CANM:2; + unsigned char TSPS:2; + unsigned char TSRC:1; + unsigned char TPM:1; + unsigned char MLM:1; + unsigned char IDFM:2; + unsigned char MBM:1; + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :1; + unsigned char RECST:1; + unsigned char TRMST:1; + unsigned char BOST:1; + unsigned char EPST:1; + unsigned char SLPST:1; + unsigned char HLTST:1; + unsigned char RSTST:1; + unsigned char EST:1; + unsigned char TABST:1; + unsigned char FMLST:1; + unsigned char NMLST:1; + unsigned char TFST:1; + unsigned char RFST:1; + unsigned char SDST:1; + unsigned char NDST:1; + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long TSEG1:4; + unsigned long :2; + unsigned long BRP:10; + unsigned long :2; + unsigned long SJW:2; + unsigned long :1; + unsigned long TSEG2:3; + unsigned long :7; + unsigned long CCLKS:1; + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + unsigned char RFEST:1; + unsigned char RFWST:1; + unsigned char RFFST:1; + unsigned char RFMLF:1; + unsigned char RFUST:3; + unsigned char RFE:1; + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + unsigned char TFEST:1; + unsigned char TFFST:1; + unsigned char :2; + unsigned char TFUST:3; + unsigned char TFE:1; + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + unsigned char BLIE:1; + unsigned char OLIE:1; + unsigned char ORIE:1; + unsigned char BORIE:1; + unsigned char BOEIE:1; + unsigned char EPIE:1; + unsigned char EWIE:1; + unsigned char BEIE:1; + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + unsigned char BLIF:1; + unsigned char OLIF:1; + unsigned char ORIF:1; + unsigned char BORIF:1; + unsigned char BOEIF:1; + unsigned char EPIF:1; + unsigned char EWIF:1; + unsigned char BEIF:1; + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + unsigned char EDPM:1; + unsigned char ADEF:1; + unsigned char BE0F:1; + unsigned char BE1F:1; + unsigned char CEF:1; + unsigned char AEF:1; + unsigned char FEF:1; + unsigned char SEF:1; + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + unsigned char SEST:1; + unsigned char :2; + unsigned char MBNST:5; + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MBSM:2; + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TSTM:2; + unsigned char TSTE:1; + } BIT; + } TCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char :4; + unsigned char LMS:1; + unsigned char GPS:2; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + unsigned char DAE:1; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + unsigned char DAADST:1; + } BIT; + } DAADSCR; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } DMAST; +}; + +struct st_dmac0 { + unsigned long DMSAR; + unsigned long DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + unsigned long DMSAR; + unsigned long DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + } BIT; + } DTCCR; + char wk0[3]; + unsigned long DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; +}; + +struct st_flash { + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char FLWE:2; + } BIT; + } FWEPROR; + char wk0[7799147]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char FRDMD:1; + } BIT; + } FMODR; + char wk1[13]; + union { + unsigned char BYTE; + struct { + unsigned char ROMAE:1; + unsigned char :2; + unsigned char CMDLK:1; + unsigned char DFLAE:1; + unsigned char :1; + unsigned char DFLRPE:1; + unsigned char DFLWPE:1; + } BIT; + } FASTAT; + union { + unsigned char BYTE; + struct { + unsigned char ROMAEIE:1; + unsigned char :2; + unsigned char CMDLKIE:1; + unsigned char DFLAEIE:1; + unsigned char :1; + unsigned char DFLRPEIE:1; + unsigned char DFLWPEIE:1; + } BIT; + } FAEINT; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRDYIE:1; + } BIT; + } FRDYIE; + char wk2[45]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBRE07:1; + unsigned short DBRE06:1; + unsigned short DBRE05:1; + unsigned short DBRE04:1; + unsigned short DBRE03:1; + unsigned short DBRE02:1; + unsigned short DBRE01:1; + unsigned short DBRE00:1; + } BIT; + } DFLRE0; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBRE15:1; + unsigned short DBRE14:1; + unsigned short DBRE13:1; + unsigned short DBRE12:1; + unsigned short DBRE11:1; + unsigned short DBRE10:1; + unsigned short DBRE09:1; + unsigned short DBRE08:1; + } BIT; + } DFLRE1; + char wk3[12]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBWE07:1; + unsigned short DBW006:1; + unsigned short DBWE05:1; + unsigned short DBWE04:1; + unsigned short DBWE03:1; + unsigned short DBWE02:1; + unsigned short DBWE01:1; + unsigned short DBWE00:1; + } BIT; + } DFLWE0; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short DBWE15:1; + unsigned short DBWE14:1; + unsigned short DBWE13:1; + unsigned short DBWE12:1; + unsigned short DBWE11:1; + unsigned short DBWE10:1; + unsigned short DBWE09:1; + unsigned short DBWE08:1; + } BIT; + } DFLWE1; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :7; + unsigned short FCRME:1; + } BIT; + } FCURAME; + char wk4[15194]; + union { + unsigned char BYTE; + struct { + unsigned char FRDY:1; + unsigned char ILGLERR:1; + unsigned char ERSERR:1; + unsigned char PRGERR:1; + unsigned char SUSRDY:1; + unsigned char :1; + unsigned char ERSSPD:1; + unsigned char PRGSPD:1; + } BIT; + } FSTATR0; + union { + unsigned char BYTE; + struct { + unsigned char FCUERR:1; + unsigned char :2; + unsigned char FLOCKST:1; + } BIT; + } FSTATR1; + union { + unsigned short WORD; + struct { + unsigned short FEKEY:8; + unsigned short FENTRYD:1; + unsigned short :3; + unsigned short FENTRY3:1; + unsigned short FENTRY2:1; + unsigned short FENTRY1:1; + unsigned short FENTRY0:1; + } BIT; + } FENTRYR; + union { + unsigned short WORD; + struct { + unsigned short FPKEY:8; + unsigned short :7; + unsigned short FPROTCN:1; + } BIT; + } FPROTR; + union { + unsigned short WORD; + struct { + unsigned short FRKEY:8; + unsigned short :7; + unsigned short FRESET:1; + } BIT; + } FRESETR; + char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short CMDR:8; + unsigned short PCMDR:8; + } BIT; + } FCMDR; + char wk6[12]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ESUSPMD:1; + } BIT; + } FCPSR; + union { + unsigned short WORD; + struct { + unsigned short BCSIZE:1; + unsigned short :4; + unsigned short BCADR:11; + } BIT; + } DFLBCCNT; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short PEERRST:8; + } BIT; + } FPESTAT; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short BCST:1; + } BIT; + } DFLBCSTAT; + char wk7[24]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short PCKA:8; + } BIT; + } PCKAR; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[254]; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[252]; + char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[254]; + char wk5[2]; + union { + unsigned char BYTE; + struct { + unsigned char DMRS:8; + } BIT; + } DMRSR0; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char DMRS:8; + } BIT; + } DMRSR1; + char wk7[3]; + union { + unsigned char BYTE; + struct { + unsigned char DMRS:8; + } BIT; + } DMRSR2; + char wk8[3]; + union { + unsigned char BYTE; + struct { + unsigned char DMRS:8; + } BIT; + } DMRSR3; + char wk9[243]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + } BIT; + } IRQCR[16]; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN7:1; + unsigned char FLTEN6:1; + unsigned char FLTEN5:1; + unsigned char FLTEN4:1; + unsigned char FLTEN3:1; + unsigned char FLTEN2:1; + unsigned char FLTEN1:1; + unsigned char FLTEN0:1; + } BIT; + } IRQFLTE0; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN15:1; + unsigned char FLTEN14:1; + unsigned char FLTEN13:1; + unsigned char FLTEN12:1; + unsigned char FLTEN11:1; + unsigned char FLTEN10:1; + unsigned char FLTEN9:1; + unsigned char FLTEN8:1; + } BIT; + } IRQFLTE1; + char wk10[2]; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL7:2; + unsigned short FCLKSEL6:2; + unsigned short FCLKSEL5:2; + unsigned short FCLKSEL4:2; + unsigned short FCLKSEL3:2; + unsigned short FCLKSEL2:2; + unsigned short FCLKSEL1:2; + unsigned short FCLKSEL0:2; + } BIT; + } IRQFLTC0; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL15:2; + unsigned short FCLKSEL14:2; + unsigned short FCLKSEL13:2; + unsigned short FCLKSEL12:2; + unsigned short FCLKSEL11:2; + unsigned short FCLKSEL10:2; + unsigned short FCLKSEL9:2; + unsigned short FCLKSEL8:2; + } BIT; + } IRQFLTC1; + char wk11[104]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2ST:1; + unsigned char LVD1ST:1; + unsigned char IWDTST:1; + unsigned char WDTST:1; + unsigned char OSTST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2EN:1; + unsigned char LVD1EN:1; + unsigned char IWDTEN:1; + unsigned char WDTEN:1; + unsigned char OSTEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2CLR:1; + unsigned char LVD1CLR:1; + unsigned char IWDTCLR:1; + unsigned char WDTCLR:1; + unsigned char OSTCLR:1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + } BIT; + } NMICR; + char wk12[12]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char NFLTEN:1; + } BIT; + } NMIFLTE; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char NFCLKSEL:2; + } BIT; + } NMIFLTC; + char wk14[19819]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRP[13]; + char wk15[12]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GEN[13]; + char wk16[12]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long CLR15:1; + unsigned long CLR14:1; + unsigned long CLR13:1; + unsigned long CLR12:1; + unsigned long CLR11:1; + unsigned long CLR10:1; + unsigned long CLR9:1; + unsigned long CLR8:1; + unsigned long CLR7:1; + unsigned long CLR6:1; + unsigned long CLR5:1; + unsigned long CLR4:1; + unsigned long CLR3:1; + unsigned long CLR2:1; + unsigned long CLR1:1; + unsigned long CLR0:1; + } BIT; + } GCR[13]; + char wk17[12]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long CN5:1; + unsigned long CN4:1; + unsigned long CN3:1; + unsigned long CN2:1; + unsigned long CN1:1; + unsigned long CN0:1; + } BIT; + } SEL; +}; + +struct st_ieb { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char IOL:1; + unsigned char DEE:1; + unsigned char :1; + unsigned char RE:1; + } BIT; + } IECTR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMD:3; + } BIT; + } IECMR; + union { + unsigned char BYTE; + struct { + unsigned char SS:1; + unsigned char RN:3; + unsigned char CTL:4; + } BIT; + } IEMCR; + union { + unsigned char BYTE; + struct { + unsigned char IARL4:4; + unsigned char IMD:2; + unsigned char :1; + unsigned char STE:1; + } BIT; + } IEAR1; + union { + unsigned char BYTE; + struct { + unsigned char IARU8:8; + } BIT; + } IEAR2; + union { + unsigned char BYTE; + struct { + unsigned char ISAL4:4; + } BIT; + } IESA1; + union { + unsigned char BYTE; + struct { + unsigned char ISAU8:8; + } BIT; + } IESA2; + union { + unsigned char BYTE; + struct { + unsigned char IBFL:8; + } BIT; + } IETBFL; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char ISAL4:4; + } BIT; + } IEMA1; + union { + unsigned char BYTE; + struct { + unsigned char IMAU8:8; + } BIT; + } IEMA2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RCTL:4; + } BIT; + } IERCTL; + union { + unsigned char BYTE; + struct { + unsigned char RBFL:8; + } BIT; + } IERBFL; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char ILAL8:8; + } BIT; + } IELA1; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char ILAU4:4; + } BIT; + } IELA2; + union { + unsigned char BYTE; + struct { + unsigned char CMX:1; + unsigned char MRQ:1; + unsigned char SRQ:1; + unsigned char SRE:1; + unsigned char LCK:1; + unsigned char :1; + unsigned char RSS:1; + unsigned char GG:1; + } BIT; + } IEFLG; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TXS:1; + unsigned char TXF:1; + unsigned char :1; + unsigned char TXEAL:1; + unsigned char TXETTME:1; + unsigned char TXERO:1; + unsigned char TXEACK:1; + } BIT; + } IETSR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TXSE:1; + unsigned char TXFE:1; + unsigned char :1; + unsigned char TXEALE:1; + unsigned char TXETTMEE:1; + unsigned char TXEROE:1; + unsigned char TXEACKE:1; + } BIT; + } IEIET; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char RXBSY:1; + unsigned char RXS:1; + unsigned char RXF:1; + unsigned char RXEDE:1; + unsigned char RXEOVE:1; + unsigned char RXERTME:1; + unsigned char RXEDLE:1; + unsigned char RXEPE:1; + } BIT; + } IERSR; + union { + unsigned char BYTE; + struct { + unsigned char RXBSYE:1; + unsigned char RXSE:1; + unsigned char RXFE:1; + unsigned char RXEDEE:1; + unsigned char RXEOVEE:1; + unsigned char RXERTMEE:1; + unsigned char RXEDLEE:1; + unsigned char RXEPEE:1; + } BIT; + } IEIER; + char wk3[2]; + union { + unsigned char BYTE; + struct { + unsigned char FLT:1; + unsigned char FCKS:2; + unsigned char CKS3:1; + unsigned char SRSTP:1; + unsigned char CKS:3; + } BIT; + } IECKSR; + char wk4[230]; + unsigned char IETB[33]; + char wk5[223]; + unsigned char IERB[33]; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char SLCSTP:1; + } BIT; + } IWDTCSTPR; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + unsigned char CS7E:1; + unsigned char CS6E:1; + unsigned char CS5E:1; + unsigned char CS4E:1; + unsigned char CS3E:1; + unsigned char CS2E:1; + unsigned char CS1E:1; + unsigned char CS0E:1; + } BIT; + } PFCSE; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CS3S:2; + unsigned char CS2S:2; + unsigned char CS1S:2; + unsigned char :1; + unsigned char CS0S:1; + } BIT; + } PFCSS0; + union { + unsigned char BYTE; + struct { + unsigned char CS7S:2; + unsigned char CS6S:2; + unsigned char CS5S:2; + unsigned char CS4S:2; + } BIT; + } PFCSS1; + union { + unsigned char BYTE; + struct { + unsigned char A15E:1; + unsigned char A14E:1; + unsigned char A13E:1; + unsigned char A12E:1; + unsigned char A11E:1; + unsigned char A10E:1; + unsigned char A9E:1; + unsigned char A8E:1; + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + unsigned char A23E:1; + unsigned char A22E:1; + unsigned char A21E:1; + unsigned char A20E:1; + unsigned char A19E:1; + unsigned char A18E:1; + unsigned char A17E:1; + unsigned char A16E:1; + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + unsigned char WR32BC32E:1; + unsigned char WR1BC1E:1; + unsigned char DH32E:1; + unsigned char DHE:1; + unsigned char :2; + unsigned char ADRHMS:1; + unsigned char ADRLE:1; + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char ALEOE:1; + unsigned char WAITS:2; + } BIT; + } PFBCR1; + char wk1[12]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char PUPHZS:1; + } BIT; + } PFUSB0; + char wk2[10]; + union { + unsigned char BYTE; + struct { + unsigned char B0WI:1; + unsigned char PFSWE:1; + } BIT; + } PWPR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P00PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P01PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P02PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P03PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P05PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P07PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P11PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P52PFS; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P56PFS; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P60PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P61PFS; + char wk9[4]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P66PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P67PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P70PFS; + char wk10[2]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P73PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P74PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P75PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P76PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P77PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P80PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P81PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P82PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P83PFS; + char wk11[2]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P86PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P87PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P92PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P93PFS; + char wk12[4]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PF0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PF1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PF2PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PF5PFS; + char wk14[21]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PJ3PFS; + char wk15[6]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PK2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PK3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PK4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PK5PFS; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BDC:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :6; + unsigned char WRE:1; + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :3; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :1; + unsigned char NFWEN:1; + unsigned char NFVEN:1; + unsigned char NFUEN:1; + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned short POE3F:1; + unsigned short POE2F:1; + unsigned short POE1F:1; + unsigned short POE0F:1; + unsigned short :3; + unsigned short PIE1:1; + unsigned short POE3M:2; + unsigned short POE2M:2; + unsigned short POE1M:2; + unsigned short POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned short OSF1:1; + unsigned short :5; + unsigned short OCE1:1; + unsigned short OIE1:1; + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE8F:1; + unsigned short :2; + unsigned short POE8E:1; + unsigned short PIE2:1; + unsigned short :6; + unsigned short POE8M:2; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CH0HIZ:1; + unsigned char CH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PE3ZE:1; + unsigned char PE2ZE:1; + unsigned char PE1ZE:1; + unsigned char PE0ZE:1; + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char P1CZEA:1; + unsigned char P2CZEA:1; + unsigned char P3CZEA:1; + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short OSTSTF:1; + unsigned short :2; + unsigned short OSTSTE:1; + } BIT; + } ICSR3; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :3; + unsigned char B2:1; + } BIT; + } ODR1; + char wk4[62]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + } BIT; + } DSCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[35]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[58]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :3; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port6 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[37]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[56]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port7 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[38]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[55]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port8 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[39]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[54]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[40]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[53]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[49]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[46]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[47]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portg { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[47]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[46]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porth { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[45]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + } BIT; + } PCR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + } BIT; + } ODR1; + char wk4[44]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + } BIT; + } PCR; +}; + +struct st_portk { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[50]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[43]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_portl { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[51]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[42]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_ppg0 { + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER15:1; + unsigned char NDER14:1; + unsigned char NDER13:1; + unsigned char NDER12:1; + unsigned char NDER11:1; + unsigned char NDER10:1; + unsigned char NDER9:1; + unsigned char NDER8:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER7:1; + unsigned char NDER6:1; + unsigned char NDER5:1; + unsigned char NDER4:1; + unsigned char NDER3:1; + unsigned char NDER2:1; + unsigned char NDER1:1; + unsigned char NDER0:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD15:1; + unsigned char POD14:1; + unsigned char POD13:1; + unsigned char POD12:1; + unsigned char POD11:1; + unsigned char POD10:1; + unsigned char POD9:1; + unsigned char POD8:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD7:1; + unsigned char POD6:1; + unsigned char POD5:1; + unsigned char POD4:1; + unsigned char POD3:1; + unsigned char POD2:1; + unsigned char POD1:1; + unsigned char POD0:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR15:1; + unsigned char NDR14:1; + unsigned char NDR13:1; + unsigned char NDR12:1; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR7:1; + unsigned char NDR6:1; + unsigned char NDR5:1; + unsigned char NDR4:1; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL2; +}; + +struct st_ppg1 { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PTRSL:1; + } BIT; + } PTRSLR; + char wk0[5]; + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER31:1; + unsigned char NDER30:1; + unsigned char NDER29:1; + unsigned char NDER28:1; + unsigned char NDER27:1; + unsigned char NDER26:1; + unsigned char NDER25:1; + unsigned char NDER24:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER23:1; + unsigned char NDER22:1; + unsigned char NDER21:1; + unsigned char NDER20:1; + unsigned char NDER19:1; + unsigned char NDER18:1; + unsigned char NDER17:1; + unsigned char NDER16:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD31:1; + unsigned char POD30:1; + unsigned char POD29:1; + unsigned char POD28:1; + unsigned char POD27:1; + unsigned char POD26:1; + unsigned char POD25:1; + unsigned char POD24:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD23:1; + unsigned char POD22:1; + unsigned char POD21:1; + unsigned char POD20:1; + unsigned char POD19:1; + unsigned char POD18:1; + unsigned char POD17:1; + unsigned char POD16:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR31:1; + unsigned char NDR30:1; + unsigned char NDR29:1; + unsigned char NDR28:1; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR23:1; + unsigned char NDR22:1; + unsigned char NDR21:1; + unsigned char NDR20:1; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL2; +}; + +struct st_riic0 { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char FMPE:1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_riic1 { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSL3P:1; + unsigned char SSL2P:1; + unsigned char SSL1P:1; + unsigned char SSL0P:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :1; + unsigned char SPOM:1; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + unsigned long SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + unsigned char SPR7:1; + unsigned char SPR6:1; + unsigned char SPR5:1; + unsigned char SPR4:1; + unsigned char SPR3:1; + unsigned char SPR2:1; + unsigned char SPR1:1; + unsigned char SPR0:1; + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char SLSEL:2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCNT; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAYW:3; + } BIT; + } RWKCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRCNT; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRAR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAYW:3; + } BIT; + } RWKAR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYAR; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + char wk12[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + } BIT; + } RYRAREN; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char PES:4; + unsigned char :1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char HR24:1; + unsigned char AADJP:1; + unsigned char AADJE:1; + unsigned char RTCOE:1; + unsigned char ADJ30:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RTCEN:1; + } BIT; + } RCR3; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RCKSEL:1; + } BIT; + } RCR4; + char wk17[1]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RFC:1; + } BIT; + } RFRH; + union { + unsigned short WORD; + struct { + unsigned short RFC:16; + } BIT; + } RFRL; + union { + unsigned char BYTE; + struct { + unsigned char PMADJ:2; + unsigned char ADJ:6; + } BIT; + } RADJ; + char wk18[17]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR0; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR1; + char wk20[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR2; + char wk21[13]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP0; + char wk22[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP0; + char wk23[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP0; + char wk24[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DATE10:3; + unsigned char DATE1:4; + } BIT; + } RDAYCP0; + char wk25[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP0; + char wk26[5]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP1; + char wk27[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP1; + char wk28[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP1; + char wk29[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DATE10:3; + unsigned char DATE1:4; + } BIT; + } RDAYCP1; + char wk30[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP1; + char wk31[5]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP2; + char wk32[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP2; + char wk33[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP2; + char wk34[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DATE10:3; + unsigned char DATE1:4; + } BIT; + } RDAYCP2; + char wk35[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP2; +}; + +struct st_s12ad { + union { + unsigned char BYTE; + struct { + unsigned char ADST:1; + unsigned char ADCS:1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char CKS:2; + unsigned char TRGE:1; + unsigned char EXTRG:1; + } BIT; + } ADCSR; + char wk0[3]; + union { + unsigned short WORD; + struct { + unsigned short ANS0:16; + } BIT; + } ADANS0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANS1:5; + } BIT; + } ADANS1; + union { + unsigned short WORD; + struct { + unsigned short ADS0:16; + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ADS1:5; + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char ADC:2; + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :9; + unsigned short ACE:1; + } BIT; + } ADCER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char ADSTRS:4; + } BIT; + } ADSTRGR; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short OCS:1; + unsigned short TSS:1; + unsigned short :6; + unsigned short OCSAD:1; + unsigned short TSSAD:1; + } BIT; + } ADEXICR; + char wk3[6]; + unsigned short ADTSDR; + unsigned short ADOCDR; + char wk4[2]; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + char wk5[38]; + union { + unsigned short WORD; + struct { + unsigned short SST2:8; + } BIT; + } ADSSTR23; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :3; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; +}; + +struct st_sci7 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :3; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :3; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + char wk0[18]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ESME:1; + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char BRME:1; + unsigned char RXDSF:1; + unsigned char SFSF:1; + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + unsigned char PIBS:3; + unsigned char PIBE:1; + unsigned char CF1DS:2; + unsigned char CF0RE:1; + unsigned char BFE:1; + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + unsigned char RTS:2; + unsigned char BCCS:2; + unsigned char :1; + unsigned char DFCS:3; + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SDST:1; + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SHARPS:1; + unsigned char :2; + unsigned char RXDXPS:1; + unsigned char TXDXPS:1; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDIE:1; + unsigned char BCDIE:1; + unsigned char PIBDIE:1; + unsigned char CF1MIE:1; + unsigned char CF0MIE:1; + unsigned char BFDIE:1; + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDF:1; + unsigned char BCDF:1; + unsigned char PIBDF:1; + unsigned char CF1MF:1; + unsigned char CF0MF:1; + unsigned char BFDF:1; + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDCL:1; + unsigned char BCDCL:1; + unsigned char PIBDCL:1; + unsigned char CF1MCL:1; + unsigned char CF0MCL:1; + unsigned char BFDCL:1; + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + unsigned char CF0CE7:1; + unsigned char CF0CE6:1; + unsigned char CF0CE5:1; + unsigned char CF0CE4:1; + unsigned char CF0CE3:1; + unsigned char CF0CE2:1; + unsigned char CF0CE1:1; + unsigned char CF0CE0:1; + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + unsigned char CF1CE7:1; + unsigned char CF1CE6:1; + unsigned char CF1CE5:1; + unsigned char CF1CE4:1; + unsigned char CF1CE3:1; + unsigned char CF1CE2:1; + unsigned char CF1CE1:1; + unsigned char CF1CE0:1; + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCST:1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TCSS:3; + unsigned char TWRC:1; + unsigned char :1; + unsigned char TOMS:2; + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_smci0 { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BCLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; +}; + +struct st_smci7 { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BCLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :3; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short MD:1; + } BIT; + } MDMONR; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short UBTS:1; + unsigned short BOTS:1; + unsigned short :2; + unsigned short EXB:1; + unsigned short IROM:1; + } BIT; + } MDSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short EXBE:1; + unsigned short ROME:1; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RAME:1; + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + unsigned short OPE:1; + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long ACSE:1; + unsigned long :1; + unsigned long MSTPA29:1; + unsigned long MSTPA28:1; + unsigned long MSTPA27:1; + unsigned long :2; + unsigned long MSTPA24:1; + unsigned long MSTPA23:1; + unsigned long :3; + unsigned long MSTPA19:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long :1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long MSTPA13:1; + unsigned long MSTPA12:1; + unsigned long MSTPA11:1; + unsigned long MSTPA10:1; + unsigned long MSTPA9:1; + unsigned long :3; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long MSTPB29:1; + unsigned long MSTPB28:1; + unsigned long MSTPB27:1; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long MSTPB24:1; + unsigned long MSTPB23:1; + unsigned long :1; + unsigned long MSTPB21:1; + unsigned long MSTPB20:1; + unsigned long MSTPB19:1; + unsigned long :1; + unsigned long MSTPB17:1; + unsigned long MSTPB16:1; + unsigned long :7; + unsigned long MSTPB8:1; + unsigned long :3; + unsigned long MSTPB4:1; + unsigned long :1; + unsigned long MSTPB2:1; + unsigned long MSTPB1:1; + unsigned long MSTPB0:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long MSTPC27:1; + unsigned long MSTPC26:1; + unsigned long MSTPC25:1; + unsigned long MSTPC24:1; + unsigned long :1; + unsigned long MSTPC22:1; + unsigned long :2; + unsigned long MSTPC19:1; + unsigned long MSTPC18:1; + unsigned long MSTPC17:1; + unsigned long MSTPC16:1; + unsigned long :14; + unsigned long MSTPC1:1; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long FCK:4; + unsigned long ICK:4; + unsigned long PSTOP1:1; + unsigned long :3; + unsigned long BCK:4; + unsigned long :4; + unsigned long PCKB:4; + } BIT; + } SCKCR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short UCK:4; + unsigned short IEBCK:4; + } BIT; + } SCKCR2; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CKSEL:3; + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short STC:6; + unsigned short :6; + unsigned short PLIDIV:2; + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PLLEN:1; + } BIT; + } PLLCR2; + char wk4[5]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCLKDIV:1; + } BIT; + } BCKCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MOSTP:1; + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SOSTP:1; + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LCSTP:1; + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ILCSTP:1; + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HCSTP:1; + } BIT; + } HOCOCR; + char wk6[9]; + union { + unsigned char BYTE; + struct { + unsigned char OSTDE:1; + unsigned char :6; + unsigned char OSTDIE:1; + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char OSTDF:1; + } BIT; + } OSTDSR; + char wk7[94]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char OPCMTSF:1; + unsigned char :1; + unsigned char OPCM:3; + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + unsigned char RSTCKEN:1; + unsigned char :4; + unsigned char RSTCKSEL:3; + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MSTS:5; + } BIT; + } MOSCWTCR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SSTS:5; + } BIT; + } SOSCWTCR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSTS:5; + } BIT; + } PLLWTCR; + char wk9[25]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SWRF:1; + unsigned char WDTRF:1; + unsigned char IWTDRF:1; + } BIT; + } RSTSR2; + char wk10[1]; + unsigned short SWRR; + char wk11[28]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD1IDTSEL:2; + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD1MON:1; + unsigned char LVD1DET:1; + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD2IDTSEL:2; + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD2MON:1; + unsigned char LVD2DET:1; + } BIT; + } LVD2SR; + char wk12[794]; + union { + unsigned short WORD; + struct { + unsigned short PRKEY:8; + unsigned short :4; + unsigned short PRC3:1; + unsigned short :1; + unsigned short PRC1:1; + unsigned short PRC0:1; + } BIT; + } PRCR; + char wk13[48768]; + union { + unsigned char BYTE; + struct { + unsigned char DPSBY:1; + unsigned char IOKEEP:1; + unsigned char :4; + unsigned char DEEPCUT:2; + } BIT; + } DPSBYCR; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7E:1; + unsigned char DIRQ6E:1; + unsigned char DIRQ5E:1; + unsigned char DIRQ4E:1; + unsigned char DIRQ3E:1; + unsigned char DIRQ2E:1; + unsigned char DIRQ1E:1; + unsigned char DIRQ0E:1; + } BIT; + } DPSIER0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15E:1; + unsigned char DIRQ14E:1; + unsigned char DIRQ13E:1; + unsigned char DIRQ12E:1; + unsigned char DIRQ11E:1; + unsigned char DIRQ10E:1; + unsigned char DIRQ9E:1; + unsigned char DIRQ8E:1; + } BIT; + } DPSIER1; + union { + unsigned char BYTE; + struct { + unsigned char DUSBIE:1; + unsigned char DIICCIE:1; + unsigned char DIICDIE:1; + unsigned char DNMIE:1; + unsigned char DRTCAIE:1; + unsigned char DRTCIIE:1; + unsigned char DLVD2IE:1; + unsigned char DLVD1IE:1; + } BIT; + } DPSIER2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIE:1; + } BIT; + } DPSIER3; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7F:1; + unsigned char DIRQ6F:1; + unsigned char DIRQ5F:1; + unsigned char DIRQ4F:1; + unsigned char DIRQ3F:1; + unsigned char DIRQ2F:1; + unsigned char DIRQ1F:1; + unsigned char DIRQ0F:1; + } BIT; + } DPSIFR0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15F:1; + unsigned char DIRQ14F:1; + unsigned char DIRQ13F:1; + unsigned char DIRQ12F:1; + unsigned char DIRQ11F:1; + unsigned char DIRQ10F:1; + unsigned char DIRQ9F:1; + unsigned char DIRQ8F:1; + } BIT; + } DPSIFR1; + union { + unsigned char BYTE; + struct { + unsigned char DUSBIF:1; + unsigned char DIICCIF:1; + unsigned char DIICDIF:1; + unsigned char DNMIF:1; + unsigned char DRTCAIF:1; + unsigned char DRTCIIF:1; + unsigned char DLVD2IF:1; + unsigned char DLVD1IF:1; + } BIT; + } DPSIFR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIF:1; + } BIT; + } DPSIFR3; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7EG:1; + unsigned char DIRQ6EG:1; + unsigned char DIRQ5EG:1; + unsigned char DIRQ4EG:1; + unsigned char DIRQ3EG:1; + unsigned char DIRQ2EG:1; + unsigned char DIRQ1EG:1; + unsigned char DIRQ0EG:1; + } BIT; + } DPSIEGR0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15EG:1; + unsigned char DIRQ14EG:1; + unsigned char DIRQ13EG:1; + unsigned char DIRQ12EG:1; + unsigned char DIRQ11EG:1; + unsigned char DIRQ10EG:1; + unsigned char DIRQ9EG:1; + unsigned char DIRQ8EG:1; + } BIT; + } DPSIEGR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DIICCEG:1; + unsigned char DIICDEG:1; + unsigned char DNMIEG:1; + unsigned char :2; + unsigned char DLVD2EG:1; + unsigned char DLVD1EG:1; + } BIT; + } DPSIEGR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIEG:1; + } BIT; + } DPSIEGR3; + char wk15[2]; + union { + unsigned char BYTE; + struct { + unsigned char DPSRSTF:1; + unsigned char :3; + unsigned char LVD2RF:1; + unsigned char LVD1RF:1; + unsigned char LVD0RF:1; + unsigned char PORF:1; + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CWSF:1; + } BIT; + } RSTSR1; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MOFXIN:1; + } BIT; + } MOFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HOCOPCNT:1; + } BIT; + } HOCOPCR; + char wk17[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LVD2E:1; + unsigned char LVD1E:1; + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char LVD2LVL:4; + unsigned char LVD1LVL:4; + } BIT; + } LVDLVLR; + char wk18[1]; + union { + unsigned char BYTE; + struct { + unsigned char LVD1RN:1; + unsigned char LVD1RI:1; + unsigned char LVD1FSAMP:2; + unsigned char :1; + unsigned char LVD1CMPE:1; + unsigned char LVD1DFDIS:1; + unsigned char LVD1RIE:1; + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + unsigned char LVD2RN:1; + unsigned char LVD2RI:1; + unsigned char LVD2FSAMP:2; + unsigned char :1; + unsigned char LVD2CMPE:1; + unsigned char LVD2DFDIS:1; + unsigned char LVD2RIE:1; + } BIT; + } LVD2CR0; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char VBATTMNSEL:1; + } BIT; + } VBATTMNSELR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char VBATTMON:1; + } BIT; + } VBATTMONR; + char wk20[1]; + unsigned char DPSBKR[32]; + char wk21[1472]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SCK:2; + } BIT; + } SCK1; + char wk22[15]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SCK:2; + } BIT; + } SCK2; +}; + +struct st_temps { + union { + unsigned char BYTE; + struct { + unsigned char TSEN:1; + unsigned char :2; + unsigned char TSOE:1; + } BIT; + } TSCR; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADTE:1; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_tpu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu4 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpua { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CST5:1; + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SYNC5:1; + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; +}; + +struct st_tpub { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CST11:1; + unsigned char CST10:1; + unsigned char CST9:1; + unsigned char CST8:1; + unsigned char CST7:1; + unsigned char CST6:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SYNC11:1; + unsigned char SYNC10:1; + unsigned char SYNC9:1; + unsigned char SYNC8:1; + unsigned char SYNC7:1; + unsigned char SYNC6:1; + } BIT; + } TSYR; +}; + +struct st_usb { + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DVBSTS0:1; + unsigned long :5; + unsigned long DM0:1; + unsigned long DP0:1; + unsigned long :11; + unsigned long FIXPHY0:1; + unsigned long :3; + unsigned long SRPC0:1; + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DVBINT0:1; + unsigned long :6; + unsigned long DPINT0:1; + unsigned long :8; + unsigned long DVBSE0:1; + unsigned long :6; + unsigned long DPINTE0:1; + } BIT; + } DPUSR1R; +}; + +struct st_usb0 { + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SCKE:1; + unsigned short :5; + unsigned short DPRPU:1; + unsigned short :3; + unsigned short USBE:1; + } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short WKUP:1; + unsigned short :5; + unsigned short RHST:3; + } BIT; + } DVSTCTR0; + char wk2[10]; + unsigned short CFIFO; + char wk3[2]; + unsigned short D0FIFO; + char wk4[2]; + unsigned short D1FIFO; + char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short :3; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :2; + unsigned short ISEL:1; + unsigned short :1; + unsigned short CURPIPE:4; + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short VBSE:1; + unsigned short RSME:1; + unsigned short SOFE:1; + unsigned short DVSE:1; + unsigned short CTRE:1; + unsigned short BEMPE:1; + unsigned short NRDYE:1; + unsigned short BRDYE:1; + } BIT; + } INTENB0; + char wk7[4]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short EDGESTS:1; + } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short VBINT:1; + unsigned short RESM:1; + unsigned short SOFR:1; + unsigned short DVST:1; + unsigned short CTRT:1; + unsigned short BEMP:1; + unsigned short NRDY:1; + unsigned short BRDY:1; + unsigned short VBSTS:1; + unsigned short DVSQ:3; + unsigned short VALID:1; + unsigned short CTSQ:3; + } BIT; + } INTSTS0; + char wk9[4]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BENP:1; + unsigned short PIPE6BENP:1; + unsigned short PIPE5BENP:1; + unsigned short PIPE4BENP:1; + unsigned short PIPE3BENP:1; + unsigned short PIPE2BENP:1; + unsigned short PIPE1BENP:1; + unsigned short PIPE0BENP:1; + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + unsigned short OVRN:1; + unsigned short CRCE:1; + unsigned short :3; + unsigned short FRNM:11; + } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short DVCHG:1; + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short STSRECOV:4; + unsigned short :1; + unsigned short USBADDR:7; + } BIT; + } USBADDR; + char wk10[2]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SHTNAK:1; + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short MXPS:7; + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :6; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :2; + unsigned short CCPL:1; + unsigned short PID:2; + } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short PIPESEL:4; + } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short TYPE:2; + unsigned short :3; + unsigned short BFRE:1; + unsigned short DBLB:1; + unsigned short :1; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short EPNUM:4; + } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short MXPS:9; + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short IFIS:1; + unsigned short :9; + unsigned short IITV:3; + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; +}; + +struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + } BIT; + } WDTRCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FIFERR=21, +IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMT2_CMI2, +IR_CMT3_CMI3, +IR_USB0_D0FIFO0=33,IR_USB0_D1FIFO0,IR_USB0_USBI0,IR_USB0_D0FIFO1,IR_USB0_D1FIFO1,IR_USB0_USBI1, +IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,IR_RSPI1_SPII1, +IR_RSPI2_SPRI2,IR_RSPI2_SPTI2,IR_RSPI2_SPII2, +IR_CAN0_RXF0,IR_CAN0_TXF0,IR_CAN0_RXM0,IR_CAN0_TXM0, +IR_CAN1_RXF1,IR_CAN1_TXF1,IR_CAN1_RXM1,IR_CAN1_TXM1, +IR_CAN2_RXF2,IR_CAN2_TXF2,IR_CAN2_RXM2,IR_CAN2_TXM2, +IR_RTC_COUNTUP=62, +IR_ICU_IRQ0=64,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_USB_USBR0=90, +IR_RTC_ALARM=92,IR_RTC_PRD, +IR_AD0_ADI0=98, +IR_S12AD0_S12ADI0=102, +IR_ICU_GROUPE0=106,IR_ICU_GROUPE1,IR_ICU_GROUPE2,IR_ICU_GROUPE3,IR_ICU_GROUPE4,IR_ICU_GROUPE5,IR_ICU_GROUPE6,IR_ICU_GROUPL0=114, +IR_SCIX_SCIX0=122,IR_SCIX_SCIX1,IR_SCIX_SCIX2,IR_SCIX_SCIX3, +IR_TPU0_TGI0A,IR_TPU0_TGI0B,IR_TPU0_TGI0C,IR_TPU0_TGI0D, +IR_TPU1_TGI1A,IR_TPU1_TGI1B, +IR_TPU2_TGI2A,IR_TPU2_TGI2B, +IR_TPU3_TGI3A,IR_TPU3_TGI3B,IR_TPU3_TGI3C,IR_TPU3_TGI3D, +IR_TPU4_TGI4A,IR_TPU4_TGI4B, +IR_TPU5_TGI5A,IR_TPU5_TGI5B, +IR_TPU6_TGI6A,IR_TPU6_TGI6B,IR_TPU6_TGI6C,IR_TPU6_TGI6D, +IR_MTU0_TGIA0=142,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_TPU7_TGI7A,IR_TPU7_TGI7B, +IR_MTU1_TGIA1=148,IR_MTU1_TGIB1, +IR_TPU8_TGI8A,IR_TPU8_TGI8B, +IR_MTU2_TGIA2=150,IR_MTU2_TGIB2, +IR_TPU9_TGI9A,IR_TPU9_TGI9B,IR_TPU9_TGI9C,IR_TPU9_TGI9D, +IR_MTU3_TGIA3=152,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3, +IR_TPU10_TGI10A,IR_TPU10_TGI10B, +IR_MTU4_TGIA4=156,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_TPU11_TGI11A,IR_TPU11_TGI11B, +IR_POE_OEI1,IR_POE_OEI2, +IR_TMR0_CMIA0=170,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0, +IR_RIIC1_EEI1,IR_RIIC1_RXI1,IR_RIIC1_TXI1,IR_RIIC1_TEI1, +IR_RIIC2_EEI2,IR_RIIC2_RXI2,IR_RIIC2_TXI2,IR_RIIC2_TEI2, +IR_RIIC3_EEI3,IR_RIIC3_RXI3,IR_RIIC3_TXI3,IR_RIIC3_TEI3, +IR_DMAC_DMAC0I,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I, +IR_SCI0_RXI0=214,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2, +IR_SCI3_RXI3,IR_SCI3_TXI3,IR_SCI3_TEI3, +IR_SCI4_RXI4,IR_SCI4_TXI4,IR_SCI4_TEI4, +IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI7_RXI7,IR_SCI7_TXI7,IR_SCI7_TEI7, +IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI10_RXI10,IR_SCI10_TXI10,IR_SCI10_TEI10, +IR_SCI11_RXI11,IR_SCI11_TXI11,IR_SCI11_TEI11, +IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12, +IR_IEB_IEBINT +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2, +DTCE_CMT3_CMI3, +DTCE_USB0_D0FIFO0=33,DTCE_USB0_D1FIFO0,DTCE_USB0_D0FIFO1=36,DTCE_USB0_D1FIFO1, +DTCE_RSPI0_SPRI0=39,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1=42,DTCE_RSPI1_SPTI1, +DTCE_RSPI2_SPRI2=45,DTCE_RSPI2_SPTI2, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_AD0_ADI0=98, +DTCE_S12AD0_S12ADI0=102, +DTCE_TPU0_TGI0A=126,DTCE_TPU0_TGI0B,DTCE_TPU0_TGI0C,DTCE_TPU0_TGI0D, +DTCE_TPU1_TGI1A,DTCE_TPU1_TGI1B, +DTCE_TPU2_TGI2A,DTCE_TPU2_TGI2B, +DTCE_TPU3_TGI3A,DTCE_TPU3_TGI3B,DTCE_TPU3_TGI3C,DTCE_TPU3_TGI3D, +DTCE_TPU4_TGI4A,DTCE_TPU4_TGI4B, +DTCE_TPU5_TGI5A,DTCE_TPU5_TGI5B, +DTCE_TPU6_TGI6A,DTCE_TPU6_TGI6B,DTCE_TPU6_TGI6C,DTCE_TPU6_TGI6D, +DTCE_MTU0_TGIA0=142,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_TPU7_TGI7A=148,DTCE_TPU7_TGI7B, +DTCE_MTU1_TGIA1=148,DTCE_MTU1_TGIB1, +DTCE_TPU8_TGI8A,DTCE_TPU8_TGI8B, +DTCE_MTU2_TGIA2=150,DTCE_MTU2_TGIB2, +DTCE_TPU9_TGI9A,DTCE_TPU9_TGI9B,DTCE_TPU9_TGI9C,DTCE_TPU9_TGI9D, +DTCE_MTU3_TGIA3=152,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_TPU10_TGI10A,DTCE_TPU10_TGI10B, +DTCE_MTU4_TGIA4=156,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TPU11_TGI11A,DTCE_TPU11_TGI11B, +DTCE_TMR0_CMIA0=170,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=173,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=176,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=179,DTCE_TMR3_CMIB3, +DTCE_RIIC0_RXI0=183,DTCE_RIIC0_TXI0, +DTCE_RIIC1_RXI1=187,DTCE_RIIC1_TXI1, +DTCE_RIIC2_RXI2=191,DTCE_RIIC2_TXI2, +DTCE_RIIC3_RXI3=195,DTCE_RIIC3_TXI3, +DTCE_DMAC_DMAC0I=198,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_SCI0_RXI0=214,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=217,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2=220,DTCE_SCI2_TXI2, +DTCE_SCI3_RXI3=223,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4=226,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5=229,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=232,DTCE_SCI6_TXI6, +DTCE_SCI7_RXI7=235,DTCE_SCI7_TXI7, +DTCE_SCI8_RXI8=238,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=241,DTCE_SCI9_TXI9, +DTCE_SCI10_RXI10=244,DTCE_SCI10_TXI10, +DTCE_SCI11_RXI11=247,DTCE_SCI11_TXI11, +DTCE_SCI12_RXI12=250,DTCE_SCI12_TXI12 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03, +IER_CMT3_CMI3=0x03, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,IER_USB0_D0FIFO1=0x04,IER_USB0_D1FIFO1=0x04,IER_USB0_USBI1=0x04, +IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSPI1_SPRI1=0x05,IER_RSPI1_SPTI1=0x05,IER_RSPI1_SPII1=0x05, +IER_RSPI2_SPRI2=0x05,IER_RSPI2_SPTI2=0x05,IER_RSPI2_SPII2=0x05, +IER_CAN0_RXF0=0x06,IER_CAN0_TXF0=0x06,IER_CAN0_RXM0=0x06,IER_CAN0_TXM0=0x06, +IER_CAN1_RXF1=0x06,IER_CAN1_TXF1=0x06,IER_CAN1_RXM1=0x06,IER_CAN1_TXM1=0x06, +IER_CAN2_RXF2=0x07,IER_CAN2_TXF2=0x07,IER_CAN2_RXM2=0x07,IER_CAN2_TXM2=0x07, +IER_RTC_COUNTUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_USB_USBR0=0x0B, +IER_RTC_ALARM=0x0B,IER_RTC_PRD=0x0B, +IER_AD0_ADI0=0x0C, +IER_S12AD0_S12ADI0=0x0C, +IER_ICU_GROUPE0=0x0D,IER_ICU_GROUPE1=0x0D,IER_ICU_GROUPE2=0x0D,IER_ICU_GROUPE3=0x0D,IER_ICU_GROUPE4=0x0D,IER_ICU_GROUPE5=0x0D,IER_ICU_GROUPE6=0x0E,IER_ICU_GROUPL0=0x0E, +IER_SCIX_SCIX0=0x0F,IER_SCIX_SCIX1=0x0F,IER_SCIX_SCIX2=0x0F,IER_SCIX_SCIX3=0x0F, +IER_TPU0_TGI0A=0x0F,IER_TPU0_TGI0B=0x0F,IER_TPU0_TGI0C=0x10,IER_TPU0_TGI0D=0x10, +IER_TPU1_TGI1A=0x10,IER_TPU1_TGI1B=0x10, +IER_TPU2_TGI2A=0x10,IER_TPU2_TGI2B=0x10, +IER_TPU3_TGI3A=0x10,IER_TPU3_TGI3B=0x10,IER_TPU3_TGI3C=0x11,IER_TPU3_TGI3D=0x11, +IER_TPU4_TGI4A=0x11,IER_TPU4_TGI4B=0x11, +IER_TPU5_TGI5A=0x11,IER_TPU5_TGI5B=0x11, +IER_TPU6_TGI6A=0x11,IER_TPU6_TGI6B=0x11,IER_TPU6_TGI6C=0x12,IER_TPU6_TGI6D=0x12, +IER_MTU0_TGIA0=0x11,IER_MTU0_TGIB0=0x11,IER_MTU0_TGIC0=0x12,IER_MTU0_TGID0=0x12,IER_MTU0_TGIE0=0x12,IER_MTU0_TGIF0=0x12, +IER_TPU7_TGI7A=0x12,IER_TPU7_TGI7B=0x12, +IER_MTU1_TGIA1=0x12,IER_MTU1_TGIB1=0x12, +IER_TPU8_TGI8A=0x12,IER_TPU8_TGI8B=0x12, +IER_MTU2_TGIA2=0x12,IER_MTU2_TGIB2=0x12, +IER_TPU9_TGI9A=0x13,IER_TPU9_TGI9B=0x13,IER_TPU9_TGI9C=0x13,IER_TPU9_TGI9D=0x13, +IER_MTU3_TGIA3=0x13,IER_MTU3_TGIB3=0x13,IER_MTU3_TGIC3=0x13,IER_MTU3_TGID3=0x13, +IER_TPU10_TGI10A=0x13,IER_TPU10_TGI10B=0x13, +IER_MTU4_TGIA4=0x13,IER_MTU4_TGIB4=0x13,IER_MTU4_TGIC4=0x13,IER_MTU4_TGID4=0x13,IER_MTU4_TCIV4=0x14, +IER_MTU5_TGIU5=0x14,IER_MTU5_TGIV5=0x14,IER_MTU5_TGIW5=0x14, +IER_TPU11_TGI11A=0x14,IER_TPU11_TGI11B=0x14, +IER_POE_OEI1=0x14,IER_POE_OEI2=0x14, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x15, +IER_TMR1_CMIA1=0x15,IER_TMR1_CMIB1=0x15,IER_TMR1_OVI1=0x15, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x16,IER_TMR3_OVI3=0x16, +IER_RIIC0_EEI0=0x16,IER_RIIC0_RXI0=0x16,IER_RIIC0_TXI0=0x17,IER_RIIC0_TEI0=0x17, +IER_RIIC1_EEI1=0x17,IER_RIIC1_RXI1=0x17,IER_RIIC1_TXI1=0x17,IER_RIIC1_TEI1=0x17, +IER_RIIC2_EEI2=0x17,IER_RIIC2_RXI2=0x17,IER_RIIC2_TXI2=0x18,IER_RIIC2_TEI2=0x18, +IER_RIIC3_EEI3=0x18,IER_RIIC3_RXI3=0x18,IER_RIIC3_TXI3=0x18,IER_RIIC3_TEI3=0x18, +IER_DMAC_DMAC0I=0x18,IER_DMAC_DMAC1I=0x18,IER_DMAC_DMAC2I=0x19,IER_DMAC_DMAC3I=0x19, +IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1A,IER_SCI0_TEI0=0x1B, +IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI2_RXI2=0x1B,IER_SCI2_TXI2=0x1B,IER_SCI2_TEI2=0x1B, +IER_SCI3_RXI3=0x1B,IER_SCI3_TXI3=0x1C,IER_SCI3_TEI3=0x1C, +IER_SCI4_RXI4=0x1C,IER_SCI4_TXI4=0x1C,IER_SCI4_TEI4=0x1C, +IER_SCI5_RXI5=0x1C,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_RXI6=0x1D,IER_SCI6_TXI6=0x1D,IER_SCI6_TEI6=0x1D, +IER_SCI7_RXI7=0x1D,IER_SCI7_TXI7=0x1D,IER_SCI7_TEI7=0x1D, +IER_SCI8_RXI8=0x1D,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1E, +IER_SCI9_RXI9=0x1E,IER_SCI9_TXI9=0x1E,IER_SCI9_TEI9=0x1E, +IER_SCI10_RXI10=0x1E,IER_SCI10_TXI10=0x1E,IER_SCI10_TEI10=0x1E, +IER_SCI11_RXI11=0x1E,IER_SCI11_TXI11=0x1F,IER_SCI11_TEI11=0x1F, +IER_SCI12_RXI12=0x1F,IER_SCI12_TXI12=0x1F,IER_SCI12_TEI12=0x1F, +IER_IEB_IEBINT=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMT2_CMI2=6, +IPR_CMT3_CMI3=7, +IPR_USB0_D0FIFO0=33,IPR_USB0_D1FIFO0=34,IPR_USB0_USBI0=35,IPR_USB0_D0FIFO1=36,IPR_USB0_D1FIFO1=37,IPR_USB0_USBI1=38, +IPR_RSPI0_SPRI0=39,IPR_RSPI0_SPTI0=39,IPR_RSPI0_SPII0=39, +IPR_RSPI1_SPRI1=42,IPR_RSPI1_SPTI1=42,IPR_RSPI1_SPII1=42, +IPR_RSPI2_SPRI2=45,IPR_RSPI2_SPTI2=45,IPR_RSPI2_SPII2=45, +IPR_CAN0_RXF0=48,IPR_CAN0_TXF0=48,IPR_CAN0_RXM0=48,IPR_CAN0_TXM0=48, +IPR_CAN1_RXF1=52,IPR_CAN1_TXF1=52,IPR_CAN1_RXM1=52,IPR_CAN1_TXM1=52, +IPR_CAN2_RXF2=56,IPR_CAN2_TXF2=56,IPR_CAN2_RXM2=56,IPR_CAN2_TXM2=56, +IPR_RTC_COUNTUP=62, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79, +IPR_USB_USBR0=90, +IPR_RTC_ALARM=92,IPR_RTC_PRD=93, +IPR_AD0_ADI0=98, +IPR_S12AD0_S12ADI0=102, +IPR_ICU_GROUPE0=106,IPR_ICU_GROUPE1=107,IPR_ICU_GROUPE2=108,IPR_ICU_GROUPE3=109,IPR_ICU_GROUPE4=110,IPR_ICU_GROUPE5=111,IPR_ICU_GROUPE6=112,IPR_ICU_GROUPL0=114, +IPR_SCIX_SCIX0=122,IPR_SCIX_SCIX1=122,IPR_SCIX_SCIX2=122,IPR_SCIX_SCIX3=122, +IPR_TPU0_TGI0A=126,IPR_TPU0_TGI0B=126,IPR_TPU0_TGI0C=126,IPR_TPU0_TGI0D=126, +IPR_TPU1_TGI1A=130,IPR_TPU1_TGI1B=130, +IPR_TPU2_TGI2A=132,IPR_TPU2_TGI2B=132, +IPR_TPU3_TGI3A=134,IPR_TPU3_TGI3B=134,IPR_TPU3_TGI3C=134,IPR_TPU3_TGI3D=134, +IPR_TPU4_TGI4A=138,IPR_TPU4_TGI4B=138, +IPR_TPU5_TGI5A=140,IPR_TPU5_TGI5B=140, +IPR_TPU6_TGI6A=142,IPR_TPU6_TGI6B=142,IPR_TPU6_TGI6C=142,IPR_TPU6_TGI6D=142, +IPR_MTU0_TGIA0=142,IPR_MTU0_TGIB0=142,IPR_MTU0_TGIC0=142,IPR_MTU0_TGID0=142,IPR_MTU0_TGIE0=146,IPR_MTU0_TGIF0=146, +IPR_TPU7_TGI7A=148,IPR_TPU7_TGI7B=148, +IPR_MTU1_TGIA1=148,IPR_MTU1_TGIB1=148, +IPR_TPU8_TGI8A=150,IPR_TPU8_TGI8B=150, +IPR_MTU2_TGIA2=150,IPR_MTU2_TGIB2=150, +IPR_TPU9_TGI9A=152,IPR_TPU9_TGI9B=152,IPR_TPU9_TGI9C=152,IPR_TPU9_TGI9D=152, +IPR_MTU3_TGIA3=152,IPR_MTU3_TGIB3=152,IPR_MTU3_TGIC3=152,IPR_MTU3_TGID3=152, +IPR_TPU10_TGI10A=156,IPR_TPU10_TGI10B=156, +IPR_MTU4_TGIA4=156,IPR_MTU4_TGIB4=156,IPR_MTU4_TGIC4=156,IPR_MTU4_TGID4=156,IPR_MTU4_TCIV4=160, +IPR_MTU5_TGIU5=161,IPR_MTU5_TGIV5=161,IPR_MTU5_TGIW5=161, +IPR_TPU11_TGI11A=164,IPR_TPU11_TGI11B=164, +IPR_POE_OEI1=166,IPR_POE_OEI2=166, +IPR_TMR0_CMIA0=170,IPR_TMR0_CMIB0=170,IPR_TMR0_OVI0=170, +IPR_TMR1_CMIA1=173,IPR_TMR1_CMIB1=173,IPR_TMR1_OVI1=173, +IPR_TMR2_CMIA2=176,IPR_TMR2_CMIB2=176,IPR_TMR2_OVI2=176, +IPR_TMR3_CMIA3=179,IPR_TMR3_CMIB3=179,IPR_TMR3_OVI3=179, +IPR_RIIC0_EEI0=182,IPR_RIIC0_RXI0=183,IPR_RIIC0_TXI0=184,IPR_RIIC0_TEI0=185, +IPR_RIIC1_EEI1=186,IPR_RIIC1_RXI1=187,IPR_RIIC1_TXI1=188,IPR_RIIC1_TEI1=189, +IPR_RIIC2_EEI2=190,IPR_RIIC2_RXI2=191,IPR_RIIC2_TXI2=192,IPR_RIIC2_TEI2=193, +IPR_RIIC3_EEI3=194,IPR_RIIC3_RXI3=195,IPR_RIIC3_TXI3=196,IPR_RIIC3_TEI3=197, +IPR_DMAC_DMAC0I=198,IPR_DMAC_DMAC1I=199,IPR_DMAC_DMAC2I=200,IPR_DMAC_DMAC3I=201, +IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214, +IPR_SCI1_RXI1=217,IPR_SCI1_TXI1=217,IPR_SCI1_TEI1=217, +IPR_SCI2_RXI2=220,IPR_SCI2_TXI2=220,IPR_SCI2_TEI2=220, +IPR_SCI3_RXI3=223,IPR_SCI3_TXI3=223,IPR_SCI3_TEI3=223, +IPR_SCI4_RXI4=226,IPR_SCI4_TXI4=226,IPR_SCI4_TEI4=226, +IPR_SCI5_RXI5=229,IPR_SCI5_TXI5=229,IPR_SCI5_TEI5=229, +IPR_SCI6_RXI6=232,IPR_SCI6_TXI6=232,IPR_SCI6_TEI6=232, +IPR_SCI7_RXI7=235,IPR_SCI7_TXI7=235,IPR_SCI7_TEI7=235, +IPR_SCI8_RXI8=238,IPR_SCI8_TXI8=238,IPR_SCI8_TEI8=238, +IPR_SCI9_RXI9=241,IPR_SCI9_TXI9=241,IPR_SCI9_TEI9=241, +IPR_SCI10_RXI10=244,IPR_SCI10_TXI10=244,IPR_SCI10_TEI10=244, +IPR_SCI11_RXI11=247,IPR_SCI11_TXI11=247,IPR_SCI11_TEI11=247, +IPR_SCI12_RXI12=250,IPR_SCI12_TXI12=250,IPR_SCI12_TEI12=250, +IPR_IEB_IEBINT=253, +IPR_BSC_=0, +IPR_CMT0_=4, +IPR_CMT1_=5, +IPR_CMT2_=6, +IPR_CMT3_=7, +IPR_RSPI0_=39, +IPR_RSPI1_=42, +IPR_RSPI2_=45, +IPR_CAN0_=48, +IPR_CAN1_=52, +IPR_CAN2_=56, +IPR_USB_=90, +IPR_AD0_=98, +IPR_S12AD0_=102, +IPR_SCIX_=122, +IPR_SCIX_SCI=122, +IPR_TPU0_=126, +IPR_TPU0_TGI=126, +IPR_TPU1_=130, +IPR_TPU1_TGI=130, +IPR_TPU2_=132, +IPR_TPU2_TGI=132, +IPR_TPU3_=134, +IPR_TPU3_TGI=134, +IPR_TPU4_=138, +IPR_TPU4_TGI=138, +IPR_TPU5_=140, +IPR_TPU5_TGI=140, +IPR_MTU5_=161, +IPR_MTU5_TGI=161, +IPR_TPU11_=164, +IPR_TPU11_TGI=164, +IPR_POE_=166, +IPR_POE_OEI=166, +IPR_TMR0_=170, +IPR_TMR1_=173, +IPR_TMR2_=176, +IPR_TMR3_=179, +IPR_SCI0_=214, +IPR_SCI1_=217, +IPR_SCI2_=220, +IPR_SCI3_=223, +IPR_SCI4_=226, +IPR_SCI5_=229, +IPR_SCI6_=232, +IPR_SCI7_=235, +IPR_SCI8_=238, +IPR_SCI9_=241, +IPR_SCI10_=244, +IPR_SCI11_=247, +IPR_SCI12_=250, +IPR_IEB_=253 +}; + +enum enum_grp { +GRP_CAN0_ERS0=0,GRP_CAN1_ERS1=0,GRP_CAN2_ERS2=0, +GRP_MTU0_TCIV0=1,GRP_MTU1_TCIV1=1,GRP_MTU1_TCIU1=1, +GRP_MTU2_TCIV2=2,GRP_MTU2_TCIU2=2,GRP_MTU3_TCIV3=2, +GRP_TPU0_TCI0V=3,GRP_TPU1_TCI1V=3,GRP_TPU1_TCI1U=3,GRP_TPU5_TCI5V=3,GRP_TPU5_TCI5U=3, +GRP_TPU2_TCI2V=4,GRP_TPU2_TCI2U=4,GRP_TPU3_TCI3V=4,GRP_TPU4_TCI4V=4,GRP_TPU4_TCI4U=4, +GRP_TPU6_TCI6V=5,GRP_TPU7_TCI7V=5,GRP_TPU7_TCI7U=5,GRP_TPU11_TCI11V=5,GRP_TPU11_TCI11U=5, +GRP_TPU8_TCI8V=6,GRP_TPU8_TCI8U=6,GRP_TPU9_TCI9V=6,GRP_TPU10_TCI10V=6,GRP_TPU10_TCI10U=6, +GRP_SCI0_ERI0=12,GRP_SCI1_ERI1=12,GRP_SCI2_ERI2=12,GRP_SCI3_ERI3=12,GRP_SCI4_ERI4=12,GRP_SCI5_ERI5=12,GRP_SCI6_ERI6=12, +GRP_SCI7_ERI7=12,GRP_SCI8_ERI8=12,GRP_SCI9_ERI9=12,GRP_SCI10_ERI10=12,GRP_SCI11_ERI11=12,GRP_SCI12_ERI12=12, +GRP_RSPI0_SPEI0=12,GRP_RSPI1_SPEI1=12,GRP_RSPI2_SPEI2=12 +}; + +enum enum_gen { +GEN_CAN0_ERS0=0,GEN_CAN1_ERS1=0,GEN_CAN2_ERS2=0, +GEN_MTU0_TCIV0=1,GEN_MTU1_TCIV1=1,GEN_MTU1_TCIU1=1, +GEN_MTU2_TCIV2=2,GEN_MTU2_TCIU2=2,GEN_MTU3_TCIV3=2, +GEN_TPU0_TCI0V=3,GEN_TPU1_TCI1V=3,GEN_TPU1_TCI1U=3,GEN_TPU5_TCI5V=3,GEN_TPU5_TCI5U=3, +GEN_TPU2_TCI2V=4,GEN_TPU2_TCI2U=4,GEN_TPU3_TCI3V=4,GEN_TPU4_TCI4V=4,GEN_TPU4_TCI4U=4, +GEN_TPU6_TCI6V=5,GEN_TPU7_TCI7V=5,GEN_TPU7_TCI7U=5,GEN_TPU11_TCI11V=5,GEN_TPU11_TCI11U=5, +GEN_TPU8_TCI8V=6,GEN_TPU8_TCI8U=6,GEN_TPU9_TCI9V=6,GEN_TPU10_TCI10V=6,GEN_TPU10_TCI10U=6, +GEN_SCI0_ERI0=12,GEN_SCI1_ERI1=12,GEN_SCI2_ERI2=12,GEN_SCI3_ERI3=12,GEN_SCI4_ERI4=12,GEN_SCI5_ERI5=12,GEN_SCI6_ERI6=12, +GEN_SCI7_ERI7=12,GEN_SCI8_ERI8=12,GEN_SCI9_ERI9=12,GEN_SCI10_ERI10=12,GEN_SCI11_ERI11=12,GEN_SCI12_ERI12=12, +GEN_RSPI0_SPEI0=12,GEN_RSPI1_SPEI1=12,GEN_RSPI2_SPEI2=12 +}; + +enum enum_gcr { +GCR_CAN0_ERS0=0,GCR_CAN1_ERS1=0,GCR_CAN2_ERS2=0, +GCR_MTU0_TCIV0=1,GCR_MTU1_TCIV1=1,GCR_MTU1_TCIU1=1, +GCR_MTU2_TCIV2=2,GCR_MTU2_TCIU2=2,GCR_MTU3_TCIV3=2, +GCR_TPU0_TCI0V=3,GCR_TPU1_TCI1V=3,GCR_TPU1_TCI1U=3,GCR_TPU5_TCI5V=3,GCR_TPU5_TCI5U=3, +GCR_TPU2_TCI2V=4,GCR_TPU2_TCI2U=4,GCR_TPU3_TCI3V=4,GCR_TPU4_TCI4V=4,GCR_TPU4_TCI4U=4, +GCR_TPU6_TCI6V=5,GCR_TPU7_TCI7V=5,GCR_TPU7_TCI7U=5,GCR_TPU11_TCI11V=5,GCR_TPU11_TCI11U=5, +GCR_TPU8_TCI8V=6,GCR_TPU8_TCI8U=6,GCR_TPU9_TCI9V=6,GCR_TPU10_TCI10V=6,GCR_TPU10_TCI10U=6, +GCR_SCI0_ERI0=12,GCR_SCI1_ERI1=12,GCR_SCI2_ERI2=12,GCR_SCI3_ERI3=12,GCR_SCI4_ERI4=12,GCR_SCI5_ERI5=12,GCR_SCI6_ERI6=12, +GCR_SCI7_ERI7=12,GCR_SCI8_ERI8=12,GCR_SCI9_ERI9=12,GCR_SCI10_ERI10=12,GCR_SCI11_ERI11=12,GCR_SCI12_ERI12=12, +GCR_RSPI0_SPEI0=12,GCR_RSPI1_SPEI1=12,GCR_RSPI2_SPEI2=12 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_USB0_D0FIFO0 IEN1 +#define IEN_USB0_D1FIFO0 IEN2 +#define IEN_USB0_USBI0 IEN3 +#define IEN_USB0_D0FIFO1 IEN4 +#define IEN_USB0_D1FIFO1 IEN5 +#define IEN_USB0_USBI1 IEN6 +#define IEN_RSPI0_SPRI0 IEN7 +#define IEN_RSPI0_SPTI0 IEN0 +#define IEN_RSPI0_SPII0 IEN1 +#define IEN_RSPI1_SPRI1 IEN2 +#define IEN_RSPI1_SPTI1 IEN3 +#define IEN_RSPI1_SPII1 IEN4 +#define IEN_RSPI2_SPRI2 IEN5 +#define IEN_RSPI2_SPTI2 IEN6 +#define IEN_RSPI2_SPII2 IEN7 +#define IEN_CAN0_RXF0 IEN0 +#define IEN_CAN0_TXF0 IEN1 +#define IEN_CAN0_RXM0 IEN2 +#define IEN_CAN0_TXM0 IEN3 +#define IEN_CAN1_RXF1 IEN4 +#define IEN_CAN1_TXF1 IEN5 +#define IEN_CAN1_RXM1 IEN6 +#define IEN_CAN1_TXM1 IEN7 +#define IEN_CAN2_RXF2 IEN0 +#define IEN_CAN2_TXF2 IEN1 +#define IEN_CAN2_RXM2 IEN2 +#define IEN_CAN2_TXM2 IEN3 +#define IEN_RTC_COUNTUP IEN6 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_USB_USBR0 IEN2 +#define IEN_RTC_ALARM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_AD0_ADI0 IEN2 +#define IEN_S12AD0_S12ADI0 IEN6 +#define IEN_ICU_GROUPE0 IEN2 +#define IEN_ICU_GROUPE1 IEN3 +#define IEN_ICU_GROUPE2 IEN4 +#define IEN_ICU_GROUPE3 IEN5 +#define IEN_ICU_GROUPE4 IEN6 +#define IEN_ICU_GROUPE5 IEN7 +#define IEN_ICU_GROUPE6 IEN0 +#define IEN_ICU_GROUPL0 IEN2 +#define IEN_SCIX_SCIX0 IEN2 +#define IEN_SCIX_SCIX1 IEN3 +#define IEN_SCIX_SCIX2 IEN4 +#define IEN_SCIX_SCIX3 IEN5 +#define IEN_TPU0_TGI0A IEN6 +#define IEN_TPU0_TGI0B IEN7 +#define IEN_TPU0_TGI0C IEN0 +#define IEN_TPU0_TGI0D IEN1 +#define IEN_TPU1_TGI1A IEN2 +#define IEN_TPU1_TGI1B IEN3 +#define IEN_TPU2_TGI2A IEN4 +#define IEN_TPU2_TGI2B IEN5 +#define IEN_TPU3_TGI3A IEN6 +#define IEN_TPU3_TGI3B IEN7 +#define IEN_TPU3_TGI3C IEN0 +#define IEN_TPU3_TGI3D IEN1 +#define IEN_TPU4_TGI4A IEN2 +#define IEN_TPU4_TGI4B IEN3 +#define IEN_TPU5_TGI5A IEN4 +#define IEN_TPU5_TGI5B IEN5 +#define IEN_TPU6_TGI6A IEN6 +#define IEN_TPU6_TGI6B IEN7 +#define IEN_TPU6_TGI6C IEN0 +#define IEN_TPU6_TGI6D IEN1 +#define IEN_MTU0_TGIA0 IEN6 +#define IEN_MTU0_TGIB0 IEN7 +#define IEN_MTU0_TGIC0 IEN0 +#define IEN_MTU0_TGID0 IEN1 +#define IEN_MTU0_TGIE0 IEN2 +#define IEN_MTU0_TGIF0 IEN3 +#define IEN_TPU7_TGI7A IEN4 +#define IEN_TPU7_TGI7B IEN5 +#define IEN_MTU1_TGIA1 IEN4 +#define IEN_MTU1_TGIB1 IEN5 +#define IEN_TPU8_TGI8A IEN6 +#define IEN_TPU8_TGI8B IEN7 +#define IEN_MTU2_TGIA2 IEN6 +#define IEN_MTU2_TGIB2 IEN7 +#define IEN_TPU9_TGI9A IEN0 +#define IEN_TPU9_TGI9B IEN1 +#define IEN_TPU9_TGI9C IEN2 +#define IEN_TPU9_TGI9D IEN3 +#define IEN_MTU3_TGIA3 IEN0 +#define IEN_MTU3_TGIB3 IEN1 +#define IEN_MTU3_TGIC3 IEN2 +#define IEN_MTU3_TGID3 IEN3 +#define IEN_TPU10_TGI10A IEN4 +#define IEN_TPU10_TGI10B IEN5 +#define IEN_MTU4_TGIA4 IEN4 +#define IEN_MTU4_TGIB4 IEN5 +#define IEN_MTU4_TGIC4 IEN6 +#define IEN_MTU4_TGID4 IEN7 +#define IEN_MTU4_TCIV4 IEN0 +#define IEN_MTU5_TGIU5 IEN1 +#define IEN_MTU5_TGIV5 IEN2 +#define IEN_MTU5_TGIW5 IEN3 +#define IEN_TPU11_TGI11A IEN4 +#define IEN_TPU11_TGI11B IEN5 +#define IEN_POE_OEI1 IEN6 +#define IEN_POE_OEI2 IEN7 +#define IEN_TMR0_CMIA0 IEN2 +#define IEN_TMR0_CMIB0 IEN3 +#define IEN_TMR0_OVI0 IEN4 +#define IEN_TMR1_CMIA1 IEN5 +#define IEN_TMR1_CMIB1 IEN6 +#define IEN_TMR1_OVI1 IEN7 +#define IEN_TMR2_CMIA2 IEN0 +#define IEN_TMR2_CMIB2 IEN1 +#define IEN_TMR2_OVI2 IEN2 +#define IEN_TMR3_CMIA3 IEN3 +#define IEN_TMR3_CMIB3 IEN4 +#define IEN_TMR3_OVI3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 +#define IEN_RIIC1_EEI1 IEN2 +#define IEN_RIIC1_RXI1 IEN3 +#define IEN_RIIC1_TXI1 IEN4 +#define IEN_RIIC1_TEI1 IEN5 +#define IEN_RIIC2_EEI2 IEN6 +#define IEN_RIIC2_RXI2 IEN7 +#define IEN_RIIC2_TXI2 IEN0 +#define IEN_RIIC2_TEI2 IEN1 +#define IEN_RIIC3_EEI3 IEN2 +#define IEN_RIIC3_RXI3 IEN3 +#define IEN_RIIC3_TXI3 IEN4 +#define IEN_RIIC3_TEI3 IEN5 +#define IEN_DMAC_DMAC0I IEN6 +#define IEN_DMAC_DMAC1I IEN7 +#define IEN_DMAC_DMAC2I IEN0 +#define IEN_DMAC_DMAC3I IEN1 +#define IEN_SCI0_RXI0 IEN6 +#define IEN_SCI0_TXI0 IEN7 +#define IEN_SCI0_TEI0 IEN0 +#define IEN_SCI1_RXI1 IEN1 +#define IEN_SCI1_TXI1 IEN2 +#define IEN_SCI1_TEI1 IEN3 +#define IEN_SCI2_RXI2 IEN4 +#define IEN_SCI2_TXI2 IEN5 +#define IEN_SCI2_TEI2 IEN6 +#define IEN_SCI3_RXI3 IEN7 +#define IEN_SCI3_TXI3 IEN0 +#define IEN_SCI3_TEI3 IEN1 +#define IEN_SCI4_RXI4 IEN2 +#define IEN_SCI4_TXI4 IEN3 +#define IEN_SCI4_TEI4 IEN4 +#define IEN_SCI5_RXI5 IEN5 +#define IEN_SCI5_TXI5 IEN6 +#define IEN_SCI5_TEI5 IEN7 +#define IEN_SCI6_RXI6 IEN0 +#define IEN_SCI6_TXI6 IEN1 +#define IEN_SCI6_TEI6 IEN2 +#define IEN_SCI7_RXI7 IEN3 +#define IEN_SCI7_TXI7 IEN4 +#define IEN_SCI7_TEI7 IEN5 +#define IEN_SCI8_RXI8 IEN6 +#define IEN_SCI8_TXI8 IEN7 +#define IEN_SCI8_TEI8 IEN0 +#define IEN_SCI9_RXI9 IEN1 +#define IEN_SCI9_TXI9 IEN2 +#define IEN_SCI9_TEI9 IEN3 +#define IEN_SCI10_RXI10 IEN4 +#define IEN_SCI10_TXI10 IEN5 +#define IEN_SCI10_TEI10 IEN6 +#define IEN_SCI11_RXI11 IEN7 +#define IEN_SCI11_TXI11 IEN0 +#define IEN_SCI11_TEI11 IEN1 +#define IEN_SCI12_RXI12 IEN2 +#define IEN_SCI12_TXI12 IEN3 +#define IEN_SCI12_TEI12 IEN4 +#define IEN_IEB_IEBINT IEN5 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_USB0_D0FIFO0 33 +#define VECT_USB0_D1FIFO0 34 +#define VECT_USB0_USBI0 35 +#define VECT_USB0_D0FIFO1 36 +#define VECT_USB0_D1FIFO1 37 +#define VECT_USB0_USBI1 38 +#define VECT_RSPI0_SPRI0 39 +#define VECT_RSPI0_SPTI0 40 +#define VECT_RSPI0_SPII0 41 +#define VECT_RSPI1_SPRI1 42 +#define VECT_RSPI1_SPTI1 43 +#define VECT_RSPI1_SPII1 44 +#define VECT_RSPI2_SPRI2 45 +#define VECT_RSPI2_SPTI2 46 +#define VECT_RSPI2_SPII2 47 +#define VECT_CAN0_RXF0 48 +#define VECT_CAN0_TXF0 49 +#define VECT_CAN0_RXM0 50 +#define VECT_CAN0_TXM0 51 +#define VECT_CAN1_RXF1 52 +#define VECT_CAN1_TXF1 53 +#define VECT_CAN1_RXM1 54 +#define VECT_CAN1_TXM1 55 +#define VECT_CAN2_RXF2 56 +#define VECT_CAN2_TXF2 57 +#define VECT_CAN2_RXM2 58 +#define VECT_CAN2_TXM2 59 +#define VECT_RTC_COUNTUP 62 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_USB_USBR0 90 +#define VECT_RTC_ALARM 92 +#define VECT_RTC_PRD 93 +#define VECT_AD0_ADI0 98 +#define VECT_S12AD0_S12ADI0 102 +#define VECT_ICU_GROUPE0 106 +#define VECT_ICU_GROUPE1 107 +#define VECT_ICU_GROUPE2 108 +#define VECT_ICU_GROUPE3 109 +#define VECT_ICU_GROUPE4 110 +#define VECT_ICU_GROUPE5 111 +#define VECT_ICU_GROUPE6 112 +#define VECT_ICU_GROUPL0 114 +#define VECT_SCIX_SCIX0 122 +#define VECT_SCIX_SCIX1 123 +#define VECT_SCIX_SCIX2 124 +#define VECT_SCIX_SCIX3 125 +#define VECT_TPU0_TGI0A 126 +#define VECT_TPU0_TGI0B 127 +#define VECT_TPU0_TGI0C 128 +#define VECT_TPU0_TGI0D 129 +#define VECT_TPU1_TGI1A 130 +#define VECT_TPU1_TGI1B 131 +#define VECT_TPU2_TGI2A 132 +#define VECT_TPU2_TGI2B 133 +#define VECT_TPU3_TGI3A 134 +#define VECT_TPU3_TGI3B 135 +#define VECT_TPU3_TGI3C 136 +#define VECT_TPU3_TGI3D 137 +#define VECT_TPU4_TGI4A 138 +#define VECT_TPU4_TGI4B 139 +#define VECT_TPU5_TGI5A 140 +#define VECT_TPU5_TGI5B 141 +#define VECT_TPU6_TGI6A 142 +#define VECT_TPU6_TGI6B 143 +#define VECT_TPU6_TGI6C 144 +#define VECT_TPU6_TGI6D 145 +#define VECT_MTU0_TGIA0 142 +#define VECT_MTU0_TGIB0 143 +#define VECT_MTU0_TGIC0 144 +#define VECT_MTU0_TGID0 145 +#define VECT_MTU0_TGIE0 146 +#define VECT_MTU0_TGIF0 147 +#define VECT_TPU7_TGI7A 148 +#define VECT_TPU7_TGI7B 149 +#define VECT_MTU1_TGIA1 148 +#define VECT_MTU1_TGIB1 149 +#define VECT_TPU8_TGI8A 150 +#define VECT_TPU8_TGI8B 151 +#define VECT_MTU2_TGIA2 150 +#define VECT_MTU2_TGIB2 151 +#define VECT_TPU9_TGI9A 152 +#define VECT_TPU9_TGI9B 153 +#define VECT_TPU9_TGI9C 154 +#define VECT_TPU9_TGI9D 155 +#define VECT_MTU3_TGIA3 152 +#define VECT_MTU3_TGIB3 153 +#define VECT_MTU3_TGIC3 154 +#define VECT_MTU3_TGID3 155 +#define VECT_TPU10_TGI10A 156 +#define VECT_TPU10_TGI10B 157 +#define VECT_MTU4_TGIA4 156 +#define VECT_MTU4_TGIB4 157 +#define VECT_MTU4_TGIC4 158 +#define VECT_MTU4_TGID4 159 +#define VECT_MTU4_TCIV4 160 +#define VECT_MTU5_TGIU5 161 +#define VECT_MTU5_TGIV5 162 +#define VECT_MTU5_TGIW5 163 +#define VECT_TPU11_TGI11A 164 +#define VECT_TPU11_TGI11B 165 +#define VECT_POE_OEI1 166 +#define VECT_POE_OEI2 167 +#define VECT_TMR0_CMIA0 170 +#define VECT_TMR0_CMIB0 171 +#define VECT_TMR0_OVI0 172 +#define VECT_TMR1_CMIA1 173 +#define VECT_TMR1_CMIB1 174 +#define VECT_TMR1_OVI1 175 +#define VECT_TMR2_CMIA2 176 +#define VECT_TMR2_CMIB2 177 +#define VECT_TMR2_OVI2 178 +#define VECT_TMR3_CMIA3 179 +#define VECT_TMR3_CMIB3 180 +#define VECT_TMR3_OVI3 181 +#define VECT_RIIC0_EEI0 182 +#define VECT_RIIC0_RXI0 183 +#define VECT_RIIC0_TXI0 184 +#define VECT_RIIC0_TEI0 185 +#define VECT_RIIC1_EEI1 186 +#define VECT_RIIC1_RXI1 187 +#define VECT_RIIC1_TXI1 188 +#define VECT_RIIC1_TEI1 189 +#define VECT_RIIC2_EEI2 190 +#define VECT_RIIC2_RXI2 191 +#define VECT_RIIC2_TXI2 192 +#define VECT_RIIC2_TEI2 193 +#define VECT_RIIC3_EEI3 194 +#define VECT_RIIC3_RXI3 195 +#define VECT_RIIC3_TXI3 196 +#define VECT_RIIC3_TEI3 197 +#define VECT_DMAC_DMAC0I 198 +#define VECT_DMAC_DMAC1I 199 +#define VECT_DMAC_DMAC2I 200 +#define VECT_DMAC_DMAC3I 201 +#define VECT_SCI0_RXI0 214 +#define VECT_SCI0_TXI0 215 +#define VECT_SCI0_TEI0 216 +#define VECT_SCI1_RXI1 217 +#define VECT_SCI1_TXI1 218 +#define VECT_SCI1_TEI1 219 +#define VECT_SCI2_RXI2 220 +#define VECT_SCI2_TXI2 221 +#define VECT_SCI2_TEI2 222 +#define VECT_SCI3_RXI3 223 +#define VECT_SCI3_TXI3 224 +#define VECT_SCI3_TEI3 225 +#define VECT_SCI4_RXI4 226 +#define VECT_SCI4_TXI4 227 +#define VECT_SCI4_TEI4 228 +#define VECT_SCI5_RXI5 229 +#define VECT_SCI5_TXI5 230 +#define VECT_SCI5_TEI5 231 +#define VECT_SCI6_RXI6 232 +#define VECT_SCI6_TXI6 233 +#define VECT_SCI6_TEI6 234 +#define VECT_SCI7_RXI7 235 +#define VECT_SCI7_TXI7 236 +#define VECT_SCI7_TEI7 237 +#define VECT_SCI8_RXI8 238 +#define VECT_SCI8_TXI8 239 +#define VECT_SCI8_TEI8 240 +#define VECT_SCI9_RXI9 241 +#define VECT_SCI9_TXI9 242 +#define VECT_SCI9_TEI9 243 +#define VECT_SCI10_RXI10 244 +#define VECT_SCI10_TXI10 245 +#define VECT_SCI10_TEI10 246 +#define VECT_SCI11_RXI11 247 +#define VECT_SCI11_TXI11 248 +#define VECT_SCI11_TEI11 249 +#define VECT_SCI12_RXI12 250 +#define VECT_SCI12_TXI12 251 +#define VECT_SCI12_TEI12 252 +#define VECT_IEB_IEBINT 253 + +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_AD SYSTEM.MSTPCRA.BIT.MSTPA23 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU6 SYSTEM.MSTPCRA.BIT.MSTPA12 +#define MSTP_TPU7 SYSTEM.MSTPCRA.BIT.MSTPA12 +#define MSTP_TPU8 SYSTEM.MSTPCRA.BIT.MSTPA12 +#define MSTP_TPU9 SYSTEM.MSTPCRA.BIT.MSTPA12 +#define MSTP_TPU10 SYSTEM.MSTPCRA.BIT.MSTPA12 +#define MSTP_TPU11 SYSTEM.MSTPCRA.BIT.MSTPA12 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_CAN2 SYSTEM.MSTPCRB.BIT.MSTPB2 +#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SMCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_SMCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_RSPI2 SYSTEM.MSTPCRC.BIT.MSTPC22 +#define MSTP_LVD SYSTEM.MSTPCRC.BIT.MSTPC20 +#define MSTP_IEB SYSTEM.MSTPCRC.BIT.MSTPC18 +#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17 +#define MSTP_RIIC3 SYSTEM.MSTPCRC.BIT.MSTPC16 +#define MSTP_RAM1 SYSTEM.MSTPCRC.BIT.MSTPC1 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 + +#define IS_CAN0_ERS0 IS0 +#define IS_CAN1_ERS1 IS1 +#define IS_CAN2_ERS2 IS2 +#define IS_MTU0_TCIV0 IS0 +#define IS_MTU1_TCIV1 IS1 +#define IS_MTU1_TCIU1 IS2 +#define IS_MTU2_TCIV2 IS0 +#define IS_MTU2_TCIU2 IS1 +#define IS_MTU3_TCIV3 IS2 +#define IS_TPU0_TCI0V IS0 +#define IS_TPU1_TCI1V IS1 +#define IS_TPU1_TCI1U IS2 +#define IS_TPU5_TCI5V IS3 +#define IS_TPU5_TCI5U IS4 +#define IS_TPU2_TCI2V IS0 +#define IS_TPU2_TCI2U IS1 +#define IS_TPU3_TCI3V IS2 +#define IS_TPU4_TCI4V IS3 +#define IS_TPU4_TCI4U IS4 +#define IS_TPU6_TCI6V IS0 +#define IS_TPU7_TCI7V IS1 +#define IS_TPU7_TCI7U IS2 +#define IS_TPU11_TCI11V IS3 +#define IS_TPU11_TCI11U IS4 +#define IS_TPU8_TCI8V IS0 +#define IS_TPU8_TCI8U IS1 +#define IS_TPU9_TCI9V IS2 +#define IS_TPU10_TCI10V IS3 +#define IS_TPU10_TCI10U IS4 +#define IS_SCI0_ERI0 IS0 +#define IS_SCI1_ERI1 IS1 +#define IS_SCI2_ERI2 IS2 +#define IS_SCI3_ERI3 IS3 +#define IS_SCI4_ERI4 IS4 +#define IS_SCI5_ERI5 IS5 +#define IS_SCI6_ERI6 IS6 +#define IS_SCI7_ERI7 IS7 +#define IS_SCI8_ERI8 IS8 +#define IS_SCI9_ERI9 IS9 +#define IS_SCI10_ERI10 IS10 +#define IS_SCI11_ERI11 IS11 +#define IS_SCI12_ERI12 IS12 +#define IS_RSPI0_SPEI0 IS13 +#define IS_RSPI1_SPEI1 IS14 +#define IS_RSPI2_SPEI2 IS15 + +#define EN_CAN0_ERS0 EN0 +#define EN_CAN1_ERS1 EN1 +#define EN_CAN2_ERS2 EN2 +#define EN_MTU0_TCIV0 EN0 +#define EN_MTU1_TCIV1 EN1 +#define EN_MTU1_TCIU1 EN2 +#define EN_MTU2_TCIV2 EN0 +#define EN_MTU2_TCIU2 EN1 +#define EN_MTU3_TCIV3 EN2 +#define EN_TPU0_TCI0V EN0 +#define EN_TPU1_TCI1V EN1 +#define EN_TPU1_TCI1U EN2 +#define EN_TPU5_TCI5V EN3 +#define EN_TPU5_TCI5U EN4 +#define EN_TPU2_TCI2V EN0 +#define EN_TPU2_TCI2U EN1 +#define EN_TPU3_TCI3V EN2 +#define EN_TPU4_TCI4V EN3 +#define EN_TPU4_TCI4U EN4 +#define EN_TPU6_TCI6V EN0 +#define EN_TPU7_TCI7V EN1 +#define EN_TPU7_TCI7U EN2 +#define EN_TPU11_TCI11V EN3 +#define EN_TPU11_TCI11U EN4 +#define EN_TPU8_TCI8V EN0 +#define EN_TPU8_TCI8U EN1 +#define EN_TPU9_TCI9V EN2 +#define EN_TPU10_TCI10V EN3 +#define EN_TPU10_TCI10U EN4 +#define EN_SCI0_ERI0 EN0 +#define EN_SCI1_ERI1 EN1 +#define EN_SCI2_ERI2 EN2 +#define EN_SCI3_ERI3 EN3 +#define EN_SCI4_ERI4 EN4 +#define EN_SCI5_ERI5 EN5 +#define EN_SCI6_ERI6 EN6 +#define EN_SCI7_ERI7 EN7 +#define EN_SCI8_ERI8 EN8 +#define EN_SCI9_ERI9 EN9 +#define EN_SCI10_ERI10 EN10 +#define EN_SCI11_ERI11 EN11 +#define EN_SCI12_ERI12 EN12 +#define EN_RSPI0_SPEI0 EN13 +#define EN_RSPI1_SPEI1 EN14 +#define EN_RSPI2_SPEI2 EN15 + +#define CLR_CAN0_ERS0 CLR0 +#define CLR_CAN1_ERS1 CLR1 +#define CLR_CAN2_ERS2 CLR2 +#define CLR_MTU0_TCIV0 CLR0 +#define CLR_MTU1_TCIV1 CLR1 +#define CLR_MTU1_TCIU1 CLR2 +#define CLR_MTU2_TCIV2 CLR0 +#define CLR_MTU2_TCIU2 CLR1 +#define CLR_MTU3_TCIV3 CLR2 +#define CLR_TPU0_TCI0V CLR0 +#define CLR_TPU1_TCI1V CLR1 +#define CLR_TPU1_TCI1U CLR2 +#define CLR_TPU5_TCI5V CLR3 +#define CLR_TPU5_TCI5U CLR4 +#define CLR_TPU2_TCI2V CLR0 +#define CLR_TPU2_TCI2U CLR1 +#define CLR_TPU3_TCI3V CLR2 +#define CLR_TPU4_TCI4V CLR3 +#define CLR_TPU4_TCI4U CLR4 +#define CLR_TPU6_TCI6V CLR0 +#define CLR_TPU7_TCI7V CLR1 +#define CLR_TPU7_TCI7U CLR2 +#define CLR_TPU11_TCI11V CLR3 +#define CLR_TPU11_TCI11U CLR4 +#define CLR_TPU8_TCI8V CLR0 +#define CLR_TPU8_TCI8U CLR1 +#define CLR_TPU9_TCI9V CLR2 +#define CLR_TPU10_TCI10V CLR3 +#define CLR_TPU10_TCI10U CLR4 +#define CLR_SCI0_ERI0 CLR0 +#define CLR_SCI1_ERI1 CLR1 +#define CLR_SCI2_ERI2 CLR2 +#define CLR_SCI3_ERI3 CLR3 +#define CLR_SCI4_ERI4 CLR4 +#define CLR_SCI5_ERI5 CLR5 +#define CLR_SCI6_ERI6 CLR6 +#define CLR_SCI7_ERI7 CLR7 +#define CLR_SCI8_ERI8 CLR8 +#define CLR_SCI9_ERI9 CLR9 +#define CLR_SCI10_ERI10 CLR10 +#define CLR_SCI11_ERI11 CLR11 +#define CLR_SCI12_ERI12 CLR12 +#define CLR_RSPI0_SPEI0 CLR13 +#define CLR_RSPI1_SPEI1 CLR14 +#define CLR_RSPI2_SPEI2 CLR15 + +#define CN_TPU6_TGI6A CN0 +#define CN_TPU6_TGI6B CN0 +#define CN_TPU6_TGI6C CN0 +#define CN_TPU6_TGI6D CN0 +#define CN_MTU0_TGIA0 CN0 +#define CN_MTU0_TGIB0 CN0 +#define CN_MTU0_TGIC0 CN0 +#define CN_MTU0_TGID0 CN0 +#define CN_MTU0_TGIE0 CN0 +#define CN_MTU0_TGIF0 CN0 +#define CN_TPU7_TGI7A CN1 +#define CN_TPU7_TGI7B CN1 +#define CN_MTU1_TGIA1 CN1 +#define CN_MTU1_TGIB1 CN1 +#define CN_TPU8_TGI8A CN2 +#define CN_TPU8_TGI8B CN2 +#define CN_MTU2_TGIA2 CN2 +#define CN_MTU2_TGIB2 CN2 +#define CN_TPU9_TGI9A CN3 +#define CN_TPU9_TGI9B CN3 +#define CN_TPU9_TGI9C CN3 +#define CN_TPU9_TGI9D CN3 +#define CN_MTU3_TGIA3 CN3 +#define CN_MTU3_TGIB3 CN3 +#define CN_MTU3_TGIC3 CN3 +#define CN_MTU3_TGID3 CN3 +#define CN_TPU10_TGI10A CN4 +#define CN_TPU10_TGI10B CN4 +#define CN_MTU4_TGIA4 CN4 +#define CN_MTU4_TGIB4 CN4 +#define CN_MTU4_TGIC4 CN4 +#define CN_MTU4_TGID4 CN4 +#define CN_MTU4_TGIV4 CN4 +#define CN_TPU11_TGI11A CN5 +#define CN_TPU11_TGI11B CN5 +#define CN_MTU5_TGIU5 CN5 +#define CN_MTU5_TGIV5 CN5 +#define CN_MTU5_TGIW5 CN5 +#define CN_TPU6_ CN0 +#define CN_MTU0_ CN0 +#define CN_TPU7_ CN1 +#define CN_MTU1_ CN1 +#define CN_TPU8_ CN2 +#define CN_MTU2_ CN2 +#define CN_TPU9_ CN3 +#define CN_MTU3_ CN3 +#define CN_TPU10_ CN4 +#define CN_MTU4_ CN4 +#define CN_TPU11_ CN5 +#define CN_MTU5_ CN5 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP[ GRP ## x ].BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN[ GEN ## x ].BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR[ GCR ## x ].BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) +#define __CN( x ) ICU.SEL.BIT.CN ## x +#define _CN( x ) __CN( x ) +#define CN( x , y ) _CN( _ ## x ## _ ## y ) + +#define AD (*(volatile struct st_ad __evenaccess *)0x89800) +#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300) +#define CAN0 (*(volatile struct st_can __evenaccess *)0x90200) +#define CAN1 (*(volatile struct st_can __evenaccess *)0x91200) +#define CAN2 (*(volatile struct st_can __evenaccess *)0x92200) +#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018) +#define CRC (*(volatile struct st_crc __evenaccess *)0x88280) +#define DA (*(volatile struct st_da __evenaccess *)0x880C0) +#define DMAC (*(volatile struct st_dmac __evenaccess *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 __evenaccess *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 __evenaccess *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 __evenaccess *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 __evenaccess *)0x820C0) +#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400) +#define FLASH (*(volatile struct st_flash __evenaccess *)0x8C296) +#define ICU (*(volatile struct st_icu __evenaccess *)0x87000) +#define IEB (*(volatile struct st_ieb __evenaccess *)0x8A800) +#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030) +#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C100) +#define MTU (*(volatile struct st_mtu __evenaccess *)0x8860A) +#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88690) +#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88690) +#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88692) +#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88694) +#define POE (*(volatile struct st_poe __evenaccess *)0x88900) +#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000) +#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001) +#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002) +#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003) +#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004) +#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005) +#define PORT6 (*(volatile struct st_port6 __evenaccess *)0x8C006) +#define PORT7 (*(volatile struct st_port7 __evenaccess *)0x8C007) +#define PORT8 (*(volatile struct st_port8 __evenaccess *)0x8C008) +#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009) +#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A) +#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B) +#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C) +#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D) +#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E) +#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F) +#define PORTG (*(volatile struct st_portg __evenaccess *)0x8C010) +#define PORTH (*(volatile struct st_porth __evenaccess *)0x8C011) +#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012) +#define PORTK (*(volatile struct st_portk __evenaccess *)0x8C013) +#define PORTL (*(volatile struct st_portl __evenaccess *)0x8C014) +#define PPG0 (*(volatile struct st_ppg0 __evenaccess *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 __evenaccess *)0x881F0) +#define RIIC0 (*(volatile struct st_riic0 __evenaccess *)0x88300) +#define RIIC1 (*(volatile struct st_riic1 __evenaccess *)0x88320) +#define RIIC2 (*(volatile struct st_riic1 __evenaccess *)0x88340) +#define RIIC3 (*(volatile struct st_riic1 __evenaccess *)0x88360) +#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380) +#define RSPI1 (*(volatile struct st_rspi __evenaccess *)0x883A0) +#define RSPI2 (*(volatile struct st_rspi __evenaccess *)0x883C0) +#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400) +#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000) +#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020) +#define SCI2 (*(volatile struct st_sci0 __evenaccess *)0x8A040) +#define SCI3 (*(volatile struct st_sci0 __evenaccess *)0x8A060) +#define SCI4 (*(volatile struct st_sci0 __evenaccess *)0x8A080) +#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0) +#define SCI7 (*(volatile struct st_sci7 __evenaccess *)0x8A0E0) +#define SCI8 (*(volatile struct st_sci0 __evenaccess *)0x8A100) +#define SCI9 (*(volatile struct st_sci0 __evenaccess *)0x8A120) +#define SCI10 (*(volatile struct st_sci0 __evenaccess *)0x8A140) +#define SCI11 (*(volatile struct st_sci0 __evenaccess *)0x8A160) +#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300) +#define SMCI0 (*(volatile struct st_smci0 __evenaccess *)0x8A000) +#define SMCI1 (*(volatile struct st_smci0 __evenaccess *)0x8A020) +#define SMCI2 (*(volatile struct st_smci0 __evenaccess *)0x8A040) +#define SMCI3 (*(volatile struct st_smci0 __evenaccess *)0x8A060) +#define SMCI4 (*(volatile struct st_smci0 __evenaccess *)0x8A080) +#define SMCI5 (*(volatile struct st_smci0 __evenaccess *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci0 __evenaccess *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci7 __evenaccess *)0x8A0E0) +#define SMCI8 (*(volatile struct st_smci0 __evenaccess *)0x8A100) +#define SMCI9 (*(volatile struct st_smci0 __evenaccess *)0x8A120) +#define SMCI10 (*(volatile struct st_smci0 __evenaccess *)0x8A140) +#define SMCI11 (*(volatile struct st_smci0 __evenaccess *)0x8A160) +#define SMCI12 (*(volatile struct st_smci0 __evenaccess *)0x8B300) +#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000) +#define TEMPS (*(volatile struct st_temps __evenaccess *)0x8C500) +#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214) +#define TPU0 (*(volatile struct st_tpu0 __evenaccess *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 __evenaccess *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 __evenaccess *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 __evenaccess *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 __evenaccess *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 __evenaccess *)0x8810C) +#define TPU6 (*(volatile struct st_tpu0 __evenaccess *)0x88178) +#define TPU7 (*(volatile struct st_tpu1 __evenaccess *)0x88178) +#define TPU8 (*(volatile struct st_tpu2 __evenaccess *)0x8817A) +#define TPU9 (*(volatile struct st_tpu3 __evenaccess *)0x8817A) +#define TPU10 (*(volatile struct st_tpu4 __evenaccess *)0x8817C) +#define TPU11 (*(volatile struct st_tpu5 __evenaccess *)0x8817C) +#define TPUA (*(volatile struct st_tpua __evenaccess *)0x88100) +#define TPUB (*(volatile struct st_tpub __evenaccess *)0x88170) +#define USB (*(volatile struct st_usb __evenaccess *)0xA0400) +#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000) +#define WDT (*(volatile struct st_wdt __evenaccess *)0x88020) +#pragma bit_order +#pragma packoption +#endif diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/lowsrc.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/lowsrc.h new file mode 100644 index 000000000..4d2aabfc7 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/lowsrc.h @@ -0,0 +1,13 @@ +/***********************************************************************/ +/* */ +/* FILE :lowsrc.h */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Header file of I/O Stream file */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ +/*Number of I/O Stream*/ +#define IOSTREAM 20 diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/rskrx630def.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/rskrx630def.h new file mode 100644 index 000000000..c09fda5c3 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/rskrx630def.h @@ -0,0 +1,95 @@ + +/****************************************************************************** +* DISCLAIMER +* Please refer to http://www.renesas.com/disclaimer +****************************************************************************** + Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved. +******************************************************************************* +* File Name : rskrx630def.h +* Version : 1.00 +* Description : RSK RX630 board specific settings +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.10.2009 1.00 First Release +******************************************************************************/ + +#ifndef RSKRX630_H +#define RSKRX630_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "cgc.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/* System Clock Settings */ +/* Clock settings defined in CGC_SET.H */ +#if 0 +#define XTAL_FREQUENCY (12000000L) +#define ICLK_MUL (8) +#define PCLK_MUL (4) +#define BCLK_MUL (4) +#define ICLK_FREQUENCY (XTAL_FREQUENCY * ICLK_MUL) +#define PCLK_FREQUENCY (XTAL_FREQUENCY * PCLK_MUL) +#define BCLK_FREQUENCY (XTAL_FREQUENCY * BCLK_MUL) +#endif + +#define CMT0_CLK_SELECT (512) + +/* General Values */ +#define LED_ON (0) +#define LED_OFF (1) +#define SET_BIT_HIGH (1) +#define SET_BIT_LOW (0) +#define SET_BYTE_HIGH (0xFF) +#define SET_BYTE_LOW (0x00) + +/* Define switches to be polled if not available as interrupts */ +#define SW_ACTIVE FALSE +#define SW1 PORT3.PODR.BIT.B2 +#define SW2 PORT4.PODR.BIT.B4 +#define SW3 PORT0.PODR.BIT.B7 +#define SW1_PDR PORT3.PDR.BIT.B2 +#define SW2_PDR PORT4.PDR.BIT.B4 +#define SW3_PDR PORT0.PDR.BIT.B7 + +/* LEDs */ +#define LED0 PORTC.PODR.BIT.B5 +#define LED1 PORT2.PODR.BIT.B4 +#define LED2 PORTC.PODR.BIT.B2 +#define LED3 PORT1.PODR.BIT.B7 +#define LED0_PDR PORTC.PDR.BIT.B5 +#define LED1_PDR PORT2.PDR.BIT.B4 +#define LED2_PDR PORTC.PDR.BIT.B2 +#define LED3_PDR PORT1.PDR.BIT.B7 + +/* 2x8 segment LCD */ +#define LCD_RS PORTJ.PODR.BIT.B3 +#define LCD_EN PORT3.PODR.BIT.B3 +#define LCD_DATA PORTE.PODR.BYTE +#define LCD_RS_PDR PORTJ.PDR.BIT.B3 +#define LCD_EN_PDR PORT3.PDR.BIT.B3 +#define LCD_DATA_PDR PORTE.PDR.BYTE + + + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + + + +/* RSKRX62N_H */ +#endif + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/stacksct.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/stacksct.h new file mode 100644 index 000000000..1d5db830d --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/stacksct.h @@ -0,0 +1,13 @@ +/***********************************************************************/ +/* */ +/* FILE :stacksct.h */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Setting of Stack area */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ +#pragma stacksize su=0x300 +#pragma stacksize si=0x100 diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/typedefine.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/typedefine.h new file mode 100644 index 000000000..d3ad67fec --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/typedefine.h @@ -0,0 +1,41 @@ +/***********************************************************************/ +/* */ +/* FILE :typedefine.h */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Aliases of Integer Type */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX +* +* File Name : typedefine.h +* +* Abstract : Aliases of Integer Type. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/vect.h b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/vect.h new file mode 100644 index 000000000..a6a48946b --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/vect.h @@ -0,0 +1,60 @@ +/***********************************************************************/ +/* */ +/* FILE :vect.h */ +/* DATE :Wed, Aug 11, 2010 */ +/* DESCRIPTION :Definition of Vector */ +/* CPU TYPE :Other */ +/* */ +/* This file is generated by Renesas Project Generator (Ver.4.50). */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ + + + +/********************************************************************* +* +* Device : RX/RX600 +* +* File Name : vect.h +* +* Abstract : Definition of Vector. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2009 Renesas Technology Corp. +* And Renesas Solutions Corp.,All Rights Reserved. +* +*********************************************************************/ + +// Exception(Supervisor Instruction) +#pragma interrupt (Excep_SuperVisorInst) +void Excep_SuperVisorInst(void); + +// Exception(Undefined Instruction) +#pragma interrupt (Excep_UndefinedInst) +void Excep_UndefinedInst(void); + +// Exception(Floating Point) +#pragma interrupt (Excep_FloatingPoint) +void Excep_FloatingPoint(void); + +// NMI +#pragma interrupt (NonMaskableInterrupt) +void NonMaskableInterrupt(void); + +// Dummy +#pragma interrupt (Dummy) +void Dummy(void); + +// BRK +#pragma interrupt (Excep_BRK(vect=0)) +void Excep_BRK(void); + +//;<> +//;Power On Reset PC +extern void PowerON_Reset_PC(void); +//;<> + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-blinky.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-blinky.c new file mode 100644 index 000000000..15d26d343 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-blinky.c @@ -0,0 +1,222 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * This is a very simple demo that creates two tasks and one queue. One task + * (the queue receive task) blocks on the queue to wait for data to arrive, + * toggling an LED each time '100' is received. The other task (the queue send + * task) repeatedly blocks for a fixed period before sending '100' to the queue + * (causing the first task to toggle the LED). + * + * For a much more complete and complex example select either the Debug or + * Debug_with_optimisation build configurations within the HEW IDE. +*/ + +/* Hardware specific includes. */ +#include "iodefine.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Priorities at which the tasks are created. */ +#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The rate at which data is sent to the queue, specified in milliseconds. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 500 / portTICK_RATE_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added so the send task should always find the +queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* + * The tasks as defined at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/* The queue used by both tasks. */ +static xQueueHandle xQueue = NULL; + +/* This variable is not used by this simple Blinky example. It is defined +purely to allow the project to link as it is used by the full project. */ +volatile unsigned long ulHighFrequencyTickCount = 0UL; +/*-----------------------------------------------------------*/ + +void main(void) +{ +extern void HardwareSetup( void ); + + /* Renesas provided CPU configuration routine. The clocks are configured in + here. */ + HardwareSetup(); + + /* Turn all LEDs off. */ + vParTestInitialise(); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described at the top of this file. */ + xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL ); + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks running. */ + vTaskStartScheduler(); + } + + /* If all is well we will never reach here as the scheduler will now be + running. If we do reach here then it is likely that there was insufficient + heap available for the idle task to be created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +portTickType xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + The block state is specified in ticks, the constant used converts ticks + to ms. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to flash its LED. 0 + is used so the send does not block - it shouldn't need to as the queue + should always be empty here. */ + xQueueSend( xQueue, &ulValueToSend, 0 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; + + for( ;; ) + { + /* Wait until something arives in the queue - this will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have arrived, but is it the expected + value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + vParTestToggleLED( 0 ); + } + } +} +/*-----------------------------------------------------------*/ + +void vApplicationSetupTimerInterrupt( void ) +{ + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationMallocFailedHook( void ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationIdleHook( void ) +{ + /* Just to prevent the variable getting optimised away. */ + ( void ) ulHighFrequencyTickCount; +} +/*-----------------------------------------------------------*/ diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-full.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-full.c new file mode 100644 index 000000000..cf4231ba5 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-full.c @@ -0,0 +1,654 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* **************************************************************************** + * This project includes a lot of tasks and tests and is therefore complex. + * If you would prefer a much simpler project to get started with then select + * the 'Blinky' build configuration within the HEW IDE. + * **************************************************************************** + * + * Creates all the demo application tasks, then starts the scheduler. The web + * documentation provides more details of the standard demo application tasks, + * which provide no particular functionality but do provide a good example of + * how to use the FreeRTOS API. The tasks defined in flop.c are included in the + * set of standard demo tasks to ensure the floating point unit gets some + * exercise. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill the registers with known values, then check + * that each register still contains its expected value. Each task uses + * different values. The tasks run with very low priority so get preempted + * very frequently. A check variable is incremented on each iteration of the + * test loop. A register containing an unexpected value is indicative of an + * error in the context switching mechanism and will result in a branch to a + * null loop - which in turn will prevent the check variable from incrementing + * any further and allow the check task (described below) to determine that an + * error has occurred. The nature of the reg test tasks necessitates that they + * are written in assembly code. + * + * "Check" task - This only executes every five seconds but has a high priority + * to ensure it gets processor time. Its main function is to check that all the + * standard demo tasks are still operational. While no errors have been + * discovered the check task will toggle LED 5 every 5 seconds - the toggle + * rate increasing to 200ms being a visual indication that at least one task has + * reported unexpected behaviour. + * + * "High frequency timer test" - A high frequency periodic interrupt is + * generated using a timer - the interrupt is assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY so should not be effected by anything + * the kernel is doing. The frequency and priority of the interrupt, in + * combination with other standard tests executed in this demo, should result + * in interrupts nesting at least 3 and probably 4 deep. This test is only + * included in build configurations that have the optimiser switched on. In + * optimised builds the count of high frequency ticks is used as the time base + * for the run time stats. + * + * *NOTE 1* If LED3 is toggling every 5 seconds then all the demo application + * tasks are executing as expected and no errors have been reported in any + * tasks. The toggle rate increasing to 200ms indicates that at least one task + * has reported unexpected behaviour. + * + * *NOTE 2* vApplicationSetupTimerInterrupt() is called by the kernel to let + * the application set up a timer to generate the tick interrupt. In this + * example a compare match timer is used for this purpose. + * + * *NOTE 3* The CPU must be in Supervisor mode when the scheduler is started. + * The PowerON_Reset_PC() supplied in resetprg.c with this demo has + * Change_PSW_PM_to_UserMode() commented out to ensure this is the case. + * + * *NOTE 4* The IntQueue common demo tasks test interrupt nesting and make use + * of all the 8bit timers (as two cascaded 16bit units). +*/ + +/* Hardware specific includes. */ +#include "iodefine.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard demo includes. */ +#include "partest.h" +#include "flash.h" +#include "IntQueue.h" +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "semtest.h" +#include "PollQ.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" +#include "flop.h" + +/* Values that are passed into the reg test tasks using the task parameter. The +tasks check that the values are passed in correctly. */ +#define mainREG_TEST_1_PARAMETER ( 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( 0x12345678UL ) + +/* Priorities at which the tasks are created. */ +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainuIP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The WEB server uses string handling functions, which in turn use a bit more +stack than most of the other tasks. */ +#define mainuIP_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 ) + +/* The LED toggled by the check task. */ +#define mainCHECK_LED ( 3 ) + +/* The rate at which mainCHECK_LED will toggle when all the tasks are running +without error. Controlled by the check task as described at the top of this +file. */ +#define mainNO_ERROR_CYCLE_TIME ( 5000 / portTICK_RATE_MS ) + +/* The rate at which mainCHECK_LED will toggle when an error has been reported +by at least one task. Controlled by the check task as described at the top of +this file. */ +#define mainERROR_CYCLE_TIME ( 200 / portTICK_RATE_MS ) + +/* + * vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will execute if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue or + * semaphore is created. It is also called by various parts of the demo + * application. + */ +void vApplicationMallocFailedHook( void ); + +/* + * vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set to 1 + * in FreeRTOSConfig.h. It is a hook function that is called on each iteration + * of the idle task. It is essential that code added to this hook function + * never attempts to block in any way (for example, call xQueueReceive() with + * a block time specified). If the application makes use of the vTaskDelete() + * API function (as this demo application does) then it is also important that + * vApplicationIdleHook() is permitted to return to its calling function because + * it is the responsibility of the idle task to clean up memory allocated by the + * kernel to any task that has since been deleted. + */ +void vApplicationIdleHook( void ); + +/* + * vApplicationStackOverflowHook() will only be called if + * configCHECK_FOR_STACK_OVERFLOW is set to a non-zero value. The handle and + * name of the offending task should be passed in the function parameters, but + * it is possible that the stack overflow will have corrupted these - in which + * case pxCurrentTCB can be inspected to find the same information. + */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ); + +/* + * The reg test tasks as described at the top of this file. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); + +/* + * The actual implementation of the reg test functionality, which, because of + * the direct register access, have to be in assembly. + */ +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * The check task as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Contains the implementation of the WEB server. + */ +extern void vuIP_Task( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Variables that are incremented on each iteration of the reg test tasks - +provided the tasks have not reported any errors. The check task inspects these +variables to ensure they are still incrementing as expected. If a variable +stops incrementing then it is likely that its associate task has stalled. */ +unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL; + +/* The status message that is displayed at the bottom of the "task stats" web +page, which is served by the uIP task. This will report any errors picked up +by the reg test task. */ +const char *pcStatusMessage = "All tasks executing without error."; + +/*-----------------------------------------------------------*/ + +void main(void) +{ +extern void HardwareSetup( void ); + + /* Renesas provided CPU configuration routine. The clocks are configured in + here. */ + HardwareSetup(); + + /* Turn all LEDs off. */ + vParTestInitialise(); + + /* Start the reg test tasks which test the context switching mechanism. */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Start the check task as described at the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE * 3, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Create the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartInterruptQueueTasks(); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the tasks running. */ + vTaskStartScheduler(); + + /* If all is well we will never reach here as the scheduler will now be + running. If we do reach here then it is likely that there was insufficient + heap available for the idle task to be created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL; +portTickType xNextWakeTime, xCycleFrequency = mainNO_ERROR_CYCLE_TIME; +extern void vSetupHighFrequencyTimer( void ); + + /* If this is being executed then the kernel has been started. Start the high + frequency timer test as described at the top of this file. This is only + included in the optimised build configuration - otherwise it takes up too much + CPU time and can disrupt other tests. */ + #ifdef INCLUDE_HIGH_FREQUENCY_TIMER_TEST + vSetupHighFrequencyTimer(); + #endif + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, xCycleFrequency ); + + /* Check the standard demo tasks are running without error. */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + /* Increase the rate at which this task cycles, which will increase the + rate at which mainCHECK_LED flashes to give visual feedback that an error + has occurred. */ + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: GenQueue"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: QueuePeek"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: BlockQueue"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: BlockTime"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: SemTest"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: PollQueue"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: Death"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: IntMath"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: RecMutex"; + } + else if( xAreIntQueueTasksStillRunning() != pdPASS ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: IntQueue"; + } + else if( xAreMathsTaskStillRunning() != pdPASS ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: Flop"; + } + + /* Check the reg test tasks are still cycling. They will stop incrementing + their loop counters if they encounter an error. */ + if( ulRegTest1CycleCount == ulLastRegTest1CycleCount ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: RegTest1"; + } + + if( ulRegTest2CycleCount == ulLastRegTest2CycleCount ) + { + xCycleFrequency = mainERROR_CYCLE_TIME; + pcStatusMessage = "Error: RegTest2"; + } + + ulLastRegTest1CycleCount = ulRegTest1CycleCount; + ulLastRegTest2CycleCount = ulRegTest2CycleCount; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every 5 seconds then everything is ok. A faster toggle + indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + } +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationMallocFailedHook( void ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ) +{ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* This function is explained by the comments above its prototype at the top +of this file. */ +void vApplicationIdleHook( void ) +{ +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest1Implementation +static void prvRegTest1Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1CycleCount, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest2Implementation +static void prvRegTest2Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2CycleCount, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error +} +/*-----------------------------------------------------------*/ + +char *pcGetTaskStatusMessage( void ) +{ + /* Not bothered about a critical section here although technically because of + the task priorities the pointer could change it will be atomic if not near + atomic and its not critical. */ + return ( char * ) pcStatusMessage; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/uIP_Task.c b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/uIP_Task.c new file mode 100644 index 000000000..906f0e183 --- /dev/null +++ b/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/uIP_Task.c @@ -0,0 +1,345 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" + +/* uip includes. */ +#include "net/uip.h" +#include "net/uip_arp.h" +#include "apps/httpd/httpd.h" +#include "sys/timer.h" +#include "net/clock-arch.h" +#include "r_ether.h" + +/* Demo includes. */ +#include "ParTest.h" + +/*-----------------------------------------------------------*/ + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT ( 100 / portTICK_RATE_MS ) + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/* The ARP timer and the periodic timer share a callback function, so the +respective timer IDs are used to determine which timer actually expired. These +constants are assigned to the timer IDs. */ +#define uipARP_TIMER 0 +#define uipPERIODIC_TIMER 1 + +/* A block time of zero ticks simply means, "don't block". */ +#define uipDONT_BLOCK 0UL + +/*-----------------------------------------------------------*/ + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Perform any uIP initialisation necessary. + */ +static void prvInitialise_uIP( void ); + +/* + * The callback function that is assigned to both the periodic timer and the + * ARP timer. + */ +static void prvUIPTimerCallback( xTimerHandle xTimer ); + +/* + * Port functions required by the uIP stack. + */ +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used to send TCP/IP events to the uIP stack. */ +xQueueHandle xEMACEventQueue = NULL; + +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} +/*-----------------------------------------------------------*/ + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +unsigned long ulNewEvent = 0UL; +unsigned long ulUIP_Events = 0UL; + + ( void ) pvParameters; + + /* Initialise the uIP stack. */ + prvInitialise_uIP(); + + /* Initialise the MAC. */ + vInitEmac(); + + while( lEMACWaitForLink() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + + for( ;; ) + { + if( ( ulUIP_Events & uipETHERNET_RX_EVENT ) != 0UL ) + { + /* Is there received data ready to be processed? */ + uip_len = ( unsigned short ) ulEMACRead(); + + if( ( uip_len > 0 ) && ( uip_buf != NULL ) ) + { + /* Standard uIP loop taken from the uIP manual. */ + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + vEMACWrite(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + vEMACWrite(); + } + } + } + else + { + ulUIP_Events &= ~uipETHERNET_RX_EVENT; + } + } + + if( ( ulUIP_Events & uipPERIODIC_TIMER_EVENT ) != 0UL ) + { + ulUIP_Events &= ~uipPERIODIC_TIMER_EVENT; + + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + vEMACWrite(); + } + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( ( ulUIP_Events & uipARP_TIMER_EVENT ) != 0 ) + { + ulUIP_Events &= ~uipARP_TIMER_EVENT; + uip_arp_timer(); + } + + if( ulUIP_Events == pdFALSE ) + { + xQueueReceive( xEMACEventQueue, &ulNewEvent, portMAX_DELAY ); + ulUIP_Events |= ulNewEvent; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvInitialise_uIP( void ) +{ +xTimerHandle xARPTimer, xPeriodicTimer; +uip_ipaddr_t xIPAddr; +const unsigned long ul_uIPEventQueueLength = 10UL; + + /* Initialise the uIP stack. */ + uip_init(); + uip_ipaddr( &xIPAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 ); + uip_sethostaddr( &xIPAddr ); + uip_ipaddr( &xIPAddr, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 ); + uip_setnetmask( &xIPAddr ); + prvSetMACAddress(); + httpd_init(); + + /* Create the queue used to sent TCP/IP events to the uIP stack. */ + xEMACEventQueue = xQueueCreate( ul_uIPEventQueueLength, sizeof( unsigned long ) ); + + /* Create and start the uIP timers. */ + xARPTimer = xTimerCreate( ( const signed char * const ) "ARPTimer", /* Just a name that is helpful for debugging, not used by the kernel. */ + ( 10000UL / portTICK_RATE_MS ), /* Timer period. */ + pdTRUE, /* Autor-reload. */ + ( void * ) uipARP_TIMER, + prvUIPTimerCallback + ); + + xPeriodicTimer = xTimerCreate( ( const signed char * const ) "PeriodicTimer", + ( 500 / portTICK_RATE_MS ), + pdTRUE, /* Autor-reload. */ + ( void * ) uipPERIODIC_TIMER, + prvUIPTimerCallback + ); + + configASSERT( xARPTimer ); + configASSERT( xPeriodicTimer ); + + xTimerStart( xARPTimer, portMAX_DELAY ); + xTimerStart( xPeriodicTimer, portMAX_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void prvUIPTimerCallback( xTimerHandle xTimer ) +{ +static const unsigned long ulARPTimerExpired = uipARP_TIMER_EVENT; +static const unsigned long ulPeriodicTimerExpired = uipPERIODIC_TIMER_EVENT; + + /* This is a time callback, so calls to xQueueSend() must not attempt to + block. */ + switch( ( int ) pvTimerGetTimerID( xTimer ) ) + { + case uipARP_TIMER : xQueueSend( xEMACEventQueue, &ulARPTimerExpired, uipDONT_BLOCK ); + break; + + case uipPERIODIC_TIMER : xQueueSend( xEMACEventQueue, &ulPeriodicTimerExpired, uipDONT_BLOCK ); + break; + + default : /* Should not get here. */ + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +struct uip_eth_addr xAddr; + + /* Configure the MAC address in the uIP stack. */ + xAddr.addr[ 0 ] = configMAC_ADDR0; + xAddr.addr[ 1 ] = configMAC_ADDR1; + xAddr.addr[ 2 ] = configMAC_ADDR2; + xAddr.addr[ 3 ] = configMAC_ADDR3; + xAddr.addr[ 4 ] = configMAC_ADDR4; + xAddr.addr[ 5 ] = configMAC_ADDR5; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( char *pcInputString ) +{ +char *c; + + /* Only interested in processing form input if this is the IO page. */ + c = strstr( pcInputString, "io.shtml" ); + + if( c ) + { + /* Is there a command in the string? */ + c = strstr( pcInputString, "?" ); + if( c ) + { + /* Turn the LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + /* Turn the LEDs on. */ + vParTestSetLED( 7, 1 ); + vParTestSetLED( 8, 1 ); + vParTestSetLED( 9, 1 ); + vParTestSetLED( 10, 1 ); + } + else + { + /* Turn the LEDs off. */ + vParTestSetLED( 7, 0 ); + vParTestSetLED( 8, 0 ); + vParTestSetLED( 9, 0 ); + vParTestSetLED( 10, 0 ); + } + } + else + { + /* Commands to turn LEDs off are not always explicit. */ + vParTestSetLED( 7, 0 ); + vParTestSetLED( 8, 0 ); + vParTestSetLED( 9, 0 ); + vParTestSetLED( 10, 0 ); + } + } +} +