From: Haikun.Wang@freescale.com <Haikun.Wang@freescale.com>
Date: Fri, 26 Jun 2015 11:58:24 +0000 (+0800)
Subject: armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD
X-Git-Tag: v2015.10-rc1~183^2~5
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5989df7e2cfb5ac0d8c9a509aad2b84f9141cc13;p=u-boot

armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD

DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---

diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index 1f8cf8a2e5..5e7997c869 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -23,12 +23,14 @@
 #include "ls2085ardb_qixis.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
+#define PIN_MUX_SEL_DSPI	0x0a
 
 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
 DECLARE_GLOBAL_DATA_PTR;
 
 enum {
 	MUX_TYPE_SDHC,
+	MUX_TYPE_DSPI,
 };
 
 unsigned long long get_qixis_addr(void)
@@ -120,26 +122,6 @@ int select_i2c_ch_pca9547(u8 ch)
 	return 0;
 }
 
-int board_init(void)
-{
-	init_final_memctl_regs();
-
-#ifdef CONFIG_ENV_IS_NOWHERE
-	gd->env_addr = (ulong)&default_environment[0];
-#endif
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-
-	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	fsl_lsch3_early_init_f();
-	return 0;
-}
-
 int config_board_mux(int ctrl_type)
 {
 	u8 reg5;
@@ -150,6 +132,9 @@ int config_board_mux(int ctrl_type)
 	case MUX_TYPE_SDHC:
 		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
 		break;
+	case MUX_TYPE_DSPI:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+		break;
 	default:
 		printf("Wrong mux interface type\n");
 		return -1;
@@ -160,6 +145,40 @@ int config_board_mux(int ctrl_type)
 	return 0;
 }
 
+int board_init(void)
+{
+	char *env_hwconfig;
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+
+	init_final_memctl_regs();
+
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+	env_hwconfig = getenv("hwconfig");
+
+	if (hwconfig_f("dspi", env_hwconfig) &&
+	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+		config_board_mux(MUX_TYPE_DSPI);
+	else
+		config_board_mux(MUX_TYPE_SDHC);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
 int misc_init_r(void)
 {
 	if (hwconfig("sdhc"))