From:  <m8@hekate.semihalf.com>
Date: Thu, 11 Aug 2005 13:56:59 +0000 (+0200)
Subject: O2DNT FRAM write delay disabled.
X-Git-Tag: LABEL_2006_03_12_0025~214^2~6
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5a27f84855f3db8a6317389c034f8f507444185f;p=u-boot

O2DNT FRAM write delay disabled.
---

diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 6d388f3f64..12a732d9f1 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -150,12 +150,23 @@
 #define CFG_I2C_SLAVE		0x7F
 
 /*
- * EEPROM configuration
+ * EEPROM configuration:
+ *
+ * O2DNT board is equiped with Ramtron FRAM device FM24CL16
+ * 16 Kib Ferroelectric Nonvolatile serial RAM memory
+ * organized as 2048 x 8 bits and addressable as eight I2C devices
+ * 0x50 ... 0x57 each 256 bytes in size
+ *
  */
 #define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
 #define CFG_I2C_EEPROM_ADDR_LEN		1
 #define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+/*
+ * There is no write delay with FRAM, write operations are performed at bus
+ * speed. Thus, no status polling or write delay is needed.
+ */
+/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70*/
+
 
 /*
  * Flash configuration