From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 10 Dec 2015 14:32:11 +0000 (+0100)
Subject: net: emaclite: Use indirect register access for TX reset
X-Git-Tag: v2016.03-rc1~46^2~67
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5a4baa33e4d0beb9708719160bfc3f91a8f9f3bf;p=u-boot

net: emaclite: Use indirect register access for TX reset

Move to use indirect register access when timeout expires for resetting
TX buffers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 724b61e0b7..72b6e0ac42 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -408,6 +408,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len)
 	u32 reg;
 	u32 baseaddress;
 	struct xemaclite *emaclite = dev->priv;
+	struct emaclite_regs *regs = emaclite->regs;
 
 	u32 maxtry = 1000;
 
@@ -422,10 +423,9 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len)
 	if (!maxtry) {
 		printf("Error: Timeout waiting for ethernet TX buffer\n");
 		/* Restart PING TX */
-		out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
+		out_be32(&regs->tx_ping_tsr, 0);
 		if (emaclite->txpp) {
-			out_be32 (dev->iobase + XEL_TSR_OFFSET +
-				XEL_BUFFER_OFFSET, 0);
+			out_be32(&regs->tx_pong_tsr, 0);
 		}
 		return -1;
 	}