From: Grant Erickson <gerickson@nuovations.com>
Date: Wed, 9 Jul 2008 18:55:46 +0000 (-0700)
Subject: PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)
X-Git-Tag: v2008.10-rc1~211
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5b457d00730d4aa0c6450d21a9104723e606fb98;p=u-boot

PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)

While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM
controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in
the 405EX(r), SDRAM_MCSTAT has a different DCR value.

Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF
which causes SDRAM initialization to periodically fail since it can
prematurely indicate SDRAM ready status.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index cdccd8fe6f..59f1c30839 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -354,7 +354,11 @@
 /*
  * Memory controller registers
  */
+#ifndef CONFIG_405EX
 #define SDRAM_MCSTAT	0x14	/* memory controller status                  */
+#else
+#define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
+#endif
 #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
 #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
 #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */