From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Thu, 23 Oct 2008 12:55:10 +0000 (+0000)
Subject: hontor <hontor@126.com> - fix simulation step errors
X-Git-Tag: v0.1.0~218
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5df88ed3a1afb0334318a15d46474016b6e6d837;p=openocd

hontor <hontor@126.com> - fix simulation step errors

git-svn-id: svn://svn.berlios.de/openocd/trunk@1097 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 07e18016..2873a5a6 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -533,9 +533,12 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 			 load_address = Rn;
 		}
 		
-		if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
+		if((!dry_run_pc) || (instruction.info.load_store.Rd == 15))
 		{
-			return retval;
+			if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
+			{
+				return retval;
+			}
 		}
 		
 		if (dry_run_pc)
@@ -599,7 +602,10 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 		{
 			if (instruction.info.load_store_multiple.register_list & (1 << i))
 			{
-				target_read_u32(target, Rn, &load_values[i]);
+				if((!dry_run_pc) || (i == 15))
+				{
+					target_read_u32(target, Rn, &load_values[i]);
+				}
 				Rn += 4;
 			}
 		}